target/ppc/translate/vmx-impl.c.inc

   1 /*
   2  * translate/vmx-impl.c
   3  *
   4  * Altivec/VMX translation
   5  */
   6
   7 /***                      Altivec vector extension                         ***/
   8 /* Altivec registers moves */
   9
  10 static inline TCGv_ptr gen_avr_ptr(int reg)
  11 {
  12     TCGv_ptr r = tcg_temp_new_ptr();
  13     tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
  14     return r;
  15 }
  16
  17 #define GEN_VR_LDX(name, opc2, opc3)                                          \
  18 static void glue(gen_, name)(DisasContext *ctx)                               \
  19 {                                                                             \
  20     TCGv EA;                                                                  \
  21     TCGv_i64 avr;                                                             \
  22     if (unlikely(!ctx->altivec_enabled)) {                                    \
  23         gen_exception(ctx, POWERPC_EXCP_VPU);                                 \
  24         return;                                                               \
  25     }                                                                         \
  26     gen_set_access_type(ctx, ACCESS_INT);                                     \
  27     avr = tcg_temp_new_i64();                                                 \
  28     EA = tcg_temp_new();                                                      \
  29     gen_addr_reg_index(ctx, EA);                                              \
  30     tcg_gen_andi_tl(EA, EA, ~0xf);                                            \
  31     /*                                                                        \
  32      * We only need to swap high and low halves. gen_qemu_ld64_i64            \
  33      * does necessary 64-bit byteswap already.                                \
  34      */                                                                       \
  35     if (ctx->le_mode) {                                                       \
  36         gen_qemu_ld64_i64(ctx, avr, EA);                                      \
  37         set_avr64(rD(ctx->opcode), avr, false);                               \
  38         tcg_gen_addi_tl(EA, EA, 8);                                           \
  39         gen_qemu_ld64_i64(ctx, avr, EA);                                      \
  40         set_avr64(rD(ctx->opcode), avr, true);                                \
  41     } else {                                                                  \
  42         gen_qemu_ld64_i64(ctx, avr, EA);                                      \
  43         set_avr64(rD(ctx->opcode), avr, true);                                \
  44         tcg_gen_addi_tl(EA, EA, 8);                                           \
  45         gen_qemu_ld64_i64(ctx, avr, EA);                                      \
  46         set_avr64(rD(ctx->opcode), avr, false);                               \
  47     }                                                                         \
  48     tcg_temp_free(EA);                                                        \
  49     tcg_temp_free_i64(avr);                                                   \
  50 }
  51
  52 #define GEN_VR_STX(name, opc2, opc3)                                          \
  53 static void gen_st##name(DisasContext *ctx)                                   \
  54 {                                                                             \
  55     TCGv EA;                                                                  \
  56     TCGv_i64 avr;                                                             \
  57     if (unlikely(!ctx->altivec_enabled)) {                                    \
  58         gen_exception(ctx, POWERPC_EXCP_VPU);                                 \
  59         return;                                                               \
  60     }                                                                         \
  61     gen_set_access_type(ctx, ACCESS_INT);                                     \
  62     avr = tcg_temp_new_i64();                                                 \
  63     EA = tcg_temp_new();                                                      \
  64     gen_addr_reg_index(ctx, EA);                                              \
  65     tcg_gen_andi_tl(EA, EA, ~0xf);                                            \
  66     /*                                                                        \
  67      * We only need to swap high and low halves. gen_qemu_st64_i64            \
  68      * does necessary 64-bit byteswap already.                                \
  69      */                                                                       \
  70     if (ctx->le_mode) {                                                       \
  71         get_avr64(avr, rD(ctx->opcode), false);                               \
  72         gen_qemu_st64_i64(ctx, avr, EA);                                      \
  73         tcg_gen_addi_tl(EA, EA, 8);                                           \
  74         get_avr64(avr, rD(ctx->opcode), true);                                \
  75         gen_qemu_st64_i64(ctx, avr, EA);                                      \
  76     } else {                                                                  \
  77         get_avr64(avr, rD(ctx->opcode), true);                                \
  78         gen_qemu_st64_i64(ctx, avr, EA);                                      \
  79         tcg_gen_addi_tl(EA, EA, 8);                                           \
  80         get_avr64(avr, rD(ctx->opcode), false);                               \
  81         gen_qemu_st64_i64(ctx, avr, EA);                                      \
  82     }                                                                         \
  83     tcg_temp_free(EA);                                                        \
  84     tcg_temp_free_i64(avr);                                                   \
  85 }
  86
  87 #define GEN_VR_LVE(name, opc2, opc3, size)                              \
  88 static void gen_lve##name(DisasContext *ctx)                            \
  89     {                                                                   \
  90         TCGv EA;                                                        \
  91         TCGv_ptr rs;                                                    \
  92         if (unlikely(!ctx->altivec_enabled)) {                          \
  93             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
  94             return;                                                     \
  95         }                                                               \
  96         gen_set_access_type(ctx, ACCESS_INT);                           \
  97         EA = tcg_temp_new();                                            \
  98         gen_addr_reg_index(ctx, EA);                                    \
  99         if (size > 1) {                                                 \
 100             tcg_gen_andi_tl(EA, EA, ~(size - 1));                       \
 101         }                                                               \
 102         rs = gen_avr_ptr(rS(ctx->opcode));                              \
 103         gen_helper_lve##name(cpu_env, rs, EA);                          \
 104         tcg_temp_free(EA);                                              \
 105         tcg_temp_free_ptr(rs);                                          \
 106     }
 107
 108 #define GEN_VR_STVE(name, opc2, opc3, size)                             \
 109 static void gen_stve##name(DisasContext *ctx)                           \
 110     {                                                                   \
 111         TCGv EA;                                                        \
 112         TCGv_ptr rs;                                                    \
 113         if (unlikely(!ctx->altivec_enabled)) {                          \
 114             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
 115             return;                                                     \
 116         }                                                               \
 117         gen_set_access_type(ctx, ACCESS_INT);                           \
 118         EA = tcg_temp_new();                                            \
 119         gen_addr_reg_index(ctx, EA);                                    \
 120         if (size > 1) {                                                 \
 121             tcg_gen_andi_tl(EA, EA, ~(size - 1));                       \
 122         }                                                               \
 123         rs = gen_avr_ptr(rS(ctx->opcode));                              \
 124         gen_helper_stve##name(cpu_env, rs, EA);                         \
 125         tcg_temp_free(EA);                                              \
 126         tcg_temp_free_ptr(rs);                                          \
 127     }
 128
 129 GEN_VR_LDX(lvx, 0x07, 0x03);
 130 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
 131 GEN_VR_LDX(lvxl, 0x07, 0x0B);
 132
 133 GEN_VR_LVE(bx, 0x07, 0x00, 1);
 134 GEN_VR_LVE(hx, 0x07, 0x01, 2);
 135 GEN_VR_LVE(wx, 0x07, 0x02, 4);
 136
 137 GEN_VR_STX(svx, 0x07, 0x07);
 138 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
 139 GEN_VR_STX(svxl, 0x07, 0x0F);
 140
 141 GEN_VR_STVE(bx, 0x07, 0x04, 1);
 142 GEN_VR_STVE(hx, 0x07, 0x05, 2);
 143 GEN_VR_STVE(wx, 0x07, 0x06, 4);
 144
 145 static void gen_mfvscr(DisasContext *ctx)
 146 {
 147     TCGv_i32 t;
 148     TCGv_i64 avr;
 149     if (unlikely(!ctx->altivec_enabled)) {
 150         gen_exception(ctx, POWERPC_EXCP_VPU);
 151         return;
 152     }
 153     avr = tcg_temp_new_i64();
 154     tcg_gen_movi_i64(avr, 0);
 155     set_avr64(rD(ctx->opcode), avr, true);
 156     t = tcg_temp_new_i32();
 157     gen_helper_mfvscr(t, cpu_env);
 158     tcg_gen_extu_i32_i64(avr, t);
 159     set_avr64(rD(ctx->opcode), avr, false);
 160     tcg_temp_free_i32(t);
 161     tcg_temp_free_i64(avr);
 162 }
 163
 164 static void gen_mtvscr(DisasContext *ctx)
 165 {
 166     TCGv_i32 val;
 167     int bofs;
 168
 169     if (unlikely(!ctx->altivec_enabled)) {
 170         gen_exception(ctx, POWERPC_EXCP_VPU);
 171         return;
 172     }
 173
 174     val = tcg_temp_new_i32();
 175     bofs = avr_full_offset(rB(ctx->opcode));
 176 #ifdef HOST_WORDS_BIGENDIAN
 177     bofs += 3 * 4;
 178 #endif
 179
 180     tcg_gen_ld_i32(val, cpu_env, bofs);
 181     gen_helper_mtvscr(cpu_env, val);
 182     tcg_temp_free_i32(val);
 183 }
 184
 185 #define GEN_VX_VMUL10(name, add_cin, ret_carry)                         \
 186 static void glue(gen_, name)(DisasContext *ctx)                         \
 187 {                                                                       \
 188     TCGv_i64 t0;                                                        \
 189     TCGv_i64 t1;                                                        \
 190     TCGv_i64 t2;                                                        \
 191     TCGv_i64 avr;                                                       \
 192     TCGv_i64 ten, z;                                                    \
 193                                                                         \
 194     if (unlikely(!ctx->altivec_enabled)) {                              \
 195         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 196         return;                                                         \
 197     }                                                                   \
 198                                                                         \
 199     t0 = tcg_temp_new_i64();                                            \
 200     t1 = tcg_temp_new_i64();                                            \
 201     t2 = tcg_temp_new_i64();                                            \
 202     avr = tcg_temp_new_i64();                                           \
 203     ten = tcg_const_i64(10);                                            \
 204     z = tcg_const_i64(0);                                               \
 205                                                                         \
 206     if (add_cin) {                                                      \
 207         get_avr64(avr, rA(ctx->opcode), false);                         \
 208         tcg_gen_mulu2_i64(t0, t1, avr, ten);                            \
 209         get_avr64(avr, rB(ctx->opcode), false);                         \
 210         tcg_gen_andi_i64(t2, avr, 0xF);                                 \
 211         tcg_gen_add2_i64(avr, t2, t0, t1, t2, z);                       \
 212         set_avr64(rD(ctx->opcode), avr, false);                         \
 213     } else {                                                            \
 214         get_avr64(avr, rA(ctx->opcode), false);                         \
 215         tcg_gen_mulu2_i64(avr, t2, avr, ten);                           \
 216         set_avr64(rD(ctx->opcode), avr, false);                         \
 217     }                                                                   \
 218                                                                         \
 219     if (ret_carry) {                                                    \
 220         get_avr64(avr, rA(ctx->opcode), true);                          \
 221         tcg_gen_mulu2_i64(t0, t1, avr, ten);                            \
 222         tcg_gen_add2_i64(t0, avr, t0, t1, t2, z);                       \
 223         set_avr64(rD(ctx->opcode), avr, false);                         \
 224         set_avr64(rD(ctx->opcode), z, true);                            \
 225     } else {                                                            \
 226         get_avr64(avr, rA(ctx->opcode), true);                          \
 227         tcg_gen_mul_i64(t0, avr, ten);                                  \
 228         tcg_gen_add_i64(avr, t0, t2);                                   \
 229         set_avr64(rD(ctx->opcode), avr, true);                          \
 230     }                                                                   \
 231                                                                         \
 232     tcg_temp_free_i64(t0);                                              \
 233     tcg_temp_free_i64(t1);                                              \
 234     tcg_temp_free_i64(t2);                                              \
 235     tcg_temp_free_i64(avr);                                             \
 236     tcg_temp_free_i64(ten);                                             \
 237     tcg_temp_free_i64(z);                                               \
 238 }                                                                       \
 239
 240 GEN_VX_VMUL10(vmul10uq, 0, 0);
 241 GEN_VX_VMUL10(vmul10euq, 1, 0);
 242 GEN_VX_VMUL10(vmul10cuq, 0, 1);
 243 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
 244
 245 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3)                    \
 246 static void glue(gen_, name)(DisasContext *ctx)                         \
 247 {                                                                       \
 248     if (unlikely(!ctx->altivec_enabled)) {                              \
 249         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 250         return;                                                         \
 251     }                                                                   \
 252                                                                         \
 253     tcg_op(vece,                                                        \
 254            avr_full_offset(rD(ctx->opcode)),                            \
 255            avr_full_offset(rA(ctx->opcode)),                            \
 256            avr_full_offset(rB(ctx->opcode)),                            \
 257            16, 16);                                                     \
 258 }
 259
 260 /* Logical operations */
 261 GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
 262 GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
 263 GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
 264 GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
 265 GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
 266 GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
 267 GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
 268 GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
 269
 270 #define GEN_VXFORM(name, opc2, opc3)                                    \
 271 static void glue(gen_, name)(DisasContext *ctx)                         \
 272 {                                                                       \
 273     TCGv_ptr ra, rb, rd;                                                \
 274     if (unlikely(!ctx->altivec_enabled)) {                              \
 275         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 276         return;                                                         \
 277     }                                                                   \
 278     ra = gen_avr_ptr(rA(ctx->opcode));                                  \
 279     rb = gen_avr_ptr(rB(ctx->opcode));                                  \
 280     rd = gen_avr_ptr(rD(ctx->opcode));                                  \
 281     gen_helper_##name(rd, ra, rb);                                      \
 282     tcg_temp_free_ptr(ra);                                              \
 283     tcg_temp_free_ptr(rb);                                              \
 284     tcg_temp_free_ptr(rd);                                              \
 285 }
 286
 287 #define GEN_VXFORM_TRANS(name, opc2, opc3)                              \
 288 static void glue(gen_, name)(DisasContext *ctx)                         \
 289 {                                                                       \
 290     if (unlikely(!ctx->altivec_enabled)) {                              \
 291         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 292         return;                                                         \
 293     }                                                                   \
 294     trans_##name(ctx);                                                  \
 295 }
 296
 297 #define GEN_VXFORM_ENV(name, opc2, opc3)                                \
 298 static void glue(gen_, name)(DisasContext *ctx)                         \
 299 {                                                                       \
 300     TCGv_ptr ra, rb, rd;                                                \
 301     if (unlikely(!ctx->altivec_enabled)) {                              \
 302         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 303         return;                                                         \
 304     }                                                                   \
 305     ra = gen_avr_ptr(rA(ctx->opcode));                                  \
 306     rb = gen_avr_ptr(rB(ctx->opcode));                                  \
 307     rd = gen_avr_ptr(rD(ctx->opcode));                                  \
 308     gen_helper_##name(cpu_env, rd, ra, rb);                             \
 309     tcg_temp_free_ptr(ra);                                              \
 310     tcg_temp_free_ptr(rb);                                              \
 311     tcg_temp_free_ptr(rd);                                              \
 312 }
 313
 314 #define GEN_VXFORM3(name, opc2, opc3)                                   \
 315 static void glue(gen_, name)(DisasContext *ctx)                         \
 316 {                                                                       \
 317     TCGv_ptr ra, rb, rc, rd;                                            \
 318     if (unlikely(!ctx->altivec_enabled)) {                              \
 319         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 320         return;                                                         \
 321     }                                                                   \
 322     ra = gen_avr_ptr(rA(ctx->opcode));                                  \
 323     rb = gen_avr_ptr(rB(ctx->opcode));                                  \
 324     rc = gen_avr_ptr(rC(ctx->opcode));                                  \
 325     rd = gen_avr_ptr(rD(ctx->opcode));                                  \
 326     gen_helper_##name(rd, ra, rb, rc);                                  \
 327     tcg_temp_free_ptr(ra);                                              \
 328     tcg_temp_free_ptr(rb);                                              \
 329     tcg_temp_free_ptr(rc);                                              \
 330     tcg_temp_free_ptr(rd);                                              \
 331 }
 332
 333 /*
 334  * Support for Altivec instruction pairs that use bit 31 (Rc) as
 335  * an opcode bit.  In general, these pairs come from different
 336  * versions of the ISA, so we must also support a pair of flags for
 337  * each instruction.
 338  */
 339 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)          \
 340 static void glue(gen_, name0##_##name1)(DisasContext *ctx)             \
 341 {                                                                      \
 342     if ((Rc(ctx->opcode) == 0) &&                                      \
 343         ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
 344         gen_##name0(ctx);                                              \
 345     } else if ((Rc(ctx->opcode) == 1) &&                               \
 346         ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
 347         gen_##name1(ctx);                                              \
 348     } else {                                                           \
 349         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);            \
 350     }                                                                  \
 351 }
 352
 353 /*
 354  * We use this macro if one instruction is realized with direct
 355  * translation, and second one with helper.
 356  */
 357 #define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
 358 static void glue(gen_, name0##_##name1)(DisasContext *ctx)             \
 359 {                                                                      \
 360     if ((Rc(ctx->opcode) == 0) &&                                      \
 361         ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
 362         if (unlikely(!ctx->altivec_enabled)) {                         \
 363             gen_exception(ctx, POWERPC_EXCP_VPU);                      \
 364             return;                                                    \
 365         }                                                              \
 366         trans_##name0(ctx);                                            \
 367     } else if ((Rc(ctx->opcode) == 1) &&                               \
 368         ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
 369         gen_##name1(ctx);                                              \
 370     } else {                                                           \
 371         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);            \
 372     }                                                                  \
 373 }
 374
 375 /* Adds support to provide invalid mask */
 376 #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0,                \
 377                             name1, flg1, flg2_1, inval1)                \
 378 static void glue(gen_, name0##_##name1)(DisasContext *ctx)              \
 379 {                                                                       \
 380     if ((Rc(ctx->opcode) == 0) &&                                       \
 381         ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) &&  \
 382         !(ctx->opcode & inval0)) {                                      \
 383         gen_##name0(ctx);                                               \
 384     } else if ((Rc(ctx->opcode) == 1) &&                                \
 385                ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
 386                !(ctx->opcode & inval1)) {                               \
 387         gen_##name1(ctx);                                               \
 388     } else {                                                            \
 389         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);             \
 390     }                                                                   \
 391 }
 392
 393 #define GEN_VXFORM_HETRO(name, opc2, opc3)                              \
 394 static void glue(gen_, name)(DisasContext *ctx)                         \
 395 {                                                                       \
 396     TCGv_ptr rb;                                                        \
 397     if (unlikely(!ctx->altivec_enabled)) {                              \
 398         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 399         return;                                                         \
 400     }                                                                   \
 401     rb = gen_avr_ptr(rB(ctx->opcode));                                  \
 402     gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
 403     tcg_temp_free_ptr(rb);                                              \
 404 }
 405
 406 GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
 407 GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0,       \
 408                     vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
 409 GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
 410 GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE,  \
 411                 vmul10ecuq, PPC_NONE, PPC2_ISA300)
 412 GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
 413 GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
 414 GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
 415 GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
 416 GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
 417 GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
 418 GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
 419 GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
 420 GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
 421 GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
 422 GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
 423 GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
 424 GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
 425 GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
 426 GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
 427 GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
 428 GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
 429 GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
 430 GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
 431 GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
 432 GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
 433 GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
 434 GEN_VXFORM(vavgub, 1, 16);
 435 GEN_VXFORM(vabsdub, 1, 16);
 436 GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
 437                 vabsdub, PPC_NONE, PPC2_ISA300)
 438 GEN_VXFORM(vavguh, 1, 17);
 439 GEN_VXFORM(vabsduh, 1, 17);
 440 GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
 441                 vabsduh, PPC_NONE, PPC2_ISA300)
 442 GEN_VXFORM(vavguw, 1, 18);
 443 GEN_VXFORM(vabsduw, 1, 18);
 444 GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
 445                 vabsduw, PPC_NONE, PPC2_ISA300)
 446 GEN_VXFORM(vavgsb, 1, 20);
 447 GEN_VXFORM(vavgsh, 1, 21);
 448 GEN_VXFORM(vavgsw, 1, 22);
 449 GEN_VXFORM(vmrghb, 6, 0);
 450 GEN_VXFORM(vmrghh, 6, 1);
 451 GEN_VXFORM(vmrghw, 6, 2);
 452 GEN_VXFORM(vmrglb, 6, 4);
 453 GEN_VXFORM(vmrglh, 6, 5);
 454 GEN_VXFORM(vmrglw, 6, 6);
 455
 456 static void trans_vmrgew(DisasContext *ctx)
 457 {
 458     int VT = rD(ctx->opcode);
 459     int VA = rA(ctx->opcode);
 460     int VB = rB(ctx->opcode);
 461     TCGv_i64 tmp = tcg_temp_new_i64();
 462     TCGv_i64 avr = tcg_temp_new_i64();
 463
 464     get_avr64(avr, VB, true);
 465     tcg_gen_shri_i64(tmp, avr, 32);
 466     get_avr64(avr, VA, true);
 467     tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
 468     set_avr64(VT, avr, true);
 469
 470     get_avr64(avr, VB, false);
 471     tcg_gen_shri_i64(tmp, avr, 32);
 472     get_avr64(avr, VA, false);
 473     tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
 474     set_avr64(VT, avr, false);
 475
 476     tcg_temp_free_i64(tmp);
 477     tcg_temp_free_i64(avr);
 478 }
 479
 480 static void trans_vmrgow(DisasContext *ctx)
 481 {
 482     int VT = rD(ctx->opcode);
 483     int VA = rA(ctx->opcode);
 484     int VB = rB(ctx->opcode);
 485     TCGv_i64 t0 = tcg_temp_new_i64();
 486     TCGv_i64 t1 = tcg_temp_new_i64();
 487     TCGv_i64 avr = tcg_temp_new_i64();
 488
 489     get_avr64(t0, VB, true);
 490     get_avr64(t1, VA, true);
 491     tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
 492     set_avr64(VT, avr, true);
 493
 494     get_avr64(t0, VB, false);
 495     get_avr64(t1, VA, false);
 496     tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
 497     set_avr64(VT, avr, false);
 498
 499     tcg_temp_free_i64(t0);
 500     tcg_temp_free_i64(t1);
 501     tcg_temp_free_i64(avr);
 502 }
 503
 504 /*
 505  * lvsl VRT,RA,RB - Load Vector for Shift Left
 506  *
 507  * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
 508  * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
 509  * Bytes sh:sh+15 of X are placed into vD.
 510  */
 511 static void trans_lvsl(DisasContext *ctx)
 512 {
 513     int VT = rD(ctx->opcode);
 514     TCGv_i64 result = tcg_temp_new_i64();
 515     TCGv_i64 sh = tcg_temp_new_i64();
 516     TCGv EA = tcg_temp_new();
 517
 518     /* Get sh(from description) by anding EA with 0xf. */
 519     gen_addr_reg_index(ctx, EA);
 520     tcg_gen_extu_tl_i64(sh, EA);
 521     tcg_gen_andi_i64(sh, sh, 0xfULL);
 522
 523     /*
 524      * Create bytes sh:sh+7 of X(from description) and place them in
 525      * higher doubleword of vD.
 526      */
 527     tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
 528     tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
 529     set_avr64(VT, result, true);
 530     /*
 531      * Create bytes sh+8:sh+15 of X(from description) and place them in
 532      * lower doubleword of vD.
 533      */
 534     tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
 535     set_avr64(VT, result, false);
 536
 537     tcg_temp_free_i64(result);
 538     tcg_temp_free_i64(sh);
 539     tcg_temp_free(EA);
 540 }
 541
 542 /*
 543  * lvsr VRT,RA,RB - Load Vector for Shift Right
 544  *
 545  * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
 546  * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
 547  * Bytes (16-sh):(31-sh) of X are placed into vD.
 548  */
 549 static void trans_lvsr(DisasContext *ctx)
 550 {
 551     int VT = rD(ctx->opcode);
 552     TCGv_i64 result = tcg_temp_new_i64();
 553     TCGv_i64 sh = tcg_temp_new_i64();
 554     TCGv EA = tcg_temp_new();
 555
 556
 557     /* Get sh(from description) by anding EA with 0xf. */
 558     gen_addr_reg_index(ctx, EA);
 559     tcg_gen_extu_tl_i64(sh, EA);
 560     tcg_gen_andi_i64(sh, sh, 0xfULL);
 561
 562     /*
 563      * Create bytes (16-sh):(23-sh) of X(from description) and place them in
 564      * higher doubleword of vD.
 565      */
 566     tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
 567     tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
 568     set_avr64(VT, result, true);
 569     /*
 570      * Create bytes (24-sh):(32-sh) of X(from description) and place them in
 571      * lower doubleword of vD.
 572      */
 573     tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
 574     set_avr64(VT, result, false);
 575
 576     tcg_temp_free_i64(result);
 577     tcg_temp_free_i64(sh);
 578     tcg_temp_free(EA);
 579 }
 580
 581 /*
 582  * vsl VRT,VRA,VRB - Vector Shift Left
 583  *
 584  * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
 585  * Lowest 3 bits in each byte element of register vB must be identical or
 586  * result is undefined.
 587  */
 588 static void trans_vsl(DisasContext *ctx)
 589 {
 590     int VT = rD(ctx->opcode);
 591     int VA = rA(ctx->opcode);
 592     int VB = rB(ctx->opcode);
 593     TCGv_i64 avr = tcg_temp_new_i64();
 594     TCGv_i64 sh = tcg_temp_new_i64();
 595     TCGv_i64 carry = tcg_temp_new_i64();
 596     TCGv_i64 tmp = tcg_temp_new_i64();
 597
 598     /* Place bits 125-127 of vB in 'sh'. */
 599     get_avr64(avr, VB, false);
 600     tcg_gen_andi_i64(sh, avr, 0x07ULL);
 601
 602     /*
 603      * Save highest 'sh' bits of lower doubleword element of vA in variable
 604      * 'carry' and perform shift on lower doubleword.
 605      */
 606     get_avr64(avr, VA, false);
 607     tcg_gen_subfi_i64(tmp, 32, sh);
 608     tcg_gen_shri_i64(carry, avr, 32);
 609     tcg_gen_shr_i64(carry, carry, tmp);
 610     tcg_gen_shl_i64(avr, avr, sh);
 611     set_avr64(VT, avr, false);
 612
 613     /*
 614      * Perform shift on higher doubleword element of vA and replace lowest
 615      * 'sh' bits with 'carry'.
 616      */
 617     get_avr64(avr, VA, true);
 618     tcg_gen_shl_i64(avr, avr, sh);
 619     tcg_gen_or_i64(avr, avr, carry);
 620     set_avr64(VT, avr, true);
 621
 622     tcg_temp_free_i64(avr);
 623     tcg_temp_free_i64(sh);
 624     tcg_temp_free_i64(carry);
 625     tcg_temp_free_i64(tmp);
 626 }
 627
 628 /*
 629  * vsr VRT,VRA,VRB - Vector Shift Right
 630  *
 631  * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
 632  * Lowest 3 bits in each byte element of register vB must be identical or
 633  * result is undefined.
 634  */
 635 static void trans_vsr(DisasContext *ctx)
 636 {
 637     int VT = rD(ctx->opcode);
 638     int VA = rA(ctx->opcode);
 639     int VB = rB(ctx->opcode);
 640     TCGv_i64 avr = tcg_temp_new_i64();
 641     TCGv_i64 sh = tcg_temp_new_i64();
 642     TCGv_i64 carry = tcg_temp_new_i64();
 643     TCGv_i64 tmp = tcg_temp_new_i64();
 644
 645     /* Place bits 125-127 of vB in 'sh'. */
 646     get_avr64(avr, VB, false);
 647     tcg_gen_andi_i64(sh, avr, 0x07ULL);
 648
 649     /*
 650      * Save lowest 'sh' bits of higher doubleword element of vA in variable
 651      * 'carry' and perform shift on higher doubleword.
 652      */
 653     get_avr64(avr, VA, true);
 654     tcg_gen_subfi_i64(tmp, 32, sh);
 655     tcg_gen_shli_i64(carry, avr, 32);
 656     tcg_gen_shl_i64(carry, carry, tmp);
 657     tcg_gen_shr_i64(avr, avr, sh);
 658     set_avr64(VT, avr, true);
 659     /*
 660      * Perform shift on lower doubleword element of vA and replace highest
 661      * 'sh' bits with 'carry'.
 662      */
 663     get_avr64(avr, VA, false);
 664     tcg_gen_shr_i64(avr, avr, sh);
 665     tcg_gen_or_i64(avr, avr, carry);
 666     set_avr64(VT, avr, false);
 667
 668     tcg_temp_free_i64(avr);
 669     tcg_temp_free_i64(sh);
 670     tcg_temp_free_i64(carry);
 671     tcg_temp_free_i64(tmp);
 672 }
 673
 674 /*
 675  * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
 676  *
 677  * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
 678  * register are concatenated and placed into ith byte of appropriate doubleword
 679  * element in destination register.
 680  *
 681  * Following solution is done for both doubleword elements of source register
 682  * in parallel, in order to reduce the number of instructions needed(that's why
 683  * arrays are used):
 684  * First, both doubleword elements of source register vB are placed in
 685  * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
 686  * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
 687  * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
 688  * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
 689  * have to be shifted right for 7 and 8 places, respectively, in order to get
 690  * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
 691  * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
 692  * After first 8 iteration(first loop), all the first bits are in their final
 693  * places, all second bits but second bit from eight byte are in their places...
 694  * only 1 eight bit from eight byte is in it's place). In second loop we do all
 695  * operations symmetrically, in order to get other half of bits in their final
 696  * spots. Results for first and second doubleword elements are saved in
 697  * result[0] and result[1] respectively. In the end those results are saved in
 698  * appropriate doubleword element of destination register vD.
 699  */
 700 static void trans_vgbbd(DisasContext *ctx)
 701 {
 702     int VT = rD(ctx->opcode);
 703     int VB = rB(ctx->opcode);
 704     TCGv_i64 tmp = tcg_temp_new_i64();
 705     uint64_t mask = 0x8040201008040201ULL;
 706     int i, j;
 707
 708     TCGv_i64 result[2];
 709     result[0] = tcg_temp_new_i64();
 710     result[1] = tcg_temp_new_i64();
 711     TCGv_i64 avr[2];
 712     avr[0] = tcg_temp_new_i64();
 713     avr[1] = tcg_temp_new_i64();
 714     TCGv_i64 tcg_mask = tcg_temp_new_i64();
 715
 716     tcg_gen_movi_i64(tcg_mask, mask);
 717     for (j = 0; j < 2; j++) {
 718         get_avr64(avr[j], VB, j);
 719         tcg_gen_and_i64(result[j], avr[j], tcg_mask);
 720     }
 721     for (i = 1; i < 8; i++) {
 722         tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
 723         for (j = 0; j < 2; j++) {
 724             tcg_gen_shri_i64(tmp, avr[j], i * 7);
 725             tcg_gen_and_i64(tmp, tmp, tcg_mask);
 726             tcg_gen_or_i64(result[j], result[j], tmp);
 727         }
 728     }
 729     for (i = 1; i < 8; i++) {
 730         tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
 731         for (j = 0; j < 2; j++) {
 732             tcg_gen_shli_i64(tmp, avr[j], i * 7);
 733             tcg_gen_and_i64(tmp, tmp, tcg_mask);
 734             tcg_gen_or_i64(result[j], result[j], tmp);
 735         }
 736     }
 737     for (j = 0; j < 2; j++) {
 738         set_avr64(VT, result[j], j);
 739     }
 740
 741     tcg_temp_free_i64(tmp);
 742     tcg_temp_free_i64(tcg_mask);
 743     tcg_temp_free_i64(result[0]);
 744     tcg_temp_free_i64(result[1]);
 745     tcg_temp_free_i64(avr[0]);
 746     tcg_temp_free_i64(avr[1]);
 747 }
 748
 749 /*
 750  * vclzw VRT,VRB - Vector Count Leading Zeros Word
 751  *
 752  * Counting the number of leading zero bits of each word element in source
 753  * register and placing result in appropriate word element of destination
 754  * register.
 755  */
 756 static void trans_vclzw(DisasContext *ctx)
 757 {
 758     int VT = rD(ctx->opcode);
 759     int VB = rB(ctx->opcode);
 760     TCGv_i32 tmp = tcg_temp_new_i32();
 761     int i;
 762
 763     /* Perform count for every word element using tcg_gen_clzi_i32. */
 764     for (i = 0; i < 4; i++) {
 765         tcg_gen_ld_i32(tmp, cpu_env,
 766             offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
 767         tcg_gen_clzi_i32(tmp, tmp, 32);
 768         tcg_gen_st_i32(tmp, cpu_env,
 769             offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
 770     }
 771
 772     tcg_temp_free_i32(tmp);
 773 }
 774
 775 /*
 776  * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
 777  *
 778  * Counting the number of leading zero bits of each doubleword element in source
 779  * register and placing result in appropriate doubleword element of destination
 780  * register.
 781  */
 782 static void trans_vclzd(DisasContext *ctx)
 783 {
 784     int VT = rD(ctx->opcode);
 785     int VB = rB(ctx->opcode);
 786     TCGv_i64 avr = tcg_temp_new_i64();
 787
 788     /* high doubleword */
 789     get_avr64(avr, VB, true);
 790     tcg_gen_clzi_i64(avr, avr, 64);
 791     set_avr64(VT, avr, true);
 792
 793     /* low doubleword */
 794     get_avr64(avr, VB, false);
 795     tcg_gen_clzi_i64(avr, avr, 64);
 796     set_avr64(VT, avr, false);
 797
 798     tcg_temp_free_i64(avr);
 799 }
 800
 801 GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
 802 GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
 803 GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
 804 GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
 805 GEN_VXFORM(vrlwnm, 2, 6);
 806 GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
 807                 vrlwnm, PPC_NONE, PPC2_ISA300)
 808 GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);
 809 GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);
 810 GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);
 811 GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);
 812 GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);
 813 GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);
 814 GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);
 815 GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);
 816 GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);
 817 GEN_VXFORM(vsrv, 2, 28);
 818 GEN_VXFORM(vslv, 2, 29);
 819 GEN_VXFORM(vslo, 6, 16);
 820 GEN_VXFORM(vsro, 6, 17);
 821 GEN_VXFORM(vaddcuw, 0, 6);
 822 GEN_VXFORM(vsubcuw, 0, 22);
 823
 824 #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3)               \
 825 static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t,     \
 826                                          TCGv_vec sat, TCGv_vec a,      \
 827                                          TCGv_vec b)                    \
 828 {                                                                       \
 829     TCGv_vec x = tcg_temp_new_vec_matching(t);                          \
 830     glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b);                    \
 831     glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b);                     \
 832     tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t);                        \
 833     tcg_gen_or_vec(VECE, sat, sat, x);                                  \
 834     tcg_temp_free_vec(x);                                               \
 835 }                                                                       \
 836 static void glue(gen_, NAME)(DisasContext *ctx)                         \
 837 {                                                                       \
 838     static const TCGOpcode vecop_list[] = {                             \
 839         glue(glue(INDEX_op_, NORM), _vec),                              \
 840         glue(glue(INDEX_op_, SAT), _vec),                               \
 841         INDEX_op_cmp_vec, 0                                             \
 842     };                                                                  \
 843     static const GVecGen4 g = {                                         \
 844         .fniv = glue(glue(gen_, NAME), _vec),                           \
 845         .fno = glue(gen_helper_, NAME),                                 \
 846         .opt_opc = vecop_list,                                          \
 847         .write_aofs = true,                                             \
 848         .vece = VECE,                                                   \
 849     };                                                                  \
 850     if (unlikely(!ctx->altivec_enabled)) {                              \
 851         gen_exception(ctx, POWERPC_EXCP_VPU);                           \
 852         return;                                                         \
 853     }                                                                   \
 854     tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)),                    \
 855                    offsetof(CPUPPCState, vscr_sat),                     \
 856                    avr_full_offset(rA(ctx->opcode)),                    \
 857                    avr_full_offset(rB(ctx->opcode)),                    \
 858                    16, 16, &g);                                         \
 859 }
 860
 861 GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
 862 GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0,       \
 863                     vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
 864 GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
 865 GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
 866                 vmul10euq, PPC_NONE, PPC2_ISA300)
 867 GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
 868 GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
 869 GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
 870 GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
 871 GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
 872 GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
 873 GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
 874 GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
 875 GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
 876 GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
 877 GEN_VXFORM(vadduqm, 0, 4);
 878 GEN_VXFORM(vaddcuq, 0, 5);
 879 GEN_VXFORM3(vaddeuqm, 30, 0);
 880 GEN_VXFORM3(vaddecuq, 30, 0);
 881 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
 882             vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
 883 GEN_VXFORM(vsubuqm, 0, 20);
 884 GEN_VXFORM(vsubcuq, 0, 21);
 885 GEN_VXFORM3(vsubeuqm, 31, 0);
 886 GEN_VXFORM3(vsubecuq, 31, 0);
 887 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
 888             vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
 889 GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
 890 GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
 891 GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
 892 GEN_VXFORM(vrlwmi, 2, 2);
 893 GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
 894                 vrlwmi, PPC_NONE, PPC2_ISA300)
 895 GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
 896 GEN_VXFORM(vrldmi, 2, 3);
 897 GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
 898                 vrldmi, PPC_NONE, PPC2_ISA300)
 899 GEN_VXFORM_TRANS(vsl, 2, 7);
 900 GEN_VXFORM(vrldnm, 2, 7);
 901 GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
 902                 vrldnm, PPC_NONE, PPC2_ISA300)
 903 GEN_VXFORM_TRANS(vsr, 2, 11);
 904 GEN_VXFORM_ENV(vpkuhum, 7, 0);
 905 GEN_VXFORM_ENV(vpkuwum, 7, 1);
 906 GEN_VXFORM_ENV(vpkudum, 7, 17);
 907 GEN_VXFORM_ENV(vpkuhus, 7, 2);
 908 GEN_VXFORM_ENV(vpkuwus, 7, 3);
 909 GEN_VXFORM_ENV(vpkudus, 7, 19);
 910 GEN_VXFORM_ENV(vpkshus, 7, 4);
 911 GEN_VXFORM_ENV(vpkswus, 7, 5);
 912 GEN_VXFORM_ENV(vpksdus, 7, 21);
 913 GEN_VXFORM_ENV(vpkshss, 7, 6);
 914 GEN_VXFORM_ENV(vpkswss, 7, 7);
 915 GEN_VXFORM_ENV(vpksdss, 7, 23);
 916 GEN_VXFORM(vpkpx, 7, 12);
 917 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
 918 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
 919 GEN_VXFORM_ENV(vsum4shs, 4, 25);
 920 GEN_VXFORM_ENV(vsum2sws, 4, 26);
 921 GEN_VXFORM_ENV(vsumsws, 4, 30);
 922 GEN_VXFORM_ENV(vaddfp, 5, 0);
 923 GEN_VXFORM_ENV(vsubfp, 5, 1);
 924 GEN_VXFORM_ENV(vmaxfp, 5, 16);
 925 GEN_VXFORM_ENV(vminfp, 5, 17);
 926 GEN_VXFORM_HETRO(vextublx, 6, 24)
 927 GEN_VXFORM_HETRO(vextuhlx, 6, 25)
 928 GEN_VXFORM_HETRO(vextuwlx, 6, 26)
 929 GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
 930                 vextuwlx, PPC_NONE, PPC2_ISA300)
 931 GEN_VXFORM_HETRO(vextubrx, 6, 28)
 932 GEN_VXFORM_HETRO(vextuhrx, 6, 29)
 933 GEN_VXFORM_HETRO(vextuwrx, 6, 30)
 934 GEN_VXFORM_TRANS(lvsl, 6, 31)
 935 GEN_VXFORM_TRANS(lvsr, 6, 32)
 936 GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
 937                 vextuwrx, PPC_NONE, PPC2_ISA300)
 938
 939 #define GEN_VXRFORM1(opname, name, str, opc2, opc3)                     \
 940 static void glue(gen_, name)(DisasContext *ctx)                         \
 941     {                                                                   \
 942         TCGv_ptr ra, rb, rd;                                            \
 943         if (unlikely(!ctx->altivec_enabled)) {                          \
 944             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
 945             return;                                                     \
 946         }                                                               \
 947         ra = gen_avr_ptr(rA(ctx->opcode));                              \
 948         rb = gen_avr_ptr(rB(ctx->opcode));                              \
 949         rd = gen_avr_ptr(rD(ctx->opcode));                              \
 950         gen_helper_##opname(cpu_env, rd, ra, rb);                       \
 951         tcg_temp_free_ptr(ra);                                          \
 952         tcg_temp_free_ptr(rb);                                          \
 953         tcg_temp_free_ptr(rd);                                          \
 954     }
 955
 956 #define GEN_VXRFORM(name, opc2, opc3)                                \
 957     GEN_VXRFORM1(name, name, #name, opc2, opc3)                      \
 958     GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
 959
 960 /*
 961  * Support for Altivec instructions that use bit 31 (Rc) as an opcode
 962  * bit but also use bit 21 as an actual Rc bit.  In general, thse pairs
 963  * come from different versions of the ISA, so we must also support a
 964  * pair of flags for each instruction.
 965  */
 966 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)     \
 967 static void glue(gen_, name0##_##name1)(DisasContext *ctx)             \
 968 {                                                                      \
 969     if ((Rc(ctx->opcode) == 0) &&                                      \
 970         ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
 971         if (Rc21(ctx->opcode) == 0) {                                  \
 972             gen_##name0(ctx);                                          \
 973         } else {                                                       \
 974             gen_##name0##_(ctx);                                       \
 975         }                                                              \
 976     } else if ((Rc(ctx->opcode) == 1) &&                               \
 977         ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
 978         if (Rc21(ctx->opcode) == 0) {                                  \
 979             gen_##name1(ctx);                                          \
 980         } else {                                                       \
 981             gen_##name1##_(ctx);                                       \
 982         }                                                              \
 983     } else {                                                           \
 984         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);            \
 985     }                                                                  \
 986 }
 987
 988 static void do_vcmp_rc(int vrt)
 989 {
 990     TCGv_i64 tmp, set, clr;
 991
 992     tmp = tcg_temp_new_i64();
 993     set = tcg_temp_new_i64();
 994     clr = tcg_temp_new_i64();
 995
 996     get_avr64(tmp, vrt, true);
 997     tcg_gen_mov_i64(set, tmp);
 998     get_avr64(tmp, vrt, false);
 999     tcg_gen_or_i64(clr, set, tmp);
1000     tcg_gen_and_i64(set, set, tmp);
1001
1002     tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1003     tcg_gen_shli_i64(clr, clr, 1);
1004
1005     tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
1006     tcg_gen_shli_i64(set, set, 3);
1007
1008     tcg_gen_or_i64(tmp, set, clr);
1009     tcg_gen_extrl_i64_i32(cpu_crf[6], tmp);
1010
1011     tcg_temp_free_i64(tmp);
1012     tcg_temp_free_i64(set);
1013     tcg_temp_free_i64(clr);
1014 }
1015
1016 static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
1017 {
1018     REQUIRE_VECTOR(ctx);
1019
1020     tcg_gen_gvec_cmp(cond, vece, avr_full_offset(a->vrt),
1021                      avr_full_offset(a->vra), avr_full_offset(a->vrb), 16, 16);
1022
1023     if (a->rc) {
1024         do_vcmp_rc(a->vrt);
1025     }
1026
1027     return true;
1028 }
1029
1030 TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
1031 TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
1032 TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
1033 TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1034
1035 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
1036 TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
1037 TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
1038 TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1039 TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
1040 TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
1041 TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
1042 TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
1043
1044 TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
1045 TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
1046 TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
1047
1048 static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1049 {
1050     TCGv_vec t0, t1, zero;
1051
1052     t0 = tcg_temp_new_vec_matching(t);
1053     t1 = tcg_temp_new_vec_matching(t);
1054     zero = tcg_constant_vec_matching(t, vece, 0);
1055
1056     tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
1057     tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
1058     tcg_gen_cmp_vec(TCG_COND_NE, vece, t, a, b);
1059
1060     tcg_gen_or_vec(vece, t, t, t0);
1061     tcg_gen_or_vec(vece, t, t, t1);
1062
1063     tcg_temp_free_vec(t0);
1064     tcg_temp_free_vec(t1);
1065 }
1066
1067 static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece)
1068 {
1069     static const TCGOpcode vecop_list[] = {
1070         INDEX_op_cmp_vec, 0
1071     };
1072     static const GVecGen3 ops[3] = {
1073         {
1074             .fniv = gen_vcmpnez_vec,
1075             .fno = gen_helper_VCMPNEZB,
1076             .opt_opc = vecop_list,
1077             .vece = MO_8
1078         },
1079         {
1080             .fniv = gen_vcmpnez_vec,
1081             .fno = gen_helper_VCMPNEZH,
1082             .opt_opc = vecop_list,
1083             .vece = MO_16
1084         },
1085         {
1086             .fniv = gen_vcmpnez_vec,
1087             .fno = gen_helper_VCMPNEZW,
1088             .opt_opc = vecop_list,
1089             .vece = MO_32
1090         }
1091     };
1092
1093     REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1094     REQUIRE_VECTOR(ctx);
1095
1096     tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
1097                    avr_full_offset(a->vrb), 16, 16, &ops[vece]);
1098
1099     if (a->rc) {
1100         do_vcmp_rc(a->vrt);
1101     }
1102
1103     return true;
1104 }
1105
1106 TRANS(VCMPNEZB, do_vcmpnez, MO_8)
1107 TRANS(VCMPNEZH, do_vcmpnez, MO_16)
1108 TRANS(VCMPNEZW, do_vcmpnez, MO_32)
1109
1110 static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
1111 {
1112     TCGv_i64 t0, t1, t2;
1113
1114     t0 = tcg_temp_new_i64();
1115     t1 = tcg_temp_new_i64();
1116     t2 = tcg_temp_new_i64();
1117
1118     get_avr64(t0, a->vra, true);
1119     get_avr64(t1, a->vrb, true);
1120     tcg_gen_xor_i64(t2, t0, t1);
1121
1122     get_avr64(t0, a->vra, false);
1123     get_avr64(t1, a->vrb, false);
1124     tcg_gen_xor_i64(t1, t0, t1);
1125
1126     tcg_gen_or_i64(t1, t1, t2);
1127     tcg_gen_setcondi_i64(TCG_COND_EQ, t1, t1, 0);
1128     tcg_gen_neg_i64(t1, t1);
1129
1130     set_avr64(a->vrt, t1, true);
1131     set_avr64(a->vrt, t1, false);
1132
1133     if (a->rc) {
1134         tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
1135         tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
1136         tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
1137     }
1138
1139     tcg_temp_free_i64(t0);
1140     tcg_temp_free_i64(t1);
1141     tcg_temp_free_i64(t2);
1142
1143     return true;
1144 }
1145
1146 static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
1147 {
1148     TCGv_i64 t0, t1, t2;
1149
1150     t0 = tcg_temp_new_i64();
1151     t1 = tcg_temp_new_i64();
1152     t2 = tcg_temp_new_i64();
1153
1154     get_avr64(t0, a->vra, false);
1155     get_avr64(t1, a->vrb, false);
1156     tcg_gen_setcond_i64(TCG_COND_GTU, t2, t0, t1);
1157
1158     get_avr64(t0, a->vra, true);
1159     get_avr64(t1, a->vrb, true);
1160     tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0));
1161     tcg_gen_setcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1);
1162
1163     tcg_gen_or_i64(t1, t1, t2);
1164     tcg_gen_neg_i64(t1, t1);
1165
1166     set_avr64(a->vrt, t1, true);
1167     set_avr64(a->vrt, t1, false);
1168
1169     if (a->rc) {
1170         tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
1171         tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
1172         tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
1173     }
1174
1175     tcg_temp_free_i64(t0);
1176     tcg_temp_free_i64(t1);
1177     tcg_temp_free_i64(t2);
1178
1179     return true;
1180 }
1181
1182 TRANS(VCMPGTSQ, do_vcmpgtq, true)
1183 TRANS(VCMPGTUQ, do_vcmpgtq, false)
1184
1185 static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
1186 {
1187     TCGv_i64 vra, vrb;
1188     TCGLabel *gt, *lt, *done;
1189
1190     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1191     REQUIRE_VECTOR(ctx);
1192
1193     vra = tcg_temp_local_new_i64();
1194     vrb = tcg_temp_local_new_i64();
1195     gt = gen_new_label();
1196     lt = gen_new_label();
1197     done = gen_new_label();
1198
1199     get_avr64(vra, a->vra, true);
1200     get_avr64(vrb, a->vrb, true);
1201     tcg_gen_brcond_i64((sign ? TCG_COND_GT : TCG_COND_GTU), vra, vrb, gt);
1202     tcg_gen_brcond_i64((sign ? TCG_COND_LT : TCG_COND_LTU), vra, vrb, lt);
1203
1204     get_avr64(vra, a->vra, false);
1205     get_avr64(vrb, a->vrb, false);
1206     tcg_gen_brcond_i64(TCG_COND_GTU, vra, vrb, gt);
1207     tcg_gen_brcond_i64(TCG_COND_LTU, vra, vrb, lt);
1208
1209     tcg_gen_movi_i32(cpu_crf[a->bf], CRF_EQ);
1210     tcg_gen_br(done);
1211
1212     gen_set_label(gt);
1213     tcg_gen_movi_i32(cpu_crf[a->bf], CRF_GT);
1214     tcg_gen_br(done);
1215
1216     gen_set_label(lt);
1217     tcg_gen_movi_i32(cpu_crf[a->bf], CRF_LT);
1218     tcg_gen_br(done);
1219
1220     gen_set_label(done);
1221     tcg_temp_free_i64(vra);
1222     tcg_temp_free_i64(vrb);
1223
1224     return true;
1225 }
1226
1227 TRANS(VCMPSQ, do_vcmpq, true)
1228 TRANS(VCMPUQ, do_vcmpq, false)
1229
1230 GEN_VXRFORM(vcmpeqfp, 3, 3)
1231 GEN_VXRFORM(vcmpgefp, 3, 7)
1232 GEN_VXRFORM(vcmpgtfp, 3, 11)
1233 GEN_VXRFORM(vcmpbfp, 3, 15)
1234
1235 static void gen_vsplti(DisasContext *ctx, int vece)
1236 {
1237     int simm;
1238
1239     if (unlikely(!ctx->altivec_enabled)) {
1240         gen_exception(ctx, POWERPC_EXCP_VPU);
1241         return;
1242     }
1243
1244     simm = SIMM5(ctx->opcode);
1245     tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
1246 }
1247
1248 #define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
1249 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
1250
1251 GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
1252 GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
1253 GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
1254
1255 #define GEN_VXFORM_NOA(name, opc2, opc3)                                \
1256 static void glue(gen_, name)(DisasContext *ctx)                         \
1257     {                                                                   \
1258         TCGv_ptr rb, rd;                                                \
1259         if (unlikely(!ctx->altivec_enabled)) {                          \
1260             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
1261             return;                                                     \
1262         }                                                               \
1263         rb = gen_avr_ptr(rB(ctx->opcode));                              \
1264         rd = gen_avr_ptr(rD(ctx->opcode));                              \
1265         gen_helper_##name(rd, rb);                                      \
1266         tcg_temp_free_ptr(rb);                                          \
1267         tcg_temp_free_ptr(rd);                                          \
1268     }
1269
1270 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3)                            \
1271 static void glue(gen_, name)(DisasContext *ctx)                         \
1272     {                                                                   \
1273         TCGv_ptr rb, rd;                                                \
1274                                                                         \
1275         if (unlikely(!ctx->altivec_enabled)) {                          \
1276             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
1277             return;                                                     \
1278         }                                                               \
1279         rb = gen_avr_ptr(rB(ctx->opcode));                              \
1280         rd = gen_avr_ptr(rD(ctx->opcode));                              \
1281         gen_helper_##name(cpu_env, rd, rb);                             \
1282         tcg_temp_free_ptr(rb);                                          \
1283         tcg_temp_free_ptr(rd);                                          \
1284     }
1285
1286 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4)                        \
1287 static void glue(gen_, name)(DisasContext *ctx)                         \
1288     {                                                                   \
1289         TCGv_ptr rb, rd;                                                \
1290         if (unlikely(!ctx->altivec_enabled)) {                          \
1291             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
1292             return;                                                     \
1293         }                                                               \
1294         rb = gen_avr_ptr(rB(ctx->opcode));                              \
1295         rd = gen_avr_ptr(rD(ctx->opcode));                              \
1296         gen_helper_##name(rd, rb);                                      \
1297         tcg_temp_free_ptr(rb);                                          \
1298         tcg_temp_free_ptr(rd);                                          \
1299     }
1300
1301 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4)                        \
1302 static void glue(gen_, name)(DisasContext *ctx)                         \
1303     {                                                                   \
1304         TCGv_ptr rb;                                                    \
1305         if (unlikely(!ctx->altivec_enabled)) {                          \
1306             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
1307             return;                                                     \
1308         }                                                               \
1309         rb = gen_avr_ptr(rB(ctx->opcode));                              \
1310         gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb);                \
1311         tcg_temp_free_ptr(rb);                                          \
1312     }
1313 GEN_VXFORM_NOA(vupkhsb, 7, 8);
1314 GEN_VXFORM_NOA(vupkhsh, 7, 9);
1315 GEN_VXFORM_NOA(vupkhsw, 7, 25);
1316 GEN_VXFORM_NOA(vupklsb, 7, 10);
1317 GEN_VXFORM_NOA(vupklsh, 7, 11);
1318 GEN_VXFORM_NOA(vupklsw, 7, 27);
1319 GEN_VXFORM_NOA(vupkhpx, 7, 13);
1320 GEN_VXFORM_NOA(vupklpx, 7, 15);
1321 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
1322 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
1323 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
1324 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
1325 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
1326 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
1327 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
1328 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
1329 GEN_VXFORM_NOA(vprtybw, 1, 24);
1330 GEN_VXFORM_NOA(vprtybd, 1, 24);
1331 GEN_VXFORM_NOA(vprtybq, 1, 24);
1332
1333 static void gen_vsplt(DisasContext *ctx, int vece)
1334 {
1335     int uimm, dofs, bofs;
1336
1337     if (unlikely(!ctx->altivec_enabled)) {
1338         gen_exception(ctx, POWERPC_EXCP_VPU);
1339         return;
1340     }
1341
1342     uimm = UIMM5(ctx->opcode);
1343     bofs = avr_full_offset(rB(ctx->opcode));
1344     dofs = avr_full_offset(rD(ctx->opcode));
1345
1346     /* Experimental testing shows that hardware masks the immediate.  */
1347     bofs += (uimm << vece) & 15;
1348 #ifndef HOST_WORDS_BIGENDIAN
1349     bofs ^= 15;
1350     bofs &= ~((1 << vece) - 1);
1351 #endif
1352
1353     tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
1354 }
1355
1356 #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
1357 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
1358
1359 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3)                           \
1360 static void glue(gen_, name)(DisasContext *ctx)                         \
1361     {                                                                   \
1362         TCGv_ptr rb, rd;                                                \
1363         TCGv_i32 uimm;                                                  \
1364                                                                         \
1365         if (unlikely(!ctx->altivec_enabled)) {                          \
1366             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
1367             return;                                                     \
1368         }                                                               \
1369         uimm = tcg_const_i32(UIMM5(ctx->opcode));                       \
1370         rb = gen_avr_ptr(rB(ctx->opcode));                              \
1371         rd = gen_avr_ptr(rD(ctx->opcode));                              \
1372         gen_helper_##name(cpu_env, rd, rb, uimm);                       \
1373         tcg_temp_free_i32(uimm);                                        \
1374         tcg_temp_free_ptr(rb);                                          \
1375         tcg_temp_free_ptr(rd);                                          \
1376     }
1377
1378 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max)              \
1379 static void glue(gen_, name)(DisasContext *ctx)                         \
1380     {                                                                   \
1381         TCGv_ptr rb, rd;                                                \
1382         uint8_t uimm = UIMM4(ctx->opcode);                              \
1383         TCGv_i32 t0;                                                    \
1384         if (unlikely(!ctx->altivec_enabled)) {                          \
1385             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
1386             return;                                                     \
1387         }                                                               \
1388         if (uimm > splat_max) {                                         \
1389             uimm = 0;                                                   \
1390         }                                                               \
1391         t0 = tcg_temp_new_i32();                                        \
1392         tcg_gen_movi_i32(t0, uimm);                                     \
1393         rb = gen_avr_ptr(rB(ctx->opcode));                              \
1394         rd = gen_avr_ptr(rD(ctx->opcode));                              \
1395         gen_helper_##name(rd, rb, t0);                                  \
1396         tcg_temp_free_i32(t0);                                          \
1397         tcg_temp_free_ptr(rb);                                          \
1398         tcg_temp_free_ptr(rd);                                          \
1399     }
1400
1401 GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
1402 GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
1403 GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
1404 GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
1405 GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
1406 GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
1407 GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
1408 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
1409 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
1410 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
1411 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
1412 GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
1413                 vextractub, PPC_NONE, PPC2_ISA300);
1414 GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
1415                 vextractuh, PPC_NONE, PPC2_ISA300);
1416 GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
1417                 vextractuw, PPC_NONE, PPC2_ISA300);
1418
1419 static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
1420                void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
1421 {
1422     TCGv_ptr vrt, vra, vrb;
1423     TCGv rc;
1424
1425     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1426     REQUIRE_VECTOR(ctx);
1427
1428     vrt = gen_avr_ptr(a->vrt);
1429     vra = gen_avr_ptr(a->vra);
1430     vrb = gen_avr_ptr(a->vrb);
1431     rc = tcg_temp_new();
1432
1433     tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
1434     if (right) {
1435         tcg_gen_subfi_tl(rc, 32 - size, rc);
1436     }
1437     gen_helper(cpu_env, vrt, vra, vrb, rc);
1438
1439     tcg_temp_free_ptr(vrt);
1440     tcg_temp_free_ptr(vra);
1441     tcg_temp_free_ptr(vrb);
1442     tcg_temp_free(rc);
1443     return true;
1444 }
1445
1446 TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
1447 TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
1448 TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
1449 TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
1450
1451 TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
1452 TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
1453 TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
1454 TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
1455
1456 static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1457             TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1458 {
1459     TCGv_ptr t;
1460     TCGv idx;
1461
1462     t = gen_avr_ptr(vrt);
1463     idx = tcg_temp_new();
1464
1465     tcg_gen_andi_tl(idx, ra, 0xF);
1466     if (right) {
1467         tcg_gen_subfi_tl(idx, 16 - size, idx);
1468     }
1469
1470     gen_helper(cpu_env, t, rb, idx);
1471
1472     tcg_temp_free_ptr(t);
1473     tcg_temp_free(idx);
1474
1475     return true;
1476 }
1477
1478 static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1479                 int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1480 {
1481     bool ok;
1482     TCGv_i64 val;
1483
1484     val = tcg_temp_new_i64();
1485     get_avr64(val, vrb, true);
1486     ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
1487
1488     tcg_temp_free_i64(val);
1489     return ok;
1490 }
1491
1492 static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1493                         void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1494 {
1495     bool ok;
1496     TCGv_i64 val;
1497
1498     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1499     REQUIRE_VECTOR(ctx);
1500
1501     val = tcg_temp_new_i64();
1502     tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1503
1504     ok = do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_helper);
1505
1506     tcg_temp_free_i64(val);
1507     return ok;
1508 }
1509
1510 static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1511                         void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1512 {
1513     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1514     REQUIRE_VECTOR(ctx);
1515
1516     return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
1517                      gen_helper);
1518 }
1519
1520 static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1521                         void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1522 {
1523     bool ok;
1524     TCGv_i64 val;
1525
1526     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1527     REQUIRE_VECTOR(ctx);
1528
1529     if (a->uim > (16 - size)) {
1530         /*
1531          * PowerISA v3.1 says that the resulting value is undefined in this
1532          * case, so just log a guest error and leave VRT unchanged. The
1533          * real hardware would do a partial insert, e.g. if VRT is zeroed and
1534          * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
1535          * VRT = 0x0000...00001234, but we don't bother to reproduce this
1536          * behavior as software shouldn't rely on it.
1537          */
1538         qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
1539             " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1540             16 - size);
1541         return true;
1542     }
1543
1544     val = tcg_temp_new_i64();
1545     tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1546
1547     ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
1548                   gen_helper);
1549
1550     tcg_temp_free_i64(val);
1551     return ok;
1552 }
1553
1554 static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1555                         void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1556 {
1557     REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1558     REQUIRE_VECTOR(ctx);
1559
1560     if (a->uim > (16 - size)) {
1561         qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
1562             " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1563             16 - size);
1564         return true;
1565     }
1566
1567     return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
1568                      gen_helper);
1569 }
1570
1571 TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
1572 TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
1573 TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
1574 TRANS(VINSDLX, do_vinsx_VX, 8, false, gen_helper_VINSDLX)
1575
1576 TRANS(VINSBRX, do_vinsx_VX, 1, true, gen_helper_VINSBLX)
1577 TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
1578 TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
1579 TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
1580
1581 TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
1582 TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
1583
1584 TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
1585 TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
1586 TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
1587
1588 TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
1589 TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
1590 TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
1591
1592 TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
1593 TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
1594 TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
1595 TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
1596
1597 static void gen_vsldoi(DisasContext *ctx)
1598 {
1599     TCGv_ptr ra, rb, rd;
1600     TCGv_i32 sh;
1601     if (unlikely(!ctx->altivec_enabled)) {
1602         gen_exception(ctx, POWERPC_EXCP_VPU);
1603         return;
1604     }
1605     ra = gen_avr_ptr(rA(ctx->opcode));
1606     rb = gen_avr_ptr(rB(ctx->opcode));
1607     rd = gen_avr_ptr(rD(ctx->opcode));
1608     sh = tcg_const_i32(VSH(ctx->opcode));
1609     gen_helper_vsldoi(rd, ra, rb, sh);
1610     tcg_temp_free_ptr(ra);
1611     tcg_temp_free_ptr(rb);
1612     tcg_temp_free_ptr(rd);
1613     tcg_temp_free_i32(sh);
1614 }
1615
1616 static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
1617 {
1618     TCGv_i64 t0, t1, t2;
1619
1620     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1621     REQUIRE_VECTOR(ctx);
1622
1623     t0 = tcg_temp_new_i64();
1624     t1 = tcg_temp_new_i64();
1625
1626     get_avr64(t0, a->vra, true);
1627     get_avr64(t1, a->vra, false);
1628
1629     if (a->sh != 0) {
1630         t2 = tcg_temp_new_i64();
1631
1632         get_avr64(t2, a->vrb, true);
1633
1634         tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
1635         tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
1636
1637         tcg_temp_free_i64(t2);
1638     }
1639
1640     set_avr64(a->vrt, t0, true);
1641     set_avr64(a->vrt, t1, false);
1642
1643     tcg_temp_free_i64(t0);
1644     tcg_temp_free_i64(t1);
1645
1646     return true;
1647 }
1648
1649 static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
1650 {
1651     TCGv_i64 t2, t1, t0;
1652
1653     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1654     REQUIRE_VECTOR(ctx);
1655
1656     t0 = tcg_temp_new_i64();
1657     t1 = tcg_temp_new_i64();
1658
1659     get_avr64(t0, a->vrb, false);
1660     get_avr64(t1, a->vrb, true);
1661
1662     if (a->sh != 0) {
1663         t2 = tcg_temp_new_i64();
1664
1665         get_avr64(t2, a->vra, false);
1666
1667         tcg_gen_extract2_i64(t0, t0, t1, a->sh);
1668         tcg_gen_extract2_i64(t1, t1, t2, a->sh);
1669
1670         tcg_temp_free_i64(t2);
1671     }
1672
1673     set_avr64(a->vrt, t0, false);
1674     set_avr64(a->vrt, t1, true);
1675
1676     tcg_temp_free_i64(t0);
1677     tcg_temp_free_i64(t1);
1678
1679     return true;
1680 }
1681
1682 static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1683 {
1684     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1685     REQUIRE_VECTOR(ctx);
1686
1687     tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
1688                       (8 << vece) - 1, 16, 16);
1689
1690     return true;
1691 }
1692
1693 TRANS(VEXPANDBM, do_vexpand, MO_8)
1694 TRANS(VEXPANDHM, do_vexpand, MO_16)
1695 TRANS(VEXPANDWM, do_vexpand, MO_32)
1696 TRANS(VEXPANDDM, do_vexpand, MO_64)
1697
1698 static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
1699 {
1700     TCGv_i64 tmp;
1701
1702     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1703     REQUIRE_VECTOR(ctx);
1704
1705     tmp = tcg_temp_new_i64();
1706
1707     get_avr64(tmp, a->vrb, true);
1708     tcg_gen_sari_i64(tmp, tmp, 63);
1709     set_avr64(a->vrt, tmp, false);
1710     set_avr64(a->vrt, tmp, true);
1711
1712     tcg_temp_free_i64(tmp);
1713     return true;
1714 }
1715
1716 static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1717 {
1718     const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
1719                    mask = dup_const(vece, 1 << (elem_width - 1));
1720     uint64_t i, j;
1721     TCGv_i64 lo, hi, t0, t1;
1722
1723     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1724     REQUIRE_VECTOR(ctx);
1725
1726     hi = tcg_temp_new_i64();
1727     lo = tcg_temp_new_i64();
1728     t0 = tcg_temp_new_i64();
1729     t1 = tcg_temp_new_i64();
1730
1731     get_avr64(lo, a->vrb, false);
1732     get_avr64(hi, a->vrb, true);
1733
1734     tcg_gen_andi_i64(lo, lo, mask);
1735     tcg_gen_andi_i64(hi, hi, mask);
1736
1737     /*
1738      * Gather the most significant bit of each element in the highest element
1739      * element. E.g. for bytes:
1740      * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
1741      *     & dup(1 << (elem_width - 1))
1742      * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
1743      *     << 32 - 4
1744      * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
1745      *     |
1746      * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
1747      *     << 16 - 2
1748      * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
1749      *     |
1750      * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
1751      *     << 8 - 1
1752      * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
1753      *     |
1754      * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
1755      */
1756     for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
1757         tcg_gen_shli_i64(t0, hi, j - i);
1758         tcg_gen_shli_i64(t1, lo, j - i);
1759         tcg_gen_or_i64(hi, hi, t0);
1760         tcg_gen_or_i64(lo, lo, t1);
1761     }
1762
1763     tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
1764     tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
1765     tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
1766
1767     tcg_temp_free_i64(hi);
1768     tcg_temp_free_i64(lo);
1769     tcg_temp_free_i64(t0);
1770     tcg_temp_free_i64(t1);
1771
1772     return true;
1773 }
1774
1775 TRANS(VEXTRACTBM, do_vextractm, MO_8)
1776 TRANS(VEXTRACTHM, do_vextractm, MO_16)
1777 TRANS(VEXTRACTWM, do_vextractm, MO_32)
1778 TRANS(VEXTRACTDM, do_vextractm, MO_64)
1779
1780 static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
1781 {
1782     TCGv_i64 tmp;
1783
1784     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1785     REQUIRE_VECTOR(ctx);
1786
1787     tmp = tcg_temp_new_i64();
1788
1789     get_avr64(tmp, a->vrb, true);
1790     tcg_gen_shri_i64(tmp, tmp, 63);
1791     tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
1792
1793     tcg_temp_free_i64(tmp);
1794
1795     return true;
1796 }
1797
1798 static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1799 {
1800     const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece;
1801     uint64_t c;
1802     int i, j;
1803     TCGv_i64 hi, lo, t0, t1;
1804
1805     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1806     REQUIRE_VECTOR(ctx);
1807
1808     hi = tcg_temp_new_i64();
1809     lo = tcg_temp_new_i64();
1810     t0 = tcg_temp_new_i64();
1811     t1 = tcg_temp_new_i64();
1812
1813     tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]);
1814     tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half);
1815     tcg_gen_extract_i64(lo, t0, 0, elem_count_half);
1816
1817     /*
1818      * Spread the bits into their respective elements.
1819      * E.g. for bytes:
1820      * 00000000000000000000000000000000000000000000000000000000abcdefgh
1821      *   << 32 - 4
1822      * 0000000000000000000000000000abcdefgh0000000000000000000000000000
1823      *   |
1824      * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh
1825      *   << 16 - 2
1826      * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000
1827      *   |
1828      * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh
1829      *   << 8 - 1
1830      * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000
1831      *   |
1832      * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh
1833      *   & dup(1)
1834      * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
1835      *   * 0xff
1836      * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
1837      */
1838     for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
1839         tcg_gen_shli_i64(t0, hi, j - i);
1840         tcg_gen_shli_i64(t1, lo, j - i);
1841         tcg_gen_or_i64(hi, hi, t0);
1842         tcg_gen_or_i64(lo, lo, t1);
1843     }
1844
1845     c = dup_const(vece, 1);
1846     tcg_gen_andi_i64(hi, hi, c);
1847     tcg_gen_andi_i64(lo, lo, c);
1848
1849     c = MAKE_64BIT_MASK(0, elem_width);
1850     tcg_gen_muli_i64(hi, hi, c);
1851     tcg_gen_muli_i64(lo, lo, c);
1852
1853     set_avr64(a->vrt, lo, false);
1854     set_avr64(a->vrt, hi, true);
1855
1856     tcg_temp_free_i64(hi);
1857     tcg_temp_free_i64(lo);
1858     tcg_temp_free_i64(t0);
1859     tcg_temp_free_i64(t1);
1860
1861     return true;
1862 }
1863
1864 TRANS(MTVSRBM, do_mtvsrm, MO_8)
1865 TRANS(MTVSRHM, do_mtvsrm, MO_16)
1866 TRANS(MTVSRWM, do_mtvsrm, MO_32)
1867 TRANS(MTVSRDM, do_mtvsrm, MO_64)
1868
1869 static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a)
1870 {
1871     TCGv_i64 tmp;
1872
1873     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1874     REQUIRE_VECTOR(ctx);
1875
1876     tmp = tcg_temp_new_i64();
1877
1878     tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]);
1879     tcg_gen_sextract_i64(tmp, tmp, 0, 1);
1880     set_avr64(a->vrt, tmp, false);
1881     set_avr64(a->vrt, tmp, true);
1882
1883     tcg_temp_free_i64(tmp);
1884
1885     return true;
1886 }
1887
1888 static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
1889 {
1890     const uint64_t mask = dup_const(MO_8, 1);
1891     uint64_t hi, lo;
1892
1893     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1894     REQUIRE_VECTOR(ctx);
1895
1896     hi = extract16(a->b, 8, 8);
1897     lo = extract16(a->b, 0, 8);
1898
1899     for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) {
1900         hi |= hi << (j - i);
1901         lo |= lo << (j - i);
1902     }
1903
1904     hi = (hi & mask) * 0xFF;
1905     lo = (lo & mask) * 0xFF;
1906
1907     set_avr64(a->vrt, tcg_constant_i64(hi), true);
1908     set_avr64(a->vrt, tcg_constant_i64(lo), false);
1909
1910     return true;
1911 }
1912
1913 static bool do_vstri(DisasContext *ctx, arg_VX_tb_rc *a,
1914                      void (*gen_helper)(TCGv_i32, TCGv_ptr, TCGv_ptr))
1915 {
1916     TCGv_ptr vrt, vrb;
1917
1918     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1919     REQUIRE_VECTOR(ctx);
1920
1921     vrt = gen_avr_ptr(a->vrt);
1922     vrb = gen_avr_ptr(a->vrb);
1923
1924     if (a->rc) {
1925         gen_helper(cpu_crf[6], vrt, vrb);
1926     } else {
1927         TCGv_i32 discard = tcg_temp_new_i32();
1928         gen_helper(discard, vrt, vrb);
1929         tcg_temp_free_i32(discard);
1930     }
1931
1932     tcg_temp_free_ptr(vrt);
1933     tcg_temp_free_ptr(vrb);
1934
1935     return true;
1936 }
1937
1938 TRANS(VSTRIBL, do_vstri, gen_helper_VSTRIBL)
1939 TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
1940 TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
1941 TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
1942
1943 #define GEN_VAFORM_PAIRED(name0, name1, opc2)                           \
1944 static void glue(gen_, name0##_##name1)(DisasContext *ctx)              \
1945     {                                                                   \
1946         TCGv_ptr ra, rb, rc, rd;                                        \
1947         if (unlikely(!ctx->altivec_enabled)) {                          \
1948             gen_exception(ctx, POWERPC_EXCP_VPU);                       \
1949             return;                                                     \
1950         }                                                               \
1951         ra = gen_avr_ptr(rA(ctx->opcode));                              \
1952         rb = gen_avr_ptr(rB(ctx->opcode));                              \
1953         rc = gen_avr_ptr(rC(ctx->opcode));                              \
1954         rd = gen_avr_ptr(rD(ctx->opcode));                              \
1955         if (Rc(ctx->opcode)) {                                          \
1956             gen_helper_##name1(cpu_env, rd, ra, rb, rc);                \
1957         } else {                                                        \
1958             gen_helper_##name0(cpu_env, rd, ra, rb, rc);                \
1959         }                                                               \
1960         tcg_temp_free_ptr(ra);                                          \
1961         tcg_temp_free_ptr(rb);                                          \
1962         tcg_temp_free_ptr(rc);                                          \
1963         tcg_temp_free_ptr(rd);                                          \
1964     }
1965
1966 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
1967
1968 static void gen_vmladduhm(DisasContext *ctx)
1969 {
1970     TCGv_ptr ra, rb, rc, rd;
1971     if (unlikely(!ctx->altivec_enabled)) {
1972         gen_exception(ctx, POWERPC_EXCP_VPU);
1973         return;
1974     }
1975     ra = gen_avr_ptr(rA(ctx->opcode));
1976     rb = gen_avr_ptr(rB(ctx->opcode));
1977     rc = gen_avr_ptr(rC(ctx->opcode));
1978     rd = gen_avr_ptr(rD(ctx->opcode));
1979     gen_helper_vmladduhm(rd, ra, rb, rc);
1980     tcg_temp_free_ptr(ra);
1981     tcg_temp_free_ptr(rb);
1982     tcg_temp_free_ptr(rc);
1983     tcg_temp_free_ptr(rd);
1984 }
1985
1986 static void gen_vpermr(DisasContext *ctx)
1987 {
1988     TCGv_ptr ra, rb, rc, rd;
1989     if (unlikely(!ctx->altivec_enabled)) {
1990         gen_exception(ctx, POWERPC_EXCP_VPU);
1991         return;
1992     }
1993     ra = gen_avr_ptr(rA(ctx->opcode));
1994     rb = gen_avr_ptr(rB(ctx->opcode));
1995     rc = gen_avr_ptr(rC(ctx->opcode));
1996     rd = gen_avr_ptr(rD(ctx->opcode));
1997     gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
1998     tcg_temp_free_ptr(ra);
1999     tcg_temp_free_ptr(rb);
2000     tcg_temp_free_ptr(rc);
2001     tcg_temp_free_ptr(rd);
2002 }
2003
2004 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
2005 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
2006 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
2007 GEN_VAFORM_PAIRED(vsel, vperm, 21)
2008 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
2009
2010 GEN_VXFORM_NOA(vclzb, 1, 28)
2011 GEN_VXFORM_NOA(vclzh, 1, 29)
2012 GEN_VXFORM_TRANS(vclzw, 1, 30)
2013 GEN_VXFORM_TRANS(vclzd, 1, 31)
2014 GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
2015 GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
2016
2017 static void gen_vexts_i64(TCGv_i64 t, TCGv_i64 b, int64_t s)
2018 {
2019     tcg_gen_sextract_i64(t, b, 0, 64 - s);
2020 }
2021
2022 static void gen_vexts_i32(TCGv_i32 t, TCGv_i32 b, int32_t s)
2023 {
2024     tcg_gen_sextract_i32(t, b, 0, 32 - s);
2025 }
2026
2027 static void gen_vexts_vec(unsigned vece, TCGv_vec t, TCGv_vec b, int64_t s)
2028 {
2029     tcg_gen_shli_vec(vece, t, b, s);
2030     tcg_gen_sari_vec(vece, t, t, s);
2031 }
2032
2033 static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, unsigned vece, int64_t s)
2034 {
2035     static const TCGOpcode vecop_list[] = {
2036         INDEX_op_shli_vec, INDEX_op_sari_vec, 0
2037     };
2038
2039     static const GVecGen2i op[2] = {
2040         {
2041             .fni4 = gen_vexts_i32,
2042             .fniv = gen_vexts_vec,
2043             .opt_opc = vecop_list,
2044             .vece = MO_32
2045         },
2046         {
2047             .fni8 = gen_vexts_i64,
2048             .fniv = gen_vexts_vec,
2049             .opt_opc = vecop_list,
2050             .vece = MO_64
2051         },
2052     };
2053
2054     REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2055     REQUIRE_VECTOR(ctx);
2056
2057     tcg_gen_gvec_2i(avr_full_offset(a->vrt), avr_full_offset(a->vrb),
2058                     16, 16, s, &op[vece - MO_32]);
2059
2060     return true;
2061 }
2062
2063 TRANS(VEXTSB2W, do_vexts, MO_32, 24);
2064 TRANS(VEXTSH2W, do_vexts, MO_32, 16);
2065 TRANS(VEXTSB2D, do_vexts, MO_64, 56);
2066 TRANS(VEXTSH2D, do_vexts, MO_64, 48);
2067 TRANS(VEXTSW2D, do_vexts, MO_64, 32);
2068
2069 static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
2070 {
2071     TCGv_i64 tmp;
2072
2073     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2074     REQUIRE_VECTOR(ctx);
2075
2076     tmp = tcg_temp_new_i64();
2077
2078     get_avr64(tmp, a->vrb, false);
2079     set_avr64(a->vrt, tmp, false);
2080     tcg_gen_sari_i64(tmp, tmp, 63);
2081     set_avr64(a->vrt, tmp, true);
2082
2083     tcg_temp_free_i64(tmp);
2084     return true;
2085 }
2086
2087 GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
2088 GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
2089 GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
2090 GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
2091 GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
2092 GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
2093 GEN_VXFORM_NOA(vpopcntb, 1, 28)
2094 GEN_VXFORM_NOA(vpopcnth, 1, 29)
2095 GEN_VXFORM_NOA(vpopcntw, 1, 30)
2096 GEN_VXFORM_NOA(vpopcntd, 1, 31)
2097 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
2098                 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
2099 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
2100                 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
2101 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
2102                 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
2103 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
2104                 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
2105 GEN_VXFORM(vbpermd, 6, 23);
2106 GEN_VXFORM(vbpermq, 6, 21);
2107 GEN_VXFORM_TRANS(vgbbd, 6, 20);
2108 GEN_VXFORM(vpmsumb, 4, 16)
2109 GEN_VXFORM(vpmsumh, 4, 17)
2110 GEN_VXFORM(vpmsumw, 4, 18)
2111 GEN_VXFORM(vpmsumd, 4, 19)
2112
2113 #define GEN_BCD(op)                                 \
2114 static void gen_##op(DisasContext *ctx)             \
2115 {                                                   \
2116     TCGv_ptr ra, rb, rd;                            \
2117     TCGv_i32 ps;                                    \
2118                                                     \
2119     if (unlikely(!ctx->altivec_enabled)) {          \
2120         gen_exception(ctx, POWERPC_EXCP_VPU);       \
2121         return;                                     \
2122     }                                               \
2123                                                     \
2124     ra = gen_avr_ptr(rA(ctx->opcode));              \
2125     rb = gen_avr_ptr(rB(ctx->opcode));              \
2126     rd = gen_avr_ptr(rD(ctx->opcode));              \
2127                                                     \
2128     ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2129                                                     \
2130     gen_helper_##op(cpu_crf[6], rd, ra, rb, ps);    \
2131                                                     \
2132     tcg_temp_free_ptr(ra);                          \
2133     tcg_temp_free_ptr(rb);                          \
2134     tcg_temp_free_ptr(rd);                          \
2135     tcg_temp_free_i32(ps);                          \
2136 }
2137
2138 #define GEN_BCD2(op)                                \
2139 static void gen_##op(DisasContext *ctx)             \
2140 {                                                   \
2141     TCGv_ptr rd, rb;                                \
2142     TCGv_i32 ps;                                    \
2143                                                     \
2144     if (unlikely(!ctx->altivec_enabled)) {          \
2145         gen_exception(ctx, POWERPC_EXCP_VPU);       \
2146         return;                                     \
2147     }                                               \
2148                                                     \
2149     rb = gen_avr_ptr(rB(ctx->opcode));              \
2150     rd = gen_avr_ptr(rD(ctx->opcode));              \
2151                                                     \
2152     ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2153                                                     \
2154     gen_helper_##op(cpu_crf[6], rd, rb, ps);        \
2155                                                     \
2156     tcg_temp_free_ptr(rb);                          \
2157     tcg_temp_free_ptr(rd);                          \
2158     tcg_temp_free_i32(ps);                          \
2159 }
2160
2161 GEN_BCD(bcdadd)
2162 GEN_BCD(bcdsub)
2163 GEN_BCD2(bcdcfn)
2164 GEN_BCD2(bcdctn)
2165 GEN_BCD2(bcdcfz)
2166 GEN_BCD2(bcdctz)
2167 GEN_BCD2(bcdcfsq)
2168 GEN_BCD2(bcdctsq)
2169 GEN_BCD2(bcdsetsgn)
2170 GEN_BCD(bcdcpsgn);
2171 GEN_BCD(bcds);
2172 GEN_BCD(bcdus);
2173 GEN_BCD(bcdsr);
2174 GEN_BCD(bcdtrunc);
2175 GEN_BCD(bcdutrunc);
2176
2177 static void gen_xpnd04_1(DisasContext *ctx)
2178 {
2179     switch (opc4(ctx->opcode)) {
2180     case 0:
2181         gen_bcdctsq(ctx);
2182         break;
2183     case 2:
2184         gen_bcdcfsq(ctx);
2185         break;
2186     case 4:
2187         gen_bcdctz(ctx);
2188         break;
2189     case 5:
2190         gen_bcdctn(ctx);
2191         break;
2192     case 6:
2193         gen_bcdcfz(ctx);
2194         break;
2195     case 7:
2196         gen_bcdcfn(ctx);
2197         break;
2198     case 31:
2199         gen_bcdsetsgn(ctx);
2200         break;
2201     default:
2202         gen_invalid(ctx);
2203         break;
2204     }
2205 }
2206
2207 static void gen_xpnd04_2(DisasContext *ctx)
2208 {
2209     switch (opc4(ctx->opcode)) {
2210     case 0:
2211         gen_bcdctsq(ctx);
2212         break;
2213     case 2:
2214         gen_bcdcfsq(ctx);
2215         break;
2216     case 4:
2217         gen_bcdctz(ctx);
2218         break;
2219     case 6:
2220         gen_bcdcfz(ctx);
2221         break;
2222     case 7:
2223         gen_bcdcfn(ctx);
2224         break;
2225     case 31:
2226         gen_bcdsetsgn(ctx);
2227         break;
2228     default:
2229         gen_invalid(ctx);
2230         break;
2231     }
2232 }
2233
2234
2235 GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
2236                 xpnd04_1, PPC_NONE, PPC2_ISA300)
2237 GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
2238                 xpnd04_2, PPC_NONE, PPC2_ISA300)
2239
2240 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
2241                 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2242 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
2243                 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2244 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
2245                 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2246 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
2247                 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2248 GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
2249                 bcdcpsgn, PPC_NONE, PPC2_ISA300)
2250 GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
2251                 bcds, PPC_NONE, PPC2_ISA300)
2252 GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
2253                 bcdus, PPC_NONE, PPC2_ISA300)
2254 GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
2255                 bcdtrunc, PPC_NONE, PPC2_ISA300)
2256 GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
2257                 bcdtrunc, PPC_NONE, PPC2_ISA300)
2258 GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
2259                 bcdutrunc, PPC_NONE, PPC2_ISA300)
2260
2261
2262 static void gen_vsbox(DisasContext *ctx)
2263 {
2264     TCGv_ptr ra, rd;
2265     if (unlikely(!ctx->altivec_enabled)) {
2266         gen_exception(ctx, POWERPC_EXCP_VPU);
2267         return;
2268     }
2269     ra = gen_avr_ptr(rA(ctx->opcode));
2270     rd = gen_avr_ptr(rD(ctx->opcode));
2271     gen_helper_vsbox(rd, ra);
2272     tcg_temp_free_ptr(ra);
2273     tcg_temp_free_ptr(rd);
2274 }
2275
2276 GEN_VXFORM(vcipher, 4, 20)
2277 GEN_VXFORM(vcipherlast, 4, 20)
2278 GEN_VXFORM(vncipher, 4, 21)
2279 GEN_VXFORM(vncipherlast, 4, 21)
2280
2281 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
2282                 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2283 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
2284                 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2285
2286 #define VSHASIGMA(op)                         \
2287 static void gen_##op(DisasContext *ctx)       \
2288 {                                             \
2289     TCGv_ptr ra, rd;                          \
2290     TCGv_i32 st_six;                          \
2291     if (unlikely(!ctx->altivec_enabled)) {    \
2292         gen_exception(ctx, POWERPC_EXCP_VPU); \
2293         return;                               \
2294     }                                         \
2295     ra = gen_avr_ptr(rA(ctx->opcode));        \
2296     rd = gen_avr_ptr(rD(ctx->opcode));        \
2297     st_six = tcg_const_i32(rB(ctx->opcode));  \
2298     gen_helper_##op(rd, ra, st_six);          \
2299     tcg_temp_free_ptr(ra);                    \
2300     tcg_temp_free_ptr(rd);                    \
2301     tcg_temp_free_i32(st_six);                \
2302 }
2303
2304 VSHASIGMA(vshasigmaw)
2305 VSHASIGMA(vshasigmad)
2306
2307 GEN_VXFORM3(vpermxor, 22, 0xFF)
2308 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
2309                 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
2310
2311 static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
2312 {
2313     static const GVecGen3 g = {
2314         .fni8 = gen_helper_CFUGED,
2315         .vece = MO_64,
2316     };
2317
2318     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2319     REQUIRE_VECTOR(ctx);
2320
2321     tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2322                    avr_full_offset(a->vrb), 16, 16, &g);
2323
2324     return true;
2325 }
2326
2327 static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
2328 {
2329     static const GVecGen3i g = {
2330         .fni8 = do_cntzdm,
2331         .vece = MO_64,
2332     };
2333
2334     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2335     REQUIRE_VECTOR(ctx);
2336
2337     tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2338                     avr_full_offset(a->vrb), 16, 16, false, &g);
2339
2340     return true;
2341 }
2342
2343 static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
2344 {
2345     static const GVecGen3i g = {
2346         .fni8 = do_cntzdm,
2347         .vece = MO_64,
2348     };
2349
2350     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2351     REQUIRE_VECTOR(ctx);
2352
2353     tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2354                     avr_full_offset(a->vrb), 16, 16, true, &g);
2355
2356     return true;
2357 }
2358
2359 static bool trans_VPDEPD(DisasContext *ctx, arg_VX *a)
2360 {
2361     static const GVecGen3 g = {
2362         .fni8 = gen_helper_PDEPD,
2363         .vece = MO_64,
2364     };
2365
2366     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2367     REQUIRE_VECTOR(ctx);
2368
2369     tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2370                    avr_full_offset(a->vrb), 16, 16, &g);
2371
2372     return true;
2373 }
2374
2375 static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
2376 {
2377     static const GVecGen3 g = {
2378         .fni8 = gen_helper_PEXTD,
2379         .vece = MO_64,
2380     };
2381
2382     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2383     REQUIRE_VECTOR(ctx);
2384
2385     tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2386                    avr_full_offset(a->vrb), 16, 16, &g);
2387
2388     return true;
2389 }
2390
2391 static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA *a)
2392 {
2393     TCGv_i64 rl, rh, src1, src2;
2394     int dw;
2395
2396     REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2397     REQUIRE_VECTOR(ctx);
2398
2399     rh = tcg_temp_new_i64();
2400     rl = tcg_temp_new_i64();
2401     src1 = tcg_temp_new_i64();
2402     src2 = tcg_temp_new_i64();
2403
2404     get_avr64(rl, a->rc, false);
2405     get_avr64(rh, a->rc, true);
2406
2407     for (dw = 0; dw < 2; dw++) {
2408         get_avr64(src1, a->vra, dw);
2409         get_avr64(src2, a->vrb, dw);
2410         tcg_gen_mulu2_i64(src1, src2, src1, src2);
2411         tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
2412     }
2413
2414     set_avr64(a->vrt, rl, false);
2415     set_avr64(a->vrt, rh, true);
2416
2417     tcg_temp_free_i64(rl);
2418     tcg_temp_free_i64(rh);
2419     tcg_temp_free_i64(src1);
2420     tcg_temp_free_i64(src2);
2421
2422     return true;
2423 }
2424
2425 static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
2426 {
2427     TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
2428
2429     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2430     REQUIRE_VECTOR(ctx);
2431
2432     tmp0 = tcg_temp_new_i64();
2433     tmp1 = tcg_temp_new_i64();
2434     prod1h = tcg_temp_new_i64();
2435     prod1l = tcg_temp_new_i64();
2436     prod0h = tcg_temp_new_i64();
2437     prod0l = tcg_temp_new_i64();
2438     zero = tcg_constant_i64(0);
2439
2440     /* prod1 = vsr[vra+32].dw[1] * vsr[vrb+32].dw[1] */
2441     get_avr64(tmp0, a->vra, false);
2442     get_avr64(tmp1, a->vrb, false);
2443     tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
2444
2445     /* prod0 = vsr[vra+32].dw[0] * vsr[vrb+32].dw[0] */
2446     get_avr64(tmp0, a->vra, true);
2447     get_avr64(tmp1, a->vrb, true);
2448     tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
2449
2450     /* Sum lower 64-bits elements */
2451     get_avr64(tmp1, a->rc, false);
2452     tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
2453     tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
2454
2455     /*
2456      * Discard lower 64-bits, leaving the carry into bit 64.
2457      * Then sum the higher 64-bit elements.
2458      */
2459     get_avr64(tmp1, a->rc, true);
2460     tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero);
2461     tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero);
2462     tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0h, zero);
2463
2464     /* Discard 64 more bits to complete the CHOP128(temp >> 128) */
2465     set_avr64(a->vrt, tmp0, false);
2466     set_avr64(a->vrt, zero, true);
2467
2468     tcg_temp_free_i64(tmp0);
2469     tcg_temp_free_i64(tmp1);
2470     tcg_temp_free_i64(prod1h);
2471     tcg_temp_free_i64(prod1l);
2472     tcg_temp_free_i64(prod0h);
2473     tcg_temp_free_i64(prod0l);
2474
2475     return true;
2476 }
2477
2478 static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
2479                          void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
2480 {
2481     TCGv_ptr ra, rb, rd;
2482     REQUIRE_VECTOR(ctx);
2483
2484     ra = gen_avr_ptr(a->vra);
2485     rb = gen_avr_ptr(a->vrb);
2486     rd = gen_avr_ptr(a->vrt);
2487     gen_helper(rd, ra, rb);
2488     tcg_temp_free_ptr(ra);
2489     tcg_temp_free_ptr(rb);
2490     tcg_temp_free_ptr(rd);
2491
2492     return true;
2493 }
2494
2495 static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
2496                          void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
2497 {
2498     TCGv_i64 vra, vrb, vrt0, vrt1;
2499     REQUIRE_VECTOR(ctx);
2500
2501     vra = tcg_temp_new_i64();
2502     vrb = tcg_temp_new_i64();
2503     vrt0 = tcg_temp_new_i64();
2504     vrt1 = tcg_temp_new_i64();
2505
2506     get_avr64(vra, a->vra, even);
2507     get_avr64(vrb, a->vrb, even);
2508     gen_mul(vrt0, vrt1, vra, vrb);
2509     set_avr64(a->vrt, vrt0, false);
2510     set_avr64(a->vrt, vrt1, true);
2511
2512     tcg_temp_free_i64(vra);
2513     tcg_temp_free_i64(vrb);
2514     tcg_temp_free_i64(vrt0);
2515     tcg_temp_free_i64(vrt1);
2516
2517     return true;
2518 }
2519
2520 static bool trans_VMULLD(DisasContext *ctx, arg_VX *a)
2521 {
2522     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2523     REQUIRE_VECTOR(ctx);
2524
2525     tcg_gen_gvec_mul(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->vra),
2526                      avr_full_offset(a->vrb), 16, 16);
2527
2528     return true;
2529 }
2530
2531 TRANS_FLAGS2(ALTIVEC_207, VMULESB, do_vx_helper, gen_helper_VMULESB)
2532 TRANS_FLAGS2(ALTIVEC_207, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
2533 TRANS_FLAGS2(ALTIVEC_207, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
2534 TRANS_FLAGS2(ALTIVEC_207, VMULOUB, do_vx_helper, gen_helper_VMULOUB)
2535 TRANS_FLAGS2(ALTIVEC_207, VMULESH, do_vx_helper, gen_helper_VMULESH)
2536 TRANS_FLAGS2(ALTIVEC_207, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
2537 TRANS_FLAGS2(ALTIVEC_207, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
2538 TRANS_FLAGS2(ALTIVEC_207, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
2539 TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
2540 TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
2541 TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
2542 TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
2543 TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
2544 TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
2545 TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
2546 TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
2547
2548 static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2549 {
2550     TCGv_i64 hh, lh, temp;
2551
2552     uint64_t c;
2553     hh = tcg_temp_new_i64();
2554     lh = tcg_temp_new_i64();
2555     temp = tcg_temp_new_i64();
2556
2557     c = 0xFFFFFFFF;
2558
2559     if (sign) {
2560         tcg_gen_ext32s_i64(lh, a);
2561         tcg_gen_ext32s_i64(temp, b);
2562     } else {
2563         tcg_gen_andi_i64(lh, a, c);
2564         tcg_gen_andi_i64(temp, b, c);
2565     }
2566     tcg_gen_mul_i64(lh, lh, temp);
2567
2568     if (sign) {
2569         tcg_gen_sari_i64(hh, a, 32);
2570         tcg_gen_sari_i64(temp, b, 32);
2571     } else {
2572         tcg_gen_shri_i64(hh, a, 32);
2573         tcg_gen_shri_i64(temp, b, 32);
2574     }
2575     tcg_gen_mul_i64(hh, hh, temp);
2576
2577     tcg_gen_shri_i64(lh, lh, 32);
2578     tcg_gen_andi_i64(hh, hh, c << 32);
2579     tcg_gen_or_i64(t, hh, lh);
2580
2581     tcg_temp_free_i64(hh);
2582     tcg_temp_free_i64(lh);
2583     tcg_temp_free_i64(temp);
2584 }
2585
2586 static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2587 {
2588     TCGv_i64 tlow;
2589
2590     tlow  = tcg_temp_new_i64();
2591     if (sign) {
2592         tcg_gen_muls2_i64(tlow, t, a, b);
2593     } else {
2594         tcg_gen_mulu2_i64(tlow, t, a, b);
2595     }
2596
2597     tcg_temp_free_i64(tlow);
2598 }
2599
2600 static bool do_vx_mulh(DisasContext *ctx, arg_VX *a, bool sign,
2601                        void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, bool))
2602 {
2603     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2604     REQUIRE_VECTOR(ctx);
2605
2606     TCGv_i64 vra, vrb, vrt;
2607     int i;
2608
2609     vra = tcg_temp_new_i64();
2610     vrb = tcg_temp_new_i64();
2611     vrt = tcg_temp_new_i64();
2612
2613     for (i = 0; i < 2; i++) {
2614         get_avr64(vra, a->vra, i);
2615         get_avr64(vrb, a->vrb, i);
2616         get_avr64(vrt, a->vrt, i);
2617
2618         func(vrt, vra, vrb, sign);
2619
2620         set_avr64(a->vrt, vrt, i);
2621     }
2622
2623     tcg_temp_free_i64(vra);
2624     tcg_temp_free_i64(vrb);
2625     tcg_temp_free_i64(vrt);
2626
2627     return true;
2628
2629 }
2630
2631 TRANS(VMULHSW, do_vx_mulh, true , do_vx_vmulhw_i64)
2632 TRANS(VMULHSD, do_vx_mulh, true , do_vx_vmulhd_i64)
2633 TRANS(VMULHUW, do_vx_mulh, false, do_vx_vmulhw_i64)
2634 TRANS(VMULHUD, do_vx_mulh, false, do_vx_vmulhd_i64)
2635
2636 #undef GEN_VR_LDX
2637 #undef GEN_VR_STX
2638 #undef GEN_VR_LVE
2639 #undef GEN_VR_STVE
2640
2641 #undef GEN_VX_LOGICAL
2642 #undef GEN_VX_LOGICAL_207
2643 #undef GEN_VXFORM
2644 #undef GEN_VXFORM_207
2645 #undef GEN_VXFORM_DUAL
2646 #undef GEN_VXRFORM_DUAL
2647 #undef GEN_VXRFORM1
2648 #undef GEN_VXRFORM
2649 #undef GEN_VXFORM_VSPLTI
2650 #undef GEN_VXFORM_NOA
2651 #undef GEN_VXFORM_UIMM
2652 #undef GEN_VAFORM_PAIRED
2653
2654 #undef GEN_BCD2