6 static void save_tc(QEMUFile
*f
, TCState
*tc
)
11 for(i
= 0; i
< 32; i
++)
12 qemu_put_betls(f
, &tc
->gpr
[i
]);
13 qemu_put_betls(f
, &tc
->PC
);
14 for(i
= 0; i
< MIPS_DSP_ACC
; i
++)
15 qemu_put_betls(f
, &tc
->HI
[i
]);
16 for(i
= 0; i
< MIPS_DSP_ACC
; i
++)
17 qemu_put_betls(f
, &tc
->LO
[i
]);
18 for(i
= 0; i
< MIPS_DSP_ACC
; i
++)
19 qemu_put_betls(f
, &tc
->ACX
[i
]);
20 qemu_put_betls(f
, &tc
->DSPControl
);
21 qemu_put_sbe32s(f
, &tc
->CP0_TCStatus
);
22 qemu_put_sbe32s(f
, &tc
->CP0_TCBind
);
23 qemu_put_betls(f
, &tc
->CP0_TCHalt
);
24 qemu_put_betls(f
, &tc
->CP0_TCContext
);
25 qemu_put_betls(f
, &tc
->CP0_TCSchedule
);
26 qemu_put_betls(f
, &tc
->CP0_TCScheFBack
);
27 qemu_put_sbe32s(f
, &tc
->CP0_Debug_tcstatus
);
28 qemu_put_betls(f
, &tc
->CP0_UserLocal
);
31 static void save_fpu(QEMUFile
*f
, CPUMIPSFPUContext
*fpu
)
35 for(i
= 0; i
< 32; i
++)
36 qemu_put_be64s(f
, &fpu
->fpr
[i
].d
);
37 qemu_put_s8s(f
, &fpu
->fp_status
.float_detect_tininess
);
38 qemu_put_s8s(f
, &fpu
->fp_status
.float_rounding_mode
);
39 qemu_put_s8s(f
, &fpu
->fp_status
.float_exception_flags
);
40 qemu_put_be32s(f
, &fpu
->fcr0
);
41 qemu_put_be32s(f
, &fpu
->fcr31
);
44 void cpu_save(QEMUFile
*f
, void *opaque
)
46 CPUMIPSState
*env
= opaque
;
50 save_tc(f
, &env
->active_tc
);
53 save_fpu(f
, &env
->active_fpu
);
56 qemu_put_sbe32s(f
, &env
->mvp
->CP0_MVPControl
);
57 qemu_put_sbe32s(f
, &env
->mvp
->CP0_MVPConf0
);
58 qemu_put_sbe32s(f
, &env
->mvp
->CP0_MVPConf1
);
61 qemu_put_be32s(f
, &env
->tlb
->nb_tlb
);
62 qemu_put_be32s(f
, &env
->tlb
->tlb_in_use
);
63 for(i
= 0; i
< MIPS_TLB_MAX
; i
++) {
64 uint16_t flags
= ((env
->tlb
->mmu
.r4k
.tlb
[i
].G
<< 10) |
65 (env
->tlb
->mmu
.r4k
.tlb
[i
].C0
<< 7) |
66 (env
->tlb
->mmu
.r4k
.tlb
[i
].C1
<< 4) |
67 (env
->tlb
->mmu
.r4k
.tlb
[i
].V0
<< 3) |
68 (env
->tlb
->mmu
.r4k
.tlb
[i
].V1
<< 2) |
69 (env
->tlb
->mmu
.r4k
.tlb
[i
].D0
<< 1) |
70 (env
->tlb
->mmu
.r4k
.tlb
[i
].D1
<< 0));
73 qemu_put_betls(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].VPN
);
74 qemu_put_be32s(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].PageMask
);
75 asid
= env
->tlb
->mmu
.r4k
.tlb
[i
].ASID
;
76 qemu_put_8s(f
, &asid
);
77 qemu_put_be16s(f
, &flags
);
78 qemu_put_betls(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].PFN
[0]);
79 qemu_put_betls(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].PFN
[1]);
82 /* Save CPU metastate */
83 qemu_put_be32s(f
, &env
->current_tc
);
84 qemu_put_be32s(f
, &env
->current_fpu
);
85 qemu_put_sbe32s(f
, &env
->error_code
);
86 qemu_put_be32s(f
, &env
->hflags
);
87 qemu_put_betls(f
, &env
->btarget
);
89 qemu_put_sbe32s(f
, &i
);
91 /* Save remaining CP1 registers */
92 qemu_put_sbe32s(f
, &env
->CP0_Index
);
93 qemu_put_sbe32s(f
, &env
->CP0_Random
);
94 qemu_put_sbe32s(f
, &env
->CP0_VPEControl
);
95 qemu_put_sbe32s(f
, &env
->CP0_VPEConf0
);
96 qemu_put_sbe32s(f
, &env
->CP0_VPEConf1
);
97 qemu_put_betls(f
, &env
->CP0_YQMask
);
98 qemu_put_betls(f
, &env
->CP0_VPESchedule
);
99 qemu_put_betls(f
, &env
->CP0_VPEScheFBack
);
100 qemu_put_sbe32s(f
, &env
->CP0_VPEOpt
);
101 qemu_put_betls(f
, &env
->CP0_EntryLo0
);
102 qemu_put_betls(f
, &env
->CP0_EntryLo1
);
103 qemu_put_betls(f
, &env
->CP0_Context
);
104 qemu_put_sbe32s(f
, &env
->CP0_PageMask
);
105 qemu_put_sbe32s(f
, &env
->CP0_PageGrain
);
106 qemu_put_sbe32s(f
, &env
->CP0_Wired
);
107 qemu_put_sbe32s(f
, &env
->CP0_SRSConf0
);
108 qemu_put_sbe32s(f
, &env
->CP0_SRSConf1
);
109 qemu_put_sbe32s(f
, &env
->CP0_SRSConf2
);
110 qemu_put_sbe32s(f
, &env
->CP0_SRSConf3
);
111 qemu_put_sbe32s(f
, &env
->CP0_SRSConf4
);
112 qemu_put_sbe32s(f
, &env
->CP0_HWREna
);
113 qemu_put_betls(f
, &env
->CP0_BadVAddr
);
114 qemu_put_sbe32s(f
, &env
->CP0_Count
);
115 qemu_put_betls(f
, &env
->CP0_EntryHi
);
116 qemu_put_sbe32s(f
, &env
->CP0_Compare
);
117 qemu_put_sbe32s(f
, &env
->CP0_Status
);
118 qemu_put_sbe32s(f
, &env
->CP0_IntCtl
);
119 qemu_put_sbe32s(f
, &env
->CP0_SRSCtl
);
120 qemu_put_sbe32s(f
, &env
->CP0_SRSMap
);
121 qemu_put_sbe32s(f
, &env
->CP0_Cause
);
122 qemu_put_betls(f
, &env
->CP0_EPC
);
123 qemu_put_sbe32s(f
, &env
->CP0_PRid
);
124 qemu_put_sbe32s(f
, &env
->CP0_EBase
);
125 qemu_put_sbe32s(f
, &env
->CP0_Config0
);
126 qemu_put_sbe32s(f
, &env
->CP0_Config1
);
127 qemu_put_sbe32s(f
, &env
->CP0_Config2
);
128 qemu_put_sbe32s(f
, &env
->CP0_Config3
);
129 qemu_put_sbe32s(f
, &env
->CP0_Config6
);
130 qemu_put_sbe32s(f
, &env
->CP0_Config7
);
131 qemu_put_betls(f
, &env
->lladdr
);
132 for(i
= 0; i
< 8; i
++)
133 qemu_put_betls(f
, &env
->CP0_WatchLo
[i
]);
134 for(i
= 0; i
< 8; i
++)
135 qemu_put_sbe32s(f
, &env
->CP0_WatchHi
[i
]);
136 qemu_put_betls(f
, &env
->CP0_XContext
);
137 qemu_put_sbe32s(f
, &env
->CP0_Framemask
);
138 qemu_put_sbe32s(f
, &env
->CP0_Debug
);
139 qemu_put_betls(f
, &env
->CP0_DEPC
);
140 qemu_put_sbe32s(f
, &env
->CP0_Performance0
);
141 qemu_put_sbe32s(f
, &env
->CP0_TagLo
);
142 qemu_put_sbe32s(f
, &env
->CP0_DataLo
);
143 qemu_put_sbe32s(f
, &env
->CP0_TagHi
);
144 qemu_put_sbe32s(f
, &env
->CP0_DataHi
);
145 qemu_put_betls(f
, &env
->CP0_ErrorEPC
);
146 qemu_put_sbe32s(f
, &env
->CP0_DESAVE
);
148 /* Save inactive TC state */
149 for (i
= 0; i
< MIPS_SHADOW_SET_MAX
; i
++)
150 save_tc(f
, &env
->tcs
[i
]);
151 for (i
= 0; i
< MIPS_FPU_MAX
; i
++)
152 save_fpu(f
, &env
->fpus
[i
]);
155 static void load_tc(QEMUFile
*f
, TCState
*tc
, int version_id
)
160 for(i
= 0; i
< 32; i
++)
161 qemu_get_betls(f
, &tc
->gpr
[i
]);
162 qemu_get_betls(f
, &tc
->PC
);
163 for(i
= 0; i
< MIPS_DSP_ACC
; i
++)
164 qemu_get_betls(f
, &tc
->HI
[i
]);
165 for(i
= 0; i
< MIPS_DSP_ACC
; i
++)
166 qemu_get_betls(f
, &tc
->LO
[i
]);
167 for(i
= 0; i
< MIPS_DSP_ACC
; i
++)
168 qemu_get_betls(f
, &tc
->ACX
[i
]);
169 qemu_get_betls(f
, &tc
->DSPControl
);
170 qemu_get_sbe32s(f
, &tc
->CP0_TCStatus
);
171 qemu_get_sbe32s(f
, &tc
->CP0_TCBind
);
172 qemu_get_betls(f
, &tc
->CP0_TCHalt
);
173 qemu_get_betls(f
, &tc
->CP0_TCContext
);
174 qemu_get_betls(f
, &tc
->CP0_TCSchedule
);
175 qemu_get_betls(f
, &tc
->CP0_TCScheFBack
);
176 qemu_get_sbe32s(f
, &tc
->CP0_Debug_tcstatus
);
177 if (version_id
>= 4) {
178 qemu_get_betls(f
, &tc
->CP0_UserLocal
);
182 static void load_fpu(QEMUFile
*f
, CPUMIPSFPUContext
*fpu
)
186 for(i
= 0; i
< 32; i
++)
187 qemu_get_be64s(f
, &fpu
->fpr
[i
].d
);
188 qemu_get_s8s(f
, &fpu
->fp_status
.float_detect_tininess
);
189 qemu_get_s8s(f
, &fpu
->fp_status
.float_rounding_mode
);
190 qemu_get_s8s(f
, &fpu
->fp_status
.float_exception_flags
);
191 qemu_get_be32s(f
, &fpu
->fcr0
);
192 qemu_get_be32s(f
, &fpu
->fcr31
);
195 int cpu_load(QEMUFile
*f
, void *opaque
, int version_id
)
197 CPUMIPSState
*env
= opaque
;
198 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
201 if (version_id
< 3) {
206 load_tc(f
, &env
->active_tc
, version_id
);
208 /* Load active FPU */
209 load_fpu(f
, &env
->active_fpu
);
212 qemu_get_sbe32s(f
, &env
->mvp
->CP0_MVPControl
);
213 qemu_get_sbe32s(f
, &env
->mvp
->CP0_MVPConf0
);
214 qemu_get_sbe32s(f
, &env
->mvp
->CP0_MVPConf1
);
217 qemu_get_be32s(f
, &env
->tlb
->nb_tlb
);
218 qemu_get_be32s(f
, &env
->tlb
->tlb_in_use
);
219 for(i
= 0; i
< MIPS_TLB_MAX
; i
++) {
223 qemu_get_betls(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].VPN
);
224 qemu_get_be32s(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].PageMask
);
225 qemu_get_8s(f
, &asid
);
226 env
->tlb
->mmu
.r4k
.tlb
[i
].ASID
= asid
;
227 qemu_get_be16s(f
, &flags
);
228 env
->tlb
->mmu
.r4k
.tlb
[i
].G
= (flags
>> 10) & 1;
229 env
->tlb
->mmu
.r4k
.tlb
[i
].C0
= (flags
>> 7) & 3;
230 env
->tlb
->mmu
.r4k
.tlb
[i
].C1
= (flags
>> 4) & 3;
231 env
->tlb
->mmu
.r4k
.tlb
[i
].V0
= (flags
>> 3) & 1;
232 env
->tlb
->mmu
.r4k
.tlb
[i
].V1
= (flags
>> 2) & 1;
233 env
->tlb
->mmu
.r4k
.tlb
[i
].D0
= (flags
>> 1) & 1;
234 env
->tlb
->mmu
.r4k
.tlb
[i
].D1
= (flags
>> 0) & 1;
235 qemu_get_betls(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].PFN
[0]);
236 qemu_get_betls(f
, &env
->tlb
->mmu
.r4k
.tlb
[i
].PFN
[1]);
239 /* Load CPU metastate */
240 qemu_get_be32s(f
, &env
->current_tc
);
241 qemu_get_be32s(f
, &env
->current_fpu
);
242 qemu_get_sbe32s(f
, &env
->error_code
);
243 qemu_get_be32s(f
, &env
->hflags
);
244 qemu_get_betls(f
, &env
->btarget
);
245 qemu_get_sbe32s(f
, &i
);
248 /* Load remaining CP1 registers */
249 qemu_get_sbe32s(f
, &env
->CP0_Index
);
250 qemu_get_sbe32s(f
, &env
->CP0_Random
);
251 qemu_get_sbe32s(f
, &env
->CP0_VPEControl
);
252 qemu_get_sbe32s(f
, &env
->CP0_VPEConf0
);
253 qemu_get_sbe32s(f
, &env
->CP0_VPEConf1
);
254 qemu_get_betls(f
, &env
->CP0_YQMask
);
255 qemu_get_betls(f
, &env
->CP0_VPESchedule
);
256 qemu_get_betls(f
, &env
->CP0_VPEScheFBack
);
257 qemu_get_sbe32s(f
, &env
->CP0_VPEOpt
);
258 qemu_get_betls(f
, &env
->CP0_EntryLo0
);
259 qemu_get_betls(f
, &env
->CP0_EntryLo1
);
260 qemu_get_betls(f
, &env
->CP0_Context
);
261 qemu_get_sbe32s(f
, &env
->CP0_PageMask
);
262 qemu_get_sbe32s(f
, &env
->CP0_PageGrain
);
263 qemu_get_sbe32s(f
, &env
->CP0_Wired
);
264 qemu_get_sbe32s(f
, &env
->CP0_SRSConf0
);
265 qemu_get_sbe32s(f
, &env
->CP0_SRSConf1
);
266 qemu_get_sbe32s(f
, &env
->CP0_SRSConf2
);
267 qemu_get_sbe32s(f
, &env
->CP0_SRSConf3
);
268 qemu_get_sbe32s(f
, &env
->CP0_SRSConf4
);
269 qemu_get_sbe32s(f
, &env
->CP0_HWREna
);
270 qemu_get_betls(f
, &env
->CP0_BadVAddr
);
271 qemu_get_sbe32s(f
, &env
->CP0_Count
);
272 qemu_get_betls(f
, &env
->CP0_EntryHi
);
273 qemu_get_sbe32s(f
, &env
->CP0_Compare
);
274 qemu_get_sbe32s(f
, &env
->CP0_Status
);
275 qemu_get_sbe32s(f
, &env
->CP0_IntCtl
);
276 qemu_get_sbe32s(f
, &env
->CP0_SRSCtl
);
277 qemu_get_sbe32s(f
, &env
->CP0_SRSMap
);
278 qemu_get_sbe32s(f
, &env
->CP0_Cause
);
279 qemu_get_betls(f
, &env
->CP0_EPC
);
280 qemu_get_sbe32s(f
, &env
->CP0_PRid
);
281 qemu_get_sbe32s(f
, &env
->CP0_EBase
);
282 qemu_get_sbe32s(f
, &env
->CP0_Config0
);
283 qemu_get_sbe32s(f
, &env
->CP0_Config1
);
284 qemu_get_sbe32s(f
, &env
->CP0_Config2
);
285 qemu_get_sbe32s(f
, &env
->CP0_Config3
);
286 qemu_get_sbe32s(f
, &env
->CP0_Config6
);
287 qemu_get_sbe32s(f
, &env
->CP0_Config7
);
288 qemu_get_betls(f
, &env
->lladdr
);
289 for(i
= 0; i
< 8; i
++)
290 qemu_get_betls(f
, &env
->CP0_WatchLo
[i
]);
291 for(i
= 0; i
< 8; i
++)
292 qemu_get_sbe32s(f
, &env
->CP0_WatchHi
[i
]);
293 qemu_get_betls(f
, &env
->CP0_XContext
);
294 qemu_get_sbe32s(f
, &env
->CP0_Framemask
);
295 qemu_get_sbe32s(f
, &env
->CP0_Debug
);
296 qemu_get_betls(f
, &env
->CP0_DEPC
);
297 qemu_get_sbe32s(f
, &env
->CP0_Performance0
);
298 qemu_get_sbe32s(f
, &env
->CP0_TagLo
);
299 qemu_get_sbe32s(f
, &env
->CP0_DataLo
);
300 qemu_get_sbe32s(f
, &env
->CP0_TagHi
);
301 qemu_get_sbe32s(f
, &env
->CP0_DataHi
);
302 qemu_get_betls(f
, &env
->CP0_ErrorEPC
);
303 qemu_get_sbe32s(f
, &env
->CP0_DESAVE
);
305 /* Load inactive TC state */
306 for (i
= 0; i
< MIPS_SHADOW_SET_MAX
; i
++) {
307 load_tc(f
, &env
->tcs
[i
], version_id
);
309 for (i
= 0; i
< MIPS_FPU_MAX
; i
++)
310 load_fpu(f
, &env
->fpus
[i
]);
312 /* XXX: ensure compatibility for halted bit ? */
313 tlb_flush(CPU(cpu
), 1);