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target-ppc: add xxspltib instruction
[qemu/rayw.git] / target-ppc / translate.c
blob133c53133c825b4ffecd90fa78b8cbafba19d9db
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->nip - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->nip - 4);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->nip);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 typedef struct opcode_t {
380 unsigned char opc1, opc2, opc3, opc4;
381 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
382 unsigned char pad[4];
383 #endif
384 opc_handler_t handler;
385 const char *oname;
386 } opcode_t;
387
388 /* Helpers for priv. check */
389 #define GEN_PRIV \
390 do { \
391 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
392 } while (0)
393
394 #if defined(CONFIG_USER_ONLY)
395 #define CHK_HV GEN_PRIV
396 #define CHK_SV GEN_PRIV
397 #define CHK_HVRM GEN_PRIV
398 #else
399 #define CHK_HV \
400 do { \
401 if (unlikely(ctx->pr || !ctx->hv)) { \
402 GEN_PRIV; \
403 } \
404 } while (0)
405 #define CHK_SV \
406 do { \
407 if (unlikely(ctx->pr)) { \
408 GEN_PRIV; \
409 } \
410 } while (0)
411 #define CHK_HVRM \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #endif
418
419 #define CHK_NONE
420
421
422 /*****************************************************************************/
423 /*** Instruction decoding ***/
424 #define EXTRACT_HELPER(name, shift, nb) \
425 static inline uint32_t name(uint32_t opcode) \
426 { \
427 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
428 }
429
430 #define EXTRACT_SHELPER(name, shift, nb) \
431 static inline int32_t name(uint32_t opcode) \
432 { \
433 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
437 static inline uint32_t name(uint32_t opcode) \
438 { \
439 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
440 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
441 }
442
443 #define EXTRACT_HELPER_DXFORM(name, \
444 d0_bits, shift_op_d0, shift_d0, \
445 d1_bits, shift_op_d1, shift_d1, \
446 d2_bits, shift_op_d2, shift_d2) \
447 static inline int16_t name(uint32_t opcode) \
448 { \
449 return \
450 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
451 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
452 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
453 }
454
455
456 /* Opcode part 1 */
457 EXTRACT_HELPER(opc1, 26, 6);
458 /* Opcode part 2 */
459 EXTRACT_HELPER(opc2, 1, 5);
460 /* Opcode part 3 */
461 EXTRACT_HELPER(opc3, 6, 5);
462 /* Opcode part 4 */
463 EXTRACT_HELPER(opc4, 16, 5);
464 /* Update Cr0 flags */
465 EXTRACT_HELPER(Rc, 0, 1);
466 /* Update Cr6 flags (Altivec) */
467 EXTRACT_HELPER(Rc21, 10, 1);
468 /* Destination */
469 EXTRACT_HELPER(rD, 21, 5);
470 /* Source */
471 EXTRACT_HELPER(rS, 21, 5);
472 /* First operand */
473 EXTRACT_HELPER(rA, 16, 5);
474 /* Second operand */
475 EXTRACT_HELPER(rB, 11, 5);
476 /* Third operand */
477 EXTRACT_HELPER(rC, 6, 5);
478 /*** Get CRn ***/
479 EXTRACT_HELPER(crfD, 23, 3);
480 EXTRACT_HELPER(crfS, 18, 3);
481 EXTRACT_HELPER(crbD, 21, 5);
482 EXTRACT_HELPER(crbA, 16, 5);
483 EXTRACT_HELPER(crbB, 11, 5);
484 /* SPR / TBL */
485 EXTRACT_HELPER(_SPR, 11, 10);
486 static inline uint32_t SPR(uint32_t opcode)
487 {
488 uint32_t sprn = _SPR(opcode);
489
490 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
491 }
492 /*** Get constants ***/
493 /* 16 bits signed immediate value */
494 EXTRACT_SHELPER(SIMM, 0, 16);
495 /* 16 bits unsigned immediate value */
496 EXTRACT_HELPER(UIMM, 0, 16);
497 /* 5 bits signed immediate value */
498 EXTRACT_HELPER(SIMM5, 16, 5);
499 /* 5 bits signed immediate value */
500 EXTRACT_HELPER(UIMM5, 16, 5);
501 /* 4 bits unsigned immediate value */
502 EXTRACT_HELPER(UIMM4, 16, 4);
503 /* Bit count */
504 EXTRACT_HELPER(NB, 11, 5);
505 /* Shift count */
506 EXTRACT_HELPER(SH, 11, 5);
507 /* Vector shift count */
508 EXTRACT_HELPER(VSH, 6, 4);
509 /* Mask start */
510 EXTRACT_HELPER(MB, 6, 5);
511 /* Mask end */
512 EXTRACT_HELPER(ME, 1, 5);
513 /* Trap operand */
514 EXTRACT_HELPER(TO, 21, 5);
515
516 EXTRACT_HELPER(CRM, 12, 8);
517
518 #ifndef CONFIG_USER_ONLY
519 EXTRACT_HELPER(SR, 16, 4);
520 #endif
521
522 /* mtfsf/mtfsfi */
523 EXTRACT_HELPER(FPBF, 23, 3);
524 EXTRACT_HELPER(FPIMM, 12, 4);
525 EXTRACT_HELPER(FPL, 25, 1);
526 EXTRACT_HELPER(FPFLM, 17, 8);
527 EXTRACT_HELPER(FPW, 16, 1);
528
529 /* addpcis */
530 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
531
532 /*** Jump target decoding ***/
533 /* Immediate address */
534 static inline target_ulong LI(uint32_t opcode)
535 {
536 return (opcode >> 0) & 0x03FFFFFC;
537 }
538
539 static inline uint32_t BD(uint32_t opcode)
540 {
541 return (opcode >> 0) & 0xFFFC;
542 }
543
544 EXTRACT_HELPER(BO, 21, 5);
545 EXTRACT_HELPER(BI, 16, 5);
546 /* Absolute/relative address */
547 EXTRACT_HELPER(AA, 1, 1);
548 /* Link */
549 EXTRACT_HELPER(LK, 0, 1);
550
551 /* DFP Z22-form */
552 EXTRACT_HELPER(DCM, 10, 6)
553
554 /* DFP Z23-form */
555 EXTRACT_HELPER(RMC, 9, 2)
556
557 /* Create a mask between <start> and <end> bits */
558 static inline target_ulong MASK(uint32_t start, uint32_t end)
559 {
560 target_ulong ret;
561
562 #if defined(TARGET_PPC64)
563 if (likely(start == 0)) {
564 ret = UINT64_MAX << (63 - end);
565 } else if (likely(end == 63)) {
566 ret = UINT64_MAX >> start;
567 }
568 #else
569 if (likely(start == 0)) {
570 ret = UINT32_MAX << (31 - end);
571 } else if (likely(end == 31)) {
572 ret = UINT32_MAX >> start;
573 }
574 #endif
575 else {
576 ret = (((target_ulong)(-1ULL)) >> (start)) ^
577 (((target_ulong)(-1ULL) >> (end)) >> 1);
578 if (unlikely(start > end))
579 return ~ret;
580 }
581
582 return ret;
583 }
584
585 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
586 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
587 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
588 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
589 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
590 EXTRACT_HELPER(DM, 8, 2);
591 EXTRACT_HELPER(UIM, 16, 2);
592 EXTRACT_HELPER(SHW, 8, 2);
593 EXTRACT_HELPER(SP, 19, 2);
594 EXTRACT_HELPER(IMM8, 11, 8);
595
596 /*****************************************************************************/
597 /* PowerPC instructions table */
598
599 #if defined(DO_PPC_STATISTICS)
600 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
601 { \
602 .opc1 = op1, \
603 .opc2 = op2, \
604 .opc3 = op3, \
605 .opc4 = 0xff, \
606 .handler = { \
607 .inval1 = invl, \
608 .type = _typ, \
609 .type2 = _typ2, \
610 .handler = &gen_##name, \
611 .oname = stringify(name), \
612 }, \
613 .oname = stringify(name), \
614 }
615 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
616 { \
617 .opc1 = op1, \
618 .opc2 = op2, \
619 .opc3 = op3, \
620 .opc4 = 0xff, \
621 .handler = { \
622 .inval1 = invl1, \
623 .inval2 = invl2, \
624 .type = _typ, \
625 .type2 = _typ2, \
626 .handler = &gen_##name, \
627 .oname = stringify(name), \
628 }, \
629 .oname = stringify(name), \
630 }
631 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
632 { \
633 .opc1 = op1, \
634 .opc2 = op2, \
635 .opc3 = op3, \
636 .opc4 = 0xff, \
637 .handler = { \
638 .inval1 = invl, \
639 .type = _typ, \
640 .type2 = _typ2, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645 }
646 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
647 { \
648 .opc1 = op1, \
649 .opc2 = op2, \
650 .opc3 = op3, \
651 .opc4 = op4, \
652 .handler = { \
653 .inval1 = invl, \
654 .type = _typ, \
655 .type2 = _typ2, \
656 .handler = &gen_##name, \
657 .oname = stringify(name), \
658 }, \
659 .oname = stringify(name), \
660 }
661 #else
662 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
663 { \
664 .opc1 = op1, \
665 .opc2 = op2, \
666 .opc3 = op3, \
667 .opc4 = 0xff, \
668 .handler = { \
669 .inval1 = invl, \
670 .type = _typ, \
671 .type2 = _typ2, \
672 .handler = &gen_##name, \
673 }, \
674 .oname = stringify(name), \
675 }
676 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
677 { \
678 .opc1 = op1, \
679 .opc2 = op2, \
680 .opc3 = op3, \
681 .opc4 = 0xff, \
682 .handler = { \
683 .inval1 = invl1, \
684 .inval2 = invl2, \
685 .type = _typ, \
686 .type2 = _typ2, \
687 .handler = &gen_##name, \
688 }, \
689 .oname = stringify(name), \
690 }
691 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
692 { \
693 .opc1 = op1, \
694 .opc2 = op2, \
695 .opc3 = op3, \
696 .opc4 = 0xff, \
697 .handler = { \
698 .inval1 = invl, \
699 .type = _typ, \
700 .type2 = _typ2, \
701 .handler = &gen_##name, \
702 }, \
703 .oname = onam, \
704 }
705 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
706 { \
707 .opc1 = op1, \
708 .opc2 = op2, \
709 .opc3 = op3, \
710 .opc4 = op4, \
711 .handler = { \
712 .inval1 = invl, \
713 .type = _typ, \
714 .type2 = _typ2, \
715 .handler = &gen_##name, \
716 }, \
717 .oname = stringify(name), \
718 }
719 #endif
720
721 /* SPR load/store helpers */
722 static inline void gen_load_spr(TCGv t, int reg)
723 {
724 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
725 }
726
727 static inline void gen_store_spr(int reg, TCGv t)
728 {
729 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
730 }
731
732 /* Invalid instruction */
733 static void gen_invalid(DisasContext *ctx)
734 {
735 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
736 }
737
738 static opc_handler_t invalid_handler = {
739 .inval1 = 0xFFFFFFFF,
740 .inval2 = 0xFFFFFFFF,
741 .type = PPC_NONE,
742 .type2 = PPC_NONE,
743 .handler = gen_invalid,
744 };
745
746 /*** Integer comparison ***/
747
748 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
749 {
750 TCGv t0 = tcg_temp_new();
751 TCGv_i32 t1 = tcg_temp_new_i32();
752
753 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
754
755 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
756 tcg_gen_trunc_tl_i32(t1, t0);
757 tcg_gen_shli_i32(t1, t1, CRF_LT);
758 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
759
760 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
761 tcg_gen_trunc_tl_i32(t1, t0);
762 tcg_gen_shli_i32(t1, t1, CRF_GT);
763 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
764
765 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
766 tcg_gen_trunc_tl_i32(t1, t0);
767 tcg_gen_shli_i32(t1, t1, CRF_EQ);
768 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
769
770 tcg_temp_free(t0);
771 tcg_temp_free_i32(t1);
772 }
773
774 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
775 {
776 TCGv t0 = tcg_const_tl(arg1);
777 gen_op_cmp(arg0, t0, s, crf);
778 tcg_temp_free(t0);
779 }
780
781 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
782 {
783 TCGv t0, t1;
784 t0 = tcg_temp_new();
785 t1 = tcg_temp_new();
786 if (s) {
787 tcg_gen_ext32s_tl(t0, arg0);
788 tcg_gen_ext32s_tl(t1, arg1);
789 } else {
790 tcg_gen_ext32u_tl(t0, arg0);
791 tcg_gen_ext32u_tl(t1, arg1);
792 }
793 gen_op_cmp(t0, t1, s, crf);
794 tcg_temp_free(t1);
795 tcg_temp_free(t0);
796 }
797
798 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
799 {
800 TCGv t0 = tcg_const_tl(arg1);
801 gen_op_cmp32(arg0, t0, s, crf);
802 tcg_temp_free(t0);
803 }
804
805 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
806 {
807 if (NARROW_MODE(ctx)) {
808 gen_op_cmpi32(reg, 0, 1, 0);
809 } else {
810 gen_op_cmpi(reg, 0, 1, 0);
811 }
812 }
813
814 /* cmp */
815 static void gen_cmp(DisasContext *ctx)
816 {
817 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
818 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
819 1, crfD(ctx->opcode));
820 } else {
821 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
822 1, crfD(ctx->opcode));
823 }
824 }
825
826 /* cmpi */
827 static void gen_cmpi(DisasContext *ctx)
828 {
829 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
830 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
831 1, crfD(ctx->opcode));
832 } else {
833 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
834 1, crfD(ctx->opcode));
835 }
836 }
837
838 /* cmpl */
839 static void gen_cmpl(DisasContext *ctx)
840 {
841 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
842 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
843 0, crfD(ctx->opcode));
844 } else {
845 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
846 0, crfD(ctx->opcode));
847 }
848 }
849
850 /* cmpli */
851 static void gen_cmpli(DisasContext *ctx)
852 {
853 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
854 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
855 0, crfD(ctx->opcode));
856 } else {
857 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
858 0, crfD(ctx->opcode));
859 }
860 }
861
862 /* cmprb - range comparison: isupper, isaplha, islower*/
863 static void gen_cmprb(DisasContext *ctx)
864 {
865 TCGv_i32 src1 = tcg_temp_new_i32();
866 TCGv_i32 src2 = tcg_temp_new_i32();
867 TCGv_i32 src2lo = tcg_temp_new_i32();
868 TCGv_i32 src2hi = tcg_temp_new_i32();
869 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
870
871 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
872 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
873
874 tcg_gen_andi_i32(src1, src1, 0xFF);
875 tcg_gen_ext8u_i32(src2lo, src2);
876 tcg_gen_shri_i32(src2, src2, 8);
877 tcg_gen_ext8u_i32(src2hi, src2);
878
879 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
880 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
881 tcg_gen_and_i32(crf, src2lo, src2hi);
882
883 if (ctx->opcode & 0x00200000) {
884 tcg_gen_shri_i32(src2, src2, 8);
885 tcg_gen_ext8u_i32(src2lo, src2);
886 tcg_gen_shri_i32(src2, src2, 8);
887 tcg_gen_ext8u_i32(src2hi, src2);
888 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
889 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
890 tcg_gen_and_i32(src2lo, src2lo, src2hi);
891 tcg_gen_or_i32(crf, crf, src2lo);
892 }
893 tcg_gen_shli_i32(crf, crf, CRF_GT);
894 tcg_temp_free_i32(src1);
895 tcg_temp_free_i32(src2);
896 tcg_temp_free_i32(src2lo);
897 tcg_temp_free_i32(src2hi);
898 }
899
900 #if defined(TARGET_PPC64)
901 /* cmpeqb */
902 static void gen_cmpeqb(DisasContext *ctx)
903 {
904 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
905 cpu_gpr[rB(ctx->opcode)]);
906 }
907 #endif
908
909 /* isel (PowerPC 2.03 specification) */
910 static void gen_isel(DisasContext *ctx)
911 {
912 uint32_t bi = rC(ctx->opcode);
913 uint32_t mask = 0x08 >> (bi & 0x03);
914 TCGv t0 = tcg_temp_new();
915 TCGv zr;
916
917 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
918 tcg_gen_andi_tl(t0, t0, mask);
919
920 zr = tcg_const_tl(0);
921 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
922 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
923 cpu_gpr[rB(ctx->opcode)]);
924 tcg_temp_free(zr);
925 tcg_temp_free(t0);
926 }
927
928 /* cmpb: PowerPC 2.05 specification */
929 static void gen_cmpb(DisasContext *ctx)
930 {
931 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
932 cpu_gpr[rB(ctx->opcode)]);
933 }
934
935 /*** Integer arithmetic ***/
936
937 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
938 TCGv arg1, TCGv arg2, int sub)
939 {
940 TCGv t0 = tcg_temp_new();
941
942 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
943 tcg_gen_xor_tl(t0, arg1, arg2);
944 if (sub) {
945 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
946 } else {
947 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
948 }
949 tcg_temp_free(t0);
950 if (NARROW_MODE(ctx)) {
951 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
952 }
953 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
954 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
955 }
956
957 /* Common add function */
958 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
959 TCGv arg2, bool add_ca, bool compute_ca,
960 bool compute_ov, bool compute_rc0)
961 {
962 TCGv t0 = ret;
963
964 if (compute_ca || compute_ov) {
965 t0 = tcg_temp_new();
966 }
967
968 if (compute_ca) {
969 if (NARROW_MODE(ctx)) {
970 /* Caution: a non-obvious corner case of the spec is that we
971 must produce the *entire* 64-bit addition, but produce the
972 carry into bit 32. */
973 TCGv t1 = tcg_temp_new();
974 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
975 tcg_gen_add_tl(t0, arg1, arg2);
976 if (add_ca) {
977 tcg_gen_add_tl(t0, t0, cpu_ca);
978 }
979 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
980 tcg_temp_free(t1);
981 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
982 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
983 } else {
984 TCGv zero = tcg_const_tl(0);
985 if (add_ca) {
986 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
987 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
988 } else {
989 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
990 }
991 tcg_temp_free(zero);
992 }
993 } else {
994 tcg_gen_add_tl(t0, arg1, arg2);
995 if (add_ca) {
996 tcg_gen_add_tl(t0, t0, cpu_ca);
997 }
998 }
999
1000 if (compute_ov) {
1001 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1002 }
1003 if (unlikely(compute_rc0)) {
1004 gen_set_Rc0(ctx, t0);
1005 }
1006
1007 if (!TCGV_EQUAL(t0, ret)) {
1008 tcg_gen_mov_tl(ret, t0);
1009 tcg_temp_free(t0);
1010 }
1011 }
1012 /* Add functions with two operands */
1013 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1014 static void glue(gen_, name)(DisasContext *ctx) \
1015 { \
1016 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1017 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1018 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1019 }
1020 /* Add functions with one operand and one immediate */
1021 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1022 add_ca, compute_ca, compute_ov) \
1023 static void glue(gen_, name)(DisasContext *ctx) \
1024 { \
1025 TCGv t0 = tcg_const_tl(const_val); \
1026 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1027 cpu_gpr[rA(ctx->opcode)], t0, \
1028 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1029 tcg_temp_free(t0); \
1030 }
1031
1032 /* add add. addo addo. */
1033 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1034 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1035 /* addc addc. addco addco. */
1036 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1037 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1038 /* adde adde. addeo addeo. */
1039 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1040 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1041 /* addme addme. addmeo addmeo. */
1042 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1043 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1044 /* addze addze. addzeo addzeo.*/
1045 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1046 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1047 /* addi */
1048 static void gen_addi(DisasContext *ctx)
1049 {
1050 target_long simm = SIMM(ctx->opcode);
1051
1052 if (rA(ctx->opcode) == 0) {
1053 /* li case */
1054 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1055 } else {
1056 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1057 cpu_gpr[rA(ctx->opcode)], simm);
1058 }
1059 }
1060 /* addic addic.*/
1061 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1062 {
1063 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1064 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1065 c, 0, 1, 0, compute_rc0);
1066 tcg_temp_free(c);
1067 }
1068
1069 static void gen_addic(DisasContext *ctx)
1070 {
1071 gen_op_addic(ctx, 0);
1072 }
1073
1074 static void gen_addic_(DisasContext *ctx)
1075 {
1076 gen_op_addic(ctx, 1);
1077 }
1078
1079 /* addis */
1080 static void gen_addis(DisasContext *ctx)
1081 {
1082 target_long simm = SIMM(ctx->opcode);
1083
1084 if (rA(ctx->opcode) == 0) {
1085 /* lis case */
1086 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1087 } else {
1088 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1089 cpu_gpr[rA(ctx->opcode)], simm << 16);
1090 }
1091 }
1092
1093 /* addpcis */
1094 static void gen_addpcis(DisasContext *ctx)
1095 {
1096 target_long d = DX(ctx->opcode);
1097
1098 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1099 }
1100
1101 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1102 TCGv arg2, int sign, int compute_ov)
1103 {
1104 TCGv_i32 t0 = tcg_temp_new_i32();
1105 TCGv_i32 t1 = tcg_temp_new_i32();
1106 TCGv_i32 t2 = tcg_temp_new_i32();
1107 TCGv_i32 t3 = tcg_temp_new_i32();
1108
1109 tcg_gen_trunc_tl_i32(t0, arg1);
1110 tcg_gen_trunc_tl_i32(t1, arg2);
1111 if (sign) {
1112 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1113 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1114 tcg_gen_and_i32(t2, t2, t3);
1115 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1116 tcg_gen_or_i32(t2, t2, t3);
1117 tcg_gen_movi_i32(t3, 0);
1118 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1119 tcg_gen_div_i32(t3, t0, t1);
1120 tcg_gen_extu_i32_tl(ret, t3);
1121 } else {
1122 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1123 tcg_gen_movi_i32(t3, 0);
1124 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1125 tcg_gen_divu_i32(t3, t0, t1);
1126 tcg_gen_extu_i32_tl(ret, t3);
1127 }
1128 if (compute_ov) {
1129 tcg_gen_extu_i32_tl(cpu_ov, t2);
1130 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1131 }
1132 tcg_temp_free_i32(t0);
1133 tcg_temp_free_i32(t1);
1134 tcg_temp_free_i32(t2);
1135 tcg_temp_free_i32(t3);
1136
1137 if (unlikely(Rc(ctx->opcode) != 0))
1138 gen_set_Rc0(ctx, ret);
1139 }
1140 /* Div functions */
1141 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1142 static void glue(gen_, name)(DisasContext *ctx) \
1143 { \
1144 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1145 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1146 sign, compute_ov); \
1147 }
1148 /* divwu divwu. divwuo divwuo. */
1149 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1150 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1151 /* divw divw. divwo divwo. */
1152 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1153 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1154
1155 /* div[wd]eu[o][.] */
1156 #define GEN_DIVE(name, hlpr, compute_ov) \
1157 static void gen_##name(DisasContext *ctx) \
1158 { \
1159 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1160 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1162 tcg_temp_free_i32(t0); \
1163 if (unlikely(Rc(ctx->opcode) != 0)) { \
1164 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1165 } \
1166 }
1167
1168 GEN_DIVE(divweu, divweu, 0);
1169 GEN_DIVE(divweuo, divweu, 1);
1170 GEN_DIVE(divwe, divwe, 0);
1171 GEN_DIVE(divweo, divwe, 1);
1172
1173 #if defined(TARGET_PPC64)
1174 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1175 TCGv arg2, int sign, int compute_ov)
1176 {
1177 TCGv_i64 t0 = tcg_temp_new_i64();
1178 TCGv_i64 t1 = tcg_temp_new_i64();
1179 TCGv_i64 t2 = tcg_temp_new_i64();
1180 TCGv_i64 t3 = tcg_temp_new_i64();
1181
1182 tcg_gen_mov_i64(t0, arg1);
1183 tcg_gen_mov_i64(t1, arg2);
1184 if (sign) {
1185 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1186 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1187 tcg_gen_and_i64(t2, t2, t3);
1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1189 tcg_gen_or_i64(t2, t2, t3);
1190 tcg_gen_movi_i64(t3, 0);
1191 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1192 tcg_gen_div_i64(ret, t0, t1);
1193 } else {
1194 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1195 tcg_gen_movi_i64(t3, 0);
1196 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1197 tcg_gen_divu_i64(ret, t0, t1);
1198 }
1199 if (compute_ov) {
1200 tcg_gen_mov_tl(cpu_ov, t2);
1201 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1202 }
1203 tcg_temp_free_i64(t0);
1204 tcg_temp_free_i64(t1);
1205 tcg_temp_free_i64(t2);
1206 tcg_temp_free_i64(t3);
1207
1208 if (unlikely(Rc(ctx->opcode) != 0))
1209 gen_set_Rc0(ctx, ret);
1210 }
1211
1212 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1213 static void glue(gen_, name)(DisasContext *ctx) \
1214 { \
1215 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1216 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1217 sign, compute_ov); \
1218 }
1219 /* divwu divwu. divwuo divwuo. */
1220 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1221 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1222 /* divw divw. divwo divwo. */
1223 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1224 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1225
1226 GEN_DIVE(divdeu, divdeu, 0);
1227 GEN_DIVE(divdeuo, divdeu, 1);
1228 GEN_DIVE(divde, divde, 0);
1229 GEN_DIVE(divdeo, divde, 1);
1230 #endif
1231
1232 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1233 TCGv arg2, int sign)
1234 {
1235 TCGv_i32 t0 = tcg_temp_new_i32();
1236 TCGv_i32 t1 = tcg_temp_new_i32();
1237
1238 tcg_gen_trunc_tl_i32(t0, arg1);
1239 tcg_gen_trunc_tl_i32(t1, arg2);
1240 if (sign) {
1241 TCGv_i32 t2 = tcg_temp_new_i32();
1242 TCGv_i32 t3 = tcg_temp_new_i32();
1243 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1244 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1245 tcg_gen_and_i32(t2, t2, t3);
1246 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1247 tcg_gen_or_i32(t2, t2, t3);
1248 tcg_gen_movi_i32(t3, 0);
1249 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1250 tcg_gen_rem_i32(t3, t0, t1);
1251 tcg_gen_ext_i32_tl(ret, t3);
1252 tcg_temp_free_i32(t2);
1253 tcg_temp_free_i32(t3);
1254 } else {
1255 TCGv_i32 t2 = tcg_const_i32(1);
1256 TCGv_i32 t3 = tcg_const_i32(0);
1257 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1258 tcg_gen_remu_i32(t3, t0, t1);
1259 tcg_gen_extu_i32_tl(ret, t3);
1260 tcg_temp_free_i32(t2);
1261 tcg_temp_free_i32(t3);
1262 }
1263 tcg_temp_free_i32(t0);
1264 tcg_temp_free_i32(t1);
1265 }
1266
1267 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1268 static void glue(gen_, name)(DisasContext *ctx) \
1269 { \
1270 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1271 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1272 sign); \
1273 }
1274
1275 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1276 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1277
1278 #if defined(TARGET_PPC64)
1279 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1280 TCGv arg2, int sign)
1281 {
1282 TCGv_i64 t0 = tcg_temp_new_i64();
1283 TCGv_i64 t1 = tcg_temp_new_i64();
1284
1285 tcg_gen_mov_i64(t0, arg1);
1286 tcg_gen_mov_i64(t1, arg2);
1287 if (sign) {
1288 TCGv_i64 t2 = tcg_temp_new_i64();
1289 TCGv_i64 t3 = tcg_temp_new_i64();
1290 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1291 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1292 tcg_gen_and_i64(t2, t2, t3);
1293 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1294 tcg_gen_or_i64(t2, t2, t3);
1295 tcg_gen_movi_i64(t3, 0);
1296 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1297 tcg_gen_rem_i64(ret, t0, t1);
1298 tcg_temp_free_i64(t2);
1299 tcg_temp_free_i64(t3);
1300 } else {
1301 TCGv_i64 t2 = tcg_const_i64(1);
1302 TCGv_i64 t3 = tcg_const_i64(0);
1303 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1304 tcg_gen_remu_i64(ret, t0, t1);
1305 tcg_temp_free_i64(t2);
1306 tcg_temp_free_i64(t3);
1307 }
1308 tcg_temp_free_i64(t0);
1309 tcg_temp_free_i64(t1);
1310 }
1311
1312 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1313 static void glue(gen_, name)(DisasContext *ctx) \
1314 { \
1315 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1316 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1317 sign); \
1318 }
1319
1320 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1321 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1322 #endif
1323
1324 /* mulhw mulhw. */
1325 static void gen_mulhw(DisasContext *ctx)
1326 {
1327 TCGv_i32 t0 = tcg_temp_new_i32();
1328 TCGv_i32 t1 = tcg_temp_new_i32();
1329
1330 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1331 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1332 tcg_gen_muls2_i32(t0, t1, t0, t1);
1333 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1334 tcg_temp_free_i32(t0);
1335 tcg_temp_free_i32(t1);
1336 if (unlikely(Rc(ctx->opcode) != 0))
1337 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1338 }
1339
1340 /* mulhwu mulhwu. */
1341 static void gen_mulhwu(DisasContext *ctx)
1342 {
1343 TCGv_i32 t0 = tcg_temp_new_i32();
1344 TCGv_i32 t1 = tcg_temp_new_i32();
1345
1346 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1347 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1348 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1349 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1350 tcg_temp_free_i32(t0);
1351 tcg_temp_free_i32(t1);
1352 if (unlikely(Rc(ctx->opcode) != 0))
1353 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1354 }
1355
1356 /* mullw mullw. */
1357 static void gen_mullw(DisasContext *ctx)
1358 {
1359 #if defined(TARGET_PPC64)
1360 TCGv_i64 t0, t1;
1361 t0 = tcg_temp_new_i64();
1362 t1 = tcg_temp_new_i64();
1363 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1364 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1365 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1366 tcg_temp_free(t0);
1367 tcg_temp_free(t1);
1368 #else
1369 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1370 cpu_gpr[rB(ctx->opcode)]);
1371 #endif
1372 if (unlikely(Rc(ctx->opcode) != 0))
1373 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1374 }
1375
1376 /* mullwo mullwo. */
1377 static void gen_mullwo(DisasContext *ctx)
1378 {
1379 TCGv_i32 t0 = tcg_temp_new_i32();
1380 TCGv_i32 t1 = tcg_temp_new_i32();
1381
1382 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1383 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1384 tcg_gen_muls2_i32(t0, t1, t0, t1);
1385 #if defined(TARGET_PPC64)
1386 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1387 #else
1388 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1389 #endif
1390
1391 tcg_gen_sari_i32(t0, t0, 31);
1392 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1393 tcg_gen_extu_i32_tl(cpu_ov, t0);
1394 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1395
1396 tcg_temp_free_i32(t0);
1397 tcg_temp_free_i32(t1);
1398 if (unlikely(Rc(ctx->opcode) != 0))
1399 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1400 }
1401
1402 /* mulli */
1403 static void gen_mulli(DisasContext *ctx)
1404 {
1405 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1406 SIMM(ctx->opcode));
1407 }
1408
1409 #if defined(TARGET_PPC64)
1410 /* mulhd mulhd. */
1411 static void gen_mulhd(DisasContext *ctx)
1412 {
1413 TCGv lo = tcg_temp_new();
1414 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1415 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1416 tcg_temp_free(lo);
1417 if (unlikely(Rc(ctx->opcode) != 0)) {
1418 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1419 }
1420 }
1421
1422 /* mulhdu mulhdu. */
1423 static void gen_mulhdu(DisasContext *ctx)
1424 {
1425 TCGv lo = tcg_temp_new();
1426 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1427 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1428 tcg_temp_free(lo);
1429 if (unlikely(Rc(ctx->opcode) != 0)) {
1430 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1431 }
1432 }
1433
1434 /* mulld mulld. */
1435 static void gen_mulld(DisasContext *ctx)
1436 {
1437 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1438 cpu_gpr[rB(ctx->opcode)]);
1439 if (unlikely(Rc(ctx->opcode) != 0))
1440 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1441 }
1442
1443 /* mulldo mulldo. */
1444 static void gen_mulldo(DisasContext *ctx)
1445 {
1446 TCGv_i64 t0 = tcg_temp_new_i64();
1447 TCGv_i64 t1 = tcg_temp_new_i64();
1448
1449 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1450 cpu_gpr[rB(ctx->opcode)]);
1451 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1452
1453 tcg_gen_sari_i64(t0, t0, 63);
1454 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1455 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1456
1457 tcg_temp_free_i64(t0);
1458 tcg_temp_free_i64(t1);
1459
1460 if (unlikely(Rc(ctx->opcode) != 0)) {
1461 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1462 }
1463 }
1464 #endif
1465
1466 /* Common subf function */
1467 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1468 TCGv arg2, bool add_ca, bool compute_ca,
1469 bool compute_ov, bool compute_rc0)
1470 {
1471 TCGv t0 = ret;
1472
1473 if (compute_ca || compute_ov) {
1474 t0 = tcg_temp_new();
1475 }
1476
1477 if (compute_ca) {
1478 /* dest = ~arg1 + arg2 [+ ca]. */
1479 if (NARROW_MODE(ctx)) {
1480 /* Caution: a non-obvious corner case of the spec is that we
1481 must produce the *entire* 64-bit addition, but produce the
1482 carry into bit 32. */
1483 TCGv inv1 = tcg_temp_new();
1484 TCGv t1 = tcg_temp_new();
1485 tcg_gen_not_tl(inv1, arg1);
1486 if (add_ca) {
1487 tcg_gen_add_tl(t0, arg2, cpu_ca);
1488 } else {
1489 tcg_gen_addi_tl(t0, arg2, 1);
1490 }
1491 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1492 tcg_gen_add_tl(t0, t0, inv1);
1493 tcg_temp_free(inv1);
1494 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1495 tcg_temp_free(t1);
1496 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1497 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1498 } else if (add_ca) {
1499 TCGv zero, inv1 = tcg_temp_new();
1500 tcg_gen_not_tl(inv1, arg1);
1501 zero = tcg_const_tl(0);
1502 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1503 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1504 tcg_temp_free(zero);
1505 tcg_temp_free(inv1);
1506 } else {
1507 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1508 tcg_gen_sub_tl(t0, arg2, arg1);
1509 }
1510 } else if (add_ca) {
1511 /* Since we're ignoring carry-out, we can simplify the
1512 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1513 tcg_gen_sub_tl(t0, arg2, arg1);
1514 tcg_gen_add_tl(t0, t0, cpu_ca);
1515 tcg_gen_subi_tl(t0, t0, 1);
1516 } else {
1517 tcg_gen_sub_tl(t0, arg2, arg1);
1518 }
1519
1520 if (compute_ov) {
1521 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1522 }
1523 if (unlikely(compute_rc0)) {
1524 gen_set_Rc0(ctx, t0);
1525 }
1526
1527 if (!TCGV_EQUAL(t0, ret)) {
1528 tcg_gen_mov_tl(ret, t0);
1529 tcg_temp_free(t0);
1530 }
1531 }
1532 /* Sub functions with Two operands functions */
1533 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1534 static void glue(gen_, name)(DisasContext *ctx) \
1535 { \
1536 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1537 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1538 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1539 }
1540 /* Sub functions with one operand and one immediate */
1541 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1542 add_ca, compute_ca, compute_ov) \
1543 static void glue(gen_, name)(DisasContext *ctx) \
1544 { \
1545 TCGv t0 = tcg_const_tl(const_val); \
1546 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1547 cpu_gpr[rA(ctx->opcode)], t0, \
1548 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1549 tcg_temp_free(t0); \
1550 }
1551 /* subf subf. subfo subfo. */
1552 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1553 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1554 /* subfc subfc. subfco subfco. */
1555 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1556 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1557 /* subfe subfe. subfeo subfo. */
1558 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1559 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1560 /* subfme subfme. subfmeo subfmeo. */
1561 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1562 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1563 /* subfze subfze. subfzeo subfzeo.*/
1564 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1565 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1566
1567 /* subfic */
1568 static void gen_subfic(DisasContext *ctx)
1569 {
1570 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1571 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1572 c, 0, 1, 0, 0);
1573 tcg_temp_free(c);
1574 }
1575
1576 /* neg neg. nego nego. */
1577 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1578 {
1579 TCGv zero = tcg_const_tl(0);
1580 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1581 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1582 tcg_temp_free(zero);
1583 }
1584
1585 static void gen_neg(DisasContext *ctx)
1586 {
1587 gen_op_arith_neg(ctx, 0);
1588 }
1589
1590 static void gen_nego(DisasContext *ctx)
1591 {
1592 gen_op_arith_neg(ctx, 1);
1593 }
1594
1595 /*** Integer logical ***/
1596 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1597 static void glue(gen_, name)(DisasContext *ctx) \
1598 { \
1599 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1600 cpu_gpr[rB(ctx->opcode)]); \
1601 if (unlikely(Rc(ctx->opcode) != 0)) \
1602 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1603 }
1604
1605 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1606 static void glue(gen_, name)(DisasContext *ctx) \
1607 { \
1608 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1609 if (unlikely(Rc(ctx->opcode) != 0)) \
1610 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1611 }
1612
1613 /* and & and. */
1614 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1615 /* andc & andc. */
1616 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1617
1618 /* andi. */
1619 static void gen_andi_(DisasContext *ctx)
1620 {
1621 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1623 }
1624
1625 /* andis. */
1626 static void gen_andis_(DisasContext *ctx)
1627 {
1628 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1629 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1630 }
1631
1632 /* cntlzw */
1633 static void gen_cntlzw(DisasContext *ctx)
1634 {
1635 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1636 if (unlikely(Rc(ctx->opcode) != 0))
1637 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1638 }
1639
1640 /* cnttzw */
1641 static void gen_cnttzw(DisasContext *ctx)
1642 {
1643 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1644 if (unlikely(Rc(ctx->opcode) != 0)) {
1645 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1646 }
1647 }
1648
1649 /* eqv & eqv. */
1650 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1651 /* extsb & extsb. */
1652 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1653 /* extsh & extsh. */
1654 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1655 /* nand & nand. */
1656 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1657 /* nor & nor. */
1658 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1659
1660 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1661 static void gen_pause(DisasContext *ctx)
1662 {
1663 TCGv_i32 t0 = tcg_const_i32(0);
1664 tcg_gen_st_i32(t0, cpu_env,
1665 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1666 tcg_temp_free_i32(t0);
1667
1668 /* Stop translation, this gives other CPUs a chance to run */
1669 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1670 }
1671 #endif /* defined(TARGET_PPC64) */
1672
1673 /* or & or. */
1674 static void gen_or(DisasContext *ctx)
1675 {
1676 int rs, ra, rb;
1677
1678 rs = rS(ctx->opcode);
1679 ra = rA(ctx->opcode);
1680 rb = rB(ctx->opcode);
1681 /* Optimisation for mr. ri case */
1682 if (rs != ra || rs != rb) {
1683 if (rs != rb)
1684 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1685 else
1686 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1687 if (unlikely(Rc(ctx->opcode) != 0))
1688 gen_set_Rc0(ctx, cpu_gpr[ra]);
1689 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1690 gen_set_Rc0(ctx, cpu_gpr[rs]);
1691 #if defined(TARGET_PPC64)
1692 } else if (rs != 0) { /* 0 is nop */
1693 int prio = 0;
1694
1695 switch (rs) {
1696 case 1:
1697 /* Set process priority to low */
1698 prio = 2;
1699 break;
1700 case 6:
1701 /* Set process priority to medium-low */
1702 prio = 3;
1703 break;
1704 case 2:
1705 /* Set process priority to normal */
1706 prio = 4;
1707 break;
1708 #if !defined(CONFIG_USER_ONLY)
1709 case 31:
1710 if (!ctx->pr) {
1711 /* Set process priority to very low */
1712 prio = 1;
1713 }
1714 break;
1715 case 5:
1716 if (!ctx->pr) {
1717 /* Set process priority to medium-hight */
1718 prio = 5;
1719 }
1720 break;
1721 case 3:
1722 if (!ctx->pr) {
1723 /* Set process priority to high */
1724 prio = 6;
1725 }
1726 break;
1727 case 7:
1728 if (ctx->hv && !ctx->pr) {
1729 /* Set process priority to very high */
1730 prio = 7;
1731 }
1732 break;
1733 #endif
1734 default:
1735 break;
1736 }
1737 if (prio) {
1738 TCGv t0 = tcg_temp_new();
1739 gen_load_spr(t0, SPR_PPR);
1740 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1741 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1742 gen_store_spr(SPR_PPR, t0);
1743 tcg_temp_free(t0);
1744 }
1745 #if !defined(CONFIG_USER_ONLY)
1746 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1747 * CPU and the kernel hangs. This applies to all encodings other
1748 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1749 * and all currently undefined.
1750 */
1751 gen_pause(ctx);
1752 #endif
1753 #endif
1754 }
1755 }
1756 /* orc & orc. */
1757 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1758
1759 /* xor & xor. */
1760 static void gen_xor(DisasContext *ctx)
1761 {
1762 /* Optimisation for "set to zero" case */
1763 if (rS(ctx->opcode) != rB(ctx->opcode))
1764 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1765 else
1766 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1767 if (unlikely(Rc(ctx->opcode) != 0))
1768 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1769 }
1770
1771 /* ori */
1772 static void gen_ori(DisasContext *ctx)
1773 {
1774 target_ulong uimm = UIMM(ctx->opcode);
1775
1776 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1777 return;
1778 }
1779 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1780 }
1781
1782 /* oris */
1783 static void gen_oris(DisasContext *ctx)
1784 {
1785 target_ulong uimm = UIMM(ctx->opcode);
1786
1787 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1788 /* NOP */
1789 return;
1790 }
1791 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1792 }
1793
1794 /* xori */
1795 static void gen_xori(DisasContext *ctx)
1796 {
1797 target_ulong uimm = UIMM(ctx->opcode);
1798
1799 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1800 /* NOP */
1801 return;
1802 }
1803 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1804 }
1805
1806 /* xoris */
1807 static void gen_xoris(DisasContext *ctx)
1808 {
1809 target_ulong uimm = UIMM(ctx->opcode);
1810
1811 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1812 /* NOP */
1813 return;
1814 }
1815 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1816 }
1817
1818 /* popcntb : PowerPC 2.03 specification */
1819 static void gen_popcntb(DisasContext *ctx)
1820 {
1821 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1822 }
1823
1824 static void gen_popcntw(DisasContext *ctx)
1825 {
1826 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1827 }
1828
1829 #if defined(TARGET_PPC64)
1830 /* popcntd: PowerPC 2.06 specification */
1831 static void gen_popcntd(DisasContext *ctx)
1832 {
1833 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1834 }
1835 #endif
1836
1837 /* prtyw: PowerPC 2.05 specification */
1838 static void gen_prtyw(DisasContext *ctx)
1839 {
1840 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1841 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1842 TCGv t0 = tcg_temp_new();
1843 tcg_gen_shri_tl(t0, rs, 16);
1844 tcg_gen_xor_tl(ra, rs, t0);
1845 tcg_gen_shri_tl(t0, ra, 8);
1846 tcg_gen_xor_tl(ra, ra, t0);
1847 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1848 tcg_temp_free(t0);
1849 }
1850
1851 #if defined(TARGET_PPC64)
1852 /* prtyd: PowerPC 2.05 specification */
1853 static void gen_prtyd(DisasContext *ctx)
1854 {
1855 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1856 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1857 TCGv t0 = tcg_temp_new();
1858 tcg_gen_shri_tl(t0, rs, 32);
1859 tcg_gen_xor_tl(ra, rs, t0);
1860 tcg_gen_shri_tl(t0, ra, 16);
1861 tcg_gen_xor_tl(ra, ra, t0);
1862 tcg_gen_shri_tl(t0, ra, 8);
1863 tcg_gen_xor_tl(ra, ra, t0);
1864 tcg_gen_andi_tl(ra, ra, 1);
1865 tcg_temp_free(t0);
1866 }
1867 #endif
1868
1869 #if defined(TARGET_PPC64)
1870 /* bpermd */
1871 static void gen_bpermd(DisasContext *ctx)
1872 {
1873 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1874 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1875 }
1876 #endif
1877
1878 #if defined(TARGET_PPC64)
1879 /* extsw & extsw. */
1880 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1881
1882 /* cntlzd */
1883 static void gen_cntlzd(DisasContext *ctx)
1884 {
1885 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1886 if (unlikely(Rc(ctx->opcode) != 0))
1887 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1888 }
1889
1890 /* cnttzd */
1891 static void gen_cnttzd(DisasContext *ctx)
1892 {
1893 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1894 if (unlikely(Rc(ctx->opcode) != 0)) {
1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1896 }
1897 }
1898 #endif
1899
1900 /*** Integer rotate ***/
1901
1902 /* rlwimi & rlwimi. */
1903 static void gen_rlwimi(DisasContext *ctx)
1904 {
1905 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1906 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1907 uint32_t sh = SH(ctx->opcode);
1908 uint32_t mb = MB(ctx->opcode);
1909 uint32_t me = ME(ctx->opcode);
1910
1911 if (sh == (31-me) && mb <= me) {
1912 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1913 } else {
1914 target_ulong mask;
1915 TCGv t1;
1916
1917 #if defined(TARGET_PPC64)
1918 mb += 32;
1919 me += 32;
1920 #endif
1921 mask = MASK(mb, me);
1922
1923 t1 = tcg_temp_new();
1924 if (mask <= 0xffffffffu) {
1925 TCGv_i32 t0 = tcg_temp_new_i32();
1926 tcg_gen_trunc_tl_i32(t0, t_rs);
1927 tcg_gen_rotli_i32(t0, t0, sh);
1928 tcg_gen_extu_i32_tl(t1, t0);
1929 tcg_temp_free_i32(t0);
1930 } else {
1931 #if defined(TARGET_PPC64)
1932 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1933 tcg_gen_rotli_i64(t1, t1, sh);
1934 #else
1935 g_assert_not_reached();
1936 #endif
1937 }
1938
1939 tcg_gen_andi_tl(t1, t1, mask);
1940 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1941 tcg_gen_or_tl(t_ra, t_ra, t1);
1942 tcg_temp_free(t1);
1943 }
1944 if (unlikely(Rc(ctx->opcode) != 0)) {
1945 gen_set_Rc0(ctx, t_ra);
1946 }
1947 }
1948
1949 /* rlwinm & rlwinm. */
1950 static void gen_rlwinm(DisasContext *ctx)
1951 {
1952 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1953 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1954 uint32_t sh = SH(ctx->opcode);
1955 uint32_t mb = MB(ctx->opcode);
1956 uint32_t me = ME(ctx->opcode);
1957
1958 if (mb == 0 && me == (31 - sh)) {
1959 tcg_gen_shli_tl(t_ra, t_rs, sh);
1960 tcg_gen_ext32u_tl(t_ra, t_ra);
1961 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1962 tcg_gen_ext32u_tl(t_ra, t_rs);
1963 tcg_gen_shri_tl(t_ra, t_ra, mb);
1964 } else {
1965 target_ulong mask;
1966 #if defined(TARGET_PPC64)
1967 mb += 32;
1968 me += 32;
1969 #endif
1970 mask = MASK(mb, me);
1971
1972 if (mask <= 0xffffffffu) {
1973 TCGv_i32 t0 = tcg_temp_new_i32();
1974 tcg_gen_trunc_tl_i32(t0, t_rs);
1975 tcg_gen_rotli_i32(t0, t0, sh);
1976 tcg_gen_andi_i32(t0, t0, mask);
1977 tcg_gen_extu_i32_tl(t_ra, t0);
1978 tcg_temp_free_i32(t0);
1979 } else {
1980 #if defined(TARGET_PPC64)
1981 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1982 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1983 tcg_gen_andi_i64(t_ra, t_ra, mask);
1984 #else
1985 g_assert_not_reached();
1986 #endif
1987 }
1988 }
1989 if (unlikely(Rc(ctx->opcode) != 0)) {
1990 gen_set_Rc0(ctx, t_ra);
1991 }
1992 }
1993
1994 /* rlwnm & rlwnm. */
1995 static void gen_rlwnm(DisasContext *ctx)
1996 {
1997 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1998 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1999 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2000 uint32_t mb = MB(ctx->opcode);
2001 uint32_t me = ME(ctx->opcode);
2002 target_ulong mask;
2003
2004 #if defined(TARGET_PPC64)
2005 mb += 32;
2006 me += 32;
2007 #endif
2008 mask = MASK(mb, me);
2009
2010 if (mask <= 0xffffffffu) {
2011 TCGv_i32 t0 = tcg_temp_new_i32();
2012 TCGv_i32 t1 = tcg_temp_new_i32();
2013 tcg_gen_trunc_tl_i32(t0, t_rb);
2014 tcg_gen_trunc_tl_i32(t1, t_rs);
2015 tcg_gen_andi_i32(t0, t0, 0x1f);
2016 tcg_gen_rotl_i32(t1, t1, t0);
2017 tcg_gen_extu_i32_tl(t_ra, t1);
2018 tcg_temp_free_i32(t0);
2019 tcg_temp_free_i32(t1);
2020 } else {
2021 #if defined(TARGET_PPC64)
2022 TCGv_i64 t0 = tcg_temp_new_i64();
2023 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2024 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2025 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2026 tcg_temp_free_i64(t0);
2027 #else
2028 g_assert_not_reached();
2029 #endif
2030 }
2031
2032 tcg_gen_andi_tl(t_ra, t_ra, mask);
2033
2034 if (unlikely(Rc(ctx->opcode) != 0)) {
2035 gen_set_Rc0(ctx, t_ra);
2036 }
2037 }
2038
2039 #if defined(TARGET_PPC64)
2040 #define GEN_PPC64_R2(name, opc1, opc2) \
2041 static void glue(gen_, name##0)(DisasContext *ctx) \
2042 { \
2043 gen_##name(ctx, 0); \
2044 } \
2045 \
2046 static void glue(gen_, name##1)(DisasContext *ctx) \
2047 { \
2048 gen_##name(ctx, 1); \
2049 }
2050 #define GEN_PPC64_R4(name, opc1, opc2) \
2051 static void glue(gen_, name##0)(DisasContext *ctx) \
2052 { \
2053 gen_##name(ctx, 0, 0); \
2054 } \
2055 \
2056 static void glue(gen_, name##1)(DisasContext *ctx) \
2057 { \
2058 gen_##name(ctx, 0, 1); \
2059 } \
2060 \
2061 static void glue(gen_, name##2)(DisasContext *ctx) \
2062 { \
2063 gen_##name(ctx, 1, 0); \
2064 } \
2065 \
2066 static void glue(gen_, name##3)(DisasContext *ctx) \
2067 { \
2068 gen_##name(ctx, 1, 1); \
2069 }
2070
2071 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2072 {
2073 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2074 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2075
2076 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2077 tcg_gen_shli_tl(t_ra, t_rs, sh);
2078 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2079 tcg_gen_shri_tl(t_ra, t_rs, mb);
2080 } else {
2081 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2082 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2083 }
2084 if (unlikely(Rc(ctx->opcode) != 0)) {
2085 gen_set_Rc0(ctx, t_ra);
2086 }
2087 }
2088
2089 /* rldicl - rldicl. */
2090 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2091 {
2092 uint32_t sh, mb;
2093
2094 sh = SH(ctx->opcode) | (shn << 5);
2095 mb = MB(ctx->opcode) | (mbn << 5);
2096 gen_rldinm(ctx, mb, 63, sh);
2097 }
2098 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2099
2100 /* rldicr - rldicr. */
2101 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2102 {
2103 uint32_t sh, me;
2104
2105 sh = SH(ctx->opcode) | (shn << 5);
2106 me = MB(ctx->opcode) | (men << 5);
2107 gen_rldinm(ctx, 0, me, sh);
2108 }
2109 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2110
2111 /* rldic - rldic. */
2112 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2113 {
2114 uint32_t sh, mb;
2115
2116 sh = SH(ctx->opcode) | (shn << 5);
2117 mb = MB(ctx->opcode) | (mbn << 5);
2118 gen_rldinm(ctx, mb, 63 - sh, sh);
2119 }
2120 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2121
2122 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2123 {
2124 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2125 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2126 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2127 TCGv t0;
2128
2129 t0 = tcg_temp_new();
2130 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2131 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2132 tcg_temp_free(t0);
2133
2134 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2135 if (unlikely(Rc(ctx->opcode) != 0)) {
2136 gen_set_Rc0(ctx, t_ra);
2137 }
2138 }
2139
2140 /* rldcl - rldcl. */
2141 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2142 {
2143 uint32_t mb;
2144
2145 mb = MB(ctx->opcode) | (mbn << 5);
2146 gen_rldnm(ctx, mb, 63);
2147 }
2148 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2149
2150 /* rldcr - rldcr. */
2151 static inline void gen_rldcr(DisasContext *ctx, int men)
2152 {
2153 uint32_t me;
2154
2155 me = MB(ctx->opcode) | (men << 5);
2156 gen_rldnm(ctx, 0, me);
2157 }
2158 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2159
2160 /* rldimi - rldimi. */
2161 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2162 {
2163 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2164 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2165 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2166 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2167 uint32_t me = 63 - sh;
2168
2169 if (mb <= me) {
2170 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2171 } else {
2172 target_ulong mask = MASK(mb, me);
2173 TCGv t1 = tcg_temp_new();
2174
2175 tcg_gen_rotli_tl(t1, t_rs, sh);
2176 tcg_gen_andi_tl(t1, t1, mask);
2177 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2178 tcg_gen_or_tl(t_ra, t_ra, t1);
2179 tcg_temp_free(t1);
2180 }
2181 if (unlikely(Rc(ctx->opcode) != 0)) {
2182 gen_set_Rc0(ctx, t_ra);
2183 }
2184 }
2185 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2186 #endif
2187
2188 /*** Integer shift ***/
2189
2190 /* slw & slw. */
2191 static void gen_slw(DisasContext *ctx)
2192 {
2193 TCGv t0, t1;
2194
2195 t0 = tcg_temp_new();
2196 /* AND rS with a mask that is 0 when rB >= 0x20 */
2197 #if defined(TARGET_PPC64)
2198 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2199 tcg_gen_sari_tl(t0, t0, 0x3f);
2200 #else
2201 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2202 tcg_gen_sari_tl(t0, t0, 0x1f);
2203 #endif
2204 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2205 t1 = tcg_temp_new();
2206 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2207 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2208 tcg_temp_free(t1);
2209 tcg_temp_free(t0);
2210 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2211 if (unlikely(Rc(ctx->opcode) != 0))
2212 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2213 }
2214
2215 /* sraw & sraw. */
2216 static void gen_sraw(DisasContext *ctx)
2217 {
2218 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2219 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2220 if (unlikely(Rc(ctx->opcode) != 0))
2221 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2222 }
2223
2224 /* srawi & srawi. */
2225 static void gen_srawi(DisasContext *ctx)
2226 {
2227 int sh = SH(ctx->opcode);
2228 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2229 TCGv src = cpu_gpr[rS(ctx->opcode)];
2230 if (sh == 0) {
2231 tcg_gen_ext32s_tl(dst, src);
2232 tcg_gen_movi_tl(cpu_ca, 0);
2233 } else {
2234 TCGv t0;
2235 tcg_gen_ext32s_tl(dst, src);
2236 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2237 t0 = tcg_temp_new();
2238 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2239 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2240 tcg_temp_free(t0);
2241 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2242 tcg_gen_sari_tl(dst, dst, sh);
2243 }
2244 if (unlikely(Rc(ctx->opcode) != 0)) {
2245 gen_set_Rc0(ctx, dst);
2246 }
2247 }
2248
2249 /* srw & srw. */
2250 static void gen_srw(DisasContext *ctx)
2251 {
2252 TCGv t0, t1;
2253
2254 t0 = tcg_temp_new();
2255 /* AND rS with a mask that is 0 when rB >= 0x20 */
2256 #if defined(TARGET_PPC64)
2257 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2258 tcg_gen_sari_tl(t0, t0, 0x3f);
2259 #else
2260 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2261 tcg_gen_sari_tl(t0, t0, 0x1f);
2262 #endif
2263 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2264 tcg_gen_ext32u_tl(t0, t0);
2265 t1 = tcg_temp_new();
2266 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2267 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2268 tcg_temp_free(t1);
2269 tcg_temp_free(t0);
2270 if (unlikely(Rc(ctx->opcode) != 0))
2271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2272 }
2273
2274 #if defined(TARGET_PPC64)
2275 /* sld & sld. */
2276 static void gen_sld(DisasContext *ctx)
2277 {
2278 TCGv t0, t1;
2279
2280 t0 = tcg_temp_new();
2281 /* AND rS with a mask that is 0 when rB >= 0x40 */
2282 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2283 tcg_gen_sari_tl(t0, t0, 0x3f);
2284 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2285 t1 = tcg_temp_new();
2286 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2287 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2288 tcg_temp_free(t1);
2289 tcg_temp_free(t0);
2290 if (unlikely(Rc(ctx->opcode) != 0))
2291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2292 }
2293
2294 /* srad & srad. */
2295 static void gen_srad(DisasContext *ctx)
2296 {
2297 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2298 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2299 if (unlikely(Rc(ctx->opcode) != 0))
2300 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2301 }
2302 /* sradi & sradi. */
2303 static inline void gen_sradi(DisasContext *ctx, int n)
2304 {
2305 int sh = SH(ctx->opcode) + (n << 5);
2306 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2307 TCGv src = cpu_gpr[rS(ctx->opcode)];
2308 if (sh == 0) {
2309 tcg_gen_mov_tl(dst, src);
2310 tcg_gen_movi_tl(cpu_ca, 0);
2311 } else {
2312 TCGv t0;
2313 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2314 t0 = tcg_temp_new();
2315 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2316 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2317 tcg_temp_free(t0);
2318 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2319 tcg_gen_sari_tl(dst, src, sh);
2320 }
2321 if (unlikely(Rc(ctx->opcode) != 0)) {
2322 gen_set_Rc0(ctx, dst);
2323 }
2324 }
2325
2326 static void gen_sradi0(DisasContext *ctx)
2327 {
2328 gen_sradi(ctx, 0);
2329 }
2330
2331 static void gen_sradi1(DisasContext *ctx)
2332 {
2333 gen_sradi(ctx, 1);
2334 }
2335
2336 /* extswsli & extswsli. */
2337 static inline void gen_extswsli(DisasContext *ctx, int n)
2338 {
2339 int sh = SH(ctx->opcode) + (n << 5);
2340 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2341 TCGv src = cpu_gpr[rS(ctx->opcode)];
2342
2343 tcg_gen_ext32s_tl(dst, src);
2344 tcg_gen_shli_tl(dst, dst, sh);
2345 if (unlikely(Rc(ctx->opcode) != 0)) {
2346 gen_set_Rc0(ctx, dst);
2347 }
2348 }
2349
2350 static void gen_extswsli0(DisasContext *ctx)
2351 {
2352 gen_extswsli(ctx, 0);
2353 }
2354
2355 static void gen_extswsli1(DisasContext *ctx)
2356 {
2357 gen_extswsli(ctx, 1);
2358 }
2359
2360 /* srd & srd. */
2361 static void gen_srd(DisasContext *ctx)
2362 {
2363 TCGv t0, t1;
2364
2365 t0 = tcg_temp_new();
2366 /* AND rS with a mask that is 0 when rB >= 0x40 */
2367 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2368 tcg_gen_sari_tl(t0, t0, 0x3f);
2369 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2370 t1 = tcg_temp_new();
2371 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2372 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2373 tcg_temp_free(t1);
2374 tcg_temp_free(t0);
2375 if (unlikely(Rc(ctx->opcode) != 0))
2376 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2377 }
2378 #endif
2379
2380 /*** Addressing modes ***/
2381 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2382 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2383 target_long maskl)
2384 {
2385 target_long simm = SIMM(ctx->opcode);
2386
2387 simm &= ~maskl;
2388 if (rA(ctx->opcode) == 0) {
2389 if (NARROW_MODE(ctx)) {
2390 simm = (uint32_t)simm;
2391 }
2392 tcg_gen_movi_tl(EA, simm);
2393 } else if (likely(simm != 0)) {
2394 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2395 if (NARROW_MODE(ctx)) {
2396 tcg_gen_ext32u_tl(EA, EA);
2397 }
2398 } else {
2399 if (NARROW_MODE(ctx)) {
2400 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2401 } else {
2402 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2403 }
2404 }
2405 }
2406
2407 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2408 {
2409 if (rA(ctx->opcode) == 0) {
2410 if (NARROW_MODE(ctx)) {
2411 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2412 } else {
2413 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2414 }
2415 } else {
2416 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2417 if (NARROW_MODE(ctx)) {
2418 tcg_gen_ext32u_tl(EA, EA);
2419 }
2420 }
2421 }
2422
2423 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2424 {
2425 if (rA(ctx->opcode) == 0) {
2426 tcg_gen_movi_tl(EA, 0);
2427 } else if (NARROW_MODE(ctx)) {
2428 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2429 } else {
2430 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2431 }
2432 }
2433
2434 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2435 target_long val)
2436 {
2437 tcg_gen_addi_tl(ret, arg1, val);
2438 if (NARROW_MODE(ctx)) {
2439 tcg_gen_ext32u_tl(ret, ret);
2440 }
2441 }
2442
2443 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2444 {
2445 TCGLabel *l1 = gen_new_label();
2446 TCGv t0 = tcg_temp_new();
2447 TCGv_i32 t1, t2;
2448 tcg_gen_andi_tl(t0, EA, mask);
2449 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2450 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2451 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2452 gen_update_nip(ctx, ctx->nip - 4);
2453 gen_helper_raise_exception_err(cpu_env, t1, t2);
2454 tcg_temp_free_i32(t1);
2455 tcg_temp_free_i32(t2);
2456 gen_set_label(l1);
2457 tcg_temp_free(t0);
2458 }
2459
2460 static inline void gen_align_no_le(DisasContext *ctx)
2461 {
2462 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2463 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2464 }
2465
2466 /*** Integer load ***/
2467 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2468 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2469
2470 #define GEN_QEMU_LOAD_TL(ldop, op) \
2471 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2472 TCGv val, \
2473 TCGv addr) \
2474 { \
2475 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2476 }
2477
2478 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2479 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2480 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2481 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2482 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2483
2484 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2485 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2486
2487 #define GEN_QEMU_LOAD_64(ldop, op) \
2488 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2489 TCGv_i64 val, \
2490 TCGv addr) \
2491 { \
2492 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2493 }
2494
2495 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2496 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2497 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2498
2499 #if defined(TARGET_PPC64)
2500 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2501 #endif
2502
2503 #define GEN_QEMU_STORE_TL(stop, op) \
2504 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2505 TCGv val, \
2506 TCGv addr) \
2507 { \
2508 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2509 }
2510
2511 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2512 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2513 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2514
2515 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2516 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2517
2518 #define GEN_QEMU_STORE_64(stop, op) \
2519 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2520 TCGv_i64 val, \
2521 TCGv addr) \
2522 { \
2523 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2524 }
2525
2526 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2527 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2528
2529 #if defined(TARGET_PPC64)
2530 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2531 #endif
2532
2533 #define GEN_LD(name, ldop, opc, type) \
2534 static void glue(gen_, name)(DisasContext *ctx) \
2535 { \
2536 TCGv EA; \
2537 gen_set_access_type(ctx, ACCESS_INT); \
2538 EA = tcg_temp_new(); \
2539 gen_addr_imm_index(ctx, EA, 0); \
2540 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2541 tcg_temp_free(EA); \
2542 }
2543
2544 #define GEN_LDU(name, ldop, opc, type) \
2545 static void glue(gen_, name##u)(DisasContext *ctx) \
2546 { \
2547 TCGv EA; \
2548 if (unlikely(rA(ctx->opcode) == 0 || \
2549 rA(ctx->opcode) == rD(ctx->opcode))) { \
2550 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2551 return; \
2552 } \
2553 gen_set_access_type(ctx, ACCESS_INT); \
2554 EA = tcg_temp_new(); \
2555 if (type == PPC_64B) \
2556 gen_addr_imm_index(ctx, EA, 0x03); \
2557 else \
2558 gen_addr_imm_index(ctx, EA, 0); \
2559 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2560 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2561 tcg_temp_free(EA); \
2562 }
2563
2564 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2565 static void glue(gen_, name##ux)(DisasContext *ctx) \
2566 { \
2567 TCGv EA; \
2568 if (unlikely(rA(ctx->opcode) == 0 || \
2569 rA(ctx->opcode) == rD(ctx->opcode))) { \
2570 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2571 return; \
2572 } \
2573 gen_set_access_type(ctx, ACCESS_INT); \
2574 EA = tcg_temp_new(); \
2575 gen_addr_reg_index(ctx, EA); \
2576 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2577 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2578 tcg_temp_free(EA); \
2579 }
2580
2581 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2582 static void glue(gen_, name##x)(DisasContext *ctx) \
2583 { \
2584 TCGv EA; \
2585 chk; \
2586 gen_set_access_type(ctx, ACCESS_INT); \
2587 EA = tcg_temp_new(); \
2588 gen_addr_reg_index(ctx, EA); \
2589 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2590 tcg_temp_free(EA); \
2591 }
2592
2593 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2594 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2595
2596 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2597 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2598
2599 #define GEN_LDS(name, ldop, op, type) \
2600 GEN_LD(name, ldop, op | 0x20, type); \
2601 GEN_LDU(name, ldop, op | 0x21, type); \
2602 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2603 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2604
2605 /* lbz lbzu lbzux lbzx */
2606 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2607 /* lha lhau lhaux lhax */
2608 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2609 /* lhz lhzu lhzux lhzx */
2610 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2611 /* lwz lwzu lwzux lwzx */
2612 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2613 #if defined(TARGET_PPC64)
2614 /* lwaux */
2615 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2616 /* lwax */
2617 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2618 /* ldux */
2619 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2620 /* ldx */
2621 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2622
2623 /* CI load/store variants */
2624 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2625 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2626 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2627 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2628
2629 static void gen_ld(DisasContext *ctx)
2630 {
2631 TCGv EA;
2632 if (Rc(ctx->opcode)) {
2633 if (unlikely(rA(ctx->opcode) == 0 ||
2634 rA(ctx->opcode) == rD(ctx->opcode))) {
2635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2636 return;
2637 }
2638 }
2639 gen_set_access_type(ctx, ACCESS_INT);
2640 EA = tcg_temp_new();
2641 gen_addr_imm_index(ctx, EA, 0x03);
2642 if (ctx->opcode & 0x02) {
2643 /* lwa (lwau is undefined) */
2644 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2645 } else {
2646 /* ld - ldu */
2647 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2648 }
2649 if (Rc(ctx->opcode))
2650 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2651 tcg_temp_free(EA);
2652 }
2653
2654 /* lq */
2655 static void gen_lq(DisasContext *ctx)
2656 {
2657 int ra, rd;
2658 TCGv EA;
2659
2660 /* lq is a legal user mode instruction starting in ISA 2.07 */
2661 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2662 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2663
2664 if (!legal_in_user_mode && ctx->pr) {
2665 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2666 return;
2667 }
2668
2669 if (!le_is_supported && ctx->le_mode) {
2670 gen_align_no_le(ctx);
2671 return;
2672 }
2673 ra = rA(ctx->opcode);
2674 rd = rD(ctx->opcode);
2675 if (unlikely((rd & 1) || rd == ra)) {
2676 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2677 return;
2678 }
2679
2680 gen_set_access_type(ctx, ACCESS_INT);
2681 EA = tcg_temp_new();
2682 gen_addr_imm_index(ctx, EA, 0x0F);
2683
2684 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2685 necessary 64-bit byteswap already. */
2686 if (unlikely(ctx->le_mode)) {
2687 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2688 gen_addr_add(ctx, EA, EA, 8);
2689 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2690 } else {
2691 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2692 gen_addr_add(ctx, EA, EA, 8);
2693 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2694 }
2695 tcg_temp_free(EA);
2696 }
2697 #endif
2698
2699 /*** Integer store ***/
2700 #define GEN_ST(name, stop, opc, type) \
2701 static void glue(gen_, name)(DisasContext *ctx) \
2702 { \
2703 TCGv EA; \
2704 gen_set_access_type(ctx, ACCESS_INT); \
2705 EA = tcg_temp_new(); \
2706 gen_addr_imm_index(ctx, EA, 0); \
2707 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2708 tcg_temp_free(EA); \
2709 }
2710
2711 #define GEN_STU(name, stop, opc, type) \
2712 static void glue(gen_, stop##u)(DisasContext *ctx) \
2713 { \
2714 TCGv EA; \
2715 if (unlikely(rA(ctx->opcode) == 0)) { \
2716 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2717 return; \
2718 } \
2719 gen_set_access_type(ctx, ACCESS_INT); \
2720 EA = tcg_temp_new(); \
2721 if (type == PPC_64B) \
2722 gen_addr_imm_index(ctx, EA, 0x03); \
2723 else \
2724 gen_addr_imm_index(ctx, EA, 0); \
2725 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2726 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2727 tcg_temp_free(EA); \
2728 }
2729
2730 #define GEN_STUX(name, stop, opc2, opc3, type) \
2731 static void glue(gen_, name##ux)(DisasContext *ctx) \
2732 { \
2733 TCGv EA; \
2734 if (unlikely(rA(ctx->opcode) == 0)) { \
2735 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2736 return; \
2737 } \
2738 gen_set_access_type(ctx, ACCESS_INT); \
2739 EA = tcg_temp_new(); \
2740 gen_addr_reg_index(ctx, EA); \
2741 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2742 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2743 tcg_temp_free(EA); \
2744 }
2745
2746 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2747 static void glue(gen_, name##x)(DisasContext *ctx) \
2748 { \
2749 TCGv EA; \
2750 chk; \
2751 gen_set_access_type(ctx, ACCESS_INT); \
2752 EA = tcg_temp_new(); \
2753 gen_addr_reg_index(ctx, EA); \
2754 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2755 tcg_temp_free(EA); \
2756 }
2757 #define GEN_STX(name, stop, opc2, opc3, type) \
2758 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2759
2760 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2761 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2762
2763 #define GEN_STS(name, stop, op, type) \
2764 GEN_ST(name, stop, op | 0x20, type); \
2765 GEN_STU(name, stop, op | 0x21, type); \
2766 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2767 GEN_STX(name, stop, 0x17, op | 0x00, type)
2768
2769 /* stb stbu stbux stbx */
2770 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2771 /* sth sthu sthux sthx */
2772 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2773 /* stw stwu stwux stwx */
2774 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2775 #if defined(TARGET_PPC64)
2776 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2777 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2778 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2779 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2780 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2781 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2782
2783 static void gen_std(DisasContext *ctx)
2784 {
2785 int rs;
2786 TCGv EA;
2787
2788 rs = rS(ctx->opcode);
2789 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2790 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2791 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2792
2793 if (!(ctx->insns_flags & PPC_64BX)) {
2794 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2795 }
2796
2797 if (!legal_in_user_mode && ctx->pr) {
2798 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2799 return;
2800 }
2801
2802 if (!le_is_supported && ctx->le_mode) {
2803 gen_align_no_le(ctx);
2804 return;
2805 }
2806
2807 if (unlikely(rs & 1)) {
2808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2809 return;
2810 }
2811 gen_set_access_type(ctx, ACCESS_INT);
2812 EA = tcg_temp_new();
2813 gen_addr_imm_index(ctx, EA, 0x03);
2814
2815 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2816 necessary 64-bit byteswap already. */
2817 if (unlikely(ctx->le_mode)) {
2818 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2819 gen_addr_add(ctx, EA, EA, 8);
2820 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2821 } else {
2822 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2823 gen_addr_add(ctx, EA, EA, 8);
2824 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2825 }
2826 tcg_temp_free(EA);
2827 } else {
2828 /* std / stdu*/
2829 if (Rc(ctx->opcode)) {
2830 if (unlikely(rA(ctx->opcode) == 0)) {
2831 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2832 return;
2833 }
2834 }
2835 gen_set_access_type(ctx, ACCESS_INT);
2836 EA = tcg_temp_new();
2837 gen_addr_imm_index(ctx, EA, 0x03);
2838 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2839 if (Rc(ctx->opcode))
2840 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2841 tcg_temp_free(EA);
2842 }
2843 }
2844 #endif
2845 /*** Integer load and store with byte reverse ***/
2846
2847 /* lhbrx */
2848 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2849
2850 /* lwbrx */
2851 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2852
2853 #if defined(TARGET_PPC64)
2854 /* ldbrx */
2855 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2856 /* stdbrx */
2857 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2858 #endif /* TARGET_PPC64 */
2859
2860 /* sthbrx */
2861 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2862 /* stwbrx */
2863 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2864
2865 /*** Integer load and store multiple ***/
2866
2867 /* lmw */
2868 static void gen_lmw(DisasContext *ctx)
2869 {
2870 TCGv t0;
2871 TCGv_i32 t1;
2872
2873 if (ctx->le_mode) {
2874 gen_align_no_le(ctx);
2875 return;
2876 }
2877 gen_set_access_type(ctx, ACCESS_INT);
2878 t0 = tcg_temp_new();
2879 t1 = tcg_const_i32(rD(ctx->opcode));
2880 gen_addr_imm_index(ctx, t0, 0);
2881 gen_helper_lmw(cpu_env, t0, t1);
2882 tcg_temp_free(t0);
2883 tcg_temp_free_i32(t1);
2884 }
2885
2886 /* stmw */
2887 static void gen_stmw(DisasContext *ctx)
2888 {
2889 TCGv t0;
2890 TCGv_i32 t1;
2891
2892 if (ctx->le_mode) {
2893 gen_align_no_le(ctx);
2894 return;
2895 }
2896 gen_set_access_type(ctx, ACCESS_INT);
2897 t0 = tcg_temp_new();
2898 t1 = tcg_const_i32(rS(ctx->opcode));
2899 gen_addr_imm_index(ctx, t0, 0);
2900 gen_helper_stmw(cpu_env, t0, t1);
2901 tcg_temp_free(t0);
2902 tcg_temp_free_i32(t1);
2903 }
2904
2905 /*** Integer load and store strings ***/
2906
2907 /* lswi */
2908 /* PowerPC32 specification says we must generate an exception if
2909 * rA is in the range of registers to be loaded.
2910 * In an other hand, IBM says this is valid, but rA won't be loaded.
2911 * For now, I'll follow the spec...
2912 */
2913 static void gen_lswi(DisasContext *ctx)
2914 {
2915 TCGv t0;
2916 TCGv_i32 t1, t2;
2917 int nb = NB(ctx->opcode);
2918 int start = rD(ctx->opcode);
2919 int ra = rA(ctx->opcode);
2920 int nr;
2921
2922 if (ctx->le_mode) {
2923 gen_align_no_le(ctx);
2924 return;
2925 }
2926 if (nb == 0)
2927 nb = 32;
2928 nr = (nb + 3) / 4;
2929 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2930 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2931 return;
2932 }
2933 gen_set_access_type(ctx, ACCESS_INT);
2934 t0 = tcg_temp_new();
2935 gen_addr_register(ctx, t0);
2936 t1 = tcg_const_i32(nb);
2937 t2 = tcg_const_i32(start);
2938 gen_helper_lsw(cpu_env, t0, t1, t2);
2939 tcg_temp_free(t0);
2940 tcg_temp_free_i32(t1);
2941 tcg_temp_free_i32(t2);
2942 }
2943
2944 /* lswx */
2945 static void gen_lswx(DisasContext *ctx)
2946 {
2947 TCGv t0;
2948 TCGv_i32 t1, t2, t3;
2949
2950 if (ctx->le_mode) {
2951 gen_align_no_le(ctx);
2952 return;
2953 }
2954 gen_set_access_type(ctx, ACCESS_INT);
2955 t0 = tcg_temp_new();
2956 gen_addr_reg_index(ctx, t0);
2957 t1 = tcg_const_i32(rD(ctx->opcode));
2958 t2 = tcg_const_i32(rA(ctx->opcode));
2959 t3 = tcg_const_i32(rB(ctx->opcode));
2960 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2961 tcg_temp_free(t0);
2962 tcg_temp_free_i32(t1);
2963 tcg_temp_free_i32(t2);
2964 tcg_temp_free_i32(t3);
2965 }
2966
2967 /* stswi */
2968 static void gen_stswi(DisasContext *ctx)
2969 {
2970 TCGv t0;
2971 TCGv_i32 t1, t2;
2972 int nb = NB(ctx->opcode);
2973
2974 if (ctx->le_mode) {
2975 gen_align_no_le(ctx);
2976 return;
2977 }
2978 gen_set_access_type(ctx, ACCESS_INT);
2979 t0 = tcg_temp_new();
2980 gen_addr_register(ctx, t0);
2981 if (nb == 0)
2982 nb = 32;
2983 t1 = tcg_const_i32(nb);
2984 t2 = tcg_const_i32(rS(ctx->opcode));
2985 gen_helper_stsw(cpu_env, t0, t1, t2);
2986 tcg_temp_free(t0);
2987 tcg_temp_free_i32(t1);
2988 tcg_temp_free_i32(t2);
2989 }
2990
2991 /* stswx */
2992 static void gen_stswx(DisasContext *ctx)
2993 {
2994 TCGv t0;
2995 TCGv_i32 t1, t2;
2996
2997 if (ctx->le_mode) {
2998 gen_align_no_le(ctx);
2999 return;
3000 }
3001 gen_set_access_type(ctx, ACCESS_INT);
3002 t0 = tcg_temp_new();
3003 gen_addr_reg_index(ctx, t0);
3004 t1 = tcg_temp_new_i32();
3005 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3006 tcg_gen_andi_i32(t1, t1, 0x7F);
3007 t2 = tcg_const_i32(rS(ctx->opcode));
3008 gen_helper_stsw(cpu_env, t0, t1, t2);
3009 tcg_temp_free(t0);
3010 tcg_temp_free_i32(t1);
3011 tcg_temp_free_i32(t2);
3012 }
3013
3014 /*** Memory synchronisation ***/
3015 /* eieio */
3016 static void gen_eieio(DisasContext *ctx)
3017 {
3018 }
3019
3020 #if !defined(CONFIG_USER_ONLY)
3021 static inline void gen_check_tlb_flush(DisasContext *ctx)
3022 {
3023 TCGv_i32 t;
3024 TCGLabel *l;
3025
3026 if (!ctx->lazy_tlb_flush) {
3027 return;
3028 }
3029 l = gen_new_label();
3030 t = tcg_temp_new_i32();
3031 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3032 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3033 gen_helper_check_tlb_flush(cpu_env);
3034 gen_set_label(l);
3035 tcg_temp_free_i32(t);
3036 }
3037 #else
3038 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3039 #endif
3040
3041 /* isync */
3042 static void gen_isync(DisasContext *ctx)
3043 {
3044 /*
3045 * We need to check for a pending TLB flush. This can only happen in
3046 * kernel mode however so check MSR_PR
3047 */
3048 if (!ctx->pr) {
3049 gen_check_tlb_flush(ctx);
3050 }
3051 gen_stop_exception(ctx);
3052 }
3053
3054 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3055
3056 #define LARX(name, memop) \
3057 static void gen_##name(DisasContext *ctx) \
3058 { \
3059 TCGv t0; \
3060 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3061 int len = MEMOP_GET_SIZE(memop); \
3062 gen_set_access_type(ctx, ACCESS_RES); \
3063 t0 = tcg_temp_local_new(); \
3064 gen_addr_reg_index(ctx, t0); \
3065 if ((len) > 1) { \
3066 gen_check_align(ctx, t0, (len)-1); \
3067 } \
3068 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3069 tcg_gen_mov_tl(cpu_reserve, t0); \
3070 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3071 tcg_temp_free(t0); \
3072 }
3073
3074 /* lwarx */
3075 LARX(lbarx, DEF_MEMOP(MO_UB))
3076 LARX(lharx, DEF_MEMOP(MO_UW))
3077 LARX(lwarx, DEF_MEMOP(MO_UL))
3078
3079 #if defined(CONFIG_USER_ONLY)
3080 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3081 int reg, int memop)
3082 {
3083 TCGv t0 = tcg_temp_new();
3084
3085 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3086 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3087 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3088 tcg_temp_free(t0);
3089 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3090 }
3091 #else
3092 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3093 int reg, int memop)
3094 {
3095 TCGLabel *l1;
3096
3097 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3098 l1 = gen_new_label();
3099 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3100 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3101 tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
3102 gen_set_label(l1);
3103 tcg_gen_movi_tl(cpu_reserve, -1);
3104 }
3105 #endif
3106
3107 #define STCX(name, memop) \
3108 static void gen_##name(DisasContext *ctx) \
3109 { \
3110 TCGv t0; \
3111 int len = MEMOP_GET_SIZE(memop); \
3112 gen_set_access_type(ctx, ACCESS_RES); \
3113 t0 = tcg_temp_local_new(); \
3114 gen_addr_reg_index(ctx, t0); \
3115 if (len > 1) { \
3116 gen_check_align(ctx, t0, (len) - 1); \
3117 } \
3118 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3119 tcg_temp_free(t0); \
3120 }
3121
3122 STCX(stbcx_, DEF_MEMOP(MO_UB))
3123 STCX(sthcx_, DEF_MEMOP(MO_UW))
3124 STCX(stwcx_, DEF_MEMOP(MO_UL))
3125
3126 #if defined(TARGET_PPC64)
3127 /* ldarx */
3128 LARX(ldarx, DEF_MEMOP(MO_Q))
3129 /* stdcx. */
3130 STCX(stdcx_, DEF_MEMOP(MO_Q))
3131
3132 /* lqarx */
3133 static void gen_lqarx(DisasContext *ctx)
3134 {
3135 TCGv EA;
3136 int rd = rD(ctx->opcode);
3137 TCGv gpr1, gpr2;
3138
3139 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3140 (rd == rB(ctx->opcode)))) {
3141 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3142 return;
3143 }
3144
3145 gen_set_access_type(ctx, ACCESS_RES);
3146 EA = tcg_temp_local_new();
3147 gen_addr_reg_index(ctx, EA);
3148 gen_check_align(ctx, EA, 15);
3149 if (unlikely(ctx->le_mode)) {
3150 gpr1 = cpu_gpr[rd+1];
3151 gpr2 = cpu_gpr[rd];
3152 } else {
3153 gpr1 = cpu_gpr[rd];
3154 gpr2 = cpu_gpr[rd+1];
3155 }
3156 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3157 tcg_gen_mov_tl(cpu_reserve, EA);
3158 gen_addr_add(ctx, EA, EA, 8);
3159 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3160
3161 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3162 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3163 tcg_temp_free(EA);
3164 }
3165
3166 /* stqcx. */
3167 static void gen_stqcx_(DisasContext *ctx)
3168 {
3169 TCGv EA;
3170 int reg = rS(ctx->opcode);
3171 int len = 16;
3172 #if !defined(CONFIG_USER_ONLY)
3173 TCGLabel *l1;
3174 TCGv gpr1, gpr2;
3175 #endif
3176
3177 if (unlikely((rD(ctx->opcode) & 1))) {
3178 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3179 return;
3180 }
3181 gen_set_access_type(ctx, ACCESS_RES);
3182 EA = tcg_temp_local_new();
3183 gen_addr_reg_index(ctx, EA);
3184 if (len > 1) {
3185 gen_check_align(ctx, EA, (len) - 1);
3186 }
3187
3188 #if defined(CONFIG_USER_ONLY)
3189 gen_conditional_store(ctx, EA, reg, 16);
3190 #else
3191 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3192 l1 = gen_new_label();
3193 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3194 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3195
3196 if (unlikely(ctx->le_mode)) {
3197 gpr1 = cpu_gpr[reg + 1];
3198 gpr2 = cpu_gpr[reg];
3199 } else {
3200 gpr1 = cpu_gpr[reg];
3201 gpr2 = cpu_gpr[reg + 1];
3202 }
3203 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3204 gen_addr_add(ctx, EA, EA, 8);
3205 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3206
3207 gen_set_label(l1);
3208 tcg_gen_movi_tl(cpu_reserve, -1);
3209 #endif
3210 tcg_temp_free(EA);
3211 }
3212
3213 #endif /* defined(TARGET_PPC64) */
3214
3215 /* sync */
3216 static void gen_sync(DisasContext *ctx)
3217 {
3218 uint32_t l = (ctx->opcode >> 21) & 3;
3219
3220 /*
3221 * We may need to check for a pending TLB flush.
3222 *
3223 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3224 *
3225 * Additionally, this can only happen in kernel mode however so
3226 * check MSR_PR as well.
3227 */
3228 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3229 gen_check_tlb_flush(ctx);
3230 }
3231 }
3232
3233 /* wait */
3234 static void gen_wait(DisasContext *ctx)
3235 {
3236 TCGv_i32 t0 = tcg_const_i32(1);
3237 tcg_gen_st_i32(t0, cpu_env,
3238 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3239 tcg_temp_free_i32(t0);
3240 /* Stop translation, as the CPU is supposed to sleep from now */
3241 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3242 }
3243
3244 #if defined(TARGET_PPC64)
3245 static void gen_doze(DisasContext *ctx)
3246 {
3247 #if defined(CONFIG_USER_ONLY)
3248 GEN_PRIV;
3249 #else
3250 TCGv_i32 t;
3251
3252 CHK_HV;
3253 t = tcg_const_i32(PPC_PM_DOZE);
3254 gen_helper_pminsn(cpu_env, t);
3255 tcg_temp_free_i32(t);
3256 gen_stop_exception(ctx);
3257 #endif /* defined(CONFIG_USER_ONLY) */
3258 }
3259
3260 static void gen_nap(DisasContext *ctx)
3261 {
3262 #if defined(CONFIG_USER_ONLY)
3263 GEN_PRIV;
3264 #else
3265 TCGv_i32 t;
3266
3267 CHK_HV;
3268 t = tcg_const_i32(PPC_PM_NAP);
3269 gen_helper_pminsn(cpu_env, t);
3270 tcg_temp_free_i32(t);
3271 gen_stop_exception(ctx);
3272 #endif /* defined(CONFIG_USER_ONLY) */
3273 }
3274
3275 static void gen_sleep(DisasContext *ctx)
3276 {
3277 #if defined(CONFIG_USER_ONLY)
3278 GEN_PRIV;
3279 #else
3280 TCGv_i32 t;
3281
3282 CHK_HV;
3283 t = tcg_const_i32(PPC_PM_SLEEP);
3284 gen_helper_pminsn(cpu_env, t);
3285 tcg_temp_free_i32(t);
3286 gen_stop_exception(ctx);
3287 #endif /* defined(CONFIG_USER_ONLY) */
3288 }
3289
3290 static void gen_rvwinkle(DisasContext *ctx)
3291 {
3292 #if defined(CONFIG_USER_ONLY)
3293 GEN_PRIV;
3294 #else
3295 TCGv_i32 t;
3296
3297 CHK_HV;
3298 t = tcg_const_i32(PPC_PM_RVWINKLE);
3299 gen_helper_pminsn(cpu_env, t);
3300 tcg_temp_free_i32(t);
3301 gen_stop_exception(ctx);
3302 #endif /* defined(CONFIG_USER_ONLY) */
3303 }
3304 #endif /* #if defined(TARGET_PPC64) */
3305
3306 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3307 {
3308 #if defined(TARGET_PPC64)
3309 if (ctx->has_cfar)
3310 tcg_gen_movi_tl(cpu_cfar, nip);
3311 #endif
3312 }
3313
3314 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3315 {
3316 if (unlikely(ctx->singlestep_enabled)) {
3317 return false;
3318 }
3319
3320 #ifndef CONFIG_USER_ONLY
3321 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3322 #else
3323 return true;
3324 #endif
3325 }
3326
3327 /*** Branch ***/
3328 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3329 {
3330 if (NARROW_MODE(ctx)) {
3331 dest = (uint32_t) dest;
3332 }
3333 if (use_goto_tb(ctx, dest)) {
3334 tcg_gen_goto_tb(n);
3335 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3336 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3337 } else {
3338 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3339 if (unlikely(ctx->singlestep_enabled)) {
3340 if ((ctx->singlestep_enabled &
3341 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3342 (ctx->exception == POWERPC_EXCP_BRANCH ||
3343 ctx->exception == POWERPC_EXCP_TRACE)) {
3344 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3345 }
3346 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3347 gen_debug_exception(ctx);
3348 }
3349 }
3350 tcg_gen_exit_tb(0);
3351 }
3352 }
3353
3354 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3355 {
3356 if (NARROW_MODE(ctx)) {
3357 nip = (uint32_t)nip;
3358 }
3359 tcg_gen_movi_tl(cpu_lr, nip);
3360 }
3361
3362 /* b ba bl bla */
3363 static void gen_b(DisasContext *ctx)
3364 {
3365 target_ulong li, target;
3366
3367 ctx->exception = POWERPC_EXCP_BRANCH;
3368 /* sign extend LI */
3369 li = LI(ctx->opcode);
3370 li = (li ^ 0x02000000) - 0x02000000;
3371 if (likely(AA(ctx->opcode) == 0)) {
3372 target = ctx->nip + li - 4;
3373 } else {
3374 target = li;
3375 }
3376 if (LK(ctx->opcode)) {
3377 gen_setlr(ctx, ctx->nip);
3378 }
3379 gen_update_cfar(ctx, ctx->nip - 4);
3380 gen_goto_tb(ctx, 0, target);
3381 }
3382
3383 #define BCOND_IM 0
3384 #define BCOND_LR 1
3385 #define BCOND_CTR 2
3386 #define BCOND_TAR 3
3387
3388 static inline void gen_bcond(DisasContext *ctx, int type)
3389 {
3390 uint32_t bo = BO(ctx->opcode);
3391 TCGLabel *l1;
3392 TCGv target;
3393
3394 ctx->exception = POWERPC_EXCP_BRANCH;
3395 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3396 target = tcg_temp_local_new();
3397 if (type == BCOND_CTR)
3398 tcg_gen_mov_tl(target, cpu_ctr);
3399 else if (type == BCOND_TAR)
3400 gen_load_spr(target, SPR_TAR);
3401 else
3402 tcg_gen_mov_tl(target, cpu_lr);
3403 } else {
3404 TCGV_UNUSED(target);
3405 }
3406 if (LK(ctx->opcode))
3407 gen_setlr(ctx, ctx->nip);
3408 l1 = gen_new_label();
3409 if ((bo & 0x4) == 0) {
3410 /* Decrement and test CTR */
3411 TCGv temp = tcg_temp_new();
3412 if (unlikely(type == BCOND_CTR)) {
3413 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3414 return;
3415 }
3416 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3417 if (NARROW_MODE(ctx)) {
3418 tcg_gen_ext32u_tl(temp, cpu_ctr);
3419 } else {
3420 tcg_gen_mov_tl(temp, cpu_ctr);
3421 }
3422 if (bo & 0x2) {
3423 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3424 } else {
3425 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3426 }
3427 tcg_temp_free(temp);
3428 }
3429 if ((bo & 0x10) == 0) {
3430 /* Test CR */
3431 uint32_t bi = BI(ctx->opcode);
3432 uint32_t mask = 0x08 >> (bi & 0x03);
3433 TCGv_i32 temp = tcg_temp_new_i32();
3434
3435 if (bo & 0x8) {
3436 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3437 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3438 } else {
3439 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3440 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3441 }
3442 tcg_temp_free_i32(temp);
3443 }
3444 gen_update_cfar(ctx, ctx->nip - 4);
3445 if (type == BCOND_IM) {
3446 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3447 if (likely(AA(ctx->opcode) == 0)) {
3448 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3449 } else {
3450 gen_goto_tb(ctx, 0, li);
3451 }
3452 if ((bo & 0x14) != 0x14) {
3453 gen_set_label(l1);
3454 gen_goto_tb(ctx, 1, ctx->nip);
3455 }
3456 } else {
3457 if (NARROW_MODE(ctx)) {
3458 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3459 } else {
3460 tcg_gen_andi_tl(cpu_nip, target, ~3);
3461 }
3462 tcg_gen_exit_tb(0);
3463 if ((bo & 0x14) != 0x14) {
3464 gen_set_label(l1);
3465 gen_update_nip(ctx, ctx->nip);
3466 tcg_gen_exit_tb(0);
3467 }
3468 }
3469 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3470 tcg_temp_free(target);
3471 }
3472 }
3473
3474 static void gen_bc(DisasContext *ctx)
3475 {
3476 gen_bcond(ctx, BCOND_IM);
3477 }
3478
3479 static void gen_bcctr(DisasContext *ctx)
3480 {
3481 gen_bcond(ctx, BCOND_CTR);
3482 }
3483
3484 static void gen_bclr(DisasContext *ctx)
3485 {
3486 gen_bcond(ctx, BCOND_LR);
3487 }
3488
3489 static void gen_bctar(DisasContext *ctx)
3490 {
3491 gen_bcond(ctx, BCOND_TAR);
3492 }
3493
3494 /*** Condition register logical ***/
3495 #define GEN_CRLOGIC(name, tcg_op, opc) \
3496 static void glue(gen_, name)(DisasContext *ctx) \
3497 { \
3498 uint8_t bitmask; \
3499 int sh; \
3500 TCGv_i32 t0, t1; \
3501 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3502 t0 = tcg_temp_new_i32(); \
3503 if (sh > 0) \
3504 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3505 else if (sh < 0) \
3506 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3507 else \
3508 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3509 t1 = tcg_temp_new_i32(); \
3510 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3511 if (sh > 0) \
3512 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3513 else if (sh < 0) \
3514 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3515 else \
3516 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3517 tcg_op(t0, t0, t1); \
3518 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3519 tcg_gen_andi_i32(t0, t0, bitmask); \
3520 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3521 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3522 tcg_temp_free_i32(t0); \
3523 tcg_temp_free_i32(t1); \
3524 }
3525
3526 /* crand */
3527 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3528 /* crandc */
3529 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3530 /* creqv */
3531 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3532 /* crnand */
3533 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3534 /* crnor */
3535 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3536 /* cror */
3537 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3538 /* crorc */
3539 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3540 /* crxor */
3541 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3542
3543 /* mcrf */
3544 static void gen_mcrf(DisasContext *ctx)
3545 {
3546 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3547 }
3548
3549 /*** System linkage ***/
3550
3551 /* rfi (supervisor only) */
3552 static void gen_rfi(DisasContext *ctx)
3553 {
3554 #if defined(CONFIG_USER_ONLY)
3555 GEN_PRIV;
3556 #else
3557 /* This instruction doesn't exist anymore on 64-bit server
3558 * processors compliant with arch 2.x
3559 */
3560 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3561 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3562 return;
3563 }
3564 /* Restore CPU state */
3565 CHK_SV;
3566 gen_update_cfar(ctx, ctx->nip - 4);
3567 gen_helper_rfi(cpu_env);
3568 gen_sync_exception(ctx);
3569 #endif
3570 }
3571
3572 #if defined(TARGET_PPC64)
3573 static void gen_rfid(DisasContext *ctx)
3574 {
3575 #if defined(CONFIG_USER_ONLY)
3576 GEN_PRIV;
3577 #else
3578 /* Restore CPU state */
3579 CHK_SV;
3580 gen_update_cfar(ctx, ctx->nip - 4);
3581 gen_helper_rfid(cpu_env);
3582 gen_sync_exception(ctx);
3583 #endif
3584 }
3585
3586 static void gen_hrfid(DisasContext *ctx)
3587 {
3588 #if defined(CONFIG_USER_ONLY)
3589 GEN_PRIV;
3590 #else
3591 /* Restore CPU state */
3592 CHK_HV;
3593 gen_helper_hrfid(cpu_env);
3594 gen_sync_exception(ctx);
3595 #endif
3596 }
3597 #endif
3598
3599 /* sc */
3600 #if defined(CONFIG_USER_ONLY)
3601 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3602 #else
3603 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3604 #endif
3605 static void gen_sc(DisasContext *ctx)
3606 {
3607 uint32_t lev;
3608
3609 lev = (ctx->opcode >> 5) & 0x7F;
3610 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3611 }
3612
3613 /*** Trap ***/
3614
3615 /* Check for unconditional traps (always or never) */
3616 static bool check_unconditional_trap(DisasContext *ctx)
3617 {
3618 /* Trap never */
3619 if (TO(ctx->opcode) == 0) {
3620 return true;
3621 }
3622 /* Trap always */
3623 if (TO(ctx->opcode) == 31) {
3624 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3625 return true;
3626 }
3627 return false;
3628 }
3629
3630 /* tw */
3631 static void gen_tw(DisasContext *ctx)
3632 {
3633 TCGv_i32 t0;
3634
3635 if (check_unconditional_trap(ctx)) {
3636 return;
3637 }
3638 t0 = tcg_const_i32(TO(ctx->opcode));
3639 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3640 t0);
3641 tcg_temp_free_i32(t0);
3642 }
3643
3644 /* twi */
3645 static void gen_twi(DisasContext *ctx)
3646 {
3647 TCGv t0;
3648 TCGv_i32 t1;
3649
3650 if (check_unconditional_trap(ctx)) {
3651 return;
3652 }
3653 t0 = tcg_const_tl(SIMM(ctx->opcode));
3654 t1 = tcg_const_i32(TO(ctx->opcode));
3655 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3656 tcg_temp_free(t0);
3657 tcg_temp_free_i32(t1);
3658 }
3659
3660 #if defined(TARGET_PPC64)
3661 /* td */
3662 static void gen_td(DisasContext *ctx)
3663 {
3664 TCGv_i32 t0;
3665
3666 if (check_unconditional_trap(ctx)) {
3667 return;
3668 }
3669 t0 = tcg_const_i32(TO(ctx->opcode));
3670 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3671 t0);
3672 tcg_temp_free_i32(t0);
3673 }
3674
3675 /* tdi */
3676 static void gen_tdi(DisasContext *ctx)
3677 {
3678 TCGv t0;
3679 TCGv_i32 t1;
3680
3681 if (check_unconditional_trap(ctx)) {
3682 return;
3683 }
3684 t0 = tcg_const_tl(SIMM(ctx->opcode));
3685 t1 = tcg_const_i32(TO(ctx->opcode));
3686 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3687 tcg_temp_free(t0);
3688 tcg_temp_free_i32(t1);
3689 }
3690 #endif
3691
3692 /*** Processor control ***/
3693
3694 static void gen_read_xer(TCGv dst)
3695 {
3696 TCGv t0 = tcg_temp_new();
3697 TCGv t1 = tcg_temp_new();
3698 TCGv t2 = tcg_temp_new();
3699 tcg_gen_mov_tl(dst, cpu_xer);
3700 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3701 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3702 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3703 tcg_gen_or_tl(t0, t0, t1);
3704 tcg_gen_or_tl(dst, dst, t2);
3705 tcg_gen_or_tl(dst, dst, t0);
3706 tcg_temp_free(t0);
3707 tcg_temp_free(t1);
3708 tcg_temp_free(t2);
3709 }
3710
3711 static void gen_write_xer(TCGv src)
3712 {
3713 tcg_gen_andi_tl(cpu_xer, src,
3714 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3715 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3716 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3717 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3718 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3719 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3720 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3721 }
3722
3723 /* mcrxr */
3724 static void gen_mcrxr(DisasContext *ctx)
3725 {
3726 TCGv_i32 t0 = tcg_temp_new_i32();
3727 TCGv_i32 t1 = tcg_temp_new_i32();
3728 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3729
3730 tcg_gen_trunc_tl_i32(t0, cpu_so);
3731 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3732 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3733 tcg_gen_shli_i32(t0, t0, 3);
3734 tcg_gen_shli_i32(t1, t1, 2);
3735 tcg_gen_shli_i32(dst, dst, 1);
3736 tcg_gen_or_i32(dst, dst, t0);
3737 tcg_gen_or_i32(dst, dst, t1);
3738 tcg_temp_free_i32(t0);
3739 tcg_temp_free_i32(t1);
3740
3741 tcg_gen_movi_tl(cpu_so, 0);
3742 tcg_gen_movi_tl(cpu_ov, 0);
3743 tcg_gen_movi_tl(cpu_ca, 0);
3744 }
3745
3746 /* mfcr mfocrf */
3747 static void gen_mfcr(DisasContext *ctx)
3748 {
3749 uint32_t crm, crn;
3750
3751 if (likely(ctx->opcode & 0x00100000)) {
3752 crm = CRM(ctx->opcode);
3753 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3754 crn = ctz32 (crm);
3755 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3756 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3757 cpu_gpr[rD(ctx->opcode)], crn * 4);
3758 }
3759 } else {
3760 TCGv_i32 t0 = tcg_temp_new_i32();
3761 tcg_gen_mov_i32(t0, cpu_crf[0]);
3762 tcg_gen_shli_i32(t0, t0, 4);
3763 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3764 tcg_gen_shli_i32(t0, t0, 4);
3765 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3766 tcg_gen_shli_i32(t0, t0, 4);
3767 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3768 tcg_gen_shli_i32(t0, t0, 4);
3769 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3770 tcg_gen_shli_i32(t0, t0, 4);
3771 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3772 tcg_gen_shli_i32(t0, t0, 4);
3773 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3774 tcg_gen_shli_i32(t0, t0, 4);
3775 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3776 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3777 tcg_temp_free_i32(t0);
3778 }
3779 }
3780
3781 /* mfmsr */
3782 static void gen_mfmsr(DisasContext *ctx)
3783 {
3784 CHK_SV;
3785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3786 }
3787
3788 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3789 {
3790 #if 0
3791 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3792 printf("ERROR: try to access SPR %d !\n", sprn);
3793 #endif
3794 }
3795 #define SPR_NOACCESS (&spr_noaccess)
3796
3797 /* mfspr */
3798 static inline void gen_op_mfspr(DisasContext *ctx)
3799 {
3800 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3801 uint32_t sprn = SPR(ctx->opcode);
3802
3803 #if defined(CONFIG_USER_ONLY)
3804 read_cb = ctx->spr_cb[sprn].uea_read;
3805 #else
3806 if (ctx->pr) {
3807 read_cb = ctx->spr_cb[sprn].uea_read;
3808 } else if (ctx->hv) {
3809 read_cb = ctx->spr_cb[sprn].hea_read;
3810 } else {
3811 read_cb = ctx->spr_cb[sprn].oea_read;
3812 }
3813 #endif
3814 if (likely(read_cb != NULL)) {
3815 if (likely(read_cb != SPR_NOACCESS)) {
3816 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3817 } else {
3818 /* Privilege exception */
3819 /* This is a hack to avoid warnings when running Linux:
3820 * this OS breaks the PowerPC virtualisation model,
3821 * allowing userland application to read the PVR
3822 */
3823 if (sprn != SPR_PVR) {
3824 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3825 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3826 if (qemu_log_separate()) {
3827 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3828 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3829 }
3830 }
3831 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3832 }
3833 } else {
3834 /* ISA 2.07 defines these as no-ops */
3835 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3836 (sprn >= 808 && sprn <= 811)) {
3837 /* This is a nop */
3838 return;
3839 }
3840 /* Not defined */
3841 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3842 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3843 if (qemu_log_separate()) {
3844 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3845 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3846 }
3847
3848 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3849 * it can generate a priv, a hv emu or a no-op
3850 */
3851 if (sprn & 0x10) {
3852 if (ctx->pr) {
3853 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3854 }
3855 } else {
3856 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3857 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3858 }
3859 }
3860 }
3861 }
3862
3863 static void gen_mfspr(DisasContext *ctx)
3864 {
3865 gen_op_mfspr(ctx);
3866 }
3867
3868 /* mftb */
3869 static void gen_mftb(DisasContext *ctx)
3870 {
3871 gen_op_mfspr(ctx);
3872 }
3873
3874 /* mtcrf mtocrf*/
3875 static void gen_mtcrf(DisasContext *ctx)
3876 {
3877 uint32_t crm, crn;
3878
3879 crm = CRM(ctx->opcode);
3880 if (likely((ctx->opcode & 0x00100000))) {
3881 if (crm && ((crm & (crm - 1)) == 0)) {
3882 TCGv_i32 temp = tcg_temp_new_i32();
3883 crn = ctz32 (crm);
3884 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3885 tcg_gen_shri_i32(temp, temp, crn * 4);
3886 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3887 tcg_temp_free_i32(temp);
3888 }
3889 } else {
3890 TCGv_i32 temp = tcg_temp_new_i32();
3891 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3892 for (crn = 0 ; crn < 8 ; crn++) {
3893 if (crm & (1 << crn)) {
3894 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3895 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3896 }
3897 }
3898 tcg_temp_free_i32(temp);
3899 }
3900 }
3901
3902 /* mtmsr */
3903 #if defined(TARGET_PPC64)
3904 static void gen_mtmsrd(DisasContext *ctx)
3905 {
3906 CHK_SV;
3907
3908 #if !defined(CONFIG_USER_ONLY)
3909 if (ctx->opcode & 0x00010000) {
3910 /* Special form that does not need any synchronisation */
3911 TCGv t0 = tcg_temp_new();
3912 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3913 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3914 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3915 tcg_temp_free(t0);
3916 } else {
3917 /* XXX: we need to update nip before the store
3918 * if we enter power saving mode, we will exit the loop
3919 * directly from ppc_store_msr
3920 */
3921 gen_update_nip(ctx, ctx->nip);
3922 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3923 /* Must stop the translation as machine state (may have) changed */
3924 /* Note that mtmsr is not always defined as context-synchronizing */
3925 gen_stop_exception(ctx);
3926 }
3927 #endif /* !defined(CONFIG_USER_ONLY) */
3928 }
3929 #endif /* defined(TARGET_PPC64) */
3930
3931 static void gen_mtmsr(DisasContext *ctx)
3932 {
3933 CHK_SV;
3934
3935 #if !defined(CONFIG_USER_ONLY)
3936 if (ctx->opcode & 0x00010000) {
3937 /* Special form that does not need any synchronisation */
3938 TCGv t0 = tcg_temp_new();
3939 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3940 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3941 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3942 tcg_temp_free(t0);
3943 } else {
3944 TCGv msr = tcg_temp_new();
3945
3946 /* XXX: we need to update nip before the store
3947 * if we enter power saving mode, we will exit the loop
3948 * directly from ppc_store_msr
3949 */
3950 gen_update_nip(ctx, ctx->nip);
3951 #if defined(TARGET_PPC64)
3952 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3953 #else
3954 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3955 #endif
3956 gen_helper_store_msr(cpu_env, msr);
3957 tcg_temp_free(msr);
3958 /* Must stop the translation as machine state (may have) changed */
3959 /* Note that mtmsr is not always defined as context-synchronizing */
3960 gen_stop_exception(ctx);
3961 }
3962 #endif
3963 }
3964
3965 /* mtspr */
3966 static void gen_mtspr(DisasContext *ctx)
3967 {
3968 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3969 uint32_t sprn = SPR(ctx->opcode);
3970
3971 #if defined(CONFIG_USER_ONLY)
3972 write_cb = ctx->spr_cb[sprn].uea_write;
3973 #else
3974 if (ctx->pr) {
3975 write_cb = ctx->spr_cb[sprn].uea_write;
3976 } else if (ctx->hv) {
3977 write_cb = ctx->spr_cb[sprn].hea_write;
3978 } else {
3979 write_cb = ctx->spr_cb[sprn].oea_write;
3980 }
3981 #endif
3982 if (likely(write_cb != NULL)) {
3983 if (likely(write_cb != SPR_NOACCESS)) {
3984 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3985 } else {
3986 /* Privilege exception */
3987 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3988 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3989 if (qemu_log_separate()) {
3990 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3991 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3992 }
3993 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3994 }
3995 } else {
3996 /* ISA 2.07 defines these as no-ops */
3997 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3998 (sprn >= 808 && sprn <= 811)) {
3999 /* This is a nop */
4000 return;
4001 }
4002
4003 /* Not defined */
4004 if (qemu_log_separate()) {
4005 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4006 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4007 }
4008 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4009 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4010
4011
4012 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4013 * it can generate a priv, a hv emu or a no-op
4014 */
4015 if (sprn & 0x10) {
4016 if (ctx->pr) {
4017 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4018 }
4019 } else {
4020 if (ctx->pr || sprn == 0) {
4021 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4022 }
4023 }
4024 }
4025 }
4026
4027 #if defined(TARGET_PPC64)
4028 /* setb */
4029 static void gen_setb(DisasContext *ctx)
4030 {
4031 TCGv_i32 t0 = tcg_temp_new_i32();
4032 TCGv_i32 t8 = tcg_temp_new_i32();
4033 TCGv_i32 tm1 = tcg_temp_new_i32();
4034 int crf = crfS(ctx->opcode);
4035
4036 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4037 tcg_gen_movi_i32(t8, 8);
4038 tcg_gen_movi_i32(tm1, -1);
4039 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4040 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4041
4042 tcg_temp_free_i32(t0);
4043 tcg_temp_free_i32(t8);
4044 tcg_temp_free_i32(tm1);
4045 }
4046 #endif
4047
4048 /*** Cache management ***/
4049
4050 /* dcbf */
4051 static void gen_dcbf(DisasContext *ctx)
4052 {
4053 /* XXX: specification says this is treated as a load by the MMU */
4054 TCGv t0;
4055 gen_set_access_type(ctx, ACCESS_CACHE);
4056 t0 = tcg_temp_new();
4057 gen_addr_reg_index(ctx, t0);
4058 gen_qemu_ld8u(ctx, t0, t0);
4059 tcg_temp_free(t0);
4060 }
4061
4062 /* dcbi (Supervisor only) */
4063 static void gen_dcbi(DisasContext *ctx)
4064 {
4065 #if defined(CONFIG_USER_ONLY)
4066 GEN_PRIV;
4067 #else
4068 TCGv EA, val;
4069
4070 CHK_SV;
4071 EA = tcg_temp_new();
4072 gen_set_access_type(ctx, ACCESS_CACHE);
4073 gen_addr_reg_index(ctx, EA);
4074 val = tcg_temp_new();
4075 /* XXX: specification says this should be treated as a store by the MMU */
4076 gen_qemu_ld8u(ctx, val, EA);
4077 gen_qemu_st8(ctx, val, EA);
4078 tcg_temp_free(val);
4079 tcg_temp_free(EA);
4080 #endif /* defined(CONFIG_USER_ONLY) */
4081 }
4082
4083 /* dcdst */
4084 static void gen_dcbst(DisasContext *ctx)
4085 {
4086 /* XXX: specification say this is treated as a load by the MMU */
4087 TCGv t0;
4088 gen_set_access_type(ctx, ACCESS_CACHE);
4089 t0 = tcg_temp_new();
4090 gen_addr_reg_index(ctx, t0);
4091 gen_qemu_ld8u(ctx, t0, t0);
4092 tcg_temp_free(t0);
4093 }
4094
4095 /* dcbt */
4096 static void gen_dcbt(DisasContext *ctx)
4097 {
4098 /* interpreted as no-op */
4099 /* XXX: specification say this is treated as a load by the MMU
4100 * but does not generate any exception
4101 */
4102 }
4103
4104 /* dcbtst */
4105 static void gen_dcbtst(DisasContext *ctx)
4106 {
4107 /* interpreted as no-op */
4108 /* XXX: specification say this is treated as a load by the MMU
4109 * but does not generate any exception
4110 */
4111 }
4112
4113 /* dcbtls */
4114 static void gen_dcbtls(DisasContext *ctx)
4115 {
4116 /* Always fails locking the cache */
4117 TCGv t0 = tcg_temp_new();
4118 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4119 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4120 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4121 tcg_temp_free(t0);
4122 }
4123
4124 /* dcbz */
4125 static void gen_dcbz(DisasContext *ctx)
4126 {
4127 TCGv tcgv_addr;
4128 TCGv_i32 tcgv_op;
4129
4130 gen_set_access_type(ctx, ACCESS_CACHE);
4131 tcgv_addr = tcg_temp_new();
4132 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4133 gen_addr_reg_index(ctx, tcgv_addr);
4134 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4135 tcg_temp_free(tcgv_addr);
4136 tcg_temp_free_i32(tcgv_op);
4137 }
4138
4139 /* dst / dstt */
4140 static void gen_dst(DisasContext *ctx)
4141 {
4142 if (rA(ctx->opcode) == 0) {
4143 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4144 } else {
4145 /* interpreted as no-op */
4146 }
4147 }
4148
4149 /* dstst /dststt */
4150 static void gen_dstst(DisasContext *ctx)
4151 {
4152 if (rA(ctx->opcode) == 0) {
4153 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4154 } else {
4155 /* interpreted as no-op */
4156 }
4157
4158 }
4159
4160 /* dss / dssall */
4161 static void gen_dss(DisasContext *ctx)
4162 {
4163 /* interpreted as no-op */
4164 }
4165
4166 /* icbi */
4167 static void gen_icbi(DisasContext *ctx)
4168 {
4169 TCGv t0;
4170 gen_set_access_type(ctx, ACCESS_CACHE);
4171 t0 = tcg_temp_new();
4172 gen_addr_reg_index(ctx, t0);
4173 gen_helper_icbi(cpu_env, t0);
4174 tcg_temp_free(t0);
4175 }
4176
4177 /* Optional: */
4178 /* dcba */
4179 static void gen_dcba(DisasContext *ctx)
4180 {
4181 /* interpreted as no-op */
4182 /* XXX: specification say this is treated as a store by the MMU
4183 * but does not generate any exception
4184 */
4185 }
4186
4187 /*** Segment register manipulation ***/
4188 /* Supervisor only: */
4189
4190 /* mfsr */
4191 static void gen_mfsr(DisasContext *ctx)
4192 {
4193 #if defined(CONFIG_USER_ONLY)
4194 GEN_PRIV;
4195 #else
4196 TCGv t0;
4197
4198 CHK_SV;
4199 t0 = tcg_const_tl(SR(ctx->opcode));
4200 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4201 tcg_temp_free(t0);
4202 #endif /* defined(CONFIG_USER_ONLY) */
4203 }
4204
4205 /* mfsrin */
4206 static void gen_mfsrin(DisasContext *ctx)
4207 {
4208 #if defined(CONFIG_USER_ONLY)
4209 GEN_PRIV;
4210 #else
4211 TCGv t0;
4212
4213 CHK_SV;
4214 t0 = tcg_temp_new();
4215 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4216 tcg_gen_andi_tl(t0, t0, 0xF);
4217 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4218 tcg_temp_free(t0);
4219 #endif /* defined(CONFIG_USER_ONLY) */
4220 }
4221
4222 /* mtsr */
4223 static void gen_mtsr(DisasContext *ctx)
4224 {
4225 #if defined(CONFIG_USER_ONLY)
4226 GEN_PRIV;
4227 #else
4228 TCGv t0;
4229
4230 CHK_SV;
4231 t0 = tcg_const_tl(SR(ctx->opcode));
4232 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4233 tcg_temp_free(t0);
4234 #endif /* defined(CONFIG_USER_ONLY) */
4235 }
4236
4237 /* mtsrin */
4238 static void gen_mtsrin(DisasContext *ctx)
4239 {
4240 #if defined(CONFIG_USER_ONLY)
4241 GEN_PRIV;
4242 #else
4243 TCGv t0;
4244 CHK_SV;
4245
4246 t0 = tcg_temp_new();
4247 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4248 tcg_gen_andi_tl(t0, t0, 0xF);
4249 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4250 tcg_temp_free(t0);
4251 #endif /* defined(CONFIG_USER_ONLY) */
4252 }
4253
4254 #if defined(TARGET_PPC64)
4255 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4256
4257 /* mfsr */
4258 static void gen_mfsr_64b(DisasContext *ctx)
4259 {
4260 #if defined(CONFIG_USER_ONLY)
4261 GEN_PRIV;
4262 #else
4263 TCGv t0;
4264
4265 CHK_SV;
4266 t0 = tcg_const_tl(SR(ctx->opcode));
4267 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4268 tcg_temp_free(t0);
4269 #endif /* defined(CONFIG_USER_ONLY) */
4270 }
4271
4272 /* mfsrin */
4273 static void gen_mfsrin_64b(DisasContext *ctx)
4274 {
4275 #if defined(CONFIG_USER_ONLY)
4276 GEN_PRIV;
4277 #else
4278 TCGv t0;
4279
4280 CHK_SV;
4281 t0 = tcg_temp_new();
4282 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4283 tcg_gen_andi_tl(t0, t0, 0xF);
4284 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4285 tcg_temp_free(t0);
4286 #endif /* defined(CONFIG_USER_ONLY) */
4287 }
4288
4289 /* mtsr */
4290 static void gen_mtsr_64b(DisasContext *ctx)
4291 {
4292 #if defined(CONFIG_USER_ONLY)
4293 GEN_PRIV;
4294 #else
4295 TCGv t0;
4296
4297 CHK_SV;
4298 t0 = tcg_const_tl(SR(ctx->opcode));
4299 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4300 tcg_temp_free(t0);
4301 #endif /* defined(CONFIG_USER_ONLY) */
4302 }
4303
4304 /* mtsrin */
4305 static void gen_mtsrin_64b(DisasContext *ctx)
4306 {
4307 #if defined(CONFIG_USER_ONLY)
4308 GEN_PRIV;
4309 #else
4310 TCGv t0;
4311
4312 CHK_SV;
4313 t0 = tcg_temp_new();
4314 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4315 tcg_gen_andi_tl(t0, t0, 0xF);
4316 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4317 tcg_temp_free(t0);
4318 #endif /* defined(CONFIG_USER_ONLY) */
4319 }
4320
4321 /* slbmte */
4322 static void gen_slbmte(DisasContext *ctx)
4323 {
4324 #if defined(CONFIG_USER_ONLY)
4325 GEN_PRIV;
4326 #else
4327 CHK_SV;
4328
4329 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4330 cpu_gpr[rS(ctx->opcode)]);
4331 #endif /* defined(CONFIG_USER_ONLY) */
4332 }
4333
4334 static void gen_slbmfee(DisasContext *ctx)
4335 {
4336 #if defined(CONFIG_USER_ONLY)
4337 GEN_PRIV;
4338 #else
4339 CHK_SV;
4340
4341 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4342 cpu_gpr[rB(ctx->opcode)]);
4343 #endif /* defined(CONFIG_USER_ONLY) */
4344 }
4345
4346 static void gen_slbmfev(DisasContext *ctx)
4347 {
4348 #if defined(CONFIG_USER_ONLY)
4349 GEN_PRIV;
4350 #else
4351 CHK_SV;
4352
4353 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4354 cpu_gpr[rB(ctx->opcode)]);
4355 #endif /* defined(CONFIG_USER_ONLY) */
4356 }
4357
4358 static void gen_slbfee_(DisasContext *ctx)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4362 #else
4363 TCGLabel *l1, *l2;
4364
4365 if (unlikely(ctx->pr)) {
4366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4367 return;
4368 }
4369 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4370 cpu_gpr[rB(ctx->opcode)]);
4371 l1 = gen_new_label();
4372 l2 = gen_new_label();
4373 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4374 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4375 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4376 tcg_gen_br(l2);
4377 gen_set_label(l1);
4378 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4379 gen_set_label(l2);
4380 #endif
4381 }
4382 #endif /* defined(TARGET_PPC64) */
4383
4384 /*** Lookaside buffer management ***/
4385 /* Optional & supervisor only: */
4386
4387 /* tlbia */
4388 static void gen_tlbia(DisasContext *ctx)
4389 {
4390 #if defined(CONFIG_USER_ONLY)
4391 GEN_PRIV;
4392 #else
4393 CHK_HV;
4394
4395 gen_helper_tlbia(cpu_env);
4396 #endif /* defined(CONFIG_USER_ONLY) */
4397 }
4398
4399 /* tlbiel */
4400 static void gen_tlbiel(DisasContext *ctx)
4401 {
4402 #if defined(CONFIG_USER_ONLY)
4403 GEN_PRIV;
4404 #else
4405 CHK_SV;
4406
4407 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4408 #endif /* defined(CONFIG_USER_ONLY) */
4409 }
4410
4411 /* tlbie */
4412 static void gen_tlbie(DisasContext *ctx)
4413 {
4414 #if defined(CONFIG_USER_ONLY)
4415 GEN_PRIV;
4416 #else
4417 CHK_HV;
4418
4419 if (NARROW_MODE(ctx)) {
4420 TCGv t0 = tcg_temp_new();
4421 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4422 gen_helper_tlbie(cpu_env, t0);
4423 tcg_temp_free(t0);
4424 } else {
4425 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4426 }
4427 #endif /* defined(CONFIG_USER_ONLY) */
4428 }
4429
4430 /* tlbsync */
4431 static void gen_tlbsync(DisasContext *ctx)
4432 {
4433 #if defined(CONFIG_USER_ONLY)
4434 GEN_PRIV;
4435 #else
4436 CHK_HV;
4437
4438 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4439 * embedded however needs to deal with tlbsync. We don't try to be
4440 * fancy and swallow the overhead of checking for both.
4441 */
4442 gen_check_tlb_flush(ctx);
4443 #endif /* defined(CONFIG_USER_ONLY) */
4444 }
4445
4446 #if defined(TARGET_PPC64)
4447 /* slbia */
4448 static void gen_slbia(DisasContext *ctx)
4449 {
4450 #if defined(CONFIG_USER_ONLY)
4451 GEN_PRIV;
4452 #else
4453 CHK_SV;
4454
4455 gen_helper_slbia(cpu_env);
4456 #endif /* defined(CONFIG_USER_ONLY) */
4457 }
4458
4459 /* slbie */
4460 static void gen_slbie(DisasContext *ctx)
4461 {
4462 #if defined(CONFIG_USER_ONLY)
4463 GEN_PRIV;
4464 #else
4465 CHK_SV;
4466
4467 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4468 #endif /* defined(CONFIG_USER_ONLY) */
4469 }
4470 #endif /* defined(TARGET_PPC64) */
4471
4472 /*** External control ***/
4473 /* Optional: */
4474
4475 /* eciwx */
4476 static void gen_eciwx(DisasContext *ctx)
4477 {
4478 TCGv t0;
4479 /* Should check EAR[E] ! */
4480 gen_set_access_type(ctx, ACCESS_EXT);
4481 t0 = tcg_temp_new();
4482 gen_addr_reg_index(ctx, t0);
4483 gen_check_align(ctx, t0, 0x03);
4484 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4485 tcg_temp_free(t0);
4486 }
4487
4488 /* ecowx */
4489 static void gen_ecowx(DisasContext *ctx)
4490 {
4491 TCGv t0;
4492 /* Should check EAR[E] ! */
4493 gen_set_access_type(ctx, ACCESS_EXT);
4494 t0 = tcg_temp_new();
4495 gen_addr_reg_index(ctx, t0);
4496 gen_check_align(ctx, t0, 0x03);
4497 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4498 tcg_temp_free(t0);
4499 }
4500
4501 /* PowerPC 601 specific instructions */
4502
4503 /* abs - abs. */
4504 static void gen_abs(DisasContext *ctx)
4505 {
4506 TCGLabel *l1 = gen_new_label();
4507 TCGLabel *l2 = gen_new_label();
4508 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4509 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4510 tcg_gen_br(l2);
4511 gen_set_label(l1);
4512 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4513 gen_set_label(l2);
4514 if (unlikely(Rc(ctx->opcode) != 0))
4515 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4516 }
4517
4518 /* abso - abso. */
4519 static void gen_abso(DisasContext *ctx)
4520 {
4521 TCGLabel *l1 = gen_new_label();
4522 TCGLabel *l2 = gen_new_label();
4523 TCGLabel *l3 = gen_new_label();
4524 /* Start with XER OV disabled, the most likely case */
4525 tcg_gen_movi_tl(cpu_ov, 0);
4526 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4527 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4528 tcg_gen_movi_tl(cpu_ov, 1);
4529 tcg_gen_movi_tl(cpu_so, 1);
4530 tcg_gen_br(l2);
4531 gen_set_label(l1);
4532 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4533 tcg_gen_br(l3);
4534 gen_set_label(l2);
4535 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4536 gen_set_label(l3);
4537 if (unlikely(Rc(ctx->opcode) != 0))
4538 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4539 }
4540
4541 /* clcs */
4542 static void gen_clcs(DisasContext *ctx)
4543 {
4544 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4545 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4546 tcg_temp_free_i32(t0);
4547 /* Rc=1 sets CR0 to an undefined state */
4548 }
4549
4550 /* div - div. */
4551 static void gen_div(DisasContext *ctx)
4552 {
4553 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4554 cpu_gpr[rB(ctx->opcode)]);
4555 if (unlikely(Rc(ctx->opcode) != 0))
4556 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4557 }
4558
4559 /* divo - divo. */
4560 static void gen_divo(DisasContext *ctx)
4561 {
4562 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4563 cpu_gpr[rB(ctx->opcode)]);
4564 if (unlikely(Rc(ctx->opcode) != 0))
4565 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4566 }
4567
4568 /* divs - divs. */
4569 static void gen_divs(DisasContext *ctx)
4570 {
4571 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4572 cpu_gpr[rB(ctx->opcode)]);
4573 if (unlikely(Rc(ctx->opcode) != 0))
4574 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4575 }
4576
4577 /* divso - divso. */
4578 static void gen_divso(DisasContext *ctx)
4579 {
4580 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4581 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4582 if (unlikely(Rc(ctx->opcode) != 0))
4583 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4584 }
4585
4586 /* doz - doz. */
4587 static void gen_doz(DisasContext *ctx)
4588 {
4589 TCGLabel *l1 = gen_new_label();
4590 TCGLabel *l2 = gen_new_label();
4591 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4592 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4593 tcg_gen_br(l2);
4594 gen_set_label(l1);
4595 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4596 gen_set_label(l2);
4597 if (unlikely(Rc(ctx->opcode) != 0))
4598 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4599 }
4600
4601 /* dozo - dozo. */
4602 static void gen_dozo(DisasContext *ctx)
4603 {
4604 TCGLabel *l1 = gen_new_label();
4605 TCGLabel *l2 = gen_new_label();
4606 TCGv t0 = tcg_temp_new();
4607 TCGv t1 = tcg_temp_new();
4608 TCGv t2 = tcg_temp_new();
4609 /* Start with XER OV disabled, the most likely case */
4610 tcg_gen_movi_tl(cpu_ov, 0);
4611 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4612 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4613 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4614 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4615 tcg_gen_andc_tl(t1, t1, t2);
4616 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4617 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4618 tcg_gen_movi_tl(cpu_ov, 1);
4619 tcg_gen_movi_tl(cpu_so, 1);
4620 tcg_gen_br(l2);
4621 gen_set_label(l1);
4622 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4623 gen_set_label(l2);
4624 tcg_temp_free(t0);
4625 tcg_temp_free(t1);
4626 tcg_temp_free(t2);
4627 if (unlikely(Rc(ctx->opcode) != 0))
4628 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4629 }
4630
4631 /* dozi */
4632 static void gen_dozi(DisasContext *ctx)
4633 {
4634 target_long simm = SIMM(ctx->opcode);
4635 TCGLabel *l1 = gen_new_label();
4636 TCGLabel *l2 = gen_new_label();
4637 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4638 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4639 tcg_gen_br(l2);
4640 gen_set_label(l1);
4641 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4642 gen_set_label(l2);
4643 if (unlikely(Rc(ctx->opcode) != 0))
4644 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4645 }
4646
4647 /* lscbx - lscbx. */
4648 static void gen_lscbx(DisasContext *ctx)
4649 {
4650 TCGv t0 = tcg_temp_new();
4651 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4652 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4653 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4654
4655 gen_addr_reg_index(ctx, t0);
4656 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4657 tcg_temp_free_i32(t1);
4658 tcg_temp_free_i32(t2);
4659 tcg_temp_free_i32(t3);
4660 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4661 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4662 if (unlikely(Rc(ctx->opcode) != 0))
4663 gen_set_Rc0(ctx, t0);
4664 tcg_temp_free(t0);
4665 }
4666
4667 /* maskg - maskg. */
4668 static void gen_maskg(DisasContext *ctx)
4669 {
4670 TCGLabel *l1 = gen_new_label();
4671 TCGv t0 = tcg_temp_new();
4672 TCGv t1 = tcg_temp_new();
4673 TCGv t2 = tcg_temp_new();
4674 TCGv t3 = tcg_temp_new();
4675 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4676 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4677 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4678 tcg_gen_addi_tl(t2, t0, 1);
4679 tcg_gen_shr_tl(t2, t3, t2);
4680 tcg_gen_shr_tl(t3, t3, t1);
4681 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4682 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4683 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4684 gen_set_label(l1);
4685 tcg_temp_free(t0);
4686 tcg_temp_free(t1);
4687 tcg_temp_free(t2);
4688 tcg_temp_free(t3);
4689 if (unlikely(Rc(ctx->opcode) != 0))
4690 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4691 }
4692
4693 /* maskir - maskir. */
4694 static void gen_maskir(DisasContext *ctx)
4695 {
4696 TCGv t0 = tcg_temp_new();
4697 TCGv t1 = tcg_temp_new();
4698 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4699 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4700 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4701 tcg_temp_free(t0);
4702 tcg_temp_free(t1);
4703 if (unlikely(Rc(ctx->opcode) != 0))
4704 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4705 }
4706
4707 /* mul - mul. */
4708 static void gen_mul(DisasContext *ctx)
4709 {
4710 TCGv_i64 t0 = tcg_temp_new_i64();
4711 TCGv_i64 t1 = tcg_temp_new_i64();
4712 TCGv t2 = tcg_temp_new();
4713 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4714 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4715 tcg_gen_mul_i64(t0, t0, t1);
4716 tcg_gen_trunc_i64_tl(t2, t0);
4717 gen_store_spr(SPR_MQ, t2);
4718 tcg_gen_shri_i64(t1, t0, 32);
4719 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4720 tcg_temp_free_i64(t0);
4721 tcg_temp_free_i64(t1);
4722 tcg_temp_free(t2);
4723 if (unlikely(Rc(ctx->opcode) != 0))
4724 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4725 }
4726
4727 /* mulo - mulo. */
4728 static void gen_mulo(DisasContext *ctx)
4729 {
4730 TCGLabel *l1 = gen_new_label();
4731 TCGv_i64 t0 = tcg_temp_new_i64();
4732 TCGv_i64 t1 = tcg_temp_new_i64();
4733 TCGv t2 = tcg_temp_new();
4734 /* Start with XER OV disabled, the most likely case */
4735 tcg_gen_movi_tl(cpu_ov, 0);
4736 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4737 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4738 tcg_gen_mul_i64(t0, t0, t1);
4739 tcg_gen_trunc_i64_tl(t2, t0);
4740 gen_store_spr(SPR_MQ, t2);
4741 tcg_gen_shri_i64(t1, t0, 32);
4742 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4743 tcg_gen_ext32s_i64(t1, t0);
4744 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4745 tcg_gen_movi_tl(cpu_ov, 1);
4746 tcg_gen_movi_tl(cpu_so, 1);
4747 gen_set_label(l1);
4748 tcg_temp_free_i64(t0);
4749 tcg_temp_free_i64(t1);
4750 tcg_temp_free(t2);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4753 }
4754
4755 /* nabs - nabs. */
4756 static void gen_nabs(DisasContext *ctx)
4757 {
4758 TCGLabel *l1 = gen_new_label();
4759 TCGLabel *l2 = gen_new_label();
4760 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4761 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4762 tcg_gen_br(l2);
4763 gen_set_label(l1);
4764 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4765 gen_set_label(l2);
4766 if (unlikely(Rc(ctx->opcode) != 0))
4767 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4768 }
4769
4770 /* nabso - nabso. */
4771 static void gen_nabso(DisasContext *ctx)
4772 {
4773 TCGLabel *l1 = gen_new_label();
4774 TCGLabel *l2 = gen_new_label();
4775 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4777 tcg_gen_br(l2);
4778 gen_set_label(l1);
4779 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4780 gen_set_label(l2);
4781 /* nabs never overflows */
4782 tcg_gen_movi_tl(cpu_ov, 0);
4783 if (unlikely(Rc(ctx->opcode) != 0))
4784 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4785 }
4786
4787 /* rlmi - rlmi. */
4788 static void gen_rlmi(DisasContext *ctx)
4789 {
4790 uint32_t mb = MB(ctx->opcode);
4791 uint32_t me = ME(ctx->opcode);
4792 TCGv t0 = tcg_temp_new();
4793 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4794 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4795 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4796 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4797 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4798 tcg_temp_free(t0);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4801 }
4802
4803 /* rrib - rrib. */
4804 static void gen_rrib(DisasContext *ctx)
4805 {
4806 TCGv t0 = tcg_temp_new();
4807 TCGv t1 = tcg_temp_new();
4808 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4809 tcg_gen_movi_tl(t1, 0x80000000);
4810 tcg_gen_shr_tl(t1, t1, t0);
4811 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4812 tcg_gen_and_tl(t0, t0, t1);
4813 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4814 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4815 tcg_temp_free(t0);
4816 tcg_temp_free(t1);
4817 if (unlikely(Rc(ctx->opcode) != 0))
4818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4819 }
4820
4821 /* sle - sle. */
4822 static void gen_sle(DisasContext *ctx)
4823 {
4824 TCGv t0 = tcg_temp_new();
4825 TCGv t1 = tcg_temp_new();
4826 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4827 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4828 tcg_gen_subfi_tl(t1, 32, t1);
4829 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4830 tcg_gen_or_tl(t1, t0, t1);
4831 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4832 gen_store_spr(SPR_MQ, t1);
4833 tcg_temp_free(t0);
4834 tcg_temp_free(t1);
4835 if (unlikely(Rc(ctx->opcode) != 0))
4836 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4837 }
4838
4839 /* sleq - sleq. */
4840 static void gen_sleq(DisasContext *ctx)
4841 {
4842 TCGv t0 = tcg_temp_new();
4843 TCGv t1 = tcg_temp_new();
4844 TCGv t2 = tcg_temp_new();
4845 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4846 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4847 tcg_gen_shl_tl(t2, t2, t0);
4848 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4849 gen_load_spr(t1, SPR_MQ);
4850 gen_store_spr(SPR_MQ, t0);
4851 tcg_gen_and_tl(t0, t0, t2);
4852 tcg_gen_andc_tl(t1, t1, t2);
4853 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4854 tcg_temp_free(t0);
4855 tcg_temp_free(t1);
4856 tcg_temp_free(t2);
4857 if (unlikely(Rc(ctx->opcode) != 0))
4858 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4859 }
4860
4861 /* sliq - sliq. */
4862 static void gen_sliq(DisasContext *ctx)
4863 {
4864 int sh = SH(ctx->opcode);
4865 TCGv t0 = tcg_temp_new();
4866 TCGv t1 = tcg_temp_new();
4867 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4868 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4869 tcg_gen_or_tl(t1, t0, t1);
4870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4871 gen_store_spr(SPR_MQ, t1);
4872 tcg_temp_free(t0);
4873 tcg_temp_free(t1);
4874 if (unlikely(Rc(ctx->opcode) != 0))
4875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4876 }
4877
4878 /* slliq - slliq. */
4879 static void gen_slliq(DisasContext *ctx)
4880 {
4881 int sh = SH(ctx->opcode);
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4885 gen_load_spr(t1, SPR_MQ);
4886 gen_store_spr(SPR_MQ, t0);
4887 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4888 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4889 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4890 tcg_temp_free(t0);
4891 tcg_temp_free(t1);
4892 if (unlikely(Rc(ctx->opcode) != 0))
4893 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4894 }
4895
4896 /* sllq - sllq. */
4897 static void gen_sllq(DisasContext *ctx)
4898 {
4899 TCGLabel *l1 = gen_new_label();
4900 TCGLabel *l2 = gen_new_label();
4901 TCGv t0 = tcg_temp_local_new();
4902 TCGv t1 = tcg_temp_local_new();
4903 TCGv t2 = tcg_temp_local_new();
4904 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4905 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4906 tcg_gen_shl_tl(t1, t1, t2);
4907 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4908 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4909 gen_load_spr(t0, SPR_MQ);
4910 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4911 tcg_gen_br(l2);
4912 gen_set_label(l1);
4913 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4914 gen_load_spr(t2, SPR_MQ);
4915 tcg_gen_andc_tl(t1, t2, t1);
4916 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4917 gen_set_label(l2);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 tcg_temp_free(t2);
4921 if (unlikely(Rc(ctx->opcode) != 0))
4922 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4923 }
4924
4925 /* slq - slq. */
4926 static void gen_slq(DisasContext *ctx)
4927 {
4928 TCGLabel *l1 = gen_new_label();
4929 TCGv t0 = tcg_temp_new();
4930 TCGv t1 = tcg_temp_new();
4931 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4932 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4933 tcg_gen_subfi_tl(t1, 32, t1);
4934 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4935 tcg_gen_or_tl(t1, t0, t1);
4936 gen_store_spr(SPR_MQ, t1);
4937 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4939 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4940 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4941 gen_set_label(l1);
4942 tcg_temp_free(t0);
4943 tcg_temp_free(t1);
4944 if (unlikely(Rc(ctx->opcode) != 0))
4945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4946 }
4947
4948 /* sraiq - sraiq. */
4949 static void gen_sraiq(DisasContext *ctx)
4950 {
4951 int sh = SH(ctx->opcode);
4952 TCGLabel *l1 = gen_new_label();
4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4956 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4957 tcg_gen_or_tl(t0, t0, t1);
4958 gen_store_spr(SPR_MQ, t0);
4959 tcg_gen_movi_tl(cpu_ca, 0);
4960 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4961 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4962 tcg_gen_movi_tl(cpu_ca, 1);
4963 gen_set_label(l1);
4964 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4965 tcg_temp_free(t0);
4966 tcg_temp_free(t1);
4967 if (unlikely(Rc(ctx->opcode) != 0))
4968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4969 }
4970
4971 /* sraq - sraq. */
4972 static void gen_sraq(DisasContext *ctx)
4973 {
4974 TCGLabel *l1 = gen_new_label();
4975 TCGLabel *l2 = gen_new_label();
4976 TCGv t0 = tcg_temp_new();
4977 TCGv t1 = tcg_temp_local_new();
4978 TCGv t2 = tcg_temp_local_new();
4979 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4980 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4981 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4982 tcg_gen_subfi_tl(t2, 32, t2);
4983 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4984 tcg_gen_or_tl(t0, t0, t2);
4985 gen_store_spr(SPR_MQ, t0);
4986 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4987 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4988 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4989 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4990 gen_set_label(l1);
4991 tcg_temp_free(t0);
4992 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4993 tcg_gen_movi_tl(cpu_ca, 0);
4994 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4995 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4996 tcg_gen_movi_tl(cpu_ca, 1);
4997 gen_set_label(l2);
4998 tcg_temp_free(t1);
4999 tcg_temp_free(t2);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003
5004 /* sre - sre. */
5005 static void gen_sre(DisasContext *ctx)
5006 {
5007 TCGv t0 = tcg_temp_new();
5008 TCGv t1 = tcg_temp_new();
5009 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5010 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5011 tcg_gen_subfi_tl(t1, 32, t1);
5012 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5013 tcg_gen_or_tl(t1, t0, t1);
5014 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5015 gen_store_spr(SPR_MQ, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* srea - srea. */
5023 static void gen_srea(DisasContext *ctx)
5024 {
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5028 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5029 gen_store_spr(SPR_MQ, t0);
5030 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5031 tcg_temp_free(t0);
5032 tcg_temp_free(t1);
5033 if (unlikely(Rc(ctx->opcode) != 0))
5034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5035 }
5036
5037 /* sreq */
5038 static void gen_sreq(DisasContext *ctx)
5039 {
5040 TCGv t0 = tcg_temp_new();
5041 TCGv t1 = tcg_temp_new();
5042 TCGv t2 = tcg_temp_new();
5043 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5044 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5045 tcg_gen_shr_tl(t1, t1, t0);
5046 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5047 gen_load_spr(t2, SPR_MQ);
5048 gen_store_spr(SPR_MQ, t0);
5049 tcg_gen_and_tl(t0, t0, t1);
5050 tcg_gen_andc_tl(t2, t2, t1);
5051 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 tcg_temp_free(t2);
5055 if (unlikely(Rc(ctx->opcode) != 0))
5056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5057 }
5058
5059 /* sriq */
5060 static void gen_sriq(DisasContext *ctx)
5061 {
5062 int sh = SH(ctx->opcode);
5063 TCGv t0 = tcg_temp_new();
5064 TCGv t1 = tcg_temp_new();
5065 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5066 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5067 tcg_gen_or_tl(t1, t0, t1);
5068 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5069 gen_store_spr(SPR_MQ, t1);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
5072 if (unlikely(Rc(ctx->opcode) != 0))
5073 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5074 }
5075
5076 /* srliq */
5077 static void gen_srliq(DisasContext *ctx)
5078 {
5079 int sh = SH(ctx->opcode);
5080 TCGv t0 = tcg_temp_new();
5081 TCGv t1 = tcg_temp_new();
5082 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5083 gen_load_spr(t1, SPR_MQ);
5084 gen_store_spr(SPR_MQ, t0);
5085 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5086 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5087 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5088 tcg_temp_free(t0);
5089 tcg_temp_free(t1);
5090 if (unlikely(Rc(ctx->opcode) != 0))
5091 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5092 }
5093
5094 /* srlq */
5095 static void gen_srlq(DisasContext *ctx)
5096 {
5097 TCGLabel *l1 = gen_new_label();
5098 TCGLabel *l2 = gen_new_label();
5099 TCGv t0 = tcg_temp_local_new();
5100 TCGv t1 = tcg_temp_local_new();
5101 TCGv t2 = tcg_temp_local_new();
5102 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5103 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5104 tcg_gen_shr_tl(t2, t1, t2);
5105 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5106 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5107 gen_load_spr(t0, SPR_MQ);
5108 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5109 tcg_gen_br(l2);
5110 gen_set_label(l1);
5111 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5112 tcg_gen_and_tl(t0, t0, t2);
5113 gen_load_spr(t1, SPR_MQ);
5114 tcg_gen_andc_tl(t1, t1, t2);
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 gen_set_label(l2);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
5119 tcg_temp_free(t2);
5120 if (unlikely(Rc(ctx->opcode) != 0))
5121 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5122 }
5123
5124 /* srq */
5125 static void gen_srq(DisasContext *ctx)
5126 {
5127 TCGLabel *l1 = gen_new_label();
5128 TCGv t0 = tcg_temp_new();
5129 TCGv t1 = tcg_temp_new();
5130 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5132 tcg_gen_subfi_tl(t1, 32, t1);
5133 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5134 tcg_gen_or_tl(t1, t0, t1);
5135 gen_store_spr(SPR_MQ, t1);
5136 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5137 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5138 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5139 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5140 gen_set_label(l1);
5141 tcg_temp_free(t0);
5142 tcg_temp_free(t1);
5143 if (unlikely(Rc(ctx->opcode) != 0))
5144 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5145 }
5146
5147 /* PowerPC 602 specific instructions */
5148
5149 /* dsa */
5150 static void gen_dsa(DisasContext *ctx)
5151 {
5152 /* XXX: TODO */
5153 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5154 }
5155
5156 /* esa */
5157 static void gen_esa(DisasContext *ctx)
5158 {
5159 /* XXX: TODO */
5160 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5161 }
5162
5163 /* mfrom */
5164 static void gen_mfrom(DisasContext *ctx)
5165 {
5166 #if defined(CONFIG_USER_ONLY)
5167 GEN_PRIV;
5168 #else
5169 CHK_SV;
5170 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5171 #endif /* defined(CONFIG_USER_ONLY) */
5172 }
5173
5174 /* 602 - 603 - G2 TLB management */
5175
5176 /* tlbld */
5177 static void gen_tlbld_6xx(DisasContext *ctx)
5178 {
5179 #if defined(CONFIG_USER_ONLY)
5180 GEN_PRIV;
5181 #else
5182 CHK_SV;
5183 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5184 #endif /* defined(CONFIG_USER_ONLY) */
5185 }
5186
5187 /* tlbli */
5188 static void gen_tlbli_6xx(DisasContext *ctx)
5189 {
5190 #if defined(CONFIG_USER_ONLY)
5191 GEN_PRIV;
5192 #else
5193 CHK_SV;
5194 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5195 #endif /* defined(CONFIG_USER_ONLY) */
5196 }
5197
5198 /* 74xx TLB management */
5199
5200 /* tlbld */
5201 static void gen_tlbld_74xx(DisasContext *ctx)
5202 {
5203 #if defined(CONFIG_USER_ONLY)
5204 GEN_PRIV;
5205 #else
5206 CHK_SV;
5207 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5208 #endif /* defined(CONFIG_USER_ONLY) */
5209 }
5210
5211 /* tlbli */
5212 static void gen_tlbli_74xx(DisasContext *ctx)
5213 {
5214 #if defined(CONFIG_USER_ONLY)
5215 GEN_PRIV;
5216 #else
5217 CHK_SV;
5218 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5219 #endif /* defined(CONFIG_USER_ONLY) */
5220 }
5221
5222 /* POWER instructions not in PowerPC 601 */
5223
5224 /* clf */
5225 static void gen_clf(DisasContext *ctx)
5226 {
5227 /* Cache line flush: implemented as no-op */
5228 }
5229
5230 /* cli */
5231 static void gen_cli(DisasContext *ctx)
5232 {
5233 #if defined(CONFIG_USER_ONLY)
5234 GEN_PRIV;
5235 #else
5236 /* Cache line invalidate: privileged and treated as no-op */
5237 CHK_SV;
5238 #endif /* defined(CONFIG_USER_ONLY) */
5239 }
5240
5241 /* dclst */
5242 static void gen_dclst(DisasContext *ctx)
5243 {
5244 /* Data cache line store: treated as no-op */
5245 }
5246
5247 static void gen_mfsri(DisasContext *ctx)
5248 {
5249 #if defined(CONFIG_USER_ONLY)
5250 GEN_PRIV;
5251 #else
5252 int ra = rA(ctx->opcode);
5253 int rd = rD(ctx->opcode);
5254 TCGv t0;
5255
5256 CHK_SV;
5257 t0 = tcg_temp_new();
5258 gen_addr_reg_index(ctx, t0);
5259 tcg_gen_shri_tl(t0, t0, 28);
5260 tcg_gen_andi_tl(t0, t0, 0xF);
5261 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5262 tcg_temp_free(t0);
5263 if (ra != 0 && ra != rd)
5264 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5265 #endif /* defined(CONFIG_USER_ONLY) */
5266 }
5267
5268 static void gen_rac(DisasContext *ctx)
5269 {
5270 #if defined(CONFIG_USER_ONLY)
5271 GEN_PRIV;
5272 #else
5273 TCGv t0;
5274
5275 CHK_SV;
5276 t0 = tcg_temp_new();
5277 gen_addr_reg_index(ctx, t0);
5278 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5279 tcg_temp_free(t0);
5280 #endif /* defined(CONFIG_USER_ONLY) */
5281 }
5282
5283 static void gen_rfsvc(DisasContext *ctx)
5284 {
5285 #if defined(CONFIG_USER_ONLY)
5286 GEN_PRIV;
5287 #else
5288 CHK_SV;
5289
5290 gen_helper_rfsvc(cpu_env);
5291 gen_sync_exception(ctx);
5292 #endif /* defined(CONFIG_USER_ONLY) */
5293 }
5294
5295 /* svc is not implemented for now */
5296
5297 /* BookE specific instructions */
5298
5299 /* XXX: not implemented on 440 ? */
5300 static void gen_mfapidi(DisasContext *ctx)
5301 {
5302 /* XXX: TODO */
5303 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5304 }
5305
5306 /* XXX: not implemented on 440 ? */
5307 static void gen_tlbiva(DisasContext *ctx)
5308 {
5309 #if defined(CONFIG_USER_ONLY)
5310 GEN_PRIV;
5311 #else
5312 TCGv t0;
5313
5314 CHK_SV;
5315 t0 = tcg_temp_new();
5316 gen_addr_reg_index(ctx, t0);
5317 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5318 tcg_temp_free(t0);
5319 #endif /* defined(CONFIG_USER_ONLY) */
5320 }
5321
5322 /* All 405 MAC instructions are translated here */
5323 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5324 int ra, int rb, int rt, int Rc)
5325 {
5326 TCGv t0, t1;
5327
5328 t0 = tcg_temp_local_new();
5329 t1 = tcg_temp_local_new();
5330
5331 switch (opc3 & 0x0D) {
5332 case 0x05:
5333 /* macchw - macchw. - macchwo - macchwo. */
5334 /* macchws - macchws. - macchwso - macchwso. */
5335 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5336 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5337 /* mulchw - mulchw. */
5338 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5339 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5340 tcg_gen_ext16s_tl(t1, t1);
5341 break;
5342 case 0x04:
5343 /* macchwu - macchwu. - macchwuo - macchwuo. */
5344 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5345 /* mulchwu - mulchwu. */
5346 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5347 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5348 tcg_gen_ext16u_tl(t1, t1);
5349 break;
5350 case 0x01:
5351 /* machhw - machhw. - machhwo - machhwo. */
5352 /* machhws - machhws. - machhwso - machhwso. */
5353 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5354 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5355 /* mulhhw - mulhhw. */
5356 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5357 tcg_gen_ext16s_tl(t0, t0);
5358 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5359 tcg_gen_ext16s_tl(t1, t1);
5360 break;
5361 case 0x00:
5362 /* machhwu - machhwu. - machhwuo - machhwuo. */
5363 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5364 /* mulhhwu - mulhhwu. */
5365 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5366 tcg_gen_ext16u_tl(t0, t0);
5367 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5368 tcg_gen_ext16u_tl(t1, t1);
5369 break;
5370 case 0x0D:
5371 /* maclhw - maclhw. - maclhwo - maclhwo. */
5372 /* maclhws - maclhws. - maclhwso - maclhwso. */
5373 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5374 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5375 /* mullhw - mullhw. */
5376 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5377 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5378 break;
5379 case 0x0C:
5380 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5381 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5382 /* mullhwu - mullhwu. */
5383 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5384 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5385 break;
5386 }
5387 if (opc2 & 0x04) {
5388 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5389 tcg_gen_mul_tl(t1, t0, t1);
5390 if (opc2 & 0x02) {
5391 /* nmultiply-and-accumulate (0x0E) */
5392 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5393 } else {
5394 /* multiply-and-accumulate (0x0C) */
5395 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5396 }
5397
5398 if (opc3 & 0x12) {
5399 /* Check overflow and/or saturate */
5400 TCGLabel *l1 = gen_new_label();
5401
5402 if (opc3 & 0x10) {
5403 /* Start with XER OV disabled, the most likely case */
5404 tcg_gen_movi_tl(cpu_ov, 0);
5405 }
5406 if (opc3 & 0x01) {
5407 /* Signed */
5408 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5409 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5410 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5411 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5412 if (opc3 & 0x02) {
5413 /* Saturate */
5414 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5415 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5416 }
5417 } else {
5418 /* Unsigned */
5419 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5420 if (opc3 & 0x02) {
5421 /* Saturate */
5422 tcg_gen_movi_tl(t0, UINT32_MAX);
5423 }
5424 }
5425 if (opc3 & 0x10) {
5426 /* Check overflow */
5427 tcg_gen_movi_tl(cpu_ov, 1);
5428 tcg_gen_movi_tl(cpu_so, 1);
5429 }
5430 gen_set_label(l1);
5431 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5432 }
5433 } else {
5434 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5435 }
5436 tcg_temp_free(t0);
5437 tcg_temp_free(t1);
5438 if (unlikely(Rc) != 0) {
5439 /* Update Rc0 */
5440 gen_set_Rc0(ctx, cpu_gpr[rt]);
5441 }
5442 }
5443
5444 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5445 static void glue(gen_, name)(DisasContext *ctx) \
5446 { \
5447 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5448 rD(ctx->opcode), Rc(ctx->opcode)); \
5449 }
5450
5451 /* macchw - macchw. */
5452 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5453 /* macchwo - macchwo. */
5454 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5455 /* macchws - macchws. */
5456 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5457 /* macchwso - macchwso. */
5458 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5459 /* macchwsu - macchwsu. */
5460 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5461 /* macchwsuo - macchwsuo. */
5462 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5463 /* macchwu - macchwu. */
5464 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5465 /* macchwuo - macchwuo. */
5466 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5467 /* machhw - machhw. */
5468 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5469 /* machhwo - machhwo. */
5470 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5471 /* machhws - machhws. */
5472 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5473 /* machhwso - machhwso. */
5474 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5475 /* machhwsu - machhwsu. */
5476 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5477 /* machhwsuo - machhwsuo. */
5478 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5479 /* machhwu - machhwu. */
5480 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5481 /* machhwuo - machhwuo. */
5482 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5483 /* maclhw - maclhw. */
5484 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5485 /* maclhwo - maclhwo. */
5486 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5487 /* maclhws - maclhws. */
5488 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5489 /* maclhwso - maclhwso. */
5490 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5491 /* maclhwu - maclhwu. */
5492 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5493 /* maclhwuo - maclhwuo. */
5494 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5495 /* maclhwsu - maclhwsu. */
5496 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5497 /* maclhwsuo - maclhwsuo. */
5498 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5499 /* nmacchw - nmacchw. */
5500 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5501 /* nmacchwo - nmacchwo. */
5502 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5503 /* nmacchws - nmacchws. */
5504 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5505 /* nmacchwso - nmacchwso. */
5506 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5507 /* nmachhw - nmachhw. */
5508 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5509 /* nmachhwo - nmachhwo. */
5510 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5511 /* nmachhws - nmachhws. */
5512 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5513 /* nmachhwso - nmachhwso. */
5514 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5515 /* nmaclhw - nmaclhw. */
5516 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5517 /* nmaclhwo - nmaclhwo. */
5518 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5519 /* nmaclhws - nmaclhws. */
5520 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5521 /* nmaclhwso - nmaclhwso. */
5522 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5523
5524 /* mulchw - mulchw. */
5525 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5526 /* mulchwu - mulchwu. */
5527 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5528 /* mulhhw - mulhhw. */
5529 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5530 /* mulhhwu - mulhhwu. */
5531 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5532 /* mullhw - mullhw. */
5533 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5534 /* mullhwu - mullhwu. */
5535 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5536
5537 /* mfdcr */
5538 static void gen_mfdcr(DisasContext *ctx)
5539 {
5540 #if defined(CONFIG_USER_ONLY)
5541 GEN_PRIV;
5542 #else
5543 TCGv dcrn;
5544
5545 CHK_SV;
5546 dcrn = tcg_const_tl(SPR(ctx->opcode));
5547 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5548 tcg_temp_free(dcrn);
5549 #endif /* defined(CONFIG_USER_ONLY) */
5550 }
5551
5552 /* mtdcr */
5553 static void gen_mtdcr(DisasContext *ctx)
5554 {
5555 #if defined(CONFIG_USER_ONLY)
5556 GEN_PRIV;
5557 #else
5558 TCGv dcrn;
5559
5560 CHK_SV;
5561 dcrn = tcg_const_tl(SPR(ctx->opcode));
5562 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5563 tcg_temp_free(dcrn);
5564 #endif /* defined(CONFIG_USER_ONLY) */
5565 }
5566
5567 /* mfdcrx */
5568 /* XXX: not implemented on 440 ? */
5569 static void gen_mfdcrx(DisasContext *ctx)
5570 {
5571 #if defined(CONFIG_USER_ONLY)
5572 GEN_PRIV;
5573 #else
5574 CHK_SV;
5575 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5576 cpu_gpr[rA(ctx->opcode)]);
5577 /* Note: Rc update flag set leads to undefined state of Rc0 */
5578 #endif /* defined(CONFIG_USER_ONLY) */
5579 }
5580
5581 /* mtdcrx */
5582 /* XXX: not implemented on 440 ? */
5583 static void gen_mtdcrx(DisasContext *ctx)
5584 {
5585 #if defined(CONFIG_USER_ONLY)
5586 GEN_PRIV;
5587 #else
5588 CHK_SV;
5589 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5590 cpu_gpr[rS(ctx->opcode)]);
5591 /* Note: Rc update flag set leads to undefined state of Rc0 */
5592 #endif /* defined(CONFIG_USER_ONLY) */
5593 }
5594
5595 /* mfdcrux (PPC 460) : user-mode access to DCR */
5596 static void gen_mfdcrux(DisasContext *ctx)
5597 {
5598 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5599 cpu_gpr[rA(ctx->opcode)]);
5600 /* Note: Rc update flag set leads to undefined state of Rc0 */
5601 }
5602
5603 /* mtdcrux (PPC 460) : user-mode access to DCR */
5604 static void gen_mtdcrux(DisasContext *ctx)
5605 {
5606 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5607 cpu_gpr[rS(ctx->opcode)]);
5608 /* Note: Rc update flag set leads to undefined state of Rc0 */
5609 }
5610
5611 /* dccci */
5612 static void gen_dccci(DisasContext *ctx)
5613 {
5614 CHK_SV;
5615 /* interpreted as no-op */
5616 }
5617
5618 /* dcread */
5619 static void gen_dcread(DisasContext *ctx)
5620 {
5621 #if defined(CONFIG_USER_ONLY)
5622 GEN_PRIV;
5623 #else
5624 TCGv EA, val;
5625
5626 CHK_SV;
5627 gen_set_access_type(ctx, ACCESS_CACHE);
5628 EA = tcg_temp_new();
5629 gen_addr_reg_index(ctx, EA);
5630 val = tcg_temp_new();
5631 gen_qemu_ld32u(ctx, val, EA);
5632 tcg_temp_free(val);
5633 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5634 tcg_temp_free(EA);
5635 #endif /* defined(CONFIG_USER_ONLY) */
5636 }
5637
5638 /* icbt */
5639 static void gen_icbt_40x(DisasContext *ctx)
5640 {
5641 /* interpreted as no-op */
5642 /* XXX: specification say this is treated as a load by the MMU
5643 * but does not generate any exception
5644 */
5645 }
5646
5647 /* iccci */
5648 static void gen_iccci(DisasContext *ctx)
5649 {
5650 CHK_SV;
5651 /* interpreted as no-op */
5652 }
5653
5654 /* icread */
5655 static void gen_icread(DisasContext *ctx)
5656 {
5657 CHK_SV;
5658 /* interpreted as no-op */
5659 }
5660
5661 /* rfci (supervisor only) */
5662 static void gen_rfci_40x(DisasContext *ctx)
5663 {
5664 #if defined(CONFIG_USER_ONLY)
5665 GEN_PRIV;
5666 #else
5667 CHK_SV;
5668 /* Restore CPU state */
5669 gen_helper_40x_rfci(cpu_env);
5670 gen_sync_exception(ctx);
5671 #endif /* defined(CONFIG_USER_ONLY) */
5672 }
5673
5674 static void gen_rfci(DisasContext *ctx)
5675 {
5676 #if defined(CONFIG_USER_ONLY)
5677 GEN_PRIV;
5678 #else
5679 CHK_SV;
5680 /* Restore CPU state */
5681 gen_helper_rfci(cpu_env);
5682 gen_sync_exception(ctx);
5683 #endif /* defined(CONFIG_USER_ONLY) */
5684 }
5685
5686 /* BookE specific */
5687
5688 /* XXX: not implemented on 440 ? */
5689 static void gen_rfdi(DisasContext *ctx)
5690 {
5691 #if defined(CONFIG_USER_ONLY)
5692 GEN_PRIV;
5693 #else
5694 CHK_SV;
5695 /* Restore CPU state */
5696 gen_helper_rfdi(cpu_env);
5697 gen_sync_exception(ctx);
5698 #endif /* defined(CONFIG_USER_ONLY) */
5699 }
5700
5701 /* XXX: not implemented on 440 ? */
5702 static void gen_rfmci(DisasContext *ctx)
5703 {
5704 #if defined(CONFIG_USER_ONLY)
5705 GEN_PRIV;
5706 #else
5707 CHK_SV;
5708 /* Restore CPU state */
5709 gen_helper_rfmci(cpu_env);
5710 gen_sync_exception(ctx);
5711 #endif /* defined(CONFIG_USER_ONLY) */
5712 }
5713
5714 /* TLB management - PowerPC 405 implementation */
5715
5716 /* tlbre */
5717 static void gen_tlbre_40x(DisasContext *ctx)
5718 {
5719 #if defined(CONFIG_USER_ONLY)
5720 GEN_PRIV;
5721 #else
5722 CHK_SV;
5723 switch (rB(ctx->opcode)) {
5724 case 0:
5725 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5726 cpu_gpr[rA(ctx->opcode)]);
5727 break;
5728 case 1:
5729 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5730 cpu_gpr[rA(ctx->opcode)]);
5731 break;
5732 default:
5733 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5734 break;
5735 }
5736 #endif /* defined(CONFIG_USER_ONLY) */
5737 }
5738
5739 /* tlbsx - tlbsx. */
5740 static void gen_tlbsx_40x(DisasContext *ctx)
5741 {
5742 #if defined(CONFIG_USER_ONLY)
5743 GEN_PRIV;
5744 #else
5745 TCGv t0;
5746
5747 CHK_SV;
5748 t0 = tcg_temp_new();
5749 gen_addr_reg_index(ctx, t0);
5750 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5751 tcg_temp_free(t0);
5752 if (Rc(ctx->opcode)) {
5753 TCGLabel *l1 = gen_new_label();
5754 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5755 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5756 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5757 gen_set_label(l1);
5758 }
5759 #endif /* defined(CONFIG_USER_ONLY) */
5760 }
5761
5762 /* tlbwe */
5763 static void gen_tlbwe_40x(DisasContext *ctx)
5764 {
5765 #if defined(CONFIG_USER_ONLY)
5766 GEN_PRIV;
5767 #else
5768 CHK_SV;
5769
5770 switch (rB(ctx->opcode)) {
5771 case 0:
5772 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5773 cpu_gpr[rS(ctx->opcode)]);
5774 break;
5775 case 1:
5776 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5777 cpu_gpr[rS(ctx->opcode)]);
5778 break;
5779 default:
5780 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5781 break;
5782 }
5783 #endif /* defined(CONFIG_USER_ONLY) */
5784 }
5785
5786 /* TLB management - PowerPC 440 implementation */
5787
5788 /* tlbre */
5789 static void gen_tlbre_440(DisasContext *ctx)
5790 {
5791 #if defined(CONFIG_USER_ONLY)
5792 GEN_PRIV;
5793 #else
5794 CHK_SV;
5795
5796 switch (rB(ctx->opcode)) {
5797 case 0:
5798 case 1:
5799 case 2:
5800 {
5801 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5802 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5803 t0, cpu_gpr[rA(ctx->opcode)]);
5804 tcg_temp_free_i32(t0);
5805 }
5806 break;
5807 default:
5808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5809 break;
5810 }
5811 #endif /* defined(CONFIG_USER_ONLY) */
5812 }
5813
5814 /* tlbsx - tlbsx. */
5815 static void gen_tlbsx_440(DisasContext *ctx)
5816 {
5817 #if defined(CONFIG_USER_ONLY)
5818 GEN_PRIV;
5819 #else
5820 TCGv t0;
5821
5822 CHK_SV;
5823 t0 = tcg_temp_new();
5824 gen_addr_reg_index(ctx, t0);
5825 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5826 tcg_temp_free(t0);
5827 if (Rc(ctx->opcode)) {
5828 TCGLabel *l1 = gen_new_label();
5829 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5830 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5831 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5832 gen_set_label(l1);
5833 }
5834 #endif /* defined(CONFIG_USER_ONLY) */
5835 }
5836
5837 /* tlbwe */
5838 static void gen_tlbwe_440(DisasContext *ctx)
5839 {
5840 #if defined(CONFIG_USER_ONLY)
5841 GEN_PRIV;
5842 #else
5843 CHK_SV;
5844 switch (rB(ctx->opcode)) {
5845 case 0:
5846 case 1:
5847 case 2:
5848 {
5849 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5850 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5851 cpu_gpr[rS(ctx->opcode)]);
5852 tcg_temp_free_i32(t0);
5853 }
5854 break;
5855 default:
5856 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5857 break;
5858 }
5859 #endif /* defined(CONFIG_USER_ONLY) */
5860 }
5861
5862 /* TLB management - PowerPC BookE 2.06 implementation */
5863
5864 /* tlbre */
5865 static void gen_tlbre_booke206(DisasContext *ctx)
5866 {
5867 #if defined(CONFIG_USER_ONLY)
5868 GEN_PRIV;
5869 #else
5870 CHK_SV;
5871 gen_helper_booke206_tlbre(cpu_env);
5872 #endif /* defined(CONFIG_USER_ONLY) */
5873 }
5874
5875 /* tlbsx - tlbsx. */
5876 static void gen_tlbsx_booke206(DisasContext *ctx)
5877 {
5878 #if defined(CONFIG_USER_ONLY)
5879 GEN_PRIV;
5880 #else
5881 TCGv t0;
5882
5883 CHK_SV;
5884 if (rA(ctx->opcode)) {
5885 t0 = tcg_temp_new();
5886 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5887 } else {
5888 t0 = tcg_const_tl(0);
5889 }
5890
5891 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5892 gen_helper_booke206_tlbsx(cpu_env, t0);
5893 tcg_temp_free(t0);
5894 #endif /* defined(CONFIG_USER_ONLY) */
5895 }
5896
5897 /* tlbwe */
5898 static void gen_tlbwe_booke206(DisasContext *ctx)
5899 {
5900 #if defined(CONFIG_USER_ONLY)
5901 GEN_PRIV;
5902 #else
5903 CHK_SV;
5904 gen_helper_booke206_tlbwe(cpu_env);
5905 #endif /* defined(CONFIG_USER_ONLY) */
5906 }
5907
5908 static void gen_tlbivax_booke206(DisasContext *ctx)
5909 {
5910 #if defined(CONFIG_USER_ONLY)
5911 GEN_PRIV;
5912 #else
5913 TCGv t0;
5914
5915 CHK_SV;
5916 t0 = tcg_temp_new();
5917 gen_addr_reg_index(ctx, t0);
5918 gen_helper_booke206_tlbivax(cpu_env, t0);
5919 tcg_temp_free(t0);
5920 #endif /* defined(CONFIG_USER_ONLY) */
5921 }
5922
5923 static void gen_tlbilx_booke206(DisasContext *ctx)
5924 {
5925 #if defined(CONFIG_USER_ONLY)
5926 GEN_PRIV;
5927 #else
5928 TCGv t0;
5929
5930 CHK_SV;
5931 t0 = tcg_temp_new();
5932 gen_addr_reg_index(ctx, t0);
5933
5934 switch((ctx->opcode >> 21) & 0x3) {
5935 case 0:
5936 gen_helper_booke206_tlbilx0(cpu_env, t0);
5937 break;
5938 case 1:
5939 gen_helper_booke206_tlbilx1(cpu_env, t0);
5940 break;
5941 case 3:
5942 gen_helper_booke206_tlbilx3(cpu_env, t0);
5943 break;
5944 default:
5945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5946 break;
5947 }
5948
5949 tcg_temp_free(t0);
5950 #endif /* defined(CONFIG_USER_ONLY) */
5951 }
5952
5953
5954 /* wrtee */
5955 static void gen_wrtee(DisasContext *ctx)
5956 {
5957 #if defined(CONFIG_USER_ONLY)
5958 GEN_PRIV;
5959 #else
5960 TCGv t0;
5961
5962 CHK_SV;
5963 t0 = tcg_temp_new();
5964 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5965 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5966 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5967 tcg_temp_free(t0);
5968 /* Stop translation to have a chance to raise an exception
5969 * if we just set msr_ee to 1
5970 */
5971 gen_stop_exception(ctx);
5972 #endif /* defined(CONFIG_USER_ONLY) */
5973 }
5974
5975 /* wrteei */
5976 static void gen_wrteei(DisasContext *ctx)
5977 {
5978 #if defined(CONFIG_USER_ONLY)
5979 GEN_PRIV;
5980 #else
5981 CHK_SV;
5982 if (ctx->opcode & 0x00008000) {
5983 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5984 /* Stop translation to have a chance to raise an exception */
5985 gen_stop_exception(ctx);
5986 } else {
5987 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5988 }
5989 #endif /* defined(CONFIG_USER_ONLY) */
5990 }
5991
5992 /* PowerPC 440 specific instructions */
5993
5994 /* dlmzb */
5995 static void gen_dlmzb(DisasContext *ctx)
5996 {
5997 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5998 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5999 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6000 tcg_temp_free_i32(t0);
6001 }
6002
6003 /* mbar replaces eieio on 440 */
6004 static void gen_mbar(DisasContext *ctx)
6005 {
6006 /* interpreted as no-op */
6007 }
6008
6009 /* msync replaces sync on 440 */
6010 static void gen_msync_4xx(DisasContext *ctx)
6011 {
6012 /* interpreted as no-op */
6013 }
6014
6015 /* icbt */
6016 static void gen_icbt_440(DisasContext *ctx)
6017 {
6018 /* interpreted as no-op */
6019 /* XXX: specification say this is treated as a load by the MMU
6020 * but does not generate any exception
6021 */
6022 }
6023
6024 /* Embedded.Processor Control */
6025
6026 static void gen_msgclr(DisasContext *ctx)
6027 {
6028 #if defined(CONFIG_USER_ONLY)
6029 GEN_PRIV;
6030 #else
6031 CHK_SV;
6032 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6033 #endif /* defined(CONFIG_USER_ONLY) */
6034 }
6035
6036 static void gen_msgsnd(DisasContext *ctx)
6037 {
6038 #if defined(CONFIG_USER_ONLY)
6039 GEN_PRIV;
6040 #else
6041 CHK_SV;
6042 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6043 #endif /* defined(CONFIG_USER_ONLY) */
6044 }
6045
6046
6047 #if defined(TARGET_PPC64)
6048 static void gen_maddld(DisasContext *ctx)
6049 {
6050 TCGv_i64 t1 = tcg_temp_new_i64();
6051
6052 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6053 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6054 tcg_temp_free_i64(t1);
6055 }
6056
6057 /* maddhd maddhdu */
6058 static void gen_maddhd_maddhdu(DisasContext *ctx)
6059 {
6060 TCGv_i64 lo = tcg_temp_new_i64();
6061 TCGv_i64 hi = tcg_temp_new_i64();
6062 TCGv_i64 t1 = tcg_temp_new_i64();
6063
6064 if (Rc(ctx->opcode)) {
6065 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6066 cpu_gpr[rB(ctx->opcode)]);
6067 tcg_gen_movi_i64(t1, 0);
6068 } else {
6069 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6070 cpu_gpr[rB(ctx->opcode)]);
6071 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6072 }
6073 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6074 cpu_gpr[rC(ctx->opcode)], t1);
6075 tcg_temp_free_i64(lo);
6076 tcg_temp_free_i64(hi);
6077 tcg_temp_free_i64(t1);
6078 }
6079 #endif /* defined(TARGET_PPC64) */
6080
6081 static void gen_tbegin(DisasContext *ctx)
6082 {
6083 if (unlikely(!ctx->tm_enabled)) {
6084 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6085 return;
6086 }
6087 gen_helper_tbegin(cpu_env);
6088 }
6089
6090 #define GEN_TM_NOOP(name) \
6091 static inline void gen_##name(DisasContext *ctx) \
6092 { \
6093 if (unlikely(!ctx->tm_enabled)) { \
6094 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6095 return; \
6096 } \
6097 /* Because tbegin always fails in QEMU, these user \
6098 * space instructions all have a simple implementation: \
6099 * \
6100 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6101 * = 0b0 || 0b00 || 0b0 \
6102 */ \
6103 tcg_gen_movi_i32(cpu_crf[0], 0); \
6104 }
6105
6106 GEN_TM_NOOP(tend);
6107 GEN_TM_NOOP(tabort);
6108 GEN_TM_NOOP(tabortwc);
6109 GEN_TM_NOOP(tabortwci);
6110 GEN_TM_NOOP(tabortdc);
6111 GEN_TM_NOOP(tabortdci);
6112 GEN_TM_NOOP(tsr);
6113
6114 static void gen_tcheck(DisasContext *ctx)
6115 {
6116 if (unlikely(!ctx->tm_enabled)) {
6117 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6118 return;
6119 }
6120 /* Because tbegin always fails, the tcheck implementation
6121 * is simple:
6122 *
6123 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6124 * = 0b1 || 0b00 || 0b0
6125 */
6126 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6127 }
6128
6129 #if defined(CONFIG_USER_ONLY)
6130 #define GEN_TM_PRIV_NOOP(name) \
6131 static inline void gen_##name(DisasContext *ctx) \
6132 { \
6133 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6134 }
6135
6136 #else
6137
6138 #define GEN_TM_PRIV_NOOP(name) \
6139 static inline void gen_##name(DisasContext *ctx) \
6140 { \
6141 CHK_SV; \
6142 if (unlikely(!ctx->tm_enabled)) { \
6143 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6144 return; \
6145 } \
6146 /* Because tbegin always fails, the implementation is \
6147 * simple: \
6148 * \
6149 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6150 * = 0b0 || 0b00 | 0b0 \
6151 */ \
6152 tcg_gen_movi_i32(cpu_crf[0], 0); \
6153 }
6154
6155 #endif
6156
6157 GEN_TM_PRIV_NOOP(treclaim);
6158 GEN_TM_PRIV_NOOP(trechkpt);
6159
6160 #include "translate/fp-impl.inc.c"
6161
6162 #include "translate/vmx-impl.inc.c"
6163
6164 #include "translate/vsx-impl.inc.c"
6165
6166 #include "translate/dfp-impl.inc.c"
6167
6168 #include "translate/spe-impl.inc.c"
6169
6170 static opcode_t opcodes[] = {
6171 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6172 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6173 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6174 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6175 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6176 #if defined(TARGET_PPC64)
6177 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6178 #endif
6179 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6180 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6181 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6182 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6183 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6184 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6185 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6186 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6187 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6188 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6189 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6190 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6191 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6192 #if defined(TARGET_PPC64)
6193 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6194 #endif
6195 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6196 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6197 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6198 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6199 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6200 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6201 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6202 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6203 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6204 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6205 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6206 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6207 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6208 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6209 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6210 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6211 #if defined(TARGET_PPC64)
6212 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6213 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6214 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6215 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6216 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6217 #endif
6218 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6219 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6220 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6221 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6222 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6223 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6224 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6225 #if defined(TARGET_PPC64)
6226 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6227 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6228 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6229 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6230 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6231 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6232 PPC_NONE, PPC2_ISA300),
6233 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6234 PPC_NONE, PPC2_ISA300),
6235 #endif
6236 #if defined(TARGET_PPC64)
6237 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6238 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6239 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6240 #endif
6241 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6242 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6243 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6244 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6245 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6246 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6247 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6248 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6249 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6250 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6251 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6252 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6253 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6254 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6255 #if defined(TARGET_PPC64)
6256 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6257 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6258 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6259 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6260 #endif
6261 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6262 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6263 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6264 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6265 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6266 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6267 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6268 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6269 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6270 #if defined(TARGET_PPC64)
6271 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6272 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6273 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6274 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6275 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6276 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6277 #endif
6278 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6279 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6280 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6281 #if defined(TARGET_PPC64)
6282 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6283 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6284 #endif
6285 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6286 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6287 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6288 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6289 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6290 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6291 #if defined(TARGET_PPC64)
6292 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6293 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6294 #endif
6295 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6296 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6297 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6298 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6299 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6300 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6301 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6302 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6303 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6304 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6305 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6306 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6307 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6308 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6309 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6310 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6311 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6312 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6313 #if defined(TARGET_PPC64)
6314 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6315 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6316 PPC_SEGMENT_64B),
6317 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6318 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6319 PPC_SEGMENT_64B),
6320 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6321 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6322 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6323 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6324 #endif
6325 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6326 /* XXX Those instructions will need to be handled differently for
6327 * different ISA versions */
6328 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6329 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6330 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6331 #if defined(TARGET_PPC64)
6332 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6333 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6334 #endif
6335 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6336 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6337 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6338 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6339 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6340 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6341 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6342 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6343 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6344 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6345 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6346 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6347 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6348 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6349 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6350 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6351 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6352 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6353 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6354 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6355 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6356 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6357 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6358 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6359 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6360 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6361 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6362 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6363 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6364 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6365 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6366 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6367 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6368 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6369 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6370 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6371 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6372 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6373 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6374 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6375 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6376 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6377 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6378 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6379 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6380 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6381 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6382 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6383 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6384 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6385 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6386 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6387 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6388 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6389 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6390 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6391 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6392 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6393 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6394 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6395 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6396 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6397 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6398 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6399 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6400 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6401 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6402 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6403 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6404 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6405 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6406 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6407 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6408 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6409 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6410 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6411 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6412 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6413 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6414 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6415 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6416 PPC_NONE, PPC2_BOOKE206),
6417 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6418 PPC_NONE, PPC2_BOOKE206),
6419 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6420 PPC_NONE, PPC2_BOOKE206),
6421 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6422 PPC_NONE, PPC2_BOOKE206),
6423 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6424 PPC_NONE, PPC2_BOOKE206),
6425 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6426 PPC_NONE, PPC2_PRCNTL),
6427 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6428 PPC_NONE, PPC2_PRCNTL),
6429 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6430 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6431 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6432 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6433 PPC_BOOKE, PPC2_BOOKE206),
6434 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6435 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6436 PPC_BOOKE, PPC2_BOOKE206),
6437 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6438 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6439 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6440 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6441 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6442 #if defined(TARGET_PPC64)
6443 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6444 PPC2_ISA300),
6445 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6446 #endif
6447
6448 #undef GEN_INT_ARITH_ADD
6449 #undef GEN_INT_ARITH_ADD_CONST
6450 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6451 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6452 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6453 add_ca, compute_ca, compute_ov) \
6454 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6455 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6456 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6457 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6458 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6459 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6460 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6461 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6462 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6463 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6464 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6465
6466 #undef GEN_INT_ARITH_DIVW
6467 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6468 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6469 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6470 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6471 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6472 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6473 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6474 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6475 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6476 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6477 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6478 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6479
6480 #if defined(TARGET_PPC64)
6481 #undef GEN_INT_ARITH_DIVD
6482 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6483 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6484 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6485 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6486 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6487 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6488
6489 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6490 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6491 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6492 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6493 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6494 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6495
6496 #undef GEN_INT_ARITH_MUL_HELPER
6497 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6498 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6499 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6500 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6501 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6502 #endif
6503
6504 #undef GEN_INT_ARITH_SUBF
6505 #undef GEN_INT_ARITH_SUBF_CONST
6506 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6507 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6508 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6509 add_ca, compute_ca, compute_ov) \
6510 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6511 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6512 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6513 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6514 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6515 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6516 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6517 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6518 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6519 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6520 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6521
6522 #undef GEN_LOGICAL1
6523 #undef GEN_LOGICAL2
6524 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6525 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6526 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6527 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6528 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6529 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6530 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6531 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6532 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6533 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6534 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6535 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6536 #if defined(TARGET_PPC64)
6537 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6538 #endif
6539
6540 #if defined(TARGET_PPC64)
6541 #undef GEN_PPC64_R2
6542 #undef GEN_PPC64_R4
6543 #define GEN_PPC64_R2(name, opc1, opc2) \
6544 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6545 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6546 PPC_64B)
6547 #define GEN_PPC64_R4(name, opc1, opc2) \
6548 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6549 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6550 PPC_64B), \
6551 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6552 PPC_64B), \
6553 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6554 PPC_64B)
6555 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6556 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6557 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6558 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6559 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6560 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6561 #endif
6562
6563 #undef GEN_LD
6564 #undef GEN_LDU
6565 #undef GEN_LDUX
6566 #undef GEN_LDX_E
6567 #undef GEN_LDS
6568 #define GEN_LD(name, ldop, opc, type) \
6569 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6570 #define GEN_LDU(name, ldop, opc, type) \
6571 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6572 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6573 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6574 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6575 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6576 #define GEN_LDS(name, ldop, op, type) \
6577 GEN_LD(name, ldop, op | 0x20, type) \
6578 GEN_LDU(name, ldop, op | 0x21, type) \
6579 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6580 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6581
6582 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6583 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6584 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6585 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6586 #if defined(TARGET_PPC64)
6587 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6588 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6589 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6590 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6591 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6592
6593 /* HV/P7 and later only */
6594 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6595 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6596 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6597 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6598 #endif
6599 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6600 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6601
6602 #undef GEN_ST
6603 #undef GEN_STU
6604 #undef GEN_STUX
6605 #undef GEN_STX_E
6606 #undef GEN_STS
6607 #define GEN_ST(name, stop, opc, type) \
6608 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6609 #define GEN_STU(name, stop, opc, type) \
6610 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6611 #define GEN_STUX(name, stop, opc2, opc3, type) \
6612 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6613 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6614 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6615 #define GEN_STS(name, stop, op, type) \
6616 GEN_ST(name, stop, op | 0x20, type) \
6617 GEN_STU(name, stop, op | 0x21, type) \
6618 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6619 GEN_STX(name, stop, 0x17, op | 0x00, type)
6620
6621 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6622 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6623 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6624 #if defined(TARGET_PPC64)
6625 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6626 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6627 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6628 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6629 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6630 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6631 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6632 #endif
6633 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6634 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6635
6636 #undef GEN_CRLOGIC
6637 #define GEN_CRLOGIC(name, tcg_op, opc) \
6638 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6639 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6640 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6641 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6642 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6643 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6644 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6645 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6646 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6647
6648 #undef GEN_MAC_HANDLER
6649 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6650 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6651 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6652 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6653 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6654 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6655 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6656 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6657 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6658 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6659 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6660 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6661 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6662 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6663 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6664 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6665 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6666 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6667 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6668 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6669 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6670 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6671 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6672 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6673 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6674 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6675 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6676 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6677 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6678 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6679 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6680 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6681 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6682 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6683 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6684 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6685 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6686 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6687 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6688 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6689 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6690 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6691 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6692 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6693
6694 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6695 PPC_NONE, PPC2_TM),
6696 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6697 PPC_NONE, PPC2_TM),
6698 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6699 PPC_NONE, PPC2_TM),
6700 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6701 PPC_NONE, PPC2_TM),
6702 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6703 PPC_NONE, PPC2_TM),
6704 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6705 PPC_NONE, PPC2_TM),
6706 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6707 PPC_NONE, PPC2_TM),
6708 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6709 PPC_NONE, PPC2_TM),
6710 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6711 PPC_NONE, PPC2_TM),
6712 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6713 PPC_NONE, PPC2_TM),
6714 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6715 PPC_NONE, PPC2_TM),
6716
6717 #include "translate/fp-ops.inc.c"
6718
6719 #include "translate/vmx-ops.inc.c"
6720
6721 #include "translate/vsx-ops.inc.c"
6722
6723 #include "translate/dfp-ops.inc.c"
6724
6725 #include "translate/spe-ops.inc.c"
6726 };
6727
6728 #include "helper_regs.h"
6729 #include "translate_init.c"
6730
6731 /*****************************************************************************/
6732 /* Misc PowerPC helpers */
6733 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6734 int flags)
6735 {
6736 #define RGPL 4
6737 #define RFPL 4
6738
6739 PowerPCCPU *cpu = POWERPC_CPU(cs);
6740 CPUPPCState *env = &cpu->env;
6741 int i;
6742
6743 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6744 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6745 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6746 cs->cpu_index);
6747 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6748 TARGET_FMT_lx " iidx %d didx %d\n",
6749 env->msr, env->spr[SPR_HID0],
6750 env->hflags, env->immu_idx, env->dmmu_idx);
6751 #if !defined(NO_TIMER_DUMP)
6752 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6753 #if !defined(CONFIG_USER_ONLY)
6754 " DECR %08" PRIu32
6755 #endif
6756 "\n",
6757 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6758 #if !defined(CONFIG_USER_ONLY)
6759 , cpu_ppc_load_decr(env)
6760 #endif
6761 );
6762 #endif
6763 for (i = 0; i < 32; i++) {
6764 if ((i & (RGPL - 1)) == 0)
6765 cpu_fprintf(f, "GPR%02d", i);
6766 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6767 if ((i & (RGPL - 1)) == (RGPL - 1))
6768 cpu_fprintf(f, "\n");
6769 }
6770 cpu_fprintf(f, "CR ");
6771 for (i = 0; i < 8; i++)
6772 cpu_fprintf(f, "%01x", env->crf[i]);
6773 cpu_fprintf(f, " [");
6774 for (i = 0; i < 8; i++) {
6775 char a = '-';
6776 if (env->crf[i] & 0x08)
6777 a = 'L';
6778 else if (env->crf[i] & 0x04)
6779 a = 'G';
6780 else if (env->crf[i] & 0x02)
6781 a = 'E';
6782 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6783 }
6784 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6785 env->reserve_addr);
6786 for (i = 0; i < 32; i++) {
6787 if ((i & (RFPL - 1)) == 0)
6788 cpu_fprintf(f, "FPR%02d", i);
6789 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6790 if ((i & (RFPL - 1)) == (RFPL - 1))
6791 cpu_fprintf(f, "\n");
6792 }
6793 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6794 #if !defined(CONFIG_USER_ONLY)
6795 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6796 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6797 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6798 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6799
6800 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6801 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6802 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6803 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6804
6805 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6806 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6807 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6808 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6809
6810 #if defined(TARGET_PPC64)
6811 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6812 env->excp_model == POWERPC_EXCP_POWER8) {
6813 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6814 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6815 }
6816 #endif
6817 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6818 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6819 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6820 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6821 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6822
6823 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6824 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6825 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6826 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6827
6828 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6829 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6830 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6831 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6832
6833 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6834 " EPR " TARGET_FMT_lx "\n",
6835 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6836 env->spr[SPR_BOOKE_EPR]);
6837
6838 /* FSL-specific */
6839 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6840 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6841 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6842 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6843
6844 /*
6845 * IVORs are left out as they are large and do not change often --
6846 * they can be read with "p $ivor0", "p $ivor1", etc.
6847 */
6848 }
6849
6850 #if defined(TARGET_PPC64)
6851 if (env->flags & POWERPC_FLAG_CFAR) {
6852 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6853 }
6854 #endif
6855
6856 switch (env->mmu_model) {
6857 case POWERPC_MMU_32B:
6858 case POWERPC_MMU_601:
6859 case POWERPC_MMU_SOFT_6xx:
6860 case POWERPC_MMU_SOFT_74xx:
6861 #if defined(TARGET_PPC64)
6862 case POWERPC_MMU_64B:
6863 case POWERPC_MMU_2_03:
6864 case POWERPC_MMU_2_06:
6865 case POWERPC_MMU_2_06a:
6866 case POWERPC_MMU_2_07:
6867 case POWERPC_MMU_2_07a:
6868 #endif
6869 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6870 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6871 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6872 break;
6873 case POWERPC_MMU_BOOKE206:
6874 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6875 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6876 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6877 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6878
6879 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6880 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6881 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6882 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6883
6884 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6885 " TLB1CFG " TARGET_FMT_lx "\n",
6886 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6887 env->spr[SPR_BOOKE_TLB1CFG]);
6888 break;
6889 default:
6890 break;
6891 }
6892 #endif
6893
6894 #undef RGPL
6895 #undef RFPL
6896 }
6897
6898 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6899 fprintf_function cpu_fprintf, int flags)
6900 {
6901 #if defined(DO_PPC_STATISTICS)
6902 PowerPCCPU *cpu = POWERPC_CPU(cs);
6903 opc_handler_t **t1, **t2, **t3, *handler;
6904 int op1, op2, op3;
6905
6906 t1 = cpu->env.opcodes;
6907 for (op1 = 0; op1 < 64; op1++) {
6908 handler = t1[op1];
6909 if (is_indirect_opcode(handler)) {
6910 t2 = ind_table(handler);
6911 for (op2 = 0; op2 < 32; op2++) {
6912 handler = t2[op2];
6913 if (is_indirect_opcode(handler)) {
6914 t3 = ind_table(handler);
6915 for (op3 = 0; op3 < 32; op3++) {
6916 handler = t3[op3];
6917 if (handler->count == 0)
6918 continue;
6919 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6920 "%016" PRIx64 " %" PRId64 "\n",
6921 op1, op2, op3, op1, (op3 << 5) | op2,
6922 handler->oname,
6923 handler->count, handler->count);
6924 }
6925 } else {
6926 if (handler->count == 0)
6927 continue;
6928 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6929 "%016" PRIx64 " %" PRId64 "\n",
6930 op1, op2, op1, op2, handler->oname,
6931 handler->count, handler->count);
6932 }
6933 }
6934 } else {
6935 if (handler->count == 0)
6936 continue;
6937 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6938 " %" PRId64 "\n",
6939 op1, op1, handler->oname,
6940 handler->count, handler->count);
6941 }
6942 }
6943 #endif
6944 }
6945
6946 /*****************************************************************************/
6947 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6948 {
6949 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6950 CPUState *cs = CPU(cpu);
6951 DisasContext ctx, *ctxp = &ctx;
6952 opc_handler_t **table, *handler;
6953 target_ulong pc_start;
6954 int num_insns;
6955 int max_insns;
6956
6957 pc_start = tb->pc;
6958 ctx.nip = pc_start;
6959 ctx.tb = tb;
6960 ctx.exception = POWERPC_EXCP_NONE;
6961 ctx.spr_cb = env->spr_cb;
6962 ctx.pr = msr_pr;
6963 ctx.mem_idx = env->dmmu_idx;
6964 ctx.dr = msr_dr;
6965 #if !defined(CONFIG_USER_ONLY)
6966 ctx.hv = msr_hv || !env->has_hv_mode;
6967 #endif
6968 ctx.insns_flags = env->insns_flags;
6969 ctx.insns_flags2 = env->insns_flags2;
6970 ctx.access_type = -1;
6971 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
6972 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6973 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6974 #if defined(TARGET_PPC64)
6975 ctx.sf_mode = msr_is_64bit(env, env->msr);
6976 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6977 #endif
6978 if (env->mmu_model == POWERPC_MMU_32B ||
6979 env->mmu_model == POWERPC_MMU_601 ||
6980 (env->mmu_model & POWERPC_MMU_64B))
6981 ctx.lazy_tlb_flush = true;
6982
6983 ctx.fpu_enabled = !!msr_fp;
6984 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6985 ctx.spe_enabled = !!msr_spe;
6986 else
6987 ctx.spe_enabled = false;
6988 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6989 ctx.altivec_enabled = !!msr_vr;
6990 else
6991 ctx.altivec_enabled = false;
6992 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6993 ctx.vsx_enabled = !!msr_vsx;
6994 } else {
6995 ctx.vsx_enabled = false;
6996 }
6997 #if defined(TARGET_PPC64)
6998 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6999 ctx.tm_enabled = !!msr_tm;
7000 } else {
7001 ctx.tm_enabled = false;
7002 }
7003 #endif
7004 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7005 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7006 else
7007 ctx.singlestep_enabled = 0;
7008 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7009 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7010 if (unlikely(cs->singlestep_enabled)) {
7011 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7012 }
7013 #if defined (DO_SINGLE_STEP) && 0
7014 /* Single step trace mode */
7015 msr_se = 1;
7016 #endif
7017 num_insns = 0;
7018 max_insns = tb->cflags & CF_COUNT_MASK;
7019 if (max_insns == 0) {
7020 max_insns = CF_COUNT_MASK;
7021 }
7022 if (max_insns > TCG_MAX_INSNS) {
7023 max_insns = TCG_MAX_INSNS;
7024 }
7025
7026 gen_tb_start(tb);
7027 tcg_clear_temp_count();
7028 /* Set env in case of segfault during code fetch */
7029 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7030 tcg_gen_insn_start(ctx.nip);
7031 num_insns++;
7032
7033 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7034 gen_debug_exception(ctxp);
7035 /* The address covered by the breakpoint must be included in
7036 [tb->pc, tb->pc + tb->size) in order to for it to be
7037 properly cleared -- thus we increment the PC here so that
7038 the logic setting tb->size below does the right thing. */
7039 ctx.nip += 4;
7040 break;
7041 }
7042
7043 LOG_DISAS("----------------\n");
7044 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7045 ctx.nip, ctx.mem_idx, (int)msr_ir);
7046 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7047 gen_io_start();
7048 if (unlikely(need_byteswap(&ctx))) {
7049 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7050 } else {
7051 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7052 }
7053 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7054 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7055 opc3(ctx.opcode), opc4(ctx.opcode),
7056 ctx.le_mode ? "little" : "big");
7057 ctx.nip += 4;
7058 table = env->opcodes;
7059 handler = table[opc1(ctx.opcode)];
7060 if (is_indirect_opcode(handler)) {
7061 table = ind_table(handler);
7062 handler = table[opc2(ctx.opcode)];
7063 if (is_indirect_opcode(handler)) {
7064 table = ind_table(handler);
7065 handler = table[opc3(ctx.opcode)];
7066 if (is_indirect_opcode(handler)) {
7067 table = ind_table(handler);
7068 handler = table[opc4(ctx.opcode)];
7069 }
7070 }
7071 }
7072 /* Is opcode *REALLY* valid ? */
7073 if (unlikely(handler->handler == &gen_invalid)) {
7074 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7075 "%02x - %02x - %02x - %02x (%08x) "
7076 TARGET_FMT_lx " %d\n",
7077 opc1(ctx.opcode), opc2(ctx.opcode),
7078 opc3(ctx.opcode), opc4(ctx.opcode),
7079 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7080 } else {
7081 uint32_t inval;
7082
7083 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7084 inval = handler->inval2;
7085 } else {
7086 inval = handler->inval1;
7087 }
7088
7089 if (unlikely((ctx.opcode & inval) != 0)) {
7090 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7091 "%02x - %02x - %02x - %02x (%08x) "
7092 TARGET_FMT_lx "\n", ctx.opcode & inval,
7093 opc1(ctx.opcode), opc2(ctx.opcode),
7094 opc3(ctx.opcode), opc4(ctx.opcode),
7095 ctx.opcode, ctx.nip - 4);
7096 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7097 break;
7098 }
7099 }
7100 (*(handler->handler))(&ctx);
7101 #if defined(DO_PPC_STATISTICS)
7102 handler->count++;
7103 #endif
7104 /* Check trace mode exceptions */
7105 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7106 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7107 ctx.exception != POWERPC_SYSCALL &&
7108 ctx.exception != POWERPC_EXCP_TRAP &&
7109 ctx.exception != POWERPC_EXCP_BRANCH)) {
7110 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7111 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7112 (cs->singlestep_enabled) ||
7113 singlestep ||
7114 num_insns >= max_insns)) {
7115 /* if we reach a page boundary or are single stepping, stop
7116 * generation
7117 */
7118 break;
7119 }
7120 if (tcg_check_temp_count()) {
7121 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7122 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7123 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7124 exit(1);
7125 }
7126 }
7127 if (tb->cflags & CF_LAST_IO)
7128 gen_io_end();
7129 if (ctx.exception == POWERPC_EXCP_NONE) {
7130 gen_goto_tb(&ctx, 0, ctx.nip);
7131 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7132 if (unlikely(cs->singlestep_enabled)) {
7133 gen_debug_exception(ctxp);
7134 }
7135 /* Generate the return instruction */
7136 tcg_gen_exit_tb(0);
7137 }
7138 gen_tb_end(tb, num_insns);
7139
7140 tb->size = ctx.nip - pc_start;
7141 tb->icount = num_insns;
7142
7143 #if defined(DEBUG_DISAS)
7144 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7145 && qemu_log_in_addr_range(pc_start)) {
7146 int flags;
7147 flags = env->bfd_mach;
7148 flags |= ctx.le_mode << 16;
7149 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7150 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7151 qemu_log("\n");
7152 }
7153 #endif
7154 }
7155
7156 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7157 target_ulong *data)
7158 {
7159 env->nip = data[0];
7160 }
Ray Wang's QEMU Repository