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spapr: do proper error propagation in spapr_cpu_core_realize_child()
[qemu/rayw.git] / hw / display / exynos4210_fimd.c
blobe5be713406886a1efde4935e2a7b92060bd15ab5
1 /*
2 * Samsung exynos4210 Display Controller (FIMD)
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 * Based on LCD controller for Samsung S5PC1xx-based board emulation
7 * by Kirill Batuzov <batuzovk@ispras.ru>
8 *
9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "hw/sysbus.h"
28 #include "ui/console.h"
29 #include "ui/pixel_ops.h"
30 #include "qemu/bswap.h"
31
32 /* Debug messages configuration */
33 #define EXYNOS4210_FIMD_DEBUG 0
34 #define EXYNOS4210_FIMD_MODE_TRACE 0
35
36 #if EXYNOS4210_FIMD_DEBUG == 0
37 #define DPRINT_L1(fmt, args...) do { } while (0)
38 #define DPRINT_L2(fmt, args...) do { } while (0)
39 #define DPRINT_ERROR(fmt, args...) do { } while (0)
40 #elif EXYNOS4210_FIMD_DEBUG == 1
41 #define DPRINT_L1(fmt, args...) \
42 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
43 #define DPRINT_L2(fmt, args...) do { } while (0)
44 #define DPRINT_ERROR(fmt, args...) \
45 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
46 #else
47 #define DPRINT_L1(fmt, args...) \
48 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
49 #define DPRINT_L2(fmt, args...) \
50 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
51 #define DPRINT_ERROR(fmt, args...) \
52 do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
53 #endif
54
55 #if EXYNOS4210_FIMD_MODE_TRACE == 0
56 #define DPRINT_TRACE(fmt, args...) do { } while (0)
57 #else
58 #define DPRINT_TRACE(fmt, args...) \
59 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
60 #endif
61
62 #define NUM_OF_WINDOWS 5
63 #define FIMD_REGS_SIZE 0x4114
64
65 /* Video main control registers */
66 #define FIMD_VIDCON0 0x0000
67 #define FIMD_VIDCON1 0x0004
68 #define FIMD_VIDCON2 0x0008
69 #define FIMD_VIDCON3 0x000C
70 #define FIMD_VIDCON0_ENVID_F (1 << 0)
71 #define FIMD_VIDCON0_ENVID (1 << 1)
72 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1))
73 #define FIMD_VIDCON1_ROMASK 0x07FFE000
74
75 /* Video time control registers */
76 #define FIMD_VIDTCON_START 0x10
77 #define FIMD_VIDTCON_END 0x1C
78 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF
79 #define FIMD_VIDTCON2_HOR_SHIFT 0
80 #define FIMD_VIDTCON2_VER_SHIFT 11
81
82 /* Window control registers */
83 #define FIMD_WINCON_START 0x0020
84 #define FIMD_WINCON_END 0x0030
85 #define FIMD_WINCON_ROMASK 0x82200000
86 #define FIMD_WINCON_ENWIN (1 << 0)
87 #define FIMD_WINCON_BLD_PIX (1 << 6)
88 #define FIMD_WINCON_ALPHA_MUL (1 << 7)
89 #define FIMD_WINCON_ALPHA_SEL (1 << 1)
90 #define FIMD_WINCON_SWAP 0x078000
91 #define FIMD_WINCON_SWAP_SHIFT 15
92 #define FIMD_WINCON_SWAP_WORD 0x1
93 #define FIMD_WINCON_SWAP_HWORD 0x2
94 #define FIMD_WINCON_SWAP_BYTE 0x4
95 #define FIMD_WINCON_SWAP_BITS 0x8
96 #define FIMD_WINCON_BUFSTAT_L (1 << 21)
97 #define FIMD_WINCON_BUFSTAT_H (1 << 31)
98 #define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31))
99 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31))
100 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31))
101 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1 << 31))
102 #define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30))
103 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30))
104 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30))
105 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30))
106 #define FIMD_WINCON_BUFMODE (1 << 14)
107 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC)
108 #define PAL_MODE_WITH_ALPHA(x) ((x) == 7)
109 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF)
110 #define WIN_BPP_MODE_WITH_ALPHA(w) \
111 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
112
113 /* Shadow control register */
114 #define FIMD_SHADOWCON 0x0034
115 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w))))
116 /* Channel mapping control register */
117 #define FIMD_WINCHMAP 0x003C
118
119 /* Window position control registers */
120 #define FIMD_VIDOSD_START 0x0040
121 #define FIMD_VIDOSD_END 0x0088
122 #define FIMD_VIDOSD_COORD_MASK 0x07FF
123 #define FIMD_VIDOSD_HOR_SHIFT 11
124 #define FIMD_VIDOSD_VER_SHIFT 0
125 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000
126 #define FIMD_VIDOSD_AEN0_SHIFT 12
127 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF
128
129 /* Frame buffer address registers */
130 #define FIMD_VIDWADD0_START 0x00A0
131 #define FIMD_VIDWADD0_END 0x00C4
132 #define FIMD_VIDWADD0_END 0x00C4
133 #define FIMD_VIDWADD1_START 0x00D0
134 #define FIMD_VIDWADD1_END 0x00F4
135 #define FIMD_VIDWADD2_START 0x0100
136 #define FIMD_VIDWADD2_END 0x0110
137 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF
138 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF
139 #define FIMD_VIDWADD2_OFFSIZE_SHIFT 13
140 #define FIMD_VIDW0ADD0_B2 0x20A0
141 #define FIMD_VIDW4ADD0_B2 0x20C0
142
143 /* Video interrupt control registers */
144 #define FIMD_VIDINTCON0 0x130
145 #define FIMD_VIDINTCON1 0x134
146
147 /* Window color key registers */
148 #define FIMD_WKEYCON_START 0x140
149 #define FIMD_WKEYCON_END 0x15C
150 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF
151 #define FIMD_WKEYCON0_CTL_SHIFT 24
152 #define FIMD_WKEYCON0_DIRCON (1 << 24)
153 #define FIMD_WKEYCON0_KEYEN (1 << 25)
154 #define FIMD_WKEYCON0_KEYBLEN (1 << 26)
155 /* Window color key alpha control register */
156 #define FIMD_WKEYALPHA_START 0x160
157 #define FIMD_WKEYALPHA_END 0x16C
158
159 /* Dithering control register */
160 #define FIMD_DITHMODE 0x170
161
162 /* Window alpha control registers */
163 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F
164 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0
165 #define FIMD_VIDWALPHA_START 0x21C
166 #define FIMD_VIDWALPHA_END 0x240
167
168 /* Window color map registers */
169 #define FIMD_WINMAP_START 0x180
170 #define FIMD_WINMAP_END 0x190
171 #define FIMD_WINMAP_EN (1 << 24)
172 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF
173
174 /* Window palette control registers */
175 #define FIMD_WPALCON_HIGH 0x019C
176 #define FIMD_WPALCON_LOW 0x01A0
177 #define FIMD_WPALCON_UPDATEEN (1 << 9)
178 #define FIMD_WPAL_W0PAL_L 0x07
179 #define FIMD_WPAL_W0PAL_L_SHT 0
180 #define FIMD_WPAL_W1PAL_L 0x07
181 #define FIMD_WPAL_W1PAL_L_SHT 3
182 #define FIMD_WPAL_W2PAL_L 0x01
183 #define FIMD_WPAL_W2PAL_L_SHT 6
184 #define FIMD_WPAL_W2PAL_H 0x06
185 #define FIMD_WPAL_W2PAL_H_SHT 8
186 #define FIMD_WPAL_W3PAL_L 0x01
187 #define FIMD_WPAL_W3PAL_L_SHT 7
188 #define FIMD_WPAL_W3PAL_H 0x06
189 #define FIMD_WPAL_W3PAL_H_SHT 12
190 #define FIMD_WPAL_W4PAL_L 0x01
191 #define FIMD_WPAL_W4PAL_L_SHT 8
192 #define FIMD_WPAL_W4PAL_H 0x06
193 #define FIMD_WPAL_W4PAL_H_SHT 16
194
195 /* Trigger control registers */
196 #define FIMD_TRIGCON 0x01A4
197 #define FIMD_TRIGCON_ROMASK 0x00000004
198
199 /* LCD I80 Interface Control */
200 #define FIMD_I80IFCON_START 0x01B0
201 #define FIMD_I80IFCON_END 0x01BC
202 /* Color gain control register */
203 #define FIMD_COLORGAINCON 0x01C0
204 /* LCD i80 Interface Command Control */
205 #define FIMD_LDI_CMDCON0 0x01D0
206 #define FIMD_LDI_CMDCON1 0x01D4
207 /* I80 System Interface Manual Command Control */
208 #define FIMD_SIFCCON0 0x01E0
209 #define FIMD_SIFCCON2 0x01E8
210
211 /* Hue Control Registers */
212 #define FIMD_HUECOEFCR_START 0x01EC
213 #define FIMD_HUECOEFCR_END 0x01F4
214 #define FIMD_HUECOEFCB_START 0x01FC
215 #define FIMD_HUECOEFCB_END 0x0208
216 #define FIMD_HUEOFFSET 0x020C
217
218 /* Video interrupt control registers */
219 #define FIMD_VIDINT_INTFIFOPEND (1 << 0)
220 #define FIMD_VIDINT_INTFRMPEND (1 << 1)
221 #define FIMD_VIDINT_INTI80PEND (1 << 2)
222 #define FIMD_VIDINT_INTEN (1 << 0)
223 #define FIMD_VIDINT_INTFIFOEN (1 << 1)
224 #define FIMD_VIDINT_INTFRMEN (1 << 12)
225 #define FIMD_VIDINT_I80IFDONE (1 << 17)
226
227 /* Window blend equation control registers */
228 #define FIMD_BLENDEQ_START 0x0244
229 #define FIMD_BLENDEQ_END 0x0250
230 #define FIMD_BLENDCON 0x0260
231 #define FIMD_ALPHA_8BIT (1 << 0)
232 #define FIMD_BLENDEQ_COEF_MASK 0xF
233
234 /* Window RTQOS Control Registers */
235 #define FIMD_WRTQOSCON_START 0x0264
236 #define FIMD_WRTQOSCON_END 0x0274
237
238 /* LCD I80 Interface Command */
239 #define FIMD_I80IFCMD_START 0x0280
240 #define FIMD_I80IFCMD_END 0x02AC
241
242 /* Shadow windows control registers */
243 #define FIMD_SHD_ADD0_START 0x40A0
244 #define FIMD_SHD_ADD0_END 0x40C0
245 #define FIMD_SHD_ADD1_START 0x40D0
246 #define FIMD_SHD_ADD1_END 0x40F0
247 #define FIMD_SHD_ADD2_START 0x4100
248 #define FIMD_SHD_ADD2_END 0x4110
249
250 /* Palette memory */
251 #define FIMD_PAL_MEM_START 0x2400
252 #define FIMD_PAL_MEM_END 0x37FC
253 /* Palette memory aliases for windows 0 and 1 */
254 #define FIMD_PALMEM_AL_START 0x0400
255 #define FIMD_PALMEM_AL_END 0x0BFC
256
257 typedef struct {
258 uint8_t r, g, b;
259 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
260 uint32_t a;
261 } rgba;
262 #define RGBA_SIZE 7
263
264 typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p);
265 typedef struct Exynos4210fimdWindow Exynos4210fimdWindow;
266
267 struct Exynos4210fimdWindow {
268 uint32_t wincon; /* Window control register */
269 uint32_t buf_start[3]; /* Start address for video frame buffer */
270 uint32_t buf_end[3]; /* End address for video frame buffer */
271 uint32_t keycon[2]; /* Window color key registers */
272 uint32_t keyalpha; /* Color key alpha control register */
273 uint32_t winmap; /* Window color map register */
274 uint32_t blendeq; /* Window blending equation control register */
275 uint32_t rtqoscon; /* Window RTQOS Control Registers */
276 uint32_t palette[256]; /* Palette RAM */
277 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */
278 uint32_t shadow_buf_end; /* End address of shadow frame buffer */
279 uint32_t shadow_buf_size; /* Virtual shadow screen width */
280
281 pixel_to_rgb_func *pixel_to_rgb;
282 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
283 bool blend);
284 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
285 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */
286 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */
287 uint32_t osdsize; /* VIDOSD2&3 register */
288 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */
289 uint16_t virtpage_width; /* VIDWADD2 register */
290 uint16_t virtpage_offsize; /* VIDWADD2 register */
291 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
292 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
293 hwaddr fb_len; /* Framebuffer length */
294 };
295
296 #define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
297 #define EXYNOS4210_FIMD(obj) \
298 OBJECT_CHECK(Exynos4210fimdState, (obj), TYPE_EXYNOS4210_FIMD)
299
300 typedef struct {
301 SysBusDevice parent_obj;
302
303 MemoryRegion iomem;
304 QemuConsole *console;
305 qemu_irq irq[3];
306
307 uint32_t vidcon[4]; /* Video main control registers 0-3 */
308 uint32_t vidtcon[4]; /* Video time control registers 0-3 */
309 uint32_t shadowcon; /* Window shadow control register */
310 uint32_t winchmap; /* Channel mapping control register */
311 uint32_t vidintcon[2]; /* Video interrupt control registers */
312 uint32_t dithmode; /* Dithering control register */
313 uint32_t wpalcon[2]; /* Window palette control registers */
314 uint32_t trigcon; /* Trigger control register */
315 uint32_t i80ifcon[4]; /* I80 interface control registers */
316 uint32_t colorgaincon; /* Color gain control register */
317 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */
318 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */
319 uint32_t huecoef_cr[4]; /* Hue control registers */
320 uint32_t huecoef_cb[4]; /* Hue control registers */
321 uint32_t hueoffset; /* Hue offset control register */
322 uint32_t blendcon; /* Blending control register */
323 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */
324
325 Exynos4210fimdWindow window[5]; /* Window-specific registers */
326 uint8_t *ifb; /* Internal frame buffer */
327 bool invalidate; /* Image needs to be redrawn */
328 bool enabled; /* Display controller is enabled */
329 } Exynos4210fimdState;
330
331 /* Perform byte/halfword/word swap of data according to WINCON */
332 static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)
333 {
334 int i;
335 uint64_t res;
336 uint64_t x = *data;
337
338 if (swap_ctl & FIMD_WINCON_SWAP_BITS) {
339 res = 0;
340 for (i = 0; i < 64; i++) {
341 if (x & (1ULL << (63 - i))) {
342 res |= (1ULL << i);
343 }
344 }
345 x = res;
346 }
347
348 if (swap_ctl & FIMD_WINCON_SWAP_BYTE) {
349 x = bswap64(x);
350 }
351
352 if (swap_ctl & FIMD_WINCON_SWAP_HWORD) {
353 x = ((x & 0x000000000000FFFFULL) << 48) |
354 ((x & 0x00000000FFFF0000ULL) << 16) |
355 ((x & 0x0000FFFF00000000ULL) >> 16) |
356 ((x & 0xFFFF000000000000ULL) >> 48);
357 }
358
359 if (swap_ctl & FIMD_WINCON_SWAP_WORD) {
360 x = ((x & 0x00000000FFFFFFFFULL) << 32) |
361 ((x & 0xFFFFFFFF00000000ULL) >> 32);
362 }
363
364 *data = x;
365 }
366
367 /* Conversion routines of Pixel data from frame buffer area to internal RGBA
368 * pixel representation.
369 * Every color component internally represented as 8-bit value. If original
370 * data has less than 8 bit for component, data is extended to 8 bit. For
371 * example, if blue component has only two possible values 0 and 1 it will be
372 * extended to 0 and 0xFF */
373
374 /* One bit for alpha representation */
375 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \
376 static void N(uint32_t pixel, rgba *p) \
377 { \
378 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
379 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
380 pixel >>= (B); \
381 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
382 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
383 pixel >>= (G); \
384 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
385 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
386 pixel >>= (R); \
387 p->a = (pixel & 0x1); \
388 }
389
390 DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4)
391 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)
392 DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6)
393 DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5)
394 DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8)
395 DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7)
396
397 /* Alpha component is always zero */
398 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \
399 static void N(uint32_t pixel, rgba *p) \
400 { \
401 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
402 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
403 pixel >>= (B); \
404 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
405 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
406 pixel >>= (G); \
407 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
408 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
409 p->a = 0x0; \
410 }
411
412 DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5)
413 DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5)
414 DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6)
415 DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8)
416
417 /* Alpha component has some meaningful value */
418 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \
419 static void N(uint32_t pixel, rgba *p) \
420 { \
421 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
422 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
423 pixel >>= (B); \
424 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
425 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
426 pixel >>= (G); \
427 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
428 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
429 pixel >>= (R); \
430 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
431 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
432 p->a = p->a | (p->a << 8) | (p->a << 16); \
433 }
434
435 DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4)
436 DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8)
437
438 /* Lookup table to extent 2-bit color component to 8 bit */
439 static const uint8_t pixel_lutable_2b[4] = {
440 0x0, 0x55, 0xAA, 0xFF
441 };
442 /* Lookup table to extent 3-bit color component to 8 bit */
443 static const uint8_t pixel_lutable_3b[8] = {
444 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
445 };
446 /* Special case for a232 bpp mode */
447 static void pixel_a232_to_rgb(uint32_t pixel, rgba *p)
448 {
449 p->b = pixel_lutable_2b[(pixel & 0x3)];
450 pixel >>= 2;
451 p->g = pixel_lutable_3b[(pixel & 0x7)];
452 pixel >>= 3;
453 p->r = pixel_lutable_2b[(pixel & 0x3)];
454 pixel >>= 2;
455 p->a = (pixel & 0x1);
456 }
457
458 /* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
459 * for all three color components */
460 static void pixel_1555_to_rgb(uint32_t pixel, rgba *p)
461 {
462 uint8_t comm = (pixel >> 15) & 1;
463 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
464 pixel >>= 5;
465 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
466 pixel >>= 5;
467 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
468 p->a = 0x0;
469 }
470
471 /* Put/get pixel to/from internal LCD Controller framebuffer */
472
473 static int put_pixel_ifb(const rgba p, uint8_t *d)
474 {
475 *(uint8_t *)d++ = p.r;
476 *(uint8_t *)d++ = p.g;
477 *(uint8_t *)d++ = p.b;
478 *(uint32_t *)d = p.a;
479 return RGBA_SIZE;
480 }
481
482 static int get_pixel_ifb(const uint8_t *s, rgba *p)
483 {
484 p->r = *(uint8_t *)s++;
485 p->g = *(uint8_t *)s++;
486 p->b = *(uint8_t *)s++;
487 p->a = (*(uint32_t *)s) & 0x00FFFFFF;
488 return RGBA_SIZE;
489 }
490
491 static pixel_to_rgb_func *palette_data_format[8] = {
492 [0] = pixel_565_to_rgb,
493 [1] = pixel_a555_to_rgb,
494 [2] = pixel_666_to_rgb,
495 [3] = pixel_a665_to_rgb,
496 [4] = pixel_a666_to_rgb,
497 [5] = pixel_888_to_rgb,
498 [6] = pixel_a888_to_rgb,
499 [7] = pixel_8888_to_rgb
500 };
501
502 /* Returns Index in palette data formats table for given window number WINDOW */
503 static uint32_t
504 exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window)
505 {
506 uint32_t ret;
507
508 switch (window) {
509 case 0:
510 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L;
511 if (ret != 7) {
512 ret = 6 - ret;
513 }
514 break;
515 case 1:
516 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L;
517 if (ret != 7) {
518 ret = 6 - ret;
519 }
520 break;
521 case 2:
522 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) |
523 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L);
524 break;
525 case 3:
526 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) |
527 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L);
528 break;
529 case 4:
530 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) |
531 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L);
532 break;
533 default:
534 hw_error("exynos4210.fimd: incorrect window number %d\n", window);
535 ret = 0;
536 break;
537 }
538 return ret;
539 }
540
541 #define FIMD_1_MINUS_COLOR(x) \
542 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
543 (0xFF0000 - ((x) & 0xFF0000)))
544 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
545 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
546
547 /* Multiply three lower bytes of two 32-bit words with each other.
548 * Each byte with values 0-255 is considered as a number with possible values
549 * in a range [0 - 1] */
550 static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b)
551 {
552 uint32_t tmp;
553 uint32_t ret;
554
555 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp;
556 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
557 0xFF00 : tmp << 8;
558 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
559 0xFF0000 : tmp << 16;
560 return ret;
561 }
562
563 /* For each corresponding bytes of two 32-bit words: (a*b + c*d)
564 * Byte values 0-255 are mapped to a range [0 .. 1] */
565 static inline uint32_t
566 fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
567 {
568 uint32_t tmp;
569 uint32_t ret;
570
571 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF))
572 > 0xFF) ? 0xFF : tmp;
573 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) *
574 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8;
575 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) +
576 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
577 0xFF0000 : tmp << 16;
578 return ret;
579 }
580
581 /* These routines cover all possible sources of window's transparent factor
582 * used in blending equation. Choice of routine is affected by WPALCON
583 * registers, BLENDCON register and window's WINCON register */
584
585 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a)
586 {
587 return pix_a;
588 }
589
590 static uint32_t
591 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a)
592 {
593 return EXTEND_LOWER_HALFBYTE(pix_a);
594 }
595
596 static uint32_t
597 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a)
598 {
599 return EXTEND_UPPER_HALFBYTE(pix_a);
600 }
601
602 static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a)
603 {
604 return fimd_mult_each_byte(pix_a, w->alpha_val[0]);
605 }
606
607 static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
608 {
609 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a),
610 EXTEND_UPPER_HALFBYTE(w->alpha_val[0]));
611 }
612
613 static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a)
614 {
615 return w->alpha_val[pix_a];
616 }
617
618 static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
619 {
620 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]);
621 }
622
623 static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a)
624 {
625 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0];
626 }
627
628 static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
629 {
630 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon &
631 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]);
632 }
633
634 /* Updates currently active alpha value get function for specified window */
635 static void fimd_update_get_alpha(Exynos4210fimdState *s, int win)
636 {
637 Exynos4210fimdWindow *w = &s->window[win];
638 const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT;
639
640 if (w->wincon & FIMD_WINCON_BLD_PIX) {
641 if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) {
642 /* In this case, alpha component contains meaningful value */
643 if (w->wincon & FIMD_WINCON_ALPHA_MUL) {
644 w->get_alpha = alpha_is_8bit ?
645 fimd_get_alpha_mult : fimd_get_alpha_mult_ext;
646 } else {
647 w->get_alpha = alpha_is_8bit ?
648 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow;
649 }
650 } else {
651 if (IS_PALETTIZED_MODE(w) &&
652 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) {
653 /* Alpha component has 8-bit numeric value */
654 w->get_alpha = alpha_is_8bit ?
655 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh;
656 } else {
657 /* Alpha has only two possible values (AEN) */
658 w->get_alpha = alpha_is_8bit ?
659 fimd_get_alpha_aen : fimd_get_alpha_aen_ext;
660 }
661 }
662 } else {
663 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel :
664 fimd_get_alpha_sel_ext;
665 }
666 }
667
668 /* Blends current window's (w) pixel (foreground pixel *ret) with background
669 * window (w_blend) pixel p_bg according to formula:
670 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
671 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
672 */
673 static void
674 exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret)
675 {
676 rgba p_fg = *ret;
677 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) |
678 (p_bg.b & 0xFF);
679 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) |
680 (p_fg.b & 0xFF);
681 uint32_t alpha_fg = p_fg.a;
682 int i;
683 /* It is possible that blending equation parameters a and b do not
684 * depend on window BLENEQ register. Account for this with first_coef */
685 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4};
686 uint32_t first_coef = A_COEF;
687 uint32_t blend_param[COEF_NUM];
688
689 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) {
690 uint32_t colorkey = (w->keycon[1] &
691 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY;
692
693 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) &&
694 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
695 /* Foreground pixel is displayed */
696 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
697 alpha_fg = w->keyalpha;
698 blend_param[A_COEF] = alpha_fg;
699 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
700 } else {
701 alpha_fg = 0;
702 blend_param[A_COEF] = 0xFFFFFF;
703 blend_param[B_COEF] = 0x0;
704 }
705 first_coef = P_COEF;
706 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 &&
707 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
708 /* Background pixel is displayed */
709 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
710 alpha_fg = w->keyalpha;
711 blend_param[A_COEF] = alpha_fg;
712 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
713 } else {
714 alpha_fg = 0;
715 blend_param[A_COEF] = 0x0;
716 blend_param[B_COEF] = 0xFFFFFF;
717 }
718 first_coef = P_COEF;
719 }
720 }
721
722 for (i = first_coef; i < COEF_NUM; i++) {
723 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) {
724 case 0:
725 blend_param[i] = 0;
726 break;
727 case 1:
728 blend_param[i] = 0xFFFFFF;
729 break;
730 case 2:
731 blend_param[i] = alpha_fg;
732 break;
733 case 3:
734 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg);
735 break;
736 case 4:
737 blend_param[i] = p_bg.a;
738 break;
739 case 5:
740 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a);
741 break;
742 case 6:
743 blend_param[i] = w->alpha_val[0];
744 break;
745 case 10:
746 blend_param[i] = fg_color;
747 break;
748 case 11:
749 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color);
750 break;
751 case 12:
752 blend_param[i] = bg_color;
753 break;
754 case 13:
755 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color);
756 break;
757 default:
758 hw_error("exynos4210.fimd: blend equation coef illegal value\n");
759 break;
760 }
761 }
762
763 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF],
764 fg_color, blend_param[A_COEF]);
765 ret->b = fg_color & 0xFF;
766 fg_color >>= 8;
767 ret->g = fg_color & 0xFF;
768 fg_color >>= 8;
769 ret->r = fg_color & 0xFF;
770 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF],
771 p_bg.a, blend_param[Q_COEF]);
772 }
773
774 /* These routines read data from video frame buffer in system RAM, convert
775 * this data to display controller internal representation, if necessary,
776 * perform pixel blending with data, currently presented in internal buffer.
777 * Result is stored in display controller internal frame buffer. */
778
779 /* Draw line with index in palette table in RAM frame buffer data */
780 #define DEF_DRAW_LINE_PALETTE(N) \
781 static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
782 uint8_t *dst, bool blend) \
783 { \
784 int width = w->rightbot_x - w->lefttop_x + 1; \
785 uint8_t *ifb = dst; \
786 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
787 uint64_t data; \
788 rgba p, p_old; \
789 int i; \
790 do { \
791 memcpy(&data, src, sizeof(data)); \
792 src += 8; \
793 fimd_swap_data(swap, &data); \
794 for (i = (64 / (N) - 1); i >= 0; i--) { \
795 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
796 ((1ULL << (N)) - 1)], &p); \
797 p.a = w->get_alpha(w, p.a); \
798 if (blend) { \
799 ifb += get_pixel_ifb(ifb, &p_old); \
800 exynos4210_fimd_blend_pixel(w, p_old, &p); \
801 } \
802 dst += put_pixel_ifb(p, dst); \
803 } \
804 width -= (64 / (N)); \
805 } while (width > 0); \
806 }
807
808 /* Draw line with direct color value in RAM frame buffer data */
809 #define DEF_DRAW_LINE_NOPALETTE(N) \
810 static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
811 uint8_t *dst, bool blend) \
812 { \
813 int width = w->rightbot_x - w->lefttop_x + 1; \
814 uint8_t *ifb = dst; \
815 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
816 uint64_t data; \
817 rgba p, p_old; \
818 int i; \
819 do { \
820 memcpy(&data, src, sizeof(data)); \
821 src += 8; \
822 fimd_swap_data(swap, &data); \
823 for (i = (64 / (N) - 1); i >= 0; i--) { \
824 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
825 p.a = w->get_alpha(w, p.a); \
826 if (blend) { \
827 ifb += get_pixel_ifb(ifb, &p_old); \
828 exynos4210_fimd_blend_pixel(w, p_old, &p); \
829 } \
830 dst += put_pixel_ifb(p, dst); \
831 } \
832 width -= (64 / (N)); \
833 } while (width > 0); \
834 }
835
836 DEF_DRAW_LINE_PALETTE(1)
837 DEF_DRAW_LINE_PALETTE(2)
838 DEF_DRAW_LINE_PALETTE(4)
839 DEF_DRAW_LINE_PALETTE(8)
840 DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */
841 DEF_DRAW_LINE_NOPALETTE(16)
842 DEF_DRAW_LINE_NOPALETTE(32)
843
844 /* Special draw line routine for window color map case */
845 static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,
846 uint8_t *dst, bool blend)
847 {
848 rgba p, p_old;
849 uint8_t *ifb = dst;
850 int width = w->rightbot_x - w->lefttop_x + 1;
851 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK;
852
853 do {
854 pixel_888_to_rgb(map_color, &p);
855 p.a = w->get_alpha(w, p.a);
856 if (blend) {
857 ifb += get_pixel_ifb(ifb, &p_old);
858 exynos4210_fimd_blend_pixel(w, p_old, &p);
859 }
860 dst += put_pixel_ifb(p, dst);
861 } while (--width);
862 }
863
864 /* Write RGB to QEMU's GraphicConsole framebuffer */
865
866 static int put_to_qemufb_pixel8(const rgba p, uint8_t *d)
867 {
868 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b);
869 *(uint8_t *)d = pixel;
870 return 1;
871 }
872
873 static int put_to_qemufb_pixel15(const rgba p, uint8_t *d)
874 {
875 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b);
876 *(uint16_t *)d = pixel;
877 return 2;
878 }
879
880 static int put_to_qemufb_pixel16(const rgba p, uint8_t *d)
881 {
882 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b);
883 *(uint16_t *)d = pixel;
884 return 2;
885 }
886
887 static int put_to_qemufb_pixel24(const rgba p, uint8_t *d)
888 {
889 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
890 *(uint8_t *)d++ = (pixel >> 0) & 0xFF;
891 *(uint8_t *)d++ = (pixel >> 8) & 0xFF;
892 *(uint8_t *)d++ = (pixel >> 16) & 0xFF;
893 return 3;
894 }
895
896 static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)
897 {
898 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
899 *(uint32_t *)d = pixel;
900 return 4;
901 }
902
903 /* Routine to copy pixel from internal buffer to QEMU buffer */
904 static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel);
905 static inline void fimd_update_putpix_qemu(int bpp)
906 {
907 switch (bpp) {
908 case 8:
909 put_pixel_toqemu = put_to_qemufb_pixel8;
910 break;
911 case 15:
912 put_pixel_toqemu = put_to_qemufb_pixel15;
913 break;
914 case 16:
915 put_pixel_toqemu = put_to_qemufb_pixel16;
916 break;
917 case 24:
918 put_pixel_toqemu = put_to_qemufb_pixel24;
919 break;
920 case 32:
921 put_pixel_toqemu = put_to_qemufb_pixel32;
922 break;
923 default:
924 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp);
925 break;
926 }
927 }
928
929 /* Routine to copy a line from internal frame buffer to QEMU display */
930 static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)
931 {
932 rgba p;
933
934 do {
935 src += get_pixel_ifb(src, &p);
936 dst += put_pixel_toqemu(p, dst);
937 } while (--width);
938 }
939
940 /* Parse BPPMODE_F = WINCON1[5:2] bits */
941 static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win)
942 {
943 Exynos4210fimdWindow *w = &s->window[win];
944
945 if (w->winmap & FIMD_WINMAP_EN) {
946 w->draw_line = draw_line_mapcolor;
947 return;
948 }
949
950 switch (WIN_BPP_MODE(w)) {
951 case 0:
952 w->draw_line = draw_line_palette_1;
953 w->pixel_to_rgb =
954 palette_data_format[exynos4210_fimd_palette_format(s, win)];
955 break;
956 case 1:
957 w->draw_line = draw_line_palette_2;
958 w->pixel_to_rgb =
959 palette_data_format[exynos4210_fimd_palette_format(s, win)];
960 break;
961 case 2:
962 w->draw_line = draw_line_palette_4;
963 w->pixel_to_rgb =
964 palette_data_format[exynos4210_fimd_palette_format(s, win)];
965 break;
966 case 3:
967 w->draw_line = draw_line_palette_8;
968 w->pixel_to_rgb =
969 palette_data_format[exynos4210_fimd_palette_format(s, win)];
970 break;
971 case 4:
972 w->draw_line = draw_line_8;
973 w->pixel_to_rgb = pixel_a232_to_rgb;
974 break;
975 case 5:
976 w->draw_line = draw_line_16;
977 w->pixel_to_rgb = pixel_565_to_rgb;
978 break;
979 case 6:
980 w->draw_line = draw_line_16;
981 w->pixel_to_rgb = pixel_a555_to_rgb;
982 break;
983 case 7:
984 w->draw_line = draw_line_16;
985 w->pixel_to_rgb = pixel_1555_to_rgb;
986 break;
987 case 8:
988 w->draw_line = draw_line_32;
989 w->pixel_to_rgb = pixel_666_to_rgb;
990 break;
991 case 9:
992 w->draw_line = draw_line_32;
993 w->pixel_to_rgb = pixel_a665_to_rgb;
994 break;
995 case 10:
996 w->draw_line = draw_line_32;
997 w->pixel_to_rgb = pixel_a666_to_rgb;
998 break;
999 case 11:
1000 w->draw_line = draw_line_32;
1001 w->pixel_to_rgb = pixel_888_to_rgb;
1002 break;
1003 case 12:
1004 w->draw_line = draw_line_32;
1005 w->pixel_to_rgb = pixel_a887_to_rgb;
1006 break;
1007 case 13:
1008 w->draw_line = draw_line_32;
1009 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
1010 FIMD_WINCON_ALPHA_SEL)) {
1011 w->pixel_to_rgb = pixel_8888_to_rgb;
1012 } else {
1013 w->pixel_to_rgb = pixel_a888_to_rgb;
1014 }
1015 break;
1016 case 14:
1017 w->draw_line = draw_line_16;
1018 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
1019 FIMD_WINCON_ALPHA_SEL)) {
1020 w->pixel_to_rgb = pixel_4444_to_rgb;
1021 } else {
1022 w->pixel_to_rgb = pixel_a444_to_rgb;
1023 }
1024 break;
1025 case 15:
1026 w->draw_line = draw_line_16;
1027 w->pixel_to_rgb = pixel_555_to_rgb;
1028 break;
1029 }
1030 }
1031
1032 #if EXYNOS4210_FIMD_MODE_TRACE > 0
1033 static const char *exynos4210_fimd_get_bppmode(int mode_code)
1034 {
1035 switch (mode_code) {
1036 case 0:
1037 return "1 bpp";
1038 case 1:
1039 return "2 bpp";
1040 case 2:
1041 return "4 bpp";
1042 case 3:
1043 return "8 bpp (palettized)";
1044 case 4:
1045 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
1046 case 5:
1047 return "16 bpp (non-palettized, R:5-G:6-B:5)";
1048 case 6:
1049 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
1050 case 7:
1051 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
1052 case 8:
1053 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
1054 case 9:
1055 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
1056 case 10:
1057 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
1058 case 11:
1059 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
1060 case 12:
1061 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
1062 case 13:
1063 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
1064 case 14:
1065 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
1066 case 15:
1067 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
1068 default:
1069 return "Non-existing bpp mode";
1070 }
1071 }
1072
1073 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1074 int win_num, uint32_t val)
1075 {
1076 Exynos4210fimdWindow *w = &s->window[win_num];
1077
1078 if (w->winmap & FIMD_WINMAP_EN) {
1079 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
1080 win_num, w->winmap & 0xFFFFFF);
1081 return;
1082 }
1083
1084 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) {
1085 return;
1086 }
1087 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num,
1088 exynos4210_fimd_get_bppmode((val >> 2) & 0xF));
1089 }
1090 #else
1091 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1092 int win_num, uint32_t val)
1093 {
1094
1095 }
1096 #endif
1097
1098 static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
1099 {
1100 switch (w->wincon & FIMD_WINCON_BUFSTATUS) {
1101 case FIMD_WINCON_BUF0_STAT:
1102 return 0;
1103 case FIMD_WINCON_BUF1_STAT:
1104 return 1;
1105 case FIMD_WINCON_BUF2_STAT:
1106 return 2;
1107 default:
1108 DPRINT_ERROR("Non-existent buffer index\n");
1109 return 0;
1110 }
1111 }
1112
1113 static void exynos4210_fimd_invalidate(void *opaque)
1114 {
1115 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1116 s->invalidate = true;
1117 }
1118
1119 /* Updates specified window's MemorySection based on values of WINCON,
1120 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
1121 static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
1122 {
1123 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
1124 Exynos4210fimdWindow *w = &s->window[win];
1125 hwaddr fb_start_addr, fb_mapped_len;
1126
1127 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
1128 FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
1129 return;
1130 }
1131
1132 if (w->host_fb_addr) {
1133 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0);
1134 w->host_fb_addr = NULL;
1135 w->fb_len = 0;
1136 }
1137
1138 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)];
1139 /* Total number of bytes of virtual screen used by current window */
1140 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
1141 (w->rightbot_y - w->lefttop_y + 1);
1142
1143 /* TODO: add .exit and unref the region there. Not needed yet since sysbus
1144 * does not support hot-unplug.
1145 */
1146 if (w->mem_section.mr) {
1147 memory_region_set_log(w->mem_section.mr, false, DIRTY_MEMORY_VGA);
1148 memory_region_unref(w->mem_section.mr);
1149 }
1150
1151 w->mem_section = memory_region_find(sysbus_address_space(sbd),
1152 fb_start_addr, w->fb_len);
1153 assert(w->mem_section.mr);
1154 assert(w->mem_section.offset_within_address_space == fb_start_addr);
1155 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
1156 win, fb_start_addr, w->fb_len);
1157
1158 if (int128_get64(w->mem_section.size) != w->fb_len ||
1159 !memory_region_is_ram(w->mem_section.mr)) {
1160 DPRINT_ERROR("Failed to find window %u framebuffer region\n", win);
1161 goto error_return;
1162 }
1163
1164 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0);
1165 if (!w->host_fb_addr) {
1166 DPRINT_ERROR("Failed to map window %u framebuffer\n", win);
1167 goto error_return;
1168 }
1169
1170 if (fb_mapped_len != w->fb_len) {
1171 DPRINT_ERROR("Window %u mapped framebuffer length is less then "
1172 "expected\n", win);
1173 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
1174 goto error_return;
1175 }
1176 memory_region_set_log(w->mem_section.mr, true, DIRTY_MEMORY_VGA);
1177 exynos4210_fimd_invalidate(s);
1178 return;
1179
1180 error_return:
1181 memory_region_unref(w->mem_section.mr);
1182 w->mem_section.mr = NULL;
1183 w->mem_section.size = int128_zero();
1184 w->host_fb_addr = NULL;
1185 w->fb_len = 0;
1186 }
1187
1188 static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled)
1189 {
1190 if (enabled && !s->enabled) {
1191 unsigned w;
1192 s->enabled = true;
1193 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1194 fimd_update_memory_section(s, w);
1195 }
1196 }
1197 s->enabled = enabled;
1198 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled");
1199 }
1200
1201 static inline uint32_t unpack_upper_4(uint32_t x)
1202 {
1203 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4);
1204 }
1205
1206 static inline uint32_t pack_upper_4(uint32_t x)
1207 {
1208 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) |
1209 ((x & 0xF0) >> 4)) & 0xFFF;
1210 }
1211
1212 static void exynos4210_fimd_update_irq(Exynos4210fimdState *s)
1213 {
1214 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) {
1215 qemu_irq_lower(s->irq[0]);
1216 qemu_irq_lower(s->irq[1]);
1217 qemu_irq_lower(s->irq[2]);
1218 return;
1219 }
1220 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) &&
1221 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) {
1222 qemu_irq_raise(s->irq[0]);
1223 } else {
1224 qemu_irq_lower(s->irq[0]);
1225 }
1226 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) &&
1227 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) {
1228 qemu_irq_raise(s->irq[1]);
1229 } else {
1230 qemu_irq_lower(s->irq[1]);
1231 }
1232 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) &&
1233 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) {
1234 qemu_irq_raise(s->irq[2]);
1235 } else {
1236 qemu_irq_lower(s->irq[2]);
1237 }
1238 }
1239
1240 static void exynos4210_update_resolution(Exynos4210fimdState *s)
1241 {
1242 DisplaySurface *surface = qemu_console_surface(s->console);
1243
1244 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
1245 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) &
1246 FIMD_VIDTCON2_SIZE_MASK) + 1;
1247 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
1248 FIMD_VIDTCON2_SIZE_MASK) + 1;
1249
1250 if (s->ifb == NULL || surface_width(surface) != width ||
1251 surface_height(surface) != height) {
1252 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
1253 surface_width(surface), surface_height(surface), width, height);
1254 qemu_console_resize(s->console, width, height);
1255 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1);
1256 memset(s->ifb, 0, width * height * RGBA_SIZE + 1);
1257 exynos4210_fimd_invalidate(s);
1258 }
1259 }
1260
1261 static void exynos4210_fimd_update(void *opaque)
1262 {
1263 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1264 DisplaySurface *surface;
1265 Exynos4210fimdWindow *w;
1266 int i, line;
1267 hwaddr fb_line_addr, inc_size;
1268 int scrn_height;
1269 int first_line = -1, last_line = -1, scrn_width;
1270 bool blend = false;
1271 uint8_t *host_fb_addr;
1272 bool is_dirty = false;
1273 const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
1274 const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
1275 FIMD_VIDTCON2_SIZE_MASK) + 1;
1276
1277 if (!s || !s->console || !s->enabled ||
1278 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
1279 return;
1280 }
1281 exynos4210_update_resolution(s);
1282 surface = qemu_console_surface(s->console);
1283
1284 for (i = 0; i < NUM_OF_WINDOWS; i++) {
1285 w = &s->window[i];
1286 if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) {
1287 scrn_height = w->rightbot_y - w->lefttop_y + 1;
1288 scrn_width = w->virtpage_width;
1289 /* Total width of virtual screen page in bytes */
1290 inc_size = scrn_width + w->virtpage_offsize;
1291 memory_region_sync_dirty_bitmap(w->mem_section.mr);
1292 host_fb_addr = w->host_fb_addr;
1293 fb_line_addr = w->mem_section.offset_within_region;
1294
1295 for (line = 0; line < scrn_height; line++) {
1296 is_dirty = memory_region_get_dirty(w->mem_section.mr,
1297 fb_line_addr, scrn_width, DIRTY_MEMORY_VGA);
1298
1299 if (s->invalidate || is_dirty) {
1300 if (first_line == -1) {
1301 first_line = line;
1302 }
1303 last_line = line;
1304 w->draw_line(w, host_fb_addr, s->ifb +
1305 w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) *
1306 global_width * RGBA_SIZE, blend);
1307 }
1308 host_fb_addr += inc_size;
1309 fb_line_addr += inc_size;
1310 is_dirty = false;
1311 }
1312 memory_region_reset_dirty(w->mem_section.mr,
1313 w->mem_section.offset_within_region,
1314 w->fb_len, DIRTY_MEMORY_VGA);
1315 blend = true;
1316 }
1317 }
1318
1319 /* Copy resulting image to QEMU_CONSOLE. */
1320 if (first_line >= 0) {
1321 uint8_t *d;
1322 int bpp;
1323
1324 bpp = surface_bits_per_pixel(surface);
1325 fimd_update_putpix_qemu(bpp);
1326 bpp = (bpp + 1) >> 3;
1327 d = surface_data(surface);
1328 for (line = first_line; line <= last_line; line++) {
1329 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
1330 RGBA_SIZE, d + global_width * line * bpp);
1331 }
1332 dpy_gfx_update(s->console, 0, 0, global_width, global_height);
1333 }
1334 s->invalidate = false;
1335 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND;
1336 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) {
1337 exynos4210_fimd_enable(s, false);
1338 }
1339 exynos4210_fimd_update_irq(s);
1340 }
1341
1342 static void exynos4210_fimd_reset(DeviceState *d)
1343 {
1344 Exynos4210fimdState *s = EXYNOS4210_FIMD(d);
1345 unsigned w;
1346
1347 DPRINT_TRACE("Display controller reset\n");
1348 /* Set all display controller registers to 0 */
1349 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon);
1350 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1351 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow));
1352 s->window[w].blendeq = 0xC2;
1353 exynos4210_fimd_update_win_bppmode(s, w);
1354 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1355 fimd_update_get_alpha(s, w);
1356 }
1357
1358 g_free(s->ifb);
1359 s->ifb = NULL;
1360
1361 exynos4210_fimd_invalidate(s);
1362 exynos4210_fimd_enable(s, false);
1363 /* Some registers have non-zero initial values */
1364 s->winchmap = 0x7D517D51;
1365 s->colorgaincon = 0x10040100;
1366 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100;
1367 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100;
1368 s->hueoffset = 0x01800080;
1369 }
1370
1371 static void exynos4210_fimd_write(void *opaque, hwaddr offset,
1372 uint64_t val, unsigned size)
1373 {
1374 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1375 unsigned w, i;
1376 uint32_t old_value;
1377
1378 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset,
1379 (long long unsigned int)val, (long long unsigned int)val);
1380
1381 switch (offset) {
1382 case FIMD_VIDCON0:
1383 if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) {
1384 exynos4210_fimd_enable(s, true);
1385 } else {
1386 if ((val & FIMD_VIDCON0_ENVID) == 0) {
1387 exynos4210_fimd_enable(s, false);
1388 }
1389 }
1390 s->vidcon[0] = val;
1391 break;
1392 case FIMD_VIDCON1:
1393 /* Leave read-only bits as is */
1394 val = (val & (~FIMD_VIDCON1_ROMASK)) |
1395 (s->vidcon[1] & FIMD_VIDCON1_ROMASK);
1396 s->vidcon[1] = val;
1397 break;
1398 case FIMD_VIDCON2 ... FIMD_VIDCON3:
1399 s->vidcon[(offset) >> 2] = val;
1400 break;
1401 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1402 s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val;
1403 break;
1404 case FIMD_WINCON_START ... FIMD_WINCON_END:
1405 w = (offset - FIMD_WINCON_START) >> 2;
1406 /* Window's current buffer ID */
1407 i = fimd_get_buffer_id(&s->window[w]);
1408 old_value = s->window[w].wincon;
1409 val = (val & ~FIMD_WINCON_ROMASK) |
1410 (s->window[w].wincon & FIMD_WINCON_ROMASK);
1411 if (w == 0) {
1412 /* Window 0 wincon ALPHA_MUL bit must always be 0 */
1413 val &= ~FIMD_WINCON_ALPHA_MUL;
1414 }
1415 exynos4210_fimd_trace_bppmode(s, w, val);
1416 switch (val & FIMD_WINCON_BUFSELECT) {
1417 case FIMD_WINCON_BUF0_SEL:
1418 val &= ~FIMD_WINCON_BUFSTATUS;
1419 break;
1420 case FIMD_WINCON_BUF1_SEL:
1421 val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L;
1422 break;
1423 case FIMD_WINCON_BUF2_SEL:
1424 if (val & FIMD_WINCON_BUFMODE) {
1425 val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H;
1426 }
1427 break;
1428 default:
1429 break;
1430 }
1431 s->window[w].wincon = val;
1432 exynos4210_fimd_update_win_bppmode(s, w);
1433 fimd_update_get_alpha(s, w);
1434 if ((i != fimd_get_buffer_id(&s->window[w])) ||
1435 (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon &
1436 FIMD_WINCON_ENWIN))) {
1437 fimd_update_memory_section(s, w);
1438 }
1439 break;
1440 case FIMD_SHADOWCON:
1441 old_value = s->shadowcon;
1442 s->shadowcon = val;
1443 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1444 if (FIMD_WINDOW_PROTECTED(old_value, w) &&
1445 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) {
1446 fimd_update_memory_section(s, w);
1447 }
1448 }
1449 break;
1450 case FIMD_WINCHMAP:
1451 s->winchmap = val;
1452 break;
1453 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1454 w = (offset - FIMD_VIDOSD_START) >> 4;
1455 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1456 switch (i) {
1457 case 0:
1458 old_value = s->window[w].lefttop_y;
1459 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1460 FIMD_VIDOSD_COORD_MASK;
1461 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1462 FIMD_VIDOSD_COORD_MASK;
1463 if (s->window[w].lefttop_y != old_value) {
1464 fimd_update_memory_section(s, w);
1465 }
1466 break;
1467 case 1:
1468 old_value = s->window[w].rightbot_y;
1469 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1470 FIMD_VIDOSD_COORD_MASK;
1471 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1472 FIMD_VIDOSD_COORD_MASK;
1473 if (s->window[w].rightbot_y != old_value) {
1474 fimd_update_memory_section(s, w);
1475 }
1476 break;
1477 case 2:
1478 if (w == 0) {
1479 s->window[w].osdsize = val;
1480 } else {
1481 s->window[w].alpha_val[0] =
1482 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >>
1483 FIMD_VIDOSD_AEN0_SHIFT) |
1484 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER);
1485 s->window[w].alpha_val[1] =
1486 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) |
1487 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER);
1488 }
1489 break;
1490 case 3:
1491 if (w != 1 && w != 2) {
1492 DPRINT_ERROR("Bad write offset 0x%08x\n", offset);
1493 return;
1494 }
1495 s->window[w].osdsize = val;
1496 break;
1497 }
1498 break;
1499 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1500 w = (offset - FIMD_VIDWADD0_START) >> 3;
1501 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1502 if (i == fimd_get_buffer_id(&s->window[w]) &&
1503 s->window[w].buf_start[i] != val) {
1504 s->window[w].buf_start[i] = val;
1505 fimd_update_memory_section(s, w);
1506 break;
1507 }
1508 s->window[w].buf_start[i] = val;
1509 break;
1510 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1511 w = (offset - FIMD_VIDWADD1_START) >> 3;
1512 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1513 s->window[w].buf_end[i] = val;
1514 break;
1515 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1516 w = (offset - FIMD_VIDWADD2_START) >> 2;
1517 if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) ||
1518 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) !=
1519 s->window[w].virtpage_offsize)) {
1520 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH;
1521 s->window[w].virtpage_offsize =
1522 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE;
1523 fimd_update_memory_section(s, w);
1524 }
1525 break;
1526 case FIMD_VIDINTCON0:
1527 s->vidintcon[0] = val;
1528 break;
1529 case FIMD_VIDINTCON1:
1530 s->vidintcon[1] &= ~(val & 7);
1531 exynos4210_fimd_update_irq(s);
1532 break;
1533 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1534 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1535 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1536 s->window[w].keycon[i] = val;
1537 break;
1538 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1539 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1540 s->window[w].keyalpha = val;
1541 break;
1542 case FIMD_DITHMODE:
1543 s->dithmode = val;
1544 break;
1545 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1546 w = (offset - FIMD_WINMAP_START) >> 2;
1547 old_value = s->window[w].winmap;
1548 s->window[w].winmap = val;
1549 if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) {
1550 exynos4210_fimd_invalidate(s);
1551 exynos4210_fimd_update_win_bppmode(s, w);
1552 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1553 exynos4210_fimd_update(s);
1554 }
1555 break;
1556 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1557 i = (offset - FIMD_WPALCON_HIGH) >> 2;
1558 s->wpalcon[i] = val;
1559 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) {
1560 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1561 exynos4210_fimd_update_win_bppmode(s, w);
1562 fimd_update_get_alpha(s, w);
1563 }
1564 }
1565 break;
1566 case FIMD_TRIGCON:
1567 val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK);
1568 s->trigcon = val;
1569 break;
1570 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1571 s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val;
1572 break;
1573 case FIMD_COLORGAINCON:
1574 s->colorgaincon = val;
1575 break;
1576 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1577 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val;
1578 break;
1579 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1580 i = (offset - FIMD_SIFCCON0) >> 2;
1581 if (i != 2) {
1582 s->sifccon[i] = val;
1583 }
1584 break;
1585 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1586 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1587 s->huecoef_cr[i] = val;
1588 break;
1589 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1590 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1591 s->huecoef_cb[i] = val;
1592 break;
1593 case FIMD_HUEOFFSET:
1594 s->hueoffset = val;
1595 break;
1596 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1597 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1598 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1599 if (w == 0) {
1600 s->window[w].alpha_val[i] = val;
1601 } else {
1602 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) |
1603 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER);
1604 }
1605 break;
1606 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1607 s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val;
1608 break;
1609 case FIMD_BLENDCON:
1610 old_value = s->blendcon;
1611 s->blendcon = val;
1612 if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) {
1613 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1614 fimd_update_get_alpha(s, w);
1615 }
1616 }
1617 break;
1618 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1619 s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val;
1620 break;
1621 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1622 s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val;
1623 break;
1624 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1625 if (offset & 0x0004) {
1626 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1627 break;
1628 }
1629 w = (offset - FIMD_VIDW0ADD0_B2) >> 3;
1630 if (fimd_get_buffer_id(&s->window[w]) == 2 &&
1631 s->window[w].buf_start[2] != val) {
1632 s->window[w].buf_start[2] = val;
1633 fimd_update_memory_section(s, w);
1634 break;
1635 }
1636 s->window[w].buf_start[2] = val;
1637 break;
1638 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1639 if (offset & 0x0004) {
1640 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1641 break;
1642 }
1643 s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val;
1644 break;
1645 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1646 if (offset & 0x0004) {
1647 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1648 break;
1649 }
1650 s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val;
1651 break;
1652 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1653 s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val;
1654 break;
1655 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1656 w = (offset - FIMD_PAL_MEM_START) >> 10;
1657 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1658 s->window[w].palette[i] = val;
1659 break;
1660 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1661 /* Palette memory aliases for windows 0 and 1 */
1662 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1663 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1664 s->window[w].palette[i] = val;
1665 break;
1666 default:
1667 DPRINT_ERROR("bad write offset 0x%08x\n", offset);
1668 break;
1669 }
1670 }
1671
1672 static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
1673 unsigned size)
1674 {
1675 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1676 int w, i;
1677 uint32_t ret = 0;
1678
1679 DPRINT_L2("read offset 0x%08x\n", offset);
1680
1681 switch (offset) {
1682 case FIMD_VIDCON0 ... FIMD_VIDCON3:
1683 return s->vidcon[(offset - FIMD_VIDCON0) >> 2];
1684 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1685 return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2];
1686 case FIMD_WINCON_START ... FIMD_WINCON_END:
1687 return s->window[(offset - FIMD_WINCON_START) >> 2].wincon;
1688 case FIMD_SHADOWCON:
1689 return s->shadowcon;
1690 case FIMD_WINCHMAP:
1691 return s->winchmap;
1692 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1693 w = (offset - FIMD_VIDOSD_START) >> 4;
1694 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1695 switch (i) {
1696 case 0:
1697 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) <<
1698 FIMD_VIDOSD_HOR_SHIFT) |
1699 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK);
1700 break;
1701 case 1:
1702 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) <<
1703 FIMD_VIDOSD_HOR_SHIFT) |
1704 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK);
1705 break;
1706 case 2:
1707 if (w == 0) {
1708 ret = s->window[w].osdsize;
1709 } else {
1710 ret = (pack_upper_4(s->window[w].alpha_val[0]) <<
1711 FIMD_VIDOSD_AEN0_SHIFT) |
1712 pack_upper_4(s->window[w].alpha_val[1]);
1713 }
1714 break;
1715 case 3:
1716 if (w != 1 && w != 2) {
1717 DPRINT_ERROR("bad read offset 0x%08x\n", offset);
1718 return 0xBAADBAAD;
1719 }
1720 ret = s->window[w].osdsize;
1721 break;
1722 }
1723 return ret;
1724 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1725 w = (offset - FIMD_VIDWADD0_START) >> 3;
1726 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1727 return s->window[w].buf_start[i];
1728 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1729 w = (offset - FIMD_VIDWADD1_START) >> 3;
1730 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1731 return s->window[w].buf_end[i];
1732 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1733 w = (offset - FIMD_VIDWADD2_START) >> 2;
1734 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize <<
1735 FIMD_VIDWADD2_OFFSIZE_SHIFT);
1736 case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1:
1737 return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2];
1738 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1739 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1740 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1741 return s->window[w].keycon[i];
1742 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1743 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1744 return s->window[w].keyalpha;
1745 case FIMD_DITHMODE:
1746 return s->dithmode;
1747 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1748 return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap;
1749 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1750 return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2];
1751 case FIMD_TRIGCON:
1752 return s->trigcon;
1753 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1754 return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2];
1755 case FIMD_COLORGAINCON:
1756 return s->colorgaincon;
1757 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1758 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2];
1759 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1760 i = (offset - FIMD_SIFCCON0) >> 2;
1761 return s->sifccon[i];
1762 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1763 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1764 return s->huecoef_cr[i];
1765 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1766 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1767 return s->huecoef_cb[i];
1768 case FIMD_HUEOFFSET:
1769 return s->hueoffset;
1770 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1771 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1772 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1773 return s->window[w].alpha_val[i] &
1774 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER);
1775 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1776 return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq;
1777 case FIMD_BLENDCON:
1778 return s->blendcon;
1779 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1780 return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon;
1781 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1782 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2];
1783 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1784 if (offset & 0x0004) {
1785 break;
1786 }
1787 return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2];
1788 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1789 if (offset & 0x0004) {
1790 break;
1791 }
1792 return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start;
1793 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1794 if (offset & 0x0004) {
1795 break;
1796 }
1797 return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end;
1798 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1799 return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size;
1800 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1801 w = (offset - FIMD_PAL_MEM_START) >> 10;
1802 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1803 return s->window[w].palette[i];
1804 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1805 /* Palette aliases for win 0,1 */
1806 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1807 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1808 return s->window[w].palette[i];
1809 }
1810
1811 DPRINT_ERROR("bad read offset 0x%08x\n", offset);
1812 return 0xBAADBAAD;
1813 }
1814
1815 static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
1816 .read = exynos4210_fimd_read,
1817 .write = exynos4210_fimd_write,
1818 .valid = {
1819 .min_access_size = 4,
1820 .max_access_size = 4,
1821 .unaligned = false
1822 },
1823 .endianness = DEVICE_NATIVE_ENDIAN,
1824 };
1825
1826 static int exynos4210_fimd_load(void *opaque, int version_id)
1827 {
1828 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1829 int w;
1830
1831 if (version_id != 1) {
1832 return -EINVAL;
1833 }
1834
1835 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1836 exynos4210_fimd_update_win_bppmode(s, w);
1837 fimd_update_get_alpha(s, w);
1838 fimd_update_memory_section(s, w);
1839 }
1840
1841 /* Redraw the whole screen */
1842 exynos4210_update_resolution(s);
1843 exynos4210_fimd_invalidate(s);
1844 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) ==
1845 FIMD_VIDCON0_ENVID_MASK);
1846 return 0;
1847 }
1848
1849 static const VMStateDescription exynos4210_fimd_window_vmstate = {
1850 .name = "exynos4210.fimd_window",
1851 .version_id = 1,
1852 .minimum_version_id = 1,
1853 .fields = (VMStateField[]) {
1854 VMSTATE_UINT32(wincon, Exynos4210fimdWindow),
1855 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3),
1856 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3),
1857 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2),
1858 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow),
1859 VMSTATE_UINT32(winmap, Exynos4210fimdWindow),
1860 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow),
1861 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow),
1862 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256),
1863 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow),
1864 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow),
1865 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow),
1866 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow),
1867 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow),
1868 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow),
1869 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow),
1870 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow),
1871 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2),
1872 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow),
1873 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow),
1874 VMSTATE_END_OF_LIST()
1875 }
1876 };
1877
1878 static const VMStateDescription exynos4210_fimd_vmstate = {
1879 .name = "exynos4210.fimd",
1880 .version_id = 1,
1881 .minimum_version_id = 1,
1882 .post_load = exynos4210_fimd_load,
1883 .fields = (VMStateField[]) {
1884 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4),
1885 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4),
1886 VMSTATE_UINT32(shadowcon, Exynos4210fimdState),
1887 VMSTATE_UINT32(winchmap, Exynos4210fimdState),
1888 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2),
1889 VMSTATE_UINT32(dithmode, Exynos4210fimdState),
1890 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2),
1891 VMSTATE_UINT32(trigcon, Exynos4210fimdState),
1892 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4),
1893 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState),
1894 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2),
1895 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3),
1896 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4),
1897 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4),
1898 VMSTATE_UINT32(hueoffset, Exynos4210fimdState),
1899 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12),
1900 VMSTATE_UINT32(blendcon, Exynos4210fimdState),
1901 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1,
1902 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow),
1903 VMSTATE_END_OF_LIST()
1904 }
1905 };
1906
1907 static const GraphicHwOps exynos4210_fimd_ops = {
1908 .invalidate = exynos4210_fimd_invalidate,
1909 .gfx_update = exynos4210_fimd_update,
1910 };
1911
1912 static void exynos4210_fimd_init(Object *obj)
1913 {
1914 Exynos4210fimdState *s = EXYNOS4210_FIMD(obj);
1915 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1916
1917 s->ifb = NULL;
1918
1919 sysbus_init_irq(dev, &s->irq[0]);
1920 sysbus_init_irq(dev, &s->irq[1]);
1921 sysbus_init_irq(dev, &s->irq[2]);
1922
1923 memory_region_init_io(&s->iomem, obj, &exynos4210_fimd_mmio_ops, s,
1924 "exynos4210.fimd", FIMD_REGS_SIZE);
1925 sysbus_init_mmio(dev, &s->iomem);
1926 }
1927
1928 static void exynos4210_fimd_realize(DeviceState *dev, Error **errp)
1929 {
1930 Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
1931
1932 s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s);
1933 }
1934
1935 static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
1936 {
1937 DeviceClass *dc = DEVICE_CLASS(klass);
1938
1939 dc->vmsd = &exynos4210_fimd_vmstate;
1940 dc->reset = exynos4210_fimd_reset;
1941 dc->realize = exynos4210_fimd_realize;
1942 }
1943
1944 static const TypeInfo exynos4210_fimd_info = {
1945 .name = TYPE_EXYNOS4210_FIMD,
1946 .parent = TYPE_SYS_BUS_DEVICE,
1947 .instance_size = sizeof(Exynos4210fimdState),
1948 .instance_init = exynos4210_fimd_init,
1949 .class_init = exynos4210_fimd_class_init,
1950 };
1951
1952 static void exynos4210_fimd_register_types(void)
1953 {
1954 type_register_static(&exynos4210_fimd_info);
1955 }
1956
1957 type_init(exynos4210_fimd_register_types)
Ray Wang's QEMU Repository