target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree
[qemu/rayw.git] / tests / tcg / riscv64 / semicall.h
blobf8c88f32dc5898be7c55dd892acf5b35d005fc8d
1 /*
2 * Semihosting Tests - RiscV64 Helper
4 * Copyright (c) 2021
5 * Written by Alex Bennée <alex.bennee@linaro.org>
7 * SPDX-License-Identifier: GPL-3.0-or-later
8 */
10 uintptr_t __semi_call(uintptr_t type, uintptr_t arg0)
12 register uintptr_t t asm("a0") = type;
13 register uintptr_t a0 asm("a1") = arg0;
14 asm(".option norvc\n\t"
15 ".balign 16\n\t"
16 "slli zero, zero, 0x1f\n\t"
17 "ebreak\n\t"
18 "srai zero, zero, 0x7\n\t"
19 : "=r" (t)
20 : "r" (t), "r" (a0));
21 return t;