2 * RISC-V implementation of KVM hooks
4 * Copyright (c) 2020 Huawei Technologies Co., Ltd
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include <sys/ioctl.h>
22 #include <linux/kvm.h>
24 #include "qemu/timer.h"
25 #include "qemu/error-report.h"
26 #include "qemu/main-loop.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/kvm_int.h"
32 #include "hw/pci/pci.h"
33 #include "exec/memattrs.h"
34 #include "exec/address-spaces.h"
35 #include "hw/boards.h"
38 #include "hw/loader.h"
39 #include "kvm_riscv.h"
40 #include "sbi_ecall_interface.h"
41 #include "chardev/char-fe.h"
42 #include "migration/migration.h"
43 #include "sysemu/runstate.h"
45 static uint64_t kvm_riscv_reg_id(CPURISCVState
*env
, uint64_t type
,
48 uint64_t id
= KVM_REG_RISCV
| type
| idx
;
50 switch (riscv_cpu_mxl(env
)) {
52 id
|= KVM_REG_SIZE_U32
;
55 id
|= KVM_REG_SIZE_U64
;
58 g_assert_not_reached();
63 #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
64 KVM_REG_RISCV_CORE_REG(name))
66 #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
67 KVM_REG_RISCV_CSR_REG(name))
69 #define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
70 KVM_REG_RISCV_TIMER_REG(name))
72 #define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
74 #define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
76 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
78 int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
84 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
86 int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
92 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
94 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \
100 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
102 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \
108 static int kvm_riscv_get_regs_core(CPUState
*cs
)
113 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
115 ret
= kvm_get_one_reg(cs
, RISCV_CORE_REG(env
, regs
.pc
), ®
);
121 for (i
= 1; i
< 32; i
++) {
122 uint64_t id
= kvm_riscv_reg_id(env
, KVM_REG_RISCV_CORE
, i
);
123 ret
= kvm_get_one_reg(cs
, id
, ®
);
133 static int kvm_riscv_put_regs_core(CPUState
*cs
)
138 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
141 ret
= kvm_set_one_reg(cs
, RISCV_CORE_REG(env
, regs
.pc
), ®
);
146 for (i
= 1; i
< 32; i
++) {
147 uint64_t id
= kvm_riscv_reg_id(env
, KVM_REG_RISCV_CORE
, i
);
149 ret
= kvm_set_one_reg(cs
, id
, ®
);
158 static int kvm_riscv_get_regs_csr(CPUState
*cs
)
161 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
163 KVM_RISCV_GET_CSR(cs
, env
, sstatus
, env
->mstatus
);
164 KVM_RISCV_GET_CSR(cs
, env
, sie
, env
->mie
);
165 KVM_RISCV_GET_CSR(cs
, env
, stvec
, env
->stvec
);
166 KVM_RISCV_GET_CSR(cs
, env
, sscratch
, env
->sscratch
);
167 KVM_RISCV_GET_CSR(cs
, env
, sepc
, env
->sepc
);
168 KVM_RISCV_GET_CSR(cs
, env
, scause
, env
->scause
);
169 KVM_RISCV_GET_CSR(cs
, env
, stval
, env
->stval
);
170 KVM_RISCV_GET_CSR(cs
, env
, sip
, env
->mip
);
171 KVM_RISCV_GET_CSR(cs
, env
, satp
, env
->satp
);
175 static int kvm_riscv_put_regs_csr(CPUState
*cs
)
178 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
180 KVM_RISCV_SET_CSR(cs
, env
, sstatus
, env
->mstatus
);
181 KVM_RISCV_SET_CSR(cs
, env
, sie
, env
->mie
);
182 KVM_RISCV_SET_CSR(cs
, env
, stvec
, env
->stvec
);
183 KVM_RISCV_SET_CSR(cs
, env
, sscratch
, env
->sscratch
);
184 KVM_RISCV_SET_CSR(cs
, env
, sepc
, env
->sepc
);
185 KVM_RISCV_SET_CSR(cs
, env
, scause
, env
->scause
);
186 KVM_RISCV_SET_CSR(cs
, env
, stval
, env
->stval
);
187 KVM_RISCV_SET_CSR(cs
, env
, sip
, env
->mip
);
188 KVM_RISCV_SET_CSR(cs
, env
, satp
, env
->satp
);
193 static int kvm_riscv_get_regs_fp(CPUState
*cs
)
197 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
199 if (riscv_has_ext(env
, RVD
)) {
201 for (i
= 0; i
< 32; i
++) {
202 ret
= kvm_get_one_reg(cs
, RISCV_FP_D_REG(env
, i
), ®
);
211 if (riscv_has_ext(env
, RVF
)) {
213 for (i
= 0; i
< 32; i
++) {
214 ret
= kvm_get_one_reg(cs
, RISCV_FP_F_REG(env
, i
), ®
);
226 static int kvm_riscv_put_regs_fp(CPUState
*cs
)
230 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
232 if (riscv_has_ext(env
, RVD
)) {
234 for (i
= 0; i
< 32; i
++) {
236 ret
= kvm_set_one_reg(cs
, RISCV_FP_D_REG(env
, i
), ®
);
244 if (riscv_has_ext(env
, RVF
)) {
246 for (i
= 0; i
< 32; i
++) {
248 ret
= kvm_set_one_reg(cs
, RISCV_FP_F_REG(env
, i
), ®
);
259 static void kvm_riscv_get_regs_timer(CPUState
*cs
)
261 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
263 if (env
->kvm_timer_dirty
) {
267 KVM_RISCV_GET_TIMER(cs
, env
, time
, env
->kvm_timer_time
);
268 KVM_RISCV_GET_TIMER(cs
, env
, compare
, env
->kvm_timer_compare
);
269 KVM_RISCV_GET_TIMER(cs
, env
, state
, env
->kvm_timer_state
);
270 KVM_RISCV_GET_TIMER(cs
, env
, frequency
, env
->kvm_timer_frequency
);
272 env
->kvm_timer_dirty
= true;
275 static void kvm_riscv_put_regs_timer(CPUState
*cs
)
278 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
280 if (!env
->kvm_timer_dirty
) {
284 KVM_RISCV_SET_TIMER(cs
, env
, time
, env
->kvm_timer_time
);
285 KVM_RISCV_SET_TIMER(cs
, env
, compare
, env
->kvm_timer_compare
);
288 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
289 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
290 * doesn't matter that adaping in QEMU now.
291 * TODO If KVM changes, adapt here.
293 if (env
->kvm_timer_state
) {
294 KVM_RISCV_SET_TIMER(cs
, env
, state
, env
->kvm_timer_state
);
298 * For now, migration will not work between Hosts with different timer
299 * frequency. Therefore, we should check whether they are the same here
300 * during the migration.
302 if (migration_is_running(migrate_get_current()->state
)) {
303 KVM_RISCV_GET_TIMER(cs
, env
, frequency
, reg
);
304 if (reg
!= env
->kvm_timer_frequency
) {
305 error_report("Dst Hosts timer frequency != Src Hosts");
309 env
->kvm_timer_dirty
= false;
312 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
316 int kvm_arch_get_registers(CPUState
*cs
)
320 ret
= kvm_riscv_get_regs_core(cs
);
325 ret
= kvm_riscv_get_regs_csr(cs
);
330 ret
= kvm_riscv_get_regs_fp(cs
);
338 int kvm_arch_put_registers(CPUState
*cs
, int level
)
342 ret
= kvm_riscv_put_regs_core(cs
);
347 ret
= kvm_riscv_put_regs_csr(cs
);
352 ret
= kvm_riscv_put_regs_fp(cs
);
360 int kvm_arch_release_virq_post(int virq
)
365 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
366 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
371 int kvm_arch_destroy_vcpu(CPUState
*cs
)
376 unsigned long kvm_arch_vcpu_id(CPUState
*cpu
)
378 return cpu
->cpu_index
;
381 static void kvm_riscv_vm_state_change(void *opaque
, bool running
,
384 CPUState
*cs
= opaque
;
387 kvm_riscv_put_regs_timer(cs
);
389 kvm_riscv_get_regs_timer(cs
);
393 void kvm_arch_init_irq_routing(KVMState
*s
)
397 int kvm_arch_init_vcpu(CPUState
*cs
)
401 RISCVCPU
*cpu
= RISCV_CPU(cs
);
402 CPURISCVState
*env
= &cpu
->env
;
405 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change
, cs
);
407 id
= kvm_riscv_reg_id(env
, KVM_REG_RISCV_CONFIG
,
408 KVM_REG_RISCV_CONFIG_REG(isa
));
409 ret
= kvm_get_one_reg(cs
, id
, &isa
);
418 int kvm_arch_msi_data_to_gsi(uint32_t data
)
423 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
424 int vector
, PCIDevice
*dev
)
429 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
434 int kvm_arch_irqchip_create(KVMState
*s
)
439 int kvm_arch_process_async_events(CPUState
*cs
)
444 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
448 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
450 return MEMTXATTRS_UNSPECIFIED
;
453 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
458 static int kvm_riscv_handle_sbi(CPUState
*cs
, struct kvm_run
*run
)
462 switch (run
->riscv_sbi
.extension_id
) {
463 case SBI_EXT_0_1_CONSOLE_PUTCHAR
:
464 ch
= run
->riscv_sbi
.args
[0];
465 qemu_chr_fe_write(serial_hd(0)->be
, &ch
, sizeof(ch
));
467 case SBI_EXT_0_1_CONSOLE_GETCHAR
:
468 ret
= qemu_chr_fe_read_all(serial_hd(0)->be
, &ch
, sizeof(ch
));
469 if (ret
== sizeof(ch
)) {
470 run
->riscv_sbi
.args
[0] = ch
;
472 run
->riscv_sbi
.args
[0] = -1;
476 qemu_log_mask(LOG_UNIMP
,
477 "%s: un-handled SBI EXIT, specific reasons is %lu\n",
478 __func__
, run
->riscv_sbi
.extension_id
);
485 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
488 switch (run
->exit_reason
) {
489 case KVM_EXIT_RISCV_SBI
:
490 ret
= kvm_riscv_handle_sbi(cs
, run
);
493 qemu_log_mask(LOG_UNIMP
, "%s: un-handled exit reason %d\n",
494 __func__
, run
->exit_reason
);
501 void kvm_riscv_reset_vcpu(RISCVCPU
*cpu
)
503 CPURISCVState
*env
= &cpu
->env
;
505 if (!kvm_enabled()) {
508 env
->pc
= cpu
->env
.kernel_addr
;
509 env
->gpr
[10] = kvm_arch_vcpu_id(CPU(cpu
)); /* a0 */
510 env
->gpr
[11] = cpu
->env
.fdt_addr
; /* a1 */
514 void kvm_riscv_set_irq(RISCVCPU
*cpu
, int irq
, int level
)
517 unsigned virq
= level
? KVM_INTERRUPT_SET
: KVM_INTERRUPT_UNSET
;
519 if (irq
!= IRQ_S_EXT
) {
520 perror("kvm riscv set irq != IRQ_S_EXT\n");
524 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_INTERRUPT
, &virq
);
526 perror("Set irq failed");
531 bool kvm_arch_cpu_check_are_resettable(void)