2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "sysemu/tcg.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28 #include "qemu/cpu-float.h"
30 /* The x86 has a strong memory model with some store-after-load re-ordering */
31 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
33 #define KVM_HAVE_MCE_INJECTION 1
35 /* support for self modifying code even if the modified instruction is
36 close to the modifying instruction */
37 #define TARGET_HAS_PRECISE_SMC
40 #define I386_ELF_MACHINE EM_X86_64
41 #define ELF_MACHINE_UNAME "x86_64"
43 #define I386_ELF_MACHINE EM_386
44 #define ELF_MACHINE_UNAME "i686"
86 /* segment descriptor fields */
87 #define DESC_G_SHIFT 23
88 #define DESC_G_MASK (1 << DESC_G_SHIFT)
89 #define DESC_B_SHIFT 22
90 #define DESC_B_MASK (1 << DESC_B_SHIFT)
91 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
92 #define DESC_L_MASK (1 << DESC_L_SHIFT)
93 #define DESC_AVL_SHIFT 20
94 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
95 #define DESC_P_SHIFT 15
96 #define DESC_P_MASK (1 << DESC_P_SHIFT)
97 #define DESC_DPL_SHIFT 13
98 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
99 #define DESC_S_SHIFT 12
100 #define DESC_S_MASK (1 << DESC_S_SHIFT)
101 #define DESC_TYPE_SHIFT 8
102 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
103 #define DESC_A_MASK (1 << 8)
105 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
106 #define DESC_C_MASK (1 << 10) /* code: conforming */
107 #define DESC_R_MASK (1 << 9) /* code: readable */
109 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
110 #define DESC_W_MASK (1 << 9) /* data: writable */
112 #define DESC_TSS_BUSY_MASK (1 << 9)
123 #define IOPL_SHIFT 12
126 #define TF_MASK 0x00000100
127 #define IF_MASK 0x00000200
128 #define DF_MASK 0x00000400
129 #define IOPL_MASK 0x00003000
130 #define NT_MASK 0x00004000
131 #define RF_MASK 0x00010000
132 #define VM_MASK 0x00020000
133 #define AC_MASK 0x00040000
134 #define VIF_MASK 0x00080000
135 #define VIP_MASK 0x00100000
136 #define ID_MASK 0x00200000
138 /* hidden flags - used internally by qemu to represent additional cpu
139 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
140 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
141 positions to ease oring with eflags. */
143 #define HF_CPL_SHIFT 0
144 /* true if hardware interrupts must be disabled for next instruction */
145 #define HF_INHIBIT_IRQ_SHIFT 3
146 /* 16 or 32 segments */
147 #define HF_CS32_SHIFT 4
148 #define HF_SS32_SHIFT 5
149 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
150 #define HF_ADDSEG_SHIFT 6
151 /* copy of CR0.PE (protected mode) */
152 #define HF_PE_SHIFT 7
153 #define HF_TF_SHIFT 8 /* must be same as eflags */
154 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
155 #define HF_EM_SHIFT 10
156 #define HF_TS_SHIFT 11
157 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
158 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
159 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
160 #define HF_RF_SHIFT 16 /* must be same as eflags */
161 #define HF_VM_SHIFT 17 /* must be same as eflags */
162 #define HF_AC_SHIFT 18 /* must be same as eflags */
163 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
164 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
165 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
166 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
167 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
168 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
169 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
170 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
171 #define HF_UMIP_SHIFT 27 /* CR4.UMIP */
173 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
174 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
175 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
176 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
177 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
178 #define HF_PE_MASK (1 << HF_PE_SHIFT)
179 #define HF_TF_MASK (1 << HF_TF_SHIFT)
180 #define HF_MP_MASK (1 << HF_MP_SHIFT)
181 #define HF_EM_MASK (1 << HF_EM_SHIFT)
182 #define HF_TS_MASK (1 << HF_TS_SHIFT)
183 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
184 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
185 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
186 #define HF_RF_MASK (1 << HF_RF_SHIFT)
187 #define HF_VM_MASK (1 << HF_VM_SHIFT)
188 #define HF_AC_MASK (1 << HF_AC_SHIFT)
189 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
190 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
191 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
192 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
193 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
194 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
195 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
196 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
197 #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
201 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
202 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
203 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
204 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
205 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
206 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
207 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
208 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
209 #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/
211 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
212 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
213 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
214 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
215 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
216 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
217 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
218 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
219 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
221 #define CR0_PE_SHIFT 0
222 #define CR0_MP_SHIFT 1
224 #define CR0_PE_MASK (1U << 0)
225 #define CR0_MP_MASK (1U << 1)
226 #define CR0_EM_MASK (1U << 2)
227 #define CR0_TS_MASK (1U << 3)
228 #define CR0_ET_MASK (1U << 4)
229 #define CR0_NE_MASK (1U << 5)
230 #define CR0_WP_MASK (1U << 16)
231 #define CR0_AM_MASK (1U << 18)
232 #define CR0_NW_MASK (1U << 29)
233 #define CR0_CD_MASK (1U << 30)
234 #define CR0_PG_MASK (1U << 31)
236 #define CR4_VME_MASK (1U << 0)
237 #define CR4_PVI_MASK (1U << 1)
238 #define CR4_TSD_MASK (1U << 2)
239 #define CR4_DE_MASK (1U << 3)
240 #define CR4_PSE_MASK (1U << 4)
241 #define CR4_PAE_MASK (1U << 5)
242 #define CR4_MCE_MASK (1U << 6)
243 #define CR4_PGE_MASK (1U << 7)
244 #define CR4_PCE_MASK (1U << 8)
245 #define CR4_OSFXSR_SHIFT 9
246 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
247 #define CR4_OSXMMEXCPT_MASK (1U << 10)
248 #define CR4_UMIP_MASK (1U << 11)
249 #define CR4_LA57_MASK (1U << 12)
250 #define CR4_VMXE_MASK (1U << 13)
251 #define CR4_SMXE_MASK (1U << 14)
252 #define CR4_FSGSBASE_MASK (1U << 16)
253 #define CR4_PCIDE_MASK (1U << 17)
254 #define CR4_OSXSAVE_MASK (1U << 18)
255 #define CR4_SMEP_MASK (1U << 20)
256 #define CR4_SMAP_MASK (1U << 21)
257 #define CR4_PKE_MASK (1U << 22)
258 #define CR4_PKS_MASK (1U << 24)
260 #define CR4_RESERVED_MASK \
261 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
262 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
263 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
264 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
266 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
267 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
269 #define DR6_BD (1 << 13)
270 #define DR6_BS (1 << 14)
271 #define DR6_BT (1 << 15)
272 #define DR6_FIXED_1 0xffff0ff0
274 #define DR7_GD (1 << 13)
275 #define DR7_TYPE_SHIFT 16
276 #define DR7_LEN_SHIFT 18
277 #define DR7_FIXED_1 0x00000400
278 #define DR7_GLOBAL_BP_MASK 0xaa
279 #define DR7_LOCAL_BP_MASK 0x55
281 #define DR7_TYPE_BP_INST 0x0
282 #define DR7_TYPE_DATA_WR 0x1
283 #define DR7_TYPE_IO_RW 0x2
284 #define DR7_TYPE_DATA_RW 0x3
286 #define DR_RESERVED_MASK 0xffffffff00000000ULL
288 #define PG_PRESENT_BIT 0
290 #define PG_USER_BIT 2
293 #define PG_ACCESSED_BIT 5
294 #define PG_DIRTY_BIT 6
296 #define PG_GLOBAL_BIT 8
297 #define PG_PSE_PAT_BIT 12
298 #define PG_PKRU_BIT 59
301 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
302 #define PG_RW_MASK (1 << PG_RW_BIT)
303 #define PG_USER_MASK (1 << PG_USER_BIT)
304 #define PG_PWT_MASK (1 << PG_PWT_BIT)
305 #define PG_PCD_MASK (1 << PG_PCD_BIT)
306 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
307 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
308 #define PG_PSE_MASK (1 << PG_PSE_BIT)
309 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
310 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
311 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
312 #define PG_HI_USER_MASK 0x7ff0000000000000LL
313 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
314 #define PG_NX_MASK (1ULL << PG_NX_BIT)
316 #define PG_ERROR_W_BIT 1
318 #define PG_ERROR_P_MASK 0x01
319 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
320 #define PG_ERROR_U_MASK 0x04
321 #define PG_ERROR_RSVD_MASK 0x08
322 #define PG_ERROR_I_D_MASK 0x10
323 #define PG_ERROR_PK_MASK 0x20
325 #define PG_MODE_PAE (1 << 0)
326 #define PG_MODE_LMA (1 << 1)
327 #define PG_MODE_NXE (1 << 2)
328 #define PG_MODE_PSE (1 << 3)
329 #define PG_MODE_LA57 (1 << 4)
330 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
332 /* Bits of CR4 that do not affect the NPT page format. */
333 #define PG_MODE_WP (1 << 16)
334 #define PG_MODE_PKE (1 << 17)
335 #define PG_MODE_PKS (1 << 18)
336 #define PG_MODE_SMEP (1 << 19)
338 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
339 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
340 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
342 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
343 #define MCE_BANKS_DEF 10
345 #define MCG_CAP_BANKS_MASK 0xff
347 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
348 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
349 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
350 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
352 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
354 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
355 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
356 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
357 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
358 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
359 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
360 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
361 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
362 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
364 /* MISC register defines */
365 #define MCM_ADDR_SEGOFF 0 /* segment offset */
366 #define MCM_ADDR_LINEAR 1 /* linear address */
367 #define MCM_ADDR_PHYS 2 /* physical address */
368 #define MCM_ADDR_MEM 3 /* memory address */
369 #define MCM_ADDR_GENERIC 7 /* generic */
371 #define MSR_IA32_TSC 0x10
372 #define MSR_IA32_APICBASE 0x1b
373 #define MSR_IA32_APICBASE_BSP (1<<8)
374 #define MSR_IA32_APICBASE_ENABLE (1<<11)
375 #define MSR_IA32_APICBASE_EXTD (1 << 10)
376 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
377 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
378 #define MSR_TSC_ADJUST 0x0000003b
379 #define MSR_IA32_SPEC_CTRL 0x48
380 #define MSR_VIRT_SSBD 0xc001011f
381 #define MSR_IA32_PRED_CMD 0x49
382 #define MSR_IA32_UCODE_REV 0x8b
383 #define MSR_IA32_CORE_CAPABILITY 0xcf
385 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
386 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
388 #define MSR_IA32_PERF_CAPABILITIES 0x345
389 #define PERF_CAP_LBR_FMT 0x3f
391 #define MSR_IA32_TSX_CTRL 0x122
392 #define MSR_IA32_TSCDEADLINE 0x6e0
393 #define MSR_IA32_PKRS 0x6e1
394 #define MSR_ARCH_LBR_CTL 0x000014ce
395 #define MSR_ARCH_LBR_DEPTH 0x000014cf
396 #define MSR_ARCH_LBR_FROM_0 0x00001500
397 #define MSR_ARCH_LBR_TO_0 0x00001600
398 #define MSR_ARCH_LBR_INFO_0 0x00001200
400 #define FEATURE_CONTROL_LOCKED (1<<0)
401 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
402 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
403 #define FEATURE_CONTROL_SGX_LC (1ULL << 17)
404 #define FEATURE_CONTROL_SGX (1ULL << 18)
405 #define FEATURE_CONTROL_LMCE (1<<20)
407 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
408 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
409 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
410 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
412 #define MSR_P6_PERFCTR0 0xc1
414 #define MSR_IA32_SMBASE 0x9e
415 #define MSR_SMI_COUNT 0x34
416 #define MSR_CORE_THREAD_COUNT 0x35
417 #define MSR_MTRRcap 0xfe
418 #define MSR_MTRRcap_VCNT 8
419 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
420 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
422 #define MSR_IA32_SYSENTER_CS 0x174
423 #define MSR_IA32_SYSENTER_ESP 0x175
424 #define MSR_IA32_SYSENTER_EIP 0x176
426 #define MSR_MCG_CAP 0x179
427 #define MSR_MCG_STATUS 0x17a
428 #define MSR_MCG_CTL 0x17b
429 #define MSR_MCG_EXT_CTL 0x4d0
431 #define MSR_P6_EVNTSEL0 0x186
433 #define MSR_IA32_PERF_STATUS 0x198
435 #define MSR_IA32_MISC_ENABLE 0x1a0
436 /* Indicates good rep/movs microcode on some processors: */
437 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
438 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
440 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
441 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
443 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
445 #define MSR_MTRRfix64K_00000 0x250
446 #define MSR_MTRRfix16K_80000 0x258
447 #define MSR_MTRRfix16K_A0000 0x259
448 #define MSR_MTRRfix4K_C0000 0x268
449 #define MSR_MTRRfix4K_C8000 0x269
450 #define MSR_MTRRfix4K_D0000 0x26a
451 #define MSR_MTRRfix4K_D8000 0x26b
452 #define MSR_MTRRfix4K_E0000 0x26c
453 #define MSR_MTRRfix4K_E8000 0x26d
454 #define MSR_MTRRfix4K_F0000 0x26e
455 #define MSR_MTRRfix4K_F8000 0x26f
457 #define MSR_PAT 0x277
459 #define MSR_MTRRdefType 0x2ff
461 #define MSR_CORE_PERF_FIXED_CTR0 0x309
462 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
463 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
464 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
465 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
466 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
467 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
469 #define MSR_MC0_CTL 0x400
470 #define MSR_MC0_STATUS 0x401
471 #define MSR_MC0_ADDR 0x402
472 #define MSR_MC0_MISC 0x403
474 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
475 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
476 #define MSR_IA32_RTIT_CTL 0x570
477 #define MSR_IA32_RTIT_STATUS 0x571
478 #define MSR_IA32_RTIT_CR3_MATCH 0x572
479 #define MSR_IA32_RTIT_ADDR0_A 0x580
480 #define MSR_IA32_RTIT_ADDR0_B 0x581
481 #define MSR_IA32_RTIT_ADDR1_A 0x582
482 #define MSR_IA32_RTIT_ADDR1_B 0x583
483 #define MSR_IA32_RTIT_ADDR2_A 0x584
484 #define MSR_IA32_RTIT_ADDR2_B 0x585
485 #define MSR_IA32_RTIT_ADDR3_A 0x586
486 #define MSR_IA32_RTIT_ADDR3_B 0x587
487 #define MAX_RTIT_ADDRS 8
489 #define MSR_EFER 0xc0000080
491 #define MSR_EFER_SCE (1 << 0)
492 #define MSR_EFER_LME (1 << 8)
493 #define MSR_EFER_LMA (1 << 10)
494 #define MSR_EFER_NXE (1 << 11)
495 #define MSR_EFER_SVME (1 << 12)
496 #define MSR_EFER_FFXSR (1 << 14)
498 #define MSR_EFER_RESERVED\
499 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
500 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
503 #define MSR_STAR 0xc0000081
504 #define MSR_LSTAR 0xc0000082
505 #define MSR_CSTAR 0xc0000083
506 #define MSR_FMASK 0xc0000084
507 #define MSR_FSBASE 0xc0000100
508 #define MSR_GSBASE 0xc0000101
509 #define MSR_KERNELGSBASE 0xc0000102
510 #define MSR_TSC_AUX 0xc0000103
511 #define MSR_AMD64_TSC_RATIO 0xc0000104
513 #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
515 #define MSR_VM_HSAVE_PA 0xc0010117
517 #define MSR_IA32_XFD 0x000001c4
518 #define MSR_IA32_XFD_ERR 0x000001c5
520 #define MSR_IA32_BNDCFGS 0x00000d90
521 #define MSR_IA32_XSS 0x00000da0
522 #define MSR_IA32_UMWAIT_CONTROL 0xe1
524 #define MSR_IA32_VMX_BASIC 0x00000480
525 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
526 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
527 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
528 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
529 #define MSR_IA32_VMX_MISC 0x00000485
530 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
531 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
532 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
533 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
534 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
535 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
536 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
537 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
538 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
539 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
540 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
541 #define MSR_IA32_VMX_VMFUNC 0x00000491
543 #define XSTATE_FP_BIT 0
544 #define XSTATE_SSE_BIT 1
545 #define XSTATE_YMM_BIT 2
546 #define XSTATE_BNDREGS_BIT 3
547 #define XSTATE_BNDCSR_BIT 4
548 #define XSTATE_OPMASK_BIT 5
549 #define XSTATE_ZMM_Hi256_BIT 6
550 #define XSTATE_Hi16_ZMM_BIT 7
551 #define XSTATE_PKRU_BIT 9
552 #define XSTATE_ARCH_LBR_BIT 15
553 #define XSTATE_XTILE_CFG_BIT 17
554 #define XSTATE_XTILE_DATA_BIT 18
556 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
557 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
558 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
559 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
560 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
561 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
562 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
563 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
564 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
565 #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
566 #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
567 #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
569 #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
571 #define ESA_FEATURE_ALIGN64_BIT 1
572 #define ESA_FEATURE_XFD_BIT 2
574 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
575 #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
578 /* CPUID feature bits available in XCR0 */
579 #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
580 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
581 XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
582 XSTATE_ZMM_Hi256_MASK | \
583 XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
584 XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
586 /* CPUID feature words */
587 typedef enum FeatureWord
{
588 FEAT_1_EDX
, /* CPUID[1].EDX */
589 FEAT_1_ECX
, /* CPUID[1].ECX */
590 FEAT_7_0_EBX
, /* CPUID[EAX=7,ECX=0].EBX */
591 FEAT_7_0_ECX
, /* CPUID[EAX=7,ECX=0].ECX */
592 FEAT_7_0_EDX
, /* CPUID[EAX=7,ECX=0].EDX */
593 FEAT_7_1_EAX
, /* CPUID[EAX=7,ECX=1].EAX */
594 FEAT_8000_0001_EDX
, /* CPUID[8000_0001].EDX */
595 FEAT_8000_0001_ECX
, /* CPUID[8000_0001].ECX */
596 FEAT_8000_0007_EDX
, /* CPUID[8000_0007].EDX */
597 FEAT_8000_0008_EBX
, /* CPUID[8000_0008].EBX */
598 FEAT_C000_0001_EDX
, /* CPUID[C000_0001].EDX */
599 FEAT_KVM
, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
600 FEAT_KVM_HINTS
, /* CPUID[4000_0001].EDX */
601 FEAT_SVM
, /* CPUID[8000_000A].EDX */
602 FEAT_XSAVE
, /* CPUID[EAX=0xd,ECX=1].EAX */
603 FEAT_6_EAX
, /* CPUID[6].EAX */
604 FEAT_XSAVE_XCR0_LO
, /* CPUID[EAX=0xd,ECX=0].EAX */
605 FEAT_XSAVE_XCR0_HI
, /* CPUID[EAX=0xd,ECX=0].EDX */
606 FEAT_ARCH_CAPABILITIES
,
607 FEAT_CORE_CAPABILITY
,
608 FEAT_PERF_CAPABILITIES
,
609 FEAT_VMX_PROCBASED_CTLS
,
610 FEAT_VMX_SECONDARY_CTLS
,
611 FEAT_VMX_PINBASED_CTLS
,
615 FEAT_VMX_EPT_VPID_CAPS
,
619 FEAT_SGX_12_0_EAX
, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
620 FEAT_SGX_12_0_EBX
, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
621 FEAT_SGX_12_1_EAX
, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
622 FEAT_XSAVE_XSS_LO
, /* CPUID[EAX=0xd,ECX=1].ECX */
623 FEAT_XSAVE_XSS_HI
, /* CPUID[EAX=0xd,ECX=1].EDX */
627 typedef uint64_t FeatureWordArray
[FEATURE_WORDS
];
628 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w
,
629 bool migratable_only
);
631 /* cpuid_features bits */
632 #define CPUID_FP87 (1U << 0)
633 #define CPUID_VME (1U << 1)
634 #define CPUID_DE (1U << 2)
635 #define CPUID_PSE (1U << 3)
636 #define CPUID_TSC (1U << 4)
637 #define CPUID_MSR (1U << 5)
638 #define CPUID_PAE (1U << 6)
639 #define CPUID_MCE (1U << 7)
640 #define CPUID_CX8 (1U << 8)
641 #define CPUID_APIC (1U << 9)
642 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
643 #define CPUID_MTRR (1U << 12)
644 #define CPUID_PGE (1U << 13)
645 #define CPUID_MCA (1U << 14)
646 #define CPUID_CMOV (1U << 15)
647 #define CPUID_PAT (1U << 16)
648 #define CPUID_PSE36 (1U << 17)
649 #define CPUID_PN (1U << 18)
650 #define CPUID_CLFLUSH (1U << 19)
651 #define CPUID_DTS (1U << 21)
652 #define CPUID_ACPI (1U << 22)
653 #define CPUID_MMX (1U << 23)
654 #define CPUID_FXSR (1U << 24)
655 #define CPUID_SSE (1U << 25)
656 #define CPUID_SSE2 (1U << 26)
657 #define CPUID_SS (1U << 27)
658 #define CPUID_HT (1U << 28)
659 #define CPUID_TM (1U << 29)
660 #define CPUID_IA64 (1U << 30)
661 #define CPUID_PBE (1U << 31)
663 #define CPUID_EXT_SSE3 (1U << 0)
664 #define CPUID_EXT_PCLMULQDQ (1U << 1)
665 #define CPUID_EXT_DTES64 (1U << 2)
666 #define CPUID_EXT_MONITOR (1U << 3)
667 #define CPUID_EXT_DSCPL (1U << 4)
668 #define CPUID_EXT_VMX (1U << 5)
669 #define CPUID_EXT_SMX (1U << 6)
670 #define CPUID_EXT_EST (1U << 7)
671 #define CPUID_EXT_TM2 (1U << 8)
672 #define CPUID_EXT_SSSE3 (1U << 9)
673 #define CPUID_EXT_CID (1U << 10)
674 #define CPUID_EXT_FMA (1U << 12)
675 #define CPUID_EXT_CX16 (1U << 13)
676 #define CPUID_EXT_XTPR (1U << 14)
677 #define CPUID_EXT_PDCM (1U << 15)
678 #define CPUID_EXT_PCID (1U << 17)
679 #define CPUID_EXT_DCA (1U << 18)
680 #define CPUID_EXT_SSE41 (1U << 19)
681 #define CPUID_EXT_SSE42 (1U << 20)
682 #define CPUID_EXT_X2APIC (1U << 21)
683 #define CPUID_EXT_MOVBE (1U << 22)
684 #define CPUID_EXT_POPCNT (1U << 23)
685 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
686 #define CPUID_EXT_AES (1U << 25)
687 #define CPUID_EXT_XSAVE (1U << 26)
688 #define CPUID_EXT_OSXSAVE (1U << 27)
689 #define CPUID_EXT_AVX (1U << 28)
690 #define CPUID_EXT_F16C (1U << 29)
691 #define CPUID_EXT_RDRAND (1U << 30)
692 #define CPUID_EXT_HYPERVISOR (1U << 31)
694 #define CPUID_EXT2_FPU (1U << 0)
695 #define CPUID_EXT2_VME (1U << 1)
696 #define CPUID_EXT2_DE (1U << 2)
697 #define CPUID_EXT2_PSE (1U << 3)
698 #define CPUID_EXT2_TSC (1U << 4)
699 #define CPUID_EXT2_MSR (1U << 5)
700 #define CPUID_EXT2_PAE (1U << 6)
701 #define CPUID_EXT2_MCE (1U << 7)
702 #define CPUID_EXT2_CX8 (1U << 8)
703 #define CPUID_EXT2_APIC (1U << 9)
704 #define CPUID_EXT2_SYSCALL (1U << 11)
705 #define CPUID_EXT2_MTRR (1U << 12)
706 #define CPUID_EXT2_PGE (1U << 13)
707 #define CPUID_EXT2_MCA (1U << 14)
708 #define CPUID_EXT2_CMOV (1U << 15)
709 #define CPUID_EXT2_PAT (1U << 16)
710 #define CPUID_EXT2_PSE36 (1U << 17)
711 #define CPUID_EXT2_MP (1U << 19)
712 #define CPUID_EXT2_NX (1U << 20)
713 #define CPUID_EXT2_MMXEXT (1U << 22)
714 #define CPUID_EXT2_MMX (1U << 23)
715 #define CPUID_EXT2_FXSR (1U << 24)
716 #define CPUID_EXT2_FFXSR (1U << 25)
717 #define CPUID_EXT2_PDPE1GB (1U << 26)
718 #define CPUID_EXT2_RDTSCP (1U << 27)
719 #define CPUID_EXT2_LM (1U << 29)
720 #define CPUID_EXT2_3DNOWEXT (1U << 30)
721 #define CPUID_EXT2_3DNOW (1U << 31)
723 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
724 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
725 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
726 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
727 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
728 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
729 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
730 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
731 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
732 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
734 #define CPUID_EXT3_LAHF_LM (1U << 0)
735 #define CPUID_EXT3_CMP_LEG (1U << 1)
736 #define CPUID_EXT3_SVM (1U << 2)
737 #define CPUID_EXT3_EXTAPIC (1U << 3)
738 #define CPUID_EXT3_CR8LEG (1U << 4)
739 #define CPUID_EXT3_ABM (1U << 5)
740 #define CPUID_EXT3_SSE4A (1U << 6)
741 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
742 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
743 #define CPUID_EXT3_OSVW (1U << 9)
744 #define CPUID_EXT3_IBS (1U << 10)
745 #define CPUID_EXT3_XOP (1U << 11)
746 #define CPUID_EXT3_SKINIT (1U << 12)
747 #define CPUID_EXT3_WDT (1U << 13)
748 #define CPUID_EXT3_LWP (1U << 15)
749 #define CPUID_EXT3_FMA4 (1U << 16)
750 #define CPUID_EXT3_TCE (1U << 17)
751 #define CPUID_EXT3_NODEID (1U << 19)
752 #define CPUID_EXT3_TBM (1U << 21)
753 #define CPUID_EXT3_TOPOEXT (1U << 22)
754 #define CPUID_EXT3_PERFCORE (1U << 23)
755 #define CPUID_EXT3_PERFNB (1U << 24)
757 #define CPUID_SVM_NPT (1U << 0)
758 #define CPUID_SVM_LBRV (1U << 1)
759 #define CPUID_SVM_SVMLOCK (1U << 2)
760 #define CPUID_SVM_NRIPSAVE (1U << 3)
761 #define CPUID_SVM_TSCSCALE (1U << 4)
762 #define CPUID_SVM_VMCBCLEAN (1U << 5)
763 #define CPUID_SVM_FLUSHASID (1U << 6)
764 #define CPUID_SVM_DECODEASSIST (1U << 7)
765 #define CPUID_SVM_PAUSEFILTER (1U << 10)
766 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
767 #define CPUID_SVM_AVIC (1U << 13)
768 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
769 #define CPUID_SVM_VGIF (1U << 16)
770 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
772 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
773 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
775 #define CPUID_7_0_EBX_SGX (1U << 2)
776 /* 1st Group of Advanced Bit Manipulation Extensions */
777 #define CPUID_7_0_EBX_BMI1 (1U << 3)
778 /* Hardware Lock Elision */
779 #define CPUID_7_0_EBX_HLE (1U << 4)
780 /* Intel Advanced Vector Extensions 2 */
781 #define CPUID_7_0_EBX_AVX2 (1U << 5)
782 /* Supervisor-mode Execution Prevention */
783 #define CPUID_7_0_EBX_SMEP (1U << 7)
784 /* 2nd Group of Advanced Bit Manipulation Extensions */
785 #define CPUID_7_0_EBX_BMI2 (1U << 8)
786 /* Enhanced REP MOVSB/STOSB */
787 #define CPUID_7_0_EBX_ERMS (1U << 9)
788 /* Invalidate Process-Context Identifier */
789 #define CPUID_7_0_EBX_INVPCID (1U << 10)
790 /* Restricted Transactional Memory */
791 #define CPUID_7_0_EBX_RTM (1U << 11)
792 /* Memory Protection Extension */
793 #define CPUID_7_0_EBX_MPX (1U << 14)
794 /* AVX-512 Foundation */
795 #define CPUID_7_0_EBX_AVX512F (1U << 16)
796 /* AVX-512 Doubleword & Quadword Instruction */
797 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
798 /* Read Random SEED */
799 #define CPUID_7_0_EBX_RDSEED (1U << 18)
800 /* ADCX and ADOX instructions */
801 #define CPUID_7_0_EBX_ADX (1U << 19)
802 /* Supervisor Mode Access Prevention */
803 #define CPUID_7_0_EBX_SMAP (1U << 20)
804 /* AVX-512 Integer Fused Multiply Add */
805 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
806 /* Persistent Commit */
807 #define CPUID_7_0_EBX_PCOMMIT (1U << 22)
808 /* Flush a Cache Line Optimized */
809 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
810 /* Cache Line Write Back */
811 #define CPUID_7_0_EBX_CLWB (1U << 24)
812 /* Intel Processor Trace */
813 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
814 /* AVX-512 Prefetch */
815 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
816 /* AVX-512 Exponential and Reciprocal */
817 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
818 /* AVX-512 Conflict Detection */
819 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
820 /* SHA1/SHA256 Instruction Extensions */
821 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
822 /* AVX-512 Byte and Word Instructions */
823 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
824 /* AVX-512 Vector Length Extensions */
825 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
827 /* AVX-512 Vector Byte Manipulation Instruction */
828 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
829 /* User-Mode Instruction Prevention */
830 #define CPUID_7_0_ECX_UMIP (1U << 2)
831 /* Protection Keys for User-mode Pages */
832 #define CPUID_7_0_ECX_PKU (1U << 3)
833 /* OS Enable Protection Keys */
834 #define CPUID_7_0_ECX_OSPKE (1U << 4)
835 /* UMONITOR/UMWAIT/TPAUSE Instructions */
836 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
837 /* Additional AVX-512 Vector Byte Manipulation Instruction */
838 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
839 /* Galois Field New Instructions */
840 #define CPUID_7_0_ECX_GFNI (1U << 8)
841 /* Vector AES Instructions */
842 #define CPUID_7_0_ECX_VAES (1U << 9)
843 /* Carry-Less Multiplication Quadword */
844 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
845 /* Vector Neural Network Instructions */
846 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
847 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
848 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
849 /* POPCNT for vectors of DW/QW */
850 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
851 /* 5-level Page Tables */
852 #define CPUID_7_0_ECX_LA57 (1U << 16)
853 /* Read Processor ID */
854 #define CPUID_7_0_ECX_RDPID (1U << 22)
855 /* Bus Lock Debug Exception */
856 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
857 /* Cache Line Demote Instruction */
858 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
859 /* Move Doubleword as Direct Store Instruction */
860 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
861 /* Move 64 Bytes as Direct Store Instruction */
862 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
863 /* Support SGX Launch Control */
864 #define CPUID_7_0_ECX_SGX_LC (1U << 30)
865 /* Protection Keys for Supervisor-mode Pages */
866 #define CPUID_7_0_ECX_PKS (1U << 31)
868 /* AVX512 Neural Network Instructions */
869 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
870 /* AVX512 Multiply Accumulation Single Precision */
871 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
872 /* Fast Short Rep Mov */
873 #define CPUID_7_0_EDX_FSRM (1U << 4)
874 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
875 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
876 /* SERIALIZE instruction */
877 #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
878 /* TSX Suspend Load Address Tracking instruction */
879 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
880 /* Architectural LBRs */
881 #define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
882 /* AVX512_FP16 instruction */
883 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
884 /* AMX tile (two-dimensional register) */
885 #define CPUID_7_0_EDX_AMX_TILE (1U << 24)
886 /* Speculation Control */
887 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
888 /* Single Thread Indirect Branch Predictors */
889 #define CPUID_7_0_EDX_STIBP (1U << 27)
890 /* Arch Capabilities */
891 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
892 /* Core Capability */
893 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
894 /* Speculative Store Bypass Disable */
895 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
897 /* AVX VNNI Instruction */
898 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
899 /* AVX512 BFloat16 Instruction */
900 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
901 /* XFD Extend Feature Disabled */
902 #define CPUID_D_1_EAX_XFD (1U << 4)
904 /* Packets which contain IP payload have LIP values */
905 #define CPUID_14_0_ECX_LIP (1U << 31)
907 /* CLZERO instruction */
908 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
909 /* Always save/restore FP error pointers */
910 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
911 /* Write back and do not invalidate cache */
912 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
913 /* Indirect Branch Prediction Barrier */
914 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
915 /* Indirect Branch Restricted Speculation */
916 #define CPUID_8000_0008_EBX_IBRS (1U << 14)
917 /* Single Thread Indirect Branch Predictors */
918 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
919 /* Speculative Store Bypass Disable */
920 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
922 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
923 #define CPUID_XSAVE_XSAVEC (1U << 1)
924 #define CPUID_XSAVE_XGETBV1 (1U << 2)
925 #define CPUID_XSAVE_XSAVES (1U << 3)
927 #define CPUID_6_EAX_ARAT (1U << 2)
929 /* CPUID[0x80000007].EDX flags: */
930 #define CPUID_APM_INVTSC (1U << 8)
932 #define CPUID_VENDOR_SZ 12
934 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
935 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
936 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
937 #define CPUID_VENDOR_INTEL "GenuineIntel"
939 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
940 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
941 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
942 #define CPUID_VENDOR_AMD "AuthenticAMD"
944 #define CPUID_VENDOR_VIA "CentaurHauls"
946 #define CPUID_VENDOR_HYGON "HygonGenuine"
948 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
949 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
950 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
951 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
952 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
953 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
955 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
956 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
958 /* CPUID[0xB].ECX level types */
959 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
960 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
961 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
962 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
964 /* MSR Feature Bits */
965 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
966 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
967 #define MSR_ARCH_CAP_RSBA (1U << 2)
968 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
969 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
970 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
971 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
972 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
973 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
975 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
977 /* VMX MSR features */
978 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
979 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
980 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
981 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
982 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
983 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
985 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
986 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
987 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
988 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
989 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
990 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
991 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
992 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
994 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
995 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
996 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
997 #define MSR_VMX_EPT_UC (1ULL << 8)
998 #define MSR_VMX_EPT_WB (1ULL << 14)
999 #define MSR_VMX_EPT_2MB (1ULL << 16)
1000 #define MSR_VMX_EPT_1GB (1ULL << 17)
1001 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
1002 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1003 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1004 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1005 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1006 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
1007 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1008 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1009 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1010 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1012 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1016 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1017 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1018 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
1019 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1020 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1021 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1022 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1023 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1024 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1025 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1026 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1027 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1028 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1029 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1030 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1031 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1032 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1033 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1034 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1035 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1036 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1038 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1039 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1040 #define VMX_SECONDARY_EXEC_DESC 0x00000004
1041 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1042 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1043 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1044 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1045 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1046 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1047 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1048 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1049 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1050 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1051 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1052 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1053 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1054 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1055 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1056 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1057 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1059 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1060 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
1061 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1062 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1063 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
1065 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1066 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1067 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1068 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1069 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1070 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1071 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1072 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1073 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1074 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1075 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1076 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1077 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1079 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1080 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1081 #define VMX_VM_ENTRY_SMM 0x00000400
1082 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1083 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1084 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1085 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1086 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1087 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1088 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1089 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1091 /* Supported Hyper-V Enlightenments */
1092 #define HYPERV_FEAT_RELAXED 0
1093 #define HYPERV_FEAT_VAPIC 1
1094 #define HYPERV_FEAT_TIME 2
1095 #define HYPERV_FEAT_CRASH 3
1096 #define HYPERV_FEAT_RESET 4
1097 #define HYPERV_FEAT_VPINDEX 5
1098 #define HYPERV_FEAT_RUNTIME 6
1099 #define HYPERV_FEAT_SYNIC 7
1100 #define HYPERV_FEAT_STIMER 8
1101 #define HYPERV_FEAT_FREQUENCIES 9
1102 #define HYPERV_FEAT_REENLIGHTENMENT 10
1103 #define HYPERV_FEAT_TLBFLUSH 11
1104 #define HYPERV_FEAT_EVMCS 12
1105 #define HYPERV_FEAT_IPI 13
1106 #define HYPERV_FEAT_STIMER_DIRECT 14
1107 #define HYPERV_FEAT_AVIC 15
1108 #define HYPERV_FEAT_SYNDBG 16
1109 #define HYPERV_FEAT_MSR_BITMAP 17
1110 #define HYPERV_FEAT_XMM_INPUT 18
1111 #define HYPERV_FEAT_TLBFLUSH_EXT 19
1112 #define HYPERV_FEAT_TLBFLUSH_DIRECT 20
1114 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1115 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1118 #define EXCP00_DIVZ 0
1120 #define EXCP02_NMI 2
1121 #define EXCP03_INT3 3
1122 #define EXCP04_INTO 4
1123 #define EXCP05_BOUND 5
1124 #define EXCP06_ILLOP 6
1125 #define EXCP07_PREX 7
1126 #define EXCP08_DBLE 8
1127 #define EXCP09_XERR 9
1128 #define EXCP0A_TSS 10
1129 #define EXCP0B_NOSEG 11
1130 #define EXCP0C_STACK 12
1131 #define EXCP0D_GPF 13
1132 #define EXCP0E_PAGE 14
1133 #define EXCP10_COPR 16
1134 #define EXCP11_ALGN 17
1135 #define EXCP12_MCHK 18
1137 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1138 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1139 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1141 /* i386-specific interrupt pending bits. */
1142 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1143 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1144 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1145 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1146 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1147 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1148 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1150 /* Use a clearer name for this. */
1151 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1153 /* Instead of computing the condition codes after each x86 instruction,
1154 * QEMU just stores one operand (called CC_SRC), the result
1155 * (called CC_DST) and the type of operation (called CC_OP). When the
1156 * condition codes are needed, the condition codes can be calculated
1157 * using this information. Condition codes are not generated if they
1158 * are only needed for conditional branches.
1161 CC_OP_DYNAMIC
, /* must use dynamic code to get cc_op */
1162 CC_OP_EFLAGS
, /* all cc are explicitly computed, CC_SRC = flags */
1164 CC_OP_MULB
, /* modify all flags, C, O = (CC_SRC != 0) */
1169 CC_OP_ADDB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1174 CC_OP_ADCB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1179 CC_OP_SUBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1184 CC_OP_SBBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1189 CC_OP_LOGICB
, /* modify all flags, CC_DST = res */
1194 CC_OP_INCB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
1199 CC_OP_DECB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
1204 CC_OP_SHLB
, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1209 CC_OP_SARB
, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1214 CC_OP_BMILGB
, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1219 CC_OP_ADCX
, /* CC_DST = C, CC_SRC = rest. */
1220 CC_OP_ADOX
, /* CC_DST = O, CC_SRC = rest. */
1221 CC_OP_ADCOX
, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1223 CC_OP_CLR
, /* Z set, all other flags clear. */
1224 CC_OP_POPCNT
, /* Z via CC_SRC, all other flags clear. */
1229 typedef struct SegmentCache
{
1236 #define MMREG_UNION(n, bits) \
1238 uint8_t _b_##n[(bits)/8]; \
1239 uint16_t _w_##n[(bits)/16]; \
1240 uint32_t _l_##n[(bits)/32]; \
1241 uint64_t _q_##n[(bits)/64]; \
1242 float32 _s_##n[(bits)/32]; \
1243 float64 _d_##n[(bits)/64]; \
1246 typedef MMREG_UNION(ZMMReg
, 512) ZMMReg
;
1247 typedef MMREG_UNION(MMXReg
, 64) MMXReg
;
1249 typedef struct BNDReg
{
1254 typedef struct BNDCSReg
{
1259 #define BNDCFG_ENABLE 1ULL
1260 #define BNDCFG_BNDPRESERVE 2ULL
1261 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1264 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1265 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1266 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1267 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1268 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1269 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1271 #define MMX_B(n) _b_MMXReg[7 - (n)]
1272 #define MMX_W(n) _w_MMXReg[3 - (n)]
1273 #define MMX_L(n) _l_MMXReg[1 - (n)]
1274 #define MMX_S(n) _s_MMXReg[1 - (n)]
1276 #define ZMM_B(n) _b_ZMMReg[n]
1277 #define ZMM_W(n) _w_ZMMReg[n]
1278 #define ZMM_L(n) _l_ZMMReg[n]
1279 #define ZMM_S(n) _s_ZMMReg[n]
1280 #define ZMM_Q(n) _q_ZMMReg[n]
1281 #define ZMM_D(n) _d_ZMMReg[n]
1283 #define MMX_B(n) _b_MMXReg[n]
1284 #define MMX_W(n) _w_MMXReg[n]
1285 #define MMX_L(n) _l_MMXReg[n]
1286 #define MMX_S(n) _s_MMXReg[n]
1288 #define MMX_Q(n) _q_MMXReg[n]
1291 floatx80 d
__attribute__((aligned(16)));
1300 #define CPU_NB_REGS64 16
1301 #define CPU_NB_REGS32 8
1303 #ifdef TARGET_X86_64
1304 #define CPU_NB_REGS CPU_NB_REGS64
1306 #define CPU_NB_REGS CPU_NB_REGS32
1309 #define MAX_FIXED_COUNTERS 3
1310 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1312 #define TARGET_INSN_START_EXTRA_WORDS 1
1314 #define NB_OPMASK_REGS 8
1316 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1317 * that APIC ID hasn't been set yet
1319 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1321 typedef union X86LegacyXSaveArea
{
1331 uint32_t mxcsr_mask
;
1333 uint8_t xmm_regs
[16][16];
1336 } X86LegacyXSaveArea
;
1338 typedef struct X86XSaveHeader
{
1342 uint8_t reserved
[40];
1345 /* Ext. save area 2: AVX State */
1346 typedef struct XSaveAVX
{
1347 uint8_t ymmh
[16][16];
1350 /* Ext. save area 3: BNDREG */
1351 typedef struct XSaveBNDREG
{
1355 /* Ext. save area 4: BNDCSR */
1356 typedef union XSaveBNDCSR
{
1361 /* Ext. save area 5: Opmask */
1362 typedef struct XSaveOpmask
{
1363 uint64_t opmask_regs
[NB_OPMASK_REGS
];
1366 /* Ext. save area 6: ZMM_Hi256 */
1367 typedef struct XSaveZMM_Hi256
{
1368 uint8_t zmm_hi256
[16][32];
1371 /* Ext. save area 7: Hi16_ZMM */
1372 typedef struct XSaveHi16_ZMM
{
1373 uint8_t hi16_zmm
[16][64];
1376 /* Ext. save area 9: PKRU state */
1377 typedef struct XSavePKRU
{
1382 /* Ext. save area 17: AMX XTILECFG state */
1383 typedef struct XSaveXTILECFG
{
1384 uint8_t xtilecfg
[64];
1387 /* Ext. save area 18: AMX XTILEDATA state */
1388 typedef struct XSaveXTILEDATA
{
1389 uint8_t xtiledata
[8][1024];
1398 #define ARCH_LBR_NR_ENTRIES 32
1400 /* Ext. save area 19: Supervisor mode Arch LBR state */
1401 typedef struct XSavesArchLBR
{
1407 LBREntry lbr_records
[ARCH_LBR_NR_ENTRIES
];
1410 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX
) != 0x100);
1411 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG
) != 0x40);
1412 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR
) != 0x40);
1413 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask
) != 0x40);
1414 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256
) != 0x200);
1415 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM
) != 0x400);
1416 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU
) != 0x8);
1417 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG
) != 0x40);
1418 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA
) != 0x2000);
1419 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR
) != 0x328);
1421 typedef struct ExtSaveArea
{
1422 uint32_t feature
, bits
;
1423 uint32_t offset
, size
;
1427 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1429 extern ExtSaveArea x86_ext_save_areas
[XSAVE_STATE_AREA_COUNT
];
1431 typedef enum TPRAccess
{
1436 /* Cache information data structures: */
1444 typedef struct CPUCacheInfo
{
1445 enum CacheType type
;
1449 /* Line size, in bytes */
1453 * Note: representation of fully-associative caches is not implemented
1455 uint8_t associativity
;
1456 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1458 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1462 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1463 * (Is this synonym to @partitions?)
1465 uint8_t lines_per_tag
;
1467 /* Self-initializing cache */
1470 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1471 * non-originating threads sharing this cache.
1472 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1474 bool no_invd_sharing
;
1476 * Cache is inclusive of lower cache levels.
1477 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1481 * A complex function is used to index the cache, potentially using all
1482 * address bits. CPUID[4].EDX[bit 2].
1484 bool complex_indexing
;
1488 typedef struct CPUCaches
{
1489 CPUCacheInfo
*l1d_cache
;
1490 CPUCacheInfo
*l1i_cache
;
1491 CPUCacheInfo
*l2_cache
;
1492 CPUCacheInfo
*l3_cache
;
1495 typedef struct HVFX86LazyFlags
{
1496 target_ulong result
;
1497 target_ulong auxbits
;
1500 typedef struct CPUArchState
{
1501 /* standard registers */
1502 target_ulong regs
[CPU_NB_REGS
];
1504 target_ulong eflags
; /* eflags register. During CPU emulation, CC
1505 flags and DF are set to zero because they are
1508 /* emulator internal eflags handling */
1509 target_ulong cc_dst
;
1510 target_ulong cc_src
;
1511 target_ulong cc_src2
;
1513 int32_t df
; /* D flag : 1 if D = 0, -1 if D = 1 */
1514 uint32_t hflags
; /* TB flags, see HF_xxx constants. These flags
1515 are known at translation time. */
1516 uint32_t hflags2
; /* various other flags, see HF2_xxx constants. */
1519 SegmentCache segs
[6]; /* selector values */
1522 SegmentCache gdt
; /* only base and limit are used */
1523 SegmentCache idt
; /* only base and limit are used */
1525 target_ulong cr
[5]; /* NOTE: cr1 is unused */
1532 BNDCSReg bndcs_regs
;
1533 uint64_t msr_bndcfgs
;
1536 /* Beginning of state preserved by INIT (dummy marker). */
1537 struct {} start_init_save
;
1540 unsigned int fpstt
; /* top of stack index */
1543 uint8_t fptags
[8]; /* 0 = valid, 1 = empty */
1545 /* KVM-only so far */
1552 /* emulator internal variables */
1553 float_status fp_status
;
1556 float_status mmx_status
; /* for 3DNow! float ops */
1557 float_status sse_status
;
1559 ZMMReg xmm_regs
[CPU_NB_REGS
== 8 ? 8 : 32];
1563 uint64_t opmask_regs
[NB_OPMASK_REGS
];
1564 #ifdef TARGET_X86_64
1565 uint8_t xtilecfg
[64];
1566 uint8_t xtiledata
[8192];
1569 /* sysenter registers */
1570 uint32_t sysenter_cs
;
1571 target_ulong sysenter_esp
;
1572 target_ulong sysenter_eip
;
1577 #ifdef TARGET_X86_64
1581 target_ulong kernelgsbase
;
1584 uint64_t tsc_adjust
;
1585 uint64_t tsc_deadline
;
1590 uint64_t mcg_status
;
1591 uint64_t msr_ia32_misc_enable
;
1592 uint64_t msr_ia32_feature_control
;
1593 uint64_t msr_ia32_sgxlepubkeyhash
[4];
1595 uint64_t msr_fixed_ctr_ctrl
;
1596 uint64_t msr_global_ctrl
;
1597 uint64_t msr_global_status
;
1598 uint64_t msr_global_ovf_ctrl
;
1599 uint64_t msr_fixed_counters
[MAX_FIXED_COUNTERS
];
1600 uint64_t msr_gp_counters
[MAX_GP_COUNTERS
];
1601 uint64_t msr_gp_evtsel
[MAX_GP_COUNTERS
];
1605 uint64_t msr_smi_count
;
1612 uint64_t amd_tsc_scale_msr
;
1615 /* End of state preserved by INIT (dummy marker). */
1616 struct {} end_init_save
;
1618 uint64_t system_time_msr
;
1619 uint64_t wall_clock_msr
;
1620 uint64_t steal_time_msr
;
1621 uint64_t async_pf_en_msr
;
1622 uint64_t async_pf_int_msr
;
1623 uint64_t pv_eoi_en_msr
;
1624 uint64_t poll_control_msr
;
1626 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1627 uint64_t msr_hv_hypercall
;
1628 uint64_t msr_hv_guest_os_id
;
1629 uint64_t msr_hv_tsc
;
1630 uint64_t msr_hv_syndbg_control
;
1631 uint64_t msr_hv_syndbg_status
;
1632 uint64_t msr_hv_syndbg_send_page
;
1633 uint64_t msr_hv_syndbg_recv_page
;
1634 uint64_t msr_hv_syndbg_pending_page
;
1635 uint64_t msr_hv_syndbg_options
;
1637 /* Per-VCPU HV MSRs */
1638 uint64_t msr_hv_vapic
;
1639 uint64_t msr_hv_crash_params
[HV_CRASH_PARAMS
];
1640 uint64_t msr_hv_runtime
;
1641 uint64_t msr_hv_synic_control
;
1642 uint64_t msr_hv_synic_evt_page
;
1643 uint64_t msr_hv_synic_msg_page
;
1644 uint64_t msr_hv_synic_sint
[HV_SINT_COUNT
];
1645 uint64_t msr_hv_stimer_config
[HV_STIMER_COUNT
];
1646 uint64_t msr_hv_stimer_count
[HV_STIMER_COUNT
];
1647 uint64_t msr_hv_reenlightenment_control
;
1648 uint64_t msr_hv_tsc_emulation_control
;
1649 uint64_t msr_hv_tsc_emulation_status
;
1651 uint64_t msr_rtit_ctrl
;
1652 uint64_t msr_rtit_status
;
1653 uint64_t msr_rtit_output_base
;
1654 uint64_t msr_rtit_output_mask
;
1655 uint64_t msr_rtit_cr3_match
;
1656 uint64_t msr_rtit_addrs
[MAX_RTIT_ADDRS
];
1658 /* Per-VCPU XFD MSRs */
1660 uint64_t msr_xfd_err
;
1662 /* Per-VCPU Arch LBR MSRs */
1663 uint64_t msr_lbr_ctl
;
1664 uint64_t msr_lbr_depth
;
1665 LBREntry lbr_records
[ARCH_LBR_NR_ENTRIES
];
1667 /* exception/interrupt handling */
1669 int exception_is_int
;
1670 target_ulong exception_next_eip
;
1671 target_ulong dr
[8]; /* debug registers; note dr4 and dr5 are unused */
1673 struct CPUBreakpoint
*cpu_breakpoint
[4];
1674 struct CPUWatchpoint
*cpu_watchpoint
[4];
1675 }; /* break/watchpoints for dr[0..3] */
1676 int old_exception
; /* exception in flight */
1679 uint64_t tsc_offset
;
1681 uint16_t intercept_cr_read
;
1682 uint16_t intercept_cr_write
;
1683 uint16_t intercept_dr_read
;
1684 uint16_t intercept_dr_write
;
1685 uint32_t intercept_exceptions
;
1686 uint64_t nested_cr3
;
1687 uint32_t nested_pg_mode
;
1691 /* KVM states, automatically cleared on reset */
1692 uint8_t nmi_injected
;
1693 uint8_t nmi_pending
;
1697 /* Fields up to this point are cleared by a CPU reset */
1698 struct {} end_reset_fields
;
1700 /* Fields after this point are preserved across CPU reset. */
1702 /* processor features (e.g. for CPUID insn) */
1703 /* Minimum cpuid leaf 7 value */
1704 uint32_t cpuid_level_func7
;
1705 /* Actual cpuid leaf 7 value */
1706 uint32_t cpuid_min_level_func7
;
1707 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1708 uint32_t cpuid_min_level
, cpuid_min_xlevel
, cpuid_min_xlevel2
;
1709 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1710 uint32_t cpuid_max_level
, cpuid_max_xlevel
, cpuid_max_xlevel2
;
1711 /* Actual level/xlevel/xlevel2 value: */
1712 uint32_t cpuid_level
, cpuid_xlevel
, cpuid_xlevel2
;
1713 uint32_t cpuid_vendor1
;
1714 uint32_t cpuid_vendor2
;
1715 uint32_t cpuid_vendor3
;
1716 uint32_t cpuid_version
;
1717 FeatureWordArray features
;
1718 /* Features that were explicitly enabled/disabled */
1719 FeatureWordArray user_features
;
1720 uint32_t cpuid_model
[12];
1721 /* Cache information for CPUID. When legacy-cache=on, the cache data
1722 * on each CPUID leaf will be different, because we keep compatibility
1723 * with old QEMU versions.
1725 CPUCaches cache_info_cpuid2
, cache_info_cpuid4
, cache_info_amd
;
1728 uint64_t mtrr_fixed
[11];
1729 uint64_t mtrr_deftype
;
1730 MTRRVar mtrr_var
[MSR_MTRRcap_VCNT
];
1734 int32_t exception_nr
;
1735 int32_t interrupt_injected
;
1736 uint8_t soft_interrupt
;
1737 uint8_t exception_pending
;
1738 uint8_t exception_injected
;
1739 uint8_t has_error_code
;
1740 uint8_t exception_has_payload
;
1741 uint64_t exception_payload
;
1743 uint32_t sipi_vector
;
1746 int64_t user_tsc_khz
; /* for sanity check only */
1747 uint64_t apic_bus_freq
;
1749 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1751 uint32_t xsave_buf_len
;
1753 #if defined(CONFIG_KVM)
1754 struct kvm_nested_state
*nested_state
;
1756 #if defined(CONFIG_HVF)
1757 HVFX86LazyFlags hvf_lflags
;
1763 uint64_t mcg_ext_ctl
;
1764 uint64_t mce_banks
[MCE_BANKS_DEF
*4];
1768 uint16_t fpus_vmstate
;
1769 uint16_t fptag_vmstate
;
1770 uint16_t fpregs_format_vmstate
;
1775 TPRAccess tpr_access_type
;
1784 * @env: #CPUX86State
1785 * @migratable: If set, only migratable flags will be accepted when "enforce"
1786 * mode is used, and only migratable flags will be included in the "host"
1793 CPUState parent_obj
;
1796 CPUNegativeOffsetState neg
;
1798 VMChangeStateEntry
*vmsentry
;
1802 uint32_t hyperv_spinlock_attempts
;
1803 char *hyperv_vendor
;
1804 bool hyperv_synic_kvm_only
;
1805 uint64_t hyperv_features
;
1806 bool hyperv_passthrough
;
1807 OnOffAuto hyperv_no_nonarch_cs
;
1808 uint32_t hyperv_vendor_id
[3];
1809 uint32_t hyperv_interface_id
[4];
1810 uint32_t hyperv_limits
[3];
1811 bool hyperv_enforce_cpuid
;
1812 uint32_t hyperv_ver_id_build
;
1813 uint16_t hyperv_ver_id_major
;
1814 uint16_t hyperv_ver_id_minor
;
1815 uint32_t hyperv_ver_id_sp
;
1816 uint8_t hyperv_ver_id_sb
;
1817 uint32_t hyperv_ver_id_sn
;
1822 * Force features to be enabled even if the host doesn't support them.
1823 * This is dangerous and should be done only for testing CPUID
1826 bool force_features
;
1830 bool migrate_smi_count
;
1831 bool max_features
; /* Enable all supported features automatically */
1834 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1835 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1836 bool vmware_cpuid_freq
;
1838 /* if true the CPUID code directly forward host cache leaves to the guest */
1839 bool cache_info_passthrough
;
1841 /* if true the CPUID code directly forwards
1842 * host monitor/mwait leaves to the guest */
1850 /* Features that were filtered out because of missing host capabilities */
1851 FeatureWordArray filtered_features
;
1853 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1854 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1855 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1856 * capabilities) directly to the guest.
1861 * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
1862 * This can't be initialized with a default because it doesn't have
1863 * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
1864 * returned by kvm_arch_get_supported_msr_feature()(which depends on both
1865 * host CPU and kernel capabilities) to the guest.
1869 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1870 * disabled by default to avoid breaking migration between QEMU with
1871 * different LMCE configurations.
1875 /* Compatibility bits for old machine types.
1876 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1877 * socket share an virtual l3 cache.
1879 bool enable_l3_cache
;
1881 /* Compatibility bits for old machine types.
1882 * If true present the old cache topology information
1886 /* Compatibility bits for old machine types: */
1887 bool enable_cpuid_0xb
;
1889 /* Enable auto level-increase for all CPUID leaves */
1890 bool full_cpuid_auto_level
;
1892 /* Only advertise CPUID leaves defined by the vendor */
1893 bool vendor_cpuid_only
;
1895 /* Enable auto level-increase for Intel Processor Trace leave */
1896 bool intel_pt_auto_level
;
1898 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1899 bool fill_mtrr_mask
;
1901 /* if true override the phys_bits value with a value read from the host */
1902 bool host_phys_bits
;
1904 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
1905 uint8_t host_phys_bits_limit
;
1907 /* Stop SMI delivery for migration compatibility with old machines */
1908 bool kvm_no_smi_migration
;
1910 /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
1911 bool kvm_pv_enforce_cpuid
;
1913 /* Number of physical address bits supported */
1916 /* in order to simplify APIC support, we leave this pointer to the
1918 struct DeviceState
*apic_state
;
1919 struct MemoryRegion
*cpu_as_root
, *cpu_as_mem
, *smram
;
1920 Notifier machine_done
;
1922 struct kvm_msrs
*kvm_msr_buf
;
1924 int32_t node_id
; /* NUMA node this CPU belongs to */
1934 #ifndef CONFIG_USER_ONLY
1935 extern const VMStateDescription vmstate_x86_cpu
;
1938 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
);
1940 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
1941 int cpuid
, void *opaque
);
1942 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cpu
,
1943 int cpuid
, void *opaque
);
1944 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
1946 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f
, CPUState
*cpu
,
1949 void x86_cpu_get_memory_mapping(CPUState
*cpu
, MemoryMappingList
*list
,
1952 void x86_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
);
1954 hwaddr
x86_cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
1957 int x86_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
1958 int x86_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
1960 void x86_cpu_list(void);
1961 int cpu_x86_support_mca_broadcast(CPUX86State
*env
);
1963 #ifndef CONFIG_USER_ONLY
1964 int cpu_get_pic_interrupt(CPUX86State
*s
);
1966 /* MSDOS compatibility mode FPU exception support */
1967 void x86_register_ferr_irq(qemu_irq irq
);
1968 void fpu_check_raise_ferr_irq(CPUX86State
*s
);
1969 void cpu_set_ignne(void);
1970 void cpu_clear_ignne(void);
1974 void cpu_sync_bndcs_hflags(CPUX86State
*env
);
1976 /* this function must always be used to load data in the segment
1977 cache: it synchronizes the hflags with the segment cache values */
1978 static inline void cpu_x86_load_seg_cache(CPUX86State
*env
,
1979 X86Seg seg_reg
, unsigned int selector
,
1985 unsigned int new_hflags
;
1987 sc
= &env
->segs
[seg_reg
];
1988 sc
->selector
= selector
;
1993 /* update the hidden flags */
1995 if (seg_reg
== R_CS
) {
1996 #ifdef TARGET_X86_64
1997 if ((env
->hflags
& HF_LMA_MASK
) && (flags
& DESC_L_MASK
)) {
1999 env
->hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
2000 env
->hflags
&= ~(HF_ADDSEG_MASK
);
2004 /* legacy / compatibility case */
2005 new_hflags
= (env
->segs
[R_CS
].flags
& DESC_B_MASK
)
2006 >> (DESC_B_SHIFT
- HF_CS32_SHIFT
);
2007 env
->hflags
= (env
->hflags
& ~(HF_CS32_MASK
| HF_CS64_MASK
)) |
2011 if (seg_reg
== R_SS
) {
2012 int cpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
2013 #if HF_CPL_MASK != 3
2014 #error HF_CPL_MASK is hardcoded
2016 env
->hflags
= (env
->hflags
& ~HF_CPL_MASK
) | cpl
;
2017 /* Possibly switch between BNDCFGS and BNDCFGU */
2018 cpu_sync_bndcs_hflags(env
);
2020 new_hflags
= (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
2021 >> (DESC_B_SHIFT
- HF_SS32_SHIFT
);
2022 if (env
->hflags
& HF_CS64_MASK
) {
2023 /* zero base assumed for DS, ES and SS in long mode */
2024 } else if (!(env
->cr
[0] & CR0_PE_MASK
) ||
2025 (env
->eflags
& VM_MASK
) ||
2026 !(env
->hflags
& HF_CS32_MASK
)) {
2027 /* XXX: try to avoid this test. The problem comes from the
2028 fact that is real mode or vm86 mode we only modify the
2029 'base' and 'selector' fields of the segment cache to go
2030 faster. A solution may be to force addseg to one in
2031 translate-i386.c. */
2032 new_hflags
|= HF_ADDSEG_MASK
;
2034 new_hflags
|= ((env
->segs
[R_DS
].base
|
2035 env
->segs
[R_ES
].base
|
2036 env
->segs
[R_SS
].base
) != 0) <<
2039 env
->hflags
= (env
->hflags
&
2040 ~(HF_SS32_MASK
| HF_ADDSEG_MASK
)) | new_hflags
;
2044 static inline void cpu_x86_load_seg_cache_sipi(X86CPU
*cpu
,
2045 uint8_t sipi_vector
)
2047 CPUState
*cs
= CPU(cpu
);
2048 CPUX86State
*env
= &cpu
->env
;
2051 cpu_x86_load_seg_cache(env
, R_CS
, sipi_vector
<< 8,
2053 env
->segs
[R_CS
].limit
,
2054 env
->segs
[R_CS
].flags
);
2058 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
2059 target_ulong
*base
, unsigned int *limit
,
2060 unsigned int *flags
);
2063 /* used for debug or cpu save/restore */
2066 /* the following helpers are only usable in user mode simulation as
2067 they can trigger unexpected exceptions */
2068 void cpu_x86_load_seg(CPUX86State
*s
, X86Seg seg_reg
, int selector
);
2069 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
);
2070 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
);
2071 void cpu_x86_fxsave(CPUX86State
*s
, target_ulong ptr
);
2072 void cpu_x86_fxrstor(CPUX86State
*s
, target_ulong ptr
);
2075 void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
2076 uint32_t vendor2
, uint32_t vendor3
);
2077 typedef struct PropValue
{
2078 const char *prop
, *value
;
2080 void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
);
2082 uint32_t cpu_x86_virtual_addr_width(CPUX86State
*env
);
2084 /* cpu.c other functions (cpuid) */
2085 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2086 uint32_t *eax
, uint32_t *ebx
,
2087 uint32_t *ecx
, uint32_t *edx
);
2088 void cpu_clear_apic_feature(CPUX86State
*env
);
2089 void host_cpuid(uint32_t function
, uint32_t count
,
2090 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
);
2093 void x86_cpu_set_a20(X86CPU
*cpu
, int a20_state
);
2095 #ifndef CONFIG_USER_ONLY
2096 static inline int x86_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
2098 return !!attrs
.secure
;
2101 static inline AddressSpace
*cpu_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
2103 return cpu_get_address_space(cs
, cpu_asidx_from_attrs(cs
, attrs
));
2107 * load efer and update the corresponding hflags. XXX: do consistency
2108 * checks with cpuid bits?
2110 void cpu_load_efer(CPUX86State
*env
, uint64_t val
);
2111 uint8_t x86_ldub_phys(CPUState
*cs
, hwaddr addr
);
2112 uint32_t x86_lduw_phys(CPUState
*cs
, hwaddr addr
);
2113 uint32_t x86_ldl_phys(CPUState
*cs
, hwaddr addr
);
2114 uint64_t x86_ldq_phys(CPUState
*cs
, hwaddr addr
);
2115 void x86_stb_phys(CPUState
*cs
, hwaddr addr
, uint8_t val
);
2116 void x86_stl_phys_notdirty(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2117 void x86_stw_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2118 void x86_stl_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
);
2119 void x86_stq_phys(CPUState
*cs
, hwaddr addr
, uint64_t val
);
2122 /* will be suppressed */
2123 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
);
2124 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
);
2125 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
);
2126 void cpu_x86_update_dr7(CPUX86State
*env
, uint32_t new_dr7
);
2129 uint64_t cpu_get_tsc(CPUX86State
*env
);
2131 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
2132 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
2133 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2135 #ifdef TARGET_X86_64
2136 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2138 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2141 #define cpu_list x86_cpu_list
2143 /* MMU modes definitions */
2144 #define MMU_KSMAP_IDX 0
2145 #define MMU_USER_IDX 1
2146 #define MMU_KNOSMAP_IDX 2
2147 static inline int cpu_mmu_index(CPUX86State
*env
, bool ifetch
)
2149 return (env
->hflags
& HF_CPL_MASK
) == 3 ? MMU_USER_IDX
:
2150 (!(env
->hflags
& HF_SMAP_MASK
) || (env
->eflags
& AC_MASK
))
2151 ? MMU_KNOSMAP_IDX
: MMU_KSMAP_IDX
;
2154 static inline int cpu_mmu_index_kernel(CPUX86State
*env
)
2156 return !(env
->hflags
& HF_SMAP_MASK
) ? MMU_KNOSMAP_IDX
:
2157 ((env
->hflags
& HF_CPL_MASK
) < 3 && (env
->eflags
& AC_MASK
))
2158 ? MMU_KNOSMAP_IDX
: MMU_KSMAP_IDX
;
2161 #define CC_DST (env->cc_dst)
2162 #define CC_SRC (env->cc_src)
2163 #define CC_SRC2 (env->cc_src2)
2164 #define CC_OP (env->cc_op)
2166 #include "exec/cpu-all.h"
2169 #if !defined(CONFIG_USER_ONLY)
2170 #include "hw/i386/apic.h"
2173 static inline void cpu_get_tb_cpu_state(CPUX86State
*env
, target_ulong
*pc
,
2174 target_ulong
*cs_base
, uint32_t *flags
)
2176 *cs_base
= env
->segs
[R_CS
].base
;
2177 *pc
= *cs_base
+ env
->eip
;
2178 *flags
= env
->hflags
|
2179 (env
->eflags
& (IOPL_MASK
| TF_MASK
| RF_MASK
| VM_MASK
| AC_MASK
));
2182 void do_cpu_init(X86CPU
*cpu
);
2183 void do_cpu_sipi(X86CPU
*cpu
);
2185 #define MCE_INJECT_BROADCAST 1
2186 #define MCE_INJECT_UNCOND_AO 2
2188 void cpu_x86_inject_mce(Monitor
*mon
, X86CPU
*cpu
, int bank
,
2189 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
2190 uint64_t misc
, int flags
);
2192 uint32_t cpu_cc_compute_all(CPUX86State
*env1
, int op
);
2194 static inline uint32_t cpu_compute_eflags(CPUX86State
*env
)
2196 uint32_t eflags
= env
->eflags
;
2197 if (tcg_enabled()) {
2198 eflags
|= cpu_cc_compute_all(env
, CC_OP
) | (env
->df
& DF_MASK
);
2203 static inline MemTxAttrs
cpu_get_mem_attrs(CPUX86State
*env
)
2205 return ((MemTxAttrs
) { .secure
= (env
->hflags
& HF_SMM_MASK
) != 0 });
2208 static inline int32_t x86_get_a20_mask(CPUX86State
*env
)
2210 if (env
->hflags
& HF_SMM_MASK
) {
2213 return env
->a20_mask
;
2217 static inline bool cpu_has_vmx(CPUX86State
*env
)
2219 return env
->features
[FEAT_1_ECX
] & CPUID_EXT_VMX
;
2222 static inline bool cpu_has_svm(CPUX86State
*env
)
2224 return env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
;
2228 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2229 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2230 * VMX operation. This is because CR4.VMXE is one of the bits set
2231 * in MSR_IA32_VMX_CR4_FIXED1.
2233 * There is one exception to above statement when vCPU enters SMM mode.
2234 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2235 * may also reset CR4.VMXE during execution in SMM mode.
2236 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2237 * and CR4.VMXE is restored to it's original value of being set.
2239 * Therefore, when vCPU is not in SMM mode, we can infer whether
2240 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2243 static inline bool cpu_vmx_maybe_enabled(CPUX86State
*env
)
2245 return cpu_has_vmx(env
) &&
2246 ((env
->cr
[4] & CR4_VMXE_MASK
) || (env
->hflags
& HF_SMM_MASK
));
2250 int get_pg_mode(CPUX86State
*env
);
2253 void update_fp_status(CPUX86State
*env
);
2254 void update_mxcsr_status(CPUX86State
*env
);
2255 void update_mxcsr_from_sse_status(CPUX86State
*env
);
2257 static inline void cpu_set_mxcsr(CPUX86State
*env
, uint32_t mxcsr
)
2260 if (tcg_enabled()) {
2261 update_mxcsr_status(env
);
2265 static inline void cpu_set_fpuc(CPUX86State
*env
, uint16_t fpuc
)
2268 if (tcg_enabled()) {
2269 update_fp_status(env
);
2274 void helper_lock_init(void);
2277 #ifdef CONFIG_USER_ONLY
2279 cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
2280 uint64_t param
, uintptr_t retaddr
)
2283 cpu_svm_has_intercept(CPUX86State
*env
, uint32_t type
)
2286 void cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
2287 uint64_t param
, uintptr_t retaddr
);
2288 bool cpu_svm_has_intercept(CPUX86State
*env
, uint32_t type
);
2292 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
);
2293 void apic_handle_tpr_access_report(DeviceState
*d
, target_ulong ip
,
2296 /* Special values for X86CPUVersion: */
2298 /* Resolve to latest CPU version */
2299 #define CPU_VERSION_LATEST -1
2302 * Resolve to version defined by current machine type.
2303 * See x86_cpu_set_default_version()
2305 #define CPU_VERSION_AUTO -2
2307 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2308 #define CPU_VERSION_LEGACY 0
2310 typedef int X86CPUVersion
;
2313 * Set default CPU model version for CPU models having
2314 * version == CPU_VERSION_AUTO.
2316 void x86_cpu_set_default_version(X86CPUVersion version
);
2318 #define APIC_DEFAULT_ADDRESS 0xfee00000
2319 #define APIC_SPACE_SIZE 0x100000
2322 void x86_cpu_dump_local_apic_state(CPUState
*cs
, int flags
);
2325 bool cpu_is_bsp(X86CPU
*cpu
);
2327 void x86_cpu_xrstor_all_areas(X86CPU
*cpu
, const void *buf
, uint32_t buflen
);
2328 void x86_cpu_xsave_all_areas(X86CPU
*cpu
, void *buf
, uint32_t buflen
);
2329 void x86_update_hflags(CPUX86State
* env
);
2331 static inline bool hyperv_feat_enabled(X86CPU
*cpu
, int feat
)
2333 return !!(cpu
->hyperv_features
& BIT(feat
));
2336 static inline uint64_t cr4_reserved_bits(CPUX86State
*env
)
2338 uint64_t reserved_bits
= CR4_RESERVED_MASK
;
2339 if (!env
->features
[FEAT_XSAVE
]) {
2340 reserved_bits
|= CR4_OSXSAVE_MASK
;
2342 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SMEP
)) {
2343 reserved_bits
|= CR4_SMEP_MASK
;
2345 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SMAP
)) {
2346 reserved_bits
|= CR4_SMAP_MASK
;
2348 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
)) {
2349 reserved_bits
|= CR4_FSGSBASE_MASK
;
2351 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_PKU
)) {
2352 reserved_bits
|= CR4_PKE_MASK
;
2354 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
)) {
2355 reserved_bits
|= CR4_LA57_MASK
;
2357 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_UMIP
)) {
2358 reserved_bits
|= CR4_UMIP_MASK
;
2360 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_PKS
)) {
2361 reserved_bits
|= CR4_PKS_MASK
;
2363 return reserved_bits
;
2366 static inline bool ctl_has_irq(CPUX86State
*env
)
2371 int_prio
= (env
->int_ctl
& V_INTR_PRIO_MASK
) >> V_INTR_PRIO_SHIFT
;
2372 tpr
= env
->int_ctl
& V_TPR_MASK
;
2374 if (env
->int_ctl
& V_IGN_TPR_MASK
) {
2375 return (env
->int_ctl
& V_IRQ_MASK
);
2378 return (env
->int_ctl
& V_IRQ_MASK
) && (int_prio
>= tpr
);
2381 hwaddr
get_hphys(CPUState
*cs
, hwaddr gphys
, MMUAccessType access_type
,
2383 #if defined(TARGET_X86_64) && \
2384 defined(CONFIG_USER_ONLY) && \
2385 defined(CONFIG_LINUX)
2386 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2389 #endif /* I386_CPU_H */