hw/loongarch/loongson3.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * QEMU loongson 3a5000 develop board emulation
   4  *
   5  * Copyright (c) 2021 Loongson Technology Corporation Limited
   6  */
   7 #include "qemu/osdep.h"
   8 #include "qemu/units.h"
   9 #include "qemu/datadir.h"
  10 #include "qapi/error.h"
  11 #include "hw/boards.h"
  12 #include "hw/char/serial.h"
  13 #include "sysemu/sysemu.h"
  14 #include "sysemu/qtest.h"
  15 #include "sysemu/runstate.h"
  16 #include "sysemu/reset.h"
  17 #include "sysemu/rtc.h"
  18 #include "hw/loongarch/virt.h"
  19 #include "exec/address-spaces.h"
  20 #include "hw/irq.h"
  21 #include "net/net.h"
  22 #include "hw/loader.h"
  23 #include "elf.h"
  24 #include "hw/intc/loongarch_ipi.h"
  25 #include "hw/intc/loongarch_extioi.h"
  26 #include "hw/intc/loongarch_pch_pic.h"
  27 #include "hw/intc/loongarch_pch_msi.h"
  28 #include "hw/pci-host/ls7a.h"
  29 #include "hw/pci-host/gpex.h"
  30 #include "hw/misc/unimp.h"
  31
  32 #include "target/loongarch/cpu.h"
  33
  34 #define PM_BASE 0x10080000
  35 #define PM_SIZE 0x100
  36 #define PM_CTRL 0x10
  37
  38 /*
  39  * This is a placeholder for missing ACPI,
  40  * and will eventually be replaced.
  41  */
  42 static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size)
  43 {
  44     return 0;
  45 }
  46
  47 static void loongarch_virt_pm_write(void *opaque, hwaddr addr,
  48                                uint64_t val, unsigned size)
  49 {
  50     if (addr != PM_CTRL) {
  51         return;
  52     }
  53
  54     switch (val) {
  55     case 0x00:
  56         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  57         return;
  58     case 0xff:
  59         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  60         return;
  61     default:
  62         return;
  63     }
  64 }
  65
  66 static const MemoryRegionOps loongarch_virt_pm_ops = {
  67     .read  = loongarch_virt_pm_read,
  68     .write = loongarch_virt_pm_write,
  69     .endianness = DEVICE_NATIVE_ENDIAN,
  70     .valid = {
  71         .min_access_size = 1,
  72         .max_access_size = 1
  73     }
  74 };
  75
  76 static struct _loaderparams {
  77     uint64_t ram_size;
  78     const char *kernel_filename;
  79 } loaderparams;
  80
  81 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
  82 {
  83     return addr & 0x1fffffffll;
  84 }
  85
  86 static int64_t load_kernel_info(void)
  87 {
  88     uint64_t kernel_entry, kernel_low, kernel_high;
  89     ssize_t kernel_size;
  90
  91     kernel_size = load_elf(loaderparams.kernel_filename, NULL,
  92                            cpu_loongarch_virt_to_phys, NULL,
  93                            &kernel_entry, &kernel_low,
  94                            &kernel_high, NULL, 0,
  95                            EM_LOONGARCH, 1, 0);
  96
  97     if (kernel_size < 0) {
  98         error_report("could not load kernel '%s': %s",
  99                      loaderparams.kernel_filename,
 100                      load_elf_strerror(kernel_size));
 101         exit(1);
 102     }
 103     return kernel_entry;
 104 }
 105
 106 static void loongarch_devices_init(DeviceState *pch_pic)
 107 {
 108     DeviceState *gpex_dev;
 109     SysBusDevice *d;
 110     PCIBus *pci_bus;
 111     MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
 112     MemoryRegion *mmio_alias, *mmio_reg, *pm_mem;
 113     int i;
 114
 115     gpex_dev = qdev_new(TYPE_GPEX_HOST);
 116     d = SYS_BUS_DEVICE(gpex_dev);
 117     sysbus_realize_and_unref(d, &error_fatal);
 118     pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
 119
 120     /* Map only part size_ecam bytes of ECAM space */
 121     ecam_alias = g_new0(MemoryRegion, 1);
 122     ecam_reg = sysbus_mmio_get_region(d, 0);
 123     memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
 124                              ecam_reg, 0, LS_PCIECFG_SIZE);
 125     memory_region_add_subregion(get_system_memory(), LS_PCIECFG_BASE,
 126                                 ecam_alias);
 127
 128     /* Map PCI mem space */
 129     mmio_alias = g_new0(MemoryRegion, 1);
 130     mmio_reg = sysbus_mmio_get_region(d, 1);
 131     memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
 132                              mmio_reg, LS7A_PCI_MEM_BASE, LS7A_PCI_MEM_SIZE);
 133     memory_region_add_subregion(get_system_memory(), LS7A_PCI_MEM_BASE,
 134                                 mmio_alias);
 135
 136     /* Map PCI IO port space. */
 137     pio_alias = g_new0(MemoryRegion, 1);
 138     pio_reg = sysbus_mmio_get_region(d, 2);
 139     memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
 140                              LS7A_PCI_IO_OFFSET, LS7A_PCI_IO_SIZE);
 141     memory_region_add_subregion(get_system_memory(), LS7A_PCI_IO_BASE,
 142                                 pio_alias);
 143
 144     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 145         sysbus_connect_irq(d, i,
 146                            qdev_get_gpio_in(pch_pic, 16 + i));
 147         gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
 148     }
 149
 150     serial_mm_init(get_system_memory(), LS7A_UART_BASE, 0,
 151                    qdev_get_gpio_in(pch_pic,
 152                                     LS7A_UART_IRQ - PCH_PIC_IRQ_OFFSET),
 153                    115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 154
 155     /* Network init */
 156     for (i = 0; i < nb_nics; i++) {
 157         NICInfo *nd = &nd_table[i];
 158
 159         if (!nd->model) {
 160             nd->model = g_strdup("virtio");
 161         }
 162
 163         pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
 164     }
 165
 166     /* VGA setup */
 167     pci_vga_init(pci_bus);
 168
 169     /*
 170      * There are some invalid guest memory access.
 171      * Create some unimplemented devices to emulate this.
 172      */
 173     create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
 174     sysbus_create_simple("ls7a_rtc", LS7A_RTC_REG_BASE,
 175                          qdev_get_gpio_in(pch_pic,
 176                          LS7A_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
 177
 178     pm_mem = g_new(MemoryRegion, 1);
 179     memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
 180                           NULL, "loongarch_virt_pm", PM_SIZE);
 181     memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem);
 182 }
 183
 184 static void loongarch_irq_init(LoongArchMachineState *lams)
 185 {
 186     MachineState *ms = MACHINE(lams);
 187     DeviceState *pch_pic, *pch_msi, *cpudev;
 188     DeviceState *ipi, *extioi;
 189     SysBusDevice *d;
 190     LoongArchCPU *lacpu;
 191     CPULoongArchState *env;
 192     CPUState *cpu_state;
 193     int cpu, pin, i;
 194
 195     ipi = qdev_new(TYPE_LOONGARCH_IPI);
 196     sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
 197
 198     extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
 199     sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
 200
 201     /*
 202      * The connection of interrupts:
 203      *   +-----+    +---------+     +-------+
 204      *   | IPI |--> | CPUINTC | <-- | Timer |
 205      *   +-----+    +---------+     +-------+
 206      *                  ^
 207      *                  |
 208      *            +---------+
 209      *            | EIOINTC |
 210      *            +---------+
 211      *             ^       ^
 212      *             |       |
 213      *      +---------+ +---------+
 214      *      | PCH-PIC | | PCH-MSI |
 215      *      +---------+ +---------+
 216      *        ^      ^          ^
 217      *        |      |          |
 218      * +--------+ +---------+ +---------+
 219      * | UARTs  | | Devices | | Devices |
 220      * +--------+ +---------+ +---------+
 221      */
 222     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 223         cpu_state = qemu_get_cpu(cpu);
 224         cpudev = DEVICE(cpu_state);
 225         lacpu = LOONGARCH_CPU(cpu_state);
 226         env = &(lacpu->env);
 227
 228         /* connect ipi irq to cpu irq */
 229         qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
 230         /* IPI iocsr memory region */
 231         memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
 232                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
 233                                     cpu * 2));
 234         memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
 235                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
 236                                     cpu * 2 + 1));
 237         /* extioi iocsr memory region */
 238         memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
 239                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
 240                                 cpu));
 241     }
 242
 243     /*
 244      * connect ext irq to the cpu irq
 245      * cpu_pin[9:2] <= intc_pin[7:0]
 246      */
 247     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 248         cpudev = DEVICE(qemu_get_cpu(cpu));
 249         for (pin = 0; pin < LS3A_INTC_IP; pin++) {
 250             qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
 251                                   qdev_get_gpio_in(cpudev, pin + 2));
 252         }
 253     }
 254
 255     pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
 256     d = SYS_BUS_DEVICE(pch_pic);
 257     sysbus_realize_and_unref(d, &error_fatal);
 258     memory_region_add_subregion(get_system_memory(), LS7A_IOAPIC_REG_BASE,
 259                             sysbus_mmio_get_region(d, 0));
 260     memory_region_add_subregion(get_system_memory(),
 261                             LS7A_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
 262                             sysbus_mmio_get_region(d, 1));
 263     memory_region_add_subregion(get_system_memory(),
 264                             LS7A_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
 265                             sysbus_mmio_get_region(d, 2));
 266
 267     /* Connect 64 pch_pic irqs to extioi */
 268     for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
 269         qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
 270     }
 271
 272     pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
 273     qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
 274     d = SYS_BUS_DEVICE(pch_msi);
 275     sysbus_realize_and_unref(d, &error_fatal);
 276     sysbus_mmio_map(d, 0, LS7A_PCH_MSI_ADDR_LOW);
 277     for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
 278         /* Connect 192 pch_msi irqs to extioi */
 279         qdev_connect_gpio_out(DEVICE(d), i,
 280                               qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
 281     }
 282
 283     loongarch_devices_init(pch_pic);
 284 }
 285
 286 static void reset_load_elf(void *opaque)
 287 {
 288     LoongArchCPU *cpu = opaque;
 289     CPULoongArchState *env = &cpu->env;
 290
 291     cpu_reset(CPU(cpu));
 292     if (env->load_elf) {
 293         cpu_set_pc(CPU(cpu), env->elf_address);
 294     }
 295 }
 296
 297 static void loongarch_init(MachineState *machine)
 298 {
 299     const char *cpu_model = machine->cpu_type;
 300     const char *kernel_filename = machine->kernel_filename;
 301     ram_addr_t offset = 0;
 302     ram_addr_t ram_size = machine->ram_size;
 303     uint64_t highram_size = 0;
 304     MemoryRegion *address_space_mem = get_system_memory();
 305     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
 306     LoongArchCPU *lacpu;
 307     int i;
 308     int64_t kernel_addr = 0;
 309
 310     if (!cpu_model) {
 311         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
 312     }
 313
 314     if (!strstr(cpu_model, "la464")) {
 315         error_report("LoongArch/TCG needs cpu type la464");
 316         exit(1);
 317     }
 318
 319     if (ram_size < 1 * GiB) {
 320         error_report("ram_size must be greater than 1G.");
 321         exit(1);
 322     }
 323
 324     /* Init CPUs */
 325     for (i = 0; i < machine->smp.cpus; i++) {
 326         cpu_create(machine->cpu_type);
 327     }
 328
 329     /* Add memory region */
 330     memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
 331                              machine->ram, 0, 256 * MiB);
 332     memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
 333     offset += 256 * MiB;
 334     highram_size = ram_size - 256 * MiB;
 335     memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
 336                              machine->ram, offset, highram_size);
 337     memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
 338     /* Add isa io region */
 339     memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
 340                              get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
 341     memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE,
 342                                 &lams->isa_io);
 343     if (kernel_filename) {
 344         loaderparams.ram_size = ram_size;
 345         loaderparams.kernel_filename = kernel_filename;
 346         kernel_addr = load_kernel_info();
 347         if (!machine->firmware) {
 348             for (i = 0; i < machine->smp.cpus; i++) {
 349                 lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
 350                 lacpu->env.load_elf = true;
 351                 lacpu->env.elf_address = kernel_addr;
 352                 qemu_register_reset(reset_load_elf, lacpu);
 353             }
 354         }
 355     }
 356     /* Initialize the IO interrupt subsystem */
 357     loongarch_irq_init(lams);
 358 }
 359
 360 static void loongarch_class_init(ObjectClass *oc, void *data)
 361 {
 362     MachineClass *mc = MACHINE_CLASS(oc);
 363
 364     mc->desc = "Loongson-3A5000 LS7A1000 machine";
 365     mc->init = loongarch_init;
 366     mc->default_ram_size = 1 * GiB;
 367     mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
 368     mc->default_ram_id = "loongarch.ram";
 369     mc->max_cpus = LOONGARCH_MAX_VCPUS;
 370     mc->is_default = 1;
 371     mc->default_kernel_irqchip_split = false;
 372     mc->block_default_type = IF_VIRTIO;
 373     mc->default_boot_order = "c";
 374     mc->no_cdrom = 1;
 375 }
 376
 377 static const TypeInfo loongarch_machine_types[] = {
 378     {
 379         .name           = TYPE_LOONGARCH_MACHINE,
 380         .parent         = TYPE_MACHINE,
 381         .instance_size  = sizeof(LoongArchMachineState),
 382         .class_init     = loongarch_class_init,
 383     }
 384 };
 385
 386 DEFINE_TYPES(loongarch_machine_types)