target/loongarch/cpu.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * QEMU LoongArch CPU
   4  *
   5  * Copyright (c) 2021 Loongson Technology Corporation Limited
   6  */
   7
   8 #ifndef LOONGARCH_CPU_H
   9 #define LOONGARCH_CPU_H
  10
  11 #include "exec/cpu-defs.h"
  12 #include "fpu/softfloat-types.h"
  13 #include "hw/registerfields.h"
  14 #include "qemu/timer.h"
  15
  16 #define TCG_GUEST_DEFAULT_MO (0)
  17
  18 #define FCSR0_M1    0x1f         /* FCSR1 mask, Enables */
  19 #define FCSR0_M2    0x1f1f0000   /* FCSR2 mask, Cause and Flags */
  20 #define FCSR0_M3    0x300        /* FCSR3 mask, Round Mode */
  21 #define FCSR0_RM    8            /* Round Mode bit num on fcsr0 */
  22
  23 FIELD(FCSR0, ENABLES, 0, 5)
  24 FIELD(FCSR0, RM, 8, 2)
  25 FIELD(FCSR0, FLAGS, 16, 5)
  26 FIELD(FCSR0, CAUSE, 24, 5)
  27
  28 #define GET_FP_CAUSE(REG)      FIELD_EX32(REG, FCSR0, CAUSE)
  29 #define SET_FP_CAUSE(REG, V)   FIELD_DP32(REG, FCSR0, CAUSE, V)
  30 #define GET_FP_ENABLES(REG)    FIELD_EX32(REG, FCSR0, ENABLES)
  31 #define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
  32 #define GET_FP_FLAGS(REG)      FIELD_EX32(REG, FCSR0, FLAGS)
  33 #define SET_FP_FLAGS(REG, V)   FIELD_DP32(REG, FCSR0, FLAGS, V)
  34 #define UPDATE_FP_FLAGS(REG, V) \
  35     do { \
  36         (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
  37     } while (0)
  38
  39 #define FP_INEXACT        1
  40 #define FP_UNDERFLOW      2
  41 #define FP_OVERFLOW       4
  42 #define FP_DIV0           8
  43 #define FP_INVALID        16
  44
  45 #define  EXCCODE_EXTERNAL_INT   64   /* plus external interrupt number */
  46 #define  EXCCODE_INT                 0
  47 #define  EXCCODE_PIL                 1
  48 #define  EXCCODE_PIS                 2
  49 #define  EXCCODE_PIF                 3
  50 #define  EXCCODE_PME                 4
  51 #define  EXCCODE_PNR                 5
  52 #define  EXCCODE_PNX                 6
  53 #define  EXCCODE_PPI                 7
  54 #define  EXCCODE_ADEF                8 /* Different exception subcode */
  55 #define  EXCCODE_ADEM                8
  56 #define  EXCCODE_ALE                 9
  57 #define  EXCCODE_BCE                 10
  58 #define  EXCCODE_SYS                 11
  59 #define  EXCCODE_BRK                 12
  60 #define  EXCCODE_INE                 13
  61 #define  EXCCODE_IPE                 14
  62 #define  EXCCODE_FPD                 15
  63 #define  EXCCODE_SXD                 16
  64 #define  EXCCODE_ASXD                17
  65 #define  EXCCODE_FPE                 18 /* Different exception subcode */
  66 #define  EXCCODE_VFPE                18
  67 #define  EXCCODE_WPEF                19 /* Different exception subcode */
  68 #define  EXCCODE_WPEM                19
  69 #define  EXCCODE_BTD                 20
  70 #define  EXCCODE_BTE                 21
  71 #define  EXCCODE_DBP                 26 /* Reserved subcode used for debug */
  72
  73 /* cpucfg[0] bits */
  74 FIELD(CPUCFG0, PRID, 0, 32)
  75
  76 /* cpucfg[1] bits */
  77 FIELD(CPUCFG1, ARCH, 0, 2)
  78 FIELD(CPUCFG1, PGMMU, 2, 1)
  79 FIELD(CPUCFG1, IOCSR, 3, 1)
  80 FIELD(CPUCFG1, PALEN, 4, 8)
  81 FIELD(CPUCFG1, VALEN, 12, 8)
  82 FIELD(CPUCFG1, UAL, 20, 1)
  83 FIELD(CPUCFG1, RI, 21, 1)
  84 FIELD(CPUCFG1, EP, 22, 1)
  85 FIELD(CPUCFG1, RPLV, 23, 1)
  86 FIELD(CPUCFG1, HP, 24, 1)
  87 FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
  88 FIELD(CPUCFG1, MSG_INT, 26, 1)
  89
  90 /* cpucfg[2] bits */
  91 FIELD(CPUCFG2, FP, 0, 1)
  92 FIELD(CPUCFG2, FP_SP, 1, 1)
  93 FIELD(CPUCFG2, FP_DP, 2, 1)
  94 FIELD(CPUCFG2, FP_VER, 3, 3)
  95 FIELD(CPUCFG2, LSX, 6, 1)
  96 FIELD(CPUCFG2, LASX, 7, 1)
  97 FIELD(CPUCFG2, COMPLEX, 8, 1)
  98 FIELD(CPUCFG2, CRYPTO, 9, 1)
  99 FIELD(CPUCFG2, LVZ, 10, 1)
 100 FIELD(CPUCFG2, LVZ_VER, 11, 3)
 101 FIELD(CPUCFG2, LLFTP, 14, 1)
 102 FIELD(CPUCFG2, LLFTP_VER, 15, 3)
 103 FIELD(CPUCFG2, LBT_X86, 18, 1)
 104 FIELD(CPUCFG2, LBT_ARM, 19, 1)
 105 FIELD(CPUCFG2, LBT_MIPS, 20, 1)
 106 FIELD(CPUCFG2, LSPW, 21, 1)
 107 FIELD(CPUCFG2, LAM, 22, 1)
 108
 109 /* cpucfg[3] bits */
 110 FIELD(CPUCFG3, CCDMA, 0, 1)
 111 FIELD(CPUCFG3, SFB, 1, 1)
 112 FIELD(CPUCFG3, UCACC, 2, 1)
 113 FIELD(CPUCFG3, LLEXC, 3, 1)
 114 FIELD(CPUCFG3, SCDLY, 4, 1)
 115 FIELD(CPUCFG3, LLDBAR, 5, 1)
 116 FIELD(CPUCFG3, ITLBHMC, 6, 1)
 117 FIELD(CPUCFG3, ICHMC, 7, 1)
 118 FIELD(CPUCFG3, SPW_LVL, 8, 3)
 119 FIELD(CPUCFG3, SPW_HP_HF, 11, 1)
 120 FIELD(CPUCFG3, RVA, 12, 1)
 121 FIELD(CPUCFG3, RVAMAX, 13, 4)
 122
 123 /* cpucfg[4] bits */
 124 FIELD(CPUCFG4, CC_FREQ, 0, 32)
 125
 126 /* cpucfg[5] bits */
 127 FIELD(CPUCFG5, CC_MUL, 0, 16)
 128 FIELD(CPUCFG5, CC_DIV, 16, 16)
 129
 130 /* cpucfg[6] bits */
 131 FIELD(CPUCFG6, PMP, 0, 1)
 132 FIELD(CPUCFG6, PMVER, 1, 3)
 133 FIELD(CPUCFG6, PMNUM, 4, 4)
 134 FIELD(CPUCFG6, PMBITS, 8, 6)
 135 FIELD(CPUCFG6, UPM, 14, 1)
 136
 137 /* cpucfg[16] bits */
 138 FIELD(CPUCFG16, L1_IUPRE, 0, 1)
 139 FIELD(CPUCFG16, L1_IUUNIFY, 1, 1)
 140 FIELD(CPUCFG16, L1_DPRE, 2, 1)
 141 FIELD(CPUCFG16, L2_IUPRE, 3, 1)
 142 FIELD(CPUCFG16, L2_IUUNIFY, 4, 1)
 143 FIELD(CPUCFG16, L2_IUPRIV, 5, 1)
 144 FIELD(CPUCFG16, L2_IUINCL, 6, 1)
 145 FIELD(CPUCFG16, L2_DPRE, 7, 1)
 146 FIELD(CPUCFG16, L2_DPRIV, 8, 1)
 147 FIELD(CPUCFG16, L2_DINCL, 9, 1)
 148 FIELD(CPUCFG16, L3_IUPRE, 10, 1)
 149 FIELD(CPUCFG16, L3_IUUNIFY, 11, 1)
 150 FIELD(CPUCFG16, L3_IUPRIV, 12, 1)
 151 FIELD(CPUCFG16, L3_IUINCL, 13, 1)
 152 FIELD(CPUCFG16, L3_DPRE, 14, 1)
 153 FIELD(CPUCFG16, L3_DPRIV, 15, 1)
 154 FIELD(CPUCFG16, L3_DINCL, 16, 1)
 155
 156 /* cpucfg[17] bits */
 157 FIELD(CPUCFG17, L1IU_WAYS, 0, 16)
 158 FIELD(CPUCFG17, L1IU_SETS, 16, 8)
 159 FIELD(CPUCFG17, L1IU_SIZE, 24, 7)
 160
 161 /* cpucfg[18] bits */
 162 FIELD(CPUCFG18, L1D_WAYS, 0, 16)
 163 FIELD(CPUCFG18, L1D_SETS, 16, 8)
 164 FIELD(CPUCFG18, L1D_SIZE, 24, 7)
 165
 166 /* cpucfg[19] bits */
 167 FIELD(CPUCFG19, L2IU_WAYS, 0, 16)
 168 FIELD(CPUCFG19, L2IU_SETS, 16, 8)
 169 FIELD(CPUCFG19, L2IU_SIZE, 24, 7)
 170
 171 /* cpucfg[20] bits */
 172 FIELD(CPUCFG20, L3IU_WAYS, 0, 16)
 173 FIELD(CPUCFG20, L3IU_SETS, 16, 8)
 174 FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
 175
 176 /*CSR_CRMD */
 177 FIELD(CSR_CRMD, PLV, 0, 2)
 178 FIELD(CSR_CRMD, IE, 2, 1)
 179 FIELD(CSR_CRMD, DA, 3, 1)
 180 FIELD(CSR_CRMD, PG, 4, 1)
 181 FIELD(CSR_CRMD, DATF, 5, 2)
 182 FIELD(CSR_CRMD, DATM, 7, 2)
 183 FIELD(CSR_CRMD, WE, 9, 1)
 184
 185 extern const char * const regnames[32];
 186 extern const char * const fregnames[32];
 187
 188 #define N_IRQS      13
 189 #define IRQ_TIMER   11
 190 #define IRQ_IPI     12
 191
 192 #define LOONGARCH_STLB         2048 /* 2048 STLB */
 193 #define LOONGARCH_MTLB         64   /* 64 MTLB */
 194 #define LOONGARCH_TLB_MAX      (LOONGARCH_STLB + LOONGARCH_MTLB)
 195
 196 /*
 197  * define the ASID PS E VPPN field of TLB
 198  */
 199 FIELD(TLB_MISC, E, 0, 1)
 200 FIELD(TLB_MISC, ASID, 1, 10)
 201 FIELD(TLB_MISC, VPPN, 13, 35)
 202 FIELD(TLB_MISC, PS, 48, 6)
 203
 204 struct LoongArchTLB {
 205     uint64_t tlb_misc;
 206     /* Fields corresponding to CSR_TLBELO0/1 */
 207     uint64_t tlb_entry0;
 208     uint64_t tlb_entry1;
 209 };
 210 typedef struct LoongArchTLB LoongArchTLB;
 211
 212 typedef struct CPUArchState {
 213     uint64_t gpr[32];
 214     uint64_t pc;
 215
 216     uint64_t fpr[32];
 217     float_status fp_status;
 218     bool cf[8];
 219
 220     uint32_t fcsr0;
 221     uint32_t fcsr0_mask;
 222
 223     uint32_t cpucfg[21];
 224
 225     uint64_t lladdr; /* LL virtual address compared against SC */
 226     uint64_t llval;
 227
 228     uint64_t badaddr;
 229
 230     /* LoongArch CSRs */
 231     uint64_t CSR_CRMD;
 232     uint64_t CSR_PRMD;
 233     uint64_t CSR_EUEN;
 234     uint64_t CSR_MISC;
 235     uint64_t CSR_ECFG;
 236     uint64_t CSR_ESTAT;
 237     uint64_t CSR_ERA;
 238     uint64_t CSR_BADV;
 239     uint64_t CSR_BADI;
 240     uint64_t CSR_EENTRY;
 241     uint64_t CSR_TLBIDX;
 242     uint64_t CSR_TLBEHI;
 243     uint64_t CSR_TLBELO0;
 244     uint64_t CSR_TLBELO1;
 245     uint64_t CSR_ASID;
 246     uint64_t CSR_PGDL;
 247     uint64_t CSR_PGDH;
 248     uint64_t CSR_PGD;
 249     uint64_t CSR_PWCL;
 250     uint64_t CSR_PWCH;
 251     uint64_t CSR_STLBPS;
 252     uint64_t CSR_RVACFG;
 253     uint64_t CSR_PRCFG1;
 254     uint64_t CSR_PRCFG2;
 255     uint64_t CSR_PRCFG3;
 256     uint64_t CSR_SAVE[16];
 257     uint64_t CSR_TID;
 258     uint64_t CSR_TCFG;
 259     uint64_t CSR_TVAL;
 260     uint64_t CSR_CNTC;
 261     uint64_t CSR_TICLR;
 262     uint64_t CSR_LLBCTL;
 263     uint64_t CSR_IMPCTL1;
 264     uint64_t CSR_IMPCTL2;
 265     uint64_t CSR_TLBRENTRY;
 266     uint64_t CSR_TLBRBADV;
 267     uint64_t CSR_TLBRERA;
 268     uint64_t CSR_TLBRSAVE;
 269     uint64_t CSR_TLBRELO0;
 270     uint64_t CSR_TLBRELO1;
 271     uint64_t CSR_TLBREHI;
 272     uint64_t CSR_TLBRPRMD;
 273     uint64_t CSR_MERRCTL;
 274     uint64_t CSR_MERRINFO1;
 275     uint64_t CSR_MERRINFO2;
 276     uint64_t CSR_MERRENTRY;
 277     uint64_t CSR_MERRERA;
 278     uint64_t CSR_MERRSAVE;
 279     uint64_t CSR_CTAG;
 280     uint64_t CSR_DMW[4];
 281     uint64_t CSR_DBG;
 282     uint64_t CSR_DERA;
 283     uint64_t CSR_DSAVE;
 284
 285     LoongArchTLB  tlb[LOONGARCH_TLB_MAX];
 286 } CPULoongArchState;
 287
 288 /**
 289  * LoongArchCPU:
 290  * @env: #CPULoongArchState
 291  *
 292  * A LoongArch CPU.
 293  */
 294 struct ArchCPU {
 295     /*< private >*/
 296     CPUState parent_obj;
 297     /*< public >*/
 298
 299     CPUNegativeOffsetState neg;
 300     CPULoongArchState env;
 301     QEMUTimer timer;
 302 };
 303
 304 #define TYPE_LOONGARCH_CPU "loongarch-cpu"
 305
 306 OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
 307                         LOONGARCH_CPU)
 308
 309 /**
 310  * LoongArchCPUClass:
 311  * @parent_realize: The parent class' realize handler.
 312  * @parent_reset: The parent class' reset handler.
 313  *
 314  * A LoongArch CPU model.
 315  */
 316 struct LoongArchCPUClass {
 317     /*< private >*/
 318     CPUClass parent_class;
 319     /*< public >*/
 320
 321     DeviceRealize parent_realize;
 322     DeviceReset parent_reset;
 323 };
 324
 325 /*
 326  * LoongArch CPUs has 4 privilege levels.
 327  * 0 for kernel mode, 3 for user mode.
 328  * Define an extra index for DA(direct addressing) mode.
 329  */
 330 #define MMU_KERNEL_IDX   0
 331 #define MMU_USER_IDX     3
 332 #define MMU_DA_IDX       4
 333
 334 static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
 335 {
 336     uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
 337
 338     if (!pg) {
 339         return MMU_DA_IDX;
 340     }
 341     return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
 342 }
 343
 344 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
 345                                         target_ulong *pc,
 346                                         target_ulong *cs_base,
 347                                         uint32_t *flags)
 348 {
 349     *pc = env->pc;
 350     *cs_base = 0;
 351     *flags = cpu_mmu_index(env, false);
 352 }
 353
 354 void loongarch_cpu_list(void);
 355
 356 #define cpu_list loongarch_cpu_list
 357
 358 #include "exec/cpu-all.h"
 359
 360 #define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
 361 #define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
 362 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
 363
 364 #endif /* LOONGARCH_CPU_H */