target-mips/kvm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012-2014 Imagination Technologies Ltd.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10 */
  11
  12 #include "qemu/osdep.h"
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/kvm.h"
  23 #include "cpu.h"
  24 #include "sysemu/cpus.h"
  25 #include "kvm_mips.h"
  26 #include "exec/memattrs.h"
  27
  28 #define DEBUG_KVM 0
  29
  30 #define DPRINTF(fmt, ...) \
  31     do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
  32
  33 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  34     KVM_CAP_LAST_INFO
  35 };
  36
  37 static void kvm_mips_update_state(void *opaque, int running, RunState state);
  38
  39 unsigned long kvm_arch_vcpu_id(CPUState *cs)
  40 {
  41     return cs->cpu_index;
  42 }
  43
  44 int kvm_arch_init(MachineState *ms, KVMState *s)
  45 {
  46     /* MIPS has 128 signals */
  47     kvm_set_sigmask_len(s, 16);
  48
  49     DPRINTF("%s\n", __func__);
  50     return 0;
  51 }
  52
  53 int kvm_arch_init_vcpu(CPUState *cs)
  54 {
  55     int ret = 0;
  56
  57     qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
  58
  59     DPRINTF("%s\n", __func__);
  60     return ret;
  61 }
  62
  63 void kvm_mips_reset_vcpu(MIPSCPU *cpu)
  64 {
  65     CPUMIPSState *env = &cpu->env;
  66
  67     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  68         fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
  69         env->CP0_Config1 &= ~(1 << CP0C1_FP);
  70     }
  71
  72     DPRINTF("%s\n", __func__);
  73 }
  74
  75 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  76 {
  77     DPRINTF("%s\n", __func__);
  78     return 0;
  79 }
  80
  81 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  82 {
  83     DPRINTF("%s\n", __func__);
  84     return 0;
  85 }
  86
  87 static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
  88 {
  89     CPUMIPSState *env = &cpu->env;
  90
  91     DPRINTF("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
  92     return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
  93 }
  94
  95
  96 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  97 {
  98     MIPSCPU *cpu = MIPS_CPU(cs);
  99     int r;
 100     struct kvm_mips_interrupt intr;
 101
 102     qemu_mutex_lock_iothread();
 103
 104     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 105             cpu_mips_io_interrupts_pending(cpu)) {
 106         intr.cpu = -1;
 107         intr.irq = 2;
 108         r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 109         if (r < 0) {
 110             error_report("%s: cpu %d: failed to inject IRQ %x",
 111                          __func__, cs->cpu_index, intr.irq);
 112         }
 113     }
 114
 115     qemu_mutex_unlock_iothread();
 116 }
 117
 118 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 119 {
 120     DPRINTF("%s\n", __func__);
 121     return MEMTXATTRS_UNSPECIFIED;
 122 }
 123
 124 int kvm_arch_process_async_events(CPUState *cs)
 125 {
 126     return cs->halted;
 127 }
 128
 129 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 130 {
 131     int ret;
 132
 133     DPRINTF("%s\n", __func__);
 134     switch (run->exit_reason) {
 135     default:
 136         error_report("%s: unknown exit reason %d",
 137                      __func__, run->exit_reason);
 138         ret = -1;
 139         break;
 140     }
 141
 142     return ret;
 143 }
 144
 145 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 146 {
 147     DPRINTF("%s\n", __func__);
 148     return true;
 149 }
 150
 151 int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
 152 {
 153     DPRINTF("%s\n", __func__);
 154     return 1;
 155 }
 156
 157 int kvm_arch_on_sigbus(int code, void *addr)
 158 {
 159     DPRINTF("%s\n", __func__);
 160     return 1;
 161 }
 162
 163 void kvm_arch_init_irq_routing(KVMState *s)
 164 {
 165 }
 166
 167 int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
 168 {
 169     CPUState *cs = CPU(cpu);
 170     struct kvm_mips_interrupt intr;
 171
 172     if (!kvm_enabled()) {
 173         return 0;
 174     }
 175
 176     intr.cpu = -1;
 177
 178     if (level) {
 179         intr.irq = irq;
 180     } else {
 181         intr.irq = -irq;
 182     }
 183
 184     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 185
 186     return 0;
 187 }
 188
 189 int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
 190 {
 191     CPUState *cs = current_cpu;
 192     CPUState *dest_cs = CPU(cpu);
 193     struct kvm_mips_interrupt intr;
 194
 195     if (!kvm_enabled()) {
 196         return 0;
 197     }
 198
 199     intr.cpu = dest_cs->cpu_index;
 200
 201     if (level) {
 202         intr.irq = irq;
 203     } else {
 204         intr.irq = -irq;
 205     }
 206
 207     DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
 208
 209     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 210
 211     return 0;
 212 }
 213
 214 #define MIPS_CP0_32(_R, _S)                                     \
 215     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
 216
 217 #define MIPS_CP0_64(_R, _S)                                     \
 218     (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
 219
 220 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
 221 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
 222 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
 223 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
 224 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
 225 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
 226 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
 227 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
 228 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
 229 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
 230 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
 231 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
 232 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
 233 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 234
 235 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
 236                                        int32_t *addr)
 237 {
 238     struct kvm_one_reg cp0reg = {
 239         .id = reg_id,
 240         .addr = (uintptr_t)addr
 241     };
 242
 243     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 244 }
 245
 246 static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
 247                                          target_ulong *addr)
 248 {
 249     uint64_t val64 = *addr;
 250     struct kvm_one_reg cp0reg = {
 251         .id = reg_id,
 252         .addr = (uintptr_t)&val64
 253     };
 254
 255     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 256 }
 257
 258 static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
 259                                          uint64_t *addr)
 260 {
 261     struct kvm_one_reg cp0reg = {
 262         .id = reg_id,
 263         .addr = (uintptr_t)addr
 264     };
 265
 266     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 267 }
 268
 269 static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
 270                                        int32_t *addr)
 271 {
 272     struct kvm_one_reg cp0reg = {
 273         .id = reg_id,
 274         .addr = (uintptr_t)addr
 275     };
 276
 277     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 278 }
 279
 280 static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64_t reg_id,
 281                                          target_ulong *addr)
 282 {
 283     int ret;
 284     uint64_t val64 = 0;
 285     struct kvm_one_reg cp0reg = {
 286         .id = reg_id,
 287         .addr = (uintptr_t)&val64
 288     };
 289
 290     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 291     if (ret >= 0) {
 292         *addr = val64;
 293     }
 294     return ret;
 295 }
 296
 297 static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64_t reg_id,
 298                                          uint64_t *addr)
 299 {
 300     struct kvm_one_reg cp0reg = {
 301         .id = reg_id,
 302         .addr = (uintptr_t)addr
 303     };
 304
 305     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 306 }
 307
 308 /*
 309  * We freeze the KVM timer when either the VM clock is stopped or the state is
 310  * saved (the state is dirty).
 311  */
 312
 313 /*
 314  * Save the state of the KVM timer when VM clock is stopped or state is synced
 315  * to QEMU.
 316  */
 317 static int kvm_mips_save_count(CPUState *cs)
 318 {
 319     MIPSCPU *cpu = MIPS_CPU(cs);
 320     CPUMIPSState *env = &cpu->env;
 321     uint64_t count_ctl;
 322     int err, ret = 0;
 323
 324     /* freeze KVM timer */
 325     err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 326     if (err < 0) {
 327         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
 328         ret = err;
 329     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 330         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 331         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 332         if (err < 0) {
 333             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 334             ret = err;
 335         }
 336     }
 337
 338     /* read CP0_Cause */
 339     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 340     if (err < 0) {
 341         DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
 342         ret = err;
 343     }
 344
 345     /* read CP0_Count */
 346     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 347     if (err < 0) {
 348         DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
 349         ret = err;
 350     }
 351
 352     return ret;
 353 }
 354
 355 /*
 356  * Restore the state of the KVM timer when VM clock is restarted or state is
 357  * synced to KVM.
 358  */
 359 static int kvm_mips_restore_count(CPUState *cs)
 360 {
 361     MIPSCPU *cpu = MIPS_CPU(cs);
 362     CPUMIPSState *env = &cpu->env;
 363     uint64_t count_ctl;
 364     int err_dc, err, ret = 0;
 365
 366     /* check the timer is frozen */
 367     err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 368     if (err_dc < 0) {
 369         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
 370         ret = err_dc;
 371     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 372         /* freeze timer (sets COUNT_RESUME for us) */
 373         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 374         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 375         if (err < 0) {
 376             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 377             ret = err;
 378         }
 379     }
 380
 381     /* load CP0_Cause */
 382     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 383     if (err < 0) {
 384         DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
 385         ret = err;
 386     }
 387
 388     /* load CP0_Count */
 389     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 390     if (err < 0) {
 391         DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
 392         ret = err;
 393     }
 394
 395     /* resume KVM timer */
 396     if (err_dc >= 0) {
 397         count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
 398         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 399         if (err < 0) {
 400             DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
 401             ret = err;
 402         }
 403     }
 404
 405     return ret;
 406 }
 407
 408 /*
 409  * Handle the VM clock being started or stopped
 410  */
 411 static void kvm_mips_update_state(void *opaque, int running, RunState state)
 412 {
 413     CPUState *cs = opaque;
 414     int ret;
 415     uint64_t count_resume;
 416
 417     /*
 418      * If state is already dirty (synced to QEMU) then the KVM timer state is
 419      * already saved and can be restored when it is synced back to KVM.
 420      */
 421     if (!running) {
 422         if (!cs->kvm_vcpu_dirty) {
 423             ret = kvm_mips_save_count(cs);
 424             if (ret < 0) {
 425                 fprintf(stderr, "Failed saving count\n");
 426             }
 427         }
 428     } else {
 429         /* Set clock restore time to now */
 430         count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
 431         ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
 432                                      &count_resume);
 433         if (ret < 0) {
 434             fprintf(stderr, "Failed setting COUNT_RESUME\n");
 435             return;
 436         }
 437
 438         if (!cs->kvm_vcpu_dirty) {
 439             ret = kvm_mips_restore_count(cs);
 440             if (ret < 0) {
 441                 fprintf(stderr, "Failed restoring count\n");
 442             }
 443         }
 444     }
 445 }
 446
 447 static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
 448 {
 449     MIPSCPU *cpu = MIPS_CPU(cs);
 450     CPUMIPSState *env = &cpu->env;
 451     int err, ret = 0;
 452
 453     (void)level;
 454
 455     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 456     if (err < 0) {
 457         DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
 458         ret = err;
 459     }
 460     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 461                                  &env->CP0_Context);
 462     if (err < 0) {
 463         DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
 464         ret = err;
 465     }
 466     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 467                                  &env->active_tc.CP0_UserLocal);
 468     if (err < 0) {
 469         DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
 470         ret = err;
 471     }
 472     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 473                                &env->CP0_PageMask);
 474     if (err < 0) {
 475         DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
 476         ret = err;
 477     }
 478     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 479     if (err < 0) {
 480         DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
 481         ret = err;
 482     }
 483     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 484     if (err < 0) {
 485         DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
 486         ret = err;
 487     }
 488     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 489                                  &env->CP0_BadVAddr);
 490     if (err < 0) {
 491         DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
 492         ret = err;
 493     }
 494
 495     /* If VM clock stopped then state will be restored when it is restarted */
 496     if (runstate_is_running()) {
 497         err = kvm_mips_restore_count(cs);
 498         if (err < 0) {
 499             ret = err;
 500         }
 501     }
 502
 503     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 504                                  &env->CP0_EntryHi);
 505     if (err < 0) {
 506         DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
 507         ret = err;
 508     }
 509     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 510                                &env->CP0_Compare);
 511     if (err < 0) {
 512         DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
 513         ret = err;
 514     }
 515     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 516     if (err < 0) {
 517         DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
 518         ret = err;
 519     }
 520     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 521     if (err < 0) {
 522         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
 523         ret = err;
 524     }
 525     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 526                                  &env->CP0_ErrorEPC);
 527     if (err < 0) {
 528         DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
 529         ret = err;
 530     }
 531
 532     return ret;
 533 }
 534
 535 static int kvm_mips_get_cp0_registers(CPUState *cs)
 536 {
 537     MIPSCPU *cpu = MIPS_CPU(cs);
 538     CPUMIPSState *env = &cpu->env;
 539     int err, ret = 0;
 540
 541     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 542     if (err < 0) {
 543         DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
 544         ret = err;
 545     }
 546     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 547                                  &env->CP0_Context);
 548     if (err < 0) {
 549         DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
 550         ret = err;
 551     }
 552     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 553                                  &env->active_tc.CP0_UserLocal);
 554     if (err < 0) {
 555         DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
 556         ret = err;
 557     }
 558     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 559                                &env->CP0_PageMask);
 560     if (err < 0) {
 561         DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
 562         ret = err;
 563     }
 564     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 565     if (err < 0) {
 566         DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
 567         ret = err;
 568     }
 569     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 570     if (err < 0) {
 571         DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
 572         ret = err;
 573     }
 574     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 575                                  &env->CP0_BadVAddr);
 576     if (err < 0) {
 577         DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
 578         ret = err;
 579     }
 580     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 581                                  &env->CP0_EntryHi);
 582     if (err < 0) {
 583         DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
 584         ret = err;
 585     }
 586     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 587                                &env->CP0_Compare);
 588     if (err < 0) {
 589         DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
 590         ret = err;
 591     }
 592     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 593     if (err < 0) {
 594         DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
 595         ret = err;
 596     }
 597
 598     /* If VM clock stopped then state was already saved when it was stopped */
 599     if (runstate_is_running()) {
 600         err = kvm_mips_save_count(cs);
 601         if (err < 0) {
 602             ret = err;
 603         }
 604     }
 605
 606     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 607     if (err < 0) {
 608         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
 609         ret = err;
 610     }
 611     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 612                                  &env->CP0_ErrorEPC);
 613     if (err < 0) {
 614         DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
 615         ret = err;
 616     }
 617
 618     return ret;
 619 }
 620
 621 int kvm_arch_put_registers(CPUState *cs, int level)
 622 {
 623     MIPSCPU *cpu = MIPS_CPU(cs);
 624     CPUMIPSState *env = &cpu->env;
 625     struct kvm_regs regs;
 626     int ret;
 627     int i;
 628
 629     /* Set the registers based on QEMU's view of things */
 630     for (i = 0; i < 32; i++) {
 631         regs.gpr[i] = (int64_t)(target_long)env->active_tc.gpr[i];
 632     }
 633
 634     regs.hi = (int64_t)(target_long)env->active_tc.HI[0];
 635     regs.lo = (int64_t)(target_long)env->active_tc.LO[0];
 636     regs.pc = (int64_t)(target_long)env->active_tc.PC;
 637
 638     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
 639
 640     if (ret < 0) {
 641         return ret;
 642     }
 643
 644     ret = kvm_mips_put_cp0_registers(cs, level);
 645     if (ret < 0) {
 646         return ret;
 647     }
 648
 649     return ret;
 650 }
 651
 652 int kvm_arch_get_registers(CPUState *cs)
 653 {
 654     MIPSCPU *cpu = MIPS_CPU(cs);
 655     CPUMIPSState *env = &cpu->env;
 656     int ret = 0;
 657     struct kvm_regs regs;
 658     int i;
 659
 660     /* Get the current register set as KVM seems it */
 661     ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
 662
 663     if (ret < 0) {
 664         return ret;
 665     }
 666
 667     for (i = 0; i < 32; i++) {
 668         env->active_tc.gpr[i] = regs.gpr[i];
 669     }
 670
 671     env->active_tc.HI[0] = regs.hi;
 672     env->active_tc.LO[0] = regs.lo;
 673     env->active_tc.PC = regs.pc;
 674
 675     kvm_mips_get_cp0_registers(cs);
 676
 677     return ret;
 678 }
 679
 680 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 681                              uint64_t address, uint32_t data, PCIDevice *dev)
 682 {
 683     return 0;
 684 }
 685
 686 int kvm_arch_msi_data_to_gsi(uint32_t data)
 687 {
 688     abort();
 689 }