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apic: move target-dependent definitions to cpu.h
[qemu/rayw.git] / target-sparc / ldst_helper.c
blob658e7d8585e28399455ebee5658cf0d3a4d6e6b7
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24
25 //#define DEBUG_MMU
26 //#define DEBUG_MXCC
27 //#define DEBUG_UNALIGNED
28 //#define DEBUG_UNASSIGNED
29 //#define DEBUG_ASI
30 //#define DEBUG_CACHE_CONTROL
31
32 #ifdef DEBUG_MMU
33 #define DPRINTF_MMU(fmt, ...) \
34 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
35 #else
36 #define DPRINTF_MMU(fmt, ...) do {} while (0)
37 #endif
38
39 #ifdef DEBUG_MXCC
40 #define DPRINTF_MXCC(fmt, ...) \
41 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
42 #else
43 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
44 #endif
45
46 #ifdef DEBUG_ASI
47 #define DPRINTF_ASI(fmt, ...) \
48 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
49 #endif
50
51 #ifdef DEBUG_CACHE_CONTROL
52 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
53 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
54 #else
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
56 #endif
57
58 #ifdef TARGET_SPARC64
59 #ifndef TARGET_ABI32
60 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
61 #else
62 #define AM_CHECK(env1) (1)
63 #endif
64 #endif
65
66 #define QT0 (env->qt0)
67 #define QT1 (env->qt1)
68
69 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
70 /* Calculates TSB pointer value for fault page size 8k or 64k */
71 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
72 uint64_t tag_access_register,
73 int page_size)
74 {
75 uint64_t tsb_base = tsb_register & ~0x1fffULL;
76 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
77 int tsb_size = tsb_register & 0xf;
78
79 /* discard lower 13 bits which hold tag access context */
80 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
81
82 /* now reorder bits */
83 uint64_t tsb_base_mask = ~0x1fffULL;
84 uint64_t va = tag_access_va;
85
86 /* move va bits to correct position */
87 if (page_size == 8*1024) {
88 va >>= 9;
89 } else if (page_size == 64*1024) {
90 va >>= 12;
91 }
92
93 if (tsb_size) {
94 tsb_base_mask <<= tsb_size;
95 }
96
97 /* calculate tsb_base mask and adjust va if split is in use */
98 if (tsb_split) {
99 if (page_size == 8*1024) {
100 va &= ~(1ULL << (13 + tsb_size));
101 } else if (page_size == 64*1024) {
102 va |= (1ULL << (13 + tsb_size));
103 }
104 tsb_base_mask <<= 1;
105 }
106
107 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
108 }
109
110 /* Calculates tag target register value by reordering bits
111 in tag access register */
112 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
113 {
114 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
115 }
116
117 static void replace_tlb_entry(SparcTLBEntry *tlb,
118 uint64_t tlb_tag, uint64_t tlb_tte,
119 CPUSPARCState *env1)
120 {
121 target_ulong mask, size, va, offset;
122
123 /* flush page range if translation is valid */
124 if (TTE_IS_VALID(tlb->tte)) {
125 CPUState *cs = CPU(sparc_env_get_cpu(env1));
126
127 mask = 0xffffffffffffe000ULL;
128 mask <<= 3 * ((tlb->tte >> 61) & 3);
129 size = ~mask + 1;
130
131 va = tlb->tag & mask;
132
133 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
134 tlb_flush_page(cs, va + offset);
135 }
136 }
137
138 tlb->tag = tlb_tag;
139 tlb->tte = tlb_tte;
140 }
141
142 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
143 const char *strmmu, CPUSPARCState *env1)
144 {
145 unsigned int i;
146 target_ulong mask;
147 uint64_t context;
148
149 int is_demap_context = (demap_addr >> 6) & 1;
150
151 /* demap context */
152 switch ((demap_addr >> 4) & 3) {
153 case 0: /* primary */
154 context = env1->dmmu.mmu_primary_context;
155 break;
156 case 1: /* secondary */
157 context = env1->dmmu.mmu_secondary_context;
158 break;
159 case 2: /* nucleus */
160 context = 0;
161 break;
162 case 3: /* reserved */
163 default:
164 return;
165 }
166
167 for (i = 0; i < 64; i++) {
168 if (TTE_IS_VALID(tlb[i].tte)) {
169
170 if (is_demap_context) {
171 /* will remove non-global entries matching context value */
172 if (TTE_IS_GLOBAL(tlb[i].tte) ||
173 !tlb_compare_context(&tlb[i], context)) {
174 continue;
175 }
176 } else {
177 /* demap page
178 will remove any entry matching VA */
179 mask = 0xffffffffffffe000ULL;
180 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
181
182 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
183 continue;
184 }
185
186 /* entry should be global or matching context value */
187 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
188 !tlb_compare_context(&tlb[i], context)) {
189 continue;
190 }
191 }
192
193 replace_tlb_entry(&tlb[i], 0, 0, env1);
194 #ifdef DEBUG_MMU
195 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
196 dump_mmu(stdout, fprintf, env1);
197 #endif
198 }
199 }
200 }
201
202 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
203 uint64_t tlb_tag, uint64_t tlb_tte,
204 const char *strmmu, CPUSPARCState *env1)
205 {
206 unsigned int i, replace_used;
207
208 /* Try replacing invalid entry */
209 for (i = 0; i < 64; i++) {
210 if (!TTE_IS_VALID(tlb[i].tte)) {
211 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
212 #ifdef DEBUG_MMU
213 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
214 dump_mmu(stdout, fprintf, env1);
215 #endif
216 return;
217 }
218 }
219
220 /* All entries are valid, try replacing unlocked entry */
221
222 for (replace_used = 0; replace_used < 2; ++replace_used) {
223
224 /* Used entries are not replaced on first pass */
225
226 for (i = 0; i < 64; i++) {
227 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
228
229 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
230 #ifdef DEBUG_MMU
231 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
232 strmmu, (replace_used ? "used" : "unused"), i);
233 dump_mmu(stdout, fprintf, env1);
234 #endif
235 return;
236 }
237 }
238
239 /* Now reset used bit and search for unused entries again */
240
241 for (i = 0; i < 64; i++) {
242 TTE_SET_UNUSED(tlb[i].tte);
243 }
244 }
245
246 #ifdef DEBUG_MMU
247 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
248 #endif
249 /* error state? */
250 }
251
252 #endif
253
254 #if defined(TARGET_SPARC64) || defined(CONFIG_USER_ONLY)
255 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
256 {
257 #ifdef TARGET_SPARC64
258 if (AM_CHECK(env1)) {
259 addr &= 0xffffffffULL;
260 }
261 #endif
262 return addr;
263 }
264 #endif
265
266 #ifdef TARGET_SPARC64
267 /* returns true if access using this ASI is to have address translated by MMU
268 otherwise access is to raw physical address */
269 /* TODO: check sparc32 bits */
270 static inline int is_translating_asi(int asi)
271 {
272 /* Ultrasparc IIi translating asi
273 - note this list is defined by cpu implementation
274 */
275 switch (asi) {
276 case 0x04 ... 0x11:
277 case 0x16 ... 0x19:
278 case 0x1E ... 0x1F:
279 case 0x24 ... 0x2C:
280 case 0x70 ... 0x73:
281 case 0x78 ... 0x79:
282 case 0x80 ... 0xFF:
283 return 1;
284
285 default:
286 return 0;
287 }
288 }
289
290 static inline target_ulong asi_address_mask(CPUSPARCState *env,
291 int asi, target_ulong addr)
292 {
293 if (is_translating_asi(asi)) {
294 return address_mask(env, addr);
295 } else {
296 return addr;
297 }
298 }
299 #endif
300
301 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
302 {
303 if (addr & align) {
304 #ifdef DEBUG_UNALIGNED
305 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
306 "\n", addr, env->pc);
307 #endif
308 helper_raise_exception(env, TT_UNALIGNED);
309 }
310 }
311
312 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
313 defined(DEBUG_MXCC)
314 static void dump_mxcc(CPUSPARCState *env)
315 {
316 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
317 "\n",
318 env->mxccdata[0], env->mxccdata[1],
319 env->mxccdata[2], env->mxccdata[3]);
320 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
321 "\n"
322 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
323 "\n",
324 env->mxccregs[0], env->mxccregs[1],
325 env->mxccregs[2], env->mxccregs[3],
326 env->mxccregs[4], env->mxccregs[5],
327 env->mxccregs[6], env->mxccregs[7]);
328 }
329 #endif
330
331 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
332 && defined(DEBUG_ASI)
333 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
334 uint64_t r1)
335 {
336 switch (size) {
337 case 1:
338 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
339 addr, asi, r1 & 0xff);
340 break;
341 case 2:
342 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
343 addr, asi, r1 & 0xffff);
344 break;
345 case 4:
346 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
347 addr, asi, r1 & 0xffffffff);
348 break;
349 case 8:
350 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
351 addr, asi, r1);
352 break;
353 }
354 }
355 #endif
356
357 #ifndef TARGET_SPARC64
358 #ifndef CONFIG_USER_ONLY
359
360
361 /* Leon3 cache control */
362
363 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
364 uint64_t val, int size)
365 {
366 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
367 addr, val, size);
368
369 if (size != 4) {
370 DPRINTF_CACHE_CONTROL("32bits only\n");
371 return;
372 }
373
374 switch (addr) {
375 case 0x00: /* Cache control */
376
377 /* These values must always be read as zeros */
378 val &= ~CACHE_CTRL_FD;
379 val &= ~CACHE_CTRL_FI;
380 val &= ~CACHE_CTRL_IB;
381 val &= ~CACHE_CTRL_IP;
382 val &= ~CACHE_CTRL_DP;
383
384 env->cache_control = val;
385 break;
386 case 0x04: /* Instruction cache configuration */
387 case 0x08: /* Data cache configuration */
388 /* Read Only */
389 break;
390 default:
391 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
392 break;
393 };
394 }
395
396 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
397 int size)
398 {
399 uint64_t ret = 0;
400
401 if (size != 4) {
402 DPRINTF_CACHE_CONTROL("32bits only\n");
403 return 0;
404 }
405
406 switch (addr) {
407 case 0x00: /* Cache control */
408 ret = env->cache_control;
409 break;
410
411 /* Configuration registers are read and only always keep those
412 predefined values */
413
414 case 0x04: /* Instruction cache configuration */
415 ret = 0x10220000;
416 break;
417 case 0x08: /* Data cache configuration */
418 ret = 0x18220000;
419 break;
420 default:
421 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
422 break;
423 };
424 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
425 addr, ret, size);
426 return ret;
427 }
428
429 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
430 int sign)
431 {
432 CPUState *cs = CPU(sparc_env_get_cpu(env));
433 uint64_t ret = 0;
434 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
435 uint32_t last_addr = addr;
436 #endif
437
438 helper_check_align(env, addr, size - 1);
439 switch (asi) {
440 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
441 switch (addr) {
442 case 0x00: /* Leon3 Cache Control */
443 case 0x08: /* Leon3 Instruction Cache config */
444 case 0x0C: /* Leon3 Date Cache config */
445 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
446 ret = leon3_cache_control_ld(env, addr, size);
447 }
448 break;
449 case 0x01c00a00: /* MXCC control register */
450 if (size == 8) {
451 ret = env->mxccregs[3];
452 } else {
453 qemu_log_mask(LOG_UNIMP,
454 "%08x: unimplemented access size: %d\n", addr,
455 size);
456 }
457 break;
458 case 0x01c00a04: /* MXCC control register */
459 if (size == 4) {
460 ret = env->mxccregs[3];
461 } else {
462 qemu_log_mask(LOG_UNIMP,
463 "%08x: unimplemented access size: %d\n", addr,
464 size);
465 }
466 break;
467 case 0x01c00c00: /* Module reset register */
468 if (size == 8) {
469 ret = env->mxccregs[5];
470 /* should we do something here? */
471 } else {
472 qemu_log_mask(LOG_UNIMP,
473 "%08x: unimplemented access size: %d\n", addr,
474 size);
475 }
476 break;
477 case 0x01c00f00: /* MBus port address register */
478 if (size == 8) {
479 ret = env->mxccregs[7];
480 } else {
481 qemu_log_mask(LOG_UNIMP,
482 "%08x: unimplemented access size: %d\n", addr,
483 size);
484 }
485 break;
486 default:
487 qemu_log_mask(LOG_UNIMP,
488 "%08x: unimplemented address, size: %d\n", addr,
489 size);
490 break;
491 }
492 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
493 "addr = %08x -> ret = %" PRIx64 ","
494 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
495 #ifdef DEBUG_MXCC
496 dump_mxcc(env);
497 #endif
498 break;
499 case 3: /* MMU probe */
500 case 0x18: /* LEON3 MMU probe */
501 {
502 int mmulev;
503
504 mmulev = (addr >> 8) & 15;
505 if (mmulev > 4) {
506 ret = 0;
507 } else {
508 ret = mmu_probe(env, addr, mmulev);
509 }
510 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
511 addr, mmulev, ret);
512 }
513 break;
514 case 4: /* read MMU regs */
515 case 0x19: /* LEON3 read MMU regs */
516 {
517 int reg = (addr >> 8) & 0x1f;
518
519 ret = env->mmuregs[reg];
520 if (reg == 3) { /* Fault status cleared on read */
521 env->mmuregs[3] = 0;
522 } else if (reg == 0x13) { /* Fault status read */
523 ret = env->mmuregs[3];
524 } else if (reg == 0x14) { /* Fault address read */
525 ret = env->mmuregs[4];
526 }
527 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
528 }
529 break;
530 case 5: /* Turbosparc ITLB Diagnostic */
531 case 6: /* Turbosparc DTLB Diagnostic */
532 case 7: /* Turbosparc IOTLB Diagnostic */
533 break;
534 case 9: /* Supervisor code access */
535 switch (size) {
536 case 1:
537 ret = cpu_ldub_code(env, addr);
538 break;
539 case 2:
540 ret = cpu_lduw_code(env, addr);
541 break;
542 default:
543 case 4:
544 ret = cpu_ldl_code(env, addr);
545 break;
546 case 8:
547 ret = cpu_ldq_code(env, addr);
548 break;
549 }
550 break;
551 case 0xa: /* User data access */
552 switch (size) {
553 case 1:
554 ret = cpu_ldub_user(env, addr);
555 break;
556 case 2:
557 ret = cpu_lduw_user(env, addr);
558 break;
559 default:
560 case 4:
561 ret = cpu_ldl_user(env, addr);
562 break;
563 case 8:
564 ret = cpu_ldq_user(env, addr);
565 break;
566 }
567 break;
568 case 0xb: /* Supervisor data access */
569 case 0x80:
570 switch (size) {
571 case 1:
572 ret = cpu_ldub_kernel(env, addr);
573 break;
574 case 2:
575 ret = cpu_lduw_kernel(env, addr);
576 break;
577 default:
578 case 4:
579 ret = cpu_ldl_kernel(env, addr);
580 break;
581 case 8:
582 ret = cpu_ldq_kernel(env, addr);
583 break;
584 }
585 break;
586 case 0xc: /* I-cache tag */
587 case 0xd: /* I-cache data */
588 case 0xe: /* D-cache tag */
589 case 0xf: /* D-cache data */
590 break;
591 case 0x20: /* MMU passthrough */
592 case 0x1c: /* LEON MMU passthrough */
593 switch (size) {
594 case 1:
595 ret = ldub_phys(cs->as, addr);
596 break;
597 case 2:
598 ret = lduw_phys(cs->as, addr);
599 break;
600 default:
601 case 4:
602 ret = ldl_phys(cs->as, addr);
603 break;
604 case 8:
605 ret = ldq_phys(cs->as, addr);
606 break;
607 }
608 break;
609 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
610 switch (size) {
611 case 1:
612 ret = ldub_phys(cs->as, (hwaddr)addr
613 | ((hwaddr)(asi & 0xf) << 32));
614 break;
615 case 2:
616 ret = lduw_phys(cs->as, (hwaddr)addr
617 | ((hwaddr)(asi & 0xf) << 32));
618 break;
619 default:
620 case 4:
621 ret = ldl_phys(cs->as, (hwaddr)addr
622 | ((hwaddr)(asi & 0xf) << 32));
623 break;
624 case 8:
625 ret = ldq_phys(cs->as, (hwaddr)addr
626 | ((hwaddr)(asi & 0xf) << 32));
627 break;
628 }
629 break;
630 case 0x30: /* Turbosparc secondary cache diagnostic */
631 case 0x31: /* Turbosparc RAM snoop */
632 case 0x32: /* Turbosparc page table descriptor diagnostic */
633 case 0x39: /* data cache diagnostic register */
634 ret = 0;
635 break;
636 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
637 {
638 int reg = (addr >> 8) & 3;
639
640 switch (reg) {
641 case 0: /* Breakpoint Value (Addr) */
642 ret = env->mmubpregs[reg];
643 break;
644 case 1: /* Breakpoint Mask */
645 ret = env->mmubpregs[reg];
646 break;
647 case 2: /* Breakpoint Control */
648 ret = env->mmubpregs[reg];
649 break;
650 case 3: /* Breakpoint Status */
651 ret = env->mmubpregs[reg];
652 env->mmubpregs[reg] = 0ULL;
653 break;
654 }
655 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
656 ret);
657 }
658 break;
659 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
660 ret = env->mmubpctrv;
661 break;
662 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
663 ret = env->mmubpctrc;
664 break;
665 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
666 ret = env->mmubpctrs;
667 break;
668 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
669 ret = env->mmubpaction;
670 break;
671 case 8: /* User code access, XXX */
672 default:
673 cpu_unassigned_access(cs, addr, false, false, asi, size);
674 ret = 0;
675 break;
676 }
677 if (sign) {
678 switch (size) {
679 case 1:
680 ret = (int8_t) ret;
681 break;
682 case 2:
683 ret = (int16_t) ret;
684 break;
685 case 4:
686 ret = (int32_t) ret;
687 break;
688 default:
689 break;
690 }
691 }
692 #ifdef DEBUG_ASI
693 dump_asi("read ", last_addr, asi, size, ret);
694 #endif
695 return ret;
696 }
697
698 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
699 int size)
700 {
701 SPARCCPU *cpu = sparc_env_get_cpu(env);
702 CPUState *cs = CPU(cpu);
703
704 helper_check_align(env, addr, size - 1);
705 switch (asi) {
706 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
707 switch (addr) {
708 case 0x00: /* Leon3 Cache Control */
709 case 0x08: /* Leon3 Instruction Cache config */
710 case 0x0C: /* Leon3 Date Cache config */
711 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
712 leon3_cache_control_st(env, addr, val, size);
713 }
714 break;
715
716 case 0x01c00000: /* MXCC stream data register 0 */
717 if (size == 8) {
718 env->mxccdata[0] = val;
719 } else {
720 qemu_log_mask(LOG_UNIMP,
721 "%08x: unimplemented access size: %d\n", addr,
722 size);
723 }
724 break;
725 case 0x01c00008: /* MXCC stream data register 1 */
726 if (size == 8) {
727 env->mxccdata[1] = val;
728 } else {
729 qemu_log_mask(LOG_UNIMP,
730 "%08x: unimplemented access size: %d\n", addr,
731 size);
732 }
733 break;
734 case 0x01c00010: /* MXCC stream data register 2 */
735 if (size == 8) {
736 env->mxccdata[2] = val;
737 } else {
738 qemu_log_mask(LOG_UNIMP,
739 "%08x: unimplemented access size: %d\n", addr,
740 size);
741 }
742 break;
743 case 0x01c00018: /* MXCC stream data register 3 */
744 if (size == 8) {
745 env->mxccdata[3] = val;
746 } else {
747 qemu_log_mask(LOG_UNIMP,
748 "%08x: unimplemented access size: %d\n", addr,
749 size);
750 }
751 break;
752 case 0x01c00100: /* MXCC stream source */
753 if (size == 8) {
754 env->mxccregs[0] = val;
755 } else {
756 qemu_log_mask(LOG_UNIMP,
757 "%08x: unimplemented access size: %d\n", addr,
758 size);
759 }
760 env->mxccdata[0] = ldq_phys(cs->as,
761 (env->mxccregs[0] & 0xffffffffULL) +
762 0);
763 env->mxccdata[1] = ldq_phys(cs->as,
764 (env->mxccregs[0] & 0xffffffffULL) +
765 8);
766 env->mxccdata[2] = ldq_phys(cs->as,
767 (env->mxccregs[0] & 0xffffffffULL) +
768 16);
769 env->mxccdata[3] = ldq_phys(cs->as,
770 (env->mxccregs[0] & 0xffffffffULL) +
771 24);
772 break;
773 case 0x01c00200: /* MXCC stream destination */
774 if (size == 8) {
775 env->mxccregs[1] = val;
776 } else {
777 qemu_log_mask(LOG_UNIMP,
778 "%08x: unimplemented access size: %d\n", addr,
779 size);
780 }
781 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
782 env->mxccdata[0]);
783 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
784 env->mxccdata[1]);
785 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
786 env->mxccdata[2]);
787 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
788 env->mxccdata[3]);
789 break;
790 case 0x01c00a00: /* MXCC control register */
791 if (size == 8) {
792 env->mxccregs[3] = val;
793 } else {
794 qemu_log_mask(LOG_UNIMP,
795 "%08x: unimplemented access size: %d\n", addr,
796 size);
797 }
798 break;
799 case 0x01c00a04: /* MXCC control register */
800 if (size == 4) {
801 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
802 | val;
803 } else {
804 qemu_log_mask(LOG_UNIMP,
805 "%08x: unimplemented access size: %d\n", addr,
806 size);
807 }
808 break;
809 case 0x01c00e00: /* MXCC error register */
810 /* writing a 1 bit clears the error */
811 if (size == 8) {
812 env->mxccregs[6] &= ~val;
813 } else {
814 qemu_log_mask(LOG_UNIMP,
815 "%08x: unimplemented access size: %d\n", addr,
816 size);
817 }
818 break;
819 case 0x01c00f00: /* MBus port address register */
820 if (size == 8) {
821 env->mxccregs[7] = val;
822 } else {
823 qemu_log_mask(LOG_UNIMP,
824 "%08x: unimplemented access size: %d\n", addr,
825 size);
826 }
827 break;
828 default:
829 qemu_log_mask(LOG_UNIMP,
830 "%08x: unimplemented address, size: %d\n", addr,
831 size);
832 break;
833 }
834 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
835 asi, size, addr, val);
836 #ifdef DEBUG_MXCC
837 dump_mxcc(env);
838 #endif
839 break;
840 case 3: /* MMU flush */
841 case 0x18: /* LEON3 MMU flush */
842 {
843 int mmulev;
844
845 mmulev = (addr >> 8) & 15;
846 DPRINTF_MMU("mmu flush level %d\n", mmulev);
847 switch (mmulev) {
848 case 0: /* flush page */
849 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
850 break;
851 case 1: /* flush segment (256k) */
852 case 2: /* flush region (16M) */
853 case 3: /* flush context (4G) */
854 case 4: /* flush entire */
855 tlb_flush(CPU(cpu), 1);
856 break;
857 default:
858 break;
859 }
860 #ifdef DEBUG_MMU
861 dump_mmu(stdout, fprintf, env);
862 #endif
863 }
864 break;
865 case 4: /* write MMU regs */
866 case 0x19: /* LEON3 write MMU regs */
867 {
868 int reg = (addr >> 8) & 0x1f;
869 uint32_t oldreg;
870
871 oldreg = env->mmuregs[reg];
872 switch (reg) {
873 case 0: /* Control Register */
874 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
875 (val & 0x00ffffff);
876 /* Mappings generated during no-fault mode or MMU
877 disabled mode are invalid in normal mode */
878 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
879 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
880 tlb_flush(CPU(cpu), 1);
881 }
882 break;
883 case 1: /* Context Table Pointer Register */
884 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
885 break;
886 case 2: /* Context Register */
887 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
888 if (oldreg != env->mmuregs[reg]) {
889 /* we flush when the MMU context changes because
890 QEMU has no MMU context support */
891 tlb_flush(CPU(cpu), 1);
892 }
893 break;
894 case 3: /* Synchronous Fault Status Register with Clear */
895 case 4: /* Synchronous Fault Address Register */
896 break;
897 case 0x10: /* TLB Replacement Control Register */
898 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
899 break;
900 case 0x13: /* Synchronous Fault Status Register with Read
901 and Clear */
902 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
903 break;
904 case 0x14: /* Synchronous Fault Address Register */
905 env->mmuregs[4] = val;
906 break;
907 default:
908 env->mmuregs[reg] = val;
909 break;
910 }
911 if (oldreg != env->mmuregs[reg]) {
912 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
913 reg, oldreg, env->mmuregs[reg]);
914 }
915 #ifdef DEBUG_MMU
916 dump_mmu(stdout, fprintf, env);
917 #endif
918 }
919 break;
920 case 5: /* Turbosparc ITLB Diagnostic */
921 case 6: /* Turbosparc DTLB Diagnostic */
922 case 7: /* Turbosparc IOTLB Diagnostic */
923 break;
924 case 0xa: /* User data access */
925 switch (size) {
926 case 1:
927 cpu_stb_user(env, addr, val);
928 break;
929 case 2:
930 cpu_stw_user(env, addr, val);
931 break;
932 default:
933 case 4:
934 cpu_stl_user(env, addr, val);
935 break;
936 case 8:
937 cpu_stq_user(env, addr, val);
938 break;
939 }
940 break;
941 case 0xb: /* Supervisor data access */
942 case 0x80:
943 switch (size) {
944 case 1:
945 cpu_stb_kernel(env, addr, val);
946 break;
947 case 2:
948 cpu_stw_kernel(env, addr, val);
949 break;
950 default:
951 case 4:
952 cpu_stl_kernel(env, addr, val);
953 break;
954 case 8:
955 cpu_stq_kernel(env, addr, val);
956 break;
957 }
958 break;
959 case 0xc: /* I-cache tag */
960 case 0xd: /* I-cache data */
961 case 0xe: /* D-cache tag */
962 case 0xf: /* D-cache data */
963 case 0x10: /* I/D-cache flush page */
964 case 0x11: /* I/D-cache flush segment */
965 case 0x12: /* I/D-cache flush region */
966 case 0x13: /* I/D-cache flush context */
967 case 0x14: /* I/D-cache flush user */
968 break;
969 case 0x17: /* Block copy, sta access */
970 {
971 /* val = src
972 addr = dst
973 copy 32 bytes */
974 unsigned int i;
975 uint32_t src = val & ~3, dst = addr & ~3, temp;
976
977 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
978 temp = cpu_ldl_kernel(env, src);
979 cpu_stl_kernel(env, dst, temp);
980 }
981 }
982 break;
983 case 0x1f: /* Block fill, stda access */
984 {
985 /* addr = dst
986 fill 32 bytes with val */
987 unsigned int i;
988 uint32_t dst = addr & 7;
989
990 for (i = 0; i < 32; i += 8, dst += 8) {
991 cpu_stq_kernel(env, dst, val);
992 }
993 }
994 break;
995 case 0x20: /* MMU passthrough */
996 case 0x1c: /* LEON MMU passthrough */
997 {
998 switch (size) {
999 case 1:
1000 stb_phys(cs->as, addr, val);
1001 break;
1002 case 2:
1003 stw_phys(cs->as, addr, val);
1004 break;
1005 case 4:
1006 default:
1007 stl_phys(cs->as, addr, val);
1008 break;
1009 case 8:
1010 stq_phys(cs->as, addr, val);
1011 break;
1012 }
1013 }
1014 break;
1015 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1016 {
1017 switch (size) {
1018 case 1:
1019 stb_phys(cs->as, (hwaddr)addr
1020 | ((hwaddr)(asi & 0xf) << 32), val);
1021 break;
1022 case 2:
1023 stw_phys(cs->as, (hwaddr)addr
1024 | ((hwaddr)(asi & 0xf) << 32), val);
1025 break;
1026 case 4:
1027 default:
1028 stl_phys(cs->as, (hwaddr)addr
1029 | ((hwaddr)(asi & 0xf) << 32), val);
1030 break;
1031 case 8:
1032 stq_phys(cs->as, (hwaddr)addr
1033 | ((hwaddr)(asi & 0xf) << 32), val);
1034 break;
1035 }
1036 }
1037 break;
1038 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1039 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1040 Turbosparc snoop RAM */
1041 case 0x32: /* store buffer control or Turbosparc page table
1042 descriptor diagnostic */
1043 case 0x36: /* I-cache flash clear */
1044 case 0x37: /* D-cache flash clear */
1045 break;
1046 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1047 {
1048 int reg = (addr >> 8) & 3;
1049
1050 switch (reg) {
1051 case 0: /* Breakpoint Value (Addr) */
1052 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1053 break;
1054 case 1: /* Breakpoint Mask */
1055 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1056 break;
1057 case 2: /* Breakpoint Control */
1058 env->mmubpregs[reg] = (val & 0x7fULL);
1059 break;
1060 case 3: /* Breakpoint Status */
1061 env->mmubpregs[reg] = (val & 0xfULL);
1062 break;
1063 }
1064 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1065 env->mmuregs[reg]);
1066 }
1067 break;
1068 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1069 env->mmubpctrv = val & 0xffffffff;
1070 break;
1071 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1072 env->mmubpctrc = val & 0x3;
1073 break;
1074 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1075 env->mmubpctrs = val & 0x3;
1076 break;
1077 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1078 env->mmubpaction = val & 0x1fff;
1079 break;
1080 case 8: /* User code access, XXX */
1081 case 9: /* Supervisor code access, XXX */
1082 default:
1083 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1084 addr, true, false, asi, size);
1085 break;
1086 }
1087 #ifdef DEBUG_ASI
1088 dump_asi("write", addr, asi, size, val);
1089 #endif
1090 }
1091
1092 #endif /* CONFIG_USER_ONLY */
1093 #else /* TARGET_SPARC64 */
1094
1095 #ifdef CONFIG_USER_ONLY
1096 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1097 int sign)
1098 {
1099 uint64_t ret = 0;
1100 #if defined(DEBUG_ASI)
1101 target_ulong last_addr = addr;
1102 #endif
1103
1104 if (asi < 0x80) {
1105 helper_raise_exception(env, TT_PRIV_ACT);
1106 }
1107
1108 helper_check_align(env, addr, size - 1);
1109 addr = asi_address_mask(env, asi, addr);
1110
1111 switch (asi) {
1112 case 0x82: /* Primary no-fault */
1113 case 0x8a: /* Primary no-fault LE */
1114 if (page_check_range(addr, size, PAGE_READ) == -1) {
1115 #ifdef DEBUG_ASI
1116 dump_asi("read ", last_addr, asi, size, ret);
1117 #endif
1118 return 0;
1119 }
1120 /* Fall through */
1121 case 0x80: /* Primary */
1122 case 0x88: /* Primary LE */
1123 {
1124 switch (size) {
1125 case 1:
1126 ret = cpu_ldub_data(env, addr);
1127 break;
1128 case 2:
1129 ret = cpu_lduw_data(env, addr);
1130 break;
1131 case 4:
1132 ret = cpu_ldl_data(env, addr);
1133 break;
1134 default:
1135 case 8:
1136 ret = cpu_ldq_data(env, addr);
1137 break;
1138 }
1139 }
1140 break;
1141 case 0x83: /* Secondary no-fault */
1142 case 0x8b: /* Secondary no-fault LE */
1143 if (page_check_range(addr, size, PAGE_READ) == -1) {
1144 #ifdef DEBUG_ASI
1145 dump_asi("read ", last_addr, asi, size, ret);
1146 #endif
1147 return 0;
1148 }
1149 /* Fall through */
1150 case 0x81: /* Secondary */
1151 case 0x89: /* Secondary LE */
1152 /* XXX */
1153 break;
1154 default:
1155 break;
1156 }
1157
1158 /* Convert from little endian */
1159 switch (asi) {
1160 case 0x88: /* Primary LE */
1161 case 0x89: /* Secondary LE */
1162 case 0x8a: /* Primary no-fault LE */
1163 case 0x8b: /* Secondary no-fault LE */
1164 switch (size) {
1165 case 2:
1166 ret = bswap16(ret);
1167 break;
1168 case 4:
1169 ret = bswap32(ret);
1170 break;
1171 case 8:
1172 ret = bswap64(ret);
1173 break;
1174 default:
1175 break;
1176 }
1177 default:
1178 break;
1179 }
1180
1181 /* Convert to signed number */
1182 if (sign) {
1183 switch (size) {
1184 case 1:
1185 ret = (int8_t) ret;
1186 break;
1187 case 2:
1188 ret = (int16_t) ret;
1189 break;
1190 case 4:
1191 ret = (int32_t) ret;
1192 break;
1193 default:
1194 break;
1195 }
1196 }
1197 #ifdef DEBUG_ASI
1198 dump_asi("read ", last_addr, asi, size, ret);
1199 #endif
1200 return ret;
1201 }
1202
1203 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1204 int asi, int size)
1205 {
1206 #ifdef DEBUG_ASI
1207 dump_asi("write", addr, asi, size, val);
1208 #endif
1209 if (asi < 0x80) {
1210 helper_raise_exception(env, TT_PRIV_ACT);
1211 }
1212
1213 helper_check_align(env, addr, size - 1);
1214 addr = asi_address_mask(env, asi, addr);
1215
1216 /* Convert to little endian */
1217 switch (asi) {
1218 case 0x88: /* Primary LE */
1219 case 0x89: /* Secondary LE */
1220 switch (size) {
1221 case 2:
1222 val = bswap16(val);
1223 break;
1224 case 4:
1225 val = bswap32(val);
1226 break;
1227 case 8:
1228 val = bswap64(val);
1229 break;
1230 default:
1231 break;
1232 }
1233 default:
1234 break;
1235 }
1236
1237 switch (asi) {
1238 case 0x80: /* Primary */
1239 case 0x88: /* Primary LE */
1240 {
1241 switch (size) {
1242 case 1:
1243 cpu_stb_data(env, addr, val);
1244 break;
1245 case 2:
1246 cpu_stw_data(env, addr, val);
1247 break;
1248 case 4:
1249 cpu_stl_data(env, addr, val);
1250 break;
1251 case 8:
1252 default:
1253 cpu_stq_data(env, addr, val);
1254 break;
1255 }
1256 }
1257 break;
1258 case 0x81: /* Secondary */
1259 case 0x89: /* Secondary LE */
1260 /* XXX */
1261 return;
1262
1263 case 0x82: /* Primary no-fault, RO */
1264 case 0x83: /* Secondary no-fault, RO */
1265 case 0x8a: /* Primary no-fault LE, RO */
1266 case 0x8b: /* Secondary no-fault LE, RO */
1267 default:
1268 helper_raise_exception(env, TT_DATA_ACCESS);
1269 return;
1270 }
1271 }
1272
1273 #else /* CONFIG_USER_ONLY */
1274
1275 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1276 int sign)
1277 {
1278 CPUState *cs = CPU(sparc_env_get_cpu(env));
1279 uint64_t ret = 0;
1280 #if defined(DEBUG_ASI)
1281 target_ulong last_addr = addr;
1282 #endif
1283
1284 asi &= 0xff;
1285
1286 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1287 || (cpu_has_hypervisor(env)
1288 && asi >= 0x30 && asi < 0x80
1289 && !(env->hpstate & HS_PRIV))) {
1290 helper_raise_exception(env, TT_PRIV_ACT);
1291 }
1292
1293 helper_check_align(env, addr, size - 1);
1294 addr = asi_address_mask(env, asi, addr);
1295
1296 /* process nonfaulting loads first */
1297 if ((asi & 0xf6) == 0x82) {
1298 int mmu_idx;
1299
1300 /* secondary space access has lowest asi bit equal to 1 */
1301 if (env->pstate & PS_PRIV) {
1302 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1303 } else {
1304 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1305 }
1306
1307 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1308 #ifdef DEBUG_ASI
1309 dump_asi("read ", last_addr, asi, size, ret);
1310 #endif
1311 /* env->exception_index is set in get_physical_address_data(). */
1312 helper_raise_exception(env, cs->exception_index);
1313 }
1314
1315 /* convert nonfaulting load ASIs to normal load ASIs */
1316 asi &= ~0x02;
1317 }
1318
1319 switch (asi) {
1320 case 0x10: /* As if user primary */
1321 case 0x11: /* As if user secondary */
1322 case 0x18: /* As if user primary LE */
1323 case 0x19: /* As if user secondary LE */
1324 case 0x80: /* Primary */
1325 case 0x81: /* Secondary */
1326 case 0x88: /* Primary LE */
1327 case 0x89: /* Secondary LE */
1328 case 0xe2: /* UA2007 Primary block init */
1329 case 0xe3: /* UA2007 Secondary block init */
1330 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1331 if (cpu_hypervisor_mode(env)) {
1332 switch (size) {
1333 case 1:
1334 ret = cpu_ldub_hypv(env, addr);
1335 break;
1336 case 2:
1337 ret = cpu_lduw_hypv(env, addr);
1338 break;
1339 case 4:
1340 ret = cpu_ldl_hypv(env, addr);
1341 break;
1342 default:
1343 case 8:
1344 ret = cpu_ldq_hypv(env, addr);
1345 break;
1346 }
1347 } else {
1348 /* secondary space access has lowest asi bit equal to 1 */
1349 if (asi & 1) {
1350 switch (size) {
1351 case 1:
1352 ret = cpu_ldub_kernel_secondary(env, addr);
1353 break;
1354 case 2:
1355 ret = cpu_lduw_kernel_secondary(env, addr);
1356 break;
1357 case 4:
1358 ret = cpu_ldl_kernel_secondary(env, addr);
1359 break;
1360 default:
1361 case 8:
1362 ret = cpu_ldq_kernel_secondary(env, addr);
1363 break;
1364 }
1365 } else {
1366 switch (size) {
1367 case 1:
1368 ret = cpu_ldub_kernel(env, addr);
1369 break;
1370 case 2:
1371 ret = cpu_lduw_kernel(env, addr);
1372 break;
1373 case 4:
1374 ret = cpu_ldl_kernel(env, addr);
1375 break;
1376 default:
1377 case 8:
1378 ret = cpu_ldq_kernel(env, addr);
1379 break;
1380 }
1381 }
1382 }
1383 } else {
1384 /* secondary space access has lowest asi bit equal to 1 */
1385 if (asi & 1) {
1386 switch (size) {
1387 case 1:
1388 ret = cpu_ldub_user_secondary(env, addr);
1389 break;
1390 case 2:
1391 ret = cpu_lduw_user_secondary(env, addr);
1392 break;
1393 case 4:
1394 ret = cpu_ldl_user_secondary(env, addr);
1395 break;
1396 default:
1397 case 8:
1398 ret = cpu_ldq_user_secondary(env, addr);
1399 break;
1400 }
1401 } else {
1402 switch (size) {
1403 case 1:
1404 ret = cpu_ldub_user(env, addr);
1405 break;
1406 case 2:
1407 ret = cpu_lduw_user(env, addr);
1408 break;
1409 case 4:
1410 ret = cpu_ldl_user(env, addr);
1411 break;
1412 default:
1413 case 8:
1414 ret = cpu_ldq_user(env, addr);
1415 break;
1416 }
1417 }
1418 }
1419 break;
1420 case 0x14: /* Bypass */
1421 case 0x15: /* Bypass, non-cacheable */
1422 case 0x1c: /* Bypass LE */
1423 case 0x1d: /* Bypass, non-cacheable LE */
1424 {
1425 switch (size) {
1426 case 1:
1427 ret = ldub_phys(cs->as, addr);
1428 break;
1429 case 2:
1430 ret = lduw_phys(cs->as, addr);
1431 break;
1432 case 4:
1433 ret = ldl_phys(cs->as, addr);
1434 break;
1435 default:
1436 case 8:
1437 ret = ldq_phys(cs->as, addr);
1438 break;
1439 }
1440 break;
1441 }
1442 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1443 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1444 Only ldda allowed */
1445 helper_raise_exception(env, TT_ILL_INSN);
1446 return 0;
1447 case 0x04: /* Nucleus */
1448 case 0x0c: /* Nucleus Little Endian (LE) */
1449 {
1450 switch (size) {
1451 case 1:
1452 ret = cpu_ldub_nucleus(env, addr);
1453 break;
1454 case 2:
1455 ret = cpu_lduw_nucleus(env, addr);
1456 break;
1457 case 4:
1458 ret = cpu_ldl_nucleus(env, addr);
1459 break;
1460 default:
1461 case 8:
1462 ret = cpu_ldq_nucleus(env, addr);
1463 break;
1464 }
1465 break;
1466 }
1467 case 0x4a: /* UPA config */
1468 /* XXX */
1469 break;
1470 case 0x45: /* LSU */
1471 ret = env->lsu;
1472 break;
1473 case 0x50: /* I-MMU regs */
1474 {
1475 int reg = (addr >> 3) & 0xf;
1476
1477 if (reg == 0) {
1478 /* I-TSB Tag Target register */
1479 ret = ultrasparc_tag_target(env->immu.tag_access);
1480 } else {
1481 ret = env->immuregs[reg];
1482 }
1483
1484 break;
1485 }
1486 case 0x51: /* I-MMU 8k TSB pointer */
1487 {
1488 /* env->immuregs[5] holds I-MMU TSB register value
1489 env->immuregs[6] holds I-MMU Tag Access register value */
1490 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1491 8*1024);
1492 break;
1493 }
1494 case 0x52: /* I-MMU 64k TSB pointer */
1495 {
1496 /* env->immuregs[5] holds I-MMU TSB register value
1497 env->immuregs[6] holds I-MMU Tag Access register value */
1498 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1499 64*1024);
1500 break;
1501 }
1502 case 0x55: /* I-MMU data access */
1503 {
1504 int reg = (addr >> 3) & 0x3f;
1505
1506 ret = env->itlb[reg].tte;
1507 break;
1508 }
1509 case 0x56: /* I-MMU tag read */
1510 {
1511 int reg = (addr >> 3) & 0x3f;
1512
1513 ret = env->itlb[reg].tag;
1514 break;
1515 }
1516 case 0x58: /* D-MMU regs */
1517 {
1518 int reg = (addr >> 3) & 0xf;
1519
1520 if (reg == 0) {
1521 /* D-TSB Tag Target register */
1522 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1523 } else {
1524 ret = env->dmmuregs[reg];
1525 }
1526 break;
1527 }
1528 case 0x59: /* D-MMU 8k TSB pointer */
1529 {
1530 /* env->dmmuregs[5] holds D-MMU TSB register value
1531 env->dmmuregs[6] holds D-MMU Tag Access register value */
1532 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1533 8*1024);
1534 break;
1535 }
1536 case 0x5a: /* D-MMU 64k TSB pointer */
1537 {
1538 /* env->dmmuregs[5] holds D-MMU TSB register value
1539 env->dmmuregs[6] holds D-MMU Tag Access register value */
1540 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1541 64*1024);
1542 break;
1543 }
1544 case 0x5d: /* D-MMU data access */
1545 {
1546 int reg = (addr >> 3) & 0x3f;
1547
1548 ret = env->dtlb[reg].tte;
1549 break;
1550 }
1551 case 0x5e: /* D-MMU tag read */
1552 {
1553 int reg = (addr >> 3) & 0x3f;
1554
1555 ret = env->dtlb[reg].tag;
1556 break;
1557 }
1558 case 0x48: /* Interrupt dispatch, RO */
1559 break;
1560 case 0x49: /* Interrupt data receive */
1561 ret = env->ivec_status;
1562 break;
1563 case 0x7f: /* Incoming interrupt vector, RO */
1564 {
1565 int reg = (addr >> 4) & 0x3;
1566 if (reg < 3) {
1567 ret = env->ivec_data[reg];
1568 }
1569 break;
1570 }
1571 case 0x46: /* D-cache data */
1572 case 0x47: /* D-cache tag access */
1573 case 0x4b: /* E-cache error enable */
1574 case 0x4c: /* E-cache asynchronous fault status */
1575 case 0x4d: /* E-cache asynchronous fault address */
1576 case 0x4e: /* E-cache tag data */
1577 case 0x66: /* I-cache instruction access */
1578 case 0x67: /* I-cache tag access */
1579 case 0x6e: /* I-cache predecode */
1580 case 0x6f: /* I-cache LRU etc. */
1581 case 0x76: /* E-cache tag */
1582 case 0x7e: /* E-cache tag */
1583 break;
1584 case 0x5b: /* D-MMU data pointer */
1585 case 0x54: /* I-MMU data in, WO */
1586 case 0x57: /* I-MMU demap, WO */
1587 case 0x5c: /* D-MMU data in, WO */
1588 case 0x5f: /* D-MMU demap, WO */
1589 case 0x77: /* Interrupt vector, WO */
1590 default:
1591 cpu_unassigned_access(cs, addr, false, false, 1, size);
1592 ret = 0;
1593 break;
1594 }
1595
1596 /* Convert from little endian */
1597 switch (asi) {
1598 case 0x0c: /* Nucleus Little Endian (LE) */
1599 case 0x18: /* As if user primary LE */
1600 case 0x19: /* As if user secondary LE */
1601 case 0x1c: /* Bypass LE */
1602 case 0x1d: /* Bypass, non-cacheable LE */
1603 case 0x88: /* Primary LE */
1604 case 0x89: /* Secondary LE */
1605 switch(size) {
1606 case 2:
1607 ret = bswap16(ret);
1608 break;
1609 case 4:
1610 ret = bswap32(ret);
1611 break;
1612 case 8:
1613 ret = bswap64(ret);
1614 break;
1615 default:
1616 break;
1617 }
1618 default:
1619 break;
1620 }
1621
1622 /* Convert to signed number */
1623 if (sign) {
1624 switch (size) {
1625 case 1:
1626 ret = (int8_t) ret;
1627 break;
1628 case 2:
1629 ret = (int16_t) ret;
1630 break;
1631 case 4:
1632 ret = (int32_t) ret;
1633 break;
1634 default:
1635 break;
1636 }
1637 }
1638 #ifdef DEBUG_ASI
1639 dump_asi("read ", last_addr, asi, size, ret);
1640 #endif
1641 return ret;
1642 }
1643
1644 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1645 int asi, int size)
1646 {
1647 SPARCCPU *cpu = sparc_env_get_cpu(env);
1648 CPUState *cs = CPU(cpu);
1649
1650 #ifdef DEBUG_ASI
1651 dump_asi("write", addr, asi, size, val);
1652 #endif
1653
1654 asi &= 0xff;
1655
1656 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1657 || (cpu_has_hypervisor(env)
1658 && asi >= 0x30 && asi < 0x80
1659 && !(env->hpstate & HS_PRIV))) {
1660 helper_raise_exception(env, TT_PRIV_ACT);
1661 }
1662
1663 helper_check_align(env, addr, size - 1);
1664 addr = asi_address_mask(env, asi, addr);
1665
1666 /* Convert to little endian */
1667 switch (asi) {
1668 case 0x0c: /* Nucleus Little Endian (LE) */
1669 case 0x18: /* As if user primary LE */
1670 case 0x19: /* As if user secondary LE */
1671 case 0x1c: /* Bypass LE */
1672 case 0x1d: /* Bypass, non-cacheable LE */
1673 case 0x88: /* Primary LE */
1674 case 0x89: /* Secondary LE */
1675 switch (size) {
1676 case 2:
1677 val = bswap16(val);
1678 break;
1679 case 4:
1680 val = bswap32(val);
1681 break;
1682 case 8:
1683 val = bswap64(val);
1684 break;
1685 default:
1686 break;
1687 }
1688 default:
1689 break;
1690 }
1691
1692 switch (asi) {
1693 case 0x10: /* As if user primary */
1694 case 0x11: /* As if user secondary */
1695 case 0x18: /* As if user primary LE */
1696 case 0x19: /* As if user secondary LE */
1697 case 0x80: /* Primary */
1698 case 0x81: /* Secondary */
1699 case 0x88: /* Primary LE */
1700 case 0x89: /* Secondary LE */
1701 case 0xe2: /* UA2007 Primary block init */
1702 case 0xe3: /* UA2007 Secondary block init */
1703 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1704 if (cpu_hypervisor_mode(env)) {
1705 switch (size) {
1706 case 1:
1707 cpu_stb_hypv(env, addr, val);
1708 break;
1709 case 2:
1710 cpu_stw_hypv(env, addr, val);
1711 break;
1712 case 4:
1713 cpu_stl_hypv(env, addr, val);
1714 break;
1715 case 8:
1716 default:
1717 cpu_stq_hypv(env, addr, val);
1718 break;
1719 }
1720 } else {
1721 /* secondary space access has lowest asi bit equal to 1 */
1722 if (asi & 1) {
1723 switch (size) {
1724 case 1:
1725 cpu_stb_kernel_secondary(env, addr, val);
1726 break;
1727 case 2:
1728 cpu_stw_kernel_secondary(env, addr, val);
1729 break;
1730 case 4:
1731 cpu_stl_kernel_secondary(env, addr, val);
1732 break;
1733 case 8:
1734 default:
1735 cpu_stq_kernel_secondary(env, addr, val);
1736 break;
1737 }
1738 } else {
1739 switch (size) {
1740 case 1:
1741 cpu_stb_kernel(env, addr, val);
1742 break;
1743 case 2:
1744 cpu_stw_kernel(env, addr, val);
1745 break;
1746 case 4:
1747 cpu_stl_kernel(env, addr, val);
1748 break;
1749 case 8:
1750 default:
1751 cpu_stq_kernel(env, addr, val);
1752 break;
1753 }
1754 }
1755 }
1756 } else {
1757 /* secondary space access has lowest asi bit equal to 1 */
1758 if (asi & 1) {
1759 switch (size) {
1760 case 1:
1761 cpu_stb_user_secondary(env, addr, val);
1762 break;
1763 case 2:
1764 cpu_stw_user_secondary(env, addr, val);
1765 break;
1766 case 4:
1767 cpu_stl_user_secondary(env, addr, val);
1768 break;
1769 case 8:
1770 default:
1771 cpu_stq_user_secondary(env, addr, val);
1772 break;
1773 }
1774 } else {
1775 switch (size) {
1776 case 1:
1777 cpu_stb_user(env, addr, val);
1778 break;
1779 case 2:
1780 cpu_stw_user(env, addr, val);
1781 break;
1782 case 4:
1783 cpu_stl_user(env, addr, val);
1784 break;
1785 case 8:
1786 default:
1787 cpu_stq_user(env, addr, val);
1788 break;
1789 }
1790 }
1791 }
1792 break;
1793 case 0x14: /* Bypass */
1794 case 0x15: /* Bypass, non-cacheable */
1795 case 0x1c: /* Bypass LE */
1796 case 0x1d: /* Bypass, non-cacheable LE */
1797 {
1798 switch (size) {
1799 case 1:
1800 stb_phys(cs->as, addr, val);
1801 break;
1802 case 2:
1803 stw_phys(cs->as, addr, val);
1804 break;
1805 case 4:
1806 stl_phys(cs->as, addr, val);
1807 break;
1808 case 8:
1809 default:
1810 stq_phys(cs->as, addr, val);
1811 break;
1812 }
1813 }
1814 return;
1815 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1816 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1817 Only ldda allowed */
1818 helper_raise_exception(env, TT_ILL_INSN);
1819 return;
1820 case 0x04: /* Nucleus */
1821 case 0x0c: /* Nucleus Little Endian (LE) */
1822 {
1823 switch (size) {
1824 case 1:
1825 cpu_stb_nucleus(env, addr, val);
1826 break;
1827 case 2:
1828 cpu_stw_nucleus(env, addr, val);
1829 break;
1830 case 4:
1831 cpu_stl_nucleus(env, addr, val);
1832 break;
1833 default:
1834 case 8:
1835 cpu_stq_nucleus(env, addr, val);
1836 break;
1837 }
1838 break;
1839 }
1840
1841 case 0x4a: /* UPA config */
1842 /* XXX */
1843 return;
1844 case 0x45: /* LSU */
1845 {
1846 uint64_t oldreg;
1847
1848 oldreg = env->lsu;
1849 env->lsu = val & (DMMU_E | IMMU_E);
1850 /* Mappings generated during D/I MMU disabled mode are
1851 invalid in normal mode */
1852 if (oldreg != env->lsu) {
1853 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1854 oldreg, env->lsu);
1855 #ifdef DEBUG_MMU
1856 dump_mmu(stdout, fprintf, env);
1857 #endif
1858 tlb_flush(CPU(cpu), 1);
1859 }
1860 return;
1861 }
1862 case 0x50: /* I-MMU regs */
1863 {
1864 int reg = (addr >> 3) & 0xf;
1865 uint64_t oldreg;
1866
1867 oldreg = env->immuregs[reg];
1868 switch (reg) {
1869 case 0: /* RO */
1870 return;
1871 case 1: /* Not in I-MMU */
1872 case 2:
1873 return;
1874 case 3: /* SFSR */
1875 if ((val & 1) == 0) {
1876 val = 0; /* Clear SFSR */
1877 }
1878 env->immu.sfsr = val;
1879 break;
1880 case 4: /* RO */
1881 return;
1882 case 5: /* TSB access */
1883 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1884 PRIx64 "\n", env->immu.tsb, val);
1885 env->immu.tsb = val;
1886 break;
1887 case 6: /* Tag access */
1888 env->immu.tag_access = val;
1889 break;
1890 case 7:
1891 case 8:
1892 return;
1893 default:
1894 break;
1895 }
1896
1897 if (oldreg != env->immuregs[reg]) {
1898 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1899 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1900 }
1901 #ifdef DEBUG_MMU
1902 dump_mmu(stdout, fprintf, env);
1903 #endif
1904 return;
1905 }
1906 case 0x54: /* I-MMU data in */
1907 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1908 return;
1909 case 0x55: /* I-MMU data access */
1910 {
1911 /* TODO: auto demap */
1912
1913 unsigned int i = (addr >> 3) & 0x3f;
1914
1915 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1916
1917 #ifdef DEBUG_MMU
1918 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1919 dump_mmu(stdout, fprintf, env);
1920 #endif
1921 return;
1922 }
1923 case 0x57: /* I-MMU demap */
1924 demap_tlb(env->itlb, addr, "immu", env);
1925 return;
1926 case 0x58: /* D-MMU regs */
1927 {
1928 int reg = (addr >> 3) & 0xf;
1929 uint64_t oldreg;
1930
1931 oldreg = env->dmmuregs[reg];
1932 switch (reg) {
1933 case 0: /* RO */
1934 case 4:
1935 return;
1936 case 3: /* SFSR */
1937 if ((val & 1) == 0) {
1938 val = 0; /* Clear SFSR, Fault address */
1939 env->dmmu.sfar = 0;
1940 }
1941 env->dmmu.sfsr = val;
1942 break;
1943 case 1: /* Primary context */
1944 env->dmmu.mmu_primary_context = val;
1945 /* can be optimized to only flush MMU_USER_IDX
1946 and MMU_KERNEL_IDX entries */
1947 tlb_flush(CPU(cpu), 1);
1948 break;
1949 case 2: /* Secondary context */
1950 env->dmmu.mmu_secondary_context = val;
1951 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1952 and MMU_KERNEL_SECONDARY_IDX entries */
1953 tlb_flush(CPU(cpu), 1);
1954 break;
1955 case 5: /* TSB access */
1956 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1957 PRIx64 "\n", env->dmmu.tsb, val);
1958 env->dmmu.tsb = val;
1959 break;
1960 case 6: /* Tag access */
1961 env->dmmu.tag_access = val;
1962 break;
1963 case 7: /* Virtual Watchpoint */
1964 case 8: /* Physical Watchpoint */
1965 default:
1966 env->dmmuregs[reg] = val;
1967 break;
1968 }
1969
1970 if (oldreg != env->dmmuregs[reg]) {
1971 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1972 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1973 }
1974 #ifdef DEBUG_MMU
1975 dump_mmu(stdout, fprintf, env);
1976 #endif
1977 return;
1978 }
1979 case 0x5c: /* D-MMU data in */
1980 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1981 return;
1982 case 0x5d: /* D-MMU data access */
1983 {
1984 unsigned int i = (addr >> 3) & 0x3f;
1985
1986 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1987
1988 #ifdef DEBUG_MMU
1989 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1990 dump_mmu(stdout, fprintf, env);
1991 #endif
1992 return;
1993 }
1994 case 0x5f: /* D-MMU demap */
1995 demap_tlb(env->dtlb, addr, "dmmu", env);
1996 return;
1997 case 0x49: /* Interrupt data receive */
1998 env->ivec_status = val & 0x20;
1999 return;
2000 case 0x46: /* D-cache data */
2001 case 0x47: /* D-cache tag access */
2002 case 0x4b: /* E-cache error enable */
2003 case 0x4c: /* E-cache asynchronous fault status */
2004 case 0x4d: /* E-cache asynchronous fault address */
2005 case 0x4e: /* E-cache tag data */
2006 case 0x66: /* I-cache instruction access */
2007 case 0x67: /* I-cache tag access */
2008 case 0x6e: /* I-cache predecode */
2009 case 0x6f: /* I-cache LRU etc. */
2010 case 0x76: /* E-cache tag */
2011 case 0x7e: /* E-cache tag */
2012 return;
2013 case 0x51: /* I-MMU 8k TSB pointer, RO */
2014 case 0x52: /* I-MMU 64k TSB pointer, RO */
2015 case 0x56: /* I-MMU tag read, RO */
2016 case 0x59: /* D-MMU 8k TSB pointer, RO */
2017 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2018 case 0x5b: /* D-MMU data pointer, RO */
2019 case 0x5e: /* D-MMU tag read, RO */
2020 case 0x48: /* Interrupt dispatch, RO */
2021 case 0x7f: /* Incoming interrupt vector, RO */
2022 case 0x82: /* Primary no-fault, RO */
2023 case 0x83: /* Secondary no-fault, RO */
2024 case 0x8a: /* Primary no-fault LE, RO */
2025 case 0x8b: /* Secondary no-fault LE, RO */
2026 default:
2027 cpu_unassigned_access(cs, addr, true, false, 1, size);
2028 return;
2029 }
2030 }
2031 #endif /* CONFIG_USER_ONLY */
2032
2033 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2034 {
2035 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2036 || (cpu_has_hypervisor(env)
2037 && asi >= 0x30 && asi < 0x80
2038 && !(env->hpstate & HS_PRIV))) {
2039 helper_raise_exception(env, TT_PRIV_ACT);
2040 }
2041
2042 addr = asi_address_mask(env, asi, addr);
2043
2044 switch (asi) {
2045 #if !defined(CONFIG_USER_ONLY)
2046 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2047 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2048 helper_check_align(env, addr, 0xf);
2049 if (rd == 0) {
2050 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2051 if (asi == 0x2c) {
2052 bswap64s(&env->gregs[1]);
2053 }
2054 } else if (rd < 8) {
2055 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2056 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2057 if (asi == 0x2c) {
2058 bswap64s(&env->gregs[rd]);
2059 bswap64s(&env->gregs[rd + 1]);
2060 }
2061 } else {
2062 env->regwptr[rd - 8] = cpu_ldq_nucleus(env, addr);
2063 env->regwptr[rd + 1 - 8] = cpu_ldq_nucleus(env, addr + 8);
2064 if (asi == 0x2c) {
2065 bswap64s(&env->regwptr[rd - 8]);
2066 bswap64s(&env->regwptr[rd + 1 - 8]);
2067 }
2068 }
2069 break;
2070 #endif
2071 default:
2072 helper_check_align(env, addr, 0x3);
2073 if (rd == 0) {
2074 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2075 } else if (rd < 8) {
2076 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2077 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2078 } else {
2079 env->regwptr[rd - 8] = helper_ld_asi(env, addr, asi, 4, 0);
2080 env->regwptr[rd + 1 - 8] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2081 }
2082 break;
2083 }
2084 }
2085
2086 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2087 int rd)
2088 {
2089 unsigned int i;
2090 target_ulong val;
2091
2092 helper_check_align(env, addr, 3);
2093 addr = asi_address_mask(env, asi, addr);
2094
2095 switch (asi) {
2096 case 0xf0: /* UA2007/JPS1 Block load primary */
2097 case 0xf1: /* UA2007/JPS1 Block load secondary */
2098 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2099 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2100 if (rd & 7) {
2101 helper_raise_exception(env, TT_ILL_INSN);
2102 return;
2103 }
2104 helper_check_align(env, addr, 0x3f);
2105 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2106 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2107 }
2108 return;
2109
2110 case 0x16: /* UA2007 Block load primary, user privilege */
2111 case 0x17: /* UA2007 Block load secondary, user privilege */
2112 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2113 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2114 case 0x70: /* JPS1 Block load primary, user privilege */
2115 case 0x71: /* JPS1 Block load secondary, user privilege */
2116 case 0x78: /* JPS1 Block load primary LE, user privilege */
2117 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2118 if (rd & 7) {
2119 helper_raise_exception(env, TT_ILL_INSN);
2120 return;
2121 }
2122 helper_check_align(env, addr, 0x3f);
2123 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2124 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2125 }
2126 return;
2127
2128 default:
2129 break;
2130 }
2131
2132 switch (size) {
2133 default:
2134 case 4:
2135 val = helper_ld_asi(env, addr, asi, size, 0);
2136 if (rd & 1) {
2137 env->fpr[rd / 2].l.lower = val;
2138 } else {
2139 env->fpr[rd / 2].l.upper = val;
2140 }
2141 break;
2142 case 8:
2143 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2144 break;
2145 case 16:
2146 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2147 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2148 break;
2149 }
2150 }
2151
2152 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2153 int rd)
2154 {
2155 unsigned int i;
2156 target_ulong val;
2157
2158 addr = asi_address_mask(env, asi, addr);
2159
2160 switch (asi) {
2161 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2162 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2163 case 0xf0: /* UA2007/JPS1 Block store primary */
2164 case 0xf1: /* UA2007/JPS1 Block store secondary */
2165 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2166 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2167 if (rd & 7) {
2168 helper_raise_exception(env, TT_ILL_INSN);
2169 return;
2170 }
2171 helper_check_align(env, addr, 0x3f);
2172 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2173 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2174 }
2175
2176 return;
2177 case 0x16: /* UA2007 Block load primary, user privilege */
2178 case 0x17: /* UA2007 Block load secondary, user privilege */
2179 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2180 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2181 case 0x70: /* JPS1 Block store primary, user privilege */
2182 case 0x71: /* JPS1 Block store secondary, user privilege */
2183 case 0x78: /* JPS1 Block load primary LE, user privilege */
2184 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2185 if (rd & 7) {
2186 helper_raise_exception(env, TT_ILL_INSN);
2187 return;
2188 }
2189 helper_check_align(env, addr, 0x3f);
2190 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2191 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2192 }
2193
2194 return;
2195 case 0xd2: /* 16-bit floating point load primary */
2196 case 0xd3: /* 16-bit floating point load secondary */
2197 case 0xda: /* 16-bit floating point load primary, LE */
2198 case 0xdb: /* 16-bit floating point load secondary, LE */
2199 helper_check_align(env, addr, 1);
2200 /* Fall through */
2201 case 0xd0: /* 8-bit floating point load primary */
2202 case 0xd1: /* 8-bit floating point load secondary */
2203 case 0xd8: /* 8-bit floating point load primary, LE */
2204 case 0xd9: /* 8-bit floating point load secondary, LE */
2205 val = env->fpr[rd / 2].l.lower;
2206 helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1);
2207 return;
2208 default:
2209 helper_check_align(env, addr, 3);
2210 break;
2211 }
2212
2213 switch (size) {
2214 default:
2215 case 4:
2216 if (rd & 1) {
2217 val = env->fpr[rd / 2].l.lower;
2218 } else {
2219 val = env->fpr[rd / 2].l.upper;
2220 }
2221 helper_st_asi(env, addr, val, asi, size);
2222 break;
2223 case 8:
2224 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2225 break;
2226 case 16:
2227 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2228 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2229 break;
2230 }
2231 }
2232
2233 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2234 target_ulong val1, target_ulong val2,
2235 uint32_t asi)
2236 {
2237 target_ulong ret;
2238
2239 ret = helper_ld_asi(env, addr, asi, 8, 0);
2240 if (val2 == ret) {
2241 helper_st_asi(env, addr, val1, asi, 8);
2242 }
2243 return ret;
2244 }
2245 #endif /* TARGET_SPARC64 */
2246
2247 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2248 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2249 target_ulong val1, target_ulong val2, uint32_t asi)
2250 {
2251 target_ulong ret;
2252
2253 val2 &= 0xffffffffUL;
2254 ret = helper_ld_asi(env, addr, asi, 4, 0);
2255 ret &= 0xffffffffUL;
2256 if (val2 == ret) {
2257 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2258 }
2259 return ret;
2260 }
2261 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2262
2263 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2264 {
2265 /* XXX add 128 bit load */
2266 CPU_QuadU u;
2267
2268 helper_check_align(env, addr, 7);
2269 #if !defined(CONFIG_USER_ONLY)
2270 switch (mem_idx) {
2271 case MMU_USER_IDX:
2272 u.ll.upper = cpu_ldq_user(env, addr);
2273 u.ll.lower = cpu_ldq_user(env, addr + 8);
2274 QT0 = u.q;
2275 break;
2276 case MMU_KERNEL_IDX:
2277 u.ll.upper = cpu_ldq_kernel(env, addr);
2278 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2279 QT0 = u.q;
2280 break;
2281 #ifdef TARGET_SPARC64
2282 case MMU_HYPV_IDX:
2283 u.ll.upper = cpu_ldq_hypv(env, addr);
2284 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2285 QT0 = u.q;
2286 break;
2287 #endif
2288 default:
2289 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2290 break;
2291 }
2292 #else
2293 u.ll.upper = cpu_ldq_data(env, address_mask(env, addr));
2294 u.ll.lower = cpu_ldq_data(env, address_mask(env, addr + 8));
2295 QT0 = u.q;
2296 #endif
2297 }
2298
2299 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2300 {
2301 /* XXX add 128 bit store */
2302 CPU_QuadU u;
2303
2304 helper_check_align(env, addr, 7);
2305 #if !defined(CONFIG_USER_ONLY)
2306 switch (mem_idx) {
2307 case MMU_USER_IDX:
2308 u.q = QT0;
2309 cpu_stq_user(env, addr, u.ll.upper);
2310 cpu_stq_user(env, addr + 8, u.ll.lower);
2311 break;
2312 case MMU_KERNEL_IDX:
2313 u.q = QT0;
2314 cpu_stq_kernel(env, addr, u.ll.upper);
2315 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2316 break;
2317 #ifdef TARGET_SPARC64
2318 case MMU_HYPV_IDX:
2319 u.q = QT0;
2320 cpu_stq_hypv(env, addr, u.ll.upper);
2321 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2322 break;
2323 #endif
2324 default:
2325 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2326 break;
2327 }
2328 #else
2329 u.q = QT0;
2330 cpu_stq_data(env, address_mask(env, addr), u.ll.upper);
2331 cpu_stq_data(env, address_mask(env, addr + 8), u.ll.lower);
2332 #endif
2333 }
2334
2335 #if !defined(CONFIG_USER_ONLY)
2336 #ifndef TARGET_SPARC64
2337 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2338 bool is_write, bool is_exec, int is_asi,
2339 unsigned size)
2340 {
2341 SPARCCPU *cpu = SPARC_CPU(cs);
2342 CPUSPARCState *env = &cpu->env;
2343 int fault_type;
2344
2345 #ifdef DEBUG_UNASSIGNED
2346 if (is_asi) {
2347 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2348 " asi 0x%02x from " TARGET_FMT_lx "\n",
2349 is_exec ? "exec" : is_write ? "write" : "read", size,
2350 size == 1 ? "" : "s", addr, is_asi, env->pc);
2351 } else {
2352 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2353 " from " TARGET_FMT_lx "\n",
2354 is_exec ? "exec" : is_write ? "write" : "read", size,
2355 size == 1 ? "" : "s", addr, env->pc);
2356 }
2357 #endif
2358 /* Don't overwrite translation and access faults */
2359 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2360 if ((fault_type > 4) || (fault_type == 0)) {
2361 env->mmuregs[3] = 0; /* Fault status register */
2362 if (is_asi) {
2363 env->mmuregs[3] |= 1 << 16;
2364 }
2365 if (env->psrs) {
2366 env->mmuregs[3] |= 1 << 5;
2367 }
2368 if (is_exec) {
2369 env->mmuregs[3] |= 1 << 6;
2370 }
2371 if (is_write) {
2372 env->mmuregs[3] |= 1 << 7;
2373 }
2374 env->mmuregs[3] |= (5 << 2) | 2;
2375 /* SuperSPARC will never place instruction fault addresses in the FAR */
2376 if (!is_exec) {
2377 env->mmuregs[4] = addr; /* Fault address register */
2378 }
2379 }
2380 /* overflow (same type fault was not read before another fault) */
2381 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2382 env->mmuregs[3] |= 1;
2383 }
2384
2385 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2386 if (is_exec) {
2387 helper_raise_exception(env, TT_CODE_ACCESS);
2388 } else {
2389 helper_raise_exception(env, TT_DATA_ACCESS);
2390 }
2391 }
2392
2393 /* flush neverland mappings created during no-fault mode,
2394 so the sequential MMU faults report proper fault types */
2395 if (env->mmuregs[0] & MMU_NF) {
2396 tlb_flush(cs, 1);
2397 }
2398 }
2399 #else
2400 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2401 bool is_write, bool is_exec, int is_asi,
2402 unsigned size)
2403 {
2404 SPARCCPU *cpu = SPARC_CPU(cs);
2405 CPUSPARCState *env = &cpu->env;
2406
2407 #ifdef DEBUG_UNASSIGNED
2408 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2409 "\n", addr, env->pc);
2410 #endif
2411
2412 if (is_exec) {
2413 helper_raise_exception(env, TT_CODE_ACCESS);
2414 } else {
2415 helper_raise_exception(env, TT_DATA_ACCESS);
2416 }
2417 }
2418 #endif
2419 #endif
2420
2421 #if !defined(CONFIG_USER_ONLY)
2422 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs,
2423 vaddr addr, int is_write,
2424 int is_user, uintptr_t retaddr)
2425 {
2426 SPARCCPU *cpu = SPARC_CPU(cs);
2427 CPUSPARCState *env = &cpu->env;
2428
2429 #ifdef DEBUG_UNALIGNED
2430 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2431 "\n", addr, env->pc);
2432 #endif
2433 if (retaddr) {
2434 cpu_restore_state(CPU(cpu), retaddr);
2435 }
2436 helper_raise_exception(env, TT_UNALIGNED);
2437 }
2438
2439 /* try to fill the TLB and return an exception if error. If retaddr is
2440 NULL, it means that the function was called in C code (i.e. not
2441 from generated code or from helper.c) */
2442 /* XXX: fix it to restore all registers */
2443 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2444 uintptr_t retaddr)
2445 {
2446 int ret;
2447
2448 ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2449 if (ret) {
2450 if (retaddr) {
2451 cpu_restore_state(cs, retaddr);
2452 }
2453 cpu_loop_exit(cs);
2454 }
2455 }
2456 #endif
Ray Wang's QEMU Repository