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PPC: Add L1CFG1 SPR emulation
[qemu/rayw.git] / target-ppc / translate_init.c
blobfc9d9322689203f76448309ac5675f2408ab187c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31
32 //#define PPC_DUMP_CPU
33 //#define PPC_DEBUG_SPR
34 //#define PPC_DUMP_SPR_ACCESSES
35
36 /* For user-mode emulation, we don't emulate any IRQ controller */
37 #if defined(CONFIG_USER_ONLY)
38 #define PPC_IRQ_INIT_FN(name) \
39 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
40 { \
41 }
42 #else
43 #define PPC_IRQ_INIT_FN(name) \
44 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
45 #endif
46
47 PPC_IRQ_INIT_FN(40x);
48 PPC_IRQ_INIT_FN(6xx);
49 PPC_IRQ_INIT_FN(970);
50 PPC_IRQ_INIT_FN(POWER7);
51 PPC_IRQ_INIT_FN(e500);
52
53 /* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
56 static void spr_load_dump_spr(int sprn)
57 {
58 #ifdef PPC_DUMP_SPR_ACCESSES
59 TCGv_i32 t0 = tcg_const_i32(sprn);
60 gen_helper_load_dump_spr(cpu_env, t0);
61 tcg_temp_free_i32(t0);
62 #endif
63 }
64
65 static void spr_read_generic (void *opaque, int gprn, int sprn)
66 {
67 gen_load_spr(cpu_gpr[gprn], sprn);
68 spr_load_dump_spr(sprn);
69 }
70
71 static void spr_store_dump_spr(int sprn)
72 {
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 TCGv_i32 t0 = tcg_const_i32(sprn);
75 gen_helper_store_dump_spr(cpu_env, t0);
76 tcg_temp_free_i32(t0);
77 #endif
78 }
79
80 static void spr_write_generic (void *opaque, int sprn, int gprn)
81 {
82 gen_store_spr(sprn, cpu_gpr[gprn]);
83 spr_store_dump_spr(sprn);
84 }
85
86 #if !defined(CONFIG_USER_ONLY)
87 static void spr_write_generic32(void *opaque, int sprn, int gprn)
88 {
89 #ifdef TARGET_PPC64
90 TCGv t0 = tcg_temp_new();
91 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
92 gen_store_spr(sprn, t0);
93 tcg_temp_free(t0);
94 spr_store_dump_spr(sprn);
95 #else
96 spr_write_generic(opaque, sprn, gprn);
97 #endif
98 }
99
100 static void spr_write_clear (void *opaque, int sprn, int gprn)
101 {
102 TCGv t0 = tcg_temp_new();
103 TCGv t1 = tcg_temp_new();
104 gen_load_spr(t0, sprn);
105 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
106 tcg_gen_and_tl(t0, t0, t1);
107 gen_store_spr(sprn, t0);
108 tcg_temp_free(t0);
109 tcg_temp_free(t1);
110 }
111
112 static void spr_access_nop(void *opaque, int sprn, int gprn)
113 {
114 }
115
116 #endif
117
118 /* SPR common to all PowerPC */
119 /* XER */
120 static void spr_read_xer (void *opaque, int gprn, int sprn)
121 {
122 gen_read_xer(cpu_gpr[gprn]);
123 }
124
125 static void spr_write_xer (void *opaque, int sprn, int gprn)
126 {
127 gen_write_xer(cpu_gpr[gprn]);
128 }
129
130 /* LR */
131 static void spr_read_lr (void *opaque, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
134 }
135
136 static void spr_write_lr (void *opaque, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
139 }
140
141 /* CFAR */
142 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
143 static void spr_read_cfar (void *opaque, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
146 }
147
148 static void spr_write_cfar (void *opaque, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
151 }
152 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
153
154 /* CTR */
155 static void spr_read_ctr (void *opaque, int gprn, int sprn)
156 {
157 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
158 }
159
160 static void spr_write_ctr (void *opaque, int sprn, int gprn)
161 {
162 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
163 }
164
165 /* User read access to SPR */
166 /* USPRx */
167 /* UMMCRx */
168 /* UPMCx */
169 /* USIA */
170 /* UDECR */
171 static void spr_read_ureg (void *opaque, int gprn, int sprn)
172 {
173 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
174 }
175
176 /* SPR common to all non-embedded PowerPC */
177 /* DECR */
178 #if !defined(CONFIG_USER_ONLY)
179 static void spr_read_decr (void *opaque, int gprn, int sprn)
180 {
181 if (use_icount) {
182 gen_io_start();
183 }
184 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
185 if (use_icount) {
186 gen_io_end();
187 gen_stop_exception(opaque);
188 }
189 }
190
191 static void spr_write_decr (void *opaque, int sprn, int gprn)
192 {
193 if (use_icount) {
194 gen_io_start();
195 }
196 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
197 if (use_icount) {
198 gen_io_end();
199 gen_stop_exception(opaque);
200 }
201 }
202 #endif
203
204 /* SPR common to all non-embedded PowerPC, except 601 */
205 /* Time base */
206 static void spr_read_tbl (void *opaque, int gprn, int sprn)
207 {
208 if (use_icount) {
209 gen_io_start();
210 }
211 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
212 if (use_icount) {
213 gen_io_end();
214 gen_stop_exception(opaque);
215 }
216 }
217
218 static void spr_read_tbu (void *opaque, int gprn, int sprn)
219 {
220 if (use_icount) {
221 gen_io_start();
222 }
223 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
224 if (use_icount) {
225 gen_io_end();
226 gen_stop_exception(opaque);
227 }
228 }
229
230 __attribute__ (( unused ))
231 static void spr_read_atbl (void *opaque, int gprn, int sprn)
232 {
233 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
234 }
235
236 __attribute__ (( unused ))
237 static void spr_read_atbu (void *opaque, int gprn, int sprn)
238 {
239 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
240 }
241
242 #if !defined(CONFIG_USER_ONLY)
243 static void spr_write_tbl (void *opaque, int sprn, int gprn)
244 {
245 if (use_icount) {
246 gen_io_start();
247 }
248 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
249 if (use_icount) {
250 gen_io_end();
251 gen_stop_exception(opaque);
252 }
253 }
254
255 static void spr_write_tbu (void *opaque, int sprn, int gprn)
256 {
257 if (use_icount) {
258 gen_io_start();
259 }
260 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
261 if (use_icount) {
262 gen_io_end();
263 gen_stop_exception(opaque);
264 }
265 }
266
267 __attribute__ (( unused ))
268 static void spr_write_atbl (void *opaque, int sprn, int gprn)
269 {
270 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
271 }
272
273 __attribute__ (( unused ))
274 static void spr_write_atbu (void *opaque, int sprn, int gprn)
275 {
276 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
277 }
278
279 #if defined(TARGET_PPC64)
280 __attribute__ (( unused ))
281 static void spr_read_purr (void *opaque, int gprn, int sprn)
282 {
283 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
284 }
285 #endif
286 #endif
287
288 #if !defined(CONFIG_USER_ONLY)
289 /* IBAT0U...IBAT0U */
290 /* IBAT0L...IBAT7L */
291 static void spr_read_ibat (void *opaque, int gprn, int sprn)
292 {
293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
294 }
295
296 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
297 {
298 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
299 }
300
301 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
302 {
303 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
304 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
305 tcg_temp_free_i32(t0);
306 }
307
308 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
309 {
310 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
311 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
312 tcg_temp_free_i32(t0);
313 }
314
315 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
316 {
317 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
318 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
319 tcg_temp_free_i32(t0);
320 }
321
322 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
323 {
324 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
325 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
326 tcg_temp_free_i32(t0);
327 }
328
329 /* DBAT0U...DBAT7U */
330 /* DBAT0L...DBAT7L */
331 static void spr_read_dbat (void *opaque, int gprn, int sprn)
332 {
333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
334 }
335
336 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
337 {
338 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
339 }
340
341 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
342 {
343 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
344 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
345 tcg_temp_free_i32(t0);
346 }
347
348 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
349 {
350 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
351 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
352 tcg_temp_free_i32(t0);
353 }
354
355 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
356 {
357 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
358 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
359 tcg_temp_free_i32(t0);
360 }
361
362 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
363 {
364 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
365 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
367 }
368
369 /* SDR1 */
370 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
371 {
372 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
373 }
374
375 /* 64 bits PowerPC specific SPRs */
376 #if defined(TARGET_PPC64)
377 static void spr_read_hior (void *opaque, int gprn, int sprn)
378 {
379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
380 }
381
382 static void spr_write_hior (void *opaque, int sprn, int gprn)
383 {
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
387 tcg_temp_free(t0);
388 }
389 #endif
390 #endif
391
392 /* PowerPC 601 specific registers */
393 /* RTC */
394 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
397 }
398
399 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
400 {
401 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
402 }
403
404 #if !defined(CONFIG_USER_ONLY)
405 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
411 {
412 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
413 }
414
415 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
416 {
417 DisasContext *ctx = opaque;
418
419 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
420 /* Must stop the translation as endianness may have changed */
421 gen_stop_exception(ctx);
422 }
423 #endif
424
425 /* Unified bats */
426 #if !defined(CONFIG_USER_ONLY)
427 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
428 {
429 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
430 }
431
432 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
433 {
434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
435 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
436 tcg_temp_free_i32(t0);
437 }
438
439 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
440 {
441 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
442 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
443 tcg_temp_free_i32(t0);
444 }
445 #endif
446
447 /* PowerPC 40x specific registers */
448 #if !defined(CONFIG_USER_ONLY)
449 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
450 {
451 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
452 }
453
454 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
455 {
456 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
457 }
458
459 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
460 {
461 DisasContext *ctx = opaque;
462
463 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
464 /* We must stop translation as we may have rebooted */
465 gen_stop_exception(ctx);
466 }
467
468 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
469 {
470 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
471 }
472
473 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
474 {
475 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
476 }
477
478 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
479 {
480 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
481 }
482 #endif
483
484 /* PowerPC 403 specific registers */
485 /* PBL1 / PBU1 / PBL2 / PBU2 */
486 #if !defined(CONFIG_USER_ONLY)
487 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
488 {
489 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
490 }
491
492 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
493 {
494 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
495 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
496 tcg_temp_free_i32(t0);
497 }
498
499 static void spr_write_pir (void *opaque, int sprn, int gprn)
500 {
501 TCGv t0 = tcg_temp_new();
502 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
503 gen_store_spr(SPR_PIR, t0);
504 tcg_temp_free(t0);
505 }
506 #endif
507
508 /* SPE specific registers */
509 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
510 {
511 TCGv_i32 t0 = tcg_temp_new_i32();
512 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
513 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
514 tcg_temp_free_i32(t0);
515 }
516
517 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
518 {
519 TCGv_i32 t0 = tcg_temp_new_i32();
520 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
521 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
522 tcg_temp_free_i32(t0);
523 }
524
525 #if !defined(CONFIG_USER_ONLY)
526 /* Callback used to write the exception vector base */
527 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
528 {
529 TCGv t0 = tcg_temp_new();
530 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
531 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
532 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
533 gen_store_spr(sprn, t0);
534 tcg_temp_free(t0);
535 }
536
537 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
538 {
539 DisasContext *ctx = opaque;
540 int sprn_offs;
541
542 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
543 sprn_offs = sprn - SPR_BOOKE_IVOR0;
544 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
545 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
546 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
547 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
548 } else {
549 printf("Trying to write an unknown exception vector %d %03x\n",
550 sprn, sprn);
551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
552 return;
553 }
554
555 TCGv t0 = tcg_temp_new();
556 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
557 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
558 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
559 gen_store_spr(sprn, t0);
560 tcg_temp_free(t0);
561 }
562 #endif
563
564 static inline void vscr_init (CPUPPCState *env, uint32_t val)
565 {
566 env->vscr = val;
567 /* Altivec always uses round-to-nearest */
568 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
569 set_flush_to_zero(vscr_nj, &env->vec_status);
570 }
571
572 #ifdef CONFIG_USER_ONLY
573 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
574 oea_read, oea_write, one_reg_id, initial_value) \
575 _spr_register(env, num, name, uea_read, uea_write, initial_value)
576 #else
577 #if !defined(CONFIG_KVM)
578 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
579 oea_read, oea_write, one_reg_id, initial_value) \
580 _spr_register(env, num, name, uea_read, uea_write, \
581 oea_read, oea_write, initial_value)
582 #else
583 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, \
586 oea_read, oea_write, one_reg_id, initial_value)
587 #endif
588 #endif
589
590 #define spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, initial_value) \
592 spr_register_kvm(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, 0, initial_value)
594
595 static inline void _spr_register(CPUPPCState *env, int num,
596 const char *name,
597 void (*uea_read)(void *opaque, int gprn, int sprn),
598 void (*uea_write)(void *opaque, int sprn, int gprn),
599 #if !defined(CONFIG_USER_ONLY)
600
601 void (*oea_read)(void *opaque, int gprn, int sprn),
602 void (*oea_write)(void *opaque, int sprn, int gprn),
603 #endif
604 #if defined(CONFIG_KVM)
605 uint64_t one_reg_id,
606 #endif
607 target_ulong initial_value)
608 {
609 ppc_spr_t *spr;
610
611 spr = &env->spr_cb[num];
612 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
613 #if !defined(CONFIG_USER_ONLY)
614 spr->oea_read != NULL || spr->oea_write != NULL ||
615 #endif
616 spr->uea_read != NULL || spr->uea_write != NULL) {
617 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
618 exit(1);
619 }
620 #if defined(PPC_DEBUG_SPR)
621 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
622 name, initial_value);
623 #endif
624 spr->name = name;
625 spr->uea_read = uea_read;
626 spr->uea_write = uea_write;
627 #if !defined(CONFIG_USER_ONLY)
628 spr->oea_read = oea_read;
629 spr->oea_write = oea_write;
630 #endif
631 #if defined(CONFIG_KVM)
632 spr->one_reg_id = one_reg_id,
633 #endif
634 env->spr[num] = spr->default_value = initial_value;
635 }
636
637 /* Generic PowerPC SPRs */
638 static void gen_spr_generic (CPUPPCState *env)
639 {
640 /* Integer processing */
641 spr_register(env, SPR_XER, "XER",
642 &spr_read_xer, &spr_write_xer,
643 &spr_read_xer, &spr_write_xer,
644 0x00000000);
645 /* Branch contol */
646 spr_register(env, SPR_LR, "LR",
647 &spr_read_lr, &spr_write_lr,
648 &spr_read_lr, &spr_write_lr,
649 0x00000000);
650 spr_register(env, SPR_CTR, "CTR",
651 &spr_read_ctr, &spr_write_ctr,
652 &spr_read_ctr, &spr_write_ctr,
653 0x00000000);
654 /* Interrupt processing */
655 spr_register(env, SPR_SRR0, "SRR0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SRR1, "SRR1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Processor control */
664 spr_register(env, SPR_SPRG0, "SPRG0",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, &spr_write_generic,
667 0x00000000);
668 spr_register(env, SPR_SPRG1, "SPRG1",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_SPRG2, "SPRG2",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SPRG3, "SPRG3",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 }
681
682 /* SPR common to all non-embedded PowerPC, including 601 */
683 static void gen_spr_ne_601 (CPUPPCState *env)
684 {
685 /* Exception processing */
686 spr_register_kvm(env, SPR_DSISR, "DSISR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 KVM_REG_PPC_DSISR, 0x00000000);
690 spr_register_kvm(env, SPR_DAR, "DAR",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, &spr_write_generic,
693 KVM_REG_PPC_DAR, 0x00000000);
694 /* Timer */
695 spr_register(env, SPR_DECR, "DECR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_decr, &spr_write_decr,
698 0x00000000);
699 /* Memory management */
700 spr_register(env, SPR_SDR1, "SDR1",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_sdr1,
703 0x00000000);
704 }
705
706 /* BATs 0-3 */
707 static void gen_low_BATs (CPUPPCState *env)
708 {
709 #if !defined(CONFIG_USER_ONLY)
710 spr_register(env, SPR_IBAT0U, "IBAT0U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT0L, "IBAT0L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT1U, "IBAT1U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT1L, "IBAT1L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_IBAT2U, "IBAT2U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_ibat, &spr_write_ibatu,
729 0x00000000);
730 spr_register(env, SPR_IBAT2L, "IBAT2L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_ibat, &spr_write_ibatl,
733 0x00000000);
734 spr_register(env, SPR_IBAT3U, "IBAT3U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_ibat, &spr_write_ibatu,
737 0x00000000);
738 spr_register(env, SPR_IBAT3L, "IBAT3L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_ibat, &spr_write_ibatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT0U, "DBAT0U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT0L, "DBAT0L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT1U, "DBAT1U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT1L, "DBAT1L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 spr_register(env, SPR_DBAT2U, "DBAT2U",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_dbat, &spr_write_dbatu,
761 0x00000000);
762 spr_register(env, SPR_DBAT2L, "DBAT2L",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_dbat, &spr_write_dbatl,
765 0x00000000);
766 spr_register(env, SPR_DBAT3U, "DBAT3U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_dbat, &spr_write_dbatu,
769 0x00000000);
770 spr_register(env, SPR_DBAT3L, "DBAT3L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_dbat, &spr_write_dbatl,
773 0x00000000);
774 env->nb_BATs += 4;
775 #endif
776 }
777
778 /* BATs 4-7 */
779 static void gen_high_BATs (CPUPPCState *env)
780 {
781 #if !defined(CONFIG_USER_ONLY)
782 spr_register(env, SPR_IBAT4U, "IBAT4U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT4L, "IBAT4L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT5U, "IBAT5U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT5L, "IBAT5L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_IBAT6U, "IBAT6U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat_h, &spr_write_ibatu_h,
801 0x00000000);
802 spr_register(env, SPR_IBAT6L, "IBAT6L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat_h, &spr_write_ibatl_h,
805 0x00000000);
806 spr_register(env, SPR_IBAT7U, "IBAT7U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat_h, &spr_write_ibatu_h,
809 0x00000000);
810 spr_register(env, SPR_IBAT7L, "IBAT7L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_ibat_h, &spr_write_ibatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT4U, "DBAT4U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT4L, "DBAT4L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT5U, "DBAT5U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT5L, "DBAT5L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 spr_register(env, SPR_DBAT6U, "DBAT6U",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat_h, &spr_write_dbatu_h,
833 0x00000000);
834 spr_register(env, SPR_DBAT6L, "DBAT6L",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat_h, &spr_write_dbatl_h,
837 0x00000000);
838 spr_register(env, SPR_DBAT7U, "DBAT7U",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat_h, &spr_write_dbatu_h,
841 0x00000000);
842 spr_register(env, SPR_DBAT7L, "DBAT7L",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_dbat_h, &spr_write_dbatl_h,
845 0x00000000);
846 env->nb_BATs += 4;
847 #endif
848 }
849
850 /* Generic PowerPC time base */
851 static void gen_tbl (CPUPPCState *env)
852 {
853 spr_register(env, SPR_VTBL, "TBL",
854 &spr_read_tbl, SPR_NOACCESS,
855 &spr_read_tbl, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_TBL, "TBL",
858 &spr_read_tbl, SPR_NOACCESS,
859 &spr_read_tbl, &spr_write_tbl,
860 0x00000000);
861 spr_register(env, SPR_VTBU, "TBU",
862 &spr_read_tbu, SPR_NOACCESS,
863 &spr_read_tbu, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_TBU, "TBU",
866 &spr_read_tbu, SPR_NOACCESS,
867 &spr_read_tbu, &spr_write_tbu,
868 0x00000000);
869 }
870
871 /* Softare table search registers */
872 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
873 {
874 #if !defined(CONFIG_USER_ONLY)
875 env->nb_tlb = nb_tlbs;
876 env->nb_ways = nb_ways;
877 env->id_tlbs = 1;
878 env->tlb_type = TLB_6XX;
879 spr_register(env, SPR_DMISS, "DMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_DCMP, "DCMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_HASH1, "HASH1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 0x00000000);
891 spr_register(env, SPR_HASH2, "HASH2",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, SPR_NOACCESS,
894 0x00000000);
895 spr_register(env, SPR_IMISS, "IMISS",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 0x00000000);
899 spr_register(env, SPR_ICMP, "ICMP",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 0x00000000);
903 spr_register(env, SPR_RPA, "RPA",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 #endif
908 }
909
910 /* SPR common to MPC755 and G2 */
911 static void gen_spr_G2_755 (CPUPPCState *env)
912 {
913 /* SGPRs */
914 spr_register(env, SPR_SPRG4, "SPRG4",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 spr_register(env, SPR_SPRG5, "SPRG5",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 spr_register(env, SPR_SPRG6, "SPRG6",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 spr_register(env, SPR_SPRG7, "SPRG7",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 }
931
932 /* SPR common to all 7xx PowerPC implementations */
933 static void gen_spr_7xx (CPUPPCState *env)
934 {
935 /* Breakpoints */
936 /* XXX : not implemented */
937 spr_register_kvm(env, SPR_DABR, "DABR",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 KVM_REG_PPC_DABR, 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_IABR, "IABR",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* Cache management */
947 /* XXX : not implemented */
948 spr_register(env, SPR_ICTC, "ICTC",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* Performance monitors */
953 /* XXX : not implemented */
954 spr_register(env, SPR_MMCR0, "MMCR0",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_MMCR1, "MMCR1",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC1, "PMC1",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC2, "PMC2",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_PMC3, "PMC3",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_PMC4, "PMC4",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_SIAR, "SIAR",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, SPR_NOACCESS,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_UMMCR0, "UMMCR0",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_UMMCR1, "UMMCR1",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_UPMC1, "UPMC1",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_UPMC2, "UPMC2",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_UPMC3, "UPMC3",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_UPMC4, "UPMC4",
1015 &spr_read_ureg, SPR_NOACCESS,
1016 &spr_read_ureg, SPR_NOACCESS,
1017 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_USIAR, "USIAR",
1020 &spr_read_ureg, SPR_NOACCESS,
1021 &spr_read_ureg, SPR_NOACCESS,
1022 0x00000000);
1023 /* External access control */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_EAR, "EAR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 }
1030
1031 #ifdef TARGET_PPC64
1032 #ifndef CONFIG_USER_ONLY
1033 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1034 {
1035 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1036 spr_load_dump_spr(SPR_AMR);
1037 }
1038
1039 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1040 {
1041 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1042 spr_store_dump_spr(SPR_AMR);
1043 }
1044
1045 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1046 {
1047 TCGv t0 = tcg_temp_new();
1048
1049 gen_load_spr(t0, SPR_UAMOR);
1050 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1051 gen_store_spr(SPR_AMR, t0);
1052 spr_store_dump_spr(SPR_AMR);
1053 }
1054 #endif /* CONFIG_USER_ONLY */
1055
1056 static void gen_spr_amr (CPUPPCState *env)
1057 {
1058 #ifndef CONFIG_USER_ONLY
1059 /* Virtual Page Class Key protection */
1060 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1061 * userspace accessible, 29 is privileged. So we only need to set
1062 * the kvm ONE_REG id on one of them, we use 29 */
1063 spr_register(env, SPR_UAMR, "UAMR",
1064 &spr_read_uamr, &spr_write_uamr_pr,
1065 &spr_read_uamr, &spr_write_uamr,
1066 0);
1067 spr_register_kvm(env, SPR_AMR, "AMR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 KVM_REG_PPC_AMR, 0);
1071 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 KVM_REG_PPC_UAMOR, 0);
1075 #endif /* !CONFIG_USER_ONLY */
1076 }
1077 #endif /* TARGET_PPC64 */
1078
1079 static void gen_spr_thrm (CPUPPCState *env)
1080 {
1081 /* Thermal management */
1082 /* XXX : not implemented */
1083 spr_register(env, SPR_THRM1, "THRM1",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_generic, &spr_write_generic,
1086 0x00000000);
1087 /* XXX : not implemented */
1088 spr_register(env, SPR_THRM2, "THRM2",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_THRM3, "THRM3",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 }
1098
1099 /* SPR specific to PowerPC 604 implementation */
1100 static void gen_spr_604 (CPUPPCState *env)
1101 {
1102 /* Processor identification */
1103 spr_register(env, SPR_PIR, "PIR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_pir,
1106 0x00000000);
1107 /* Breakpoints */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_IABR, "IABR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register_kvm(env, SPR_DABR, "DABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 KVM_REG_PPC_DABR, 0x00000000);
1118 /* Performance counters */
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_MMCR0, "MMCR0",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_PMC1, "PMC1",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_PMC2, "PMC2",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_SIAR, "SIAR",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, SPR_NOACCESS,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_SDA, "SDA",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, SPR_NOACCESS,
1143 0x00000000);
1144 /* External access control */
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_EAR, "EAR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 }
1151
1152 /* SPR specific to PowerPC 603 implementation */
1153 static void gen_spr_603 (CPUPPCState *env)
1154 {
1155 /* External access control */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_EAR, "EAR",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* Breakpoints */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_IABR, "IABR",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167
1168 }
1169
1170 /* SPR specific to PowerPC G2 implementation */
1171 static void gen_spr_G2 (CPUPPCState *env)
1172 {
1173 /* Memory base address */
1174 /* MBAR */
1175 /* XXX : not implemented */
1176 spr_register(env, SPR_MBAR, "MBAR",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180 /* Exception processing */
1181 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* Breakpoints */
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_DABR, "DABR",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_DABR2, "DABR2",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* XXX : not implemented */
1201 spr_register(env, SPR_IABR, "IABR",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_IABR2, "IABR2",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_IBCR, "IBCR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_DBCR, "DBCR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220 }
1221
1222 /* SPR specific to PowerPC 602 implementation */
1223 static void gen_spr_602 (CPUPPCState *env)
1224 {
1225 /* ESA registers */
1226 /* XXX : not implemented */
1227 spr_register(env, SPR_SER, "SER",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_SEBR, "SEBR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* XXX : not implemented */
1237 spr_register(env, SPR_ESASRR, "ESASRR",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_generic,
1240 0x00000000);
1241 /* Floating point status */
1242 /* XXX : not implemented */
1243 spr_register(env, SPR_SP, "SP",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 /* XXX : not implemented */
1248 spr_register(env, SPR_LT, "LT",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 /* Watchdog timer */
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_TCR, "TCR",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 /* Interrupt base */
1259 spr_register(env, SPR_IBR, "IBR",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_IABR, "IABR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 }
1269
1270 /* SPR specific to PowerPC 601 implementation */
1271 static void gen_spr_601 (CPUPPCState *env)
1272 {
1273 /* Multiplication/division register */
1274 /* MQ */
1275 spr_register(env, SPR_MQ, "MQ",
1276 &spr_read_generic, &spr_write_generic,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
1279 /* RTC registers */
1280 spr_register(env, SPR_601_RTCU, "RTCU",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 SPR_NOACCESS, &spr_write_601_rtcu,
1283 0x00000000);
1284 spr_register(env, SPR_601_VRTCU, "RTCU",
1285 &spr_read_601_rtcu, SPR_NOACCESS,
1286 &spr_read_601_rtcu, SPR_NOACCESS,
1287 0x00000000);
1288 spr_register(env, SPR_601_RTCL, "RTCL",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 SPR_NOACCESS, &spr_write_601_rtcl,
1291 0x00000000);
1292 spr_register(env, SPR_601_VRTCL, "RTCL",
1293 &spr_read_601_rtcl, SPR_NOACCESS,
1294 &spr_read_601_rtcl, SPR_NOACCESS,
1295 0x00000000);
1296 /* Timer */
1297 #if 0 /* ? */
1298 spr_register(env, SPR_601_UDECR, "UDECR",
1299 &spr_read_decr, SPR_NOACCESS,
1300 &spr_read_decr, SPR_NOACCESS,
1301 0x00000000);
1302 #endif
1303 /* External access control */
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_EAR, "EAR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Memory management */
1310 #if !defined(CONFIG_USER_ONLY)
1311 spr_register(env, SPR_IBAT0U, "IBAT0U",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_601_ubat, &spr_write_601_ubatu,
1314 0x00000000);
1315 spr_register(env, SPR_IBAT0L, "IBAT0L",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_601_ubat, &spr_write_601_ubatl,
1318 0x00000000);
1319 spr_register(env, SPR_IBAT1U, "IBAT1U",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_601_ubat, &spr_write_601_ubatu,
1322 0x00000000);
1323 spr_register(env, SPR_IBAT1L, "IBAT1L",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_601_ubat, &spr_write_601_ubatl,
1326 0x00000000);
1327 spr_register(env, SPR_IBAT2U, "IBAT2U",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_601_ubat, &spr_write_601_ubatu,
1330 0x00000000);
1331 spr_register(env, SPR_IBAT2L, "IBAT2L",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_601_ubat, &spr_write_601_ubatl,
1334 0x00000000);
1335 spr_register(env, SPR_IBAT3U, "IBAT3U",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_601_ubat, &spr_write_601_ubatu,
1338 0x00000000);
1339 spr_register(env, SPR_IBAT3L, "IBAT3L",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_601_ubat, &spr_write_601_ubatl,
1342 0x00000000);
1343 env->nb_BATs = 4;
1344 #endif
1345 }
1346
1347 static void gen_spr_74xx (CPUPPCState *env)
1348 {
1349 /* Processor identification */
1350 spr_register(env, SPR_PIR, "PIR",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_pir,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_MMCR2, "MMCR2",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_UMMCR2, "UMMCR2",
1361 &spr_read_ureg, SPR_NOACCESS,
1362 &spr_read_ureg, SPR_NOACCESS,
1363 0x00000000);
1364 /* XXX: not implemented */
1365 spr_register(env, SPR_BAMR, "BAMR",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_MSSCR0, "MSSCR0",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* Hardware implementation registers */
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_HID0, "HID0",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_HID1, "HID1",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385 /* Altivec */
1386 spr_register(env, SPR_VRSAVE, "VRSAVE",
1387 &spr_read_generic, &spr_write_generic,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390 /* XXX : not implemented */
1391 spr_register(env, SPR_L2CR, "L2CR",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, spr_access_nop,
1394 0x00000000);
1395 /* Not strictly an SPR */
1396 vscr_init(env, 0x00010000);
1397 }
1398
1399 static void gen_l3_ctrl (CPUPPCState *env)
1400 {
1401 /* L3CR */
1402 /* XXX : not implemented */
1403 spr_register(env, SPR_L3CR, "L3CR",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407 /* L3ITCR0 */
1408 /* XXX : not implemented */
1409 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413 /* L3PM */
1414 /* XXX : not implemented */
1415 spr_register(env, SPR_L3PM, "L3PM",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419 }
1420
1421 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1422 {
1423 #if !defined(CONFIG_USER_ONLY)
1424 env->nb_tlb = nb_tlbs;
1425 env->nb_ways = nb_ways;
1426 env->id_tlbs = 1;
1427 env->tlb_type = TLB_6XX;
1428 /* XXX : not implemented */
1429 spr_register(env, SPR_PTEHI, "PTEHI",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433 /* XXX : not implemented */
1434 spr_register(env, SPR_PTELO, "PTELO",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_TLBMISS, "TLBMISS",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 #endif
1444 }
1445
1446 #if !defined(CONFIG_USER_ONLY)
1447 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1448 {
1449 TCGv t0 = tcg_temp_new();
1450
1451 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1452 gen_store_spr(sprn, t0);
1453 tcg_temp_free(t0);
1454 }
1455
1456 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1457 {
1458 TCGv_i32 t0 = tcg_const_i32(sprn);
1459 gen_helper_booke206_tlbflush(cpu_env, t0);
1460 tcg_temp_free_i32(t0);
1461 }
1462
1463 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1464 {
1465 TCGv_i32 t0 = tcg_const_i32(sprn);
1466 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1467 tcg_temp_free_i32(t0);
1468 }
1469 #endif
1470
1471 static void gen_spr_usprgh (CPUPPCState *env)
1472 {
1473 spr_register(env, SPR_USPRG4, "USPRG4",
1474 &spr_read_ureg, SPR_NOACCESS,
1475 &spr_read_ureg, SPR_NOACCESS,
1476 0x00000000);
1477 spr_register(env, SPR_USPRG5, "USPRG5",
1478 &spr_read_ureg, SPR_NOACCESS,
1479 &spr_read_ureg, SPR_NOACCESS,
1480 0x00000000);
1481 spr_register(env, SPR_USPRG6, "USPRG6",
1482 &spr_read_ureg, SPR_NOACCESS,
1483 &spr_read_ureg, SPR_NOACCESS,
1484 0x00000000);
1485 spr_register(env, SPR_USPRG7, "USPRG7",
1486 &spr_read_ureg, SPR_NOACCESS,
1487 &spr_read_ureg, SPR_NOACCESS,
1488 0x00000000);
1489 }
1490
1491 /* PowerPC BookE SPR */
1492 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1493 {
1494 const char *ivor_names[64] = {
1495 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1496 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1497 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1498 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1499 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1500 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1501 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1502 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1503 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1504 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1505 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1506 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1507 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1508 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1509 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1510 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1511 };
1512 #define SPR_BOOKE_IVORxx (-1)
1513 int ivor_sprn[64] = {
1514 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1515 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1516 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1517 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1518 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1519 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1520 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1521 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1522 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1523 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1524 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1525 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1526 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1527 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1528 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1529 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1530 };
1531 int i;
1532
1533 /* Interrupt processing */
1534 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* Debug */
1543 /* XXX : not implemented */
1544 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 /* XXX : not implemented */
1549 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 /* XXX : not implemented */
1554 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 /* XXX : not implemented */
1559 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 /* XXX : not implemented */
1564 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_40x_dbcr0,
1567 0x00000000);
1568 /* XXX : not implemented */
1569 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_clear,
1582 0x00000000);
1583 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 spr_register(env, SPR_BOOKE_ESR, "ESR",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
1591 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_excp_prefix,
1594 0x00000000);
1595 /* Exception vectors */
1596 for (i = 0; i < 64; i++) {
1597 if (ivor_mask & (1ULL << i)) {
1598 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1599 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1600 exit(1);
1601 }
1602 spr_register(env, ivor_sprn[i], ivor_names[i],
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_excp_vector,
1605 0x00000000);
1606 }
1607 }
1608 spr_register(env, SPR_BOOKE_PID, "PID",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_booke_pid,
1611 0x00000000);
1612 spr_register(env, SPR_BOOKE_TCR, "TCR",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_generic, &spr_write_booke_tcr,
1615 0x00000000);
1616 spr_register(env, SPR_BOOKE_TSR, "TSR",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_booke_tsr,
1619 0x00000000);
1620 /* Timer */
1621 spr_register(env, SPR_DECR, "DECR",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_decr, &spr_write_decr,
1624 0x00000000);
1625 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 SPR_NOACCESS, &spr_write_generic,
1628 0x00000000);
1629 /* SPRGs */
1630 spr_register(env, SPR_USPRG0, "USPRG0",
1631 &spr_read_generic, &spr_write_generic,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 spr_register(env, SPR_SPRG4, "SPRG4",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 spr_register(env, SPR_SPRG5, "SPRG5",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642 spr_register(env, SPR_SPRG6, "SPRG6",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 spr_register(env, SPR_SPRG7, "SPRG7",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650 }
1651
1652 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1653 uint32_t maxsize, uint32_t flags,
1654 uint32_t nentries)
1655 {
1656 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1657 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1658 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1659 flags | nentries;
1660 }
1661
1662 /* BookE 2.06 storage control registers */
1663 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1664 uint32_t *tlbncfg)
1665 {
1666 #if !defined(CONFIG_USER_ONLY)
1667 const char *mas_names[8] = {
1668 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1669 };
1670 int mas_sprn[8] = {
1671 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1672 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1673 };
1674 int i;
1675
1676 /* TLB assist registers */
1677 /* XXX : not implemented */
1678 for (i = 0; i < 8; i++) {
1679 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1680 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1681 uea_write = &spr_write_generic;
1682 }
1683 if (mas_mask & (1 << i)) {
1684 spr_register(env, mas_sprn[i], mas_names[i],
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, uea_write,
1687 0x00000000);
1688 }
1689 }
1690 if (env->nb_pids > 1) {
1691 /* XXX : not implemented */
1692 spr_register(env, SPR_BOOKE_PID1, "PID1",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_booke_pid,
1695 0x00000000);
1696 }
1697 if (env->nb_pids > 2) {
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_BOOKE_PID2, "PID2",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_booke_pid,
1702 0x00000000);
1703 }
1704 /* XXX : not implemented */
1705 spr_register(env, SPR_MMUCFG, "MMUCFG",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, SPR_NOACCESS,
1708 0x00000000); /* TOFIX */
1709 switch (env->nb_ways) {
1710 case 4:
1711 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, SPR_NOACCESS,
1714 tlbncfg[3]);
1715 /* Fallthru */
1716 case 3:
1717 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1718 SPR_NOACCESS, SPR_NOACCESS,
1719 &spr_read_generic, SPR_NOACCESS,
1720 tlbncfg[2]);
1721 /* Fallthru */
1722 case 2:
1723 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, SPR_NOACCESS,
1726 tlbncfg[1]);
1727 /* Fallthru */
1728 case 1:
1729 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, SPR_NOACCESS,
1732 tlbncfg[0]);
1733 /* Fallthru */
1734 case 0:
1735 default:
1736 break;
1737 }
1738 #endif
1739
1740 gen_spr_usprgh(env);
1741 }
1742
1743 /* SPR specific to PowerPC 440 implementation */
1744 static void gen_spr_440 (CPUPPCState *env)
1745 {
1746 /* Cache control */
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_440_DNV0, "DNV0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_DNV1, "DNV1",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_440_DNV2, "DNV2",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_440_DNV3, "DNV3",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_440_DTV0, "DTV0",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_440_DTV1, "DTV1",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_440_DTV2, "DTV2",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* XXX : not implemented */
1783 spr_register(env, SPR_440_DTV3, "DTV3",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 /* XXX : not implemented */
1788 spr_register(env, SPR_440_DVLIM, "DVLIM",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 /* XXX : not implemented */
1793 spr_register(env, SPR_440_INV0, "INV0",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
1797 /* XXX : not implemented */
1798 spr_register(env, SPR_440_INV1, "INV1",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 /* XXX : not implemented */
1803 spr_register(env, SPR_440_INV2, "INV2",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
1807 /* XXX : not implemented */
1808 spr_register(env, SPR_440_INV3, "INV3",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812 /* XXX : not implemented */
1813 spr_register(env, SPR_440_ITV0, "ITV0",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817 /* XXX : not implemented */
1818 spr_register(env, SPR_440_ITV1, "ITV1",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 /* XXX : not implemented */
1823 spr_register(env, SPR_440_ITV2, "ITV2",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 /* XXX : not implemented */
1828 spr_register(env, SPR_440_ITV3, "ITV3",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 /* XXX : not implemented */
1833 spr_register(env, SPR_440_IVLIM, "IVLIM",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 /* Cache debug */
1838 /* XXX : not implemented */
1839 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, SPR_NOACCESS,
1842 0x00000000);
1843 /* XXX : not implemented */
1844 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, SPR_NOACCESS,
1847 0x00000000);
1848 /* XXX : not implemented */
1849 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, SPR_NOACCESS,
1852 0x00000000);
1853 /* XXX : not implemented */
1854 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, SPR_NOACCESS,
1857 0x00000000);
1858 /* XXX : not implemented */
1859 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 &spr_read_generic, SPR_NOACCESS,
1862 0x00000000);
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_440_DBDR, "DBDR",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_generic,
1867 0x00000000);
1868 /* Processor control */
1869 spr_register(env, SPR_4xx_CCR0, "CCR0",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, SPR_NOACCESS,
1876 0x00000000);
1877 /* Storage control */
1878 spr_register(env, SPR_440_MMUCR, "MMUCR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 }
1883
1884 /* SPR shared between PowerPC 40x implementations */
1885 static void gen_spr_40x (CPUPPCState *env)
1886 {
1887 /* Cache */
1888 /* not emulated, as QEMU do not emulate caches */
1889 spr_register(env, SPR_40x_DCCR, "DCCR",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_generic,
1892 0x00000000);
1893 /* not emulated, as QEMU do not emulate caches */
1894 spr_register(env, SPR_40x_ICCR, "ICCR",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* not emulated, as QEMU do not emulate caches */
1899 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, SPR_NOACCESS,
1902 0x00000000);
1903 /* Exception */
1904 spr_register(env, SPR_40x_DEAR, "DEAR",
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 spr_register(env, SPR_40x_ESR, "ESR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 spr_register(env, SPR_40x_EVPR, "EVPR",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_excp_prefix,
1915 0x00000000);
1916 spr_register(env, SPR_40x_SRR2, "SRR2",
1917 &spr_read_generic, &spr_write_generic,
1918 &spr_read_generic, &spr_write_generic,
1919 0x00000000);
1920 spr_register(env, SPR_40x_SRR3, "SRR3",
1921 &spr_read_generic, &spr_write_generic,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* Timers */
1925 spr_register(env, SPR_40x_PIT, "PIT",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_40x_pit, &spr_write_40x_pit,
1928 0x00000000);
1929 spr_register(env, SPR_40x_TCR, "TCR",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_booke_tcr,
1932 0x00000000);
1933 spr_register(env, SPR_40x_TSR, "TSR",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_booke_tsr,
1936 0x00000000);
1937 }
1938
1939 /* SPR specific to PowerPC 405 implementation */
1940 static void gen_spr_405 (CPUPPCState *env)
1941 {
1942 /* MMU */
1943 spr_register(env, SPR_40x_PID, "PID",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 spr_register(env, SPR_4xx_CCR0, "CCR0",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00700000);
1951 /* Debug interface */
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_40x_dbcr0,
1956 0x00000000);
1957 /* XXX : not implemented */
1958 spr_register(env, SPR_405_DBCR1, "DBCR1",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
1962 /* XXX : not implemented */
1963 spr_register(env, SPR_40x_DBSR, "DBSR",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, &spr_write_clear,
1966 /* Last reset was system reset */
1967 0x00000300);
1968 /* XXX : not implemented */
1969 spr_register(env, SPR_40x_DAC1, "DAC1",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, &spr_write_generic,
1972 0x00000000);
1973 spr_register(env, SPR_40x_DAC2, "DAC2",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_generic,
1976 0x00000000);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_405_DVC1, "DVC1",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_405_DVC2, "DVC2",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_IAC1, "IAC1",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 spr_register(env, SPR_40x_IAC2, "IAC2",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_405_IAC3, "IAC3",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* XXX : not implemented */
2002 spr_register(env, SPR_405_IAC4, "IAC4",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 /* Storage control */
2007 /* XXX: TODO: not implemented */
2008 spr_register(env, SPR_405_SLER, "SLER",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_40x_sler,
2011 0x00000000);
2012 spr_register(env, SPR_40x_ZPR, "ZPR",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 /* XXX : not implemented */
2017 spr_register(env, SPR_405_SU0R, "SU0R",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 /* SPRG */
2022 spr_register(env, SPR_USPRG0, "USPRG0",
2023 &spr_read_ureg, SPR_NOACCESS,
2024 &spr_read_ureg, SPR_NOACCESS,
2025 0x00000000);
2026 spr_register(env, SPR_SPRG4, "SPRG4",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 spr_register(env, SPR_SPRG5, "SPRG5",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 spr_register(env, SPR_SPRG6, "SPRG6",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 spr_register(env, SPR_SPRG7, "SPRG7",
2039 SPR_NOACCESS, SPR_NOACCESS,
2040 spr_read_generic, &spr_write_generic,
2041 0x00000000);
2042 gen_spr_usprgh(env);
2043 }
2044
2045 /* SPR shared between PowerPC 401 & 403 implementations */
2046 static void gen_spr_401_403 (CPUPPCState *env)
2047 {
2048 /* Time base */
2049 spr_register(env, SPR_403_VTBL, "TBL",
2050 &spr_read_tbl, SPR_NOACCESS,
2051 &spr_read_tbl, SPR_NOACCESS,
2052 0x00000000);
2053 spr_register(env, SPR_403_TBL, "TBL",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 SPR_NOACCESS, &spr_write_tbl,
2056 0x00000000);
2057 spr_register(env, SPR_403_VTBU, "TBU",
2058 &spr_read_tbu, SPR_NOACCESS,
2059 &spr_read_tbu, SPR_NOACCESS,
2060 0x00000000);
2061 spr_register(env, SPR_403_TBU, "TBU",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 SPR_NOACCESS, &spr_write_tbu,
2064 0x00000000);
2065 /* Debug */
2066 /* not emulated, as QEMU do not emulate caches */
2067 spr_register(env, SPR_403_CDBCR, "CDBCR",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
2071 }
2072
2073 /* SPR specific to PowerPC 401 implementation */
2074 static void gen_spr_401 (CPUPPCState *env)
2075 {
2076 /* Debug interface */
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_40x_DBCR0, "DBCR",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_40x_dbcr0,
2081 0x00000000);
2082 /* XXX : not implemented */
2083 spr_register(env, SPR_40x_DBSR, "DBSR",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_clear,
2086 /* Last reset was system reset */
2087 0x00000300);
2088 /* XXX : not implemented */
2089 spr_register(env, SPR_40x_DAC1, "DAC",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_generic,
2092 0x00000000);
2093 /* XXX : not implemented */
2094 spr_register(env, SPR_40x_IAC1, "IAC",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
2098 /* Storage control */
2099 /* XXX: TODO: not implemented */
2100 spr_register(env, SPR_405_SLER, "SLER",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_40x_sler,
2103 0x00000000);
2104 /* not emulated, as QEMU never does speculative access */
2105 spr_register(env, SPR_40x_SGR, "SGR",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0xFFFFFFFF);
2109 /* not emulated, as QEMU do not emulate caches */
2110 spr_register(env, SPR_40x_DCWR, "DCWR",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
2114 }
2115
2116 static void gen_spr_401x2 (CPUPPCState *env)
2117 {
2118 gen_spr_401(env);
2119 spr_register(env, SPR_40x_PID, "PID",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 spr_register(env, SPR_40x_ZPR, "ZPR",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 }
2128
2129 /* SPR specific to PowerPC 403 implementation */
2130 static void gen_spr_403 (CPUPPCState *env)
2131 {
2132 /* Debug interface */
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_40x_dbcr0,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_40x_DBSR, "DBSR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_clear,
2142 /* Last reset was system reset */
2143 0x00000300);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_40x_DAC1, "DAC1",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_40x_DAC2, "DAC2",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_40x_IAC1, "IAC1",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_40x_IAC2, "IAC2",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 }
2165
2166 static void gen_spr_403_real (CPUPPCState *env)
2167 {
2168 spr_register(env, SPR_403_PBL1, "PBL1",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_403_pbr, &spr_write_403_pbr,
2171 0x00000000);
2172 spr_register(env, SPR_403_PBU1, "PBU1",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_403_pbr, &spr_write_403_pbr,
2175 0x00000000);
2176 spr_register(env, SPR_403_PBL2, "PBL2",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_403_pbr, &spr_write_403_pbr,
2179 0x00000000);
2180 spr_register(env, SPR_403_PBU2, "PBU2",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_403_pbr, &spr_write_403_pbr,
2183 0x00000000);
2184 }
2185
2186 static void gen_spr_403_mmu (CPUPPCState *env)
2187 {
2188 /* MMU */
2189 spr_register(env, SPR_40x_PID, "PID",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 spr_register(env, SPR_40x_ZPR, "ZPR",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 }
2198
2199 /* SPR specific to PowerPC compression coprocessor extension */
2200 static void gen_spr_compress (CPUPPCState *env)
2201 {
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_401_SKR, "SKR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 }
2208
2209 static void gen_spr_5xx_8xx (CPUPPCState *env)
2210 {
2211 /* Exception processing */
2212 spr_register_kvm(env, SPR_DSISR, "DSISR",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 KVM_REG_PPC_DSISR, 0x00000000);
2216 spr_register_kvm(env, SPR_DAR, "DAR",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 KVM_REG_PPC_DAR, 0x00000000);
2220 /* Timer */
2221 spr_register(env, SPR_DECR, "DECR",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_decr, &spr_write_decr,
2224 0x00000000);
2225 /* XXX : not implemented */
2226 spr_register(env, SPR_MPC_EIE, "EIE",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_generic,
2229 0x00000000);
2230 /* XXX : not implemented */
2231 spr_register(env, SPR_MPC_EID, "EID",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0x00000000);
2235 /* XXX : not implemented */
2236 spr_register(env, SPR_MPC_NRI, "NRI",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_MPC_CMPA, "CMPA",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_MPC_CMPB, "CMPB",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_MPC_CMPC, "CMPC",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 /* XXX : not implemented */
2256 spr_register(env, SPR_MPC_CMPD, "CMPD",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_MPC_ECR, "ECR",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* XXX : not implemented */
2266 spr_register(env, SPR_MPC_DER, "DER",
2267 SPR_NOACCESS, SPR_NOACCESS,
2268 &spr_read_generic, &spr_write_generic,
2269 0x00000000);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 /* XXX : not implemented */
2281 spr_register(env, SPR_MPC_CMPE, "CMPE",
2282 SPR_NOACCESS, SPR_NOACCESS,
2283 &spr_read_generic, &spr_write_generic,
2284 0x00000000);
2285 /* XXX : not implemented */
2286 spr_register(env, SPR_MPC_CMPF, "CMPF",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_generic, &spr_write_generic,
2289 0x00000000);
2290 /* XXX : not implemented */
2291 spr_register(env, SPR_MPC_CMPG, "CMPG",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 /* XXX : not implemented */
2296 spr_register(env, SPR_MPC_CMPH, "CMPH",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_generic, &spr_write_generic,
2299 0x00000000);
2300 /* XXX : not implemented */
2301 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 /* XXX : not implemented */
2306 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* XXX : not implemented */
2311 spr_register(env, SPR_MPC_BAR, "BAR",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_generic, &spr_write_generic,
2314 0x00000000);
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_MPC_DPDR, "DPDR",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_generic,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_MPC_IMMR, "IMMR",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325 }
2326
2327 static void gen_spr_5xx (CPUPPCState *env)
2328 {
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 /* XXX : not implemented */
2335 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 0x00000000);
2339 /* XXX : not implemented */
2340 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_generic, &spr_write_generic,
2343 0x00000000);
2344 /* XXX : not implemented */
2345 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2346 SPR_NOACCESS, SPR_NOACCESS,
2347 &spr_read_generic, &spr_write_generic,
2348 0x00000000);
2349 /* XXX : not implemented */
2350 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354 /* XXX : not implemented */
2355 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* XXX : not implemented */
2360 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2361 SPR_NOACCESS, SPR_NOACCESS,
2362 &spr_read_generic, &spr_write_generic,
2363 0x00000000);
2364 /* XXX : not implemented */
2365 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2366 SPR_NOACCESS, SPR_NOACCESS,
2367 &spr_read_generic, &spr_write_generic,
2368 0x00000000);
2369 /* XXX : not implemented */
2370 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374 /* XXX : not implemented */
2375 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 /* XXX : not implemented */
2390 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2391 SPR_NOACCESS, SPR_NOACCESS,
2392 &spr_read_generic, &spr_write_generic,
2393 0x00000000);
2394 /* XXX : not implemented */
2395 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2396 SPR_NOACCESS, SPR_NOACCESS,
2397 &spr_read_generic, &spr_write_generic,
2398 0x00000000);
2399 /* XXX : not implemented */
2400 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2401 SPR_NOACCESS, SPR_NOACCESS,
2402 &spr_read_generic, &spr_write_generic,
2403 0x00000000);
2404 /* XXX : not implemented */
2405 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2406 SPR_NOACCESS, SPR_NOACCESS,
2407 &spr_read_generic, &spr_write_generic,
2408 0x00000000);
2409 /* XXX : not implemented */
2410 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_generic, &spr_write_generic,
2413 0x00000000);
2414 /* XXX : not implemented */
2415 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2416 SPR_NOACCESS, SPR_NOACCESS,
2417 &spr_read_generic, &spr_write_generic,
2418 0x00000000);
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 }
2435
2436 static void gen_spr_8xx (CPUPPCState *env)
2437 {
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458 /* XXX : not implemented */
2459 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2460 SPR_NOACCESS, SPR_NOACCESS,
2461 &spr_read_generic, &spr_write_generic,
2462 0x00000000);
2463 /* XXX : not implemented */
2464 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2465 SPR_NOACCESS, SPR_NOACCESS,
2466 &spr_read_generic, &spr_write_generic,
2467 0x00000000);
2468 /* XXX : not implemented */
2469 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2470 SPR_NOACCESS, SPR_NOACCESS,
2471 &spr_read_generic, &spr_write_generic,
2472 0x00000000);
2473 /* XXX : not implemented */
2474 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2475 SPR_NOACCESS, SPR_NOACCESS,
2476 &spr_read_generic, &spr_write_generic,
2477 0x00000000);
2478 /* XXX : not implemented */
2479 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2480 SPR_NOACCESS, SPR_NOACCESS,
2481 &spr_read_generic, &spr_write_generic,
2482 0x00000000);
2483 /* XXX : not implemented */
2484 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2485 SPR_NOACCESS, SPR_NOACCESS,
2486 &spr_read_generic, &spr_write_generic,
2487 0x00000000);
2488 /* XXX : not implemented */
2489 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2490 SPR_NOACCESS, SPR_NOACCESS,
2491 &spr_read_generic, &spr_write_generic,
2492 0x00000000);
2493 /* XXX : not implemented */
2494 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2495 SPR_NOACCESS, SPR_NOACCESS,
2496 &spr_read_generic, &spr_write_generic,
2497 0x00000000);
2498 /* XXX : not implemented */
2499 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2500 SPR_NOACCESS, SPR_NOACCESS,
2501 &spr_read_generic, &spr_write_generic,
2502 0x00000000);
2503 /* XXX : not implemented */
2504 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2505 SPR_NOACCESS, SPR_NOACCESS,
2506 &spr_read_generic, &spr_write_generic,
2507 0x00000000);
2508 /* XXX : not implemented */
2509 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2510 SPR_NOACCESS, SPR_NOACCESS,
2511 &spr_read_generic, &spr_write_generic,
2512 0x00000000);
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 /* XXX : not implemented */
2519 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2520 SPR_NOACCESS, SPR_NOACCESS,
2521 &spr_read_generic, &spr_write_generic,
2522 0x00000000);
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 }
2564
2565 // XXX: TODO
2566 /*
2567 * AMR => SPR 29 (Power 2.04)
2568 * CTRL => SPR 136 (Power 2.04)
2569 * CTRL => SPR 152 (Power 2.04)
2570 * SCOMC => SPR 276 (64 bits ?)
2571 * SCOMD => SPR 277 (64 bits ?)
2572 * TBU40 => SPR 286 (Power 2.04 hypv)
2573 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2574 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2575 * HDSISR => SPR 306 (Power 2.04 hypv)
2576 * HDAR => SPR 307 (Power 2.04 hypv)
2577 * PURR => SPR 309 (Power 2.04 hypv)
2578 * HDEC => SPR 310 (Power 2.04 hypv)
2579 * HIOR => SPR 311 (hypv)
2580 * RMOR => SPR 312 (970)
2581 * HRMOR => SPR 313 (Power 2.04 hypv)
2582 * HSRR0 => SPR 314 (Power 2.04 hypv)
2583 * HSRR1 => SPR 315 (Power 2.04 hypv)
2584 * LPIDR => SPR 317 (970)
2585 * EPR => SPR 702 (Power 2.04 emb)
2586 * perf => 768-783 (Power 2.04)
2587 * perf => 784-799 (Power 2.04)
2588 * PPR => SPR 896 (Power 2.04)
2589 * EPLC => SPR 947 (Power 2.04 emb)
2590 * EPSC => SPR 948 (Power 2.04 emb)
2591 * DABRX => 1015 (Power 2.04 hypv)
2592 * FPECR => SPR 1022 (?)
2593 * ... and more (thermal management, performance counters, ...)
2594 */
2595
2596 /*****************************************************************************/
2597 /* Exception vectors models */
2598 static void init_excp_4xx_real (CPUPPCState *env)
2599 {
2600 #if !defined(CONFIG_USER_ONLY)
2601 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2602 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2603 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2604 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2605 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2606 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2607 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2608 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2609 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2610 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2611 env->ivor_mask = 0x0000FFF0UL;
2612 env->ivpr_mask = 0xFFFF0000UL;
2613 /* Hardware reset vector */
2614 env->hreset_vector = 0xFFFFFFFCUL;
2615 #endif
2616 }
2617
2618 static void init_excp_4xx_softmmu (CPUPPCState *env)
2619 {
2620 #if !defined(CONFIG_USER_ONLY)
2621 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2622 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2623 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2624 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2625 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2626 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2627 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2628 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2629 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2630 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2631 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2632 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2633 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2634 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2635 env->ivor_mask = 0x0000FFF0UL;
2636 env->ivpr_mask = 0xFFFF0000UL;
2637 /* Hardware reset vector */
2638 env->hreset_vector = 0xFFFFFFFCUL;
2639 #endif
2640 }
2641
2642 static void init_excp_MPC5xx (CPUPPCState *env)
2643 {
2644 #if !defined(CONFIG_USER_ONLY)
2645 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2646 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2647 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2648 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2649 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2650 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2651 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2652 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2653 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2654 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2655 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2656 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2657 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2658 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2659 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2660 env->ivor_mask = 0x0000FFF0UL;
2661 env->ivpr_mask = 0xFFFF0000UL;
2662 /* Hardware reset vector */
2663 env->hreset_vector = 0x00000100UL;
2664 #endif
2665 }
2666
2667 static void init_excp_MPC8xx (CPUPPCState *env)
2668 {
2669 #if !defined(CONFIG_USER_ONLY)
2670 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2671 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2672 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2673 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2674 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2675 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2676 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2677 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2678 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2679 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2680 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2681 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2682 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2683 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2684 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2685 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2686 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2687 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2688 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2689 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2690 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2691 env->ivor_mask = 0x0000FFF0UL;
2692 env->ivpr_mask = 0xFFFF0000UL;
2693 /* Hardware reset vector */
2694 env->hreset_vector = 0x00000100UL;
2695 #endif
2696 }
2697
2698 static void init_excp_G2 (CPUPPCState *env)
2699 {
2700 #if !defined(CONFIG_USER_ONLY)
2701 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2702 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2703 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2704 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2705 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2706 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2707 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2708 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2709 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2710 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2711 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2712 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2713 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2714 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2715 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2716 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2717 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2718 /* Hardware reset vector */
2719 env->hreset_vector = 0x00000100UL;
2720 #endif
2721 }
2722
2723 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2724 {
2725 #if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2727 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2746 env->ivor_mask = 0x0000FFF7UL;
2747 env->ivpr_mask = ivpr_mask;
2748 /* Hardware reset vector */
2749 env->hreset_vector = 0xFFFFFFFCUL;
2750 #endif
2751 }
2752
2753 static void init_excp_BookE (CPUPPCState *env)
2754 {
2755 #if !defined(CONFIG_USER_ONLY)
2756 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2763 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2764 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2765 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2767 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2768 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2769 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2770 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2771 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2772 env->ivor_mask = 0x0000FFE0UL;
2773 env->ivpr_mask = 0xFFFF0000UL;
2774 /* Hardware reset vector */
2775 env->hreset_vector = 0xFFFFFFFCUL;
2776 #endif
2777 }
2778
2779 static void init_excp_601 (CPUPPCState *env)
2780 {
2781 #if !defined(CONFIG_USER_ONLY)
2782 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2783 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2784 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2785 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2786 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2787 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2788 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2789 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2790 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2791 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2792 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2793 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2794 /* Hardware reset vector */
2795 env->hreset_vector = 0x00000100UL;
2796 #endif
2797 }
2798
2799 static void init_excp_602 (CPUPPCState *env)
2800 {
2801 #if !defined(CONFIG_USER_ONLY)
2802 /* XXX: exception prefix has a special behavior on 602 */
2803 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2804 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2805 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2806 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2807 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2808 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2809 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2810 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2811 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2812 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2813 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2814 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2815 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2816 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2817 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2818 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2819 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2820 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2821 /* Hardware reset vector */
2822 env->hreset_vector = 0x00000100UL;
2823 #endif
2824 }
2825
2826 static void init_excp_603 (CPUPPCState *env)
2827 {
2828 #if !defined(CONFIG_USER_ONLY)
2829 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2830 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2831 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2832 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2833 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2834 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2835 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2836 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2837 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2838 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2839 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2840 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2841 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2842 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2843 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2844 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2845 /* Hardware reset vector */
2846 env->hreset_vector = 0x00000100UL;
2847 #endif
2848 }
2849
2850 static void init_excp_604 (CPUPPCState *env)
2851 {
2852 #if !defined(CONFIG_USER_ONLY)
2853 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2861 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2862 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2863 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2864 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2865 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2866 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2867 /* Hardware reset vector */
2868 env->hreset_vector = 0x00000100UL;
2869 #endif
2870 }
2871
2872 static void init_excp_7x0 (CPUPPCState *env)
2873 {
2874 #if !defined(CONFIG_USER_ONLY)
2875 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2883 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2884 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2885 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2886 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2887 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2888 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2889 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2890 /* Hardware reset vector */
2891 env->hreset_vector = 0x00000100UL;
2892 #endif
2893 }
2894
2895 static void init_excp_750cl (CPUPPCState *env)
2896 {
2897 #if !defined(CONFIG_USER_ONLY)
2898 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2899 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2900 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2901 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2902 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2903 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2904 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2905 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2906 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2907 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2908 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2909 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2910 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2911 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2912 /* Hardware reset vector */
2913 env->hreset_vector = 0x00000100UL;
2914 #endif
2915 }
2916
2917 static void init_excp_750cx (CPUPPCState *env)
2918 {
2919 #if !defined(CONFIG_USER_ONLY)
2920 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2921 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2922 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2923 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2924 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2925 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2926 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2927 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2928 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2929 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2930 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2931 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2932 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2933 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2934 /* Hardware reset vector */
2935 env->hreset_vector = 0x00000100UL;
2936 #endif
2937 }
2938
2939 /* XXX: Check if this is correct */
2940 static void init_excp_7x5 (CPUPPCState *env)
2941 {
2942 #if !defined(CONFIG_USER_ONLY)
2943 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2944 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2945 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2946 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2947 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2948 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2949 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2950 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2951 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2955 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2956 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2957 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2958 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2959 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2960 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2961 /* Hardware reset vector */
2962 env->hreset_vector = 0x00000100UL;
2963 #endif
2964 }
2965
2966 static void init_excp_7400 (CPUPPCState *env)
2967 {
2968 #if !defined(CONFIG_USER_ONLY)
2969 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2970 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2971 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2972 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2980 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2981 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2983 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2984 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2985 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2986 /* Hardware reset vector */
2987 env->hreset_vector = 0x00000100UL;
2988 #endif
2989 }
2990
2991 static void init_excp_7450 (CPUPPCState *env)
2992 {
2993 #if !defined(CONFIG_USER_ONLY)
2994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3005 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3006 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3007 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3008 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3009 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3010 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3011 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3012 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3013 /* Hardware reset vector */
3014 env->hreset_vector = 0x00000100UL;
3015 #endif
3016 }
3017
3018 #if defined (TARGET_PPC64)
3019 static void init_excp_970 (CPUPPCState *env)
3020 {
3021 #if !defined(CONFIG_USER_ONLY)
3022 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3023 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3024 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3025 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3026 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3027 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3033 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3034 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3035 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3036 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3037 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3038 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3039 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3040 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3041 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3042 /* Hardware reset vector */
3043 env->hreset_vector = 0x0000000000000100ULL;
3044 #endif
3045 }
3046
3047 static void init_excp_POWER7 (CPUPPCState *env)
3048 {
3049 #if !defined(CONFIG_USER_ONLY)
3050 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3051 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3052 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3053 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3054 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3055 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3056 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3057 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3058 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3059 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3060 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3061 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3062 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3063 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3064 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3065 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3066 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3067 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3068 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3069 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3070 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3071 /* Hardware reset vector */
3072 env->hreset_vector = 0x0000000000000100ULL;
3073 #endif
3074 }
3075 #endif
3076
3077 /*****************************************************************************/
3078 /* Power management enable checks */
3079 static int check_pow_none (CPUPPCState *env)
3080 {
3081 return 0;
3082 }
3083
3084 static int check_pow_nocheck (CPUPPCState *env)
3085 {
3086 return 1;
3087 }
3088
3089 static int check_pow_hid0 (CPUPPCState *env)
3090 {
3091 if (env->spr[SPR_HID0] & 0x00E00000)
3092 return 1;
3093
3094 return 0;
3095 }
3096
3097 static int check_pow_hid0_74xx (CPUPPCState *env)
3098 {
3099 if (env->spr[SPR_HID0] & 0x00600000)
3100 return 1;
3101
3102 return 0;
3103 }
3104
3105 /*****************************************************************************/
3106 /* PowerPC implementations definitions */
3107
3108 #define POWERPC_FAMILY(_name) \
3109 static void \
3110 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3111 \
3112 static const TypeInfo \
3113 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3114 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3115 .parent = TYPE_POWERPC_CPU, \
3116 .abstract = true, \
3117 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3118 }; \
3119 \
3120 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3121 { \
3122 type_register_static( \
3123 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3124 } \
3125 \
3126 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3127 \
3128 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3129
3130 static void init_proc_401 (CPUPPCState *env)
3131 {
3132 gen_spr_40x(env);
3133 gen_spr_401_403(env);
3134 gen_spr_401(env);
3135 init_excp_4xx_real(env);
3136 env->dcache_line_size = 32;
3137 env->icache_line_size = 32;
3138 /* Allocate hardware IRQ controller */
3139 ppc40x_irq_init(env);
3140
3141 SET_FIT_PERIOD(12, 16, 20, 24);
3142 SET_WDT_PERIOD(16, 20, 24, 28);
3143 }
3144
3145 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3146 {
3147 DeviceClass *dc = DEVICE_CLASS(oc);
3148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3149
3150 dc->desc = "PowerPC 401";
3151 pcc->init_proc = init_proc_401;
3152 pcc->check_pow = check_pow_nocheck;
3153 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3154 PPC_WRTEE | PPC_DCR |
3155 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3156 PPC_CACHE_DCBZ |
3157 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3158 PPC_4xx_COMMON | PPC_40x_EXCP;
3159 pcc->msr_mask = (1ull << MSR_KEY) |
3160 (1ull << MSR_POW) |
3161 (1ull << MSR_CE) |
3162 (1ull << MSR_ILE) |
3163 (1ull << MSR_EE) |
3164 (1ull << MSR_PR) |
3165 (1ull << MSR_ME) |
3166 (1ull << MSR_DE) |
3167 (1ull << MSR_LE);
3168 pcc->mmu_model = POWERPC_MMU_REAL;
3169 pcc->excp_model = POWERPC_EXCP_40x;
3170 pcc->bus_model = PPC_FLAGS_INPUT_401;
3171 pcc->bfd_mach = bfd_mach_ppc_403;
3172 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3173 POWERPC_FLAG_BUS_CLK;
3174 }
3175
3176 static void init_proc_401x2 (CPUPPCState *env)
3177 {
3178 gen_spr_40x(env);
3179 gen_spr_401_403(env);
3180 gen_spr_401x2(env);
3181 gen_spr_compress(env);
3182 /* Memory management */
3183 #if !defined(CONFIG_USER_ONLY)
3184 env->nb_tlb = 64;
3185 env->nb_ways = 1;
3186 env->id_tlbs = 0;
3187 env->tlb_type = TLB_EMB;
3188 #endif
3189 init_excp_4xx_softmmu(env);
3190 env->dcache_line_size = 32;
3191 env->icache_line_size = 32;
3192 /* Allocate hardware IRQ controller */
3193 ppc40x_irq_init(env);
3194
3195 SET_FIT_PERIOD(12, 16, 20, 24);
3196 SET_WDT_PERIOD(16, 20, 24, 28);
3197 }
3198
3199 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3200 {
3201 DeviceClass *dc = DEVICE_CLASS(oc);
3202 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3203
3204 dc->desc = "PowerPC 401x2";
3205 pcc->init_proc = init_proc_401x2;
3206 pcc->check_pow = check_pow_nocheck;
3207 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3208 PPC_DCR | PPC_WRTEE |
3209 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3210 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3211 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3212 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3213 PPC_4xx_COMMON | PPC_40x_EXCP;
3214 pcc->msr_mask = (1ull << 20) |
3215 (1ull << MSR_KEY) |
3216 (1ull << MSR_POW) |
3217 (1ull << MSR_CE) |
3218 (1ull << MSR_ILE) |
3219 (1ull << MSR_EE) |
3220 (1ull << MSR_PR) |
3221 (1ull << MSR_ME) |
3222 (1ull << MSR_DE) |
3223 (1ull << MSR_IR) |
3224 (1ull << MSR_DR) |
3225 (1ull << MSR_LE);
3226 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3227 pcc->excp_model = POWERPC_EXCP_40x;
3228 pcc->bus_model = PPC_FLAGS_INPUT_401;
3229 pcc->bfd_mach = bfd_mach_ppc_403;
3230 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3231 POWERPC_FLAG_BUS_CLK;
3232 }
3233
3234 static void init_proc_401x3 (CPUPPCState *env)
3235 {
3236 gen_spr_40x(env);
3237 gen_spr_401_403(env);
3238 gen_spr_401(env);
3239 gen_spr_401x2(env);
3240 gen_spr_compress(env);
3241 init_excp_4xx_softmmu(env);
3242 env->dcache_line_size = 32;
3243 env->icache_line_size = 32;
3244 /* Allocate hardware IRQ controller */
3245 ppc40x_irq_init(env);
3246
3247 SET_FIT_PERIOD(12, 16, 20, 24);
3248 SET_WDT_PERIOD(16, 20, 24, 28);
3249 }
3250
3251 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3252 {
3253 DeviceClass *dc = DEVICE_CLASS(oc);
3254 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3255
3256 dc->desc = "PowerPC 401x3";
3257 pcc->init_proc = init_proc_401x3;
3258 pcc->check_pow = check_pow_nocheck;
3259 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3260 PPC_DCR | PPC_WRTEE |
3261 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3262 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3263 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3264 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3265 PPC_4xx_COMMON | PPC_40x_EXCP;
3266 pcc->msr_mask = (1ull << 20) |
3267 (1ull << MSR_KEY) |
3268 (1ull << MSR_POW) |
3269 (1ull << MSR_CE) |
3270 (1ull << MSR_ILE) |
3271 (1ull << MSR_EE) |
3272 (1ull << MSR_PR) |
3273 (1ull << MSR_ME) |
3274 (1ull << MSR_DWE) |
3275 (1ull << MSR_DE) |
3276 (1ull << MSR_IR) |
3277 (1ull << MSR_DR) |
3278 (1ull << MSR_LE);
3279 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3280 pcc->excp_model = POWERPC_EXCP_40x;
3281 pcc->bus_model = PPC_FLAGS_INPUT_401;
3282 pcc->bfd_mach = bfd_mach_ppc_403;
3283 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3284 POWERPC_FLAG_BUS_CLK;
3285 }
3286
3287 static void init_proc_IOP480 (CPUPPCState *env)
3288 {
3289 gen_spr_40x(env);
3290 gen_spr_401_403(env);
3291 gen_spr_401x2(env);
3292 gen_spr_compress(env);
3293 /* Memory management */
3294 #if !defined(CONFIG_USER_ONLY)
3295 env->nb_tlb = 64;
3296 env->nb_ways = 1;
3297 env->id_tlbs = 0;
3298 env->tlb_type = TLB_EMB;
3299 #endif
3300 init_excp_4xx_softmmu(env);
3301 env->dcache_line_size = 32;
3302 env->icache_line_size = 32;
3303 /* Allocate hardware IRQ controller */
3304 ppc40x_irq_init(env);
3305
3306 SET_FIT_PERIOD(8, 12, 16, 20);
3307 SET_WDT_PERIOD(16, 20, 24, 28);
3308 }
3309
3310 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3311 {
3312 DeviceClass *dc = DEVICE_CLASS(oc);
3313 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3314
3315 dc->desc = "IOP480";
3316 pcc->init_proc = init_proc_IOP480;
3317 pcc->check_pow = check_pow_nocheck;
3318 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3319 PPC_DCR | PPC_WRTEE |
3320 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3321 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3322 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3323 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3324 PPC_4xx_COMMON | PPC_40x_EXCP;
3325 pcc->msr_mask = (1ull << 20) |
3326 (1ull << MSR_KEY) |
3327 (1ull << MSR_POW) |
3328 (1ull << MSR_CE) |
3329 (1ull << MSR_ILE) |
3330 (1ull << MSR_EE) |
3331 (1ull << MSR_PR) |
3332 (1ull << MSR_ME) |
3333 (1ull << MSR_DE) |
3334 (1ull << MSR_IR) |
3335 (1ull << MSR_DR) |
3336 (1ull << MSR_LE);
3337 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3338 pcc->excp_model = POWERPC_EXCP_40x;
3339 pcc->bus_model = PPC_FLAGS_INPUT_401;
3340 pcc->bfd_mach = bfd_mach_ppc_403;
3341 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3342 POWERPC_FLAG_BUS_CLK;
3343 }
3344
3345 static void init_proc_403 (CPUPPCState *env)
3346 {
3347 gen_spr_40x(env);
3348 gen_spr_401_403(env);
3349 gen_spr_403(env);
3350 gen_spr_403_real(env);
3351 init_excp_4xx_real(env);
3352 env->dcache_line_size = 32;
3353 env->icache_line_size = 32;
3354 /* Allocate hardware IRQ controller */
3355 ppc40x_irq_init(env);
3356
3357 SET_FIT_PERIOD(8, 12, 16, 20);
3358 SET_WDT_PERIOD(16, 20, 24, 28);
3359 }
3360
3361 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3362 {
3363 DeviceClass *dc = DEVICE_CLASS(oc);
3364 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3365
3366 dc->desc = "PowerPC 403";
3367 pcc->init_proc = init_proc_403;
3368 pcc->check_pow = check_pow_nocheck;
3369 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3370 PPC_DCR | PPC_WRTEE |
3371 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3372 PPC_CACHE_DCBZ |
3373 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3374 PPC_4xx_COMMON | PPC_40x_EXCP;
3375 pcc->msr_mask = (1ull << MSR_POW) |
3376 (1ull << MSR_CE) |
3377 (1ull << MSR_ILE) |
3378 (1ull << MSR_EE) |
3379 (1ull << MSR_PR) |
3380 (1ull << MSR_ME) |
3381 (1ull << MSR_PE) |
3382 (1ull << MSR_PX) |
3383 (1ull << MSR_LE);
3384 pcc->mmu_model = POWERPC_MMU_REAL;
3385 pcc->excp_model = POWERPC_EXCP_40x;
3386 pcc->bus_model = PPC_FLAGS_INPUT_401;
3387 pcc->bfd_mach = bfd_mach_ppc_403;
3388 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3389 POWERPC_FLAG_BUS_CLK;
3390 }
3391
3392 static void init_proc_403GCX (CPUPPCState *env)
3393 {
3394 gen_spr_40x(env);
3395 gen_spr_401_403(env);
3396 gen_spr_403(env);
3397 gen_spr_403_real(env);
3398 gen_spr_403_mmu(env);
3399 /* Bus access control */
3400 /* not emulated, as QEMU never does speculative access */
3401 spr_register(env, SPR_40x_SGR, "SGR",
3402 SPR_NOACCESS, SPR_NOACCESS,
3403 &spr_read_generic, &spr_write_generic,
3404 0xFFFFFFFF);
3405 /* not emulated, as QEMU do not emulate caches */
3406 spr_register(env, SPR_40x_DCWR, "DCWR",
3407 SPR_NOACCESS, SPR_NOACCESS,
3408 &spr_read_generic, &spr_write_generic,
3409 0x00000000);
3410 /* Memory management */
3411 #if !defined(CONFIG_USER_ONLY)
3412 env->nb_tlb = 64;
3413 env->nb_ways = 1;
3414 env->id_tlbs = 0;
3415 env->tlb_type = TLB_EMB;
3416 #endif
3417 init_excp_4xx_softmmu(env);
3418 env->dcache_line_size = 32;
3419 env->icache_line_size = 32;
3420 /* Allocate hardware IRQ controller */
3421 ppc40x_irq_init(env);
3422
3423 SET_FIT_PERIOD(8, 12, 16, 20);
3424 SET_WDT_PERIOD(16, 20, 24, 28);
3425 }
3426
3427 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3428 {
3429 DeviceClass *dc = DEVICE_CLASS(oc);
3430 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3431
3432 dc->desc = "PowerPC 403 GCX";
3433 pcc->init_proc = init_proc_403GCX;
3434 pcc->check_pow = check_pow_nocheck;
3435 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3436 PPC_DCR | PPC_WRTEE |
3437 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3438 PPC_CACHE_DCBZ |
3439 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3440 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3441 PPC_4xx_COMMON | PPC_40x_EXCP;
3442 pcc->msr_mask = (1ull << MSR_POW) |
3443 (1ull << MSR_CE) |
3444 (1ull << MSR_ILE) |
3445 (1ull << MSR_EE) |
3446 (1ull << MSR_PR) |
3447 (1ull << MSR_ME) |
3448 (1ull << MSR_PE) |
3449 (1ull << MSR_PX) |
3450 (1ull << MSR_LE);
3451 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3452 pcc->excp_model = POWERPC_EXCP_40x;
3453 pcc->bus_model = PPC_FLAGS_INPUT_401;
3454 pcc->bfd_mach = bfd_mach_ppc_403;
3455 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3456 POWERPC_FLAG_BUS_CLK;
3457 }
3458
3459 static void init_proc_405 (CPUPPCState *env)
3460 {
3461 /* Time base */
3462 gen_tbl(env);
3463 gen_spr_40x(env);
3464 gen_spr_405(env);
3465 /* Bus access control */
3466 /* not emulated, as QEMU never does speculative access */
3467 spr_register(env, SPR_40x_SGR, "SGR",
3468 SPR_NOACCESS, SPR_NOACCESS,
3469 &spr_read_generic, &spr_write_generic,
3470 0xFFFFFFFF);
3471 /* not emulated, as QEMU do not emulate caches */
3472 spr_register(env, SPR_40x_DCWR, "DCWR",
3473 SPR_NOACCESS, SPR_NOACCESS,
3474 &spr_read_generic, &spr_write_generic,
3475 0x00000000);
3476 /* Memory management */
3477 #if !defined(CONFIG_USER_ONLY)
3478 env->nb_tlb = 64;
3479 env->nb_ways = 1;
3480 env->id_tlbs = 0;
3481 env->tlb_type = TLB_EMB;
3482 #endif
3483 init_excp_4xx_softmmu(env);
3484 env->dcache_line_size = 32;
3485 env->icache_line_size = 32;
3486 /* Allocate hardware IRQ controller */
3487 ppc40x_irq_init(env);
3488
3489 SET_FIT_PERIOD(8, 12, 16, 20);
3490 SET_WDT_PERIOD(16, 20, 24, 28);
3491 }
3492
3493 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3494 {
3495 DeviceClass *dc = DEVICE_CLASS(oc);
3496 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3497
3498 dc->desc = "PowerPC 405";
3499 pcc->init_proc = init_proc_405;
3500 pcc->check_pow = check_pow_nocheck;
3501 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3502 PPC_DCR | PPC_WRTEE |
3503 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3504 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3505 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3506 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3507 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3508 pcc->msr_mask = (1ull << MSR_POW) |
3509 (1ull << MSR_CE) |
3510 (1ull << MSR_EE) |
3511 (1ull << MSR_PR) |
3512 (1ull << MSR_FP) |
3513 (1ull << MSR_DWE) |
3514 (1ull << MSR_DE) |
3515 (1ull << MSR_IR) |
3516 (1ull << MSR_DR);
3517 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3518 pcc->excp_model = POWERPC_EXCP_40x;
3519 pcc->bus_model = PPC_FLAGS_INPUT_405;
3520 pcc->bfd_mach = bfd_mach_ppc_403;
3521 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3522 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3523 }
3524
3525 static void init_proc_440EP (CPUPPCState *env)
3526 {
3527 /* Time base */
3528 gen_tbl(env);
3529 gen_spr_BookE(env, 0x000000000000FFFFULL);
3530 gen_spr_440(env);
3531 gen_spr_usprgh(env);
3532 /* Processor identification */
3533 spr_register(env, SPR_BOOKE_PIR, "PIR",
3534 SPR_NOACCESS, SPR_NOACCESS,
3535 &spr_read_generic, &spr_write_pir,
3536 0x00000000);
3537 /* XXX : not implemented */
3538 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3539 SPR_NOACCESS, SPR_NOACCESS,
3540 &spr_read_generic, &spr_write_generic,
3541 0x00000000);
3542 /* XXX : not implemented */
3543 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3544 SPR_NOACCESS, SPR_NOACCESS,
3545 &spr_read_generic, &spr_write_generic,
3546 0x00000000);
3547 /* XXX : not implemented */
3548 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3549 SPR_NOACCESS, SPR_NOACCESS,
3550 &spr_read_generic, &spr_write_generic,
3551 0x00000000);
3552 /* XXX : not implemented */
3553 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3554 SPR_NOACCESS, SPR_NOACCESS,
3555 &spr_read_generic, &spr_write_generic,
3556 0x00000000);
3557 /* XXX : not implemented */
3558 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3559 SPR_NOACCESS, SPR_NOACCESS,
3560 &spr_read_generic, &spr_write_generic,
3561 0x00000000);
3562 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3567 SPR_NOACCESS, SPR_NOACCESS,
3568 &spr_read_generic, &spr_write_generic,
3569 0x00000000);
3570 /* XXX : not implemented */
3571 spr_register(env, SPR_440_CCR1, "CCR1",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_generic,
3574 0x00000000);
3575 /* Memory management */
3576 #if !defined(CONFIG_USER_ONLY)
3577 env->nb_tlb = 64;
3578 env->nb_ways = 1;
3579 env->id_tlbs = 0;
3580 env->tlb_type = TLB_EMB;
3581 #endif
3582 init_excp_BookE(env);
3583 env->dcache_line_size = 32;
3584 env->icache_line_size = 32;
3585 ppc40x_irq_init(env);
3586
3587 SET_FIT_PERIOD(12, 16, 20, 24);
3588 SET_WDT_PERIOD(20, 24, 28, 32);
3589 }
3590
3591 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3592 {
3593 DeviceClass *dc = DEVICE_CLASS(oc);
3594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3595
3596 dc->desc = "PowerPC 440 EP";
3597 pcc->init_proc = init_proc_440EP;
3598 pcc->check_pow = check_pow_nocheck;
3599 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3600 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3601 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3602 PPC_FLOAT_STFIWX |
3603 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3604 PPC_CACHE | PPC_CACHE_ICBI |
3605 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3606 PPC_MEM_TLBSYNC | PPC_MFTB |
3607 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3608 PPC_440_SPEC;
3609 pcc->msr_mask = (1ull << MSR_POW) |
3610 (1ull << MSR_CE) |
3611 (1ull << MSR_EE) |
3612 (1ull << MSR_PR) |
3613 (1ull << MSR_FP) |
3614 (1ull << MSR_ME) |
3615 (1ull << MSR_FE0) |
3616 (1ull << MSR_DWE) |
3617 (1ull << MSR_DE) |
3618 (1ull << MSR_FE1) |
3619 (1ull << MSR_IR) |
3620 (1ull << MSR_DR);
3621 pcc->mmu_model = POWERPC_MMU_BOOKE;
3622 pcc->excp_model = POWERPC_EXCP_BOOKE;
3623 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3624 pcc->bfd_mach = bfd_mach_ppc_403;
3625 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3626 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3627 }
3628
3629 static void init_proc_440GP (CPUPPCState *env)
3630 {
3631 /* Time base */
3632 gen_tbl(env);
3633 gen_spr_BookE(env, 0x000000000000FFFFULL);
3634 gen_spr_440(env);
3635 gen_spr_usprgh(env);
3636 /* Processor identification */
3637 spr_register(env, SPR_BOOKE_PIR, "PIR",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_pir,
3640 0x00000000);
3641 /* XXX : not implemented */
3642 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* XXX : not implemented */
3657 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661 /* Memory management */
3662 #if !defined(CONFIG_USER_ONLY)
3663 env->nb_tlb = 64;
3664 env->nb_ways = 1;
3665 env->id_tlbs = 0;
3666 env->tlb_type = TLB_EMB;
3667 #endif
3668 init_excp_BookE(env);
3669 env->dcache_line_size = 32;
3670 env->icache_line_size = 32;
3671 /* XXX: TODO: allocate internal IRQ controller */
3672
3673 SET_FIT_PERIOD(12, 16, 20, 24);
3674 SET_WDT_PERIOD(20, 24, 28, 32);
3675 }
3676
3677 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3678 {
3679 DeviceClass *dc = DEVICE_CLASS(oc);
3680 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3681
3682 dc->desc = "PowerPC 440 GP";
3683 pcc->init_proc = init_proc_440GP;
3684 pcc->check_pow = check_pow_nocheck;
3685 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3686 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3687 PPC_CACHE | PPC_CACHE_ICBI |
3688 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3689 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3690 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3691 PPC_440_SPEC;
3692 pcc->msr_mask = (1ull << MSR_POW) |
3693 (1ull << MSR_CE) |
3694 (1ull << MSR_EE) |
3695 (1ull << MSR_PR) |
3696 (1ull << MSR_FP) |
3697 (1ull << MSR_ME) |
3698 (1ull << MSR_FE0) |
3699 (1ull << MSR_DWE) |
3700 (1ull << MSR_DE) |
3701 (1ull << MSR_FE1) |
3702 (1ull << MSR_IR) |
3703 (1ull << MSR_DR);
3704 pcc->mmu_model = POWERPC_MMU_BOOKE;
3705 pcc->excp_model = POWERPC_EXCP_BOOKE;
3706 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3707 pcc->bfd_mach = bfd_mach_ppc_403;
3708 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3709 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3710 }
3711
3712 static void init_proc_440x4 (CPUPPCState *env)
3713 {
3714 /* Time base */
3715 gen_tbl(env);
3716 gen_spr_BookE(env, 0x000000000000FFFFULL);
3717 gen_spr_440(env);
3718 gen_spr_usprgh(env);
3719 /* Processor identification */
3720 spr_register(env, SPR_BOOKE_PIR, "PIR",
3721 SPR_NOACCESS, SPR_NOACCESS,
3722 &spr_read_generic, &spr_write_pir,
3723 0x00000000);
3724 /* XXX : not implemented */
3725 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3726 SPR_NOACCESS, SPR_NOACCESS,
3727 &spr_read_generic, &spr_write_generic,
3728 0x00000000);
3729 /* XXX : not implemented */
3730 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3731 SPR_NOACCESS, SPR_NOACCESS,
3732 &spr_read_generic, &spr_write_generic,
3733 0x00000000);
3734 /* XXX : not implemented */
3735 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3736 SPR_NOACCESS, SPR_NOACCESS,
3737 &spr_read_generic, &spr_write_generic,
3738 0x00000000);
3739 /* XXX : not implemented */
3740 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3741 SPR_NOACCESS, SPR_NOACCESS,
3742 &spr_read_generic, &spr_write_generic,
3743 0x00000000);
3744 /* Memory management */
3745 #if !defined(CONFIG_USER_ONLY)
3746 env->nb_tlb = 64;
3747 env->nb_ways = 1;
3748 env->id_tlbs = 0;
3749 env->tlb_type = TLB_EMB;
3750 #endif
3751 init_excp_BookE(env);
3752 env->dcache_line_size = 32;
3753 env->icache_line_size = 32;
3754 /* XXX: TODO: allocate internal IRQ controller */
3755
3756 SET_FIT_PERIOD(12, 16, 20, 24);
3757 SET_WDT_PERIOD(20, 24, 28, 32);
3758 }
3759
3760 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3761 {
3762 DeviceClass *dc = DEVICE_CLASS(oc);
3763 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3764
3765 dc->desc = "PowerPC 440x4";
3766 pcc->init_proc = init_proc_440x4;
3767 pcc->check_pow = check_pow_nocheck;
3768 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3769 PPC_DCR | PPC_WRTEE |
3770 PPC_CACHE | PPC_CACHE_ICBI |
3771 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3772 PPC_MEM_TLBSYNC | PPC_MFTB |
3773 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3774 PPC_440_SPEC;
3775 pcc->msr_mask = (1ull << MSR_POW) |
3776 (1ull << MSR_CE) |
3777 (1ull << MSR_EE) |
3778 (1ull << MSR_PR) |
3779 (1ull << MSR_FP) |
3780 (1ull << MSR_ME) |
3781 (1ull << MSR_FE0) |
3782 (1ull << MSR_DWE) |
3783 (1ull << MSR_DE) |
3784 (1ull << MSR_FE1) |
3785 (1ull << MSR_IR) |
3786 (1ull << MSR_DR);
3787 pcc->mmu_model = POWERPC_MMU_BOOKE;
3788 pcc->excp_model = POWERPC_EXCP_BOOKE;
3789 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3790 pcc->bfd_mach = bfd_mach_ppc_403;
3791 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3792 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3793 }
3794
3795 static void init_proc_440x5 (CPUPPCState *env)
3796 {
3797 /* Time base */
3798 gen_tbl(env);
3799 gen_spr_BookE(env, 0x000000000000FFFFULL);
3800 gen_spr_440(env);
3801 gen_spr_usprgh(env);
3802 /* Processor identification */
3803 spr_register(env, SPR_BOOKE_PIR, "PIR",
3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_pir,
3806 0x00000000);
3807 /* XXX : not implemented */
3808 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3809 SPR_NOACCESS, SPR_NOACCESS,
3810 &spr_read_generic, &spr_write_generic,
3811 0x00000000);
3812 /* XXX : not implemented */
3813 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3814 SPR_NOACCESS, SPR_NOACCESS,
3815 &spr_read_generic, &spr_write_generic,
3816 0x00000000);
3817 /* XXX : not implemented */
3818 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
3822 /* XXX : not implemented */
3823 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3824 SPR_NOACCESS, SPR_NOACCESS,
3825 &spr_read_generic, &spr_write_generic,
3826 0x00000000);
3827 /* XXX : not implemented */
3828 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3829 SPR_NOACCESS, SPR_NOACCESS,
3830 &spr_read_generic, &spr_write_generic,
3831 0x00000000);
3832 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3833 SPR_NOACCESS, SPR_NOACCESS,
3834 &spr_read_generic, &spr_write_generic,
3835 0x00000000);
3836 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3837 SPR_NOACCESS, SPR_NOACCESS,
3838 &spr_read_generic, &spr_write_generic,
3839 0x00000000);
3840 /* XXX : not implemented */
3841 spr_register(env, SPR_440_CCR1, "CCR1",
3842 SPR_NOACCESS, SPR_NOACCESS,
3843 &spr_read_generic, &spr_write_generic,
3844 0x00000000);
3845 /* Memory management */
3846 #if !defined(CONFIG_USER_ONLY)
3847 env->nb_tlb = 64;
3848 env->nb_ways = 1;
3849 env->id_tlbs = 0;
3850 env->tlb_type = TLB_EMB;
3851 #endif
3852 init_excp_BookE(env);
3853 env->dcache_line_size = 32;
3854 env->icache_line_size = 32;
3855 ppc40x_irq_init(env);
3856
3857 SET_FIT_PERIOD(12, 16, 20, 24);
3858 SET_WDT_PERIOD(20, 24, 28, 32);
3859 }
3860
3861 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3862 {
3863 DeviceClass *dc = DEVICE_CLASS(oc);
3864 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3865
3866 dc->desc = "PowerPC 440x5";
3867 pcc->init_proc = init_proc_440x5;
3868 pcc->check_pow = check_pow_nocheck;
3869 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3870 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3871 PPC_CACHE | PPC_CACHE_ICBI |
3872 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3873 PPC_MEM_TLBSYNC | PPC_MFTB |
3874 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3875 PPC_440_SPEC;
3876 pcc->msr_mask = (1ull << MSR_POW) |
3877 (1ull << MSR_CE) |
3878 (1ull << MSR_EE) |
3879 (1ull << MSR_PR) |
3880 (1ull << MSR_FP) |
3881 (1ull << MSR_ME) |
3882 (1ull << MSR_FE0) |
3883 (1ull << MSR_DWE) |
3884 (1ull << MSR_DE) |
3885 (1ull << MSR_FE1) |
3886 (1ull << MSR_IR) |
3887 (1ull << MSR_DR);
3888 pcc->mmu_model = POWERPC_MMU_BOOKE;
3889 pcc->excp_model = POWERPC_EXCP_BOOKE;
3890 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3891 pcc->bfd_mach = bfd_mach_ppc_403;
3892 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3893 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3894 }
3895
3896 static void init_proc_460 (CPUPPCState *env)
3897 {
3898 /* Time base */
3899 gen_tbl(env);
3900 gen_spr_BookE(env, 0x000000000000FFFFULL);
3901 gen_spr_440(env);
3902 gen_spr_usprgh(env);
3903 /* Processor identification */
3904 spr_register(env, SPR_BOOKE_PIR, "PIR",
3905 SPR_NOACCESS, SPR_NOACCESS,
3906 &spr_read_generic, &spr_write_pir,
3907 0x00000000);
3908 /* XXX : not implemented */
3909 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3910 SPR_NOACCESS, SPR_NOACCESS,
3911 &spr_read_generic, &spr_write_generic,
3912 0x00000000);
3913 /* XXX : not implemented */
3914 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3915 SPR_NOACCESS, SPR_NOACCESS,
3916 &spr_read_generic, &spr_write_generic,
3917 0x00000000);
3918 /* XXX : not implemented */
3919 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3920 SPR_NOACCESS, SPR_NOACCESS,
3921 &spr_read_generic, &spr_write_generic,
3922 0x00000000);
3923 /* XXX : not implemented */
3924 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3925 SPR_NOACCESS, SPR_NOACCESS,
3926 &spr_read_generic, &spr_write_generic,
3927 0x00000000);
3928 /* XXX : not implemented */
3929 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3930 SPR_NOACCESS, SPR_NOACCESS,
3931 &spr_read_generic, &spr_write_generic,
3932 0x00000000);
3933 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3938 SPR_NOACCESS, SPR_NOACCESS,
3939 &spr_read_generic, &spr_write_generic,
3940 0x00000000);
3941 /* XXX : not implemented */
3942 spr_register(env, SPR_440_CCR1, "CCR1",
3943 SPR_NOACCESS, SPR_NOACCESS,
3944 &spr_read_generic, &spr_write_generic,
3945 0x00000000);
3946 /* XXX : not implemented */
3947 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3948 &spr_read_generic, &spr_write_generic,
3949 &spr_read_generic, &spr_write_generic,
3950 0x00000000);
3951 /* Memory management */
3952 #if !defined(CONFIG_USER_ONLY)
3953 env->nb_tlb = 64;
3954 env->nb_ways = 1;
3955 env->id_tlbs = 0;
3956 env->tlb_type = TLB_EMB;
3957 #endif
3958 init_excp_BookE(env);
3959 env->dcache_line_size = 32;
3960 env->icache_line_size = 32;
3961 /* XXX: TODO: allocate internal IRQ controller */
3962
3963 SET_FIT_PERIOD(12, 16, 20, 24);
3964 SET_WDT_PERIOD(20, 24, 28, 32);
3965 }
3966
3967 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3968 {
3969 DeviceClass *dc = DEVICE_CLASS(oc);
3970 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3971
3972 dc->desc = "PowerPC 460 (guessed)";
3973 pcc->init_proc = init_proc_460;
3974 pcc->check_pow = check_pow_nocheck;
3975 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3976 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3977 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3978 PPC_CACHE | PPC_CACHE_ICBI |
3979 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3980 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3981 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3982 PPC_440_SPEC;
3983 pcc->msr_mask = (1ull << MSR_POW) |
3984 (1ull << MSR_CE) |
3985 (1ull << MSR_EE) |
3986 (1ull << MSR_PR) |
3987 (1ull << MSR_FP) |
3988 (1ull << MSR_ME) |
3989 (1ull << MSR_FE0) |
3990 (1ull << MSR_DWE) |
3991 (1ull << MSR_DE) |
3992 (1ull << MSR_FE1) |
3993 (1ull << MSR_IR) |
3994 (1ull << MSR_DR);
3995 pcc->mmu_model = POWERPC_MMU_BOOKE;
3996 pcc->excp_model = POWERPC_EXCP_BOOKE;
3997 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3998 pcc->bfd_mach = bfd_mach_ppc_403;
3999 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4000 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4001 }
4002
4003 static void init_proc_460F (CPUPPCState *env)
4004 {
4005 /* Time base */
4006 gen_tbl(env);
4007 gen_spr_BookE(env, 0x000000000000FFFFULL);
4008 gen_spr_440(env);
4009 gen_spr_usprgh(env);
4010 /* Processor identification */
4011 spr_register(env, SPR_BOOKE_PIR, "PIR",
4012 SPR_NOACCESS, SPR_NOACCESS,
4013 &spr_read_generic, &spr_write_pir,
4014 0x00000000);
4015 /* XXX : not implemented */
4016 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4017 SPR_NOACCESS, SPR_NOACCESS,
4018 &spr_read_generic, &spr_write_generic,
4019 0x00000000);
4020 /* XXX : not implemented */
4021 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4022 SPR_NOACCESS, SPR_NOACCESS,
4023 &spr_read_generic, &spr_write_generic,
4024 0x00000000);
4025 /* XXX : not implemented */
4026 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4027 SPR_NOACCESS, SPR_NOACCESS,
4028 &spr_read_generic, &spr_write_generic,
4029 0x00000000);
4030 /* XXX : not implemented */
4031 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4032 SPR_NOACCESS, SPR_NOACCESS,
4033 &spr_read_generic, &spr_write_generic,
4034 0x00000000);
4035 /* XXX : not implemented */
4036 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4037 SPR_NOACCESS, SPR_NOACCESS,
4038 &spr_read_generic, &spr_write_generic,
4039 0x00000000);
4040 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4041 SPR_NOACCESS, SPR_NOACCESS,
4042 &spr_read_generic, &spr_write_generic,
4043 0x00000000);
4044 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4045 SPR_NOACCESS, SPR_NOACCESS,
4046 &spr_read_generic, &spr_write_generic,
4047 0x00000000);
4048 /* XXX : not implemented */
4049 spr_register(env, SPR_440_CCR1, "CCR1",
4050 SPR_NOACCESS, SPR_NOACCESS,
4051 &spr_read_generic, &spr_write_generic,
4052 0x00000000);
4053 /* XXX : not implemented */
4054 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4055 &spr_read_generic, &spr_write_generic,
4056 &spr_read_generic, &spr_write_generic,
4057 0x00000000);
4058 /* Memory management */
4059 #if !defined(CONFIG_USER_ONLY)
4060 env->nb_tlb = 64;
4061 env->nb_ways = 1;
4062 env->id_tlbs = 0;
4063 env->tlb_type = TLB_EMB;
4064 #endif
4065 init_excp_BookE(env);
4066 env->dcache_line_size = 32;
4067 env->icache_line_size = 32;
4068 /* XXX: TODO: allocate internal IRQ controller */
4069
4070 SET_FIT_PERIOD(12, 16, 20, 24);
4071 SET_WDT_PERIOD(20, 24, 28, 32);
4072 }
4073
4074 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4075 {
4076 DeviceClass *dc = DEVICE_CLASS(oc);
4077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4078
4079 dc->desc = "PowerPC 460F (guessed)";
4080 pcc->init_proc = init_proc_460F;
4081 pcc->check_pow = check_pow_nocheck;
4082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4083 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4084 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4085 PPC_FLOAT_STFIWX | PPC_MFTB |
4086 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4087 PPC_WRTEE | PPC_MFAPIDI |
4088 PPC_CACHE | PPC_CACHE_ICBI |
4089 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4090 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4091 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4092 PPC_440_SPEC;
4093 pcc->msr_mask = (1ull << MSR_POW) |
4094 (1ull << MSR_CE) |
4095 (1ull << MSR_EE) |
4096 (1ull << MSR_PR) |
4097 (1ull << MSR_FP) |
4098 (1ull << MSR_ME) |
4099 (1ull << MSR_FE0) |
4100 (1ull << MSR_DWE) |
4101 (1ull << MSR_DE) |
4102 (1ull << MSR_FE1) |
4103 (1ull << MSR_IR) |
4104 (1ull << MSR_DR);
4105 pcc->mmu_model = POWERPC_MMU_BOOKE;
4106 pcc->excp_model = POWERPC_EXCP_BOOKE;
4107 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4108 pcc->bfd_mach = bfd_mach_ppc_403;
4109 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4110 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4111 }
4112
4113 static void init_proc_MPC5xx (CPUPPCState *env)
4114 {
4115 /* Time base */
4116 gen_tbl(env);
4117 gen_spr_5xx_8xx(env);
4118 gen_spr_5xx(env);
4119 init_excp_MPC5xx(env);
4120 env->dcache_line_size = 32;
4121 env->icache_line_size = 32;
4122 /* XXX: TODO: allocate internal IRQ controller */
4123 }
4124
4125 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4126 {
4127 DeviceClass *dc = DEVICE_CLASS(oc);
4128 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4129
4130 dc->desc = "Freescale 5xx cores (aka RCPU)";
4131 pcc->init_proc = init_proc_MPC5xx;
4132 pcc->check_pow = check_pow_none;
4133 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4134 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4135 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4136 PPC_MFTB;
4137 pcc->msr_mask = (1ull << MSR_ILE) |
4138 (1ull << MSR_EE) |
4139 (1ull << MSR_PR) |
4140 (1ull << MSR_FP) |
4141 (1ull << MSR_ME) |
4142 (1ull << MSR_FE0) |
4143 (1ull << MSR_SE) |
4144 (1ull << MSR_DE) |
4145 (1ull << MSR_FE1) |
4146 (1ull << MSR_EP) |
4147 (1ull << MSR_RI) |
4148 (1ull << MSR_LE);
4149 pcc->mmu_model = POWERPC_MMU_REAL;
4150 pcc->excp_model = POWERPC_EXCP_603;
4151 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4152 pcc->bfd_mach = bfd_mach_ppc_505;
4153 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4154 POWERPC_FLAG_BUS_CLK;
4155 }
4156
4157 static void init_proc_MPC8xx (CPUPPCState *env)
4158 {
4159 /* Time base */
4160 gen_tbl(env);
4161 gen_spr_5xx_8xx(env);
4162 gen_spr_8xx(env);
4163 init_excp_MPC8xx(env);
4164 env->dcache_line_size = 32;
4165 env->icache_line_size = 32;
4166 /* XXX: TODO: allocate internal IRQ controller */
4167 }
4168
4169 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4170 {
4171 DeviceClass *dc = DEVICE_CLASS(oc);
4172 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4173
4174 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4175 pcc->init_proc = init_proc_MPC8xx;
4176 pcc->check_pow = check_pow_none;
4177 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4178 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4179 PPC_CACHE_ICBI | PPC_MFTB;
4180 pcc->msr_mask = (1ull << MSR_ILE) |
4181 (1ull << MSR_EE) |
4182 (1ull << MSR_PR) |
4183 (1ull << MSR_FP) |
4184 (1ull << MSR_ME) |
4185 (1ull << MSR_SE) |
4186 (1ull << MSR_DE) |
4187 (1ull << MSR_EP) |
4188 (1ull << MSR_IR) |
4189 (1ull << MSR_DR) |
4190 (1ull << MSR_RI) |
4191 (1ull << MSR_LE);
4192 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4193 pcc->excp_model = POWERPC_EXCP_603;
4194 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4195 pcc->bfd_mach = bfd_mach_ppc_860;
4196 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4197 POWERPC_FLAG_BUS_CLK;
4198 }
4199
4200 /* Freescale 82xx cores (aka PowerQUICC-II) */
4201
4202 static void init_proc_G2 (CPUPPCState *env)
4203 {
4204 gen_spr_ne_601(env);
4205 gen_spr_G2_755(env);
4206 gen_spr_G2(env);
4207 /* Time base */
4208 gen_tbl(env);
4209 /* External access control */
4210 /* XXX : not implemented */
4211 spr_register(env, SPR_EAR, "EAR",
4212 SPR_NOACCESS, SPR_NOACCESS,
4213 &spr_read_generic, &spr_write_generic,
4214 0x00000000);
4215 /* Hardware implementation register */
4216 /* XXX : not implemented */
4217 spr_register(env, SPR_HID0, "HID0",
4218 SPR_NOACCESS, SPR_NOACCESS,
4219 &spr_read_generic, &spr_write_generic,
4220 0x00000000);
4221 /* XXX : not implemented */
4222 spr_register(env, SPR_HID1, "HID1",
4223 SPR_NOACCESS, SPR_NOACCESS,
4224 &spr_read_generic, &spr_write_generic,
4225 0x00000000);
4226 /* XXX : not implemented */
4227 spr_register(env, SPR_HID2, "HID2",
4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_generic,
4230 0x00000000);
4231 /* Memory management */
4232 gen_low_BATs(env);
4233 gen_high_BATs(env);
4234 gen_6xx_7xx_soft_tlb(env, 64, 2);
4235 init_excp_G2(env);
4236 env->dcache_line_size = 32;
4237 env->icache_line_size = 32;
4238 /* Allocate hardware IRQ controller */
4239 ppc6xx_irq_init(env);
4240 }
4241
4242 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4243 {
4244 DeviceClass *dc = DEVICE_CLASS(oc);
4245 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4246
4247 dc->desc = "PowerPC G2";
4248 pcc->init_proc = init_proc_G2;
4249 pcc->check_pow = check_pow_hid0;
4250 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4251 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4252 PPC_FLOAT_STFIWX |
4253 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4254 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4255 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4256 PPC_SEGMENT | PPC_EXTERN;
4257 pcc->msr_mask = (1ull << MSR_POW) |
4258 (1ull << MSR_TGPR) |
4259 (1ull << MSR_EE) |
4260 (1ull << MSR_PR) |
4261 (1ull << MSR_FP) |
4262 (1ull << MSR_ME) |
4263 (1ull << MSR_FE0) |
4264 (1ull << MSR_SE) |
4265 (1ull << MSR_DE) |
4266 (1ull << MSR_FE1) |
4267 (1ull << MSR_AL) |
4268 (1ull << MSR_EP) |
4269 (1ull << MSR_IR) |
4270 (1ull << MSR_DR) |
4271 (1ull << MSR_RI);
4272 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4273 pcc->excp_model = POWERPC_EXCP_G2;
4274 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4275 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4276 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4277 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4278 }
4279
4280 static void init_proc_G2LE (CPUPPCState *env)
4281 {
4282 gen_spr_ne_601(env);
4283 gen_spr_G2_755(env);
4284 gen_spr_G2(env);
4285 /* Time base */
4286 gen_tbl(env);
4287 /* External access control */
4288 /* XXX : not implemented */
4289 spr_register(env, SPR_EAR, "EAR",
4290 SPR_NOACCESS, SPR_NOACCESS,
4291 &spr_read_generic, &spr_write_generic,
4292 0x00000000);
4293 /* Hardware implementation register */
4294 /* XXX : not implemented */
4295 spr_register(env, SPR_HID0, "HID0",
4296 SPR_NOACCESS, SPR_NOACCESS,
4297 &spr_read_generic, &spr_write_generic,
4298 0x00000000);
4299 /* XXX : not implemented */
4300 spr_register(env, SPR_HID1, "HID1",
4301 SPR_NOACCESS, SPR_NOACCESS,
4302 &spr_read_generic, &spr_write_generic,
4303 0x00000000);
4304 /* XXX : not implemented */
4305 spr_register(env, SPR_HID2, "HID2",
4306 SPR_NOACCESS, SPR_NOACCESS,
4307 &spr_read_generic, &spr_write_generic,
4308 0x00000000);
4309 /* Breakpoints */
4310 /* XXX : not implemented */
4311 spr_register(env, SPR_DABR, "DABR",
4312 SPR_NOACCESS, SPR_NOACCESS,
4313 &spr_read_generic, &spr_write_generic,
4314 0x00000000);
4315 /* XXX : not implemented */
4316 spr_register(env, SPR_DABR2, "DABR2",
4317 SPR_NOACCESS, SPR_NOACCESS,
4318 &spr_read_generic, &spr_write_generic,
4319 0x00000000);
4320 /* XXX : not implemented */
4321 spr_register(env, SPR_IABR2, "IABR2",
4322 SPR_NOACCESS, SPR_NOACCESS,
4323 &spr_read_generic, &spr_write_generic,
4324 0x00000000);
4325 /* XXX : not implemented */
4326 spr_register(env, SPR_IBCR, "IBCR",
4327 SPR_NOACCESS, SPR_NOACCESS,
4328 &spr_read_generic, &spr_write_generic,
4329 0x00000000);
4330 /* XXX : not implemented */
4331 spr_register(env, SPR_DBCR, "DBCR",
4332 SPR_NOACCESS, SPR_NOACCESS,
4333 &spr_read_generic, &spr_write_generic,
4334 0x00000000);
4335
4336 /* Memory management */
4337 gen_low_BATs(env);
4338 gen_high_BATs(env);
4339 gen_6xx_7xx_soft_tlb(env, 64, 2);
4340 init_excp_G2(env);
4341 env->dcache_line_size = 32;
4342 env->icache_line_size = 32;
4343 /* Allocate hardware IRQ controller */
4344 ppc6xx_irq_init(env);
4345 }
4346
4347 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4348 {
4349 DeviceClass *dc = DEVICE_CLASS(oc);
4350 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4351
4352 dc->desc = "PowerPC G2LE";
4353 pcc->init_proc = init_proc_G2LE;
4354 pcc->check_pow = check_pow_hid0;
4355 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4356 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4357 PPC_FLOAT_STFIWX |
4358 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4359 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4360 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4361 PPC_SEGMENT | PPC_EXTERN;
4362 pcc->msr_mask = (1ull << MSR_POW) |
4363 (1ull << MSR_TGPR) |
4364 (1ull << MSR_ILE) |
4365 (1ull << MSR_EE) |
4366 (1ull << MSR_PR) |
4367 (1ull << MSR_FP) |
4368 (1ull << MSR_ME) |
4369 (1ull << MSR_FE0) |
4370 (1ull << MSR_SE) |
4371 (1ull << MSR_DE) |
4372 (1ull << MSR_FE1) |
4373 (1ull << MSR_AL) |
4374 (1ull << MSR_EP) |
4375 (1ull << MSR_IR) |
4376 (1ull << MSR_DR) |
4377 (1ull << MSR_RI) |
4378 (1ull << MSR_LE);
4379 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4380 pcc->excp_model = POWERPC_EXCP_G2;
4381 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4382 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4383 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4384 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4385 }
4386
4387 static void init_proc_e200 (CPUPPCState *env)
4388 {
4389 /* Time base */
4390 gen_tbl(env);
4391 gen_spr_BookE(env, 0x000000070000FFFFULL);
4392 /* XXX : not implemented */
4393 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4394 &spr_read_spefscr, &spr_write_spefscr,
4395 &spr_read_spefscr, &spr_write_spefscr,
4396 0x00000000);
4397 /* Memory management */
4398 gen_spr_BookE206(env, 0x0000005D, NULL);
4399 /* XXX : not implemented */
4400 spr_register(env, SPR_HID0, "HID0",
4401 SPR_NOACCESS, SPR_NOACCESS,
4402 &spr_read_generic, &spr_write_generic,
4403 0x00000000);
4404 /* XXX : not implemented */
4405 spr_register(env, SPR_HID1, "HID1",
4406 SPR_NOACCESS, SPR_NOACCESS,
4407 &spr_read_generic, &spr_write_generic,
4408 0x00000000);
4409 /* XXX : not implemented */
4410 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4411 SPR_NOACCESS, SPR_NOACCESS,
4412 &spr_read_generic, &spr_write_generic,
4413 0x00000000);
4414 /* XXX : not implemented */
4415 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4416 SPR_NOACCESS, SPR_NOACCESS,
4417 &spr_read_generic, &spr_write_generic,
4418 0x00000000);
4419 /* XXX : not implemented */
4420 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4421 SPR_NOACCESS, SPR_NOACCESS,
4422 &spr_read_generic, &spr_write_generic,
4423 0x00000000);
4424 /* XXX : not implemented */
4425 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4426 SPR_NOACCESS, SPR_NOACCESS,
4427 &spr_read_generic, &spr_write_generic,
4428 0x00000000);
4429 /* XXX : not implemented */
4430 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4431 SPR_NOACCESS, SPR_NOACCESS,
4432 &spr_read_generic, &spr_write_generic,
4433 0x00000000);
4434 /* XXX : not implemented */
4435 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4436 &spr_read_generic, SPR_NOACCESS,
4437 &spr_read_generic, SPR_NOACCESS,
4438 0x00000000);
4439 /* XXX : not implemented */
4440 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4441 SPR_NOACCESS, SPR_NOACCESS,
4442 &spr_read_generic, &spr_write_generic,
4443 0x00000000);
4444 /* XXX : not implemented */
4445 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4446 SPR_NOACCESS, SPR_NOACCESS,
4447 &spr_read_generic, &spr_write_generic,
4448 0x00000000);
4449 /* XXX : not implemented */
4450 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4451 SPR_NOACCESS, SPR_NOACCESS,
4452 &spr_read_generic, &spr_write_generic,
4453 0x00000000);
4454 /* XXX : not implemented */
4455 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4456 SPR_NOACCESS, SPR_NOACCESS,
4457 &spr_read_generic, &spr_write_generic,
4458 0x00000000);
4459 /* XXX : not implemented */
4460 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4461 SPR_NOACCESS, SPR_NOACCESS,
4462 &spr_read_generic, &spr_write_generic,
4463 0x00000000);
4464 /* XXX : not implemented */
4465 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4466 SPR_NOACCESS, SPR_NOACCESS,
4467 &spr_read_generic, &spr_write_generic,
4468 0x00000000);
4469 /* XXX : not implemented */
4470 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4471 SPR_NOACCESS, SPR_NOACCESS,
4472 &spr_read_generic, &spr_write_generic,
4473 0x00000000); /* TOFIX */
4474 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4475 SPR_NOACCESS, SPR_NOACCESS,
4476 &spr_read_generic, &spr_write_generic,
4477 0x00000000);
4478 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4479 SPR_NOACCESS, SPR_NOACCESS,
4480 &spr_read_generic, &spr_write_generic,
4481 0x00000000);
4482 #if !defined(CONFIG_USER_ONLY)
4483 env->nb_tlb = 64;
4484 env->nb_ways = 1;
4485 env->id_tlbs = 0;
4486 env->tlb_type = TLB_EMB;
4487 #endif
4488 init_excp_e200(env, 0xFFFF0000UL);
4489 env->dcache_line_size = 32;
4490 env->icache_line_size = 32;
4491 /* XXX: TODO: allocate internal IRQ controller */
4492 }
4493
4494 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4495 {
4496 DeviceClass *dc = DEVICE_CLASS(oc);
4497 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4498
4499 dc->desc = "e200 core";
4500 pcc->init_proc = init_proc_e200;
4501 pcc->check_pow = check_pow_hid0;
4502 /* XXX: unimplemented instructions:
4503 * dcblc
4504 * dcbtlst
4505 * dcbtstls
4506 * icblc
4507 * icbtls
4508 * tlbivax
4509 * all SPE multiply-accumulate instructions
4510 */
4511 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4512 PPC_SPE | PPC_SPE_SINGLE |
4513 PPC_WRTEE | PPC_RFDI |
4514 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4515 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4516 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4517 PPC_BOOKE;
4518 pcc->msr_mask = (1ull << MSR_UCLE) |
4519 (1ull << MSR_SPE) |
4520 (1ull << MSR_POW) |
4521 (1ull << MSR_CE) |
4522 (1ull << MSR_EE) |
4523 (1ull << MSR_PR) |
4524 (1ull << MSR_FP) |
4525 (1ull << MSR_ME) |
4526 (1ull << MSR_FE0) |
4527 (1ull << MSR_DWE) |
4528 (1ull << MSR_DE) |
4529 (1ull << MSR_FE1) |
4530 (1ull << MSR_IR) |
4531 (1ull << MSR_DR);
4532 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4533 pcc->excp_model = POWERPC_EXCP_BOOKE;
4534 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4535 pcc->bfd_mach = bfd_mach_ppc_860;
4536 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4537 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4538 POWERPC_FLAG_BUS_CLK;
4539 }
4540
4541 static void init_proc_e300 (CPUPPCState *env)
4542 {
4543 gen_spr_ne_601(env);
4544 gen_spr_603(env);
4545 /* Time base */
4546 gen_tbl(env);
4547 /* hardware implementation registers */
4548 /* XXX : not implemented */
4549 spr_register(env, SPR_HID0, "HID0",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 0x00000000);
4553 /* XXX : not implemented */
4554 spr_register(env, SPR_HID1, "HID1",
4555 SPR_NOACCESS, SPR_NOACCESS,
4556 &spr_read_generic, &spr_write_generic,
4557 0x00000000);
4558 /* XXX : not implemented */
4559 spr_register(env, SPR_HID2, "HID2",
4560 SPR_NOACCESS, SPR_NOACCESS,
4561 &spr_read_generic, &spr_write_generic,
4562 0x00000000);
4563 /* Memory management */
4564 gen_low_BATs(env);
4565 gen_high_BATs(env);
4566 gen_6xx_7xx_soft_tlb(env, 64, 2);
4567 init_excp_603(env);
4568 env->dcache_line_size = 32;
4569 env->icache_line_size = 32;
4570 /* Allocate hardware IRQ controller */
4571 ppc6xx_irq_init(env);
4572 }
4573
4574 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4575 {
4576 DeviceClass *dc = DEVICE_CLASS(oc);
4577 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4578
4579 dc->desc = "e300 core";
4580 pcc->init_proc = init_proc_e300;
4581 pcc->check_pow = check_pow_hid0;
4582 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4583 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4584 PPC_FLOAT_STFIWX |
4585 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4586 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4587 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4588 PPC_SEGMENT | PPC_EXTERN;
4589 pcc->msr_mask = (1ull << MSR_POW) |
4590 (1ull << MSR_TGPR) |
4591 (1ull << MSR_ILE) |
4592 (1ull << MSR_EE) |
4593 (1ull << MSR_PR) |
4594 (1ull << MSR_FP) |
4595 (1ull << MSR_ME) |
4596 (1ull << MSR_FE0) |
4597 (1ull << MSR_SE) |
4598 (1ull << MSR_DE) |
4599 (1ull << MSR_FE1) |
4600 (1ull << MSR_AL) |
4601 (1ull << MSR_EP) |
4602 (1ull << MSR_IR) |
4603 (1ull << MSR_DR) |
4604 (1ull << MSR_RI) |
4605 (1ull << MSR_LE);
4606 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4607 pcc->excp_model = POWERPC_EXCP_603;
4608 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4609 pcc->bfd_mach = bfd_mach_ppc_603;
4610 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4611 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4612 }
4613
4614 #if !defined(CONFIG_USER_ONLY)
4615 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4616 {
4617 TCGv val = tcg_temp_new();
4618 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4619 gen_store_spr(SPR_BOOKE_MAS3, val);
4620 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4621 gen_store_spr(SPR_BOOKE_MAS7, val);
4622 tcg_temp_free(val);
4623 }
4624
4625 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4626 {
4627 TCGv mas7 = tcg_temp_new();
4628 TCGv mas3 = tcg_temp_new();
4629 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4630 tcg_gen_shli_tl(mas7, mas7, 32);
4631 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4632 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4633 tcg_temp_free(mas3);
4634 tcg_temp_free(mas7);
4635 }
4636
4637 #endif
4638
4639 enum fsl_e500_version {
4640 fsl_e500v1,
4641 fsl_e500v2,
4642 fsl_e500mc,
4643 fsl_e5500,
4644 };
4645
4646 static void init_proc_e500 (CPUPPCState *env, int version)
4647 {
4648 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4649 uint32_t tlbncfg[2];
4650 uint64_t ivor_mask;
4651 uint64_t ivpr_mask = 0xFFFF0000ULL;
4652 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4653 | 0x0020; /* 32 kb */
4654 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4655 | 0x0020; /* 32 kb */
4656 #if !defined(CONFIG_USER_ONLY)
4657 int i;
4658 #endif
4659
4660 /* Time base */
4661 gen_tbl(env);
4662 /*
4663 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4664 * complain when accessing them.
4665 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4666 */
4667 switch (version) {
4668 case fsl_e500v1:
4669 case fsl_e500v2:
4670 default:
4671 ivor_mask = 0x0000000F0000FFFFULL;
4672 break;
4673 case fsl_e500mc:
4674 case fsl_e5500:
4675 ivor_mask = 0x000003FE0000FFFFULL;
4676 break;
4677 }
4678 gen_spr_BookE(env, ivor_mask);
4679 /* Processor identification */
4680 spr_register(env, SPR_BOOKE_PIR, "PIR",
4681 SPR_NOACCESS, SPR_NOACCESS,
4682 &spr_read_generic, &spr_write_pir,
4683 0x00000000);
4684 /* XXX : not implemented */
4685 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4686 &spr_read_spefscr, &spr_write_spefscr,
4687 &spr_read_spefscr, &spr_write_spefscr,
4688 0x00000000);
4689 #if !defined(CONFIG_USER_ONLY)
4690 /* Memory management */
4691 env->nb_pids = 3;
4692 env->nb_ways = 2;
4693 env->id_tlbs = 0;
4694 switch (version) {
4695 case fsl_e500v1:
4696 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4697 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4698 break;
4699 case fsl_e500v2:
4700 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4701 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4702 break;
4703 case fsl_e500mc:
4704 case fsl_e5500:
4705 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4706 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4707 break;
4708 default:
4709 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4710 }
4711 #endif
4712 /* Cache sizes */
4713 switch (version) {
4714 case fsl_e500v1:
4715 case fsl_e500v2:
4716 env->dcache_line_size = 32;
4717 env->icache_line_size = 32;
4718 break;
4719 case fsl_e500mc:
4720 case fsl_e5500:
4721 env->dcache_line_size = 64;
4722 env->icache_line_size = 64;
4723 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4724 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4725 break;
4726 default:
4727 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4728 }
4729 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4730 /* XXX : not implemented */
4731 spr_register(env, SPR_HID0, "HID0",
4732 SPR_NOACCESS, SPR_NOACCESS,
4733 &spr_read_generic, &spr_write_generic,
4734 0x00000000);
4735 /* XXX : not implemented */
4736 spr_register(env, SPR_HID1, "HID1",
4737 SPR_NOACCESS, SPR_NOACCESS,
4738 &spr_read_generic, &spr_write_generic,
4739 0x00000000);
4740 /* XXX : not implemented */
4741 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4742 SPR_NOACCESS, SPR_NOACCESS,
4743 &spr_read_generic, &spr_write_generic,
4744 0x00000000);
4745 /* XXX : not implemented */
4746 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4747 SPR_NOACCESS, SPR_NOACCESS,
4748 &spr_read_generic, &spr_write_generic,
4749 0x00000000);
4750 /* XXX : not implemented */
4751 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4752 SPR_NOACCESS, SPR_NOACCESS,
4753 &spr_read_generic, &spr_write_generic,
4754 0x00000000);
4755 /* XXX : not implemented */
4756 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4757 SPR_NOACCESS, SPR_NOACCESS,
4758 &spr_read_generic, &spr_write_generic,
4759 0x00000000);
4760 /* XXX : not implemented */
4761 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4762 SPR_NOACCESS, SPR_NOACCESS,
4763 &spr_read_generic, &spr_write_generic,
4764 0x00000000);
4765 /* XXX : not implemented */
4766 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4767 SPR_NOACCESS, SPR_NOACCESS,
4768 &spr_read_generic, &spr_write_generic,
4769 0x00000000);
4770 /* XXX : not implemented */
4771 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4772 &spr_read_generic, SPR_NOACCESS,
4773 &spr_read_generic, SPR_NOACCESS,
4774 l1cfg0);
4775 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4776 &spr_read_generic, SPR_NOACCESS,
4777 &spr_read_generic, SPR_NOACCESS,
4778 l1cfg1);
4779 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4780 SPR_NOACCESS, SPR_NOACCESS,
4781 &spr_read_generic, &spr_write_e500_l1csr0,
4782 0x00000000);
4783 /* XXX : not implemented */
4784 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4785 SPR_NOACCESS, SPR_NOACCESS,
4786 &spr_read_generic, &spr_write_generic,
4787 0x00000000);
4788 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4789 SPR_NOACCESS, SPR_NOACCESS,
4790 &spr_read_generic, &spr_write_generic,
4791 0x00000000);
4792 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_generic,
4795 0x00000000);
4796 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_booke206_mmucsr0,
4799 0x00000000);
4800 spr_register(env, SPR_BOOKE_EPR, "EPR",
4801 SPR_NOACCESS, SPR_NOACCESS,
4802 &spr_read_generic, SPR_NOACCESS,
4803 0x00000000);
4804 /* XXX better abstract into Emb.xxx features */
4805 if (version == fsl_e5500) {
4806 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4807 SPR_NOACCESS, SPR_NOACCESS,
4808 &spr_read_generic, &spr_write_generic,
4809 0x00000000);
4810 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4811 SPR_NOACCESS, SPR_NOACCESS,
4812 &spr_read_mas73, &spr_write_mas73,
4813 0x00000000);
4814 ivpr_mask = (target_ulong)~0xFFFFULL;
4815 }
4816
4817 #if !defined(CONFIG_USER_ONLY)
4818 env->nb_tlb = 0;
4819 env->tlb_type = TLB_MAS;
4820 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4821 env->nb_tlb += booke206_tlb_size(env, i);
4822 }
4823 #endif
4824
4825 init_excp_e200(env, ivpr_mask);
4826 /* Allocate hardware IRQ controller */
4827 ppce500_irq_init(env);
4828 }
4829
4830 static void init_proc_e500v1(CPUPPCState *env)
4831 {
4832 init_proc_e500(env, fsl_e500v1);
4833 }
4834
4835 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4836 {
4837 DeviceClass *dc = DEVICE_CLASS(oc);
4838 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4839
4840 dc->desc = "e500v1 core";
4841 pcc->init_proc = init_proc_e500v1;
4842 pcc->check_pow = check_pow_hid0;
4843 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4844 PPC_SPE | PPC_SPE_SINGLE |
4845 PPC_WRTEE | PPC_RFDI |
4846 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4847 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4848 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4849 pcc->insns_flags2 = PPC2_BOOKE206;
4850 pcc->msr_mask = (1ull << MSR_UCLE) |
4851 (1ull << MSR_SPE) |
4852 (1ull << MSR_POW) |
4853 (1ull << MSR_CE) |
4854 (1ull << MSR_EE) |
4855 (1ull << MSR_PR) |
4856 (1ull << MSR_FP) |
4857 (1ull << MSR_ME) |
4858 (1ull << MSR_FE0) |
4859 (1ull << MSR_DWE) |
4860 (1ull << MSR_DE) |
4861 (1ull << MSR_FE1) |
4862 (1ull << MSR_IR) |
4863 (1ull << MSR_DR);
4864 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4865 pcc->excp_model = POWERPC_EXCP_BOOKE;
4866 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4867 pcc->bfd_mach = bfd_mach_ppc_860;
4868 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4869 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4870 POWERPC_FLAG_BUS_CLK;
4871 }
4872
4873 static void init_proc_e500v2(CPUPPCState *env)
4874 {
4875 init_proc_e500(env, fsl_e500v2);
4876 }
4877
4878 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4879 {
4880 DeviceClass *dc = DEVICE_CLASS(oc);
4881 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4882
4883 dc->desc = "e500v2 core";
4884 pcc->init_proc = init_proc_e500v2;
4885 pcc->check_pow = check_pow_hid0;
4886 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4887 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4888 PPC_WRTEE | PPC_RFDI |
4889 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4890 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4891 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4892 pcc->insns_flags2 = PPC2_BOOKE206;
4893 pcc->msr_mask = (1ull << MSR_UCLE) |
4894 (1ull << MSR_SPE) |
4895 (1ull << MSR_POW) |
4896 (1ull << MSR_CE) |
4897 (1ull << MSR_EE) |
4898 (1ull << MSR_PR) |
4899 (1ull << MSR_FP) |
4900 (1ull << MSR_ME) |
4901 (1ull << MSR_FE0) |
4902 (1ull << MSR_DWE) |
4903 (1ull << MSR_DE) |
4904 (1ull << MSR_FE1) |
4905 (1ull << MSR_IR) |
4906 (1ull << MSR_DR);
4907 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4908 pcc->excp_model = POWERPC_EXCP_BOOKE;
4909 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4910 pcc->bfd_mach = bfd_mach_ppc_860;
4911 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4912 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4913 POWERPC_FLAG_BUS_CLK;
4914 }
4915
4916 static void init_proc_e500mc(CPUPPCState *env)
4917 {
4918 init_proc_e500(env, fsl_e500mc);
4919 }
4920
4921 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4922 {
4923 DeviceClass *dc = DEVICE_CLASS(oc);
4924 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4925
4926 dc->desc = "e500mc core";
4927 pcc->init_proc = init_proc_e500mc;
4928 pcc->check_pow = check_pow_none;
4929 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4930 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4931 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4932 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4933 PPC_FLOAT | PPC_FLOAT_FRES |
4934 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4935 PPC_FLOAT_STFIWX | PPC_WAIT |
4936 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4937 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4938 pcc->msr_mask = (1ull << MSR_GS) |
4939 (1ull << MSR_UCLE) |
4940 (1ull << MSR_CE) |
4941 (1ull << MSR_EE) |
4942 (1ull << MSR_PR) |
4943 (1ull << MSR_FP) |
4944 (1ull << MSR_ME) |
4945 (1ull << MSR_FE0) |
4946 (1ull << MSR_DE) |
4947 (1ull << MSR_FE1) |
4948 (1ull << MSR_IR) |
4949 (1ull << MSR_DR) |
4950 (1ull << MSR_PX) |
4951 (1ull << MSR_RI);
4952 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4953 pcc->excp_model = POWERPC_EXCP_BOOKE;
4954 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4955 /* FIXME: figure out the correct flag for e500mc */
4956 pcc->bfd_mach = bfd_mach_ppc_e500;
4957 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4958 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4959 }
4960
4961 #ifdef TARGET_PPC64
4962 static void init_proc_e5500(CPUPPCState *env)
4963 {
4964 init_proc_e500(env, fsl_e5500);
4965 }
4966
4967 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4968 {
4969 DeviceClass *dc = DEVICE_CLASS(oc);
4970 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4971
4972 dc->desc = "e5500 core";
4973 pcc->init_proc = init_proc_e5500;
4974 pcc->check_pow = check_pow_none;
4975 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4976 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4977 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4978 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4979 PPC_FLOAT | PPC_FLOAT_FRES |
4980 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4981 PPC_FLOAT_STFIWX | PPC_WAIT |
4982 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4983 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4984 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206;
4985 pcc->msr_mask = (1ull << MSR_CM) |
4986 (1ull << MSR_GS) |
4987 (1ull << MSR_UCLE) |
4988 (1ull << MSR_CE) |
4989 (1ull << MSR_EE) |
4990 (1ull << MSR_PR) |
4991 (1ull << MSR_FP) |
4992 (1ull << MSR_ME) |
4993 (1ull << MSR_FE0) |
4994 (1ull << MSR_DE) |
4995 (1ull << MSR_FE1) |
4996 (1ull << MSR_IR) |
4997 (1ull << MSR_DR) |
4998 (1ull << MSR_PX) |
4999 (1ull << MSR_RI);
5000 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5001 pcc->excp_model = POWERPC_EXCP_BOOKE;
5002 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5003 /* FIXME: figure out the correct flag for e5500 */
5004 pcc->bfd_mach = bfd_mach_ppc_e500;
5005 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5006 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5007 }
5008 #endif
5009
5010 /* Non-embedded PowerPC */
5011
5012 /* POWER : same as 601, without mfmsr, mfsr */
5013 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5014 {
5015 DeviceClass *dc = DEVICE_CLASS(oc);
5016 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5017
5018 dc->desc = "POWER";
5019 /* pcc->insns_flags = XXX_TODO; */
5020 /* POWER RSC (from RAD6000) */
5021 pcc->msr_mask = (1ull << MSR_EE) |
5022 (1ull << MSR_PR) |
5023 (1ull << MSR_FP) |
5024 (1ull << MSR_ME) |
5025 (1ull << MSR_FE0) |
5026 (1ull << MSR_SE) |
5027 (1ull << MSR_DE) |
5028 (1ull << MSR_AL) |
5029 (1ull << MSR_EP) |
5030 (1ull << MSR_IR) |
5031 (1ull << MSR_DR);
5032 }
5033
5034 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5035
5036 static void init_proc_601 (CPUPPCState *env)
5037 {
5038 gen_spr_ne_601(env);
5039 gen_spr_601(env);
5040 /* Hardware implementation registers */
5041 /* XXX : not implemented */
5042 spr_register(env, SPR_HID0, "HID0",
5043 SPR_NOACCESS, SPR_NOACCESS,
5044 &spr_read_generic, &spr_write_hid0_601,
5045 0x80010080);
5046 /* XXX : not implemented */
5047 spr_register(env, SPR_HID1, "HID1",
5048 SPR_NOACCESS, SPR_NOACCESS,
5049 &spr_read_generic, &spr_write_generic,
5050 0x00000000);
5051 /* XXX : not implemented */
5052 spr_register(env, SPR_601_HID2, "HID2",
5053 SPR_NOACCESS, SPR_NOACCESS,
5054 &spr_read_generic, &spr_write_generic,
5055 0x00000000);
5056 /* XXX : not implemented */
5057 spr_register(env, SPR_601_HID5, "HID5",
5058 SPR_NOACCESS, SPR_NOACCESS,
5059 &spr_read_generic, &spr_write_generic,
5060 0x00000000);
5061 /* Memory management */
5062 init_excp_601(env);
5063 /* XXX: beware that dcache line size is 64
5064 * but dcbz uses 32 bytes "sectors"
5065 * XXX: this breaks clcs instruction !
5066 */
5067 env->dcache_line_size = 32;
5068 env->icache_line_size = 64;
5069 /* Allocate hardware IRQ controller */
5070 ppc6xx_irq_init(env);
5071 }
5072
5073 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5074 {
5075 DeviceClass *dc = DEVICE_CLASS(oc);
5076 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5077
5078 dc->desc = "PowerPC 601";
5079 pcc->init_proc = init_proc_601;
5080 pcc->check_pow = check_pow_none;
5081 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5082 PPC_FLOAT |
5083 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5084 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5085 PPC_SEGMENT | PPC_EXTERN;
5086 pcc->msr_mask = (1ull << MSR_EE) |
5087 (1ull << MSR_PR) |
5088 (1ull << MSR_FP) |
5089 (1ull << MSR_ME) |
5090 (1ull << MSR_FE0) |
5091 (1ull << MSR_SE) |
5092 (1ull << MSR_FE1) |
5093 (1ull << MSR_EP) |
5094 (1ull << MSR_IR) |
5095 (1ull << MSR_DR);
5096 pcc->mmu_model = POWERPC_MMU_601;
5097 #if defined(CONFIG_SOFTMMU)
5098 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5099 #endif
5100 pcc->excp_model = POWERPC_EXCP_601;
5101 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5102 pcc->bfd_mach = bfd_mach_ppc_601;
5103 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5104 }
5105
5106 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5107
5108 static void init_proc_601v (CPUPPCState *env)
5109 {
5110 init_proc_601(env);
5111 /* XXX : not implemented */
5112 spr_register(env, SPR_601_HID15, "HID15",
5113 SPR_NOACCESS, SPR_NOACCESS,
5114 &spr_read_generic, &spr_write_generic,
5115 0x00000000);
5116 }
5117
5118 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5119 {
5120 DeviceClass *dc = DEVICE_CLASS(oc);
5121 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5122
5123 dc->desc = "PowerPC 601v";
5124 pcc->init_proc = init_proc_601v;
5125 pcc->check_pow = check_pow_none;
5126 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5127 PPC_FLOAT |
5128 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5129 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5130 PPC_SEGMENT | PPC_EXTERN;
5131 pcc->msr_mask = (1ull << MSR_EE) |
5132 (1ull << MSR_PR) |
5133 (1ull << MSR_FP) |
5134 (1ull << MSR_ME) |
5135 (1ull << MSR_FE0) |
5136 (1ull << MSR_SE) |
5137 (1ull << MSR_FE1) |
5138 (1ull << MSR_EP) |
5139 (1ull << MSR_IR) |
5140 (1ull << MSR_DR);
5141 pcc->mmu_model = POWERPC_MMU_601;
5142 #if defined(CONFIG_SOFTMMU)
5143 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5144 #endif
5145 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5146 pcc->bfd_mach = bfd_mach_ppc_601;
5147 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5148 }
5149
5150 static void init_proc_602 (CPUPPCState *env)
5151 {
5152 gen_spr_ne_601(env);
5153 gen_spr_602(env);
5154 /* Time base */
5155 gen_tbl(env);
5156 /* hardware implementation registers */
5157 /* XXX : not implemented */
5158 spr_register(env, SPR_HID0, "HID0",
5159 SPR_NOACCESS, SPR_NOACCESS,
5160 &spr_read_generic, &spr_write_generic,
5161 0x00000000);
5162 /* XXX : not implemented */
5163 spr_register(env, SPR_HID1, "HID1",
5164 SPR_NOACCESS, SPR_NOACCESS,
5165 &spr_read_generic, &spr_write_generic,
5166 0x00000000);
5167 /* Memory management */
5168 gen_low_BATs(env);
5169 gen_6xx_7xx_soft_tlb(env, 64, 2);
5170 init_excp_602(env);
5171 env->dcache_line_size = 32;
5172 env->icache_line_size = 32;
5173 /* Allocate hardware IRQ controller */
5174 ppc6xx_irq_init(env);
5175 }
5176
5177 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5178 {
5179 DeviceClass *dc = DEVICE_CLASS(oc);
5180 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5181
5182 dc->desc = "PowerPC 602";
5183 pcc->init_proc = init_proc_602;
5184 pcc->check_pow = check_pow_hid0;
5185 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5186 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5187 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5188 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5189 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5190 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5191 PPC_SEGMENT | PPC_602_SPEC;
5192 pcc->msr_mask = (1ull << MSR_VSX) |
5193 (1ull << MSR_SA) |
5194 (1ull << MSR_POW) |
5195 (1ull << MSR_TGPR) |
5196 (1ull << MSR_ILE) |
5197 (1ull << MSR_EE) |
5198 (1ull << MSR_PR) |
5199 (1ull << MSR_FP) |
5200 (1ull << MSR_ME) |
5201 (1ull << MSR_FE0) |
5202 (1ull << MSR_SE) |
5203 (1ull << MSR_DE) |
5204 (1ull << MSR_FE1) |
5205 (1ull << MSR_EP) |
5206 (1ull << MSR_IR) |
5207 (1ull << MSR_DR) |
5208 (1ull << MSR_RI) |
5209 (1ull << MSR_LE);
5210 /* XXX: 602 MMU is quite specific. Should add a special case */
5211 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5212 pcc->excp_model = POWERPC_EXCP_602;
5213 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5214 pcc->bfd_mach = bfd_mach_ppc_602;
5215 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5216 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5217 }
5218
5219 static void init_proc_603 (CPUPPCState *env)
5220 {
5221 gen_spr_ne_601(env);
5222 gen_spr_603(env);
5223 /* Time base */
5224 gen_tbl(env);
5225 /* hardware implementation registers */
5226 /* XXX : not implemented */
5227 spr_register(env, SPR_HID0, "HID0",
5228 SPR_NOACCESS, SPR_NOACCESS,
5229 &spr_read_generic, &spr_write_generic,
5230 0x00000000);
5231 /* XXX : not implemented */
5232 spr_register(env, SPR_HID1, "HID1",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_generic, &spr_write_generic,
5235 0x00000000);
5236 /* Memory management */
5237 gen_low_BATs(env);
5238 gen_6xx_7xx_soft_tlb(env, 64, 2);
5239 init_excp_603(env);
5240 env->dcache_line_size = 32;
5241 env->icache_line_size = 32;
5242 /* Allocate hardware IRQ controller */
5243 ppc6xx_irq_init(env);
5244 }
5245
5246 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5247 {
5248 DeviceClass *dc = DEVICE_CLASS(oc);
5249 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5250
5251 dc->desc = "PowerPC 603";
5252 pcc->init_proc = init_proc_603;
5253 pcc->check_pow = check_pow_hid0;
5254 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5255 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5256 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5257 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5258 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5259 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5260 PPC_SEGMENT | PPC_EXTERN;
5261 pcc->msr_mask = (1ull << MSR_POW) |
5262 (1ull << MSR_TGPR) |
5263 (1ull << MSR_ILE) |
5264 (1ull << MSR_EE) |
5265 (1ull << MSR_PR) |
5266 (1ull << MSR_FP) |
5267 (1ull << MSR_ME) |
5268 (1ull << MSR_FE0) |
5269 (1ull << MSR_SE) |
5270 (1ull << MSR_DE) |
5271 (1ull << MSR_FE1) |
5272 (1ull << MSR_EP) |
5273 (1ull << MSR_IR) |
5274 (1ull << MSR_DR) |
5275 (1ull << MSR_RI) |
5276 (1ull << MSR_LE);
5277 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5278 pcc->excp_model = POWERPC_EXCP_603;
5279 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5280 pcc->bfd_mach = bfd_mach_ppc_603;
5281 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5282 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5283 }
5284
5285 static void init_proc_603E (CPUPPCState *env)
5286 {
5287 gen_spr_ne_601(env);
5288 gen_spr_603(env);
5289 /* Time base */
5290 gen_tbl(env);
5291 /* hardware implementation registers */
5292 /* XXX : not implemented */
5293 spr_register(env, SPR_HID0, "HID0",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297 /* XXX : not implemented */
5298 spr_register(env, SPR_HID1, "HID1",
5299 SPR_NOACCESS, SPR_NOACCESS,
5300 &spr_read_generic, &spr_write_generic,
5301 0x00000000);
5302 /* Memory management */
5303 gen_low_BATs(env);
5304 gen_6xx_7xx_soft_tlb(env, 64, 2);
5305 init_excp_603(env);
5306 env->dcache_line_size = 32;
5307 env->icache_line_size = 32;
5308 /* Allocate hardware IRQ controller */
5309 ppc6xx_irq_init(env);
5310 }
5311
5312 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5313 {
5314 DeviceClass *dc = DEVICE_CLASS(oc);
5315 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5316
5317 dc->desc = "PowerPC 603e";
5318 pcc->init_proc = init_proc_603E;
5319 pcc->check_pow = check_pow_hid0;
5320 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5321 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5322 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5323 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5324 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5325 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5326 PPC_SEGMENT | PPC_EXTERN;
5327 pcc->msr_mask = (1ull << MSR_POW) |
5328 (1ull << MSR_TGPR) |
5329 (1ull << MSR_ILE) |
5330 (1ull << MSR_EE) |
5331 (1ull << MSR_PR) |
5332 (1ull << MSR_FP) |
5333 (1ull << MSR_ME) |
5334 (1ull << MSR_FE0) |
5335 (1ull << MSR_SE) |
5336 (1ull << MSR_DE) |
5337 (1ull << MSR_FE1) |
5338 (1ull << MSR_EP) |
5339 (1ull << MSR_IR) |
5340 (1ull << MSR_DR) |
5341 (1ull << MSR_RI) |
5342 (1ull << MSR_LE);
5343 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5344 pcc->excp_model = POWERPC_EXCP_603E;
5345 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5346 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5347 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5348 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5349 }
5350
5351 static void init_proc_604 (CPUPPCState *env)
5352 {
5353 gen_spr_ne_601(env);
5354 gen_spr_604(env);
5355 /* Time base */
5356 gen_tbl(env);
5357 /* Hardware implementation registers */
5358 /* XXX : not implemented */
5359 spr_register(env, SPR_HID0, "HID0",
5360 SPR_NOACCESS, SPR_NOACCESS,
5361 &spr_read_generic, &spr_write_generic,
5362 0x00000000);
5363 /* Memory management */
5364 gen_low_BATs(env);
5365 init_excp_604(env);
5366 env->dcache_line_size = 32;
5367 env->icache_line_size = 32;
5368 /* Allocate hardware IRQ controller */
5369 ppc6xx_irq_init(env);
5370 }
5371
5372 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5373 {
5374 DeviceClass *dc = DEVICE_CLASS(oc);
5375 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5376
5377 dc->desc = "PowerPC 604";
5378 pcc->init_proc = init_proc_604;
5379 pcc->check_pow = check_pow_nocheck;
5380 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5381 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5382 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5383 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5384 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5385 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5386 PPC_SEGMENT | PPC_EXTERN;
5387 pcc->msr_mask = (1ull << MSR_POW) |
5388 (1ull << MSR_ILE) |
5389 (1ull << MSR_EE) |
5390 (1ull << MSR_PR) |
5391 (1ull << MSR_FP) |
5392 (1ull << MSR_ME) |
5393 (1ull << MSR_FE0) |
5394 (1ull << MSR_SE) |
5395 (1ull << MSR_DE) |
5396 (1ull << MSR_FE1) |
5397 (1ull << MSR_EP) |
5398 (1ull << MSR_IR) |
5399 (1ull << MSR_DR) |
5400 (1ull << MSR_PMM) |
5401 (1ull << MSR_RI) |
5402 (1ull << MSR_LE);
5403 pcc->mmu_model = POWERPC_MMU_32B;
5404 #if defined(CONFIG_SOFTMMU)
5405 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5406 #endif
5407 pcc->excp_model = POWERPC_EXCP_604;
5408 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5409 pcc->bfd_mach = bfd_mach_ppc_604;
5410 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5411 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5412 }
5413
5414 static void init_proc_604E (CPUPPCState *env)
5415 {
5416 gen_spr_ne_601(env);
5417 gen_spr_604(env);
5418 /* XXX : not implemented */
5419 spr_register(env, SPR_MMCR1, "MMCR1",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423 /* XXX : not implemented */
5424 spr_register(env, SPR_PMC3, "PMC3",
5425 SPR_NOACCESS, SPR_NOACCESS,
5426 &spr_read_generic, &spr_write_generic,
5427 0x00000000);
5428 /* XXX : not implemented */
5429 spr_register(env, SPR_PMC4, "PMC4",
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 &spr_read_generic, &spr_write_generic,
5432 0x00000000);
5433 /* Time base */
5434 gen_tbl(env);
5435 /* Hardware implementation registers */
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_HID0, "HID0",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* XXX : not implemented */
5442 spr_register(env, SPR_HID1, "HID1",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 &spr_read_generic, &spr_write_generic,
5445 0x00000000);
5446 /* Memory management */
5447 gen_low_BATs(env);
5448 init_excp_604(env);
5449 env->dcache_line_size = 32;
5450 env->icache_line_size = 32;
5451 /* Allocate hardware IRQ controller */
5452 ppc6xx_irq_init(env);
5453 }
5454
5455 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5456 {
5457 DeviceClass *dc = DEVICE_CLASS(oc);
5458 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5459
5460 dc->desc = "PowerPC 604E";
5461 pcc->init_proc = init_proc_604E;
5462 pcc->check_pow = check_pow_nocheck;
5463 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5464 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5465 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5466 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5467 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5468 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5469 PPC_SEGMENT | PPC_EXTERN;
5470 pcc->msr_mask = (1ull << MSR_POW) |
5471 (1ull << MSR_ILE) |
5472 (1ull << MSR_EE) |
5473 (1ull << MSR_PR) |
5474 (1ull << MSR_FP) |
5475 (1ull << MSR_ME) |
5476 (1ull << MSR_FE0) |
5477 (1ull << MSR_SE) |
5478 (1ull << MSR_DE) |
5479 (1ull << MSR_FE1) |
5480 (1ull << MSR_EP) |
5481 (1ull << MSR_IR) |
5482 (1ull << MSR_DR) |
5483 (1ull << MSR_PMM) |
5484 (1ull << MSR_RI) |
5485 (1ull << MSR_LE);
5486 pcc->mmu_model = POWERPC_MMU_32B;
5487 #if defined(CONFIG_SOFTMMU)
5488 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5489 #endif
5490 pcc->excp_model = POWERPC_EXCP_604;
5491 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5492 pcc->bfd_mach = bfd_mach_ppc_604;
5493 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5494 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5495 }
5496
5497 static void init_proc_740 (CPUPPCState *env)
5498 {
5499 gen_spr_ne_601(env);
5500 gen_spr_7xx(env);
5501 /* Time base */
5502 gen_tbl(env);
5503 /* Thermal management */
5504 gen_spr_thrm(env);
5505 /* Hardware implementation registers */
5506 /* XXX : not implemented */
5507 spr_register(env, SPR_HID0, "HID0",
5508 SPR_NOACCESS, SPR_NOACCESS,
5509 &spr_read_generic, &spr_write_generic,
5510 0x00000000);
5511 /* XXX : not implemented */
5512 spr_register(env, SPR_HID1, "HID1",
5513 SPR_NOACCESS, SPR_NOACCESS,
5514 &spr_read_generic, &spr_write_generic,
5515 0x00000000);
5516 /* Memory management */
5517 gen_low_BATs(env);
5518 init_excp_7x0(env);
5519 env->dcache_line_size = 32;
5520 env->icache_line_size = 32;
5521 /* Allocate hardware IRQ controller */
5522 ppc6xx_irq_init(env);
5523 }
5524
5525 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5526 {
5527 DeviceClass *dc = DEVICE_CLASS(oc);
5528 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5529
5530 dc->desc = "PowerPC 740";
5531 pcc->init_proc = init_proc_740;
5532 pcc->check_pow = check_pow_hid0;
5533 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5534 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5535 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5536 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5537 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5538 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5539 PPC_SEGMENT | PPC_EXTERN;
5540 pcc->msr_mask = (1ull << MSR_POW) |
5541 (1ull << MSR_ILE) |
5542 (1ull << MSR_EE) |
5543 (1ull << MSR_PR) |
5544 (1ull << MSR_FP) |
5545 (1ull << MSR_ME) |
5546 (1ull << MSR_FE0) |
5547 (1ull << MSR_SE) |
5548 (1ull << MSR_DE) |
5549 (1ull << MSR_FE1) |
5550 (1ull << MSR_EP) |
5551 (1ull << MSR_IR) |
5552 (1ull << MSR_DR) |
5553 (1ull << MSR_PMM) |
5554 (1ull << MSR_RI) |
5555 (1ull << MSR_LE);
5556 pcc->mmu_model = POWERPC_MMU_32B;
5557 #if defined(CONFIG_SOFTMMU)
5558 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5559 #endif
5560 pcc->excp_model = POWERPC_EXCP_7x0;
5561 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5562 pcc->bfd_mach = bfd_mach_ppc_750;
5563 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5564 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5565 }
5566
5567 static void init_proc_750 (CPUPPCState *env)
5568 {
5569 gen_spr_ne_601(env);
5570 gen_spr_7xx(env);
5571 /* XXX : not implemented */
5572 spr_register(env, SPR_L2CR, "L2CR",
5573 SPR_NOACCESS, SPR_NOACCESS,
5574 &spr_read_generic, spr_access_nop,
5575 0x00000000);
5576 /* Time base */
5577 gen_tbl(env);
5578 /* Thermal management */
5579 gen_spr_thrm(env);
5580 /* Hardware implementation registers */
5581 /* XXX : not implemented */
5582 spr_register(env, SPR_HID0, "HID0",
5583 SPR_NOACCESS, SPR_NOACCESS,
5584 &spr_read_generic, &spr_write_generic,
5585 0x00000000);
5586 /* XXX : not implemented */
5587 spr_register(env, SPR_HID1, "HID1",
5588 SPR_NOACCESS, SPR_NOACCESS,
5589 &spr_read_generic, &spr_write_generic,
5590 0x00000000);
5591 /* Memory management */
5592 gen_low_BATs(env);
5593 /* XXX: high BATs are also present but are known to be bugged on
5594 * die version 1.x
5595 */
5596 init_excp_7x0(env);
5597 env->dcache_line_size = 32;
5598 env->icache_line_size = 32;
5599 /* Allocate hardware IRQ controller */
5600 ppc6xx_irq_init(env);
5601 }
5602
5603 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5604 {
5605 DeviceClass *dc = DEVICE_CLASS(oc);
5606 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5607
5608 dc->desc = "PowerPC 750";
5609 pcc->init_proc = init_proc_750;
5610 pcc->check_pow = check_pow_hid0;
5611 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5612 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5613 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5614 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5615 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5616 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5617 PPC_SEGMENT | PPC_EXTERN;
5618 pcc->msr_mask = (1ull << MSR_POW) |
5619 (1ull << MSR_ILE) |
5620 (1ull << MSR_EE) |
5621 (1ull << MSR_PR) |
5622 (1ull << MSR_FP) |
5623 (1ull << MSR_ME) |
5624 (1ull << MSR_FE0) |
5625 (1ull << MSR_SE) |
5626 (1ull << MSR_DE) |
5627 (1ull << MSR_FE1) |
5628 (1ull << MSR_EP) |
5629 (1ull << MSR_IR) |
5630 (1ull << MSR_DR) |
5631 (1ull << MSR_PMM) |
5632 (1ull << MSR_RI) |
5633 (1ull << MSR_LE);
5634 pcc->mmu_model = POWERPC_MMU_32B;
5635 #if defined(CONFIG_SOFTMMU)
5636 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5637 #endif
5638 pcc->excp_model = POWERPC_EXCP_7x0;
5639 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5640 pcc->bfd_mach = bfd_mach_ppc_750;
5641 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5642 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5643 }
5644
5645 static void init_proc_750cl (CPUPPCState *env)
5646 {
5647 gen_spr_ne_601(env);
5648 gen_spr_7xx(env);
5649 /* XXX : not implemented */
5650 spr_register(env, SPR_L2CR, "L2CR",
5651 SPR_NOACCESS, SPR_NOACCESS,
5652 &spr_read_generic, spr_access_nop,
5653 0x00000000);
5654 /* Time base */
5655 gen_tbl(env);
5656 /* Thermal management */
5657 /* Those registers are fake on 750CL */
5658 spr_register(env, SPR_THRM1, "THRM1",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, &spr_write_generic,
5661 0x00000000);
5662 spr_register(env, SPR_THRM2, "THRM2",
5663 SPR_NOACCESS, SPR_NOACCESS,
5664 &spr_read_generic, &spr_write_generic,
5665 0x00000000);
5666 spr_register(env, SPR_THRM3, "THRM3",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_generic, &spr_write_generic,
5669 0x00000000);
5670 /* XXX: not implemented */
5671 spr_register(env, SPR_750_TDCL, "TDCL",
5672 SPR_NOACCESS, SPR_NOACCESS,
5673 &spr_read_generic, &spr_write_generic,
5674 0x00000000);
5675 spr_register(env, SPR_750_TDCH, "TDCH",
5676 SPR_NOACCESS, SPR_NOACCESS,
5677 &spr_read_generic, &spr_write_generic,
5678 0x00000000);
5679 /* DMA */
5680 /* XXX : not implemented */
5681 spr_register(env, SPR_750_WPAR, "WPAR",
5682 SPR_NOACCESS, SPR_NOACCESS,
5683 &spr_read_generic, &spr_write_generic,
5684 0x00000000);
5685 spr_register(env, SPR_750_DMAL, "DMAL",
5686 SPR_NOACCESS, SPR_NOACCESS,
5687 &spr_read_generic, &spr_write_generic,
5688 0x00000000);
5689 spr_register(env, SPR_750_DMAU, "DMAU",
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 &spr_read_generic, &spr_write_generic,
5692 0x00000000);
5693 /* Hardware implementation registers */
5694 /* XXX : not implemented */
5695 spr_register(env, SPR_HID0, "HID0",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 &spr_read_generic, &spr_write_generic,
5698 0x00000000);
5699 /* XXX : not implemented */
5700 spr_register(env, SPR_HID1, "HID1",
5701 SPR_NOACCESS, SPR_NOACCESS,
5702 &spr_read_generic, &spr_write_generic,
5703 0x00000000);
5704 /* XXX : not implemented */
5705 spr_register(env, SPR_750CL_HID2, "HID2",
5706 SPR_NOACCESS, SPR_NOACCESS,
5707 &spr_read_generic, &spr_write_generic,
5708 0x00000000);
5709 /* XXX : not implemented */
5710 spr_register(env, SPR_750CL_HID4, "HID4",
5711 SPR_NOACCESS, SPR_NOACCESS,
5712 &spr_read_generic, &spr_write_generic,
5713 0x00000000);
5714 /* Quantization registers */
5715 /* XXX : not implemented */
5716 spr_register(env, SPR_750_GQR0, "GQR0",
5717 SPR_NOACCESS, SPR_NOACCESS,
5718 &spr_read_generic, &spr_write_generic,
5719 0x00000000);
5720 /* XXX : not implemented */
5721 spr_register(env, SPR_750_GQR1, "GQR1",
5722 SPR_NOACCESS, SPR_NOACCESS,
5723 &spr_read_generic, &spr_write_generic,
5724 0x00000000);
5725 /* XXX : not implemented */
5726 spr_register(env, SPR_750_GQR2, "GQR2",
5727 SPR_NOACCESS, SPR_NOACCESS,
5728 &spr_read_generic, &spr_write_generic,
5729 0x00000000);
5730 /* XXX : not implemented */
5731 spr_register(env, SPR_750_GQR3, "GQR3",
5732 SPR_NOACCESS, SPR_NOACCESS,
5733 &spr_read_generic, &spr_write_generic,
5734 0x00000000);
5735 /* XXX : not implemented */
5736 spr_register(env, SPR_750_GQR4, "GQR4",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_read_generic, &spr_write_generic,
5739 0x00000000);
5740 /* XXX : not implemented */
5741 spr_register(env, SPR_750_GQR5, "GQR5",
5742 SPR_NOACCESS, SPR_NOACCESS,
5743 &spr_read_generic, &spr_write_generic,
5744 0x00000000);
5745 /* XXX : not implemented */
5746 spr_register(env, SPR_750_GQR6, "GQR6",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 &spr_read_generic, &spr_write_generic,
5749 0x00000000);
5750 /* XXX : not implemented */
5751 spr_register(env, SPR_750_GQR7, "GQR7",
5752 SPR_NOACCESS, SPR_NOACCESS,
5753 &spr_read_generic, &spr_write_generic,
5754 0x00000000);
5755 /* Memory management */
5756 gen_low_BATs(env);
5757 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5758 gen_high_BATs(env);
5759 init_excp_750cl(env);
5760 env->dcache_line_size = 32;
5761 env->icache_line_size = 32;
5762 /* Allocate hardware IRQ controller */
5763 ppc6xx_irq_init(env);
5764 }
5765
5766 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5767 {
5768 DeviceClass *dc = DEVICE_CLASS(oc);
5769 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5770
5771 dc->desc = "PowerPC 750 CL";
5772 pcc->init_proc = init_proc_750cl;
5773 pcc->check_pow = check_pow_hid0;
5774 /* XXX: not implemented:
5775 * cache lock instructions:
5776 * dcbz_l
5777 * floating point paired instructions
5778 * psq_lux
5779 * psq_lx
5780 * psq_stux
5781 * psq_stx
5782 * ps_abs
5783 * ps_add
5784 * ps_cmpo0
5785 * ps_cmpo1
5786 * ps_cmpu0
5787 * ps_cmpu1
5788 * ps_div
5789 * ps_madd
5790 * ps_madds0
5791 * ps_madds1
5792 * ps_merge00
5793 * ps_merge01
5794 * ps_merge10
5795 * ps_merge11
5796 * ps_mr
5797 * ps_msub
5798 * ps_mul
5799 * ps_muls0
5800 * ps_muls1
5801 * ps_nabs
5802 * ps_neg
5803 * ps_nmadd
5804 * ps_nmsub
5805 * ps_res
5806 * ps_rsqrte
5807 * ps_sel
5808 * ps_sub
5809 * ps_sum0
5810 * ps_sum1
5811 */
5812 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5813 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5814 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5815 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5816 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5817 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5818 PPC_SEGMENT | PPC_EXTERN;
5819 pcc->msr_mask = (1ull << MSR_POW) |
5820 (1ull << MSR_ILE) |
5821 (1ull << MSR_EE) |
5822 (1ull << MSR_PR) |
5823 (1ull << MSR_FP) |
5824 (1ull << MSR_ME) |
5825 (1ull << MSR_FE0) |
5826 (1ull << MSR_SE) |
5827 (1ull << MSR_DE) |
5828 (1ull << MSR_FE1) |
5829 (1ull << MSR_EP) |
5830 (1ull << MSR_IR) |
5831 (1ull << MSR_DR) |
5832 (1ull << MSR_PMM) |
5833 (1ull << MSR_RI) |
5834 (1ull << MSR_LE);
5835 pcc->mmu_model = POWERPC_MMU_32B;
5836 #if defined(CONFIG_SOFTMMU)
5837 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5838 #endif
5839 pcc->excp_model = POWERPC_EXCP_7x0;
5840 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5841 pcc->bfd_mach = bfd_mach_ppc_750;
5842 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5843 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5844 }
5845
5846 static void init_proc_750cx (CPUPPCState *env)
5847 {
5848 gen_spr_ne_601(env);
5849 gen_spr_7xx(env);
5850 /* XXX : not implemented */
5851 spr_register(env, SPR_L2CR, "L2CR",
5852 SPR_NOACCESS, SPR_NOACCESS,
5853 &spr_read_generic, spr_access_nop,
5854 0x00000000);
5855 /* Time base */
5856 gen_tbl(env);
5857 /* Thermal management */
5858 gen_spr_thrm(env);
5859 /* This register is not implemented but is present for compatibility */
5860 spr_register(env, SPR_SDA, "SDA",
5861 SPR_NOACCESS, SPR_NOACCESS,
5862 &spr_read_generic, &spr_write_generic,
5863 0x00000000);
5864 /* Hardware implementation registers */
5865 /* XXX : not implemented */
5866 spr_register(env, SPR_HID0, "HID0",
5867 SPR_NOACCESS, SPR_NOACCESS,
5868 &spr_read_generic, &spr_write_generic,
5869 0x00000000);
5870 /* XXX : not implemented */
5871 spr_register(env, SPR_HID1, "HID1",
5872 SPR_NOACCESS, SPR_NOACCESS,
5873 &spr_read_generic, &spr_write_generic,
5874 0x00000000);
5875 /* Memory management */
5876 gen_low_BATs(env);
5877 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5878 gen_high_BATs(env);
5879 init_excp_750cx(env);
5880 env->dcache_line_size = 32;
5881 env->icache_line_size = 32;
5882 /* Allocate hardware IRQ controller */
5883 ppc6xx_irq_init(env);
5884 }
5885
5886 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5887 {
5888 DeviceClass *dc = DEVICE_CLASS(oc);
5889 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5890
5891 dc->desc = "PowerPC 750CX";
5892 pcc->init_proc = init_proc_750cx;
5893 pcc->check_pow = check_pow_hid0;
5894 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5895 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5896 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5897 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5898 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5899 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5900 PPC_SEGMENT | PPC_EXTERN;
5901 pcc->msr_mask = (1ull << MSR_POW) |
5902 (1ull << MSR_ILE) |
5903 (1ull << MSR_EE) |
5904 (1ull << MSR_PR) |
5905 (1ull << MSR_FP) |
5906 (1ull << MSR_ME) |
5907 (1ull << MSR_FE0) |
5908 (1ull << MSR_SE) |
5909 (1ull << MSR_DE) |
5910 (1ull << MSR_FE1) |
5911 (1ull << MSR_EP) |
5912 (1ull << MSR_IR) |
5913 (1ull << MSR_DR) |
5914 (1ull << MSR_PMM) |
5915 (1ull << MSR_RI) |
5916 (1ull << MSR_LE);
5917 pcc->mmu_model = POWERPC_MMU_32B;
5918 #if defined(CONFIG_SOFTMMU)
5919 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5920 #endif
5921 pcc->excp_model = POWERPC_EXCP_7x0;
5922 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5923 pcc->bfd_mach = bfd_mach_ppc_750;
5924 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5925 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5926 }
5927
5928 static void init_proc_750fx (CPUPPCState *env)
5929 {
5930 gen_spr_ne_601(env);
5931 gen_spr_7xx(env);
5932 /* XXX : not implemented */
5933 spr_register(env, SPR_L2CR, "L2CR",
5934 SPR_NOACCESS, SPR_NOACCESS,
5935 &spr_read_generic, spr_access_nop,
5936 0x00000000);
5937 /* Time base */
5938 gen_tbl(env);
5939 /* Thermal management */
5940 gen_spr_thrm(env);
5941 /* XXX : not implemented */
5942 spr_register(env, SPR_750_THRM4, "THRM4",
5943 SPR_NOACCESS, SPR_NOACCESS,
5944 &spr_read_generic, &spr_write_generic,
5945 0x00000000);
5946 /* Hardware implementation registers */
5947 /* XXX : not implemented */
5948 spr_register(env, SPR_HID0, "HID0",
5949 SPR_NOACCESS, SPR_NOACCESS,
5950 &spr_read_generic, &spr_write_generic,
5951 0x00000000);
5952 /* XXX : not implemented */
5953 spr_register(env, SPR_HID1, "HID1",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 0x00000000);
5957 /* XXX : not implemented */
5958 spr_register(env, SPR_750FX_HID2, "HID2",
5959 SPR_NOACCESS, SPR_NOACCESS,
5960 &spr_read_generic, &spr_write_generic,
5961 0x00000000);
5962 /* Memory management */
5963 gen_low_BATs(env);
5964 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5965 gen_high_BATs(env);
5966 init_excp_7x0(env);
5967 env->dcache_line_size = 32;
5968 env->icache_line_size = 32;
5969 /* Allocate hardware IRQ controller */
5970 ppc6xx_irq_init(env);
5971 }
5972
5973 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5974 {
5975 DeviceClass *dc = DEVICE_CLASS(oc);
5976 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5977
5978 dc->desc = "PowerPC 750FX";
5979 pcc->init_proc = init_proc_750fx;
5980 pcc->check_pow = check_pow_hid0;
5981 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5982 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5983 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5984 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5985 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5986 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5987 PPC_SEGMENT | PPC_EXTERN;
5988 pcc->msr_mask = (1ull << MSR_POW) |
5989 (1ull << MSR_ILE) |
5990 (1ull << MSR_EE) |
5991 (1ull << MSR_PR) |
5992 (1ull << MSR_FP) |
5993 (1ull << MSR_ME) |
5994 (1ull << MSR_FE0) |
5995 (1ull << MSR_SE) |
5996 (1ull << MSR_DE) |
5997 (1ull << MSR_FE1) |
5998 (1ull << MSR_EP) |
5999 (1ull << MSR_IR) |
6000 (1ull << MSR_DR) |
6001 (1ull << MSR_PMM) |
6002 (1ull << MSR_RI) |
6003 (1ull << MSR_LE);
6004 pcc->mmu_model = POWERPC_MMU_32B;
6005 #if defined(CONFIG_SOFTMMU)
6006 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6007 #endif
6008 pcc->excp_model = POWERPC_EXCP_7x0;
6009 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6010 pcc->bfd_mach = bfd_mach_ppc_750;
6011 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6012 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6013 }
6014
6015 static void init_proc_750gx (CPUPPCState *env)
6016 {
6017 gen_spr_ne_601(env);
6018 gen_spr_7xx(env);
6019 /* XXX : not implemented (XXX: different from 750fx) */
6020 spr_register(env, SPR_L2CR, "L2CR",
6021 SPR_NOACCESS, SPR_NOACCESS,
6022 &spr_read_generic, spr_access_nop,
6023 0x00000000);
6024 /* Time base */
6025 gen_tbl(env);
6026 /* Thermal management */
6027 gen_spr_thrm(env);
6028 /* XXX : not implemented */
6029 spr_register(env, SPR_750_THRM4, "THRM4",
6030 SPR_NOACCESS, SPR_NOACCESS,
6031 &spr_read_generic, &spr_write_generic,
6032 0x00000000);
6033 /* Hardware implementation registers */
6034 /* XXX : not implemented (XXX: different from 750fx) */
6035 spr_register(env, SPR_HID0, "HID0",
6036 SPR_NOACCESS, SPR_NOACCESS,
6037 &spr_read_generic, &spr_write_generic,
6038 0x00000000);
6039 /* XXX : not implemented */
6040 spr_register(env, SPR_HID1, "HID1",
6041 SPR_NOACCESS, SPR_NOACCESS,
6042 &spr_read_generic, &spr_write_generic,
6043 0x00000000);
6044 /* XXX : not implemented (XXX: different from 750fx) */
6045 spr_register(env, SPR_750FX_HID2, "HID2",
6046 SPR_NOACCESS, SPR_NOACCESS,
6047 &spr_read_generic, &spr_write_generic,
6048 0x00000000);
6049 /* Memory management */
6050 gen_low_BATs(env);
6051 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6052 gen_high_BATs(env);
6053 init_excp_7x0(env);
6054 env->dcache_line_size = 32;
6055 env->icache_line_size = 32;
6056 /* Allocate hardware IRQ controller */
6057 ppc6xx_irq_init(env);
6058 }
6059
6060 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6061 {
6062 DeviceClass *dc = DEVICE_CLASS(oc);
6063 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6064
6065 dc->desc = "PowerPC 750GX";
6066 pcc->init_proc = init_proc_750gx;
6067 pcc->check_pow = check_pow_hid0;
6068 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6069 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6070 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6071 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6072 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6073 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6074 PPC_SEGMENT | PPC_EXTERN;
6075 pcc->msr_mask = (1ull << MSR_POW) |
6076 (1ull << MSR_ILE) |
6077 (1ull << MSR_EE) |
6078 (1ull << MSR_PR) |
6079 (1ull << MSR_FP) |
6080 (1ull << MSR_ME) |
6081 (1ull << MSR_FE0) |
6082 (1ull << MSR_SE) |
6083 (1ull << MSR_DE) |
6084 (1ull << MSR_FE1) |
6085 (1ull << MSR_EP) |
6086 (1ull << MSR_IR) |
6087 (1ull << MSR_DR) |
6088 (1ull << MSR_PMM) |
6089 (1ull << MSR_RI) |
6090 (1ull << MSR_LE);
6091 pcc->mmu_model = POWERPC_MMU_32B;
6092 #if defined(CONFIG_SOFTMMU)
6093 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6094 #endif
6095 pcc->excp_model = POWERPC_EXCP_7x0;
6096 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6097 pcc->bfd_mach = bfd_mach_ppc_750;
6098 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6099 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6100 }
6101
6102 static void init_proc_745 (CPUPPCState *env)
6103 {
6104 gen_spr_ne_601(env);
6105 gen_spr_7xx(env);
6106 gen_spr_G2_755(env);
6107 /* Time base */
6108 gen_tbl(env);
6109 /* Thermal management */
6110 gen_spr_thrm(env);
6111 /* Hardware implementation registers */
6112 /* XXX : not implemented */
6113 spr_register(env, SPR_HID0, "HID0",
6114 SPR_NOACCESS, SPR_NOACCESS,
6115 &spr_read_generic, &spr_write_generic,
6116 0x00000000);
6117 /* XXX : not implemented */
6118 spr_register(env, SPR_HID1, "HID1",
6119 SPR_NOACCESS, SPR_NOACCESS,
6120 &spr_read_generic, &spr_write_generic,
6121 0x00000000);
6122 /* XXX : not implemented */
6123 spr_register(env, SPR_HID2, "HID2",
6124 SPR_NOACCESS, SPR_NOACCESS,
6125 &spr_read_generic, &spr_write_generic,
6126 0x00000000);
6127 /* Memory management */
6128 gen_low_BATs(env);
6129 gen_high_BATs(env);
6130 gen_6xx_7xx_soft_tlb(env, 64, 2);
6131 init_excp_7x5(env);
6132 env->dcache_line_size = 32;
6133 env->icache_line_size = 32;
6134 /* Allocate hardware IRQ controller */
6135 ppc6xx_irq_init(env);
6136 }
6137
6138 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6139 {
6140 DeviceClass *dc = DEVICE_CLASS(oc);
6141 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6142
6143 dc->desc = "PowerPC 745";
6144 pcc->init_proc = init_proc_745;
6145 pcc->check_pow = check_pow_hid0;
6146 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6147 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6148 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6149 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6150 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6151 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6152 PPC_SEGMENT | PPC_EXTERN;
6153 pcc->msr_mask = (1ull << MSR_POW) |
6154 (1ull << MSR_ILE) |
6155 (1ull << MSR_EE) |
6156 (1ull << MSR_PR) |
6157 (1ull << MSR_FP) |
6158 (1ull << MSR_ME) |
6159 (1ull << MSR_FE0) |
6160 (1ull << MSR_SE) |
6161 (1ull << MSR_DE) |
6162 (1ull << MSR_FE1) |
6163 (1ull << MSR_EP) |
6164 (1ull << MSR_IR) |
6165 (1ull << MSR_DR) |
6166 (1ull << MSR_PMM) |
6167 (1ull << MSR_RI) |
6168 (1ull << MSR_LE);
6169 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6170 pcc->excp_model = POWERPC_EXCP_7x5;
6171 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6172 pcc->bfd_mach = bfd_mach_ppc_750;
6173 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6174 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6175 }
6176
6177 static void init_proc_755 (CPUPPCState *env)
6178 {
6179 gen_spr_ne_601(env);
6180 gen_spr_7xx(env);
6181 gen_spr_G2_755(env);
6182 /* Time base */
6183 gen_tbl(env);
6184 /* L2 cache control */
6185 /* XXX : not implemented */
6186 spr_register(env, SPR_L2CR, "L2CR",
6187 SPR_NOACCESS, SPR_NOACCESS,
6188 &spr_read_generic, spr_access_nop,
6189 0x00000000);
6190 /* XXX : not implemented */
6191 spr_register(env, SPR_L2PMCR, "L2PMCR",
6192 SPR_NOACCESS, SPR_NOACCESS,
6193 &spr_read_generic, &spr_write_generic,
6194 0x00000000);
6195 /* Thermal management */
6196 gen_spr_thrm(env);
6197 /* Hardware implementation registers */
6198 /* XXX : not implemented */
6199 spr_register(env, SPR_HID0, "HID0",
6200 SPR_NOACCESS, SPR_NOACCESS,
6201 &spr_read_generic, &spr_write_generic,
6202 0x00000000);
6203 /* XXX : not implemented */
6204 spr_register(env, SPR_HID1, "HID1",
6205 SPR_NOACCESS, SPR_NOACCESS,
6206 &spr_read_generic, &spr_write_generic,
6207 0x00000000);
6208 /* XXX : not implemented */
6209 spr_register(env, SPR_HID2, "HID2",
6210 SPR_NOACCESS, SPR_NOACCESS,
6211 &spr_read_generic, &spr_write_generic,
6212 0x00000000);
6213 /* Memory management */
6214 gen_low_BATs(env);
6215 gen_high_BATs(env);
6216 gen_6xx_7xx_soft_tlb(env, 64, 2);
6217 init_excp_7x5(env);
6218 env->dcache_line_size = 32;
6219 env->icache_line_size = 32;
6220 /* Allocate hardware IRQ controller */
6221 ppc6xx_irq_init(env);
6222 }
6223
6224 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6225 {
6226 DeviceClass *dc = DEVICE_CLASS(oc);
6227 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6228
6229 dc->desc = "PowerPC 755";
6230 pcc->init_proc = init_proc_755;
6231 pcc->check_pow = check_pow_hid0;
6232 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6233 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6234 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6235 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6236 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6237 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6238 PPC_SEGMENT | PPC_EXTERN;
6239 pcc->msr_mask = (1ull << MSR_POW) |
6240 (1ull << MSR_ILE) |
6241 (1ull << MSR_EE) |
6242 (1ull << MSR_PR) |
6243 (1ull << MSR_FP) |
6244 (1ull << MSR_ME) |
6245 (1ull << MSR_FE0) |
6246 (1ull << MSR_SE) |
6247 (1ull << MSR_DE) |
6248 (1ull << MSR_FE1) |
6249 (1ull << MSR_EP) |
6250 (1ull << MSR_IR) |
6251 (1ull << MSR_DR) |
6252 (1ull << MSR_PMM) |
6253 (1ull << MSR_RI) |
6254 (1ull << MSR_LE);
6255 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6256 pcc->excp_model = POWERPC_EXCP_7x5;
6257 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6258 pcc->bfd_mach = bfd_mach_ppc_750;
6259 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6260 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6261 }
6262
6263 static void init_proc_7400 (CPUPPCState *env)
6264 {
6265 gen_spr_ne_601(env);
6266 gen_spr_7xx(env);
6267 /* Time base */
6268 gen_tbl(env);
6269 /* 74xx specific SPR */
6270 gen_spr_74xx(env);
6271 /* XXX : not implemented */
6272 spr_register(env, SPR_UBAMR, "UBAMR",
6273 &spr_read_ureg, SPR_NOACCESS,
6274 &spr_read_ureg, SPR_NOACCESS,
6275 0x00000000);
6276 /* XXX: this seems not implemented on all revisions. */
6277 /* XXX : not implemented */
6278 spr_register(env, SPR_MSSCR1, "MSSCR1",
6279 SPR_NOACCESS, SPR_NOACCESS,
6280 &spr_read_generic, &spr_write_generic,
6281 0x00000000);
6282 /* Thermal management */
6283 gen_spr_thrm(env);
6284 /* Memory management */
6285 gen_low_BATs(env);
6286 init_excp_7400(env);
6287 env->dcache_line_size = 32;
6288 env->icache_line_size = 32;
6289 /* Allocate hardware IRQ controller */
6290 ppc6xx_irq_init(env);
6291 }
6292
6293 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6294 {
6295 DeviceClass *dc = DEVICE_CLASS(oc);
6296 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6297
6298 dc->desc = "PowerPC 7400 (aka G4)";
6299 pcc->init_proc = init_proc_7400;
6300 pcc->check_pow = check_pow_hid0;
6301 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6302 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6303 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6304 PPC_FLOAT_STFIWX |
6305 PPC_CACHE | PPC_CACHE_ICBI |
6306 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6307 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6308 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6309 PPC_MEM_TLBIA |
6310 PPC_SEGMENT | PPC_EXTERN |
6311 PPC_ALTIVEC;
6312 pcc->msr_mask = (1ull << MSR_VR) |
6313 (1ull << MSR_POW) |
6314 (1ull << MSR_ILE) |
6315 (1ull << MSR_EE) |
6316 (1ull << MSR_PR) |
6317 (1ull << MSR_FP) |
6318 (1ull << MSR_ME) |
6319 (1ull << MSR_FE0) |
6320 (1ull << MSR_SE) |
6321 (1ull << MSR_DE) |
6322 (1ull << MSR_FE1) |
6323 (1ull << MSR_EP) |
6324 (1ull << MSR_IR) |
6325 (1ull << MSR_DR) |
6326 (1ull << MSR_PMM) |
6327 (1ull << MSR_RI) |
6328 (1ull << MSR_LE);
6329 pcc->mmu_model = POWERPC_MMU_32B;
6330 #if defined(CONFIG_SOFTMMU)
6331 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6332 #endif
6333 pcc->excp_model = POWERPC_EXCP_74xx;
6334 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6335 pcc->bfd_mach = bfd_mach_ppc_7400;
6336 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6337 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6338 POWERPC_FLAG_BUS_CLK;
6339 }
6340
6341 static void init_proc_7410 (CPUPPCState *env)
6342 {
6343 gen_spr_ne_601(env);
6344 gen_spr_7xx(env);
6345 /* Time base */
6346 gen_tbl(env);
6347 /* 74xx specific SPR */
6348 gen_spr_74xx(env);
6349 /* XXX : not implemented */
6350 spr_register(env, SPR_UBAMR, "UBAMR",
6351 &spr_read_ureg, SPR_NOACCESS,
6352 &spr_read_ureg, SPR_NOACCESS,
6353 0x00000000);
6354 /* Thermal management */
6355 gen_spr_thrm(env);
6356 /* L2PMCR */
6357 /* XXX : not implemented */
6358 spr_register(env, SPR_L2PMCR, "L2PMCR",
6359 SPR_NOACCESS, SPR_NOACCESS,
6360 &spr_read_generic, &spr_write_generic,
6361 0x00000000);
6362 /* LDSTDB */
6363 /* XXX : not implemented */
6364 spr_register(env, SPR_LDSTDB, "LDSTDB",
6365 SPR_NOACCESS, SPR_NOACCESS,
6366 &spr_read_generic, &spr_write_generic,
6367 0x00000000);
6368 /* Memory management */
6369 gen_low_BATs(env);
6370 init_excp_7400(env);
6371 env->dcache_line_size = 32;
6372 env->icache_line_size = 32;
6373 /* Allocate hardware IRQ controller */
6374 ppc6xx_irq_init(env);
6375 }
6376
6377 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6378 {
6379 DeviceClass *dc = DEVICE_CLASS(oc);
6380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6381
6382 dc->desc = "PowerPC 7410 (aka G4)";
6383 pcc->init_proc = init_proc_7410;
6384 pcc->check_pow = check_pow_hid0;
6385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6386 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6387 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6388 PPC_FLOAT_STFIWX |
6389 PPC_CACHE | PPC_CACHE_ICBI |
6390 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6391 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6392 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6393 PPC_MEM_TLBIA |
6394 PPC_SEGMENT | PPC_EXTERN |
6395 PPC_ALTIVEC;
6396 pcc->msr_mask = (1ull << MSR_VR) |
6397 (1ull << MSR_POW) |
6398 (1ull << MSR_ILE) |
6399 (1ull << MSR_EE) |
6400 (1ull << MSR_PR) |
6401 (1ull << MSR_FP) |
6402 (1ull << MSR_ME) |
6403 (1ull << MSR_FE0) |
6404 (1ull << MSR_SE) |
6405 (1ull << MSR_DE) |
6406 (1ull << MSR_FE1) |
6407 (1ull << MSR_EP) |
6408 (1ull << MSR_IR) |
6409 (1ull << MSR_DR) |
6410 (1ull << MSR_PMM) |
6411 (1ull << MSR_RI) |
6412 (1ull << MSR_LE);
6413 pcc->mmu_model = POWERPC_MMU_32B;
6414 #if defined(CONFIG_SOFTMMU)
6415 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6416 #endif
6417 pcc->excp_model = POWERPC_EXCP_74xx;
6418 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6419 pcc->bfd_mach = bfd_mach_ppc_7400;
6420 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6421 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6422 POWERPC_FLAG_BUS_CLK;
6423 }
6424
6425 static void init_proc_7440 (CPUPPCState *env)
6426 {
6427 gen_spr_ne_601(env);
6428 gen_spr_7xx(env);
6429 /* Time base */
6430 gen_tbl(env);
6431 /* 74xx specific SPR */
6432 gen_spr_74xx(env);
6433 /* XXX : not implemented */
6434 spr_register(env, SPR_UBAMR, "UBAMR",
6435 &spr_read_ureg, SPR_NOACCESS,
6436 &spr_read_ureg, SPR_NOACCESS,
6437 0x00000000);
6438 /* LDSTCR */
6439 /* XXX : not implemented */
6440 spr_register(env, SPR_LDSTCR, "LDSTCR",
6441 SPR_NOACCESS, SPR_NOACCESS,
6442 &spr_read_generic, &spr_write_generic,
6443 0x00000000);
6444 /* ICTRL */
6445 /* XXX : not implemented */
6446 spr_register(env, SPR_ICTRL, "ICTRL",
6447 SPR_NOACCESS, SPR_NOACCESS,
6448 &spr_read_generic, &spr_write_generic,
6449 0x00000000);
6450 /* MSSSR0 */
6451 /* XXX : not implemented */
6452 spr_register(env, SPR_MSSSR0, "MSSSR0",
6453 SPR_NOACCESS, SPR_NOACCESS,
6454 &spr_read_generic, &spr_write_generic,
6455 0x00000000);
6456 /* PMC */
6457 /* XXX : not implemented */
6458 spr_register(env, SPR_PMC5, "PMC5",
6459 SPR_NOACCESS, SPR_NOACCESS,
6460 &spr_read_generic, &spr_write_generic,
6461 0x00000000);
6462 /* XXX : not implemented */
6463 spr_register(env, SPR_UPMC5, "UPMC5",
6464 &spr_read_ureg, SPR_NOACCESS,
6465 &spr_read_ureg, SPR_NOACCESS,
6466 0x00000000);
6467 /* XXX : not implemented */
6468 spr_register(env, SPR_PMC6, "PMC6",
6469 SPR_NOACCESS, SPR_NOACCESS,
6470 &spr_read_generic, &spr_write_generic,
6471 0x00000000);
6472 /* XXX : not implemented */
6473 spr_register(env, SPR_UPMC6, "UPMC6",
6474 &spr_read_ureg, SPR_NOACCESS,
6475 &spr_read_ureg, SPR_NOACCESS,
6476 0x00000000);
6477 /* Memory management */
6478 gen_low_BATs(env);
6479 gen_74xx_soft_tlb(env, 128, 2);
6480 init_excp_7450(env);
6481 env->dcache_line_size = 32;
6482 env->icache_line_size = 32;
6483 /* Allocate hardware IRQ controller */
6484 ppc6xx_irq_init(env);
6485 }
6486
6487 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6488 {
6489 DeviceClass *dc = DEVICE_CLASS(oc);
6490 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6491
6492 dc->desc = "PowerPC 7440 (aka G4)";
6493 pcc->init_proc = init_proc_7440;
6494 pcc->check_pow = check_pow_hid0_74xx;
6495 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6496 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6497 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6498 PPC_FLOAT_STFIWX |
6499 PPC_CACHE | PPC_CACHE_ICBI |
6500 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6501 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6502 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6503 PPC_MEM_TLBIA | PPC_74xx_TLB |
6504 PPC_SEGMENT | PPC_EXTERN |
6505 PPC_ALTIVEC;
6506 pcc->msr_mask = (1ull << MSR_VR) |
6507 (1ull << MSR_POW) |
6508 (1ull << MSR_ILE) |
6509 (1ull << MSR_EE) |
6510 (1ull << MSR_PR) |
6511 (1ull << MSR_FP) |
6512 (1ull << MSR_ME) |
6513 (1ull << MSR_FE0) |
6514 (1ull << MSR_SE) |
6515 (1ull << MSR_DE) |
6516 (1ull << MSR_FE1) |
6517 (1ull << MSR_EP) |
6518 (1ull << MSR_IR) |
6519 (1ull << MSR_DR) |
6520 (1ull << MSR_PMM) |
6521 (1ull << MSR_RI) |
6522 (1ull << MSR_LE);
6523 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6524 pcc->excp_model = POWERPC_EXCP_74xx;
6525 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6526 pcc->bfd_mach = bfd_mach_ppc_7400;
6527 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6528 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6529 POWERPC_FLAG_BUS_CLK;
6530 }
6531
6532 static void init_proc_7450 (CPUPPCState *env)
6533 {
6534 gen_spr_ne_601(env);
6535 gen_spr_7xx(env);
6536 /* Time base */
6537 gen_tbl(env);
6538 /* 74xx specific SPR */
6539 gen_spr_74xx(env);
6540 /* Level 3 cache control */
6541 gen_l3_ctrl(env);
6542 /* L3ITCR1 */
6543 /* XXX : not implemented */
6544 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6545 SPR_NOACCESS, SPR_NOACCESS,
6546 &spr_read_generic, &spr_write_generic,
6547 0x00000000);
6548 /* L3ITCR2 */
6549 /* XXX : not implemented */
6550 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6551 SPR_NOACCESS, SPR_NOACCESS,
6552 &spr_read_generic, &spr_write_generic,
6553 0x00000000);
6554 /* L3ITCR3 */
6555 /* XXX : not implemented */
6556 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6557 SPR_NOACCESS, SPR_NOACCESS,
6558 &spr_read_generic, &spr_write_generic,
6559 0x00000000);
6560 /* L3OHCR */
6561 /* XXX : not implemented */
6562 spr_register(env, SPR_L3OHCR, "L3OHCR",
6563 SPR_NOACCESS, SPR_NOACCESS,
6564 &spr_read_generic, &spr_write_generic,
6565 0x00000000);
6566 /* XXX : not implemented */
6567 spr_register(env, SPR_UBAMR, "UBAMR",
6568 &spr_read_ureg, SPR_NOACCESS,
6569 &spr_read_ureg, SPR_NOACCESS,
6570 0x00000000);
6571 /* LDSTCR */
6572 /* XXX : not implemented */
6573 spr_register(env, SPR_LDSTCR, "LDSTCR",
6574 SPR_NOACCESS, SPR_NOACCESS,
6575 &spr_read_generic, &spr_write_generic,
6576 0x00000000);
6577 /* ICTRL */
6578 /* XXX : not implemented */
6579 spr_register(env, SPR_ICTRL, "ICTRL",
6580 SPR_NOACCESS, SPR_NOACCESS,
6581 &spr_read_generic, &spr_write_generic,
6582 0x00000000);
6583 /* MSSSR0 */
6584 /* XXX : not implemented */
6585 spr_register(env, SPR_MSSSR0, "MSSSR0",
6586 SPR_NOACCESS, SPR_NOACCESS,
6587 &spr_read_generic, &spr_write_generic,
6588 0x00000000);
6589 /* PMC */
6590 /* XXX : not implemented */
6591 spr_register(env, SPR_PMC5, "PMC5",
6592 SPR_NOACCESS, SPR_NOACCESS,
6593 &spr_read_generic, &spr_write_generic,
6594 0x00000000);
6595 /* XXX : not implemented */
6596 spr_register(env, SPR_UPMC5, "UPMC5",
6597 &spr_read_ureg, SPR_NOACCESS,
6598 &spr_read_ureg, SPR_NOACCESS,
6599 0x00000000);
6600 /* XXX : not implemented */
6601 spr_register(env, SPR_PMC6, "PMC6",
6602 SPR_NOACCESS, SPR_NOACCESS,
6603 &spr_read_generic, &spr_write_generic,
6604 0x00000000);
6605 /* XXX : not implemented */
6606 spr_register(env, SPR_UPMC6, "UPMC6",
6607 &spr_read_ureg, SPR_NOACCESS,
6608 &spr_read_ureg, SPR_NOACCESS,
6609 0x00000000);
6610 /* Memory management */
6611 gen_low_BATs(env);
6612 gen_74xx_soft_tlb(env, 128, 2);
6613 init_excp_7450(env);
6614 env->dcache_line_size = 32;
6615 env->icache_line_size = 32;
6616 /* Allocate hardware IRQ controller */
6617 ppc6xx_irq_init(env);
6618 }
6619
6620 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6621 {
6622 DeviceClass *dc = DEVICE_CLASS(oc);
6623 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6624
6625 dc->desc = "PowerPC 7450 (aka G4)";
6626 pcc->init_proc = init_proc_7450;
6627 pcc->check_pow = check_pow_hid0_74xx;
6628 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6629 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6630 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6631 PPC_FLOAT_STFIWX |
6632 PPC_CACHE | PPC_CACHE_ICBI |
6633 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6634 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6635 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6636 PPC_MEM_TLBIA | PPC_74xx_TLB |
6637 PPC_SEGMENT | PPC_EXTERN |
6638 PPC_ALTIVEC;
6639 pcc->msr_mask = (1ull << MSR_VR) |
6640 (1ull << MSR_POW) |
6641 (1ull << MSR_ILE) |
6642 (1ull << MSR_EE) |
6643 (1ull << MSR_PR) |
6644 (1ull << MSR_FP) |
6645 (1ull << MSR_ME) |
6646 (1ull << MSR_FE0) |
6647 (1ull << MSR_SE) |
6648 (1ull << MSR_DE) |
6649 (1ull << MSR_FE1) |
6650 (1ull << MSR_EP) |
6651 (1ull << MSR_IR) |
6652 (1ull << MSR_DR) |
6653 (1ull << MSR_PMM) |
6654 (1ull << MSR_RI) |
6655 (1ull << MSR_LE);
6656 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6657 pcc->excp_model = POWERPC_EXCP_74xx;
6658 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6659 pcc->bfd_mach = bfd_mach_ppc_7400;
6660 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6661 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6662 POWERPC_FLAG_BUS_CLK;
6663 }
6664
6665 static void init_proc_7445 (CPUPPCState *env)
6666 {
6667 gen_spr_ne_601(env);
6668 gen_spr_7xx(env);
6669 /* Time base */
6670 gen_tbl(env);
6671 /* 74xx specific SPR */
6672 gen_spr_74xx(env);
6673 /* LDSTCR */
6674 /* XXX : not implemented */
6675 spr_register(env, SPR_LDSTCR, "LDSTCR",
6676 SPR_NOACCESS, SPR_NOACCESS,
6677 &spr_read_generic, &spr_write_generic,
6678 0x00000000);
6679 /* ICTRL */
6680 /* XXX : not implemented */
6681 spr_register(env, SPR_ICTRL, "ICTRL",
6682 SPR_NOACCESS, SPR_NOACCESS,
6683 &spr_read_generic, &spr_write_generic,
6684 0x00000000);
6685 /* MSSSR0 */
6686 /* XXX : not implemented */
6687 spr_register(env, SPR_MSSSR0, "MSSSR0",
6688 SPR_NOACCESS, SPR_NOACCESS,
6689 &spr_read_generic, &spr_write_generic,
6690 0x00000000);
6691 /* PMC */
6692 /* XXX : not implemented */
6693 spr_register(env, SPR_PMC5, "PMC5",
6694 SPR_NOACCESS, SPR_NOACCESS,
6695 &spr_read_generic, &spr_write_generic,
6696 0x00000000);
6697 /* XXX : not implemented */
6698 spr_register(env, SPR_UPMC5, "UPMC5",
6699 &spr_read_ureg, SPR_NOACCESS,
6700 &spr_read_ureg, SPR_NOACCESS,
6701 0x00000000);
6702 /* XXX : not implemented */
6703 spr_register(env, SPR_PMC6, "PMC6",
6704 SPR_NOACCESS, SPR_NOACCESS,
6705 &spr_read_generic, &spr_write_generic,
6706 0x00000000);
6707 /* XXX : not implemented */
6708 spr_register(env, SPR_UPMC6, "UPMC6",
6709 &spr_read_ureg, SPR_NOACCESS,
6710 &spr_read_ureg, SPR_NOACCESS,
6711 0x00000000);
6712 /* SPRGs */
6713 spr_register(env, SPR_SPRG4, "SPRG4",
6714 SPR_NOACCESS, SPR_NOACCESS,
6715 &spr_read_generic, &spr_write_generic,
6716 0x00000000);
6717 spr_register(env, SPR_USPRG4, "USPRG4",
6718 &spr_read_ureg, SPR_NOACCESS,
6719 &spr_read_ureg, SPR_NOACCESS,
6720 0x00000000);
6721 spr_register(env, SPR_SPRG5, "SPRG5",
6722 SPR_NOACCESS, SPR_NOACCESS,
6723 &spr_read_generic, &spr_write_generic,
6724 0x00000000);
6725 spr_register(env, SPR_USPRG5, "USPRG5",
6726 &spr_read_ureg, SPR_NOACCESS,
6727 &spr_read_ureg, SPR_NOACCESS,
6728 0x00000000);
6729 spr_register(env, SPR_SPRG6, "SPRG6",
6730 SPR_NOACCESS, SPR_NOACCESS,
6731 &spr_read_generic, &spr_write_generic,
6732 0x00000000);
6733 spr_register(env, SPR_USPRG6, "USPRG6",
6734 &spr_read_ureg, SPR_NOACCESS,
6735 &spr_read_ureg, SPR_NOACCESS,
6736 0x00000000);
6737 spr_register(env, SPR_SPRG7, "SPRG7",
6738 SPR_NOACCESS, SPR_NOACCESS,
6739 &spr_read_generic, &spr_write_generic,
6740 0x00000000);
6741 spr_register(env, SPR_USPRG7, "USPRG7",
6742 &spr_read_ureg, SPR_NOACCESS,
6743 &spr_read_ureg, SPR_NOACCESS,
6744 0x00000000);
6745 /* Memory management */
6746 gen_low_BATs(env);
6747 gen_high_BATs(env);
6748 gen_74xx_soft_tlb(env, 128, 2);
6749 init_excp_7450(env);
6750 env->dcache_line_size = 32;
6751 env->icache_line_size = 32;
6752 /* Allocate hardware IRQ controller */
6753 ppc6xx_irq_init(env);
6754 }
6755
6756 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6757 {
6758 DeviceClass *dc = DEVICE_CLASS(oc);
6759 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6760
6761 dc->desc = "PowerPC 7445 (aka G4)";
6762 pcc->init_proc = init_proc_7445;
6763 pcc->check_pow = check_pow_hid0_74xx;
6764 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6765 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6766 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6767 PPC_FLOAT_STFIWX |
6768 PPC_CACHE | PPC_CACHE_ICBI |
6769 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6770 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6771 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6772 PPC_MEM_TLBIA | PPC_74xx_TLB |
6773 PPC_SEGMENT | PPC_EXTERN |
6774 PPC_ALTIVEC;
6775 pcc->msr_mask = (1ull << MSR_VR) |
6776 (1ull << MSR_POW) |
6777 (1ull << MSR_ILE) |
6778 (1ull << MSR_EE) |
6779 (1ull << MSR_PR) |
6780 (1ull << MSR_FP) |
6781 (1ull << MSR_ME) |
6782 (1ull << MSR_FE0) |
6783 (1ull << MSR_SE) |
6784 (1ull << MSR_DE) |
6785 (1ull << MSR_FE1) |
6786 (1ull << MSR_EP) |
6787 (1ull << MSR_IR) |
6788 (1ull << MSR_DR) |
6789 (1ull << MSR_PMM) |
6790 (1ull << MSR_RI) |
6791 (1ull << MSR_LE);
6792 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6793 pcc->excp_model = POWERPC_EXCP_74xx;
6794 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6795 pcc->bfd_mach = bfd_mach_ppc_7400;
6796 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6797 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6798 POWERPC_FLAG_BUS_CLK;
6799 }
6800
6801 static void init_proc_7455 (CPUPPCState *env)
6802 {
6803 gen_spr_ne_601(env);
6804 gen_spr_7xx(env);
6805 /* Time base */
6806 gen_tbl(env);
6807 /* 74xx specific SPR */
6808 gen_spr_74xx(env);
6809 /* Level 3 cache control */
6810 gen_l3_ctrl(env);
6811 /* LDSTCR */
6812 /* XXX : not implemented */
6813 spr_register(env, SPR_LDSTCR, "LDSTCR",
6814 SPR_NOACCESS, SPR_NOACCESS,
6815 &spr_read_generic, &spr_write_generic,
6816 0x00000000);
6817 /* ICTRL */
6818 /* XXX : not implemented */
6819 spr_register(env, SPR_ICTRL, "ICTRL",
6820 SPR_NOACCESS, SPR_NOACCESS,
6821 &spr_read_generic, &spr_write_generic,
6822 0x00000000);
6823 /* MSSSR0 */
6824 /* XXX : not implemented */
6825 spr_register(env, SPR_MSSSR0, "MSSSR0",
6826 SPR_NOACCESS, SPR_NOACCESS,
6827 &spr_read_generic, &spr_write_generic,
6828 0x00000000);
6829 /* PMC */
6830 /* XXX : not implemented */
6831 spr_register(env, SPR_PMC5, "PMC5",
6832 SPR_NOACCESS, SPR_NOACCESS,
6833 &spr_read_generic, &spr_write_generic,
6834 0x00000000);
6835 /* XXX : not implemented */
6836 spr_register(env, SPR_UPMC5, "UPMC5",
6837 &spr_read_ureg, SPR_NOACCESS,
6838 &spr_read_ureg, SPR_NOACCESS,
6839 0x00000000);
6840 /* XXX : not implemented */
6841 spr_register(env, SPR_PMC6, "PMC6",
6842 SPR_NOACCESS, SPR_NOACCESS,
6843 &spr_read_generic, &spr_write_generic,
6844 0x00000000);
6845 /* XXX : not implemented */
6846 spr_register(env, SPR_UPMC6, "UPMC6",
6847 &spr_read_ureg, SPR_NOACCESS,
6848 &spr_read_ureg, SPR_NOACCESS,
6849 0x00000000);
6850 /* SPRGs */
6851 spr_register(env, SPR_SPRG4, "SPRG4",
6852 SPR_NOACCESS, SPR_NOACCESS,
6853 &spr_read_generic, &spr_write_generic,
6854 0x00000000);
6855 spr_register(env, SPR_USPRG4, "USPRG4",
6856 &spr_read_ureg, SPR_NOACCESS,
6857 &spr_read_ureg, SPR_NOACCESS,
6858 0x00000000);
6859 spr_register(env, SPR_SPRG5, "SPRG5",
6860 SPR_NOACCESS, SPR_NOACCESS,
6861 &spr_read_generic, &spr_write_generic,
6862 0x00000000);
6863 spr_register(env, SPR_USPRG5, "USPRG5",
6864 &spr_read_ureg, SPR_NOACCESS,
6865 &spr_read_ureg, SPR_NOACCESS,
6866 0x00000000);
6867 spr_register(env, SPR_SPRG6, "SPRG6",
6868 SPR_NOACCESS, SPR_NOACCESS,
6869 &spr_read_generic, &spr_write_generic,
6870 0x00000000);
6871 spr_register(env, SPR_USPRG6, "USPRG6",
6872 &spr_read_ureg, SPR_NOACCESS,
6873 &spr_read_ureg, SPR_NOACCESS,
6874 0x00000000);
6875 spr_register(env, SPR_SPRG7, "SPRG7",
6876 SPR_NOACCESS, SPR_NOACCESS,
6877 &spr_read_generic, &spr_write_generic,
6878 0x00000000);
6879 spr_register(env, SPR_USPRG7, "USPRG7",
6880 &spr_read_ureg, SPR_NOACCESS,
6881 &spr_read_ureg, SPR_NOACCESS,
6882 0x00000000);
6883 /* Memory management */
6884 gen_low_BATs(env);
6885 gen_high_BATs(env);
6886 gen_74xx_soft_tlb(env, 128, 2);
6887 init_excp_7450(env);
6888 env->dcache_line_size = 32;
6889 env->icache_line_size = 32;
6890 /* Allocate hardware IRQ controller */
6891 ppc6xx_irq_init(env);
6892 }
6893
6894 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6895 {
6896 DeviceClass *dc = DEVICE_CLASS(oc);
6897 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6898
6899 dc->desc = "PowerPC 7455 (aka G4)";
6900 pcc->init_proc = init_proc_7455;
6901 pcc->check_pow = check_pow_hid0_74xx;
6902 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6903 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6904 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6905 PPC_FLOAT_STFIWX |
6906 PPC_CACHE | PPC_CACHE_ICBI |
6907 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6908 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6909 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6910 PPC_MEM_TLBIA | PPC_74xx_TLB |
6911 PPC_SEGMENT | PPC_EXTERN |
6912 PPC_ALTIVEC;
6913 pcc->msr_mask = (1ull << MSR_VR) |
6914 (1ull << MSR_POW) |
6915 (1ull << MSR_ILE) |
6916 (1ull << MSR_EE) |
6917 (1ull << MSR_PR) |
6918 (1ull << MSR_FP) |
6919 (1ull << MSR_ME) |
6920 (1ull << MSR_FE0) |
6921 (1ull << MSR_SE) |
6922 (1ull << MSR_DE) |
6923 (1ull << MSR_FE1) |
6924 (1ull << MSR_EP) |
6925 (1ull << MSR_IR) |
6926 (1ull << MSR_DR) |
6927 (1ull << MSR_PMM) |
6928 (1ull << MSR_RI) |
6929 (1ull << MSR_LE);
6930 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6931 pcc->excp_model = POWERPC_EXCP_74xx;
6932 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6933 pcc->bfd_mach = bfd_mach_ppc_7400;
6934 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6935 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6936 POWERPC_FLAG_BUS_CLK;
6937 }
6938
6939 static void init_proc_7457 (CPUPPCState *env)
6940 {
6941 gen_spr_ne_601(env);
6942 gen_spr_7xx(env);
6943 /* Time base */
6944 gen_tbl(env);
6945 /* 74xx specific SPR */
6946 gen_spr_74xx(env);
6947 /* Level 3 cache control */
6948 gen_l3_ctrl(env);
6949 /* L3ITCR1 */
6950 /* XXX : not implemented */
6951 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6952 SPR_NOACCESS, SPR_NOACCESS,
6953 &spr_read_generic, &spr_write_generic,
6954 0x00000000);
6955 /* L3ITCR2 */
6956 /* XXX : not implemented */
6957 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6958 SPR_NOACCESS, SPR_NOACCESS,
6959 &spr_read_generic, &spr_write_generic,
6960 0x00000000);
6961 /* L3ITCR3 */
6962 /* XXX : not implemented */
6963 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6964 SPR_NOACCESS, SPR_NOACCESS,
6965 &spr_read_generic, &spr_write_generic,
6966 0x00000000);
6967 /* L3OHCR */
6968 /* XXX : not implemented */
6969 spr_register(env, SPR_L3OHCR, "L3OHCR",
6970 SPR_NOACCESS, SPR_NOACCESS,
6971 &spr_read_generic, &spr_write_generic,
6972 0x00000000);
6973 /* LDSTCR */
6974 /* XXX : not implemented */
6975 spr_register(env, SPR_LDSTCR, "LDSTCR",
6976 SPR_NOACCESS, SPR_NOACCESS,
6977 &spr_read_generic, &spr_write_generic,
6978 0x00000000);
6979 /* ICTRL */
6980 /* XXX : not implemented */
6981 spr_register(env, SPR_ICTRL, "ICTRL",
6982 SPR_NOACCESS, SPR_NOACCESS,
6983 &spr_read_generic, &spr_write_generic,
6984 0x00000000);
6985 /* MSSSR0 */
6986 /* XXX : not implemented */
6987 spr_register(env, SPR_MSSSR0, "MSSSR0",
6988 SPR_NOACCESS, SPR_NOACCESS,
6989 &spr_read_generic, &spr_write_generic,
6990 0x00000000);
6991 /* PMC */
6992 /* XXX : not implemented */
6993 spr_register(env, SPR_PMC5, "PMC5",
6994 SPR_NOACCESS, SPR_NOACCESS,
6995 &spr_read_generic, &spr_write_generic,
6996 0x00000000);
6997 /* XXX : not implemented */
6998 spr_register(env, SPR_UPMC5, "UPMC5",
6999 &spr_read_ureg, SPR_NOACCESS,
7000 &spr_read_ureg, SPR_NOACCESS,
7001 0x00000000);
7002 /* XXX : not implemented */
7003 spr_register(env, SPR_PMC6, "PMC6",
7004 SPR_NOACCESS, SPR_NOACCESS,
7005 &spr_read_generic, &spr_write_generic,
7006 0x00000000);
7007 /* XXX : not implemented */
7008 spr_register(env, SPR_UPMC6, "UPMC6",
7009 &spr_read_ureg, SPR_NOACCESS,
7010 &spr_read_ureg, SPR_NOACCESS,
7011 0x00000000);
7012 /* SPRGs */
7013 spr_register(env, SPR_SPRG4, "SPRG4",
7014 SPR_NOACCESS, SPR_NOACCESS,
7015 &spr_read_generic, &spr_write_generic,
7016 0x00000000);
7017 spr_register(env, SPR_USPRG4, "USPRG4",
7018 &spr_read_ureg, SPR_NOACCESS,
7019 &spr_read_ureg, SPR_NOACCESS,
7020 0x00000000);
7021 spr_register(env, SPR_SPRG5, "SPRG5",
7022 SPR_NOACCESS, SPR_NOACCESS,
7023 &spr_read_generic, &spr_write_generic,
7024 0x00000000);
7025 spr_register(env, SPR_USPRG5, "USPRG5",
7026 &spr_read_ureg, SPR_NOACCESS,
7027 &spr_read_ureg, SPR_NOACCESS,
7028 0x00000000);
7029 spr_register(env, SPR_SPRG6, "SPRG6",
7030 SPR_NOACCESS, SPR_NOACCESS,
7031 &spr_read_generic, &spr_write_generic,
7032 0x00000000);
7033 spr_register(env, SPR_USPRG6, "USPRG6",
7034 &spr_read_ureg, SPR_NOACCESS,
7035 &spr_read_ureg, SPR_NOACCESS,
7036 0x00000000);
7037 spr_register(env, SPR_SPRG7, "SPRG7",
7038 SPR_NOACCESS, SPR_NOACCESS,
7039 &spr_read_generic, &spr_write_generic,
7040 0x00000000);
7041 spr_register(env, SPR_USPRG7, "USPRG7",
7042 &spr_read_ureg, SPR_NOACCESS,
7043 &spr_read_ureg, SPR_NOACCESS,
7044 0x00000000);
7045 /* Memory management */
7046 gen_low_BATs(env);
7047 gen_high_BATs(env);
7048 gen_74xx_soft_tlb(env, 128, 2);
7049 init_excp_7450(env);
7050 env->dcache_line_size = 32;
7051 env->icache_line_size = 32;
7052 /* Allocate hardware IRQ controller */
7053 ppc6xx_irq_init(env);
7054 }
7055
7056 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7057 {
7058 DeviceClass *dc = DEVICE_CLASS(oc);
7059 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7060
7061 dc->desc = "PowerPC 7457 (aka G4)";
7062 pcc->init_proc = init_proc_7457;
7063 pcc->check_pow = check_pow_hid0_74xx;
7064 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7065 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7066 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7067 PPC_FLOAT_STFIWX |
7068 PPC_CACHE | PPC_CACHE_ICBI |
7069 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7070 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7071 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7072 PPC_MEM_TLBIA | PPC_74xx_TLB |
7073 PPC_SEGMENT | PPC_EXTERN |
7074 PPC_ALTIVEC;
7075 pcc->msr_mask = (1ull << MSR_VR) |
7076 (1ull << MSR_POW) |
7077 (1ull << MSR_ILE) |
7078 (1ull << MSR_EE) |
7079 (1ull << MSR_PR) |
7080 (1ull << MSR_FP) |
7081 (1ull << MSR_ME) |
7082 (1ull << MSR_FE0) |
7083 (1ull << MSR_SE) |
7084 (1ull << MSR_DE) |
7085 (1ull << MSR_FE1) |
7086 (1ull << MSR_EP) |
7087 (1ull << MSR_IR) |
7088 (1ull << MSR_DR) |
7089 (1ull << MSR_PMM) |
7090 (1ull << MSR_RI) |
7091 (1ull << MSR_LE);
7092 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7093 pcc->excp_model = POWERPC_EXCP_74xx;
7094 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7095 pcc->bfd_mach = bfd_mach_ppc_7400;
7096 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7097 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7098 POWERPC_FLAG_BUS_CLK;
7099 }
7100
7101 static void init_proc_e600 (CPUPPCState *env)
7102 {
7103 gen_spr_ne_601(env);
7104 gen_spr_7xx(env);
7105 /* Time base */
7106 gen_tbl(env);
7107 /* 74xx specific SPR */
7108 gen_spr_74xx(env);
7109 /* XXX : not implemented */
7110 spr_register(env, SPR_UBAMR, "UBAMR",
7111 &spr_read_ureg, SPR_NOACCESS,
7112 &spr_read_ureg, SPR_NOACCESS,
7113 0x00000000);
7114 /* XXX : not implemented */
7115 spr_register(env, SPR_LDSTCR, "LDSTCR",
7116 SPR_NOACCESS, SPR_NOACCESS,
7117 &spr_read_generic, &spr_write_generic,
7118 0x00000000);
7119 /* XXX : not implemented */
7120 spr_register(env, SPR_ICTRL, "ICTRL",
7121 SPR_NOACCESS, SPR_NOACCESS,
7122 &spr_read_generic, &spr_write_generic,
7123 0x00000000);
7124 /* XXX : not implemented */
7125 spr_register(env, SPR_MSSSR0, "MSSSR0",
7126 SPR_NOACCESS, SPR_NOACCESS,
7127 &spr_read_generic, &spr_write_generic,
7128 0x00000000);
7129 /* XXX : not implemented */
7130 spr_register(env, SPR_PMC5, "PMC5",
7131 SPR_NOACCESS, SPR_NOACCESS,
7132 &spr_read_generic, &spr_write_generic,
7133 0x00000000);
7134 /* XXX : not implemented */
7135 spr_register(env, SPR_UPMC5, "UPMC5",
7136 &spr_read_ureg, SPR_NOACCESS,
7137 &spr_read_ureg, SPR_NOACCESS,
7138 0x00000000);
7139 /* XXX : not implemented */
7140 spr_register(env, SPR_PMC6, "PMC6",
7141 SPR_NOACCESS, SPR_NOACCESS,
7142 &spr_read_generic, &spr_write_generic,
7143 0x00000000);
7144 /* XXX : not implemented */
7145 spr_register(env, SPR_UPMC6, "UPMC6",
7146 &spr_read_ureg, SPR_NOACCESS,
7147 &spr_read_ureg, SPR_NOACCESS,
7148 0x00000000);
7149 /* SPRGs */
7150 spr_register(env, SPR_SPRG4, "SPRG4",
7151 SPR_NOACCESS, SPR_NOACCESS,
7152 &spr_read_generic, &spr_write_generic,
7153 0x00000000);
7154 spr_register(env, SPR_USPRG4, "USPRG4",
7155 &spr_read_ureg, SPR_NOACCESS,
7156 &spr_read_ureg, SPR_NOACCESS,
7157 0x00000000);
7158 spr_register(env, SPR_SPRG5, "SPRG5",
7159 SPR_NOACCESS, SPR_NOACCESS,
7160 &spr_read_generic, &spr_write_generic,
7161 0x00000000);
7162 spr_register(env, SPR_USPRG5, "USPRG5",
7163 &spr_read_ureg, SPR_NOACCESS,
7164 &spr_read_ureg, SPR_NOACCESS,
7165 0x00000000);
7166 spr_register(env, SPR_SPRG6, "SPRG6",
7167 SPR_NOACCESS, SPR_NOACCESS,
7168 &spr_read_generic, &spr_write_generic,
7169 0x00000000);
7170 spr_register(env, SPR_USPRG6, "USPRG6",
7171 &spr_read_ureg, SPR_NOACCESS,
7172 &spr_read_ureg, SPR_NOACCESS,
7173 0x00000000);
7174 spr_register(env, SPR_SPRG7, "SPRG7",
7175 SPR_NOACCESS, SPR_NOACCESS,
7176 &spr_read_generic, &spr_write_generic,
7177 0x00000000);
7178 spr_register(env, SPR_USPRG7, "USPRG7",
7179 &spr_read_ureg, SPR_NOACCESS,
7180 &spr_read_ureg, SPR_NOACCESS,
7181 0x00000000);
7182 /* Memory management */
7183 gen_low_BATs(env);
7184 gen_high_BATs(env);
7185 gen_74xx_soft_tlb(env, 128, 2);
7186 init_excp_7450(env);
7187 env->dcache_line_size = 32;
7188 env->icache_line_size = 32;
7189 /* Allocate hardware IRQ controller */
7190 ppc6xx_irq_init(env);
7191 }
7192
7193 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7194 {
7195 DeviceClass *dc = DEVICE_CLASS(oc);
7196 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7197
7198 dc->desc = "PowerPC e600";
7199 pcc->init_proc = init_proc_e600;
7200 pcc->check_pow = check_pow_hid0_74xx;
7201 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7202 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7203 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7204 PPC_FLOAT_STFIWX |
7205 PPC_CACHE | PPC_CACHE_ICBI |
7206 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7207 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7208 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7209 PPC_MEM_TLBIA | PPC_74xx_TLB |
7210 PPC_SEGMENT | PPC_EXTERN |
7211 PPC_ALTIVEC;
7212 pcc->insns_flags2 = PPC_NONE;
7213 pcc->msr_mask = (1ull << MSR_VR) |
7214 (1ull << MSR_POW) |
7215 (1ull << MSR_ILE) |
7216 (1ull << MSR_EE) |
7217 (1ull << MSR_PR) |
7218 (1ull << MSR_FP) |
7219 (1ull << MSR_ME) |
7220 (1ull << MSR_FE0) |
7221 (1ull << MSR_SE) |
7222 (1ull << MSR_DE) |
7223 (1ull << MSR_FE1) |
7224 (1ull << MSR_EP) |
7225 (1ull << MSR_IR) |
7226 (1ull << MSR_DR) |
7227 (1ull << MSR_PMM) |
7228 (1ull << MSR_RI) |
7229 (1ull << MSR_LE);
7230 pcc->mmu_model = POWERPC_MMU_32B;
7231 #if defined(CONFIG_SOFTMMU)
7232 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7233 #endif
7234 pcc->excp_model = POWERPC_EXCP_74xx;
7235 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7236 pcc->bfd_mach = bfd_mach_ppc_7400;
7237 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7238 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7239 POWERPC_FLAG_BUS_CLK;
7240 }
7241
7242 #if defined (TARGET_PPC64)
7243 #if defined(CONFIG_USER_ONLY)
7244 #define POWERPC970_HID5_INIT 0x00000080
7245 #else
7246 #define POWERPC970_HID5_INIT 0x00000000
7247 #endif
7248
7249 static int check_pow_970 (CPUPPCState *env)
7250 {
7251 if (env->spr[SPR_HID0] & 0x00600000)
7252 return 1;
7253
7254 return 0;
7255 }
7256
7257 static void init_proc_970 (CPUPPCState *env)
7258 {
7259 gen_spr_ne_601(env);
7260 gen_spr_7xx(env);
7261 /* Time base */
7262 gen_tbl(env);
7263 /* Hardware implementation registers */
7264 /* XXX : not implemented */
7265 spr_register(env, SPR_HID0, "HID0",
7266 SPR_NOACCESS, SPR_NOACCESS,
7267 &spr_read_generic, &spr_write_clear,
7268 0x60000000);
7269 /* XXX : not implemented */
7270 spr_register(env, SPR_HID1, "HID1",
7271 SPR_NOACCESS, SPR_NOACCESS,
7272 &spr_read_generic, &spr_write_generic,
7273 0x00000000);
7274 /* XXX : not implemented */
7275 spr_register(env, SPR_970_HID5, "HID5",
7276 SPR_NOACCESS, SPR_NOACCESS,
7277 &spr_read_generic, &spr_write_generic,
7278 POWERPC970_HID5_INIT);
7279 /* Memory management */
7280 /* XXX: not correct */
7281 gen_low_BATs(env);
7282 spr_register(env, SPR_HIOR, "SPR_HIOR",
7283 SPR_NOACCESS, SPR_NOACCESS,
7284 &spr_read_hior, &spr_write_hior,
7285 0x00000000);
7286 #if !defined(CONFIG_USER_ONLY)
7287 env->slb_nr = 32;
7288 #endif
7289 init_excp_970(env);
7290 env->dcache_line_size = 128;
7291 env->icache_line_size = 128;
7292 /* Allocate hardware IRQ controller */
7293 ppc970_irq_init(env);
7294 /* Can't find information on what this should be on reset. This
7295 * value is the one used by 74xx processors. */
7296 vscr_init(env, 0x00010000);
7297 }
7298
7299 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7300 {
7301 DeviceClass *dc = DEVICE_CLASS(oc);
7302 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7303
7304 dc->desc = "PowerPC 970";
7305 pcc->init_proc = init_proc_970;
7306 pcc->check_pow = check_pow_970;
7307 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7308 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7309 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7310 PPC_FLOAT_STFIWX |
7311 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7312 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7313 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7314 PPC_64B | PPC_ALTIVEC |
7315 PPC_SEGMENT_64B | PPC_SLBI;
7316 pcc->msr_mask = (1ull << MSR_SF) |
7317 (1ull << MSR_SHV) |
7318 (1ull << MSR_VR) |
7319 (1ull << MSR_POW) |
7320 (1ull << MSR_EE) |
7321 (1ull << MSR_PR) |
7322 (1ull << MSR_FP) |
7323 (1ull << MSR_ME) |
7324 (1ull << MSR_FE0) |
7325 (1ull << MSR_SE) |
7326 (1ull << MSR_DE) |
7327 (1ull << MSR_FE1) |
7328 (1ull << MSR_IR) |
7329 (1ull << MSR_DR) |
7330 (1ull << MSR_PMM) |
7331 (1ull << MSR_RI);
7332 pcc->mmu_model = POWERPC_MMU_64B;
7333 #if defined(CONFIG_SOFTMMU)
7334 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7335 #endif
7336 pcc->excp_model = POWERPC_EXCP_970;
7337 pcc->bus_model = PPC_FLAGS_INPUT_970;
7338 pcc->bfd_mach = bfd_mach_ppc64;
7339 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7340 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7341 POWERPC_FLAG_BUS_CLK;
7342 pcc->l1_dcache_size = 0x8000;
7343 pcc->l1_icache_size = 0x10000;
7344 }
7345
7346 static int check_pow_970FX (CPUPPCState *env)
7347 {
7348 if (env->spr[SPR_HID0] & 0x00600000)
7349 return 1;
7350
7351 return 0;
7352 }
7353
7354 static void init_proc_970FX (CPUPPCState *env)
7355 {
7356 gen_spr_ne_601(env);
7357 gen_spr_7xx(env);
7358 /* Time base */
7359 gen_tbl(env);
7360 /* Hardware implementation registers */
7361 /* XXX : not implemented */
7362 spr_register(env, SPR_HID0, "HID0",
7363 SPR_NOACCESS, SPR_NOACCESS,
7364 &spr_read_generic, &spr_write_clear,
7365 0x60000000);
7366 /* XXX : not implemented */
7367 spr_register(env, SPR_HID1, "HID1",
7368 SPR_NOACCESS, SPR_NOACCESS,
7369 &spr_read_generic, &spr_write_generic,
7370 0x00000000);
7371 /* XXX : not implemented */
7372 spr_register(env, SPR_970_HID5, "HID5",
7373 SPR_NOACCESS, SPR_NOACCESS,
7374 &spr_read_generic, &spr_write_generic,
7375 POWERPC970_HID5_INIT);
7376 /* Memory management */
7377 /* XXX: not correct */
7378 gen_low_BATs(env);
7379 spr_register(env, SPR_HIOR, "SPR_HIOR",
7380 SPR_NOACCESS, SPR_NOACCESS,
7381 &spr_read_hior, &spr_write_hior,
7382 0x00000000);
7383 spr_register(env, SPR_CTRL, "SPR_CTRL",
7384 SPR_NOACCESS, SPR_NOACCESS,
7385 SPR_NOACCESS, &spr_write_generic,
7386 0x00000000);
7387 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7388 SPR_NOACCESS, SPR_NOACCESS,
7389 &spr_read_generic, SPR_NOACCESS,
7390 0x00000000);
7391 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7392 &spr_read_generic, &spr_write_generic,
7393 &spr_read_generic, &spr_write_generic,
7394 0x00000000);
7395 #if !defined(CONFIG_USER_ONLY)
7396 env->slb_nr = 64;
7397 #endif
7398 init_excp_970(env);
7399 env->dcache_line_size = 128;
7400 env->icache_line_size = 128;
7401 /* Allocate hardware IRQ controller */
7402 ppc970_irq_init(env);
7403 /* Can't find information on what this should be on reset. This
7404 * value is the one used by 74xx processors. */
7405 vscr_init(env, 0x00010000);
7406 }
7407
7408 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
7409 {
7410 DeviceClass *dc = DEVICE_CLASS(oc);
7411 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7412
7413 dc->desc = "PowerPC 970FX (aka G5)";
7414 pcc->init_proc = init_proc_970FX;
7415 pcc->check_pow = check_pow_970FX;
7416 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7417 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7418 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7419 PPC_FLOAT_STFIWX |
7420 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7421 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7422 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7423 PPC_64B | PPC_ALTIVEC |
7424 PPC_SEGMENT_64B | PPC_SLBI;
7425 pcc->msr_mask = (1ull << MSR_SF) |
7426 (1ull << MSR_VR) |
7427 (1ull << MSR_POW) |
7428 (1ull << MSR_EE) |
7429 (1ull << MSR_PR) |
7430 (1ull << MSR_FP) |
7431 (1ull << MSR_ME) |
7432 (1ull << MSR_FE0) |
7433 (1ull << MSR_SE) |
7434 (1ull << MSR_DE) |
7435 (1ull << MSR_FE1) |
7436 (1ull << MSR_IR) |
7437 (1ull << MSR_DR) |
7438 (1ull << MSR_PMM) |
7439 (1ull << MSR_RI);
7440 pcc->mmu_model = POWERPC_MMU_64B;
7441 #if defined(CONFIG_SOFTMMU)
7442 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7443 #endif
7444 pcc->excp_model = POWERPC_EXCP_970;
7445 pcc->bus_model = PPC_FLAGS_INPUT_970;
7446 pcc->bfd_mach = bfd_mach_ppc64;
7447 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7448 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7449 POWERPC_FLAG_BUS_CLK;
7450 pcc->l1_dcache_size = 0x8000;
7451 pcc->l1_icache_size = 0x10000;
7452 }
7453
7454 static int check_pow_970MP (CPUPPCState *env)
7455 {
7456 if (env->spr[SPR_HID0] & 0x01C00000)
7457 return 1;
7458
7459 return 0;
7460 }
7461
7462 static void init_proc_970MP (CPUPPCState *env)
7463 {
7464 gen_spr_ne_601(env);
7465 gen_spr_7xx(env);
7466 /* Time base */
7467 gen_tbl(env);
7468 /* Hardware implementation registers */
7469 /* XXX : not implemented */
7470 spr_register(env, SPR_HID0, "HID0",
7471 SPR_NOACCESS, SPR_NOACCESS,
7472 &spr_read_generic, &spr_write_clear,
7473 0x60000000);
7474 /* XXX : not implemented */
7475 spr_register(env, SPR_HID1, "HID1",
7476 SPR_NOACCESS, SPR_NOACCESS,
7477 &spr_read_generic, &spr_write_generic,
7478 0x00000000);
7479 /* XXX : not implemented */
7480 spr_register(env, SPR_970_HID5, "HID5",
7481 SPR_NOACCESS, SPR_NOACCESS,
7482 &spr_read_generic, &spr_write_generic,
7483 POWERPC970_HID5_INIT);
7484 /* XXX : not implemented */
7485 /* Memory management */
7486 /* XXX: not correct */
7487 gen_low_BATs(env);
7488 spr_register(env, SPR_HIOR, "SPR_HIOR",
7489 SPR_NOACCESS, SPR_NOACCESS,
7490 &spr_read_hior, &spr_write_hior,
7491 0x00000000);
7492 /* Logical partitionning */
7493 spr_register_kvm(env, SPR_LPCR, "LPCR",
7494 SPR_NOACCESS, SPR_NOACCESS,
7495 &spr_read_generic, &spr_write_generic,
7496 KVM_REG_PPC_LPCR, 0x00000000);
7497 #if !defined(CONFIG_USER_ONLY)
7498 env->slb_nr = 32;
7499 #endif
7500 init_excp_970(env);
7501 env->dcache_line_size = 128;
7502 env->icache_line_size = 128;
7503 /* Allocate hardware IRQ controller */
7504 ppc970_irq_init(env);
7505 /* Can't find information on what this should be on reset. This
7506 * value is the one used by 74xx processors. */
7507 vscr_init(env, 0x00010000);
7508 }
7509
7510 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
7511 {
7512 DeviceClass *dc = DEVICE_CLASS(oc);
7513 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7514
7515 dc->desc = "PowerPC 970 MP";
7516 pcc->init_proc = init_proc_970MP;
7517 pcc->check_pow = check_pow_970MP;
7518 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7519 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7520 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7521 PPC_FLOAT_STFIWX |
7522 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7523 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7524 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7525 PPC_64B | PPC_ALTIVEC |
7526 PPC_SEGMENT_64B | PPC_SLBI;
7527 pcc->msr_mask = (1ull << MSR_SF) |
7528 (1ull << MSR_SHV) |
7529 (1ull << MSR_VR) |
7530 (1ull << MSR_POW) |
7531 (1ull << MSR_EE) |
7532 (1ull << MSR_PR) |
7533 (1ull << MSR_FP) |
7534 (1ull << MSR_ME) |
7535 (1ull << MSR_FE0) |
7536 (1ull << MSR_SE) |
7537 (1ull << MSR_DE) |
7538 (1ull << MSR_FE1) |
7539 (1ull << MSR_IR) |
7540 (1ull << MSR_DR) |
7541 (1ull << MSR_PMM) |
7542 (1ull << MSR_RI);
7543 pcc->mmu_model = POWERPC_MMU_64B;
7544 #if defined(CONFIG_SOFTMMU)
7545 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7546 #endif
7547 pcc->excp_model = POWERPC_EXCP_970;
7548 pcc->bus_model = PPC_FLAGS_INPUT_970;
7549 pcc->bfd_mach = bfd_mach_ppc64;
7550 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7551 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7552 POWERPC_FLAG_BUS_CLK;
7553 pcc->l1_dcache_size = 0x8000;
7554 pcc->l1_icache_size = 0x10000;
7555 }
7556
7557 static void init_proc_power5plus(CPUPPCState *env)
7558 {
7559 gen_spr_ne_601(env);
7560 gen_spr_7xx(env);
7561 /* Time base */
7562 gen_tbl(env);
7563 /* Hardware implementation registers */
7564 /* XXX : not implemented */
7565 spr_register(env, SPR_HID0, "HID0",
7566 SPR_NOACCESS, SPR_NOACCESS,
7567 &spr_read_generic, &spr_write_clear,
7568 0x60000000);
7569 /* XXX : not implemented */
7570 spr_register(env, SPR_HID1, "HID1",
7571 SPR_NOACCESS, SPR_NOACCESS,
7572 &spr_read_generic, &spr_write_generic,
7573 0x00000000);
7574 /* XXX : not implemented */
7575 spr_register(env, SPR_970_HID5, "HID5",
7576 SPR_NOACCESS, SPR_NOACCESS,
7577 &spr_read_generic, &spr_write_generic,
7578 POWERPC970_HID5_INIT);
7579 /* Memory management */
7580 /* XXX: not correct */
7581 gen_low_BATs(env);
7582 spr_register(env, SPR_HIOR, "SPR_HIOR",
7583 SPR_NOACCESS, SPR_NOACCESS,
7584 &spr_read_hior, &spr_write_hior,
7585 0x00000000);
7586 spr_register(env, SPR_CTRL, "SPR_CTRL",
7587 SPR_NOACCESS, SPR_NOACCESS,
7588 SPR_NOACCESS, &spr_write_generic,
7589 0x00000000);
7590 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7591 SPR_NOACCESS, SPR_NOACCESS,
7592 &spr_read_generic, SPR_NOACCESS,
7593 0x00000000);
7594 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7595 &spr_read_generic, &spr_write_generic,
7596 &spr_read_generic, &spr_write_generic,
7597 0x00000000);
7598 /* Logical partitionning */
7599 spr_register_kvm(env, SPR_LPCR, "LPCR",
7600 SPR_NOACCESS, SPR_NOACCESS,
7601 &spr_read_generic, &spr_write_generic,
7602 KVM_REG_PPC_LPCR, 0x00000000);
7603 #if !defined(CONFIG_USER_ONLY)
7604 env->slb_nr = 64;
7605 #endif
7606 init_excp_970(env);
7607 env->dcache_line_size = 128;
7608 env->icache_line_size = 128;
7609 /* Allocate hardware IRQ controller */
7610 ppc970_irq_init(env);
7611 /* Can't find information on what this should be on reset. This
7612 * value is the one used by 74xx processors. */
7613 vscr_init(env, 0x00010000);
7614 }
7615
7616 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7617 {
7618 DeviceClass *dc = DEVICE_CLASS(oc);
7619 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7620
7621 dc->fw_name = "PowerPC,POWER5";
7622 dc->desc = "POWER5+";
7623 pcc->init_proc = init_proc_power5plus;
7624 pcc->check_pow = check_pow_970FX;
7625 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7626 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7627 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7628 PPC_FLOAT_STFIWX |
7629 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7630 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7631 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7632 PPC_64B |
7633 PPC_SEGMENT_64B | PPC_SLBI;
7634 pcc->msr_mask = (1ull << MSR_SF) |
7635 (1ull << MSR_VR) |
7636 (1ull << MSR_POW) |
7637 (1ull << MSR_EE) |
7638 (1ull << MSR_PR) |
7639 (1ull << MSR_FP) |
7640 (1ull << MSR_ME) |
7641 (1ull << MSR_FE0) |
7642 (1ull << MSR_SE) |
7643 (1ull << MSR_DE) |
7644 (1ull << MSR_FE1) |
7645 (1ull << MSR_IR) |
7646 (1ull << MSR_DR) |
7647 (1ull << MSR_PMM) |
7648 (1ull << MSR_RI);
7649 pcc->mmu_model = POWERPC_MMU_64B;
7650 #if defined(CONFIG_SOFTMMU)
7651 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7652 #endif
7653 pcc->excp_model = POWERPC_EXCP_970;
7654 pcc->bus_model = PPC_FLAGS_INPUT_970;
7655 pcc->bfd_mach = bfd_mach_ppc64;
7656 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7657 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7658 POWERPC_FLAG_BUS_CLK;
7659 pcc->l1_dcache_size = 0x8000;
7660 pcc->l1_icache_size = 0x10000;
7661 }
7662
7663 static void init_proc_POWER7 (CPUPPCState *env)
7664 {
7665 gen_spr_ne_601(env);
7666 gen_spr_7xx(env);
7667 /* Time base */
7668 gen_tbl(env);
7669 /* Processor identification */
7670 spr_register(env, SPR_PIR, "PIR",
7671 SPR_NOACCESS, SPR_NOACCESS,
7672 &spr_read_generic, &spr_write_pir,
7673 0x00000000);
7674 #if !defined(CONFIG_USER_ONLY)
7675 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7676 spr_register_kvm(env, SPR_PURR, "PURR",
7677 &spr_read_purr, SPR_NOACCESS,
7678 &spr_read_purr, SPR_NOACCESS,
7679 KVM_REG_PPC_PURR, 0x00000000);
7680 spr_register_kvm(env, SPR_SPURR, "SPURR",
7681 &spr_read_purr, SPR_NOACCESS,
7682 &spr_read_purr, SPR_NOACCESS,
7683 KVM_REG_PPC_SPURR, 0x00000000);
7684 spr_register(env, SPR_CFAR, "SPR_CFAR",
7685 SPR_NOACCESS, SPR_NOACCESS,
7686 &spr_read_cfar, &spr_write_cfar,
7687 0x00000000);
7688 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7689 SPR_NOACCESS, SPR_NOACCESS,
7690 &spr_read_generic, &spr_write_generic,
7691 KVM_REG_PPC_DSCR, 0x00000000);
7692 spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
7693 SPR_NOACCESS, SPR_NOACCESS,
7694 &spr_read_generic, &spr_write_generic,
7695 KVM_REG_PPC_MMCRA, 0x00000000);
7696 spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
7697 SPR_NOACCESS, SPR_NOACCESS,
7698 &spr_read_generic, &spr_write_generic,
7699 KVM_REG_PPC_PMC5, 0x00000000);
7700 spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
7701 SPR_NOACCESS, SPR_NOACCESS,
7702 &spr_read_generic, &spr_write_generic,
7703 KVM_REG_PPC_PMC6, 0x00000000);
7704 #endif /* !CONFIG_USER_ONLY */
7705 gen_spr_amr(env);
7706 /* XXX : not implemented */
7707 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7708 SPR_NOACCESS, SPR_NOACCESS,
7709 SPR_NOACCESS, &spr_write_generic,
7710 0x80800000);
7711 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7712 SPR_NOACCESS, SPR_NOACCESS,
7713 &spr_read_generic, SPR_NOACCESS,
7714 0x80800000);
7715 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7716 &spr_read_generic, &spr_write_generic,
7717 &spr_read_generic, &spr_write_generic,
7718 0x00000000);
7719 spr_register(env, SPR_PPR, "PPR",
7720 &spr_read_generic, &spr_write_generic,
7721 &spr_read_generic, &spr_write_generic,
7722 0x00000000);
7723 /* Logical partitionning */
7724 spr_register_kvm(env, SPR_LPCR, "LPCR",
7725 SPR_NOACCESS, SPR_NOACCESS,
7726 &spr_read_generic, &spr_write_generic,
7727 KVM_REG_PPC_LPCR, 0x00000000);
7728 #if !defined(CONFIG_USER_ONLY)
7729 env->slb_nr = 32;
7730 #endif
7731 init_excp_POWER7(env);
7732 env->dcache_line_size = 128;
7733 env->icache_line_size = 128;
7734
7735 /* Allocate hardware IRQ controller */
7736 ppcPOWER7_irq_init(env);
7737 /* Can't find information on what this should be on reset. This
7738 * value is the one used by 74xx processors. */
7739 vscr_init(env, 0x00010000);
7740 }
7741
7742 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7743 {
7744 DeviceClass *dc = DEVICE_CLASS(oc);
7745 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7746
7747 dc->fw_name = "PowerPC,POWER7";
7748 dc->desc = "POWER7";
7749 pcc->pvr = CPU_POWERPC_POWER7_BASE;
7750 pcc->pvr_mask = CPU_POWERPC_POWER7_MASK;
7751 pcc->init_proc = init_proc_POWER7;
7752 pcc->check_pow = check_pow_nocheck;
7753 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7754 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7755 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7756 PPC_FLOAT_FRSQRTES |
7757 PPC_FLOAT_STFIWX |
7758 PPC_FLOAT_EXT |
7759 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7760 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7761 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7762 PPC_64B | PPC_ALTIVEC |
7763 PPC_SEGMENT_64B | PPC_SLBI |
7764 PPC_POPCNTB | PPC_POPCNTWD;
7765 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7766 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7767 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7768 PPC2_FP_TST_ISA206;
7769 pcc->msr_mask = (1ull << MSR_SF) |
7770 (1ull << MSR_VR) |
7771 (1ull << MSR_VSX) |
7772 (1ull << MSR_EE) |
7773 (1ull << MSR_PR) |
7774 (1ull << MSR_FP) |
7775 (1ull << MSR_ME) |
7776 (1ull << MSR_FE0) |
7777 (1ull << MSR_SE) |
7778 (1ull << MSR_DE) |
7779 (1ull << MSR_FE1) |
7780 (1ull << MSR_IR) |
7781 (1ull << MSR_DR) |
7782 (1ull << MSR_PMM) |
7783 (1ull << MSR_RI) |
7784 (1ull << MSR_LE);
7785 pcc->mmu_model = POWERPC_MMU_2_06;
7786 #if defined(CONFIG_SOFTMMU)
7787 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7788 #endif
7789 pcc->excp_model = POWERPC_EXCP_POWER7;
7790 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7791 pcc->bfd_mach = bfd_mach_ppc64;
7792 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7793 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7794 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7795 POWERPC_FLAG_VSX;
7796 pcc->l1_dcache_size = 0x8000;
7797 pcc->l1_icache_size = 0x8000;
7798 }
7799
7800 POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
7801 {
7802 DeviceClass *dc = DEVICE_CLASS(oc);
7803 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7804
7805 dc->fw_name = "PowerPC,POWER7+";
7806 dc->desc = "POWER7+";
7807 pcc->pvr = CPU_POWERPC_POWER7P_BASE;
7808 pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK;
7809 pcc->init_proc = init_proc_POWER7;
7810 pcc->check_pow = check_pow_nocheck;
7811 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7812 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7813 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7814 PPC_FLOAT_FRSQRTES |
7815 PPC_FLOAT_STFIWX |
7816 PPC_FLOAT_EXT |
7817 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7818 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7819 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7820 PPC_64B | PPC_ALTIVEC |
7821 PPC_SEGMENT_64B | PPC_SLBI |
7822 PPC_POPCNTB | PPC_POPCNTWD;
7823 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7824 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7825 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7826 PPC2_FP_TST_ISA206;
7827 pcc->msr_mask = (1ull << MSR_SF) |
7828 (1ull << MSR_VR) |
7829 (1ull << MSR_VSX) |
7830 (1ull << MSR_EE) |
7831 (1ull << MSR_PR) |
7832 (1ull << MSR_FP) |
7833 (1ull << MSR_ME) |
7834 (1ull << MSR_FE0) |
7835 (1ull << MSR_SE) |
7836 (1ull << MSR_DE) |
7837 (1ull << MSR_FE1) |
7838 (1ull << MSR_IR) |
7839 (1ull << MSR_DR) |
7840 (1ull << MSR_PMM) |
7841 (1ull << MSR_RI) |
7842 (1ull << MSR_LE);
7843 pcc->mmu_model = POWERPC_MMU_2_06;
7844 #if defined(CONFIG_SOFTMMU)
7845 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7846 #endif
7847 pcc->excp_model = POWERPC_EXCP_POWER7;
7848 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7849 pcc->bfd_mach = bfd_mach_ppc64;
7850 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7851 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7852 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7853 POWERPC_FLAG_VSX;
7854 pcc->l1_dcache_size = 0x8000;
7855 pcc->l1_icache_size = 0x8000;
7856 }
7857
7858 static void init_proc_POWER8(CPUPPCState *env)
7859 {
7860 /* inherit P7 */
7861 init_proc_POWER7(env);
7862
7863 /* P8 supports the TAR */
7864 spr_register(env, SPR_TAR, "TAR",
7865 &spr_read_generic, &spr_write_generic,
7866 &spr_read_generic, &spr_write_generic,
7867 0x00000000);
7868 }
7869
7870 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7871 {
7872 DeviceClass *dc = DEVICE_CLASS(oc);
7873 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7874
7875 dc->fw_name = "PowerPC,POWER8";
7876 dc->desc = "POWER8";
7877 pcc->pvr = CPU_POWERPC_POWER8_BASE;
7878 pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
7879 pcc->init_proc = init_proc_POWER8;
7880 pcc->check_pow = check_pow_nocheck;
7881 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7882 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7883 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7884 PPC_FLOAT_FRSQRTES |
7885 PPC_FLOAT_STFIWX |
7886 PPC_FLOAT_EXT |
7887 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7888 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7889 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7890 PPC_64B | PPC_64BX | PPC_ALTIVEC |
7891 PPC_SEGMENT_64B | PPC_SLBI |
7892 PPC_POPCNTB | PPC_POPCNTWD;
7893 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7894 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7895 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7896 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7897 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7898 PPC2_ISA205 | PPC2_ISA207S;
7899 pcc->msr_mask = (1ull << MSR_SF) |
7900 (1ull << MSR_VR) |
7901 (1ull << MSR_VSX) |
7902 (1ull << MSR_EE) |
7903 (1ull << MSR_PR) |
7904 (1ull << MSR_FP) |
7905 (1ull << MSR_ME) |
7906 (1ull << MSR_FE0) |
7907 (1ull << MSR_SE) |
7908 (1ull << MSR_DE) |
7909 (1ull << MSR_FE1) |
7910 (1ull << MSR_IR) |
7911 (1ull << MSR_DR) |
7912 (1ull << MSR_PMM) |
7913 (1ull << MSR_RI) |
7914 (1ull << MSR_LE);
7915 pcc->mmu_model = POWERPC_MMU_2_06;
7916 #if defined(CONFIG_SOFTMMU)
7917 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7918 #endif
7919 pcc->excp_model = POWERPC_EXCP_POWER7;
7920 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7921 pcc->bfd_mach = bfd_mach_ppc64;
7922 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7923 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7924 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7925 POWERPC_FLAG_VSX;
7926 pcc->l1_dcache_size = 0x8000;
7927 pcc->l1_icache_size = 0x8000;
7928 }
7929 #endif /* defined (TARGET_PPC64) */
7930
7931
7932 /*****************************************************************************/
7933 /* Generic CPU instantiation routine */
7934 static void init_ppc_proc(PowerPCCPU *cpu)
7935 {
7936 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7937 CPUPPCState *env = &cpu->env;
7938 #if !defined(CONFIG_USER_ONLY)
7939 int i;
7940
7941 env->irq_inputs = NULL;
7942 /* Set all exception vectors to an invalid address */
7943 for (i = 0; i < POWERPC_EXCP_NB; i++)
7944 env->excp_vectors[i] = (target_ulong)(-1ULL);
7945 env->ivor_mask = 0x00000000;
7946 env->ivpr_mask = 0x00000000;
7947 /* Default MMU definitions */
7948 env->nb_BATs = 0;
7949 env->nb_tlb = 0;
7950 env->nb_ways = 0;
7951 env->tlb_type = TLB_NONE;
7952 #endif
7953 /* Register SPR common to all PowerPC implementations */
7954 gen_spr_generic(env);
7955 spr_register(env, SPR_PVR, "PVR",
7956 /* Linux permits userspace to read PVR */
7957 #if defined(CONFIG_LINUX_USER)
7958 &spr_read_generic,
7959 #else
7960 SPR_NOACCESS,
7961 #endif
7962 SPR_NOACCESS,
7963 &spr_read_generic, SPR_NOACCESS,
7964 pcc->pvr);
7965 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7966 if (pcc->svr != POWERPC_SVR_NONE) {
7967 if (pcc->svr & POWERPC_SVR_E500) {
7968 spr_register(env, SPR_E500_SVR, "SVR",
7969 SPR_NOACCESS, SPR_NOACCESS,
7970 &spr_read_generic, SPR_NOACCESS,
7971 pcc->svr & ~POWERPC_SVR_E500);
7972 } else {
7973 spr_register(env, SPR_SVR, "SVR",
7974 SPR_NOACCESS, SPR_NOACCESS,
7975 &spr_read_generic, SPR_NOACCESS,
7976 pcc->svr);
7977 }
7978 }
7979 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7980 (*pcc->init_proc)(env);
7981
7982 /* MSR bits & flags consistency checks */
7983 if (env->msr_mask & (1 << 25)) {
7984 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7985 case POWERPC_FLAG_SPE:
7986 case POWERPC_FLAG_VRE:
7987 break;
7988 default:
7989 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7990 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7991 exit(1);
7992 }
7993 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7994 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7995 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7996 exit(1);
7997 }
7998 if (env->msr_mask & (1 << 17)) {
7999 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8000 case POWERPC_FLAG_TGPR:
8001 case POWERPC_FLAG_CE:
8002 break;
8003 default:
8004 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8005 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8006 exit(1);
8007 }
8008 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8009 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8010 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8011 exit(1);
8012 }
8013 if (env->msr_mask & (1 << 10)) {
8014 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8015 POWERPC_FLAG_UBLE)) {
8016 case POWERPC_FLAG_SE:
8017 case POWERPC_FLAG_DWE:
8018 case POWERPC_FLAG_UBLE:
8019 break;
8020 default:
8021 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8022 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8023 "POWERPC_FLAG_UBLE\n");
8024 exit(1);
8025 }
8026 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8027 POWERPC_FLAG_UBLE)) {
8028 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8029 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8030 "POWERPC_FLAG_UBLE\n");
8031 exit(1);
8032 }
8033 if (env->msr_mask & (1 << 9)) {
8034 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8035 case POWERPC_FLAG_BE:
8036 case POWERPC_FLAG_DE:
8037 break;
8038 default:
8039 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8040 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8041 exit(1);
8042 }
8043 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8044 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8045 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8046 exit(1);
8047 }
8048 if (env->msr_mask & (1 << 2)) {
8049 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8050 case POWERPC_FLAG_PX:
8051 case POWERPC_FLAG_PMM:
8052 break;
8053 default:
8054 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8055 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8056 exit(1);
8057 }
8058 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8059 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8060 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8061 exit(1);
8062 }
8063 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8064 fprintf(stderr, "PowerPC flags inconsistency\n"
8065 "Should define the time-base and decrementer clock source\n");
8066 exit(1);
8067 }
8068 /* Allocate TLBs buffer when needed */
8069 #if !defined(CONFIG_USER_ONLY)
8070 if (env->nb_tlb != 0) {
8071 int nb_tlb = env->nb_tlb;
8072 if (env->id_tlbs != 0)
8073 nb_tlb *= 2;
8074 switch (env->tlb_type) {
8075 case TLB_6XX:
8076 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8077 break;
8078 case TLB_EMB:
8079 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8080 break;
8081 case TLB_MAS:
8082 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8083 break;
8084 }
8085 /* Pre-compute some useful values */
8086 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8087 }
8088 if (env->irq_inputs == NULL) {
8089 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8090 " Attempt QEMU to crash very soon !\n");
8091 }
8092 #endif
8093 if (env->check_pow == NULL) {
8094 fprintf(stderr, "WARNING: no power management check handler "
8095 "registered.\n"
8096 " Attempt QEMU to crash very soon !\n");
8097 }
8098 }
8099
8100 #if defined(PPC_DUMP_CPU)
8101 static void dump_ppc_sprs (CPUPPCState *env)
8102 {
8103 ppc_spr_t *spr;
8104 #if !defined(CONFIG_USER_ONLY)
8105 uint32_t sr, sw;
8106 #endif
8107 uint32_t ur, uw;
8108 int i, j, n;
8109
8110 printf("Special purpose registers:\n");
8111 for (i = 0; i < 32; i++) {
8112 for (j = 0; j < 32; j++) {
8113 n = (i << 5) | j;
8114 spr = &env->spr_cb[n];
8115 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8116 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8117 #if !defined(CONFIG_USER_ONLY)
8118 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8119 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8120 if (sw || sr || uw || ur) {
8121 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8122 (i << 5) | j, (i << 5) | j, spr->name,
8123 sw ? 'w' : '-', sr ? 'r' : '-',
8124 uw ? 'w' : '-', ur ? 'r' : '-');
8125 }
8126 #else
8127 if (uw || ur) {
8128 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8129 (i << 5) | j, (i << 5) | j, spr->name,
8130 uw ? 'w' : '-', ur ? 'r' : '-');
8131 }
8132 #endif
8133 }
8134 }
8135 fflush(stdout);
8136 fflush(stderr);
8137 }
8138 #endif
8139
8140 /*****************************************************************************/
8141 #include <stdlib.h>
8142 #include <string.h>
8143
8144 /* Opcode types */
8145 enum {
8146 PPC_DIRECT = 0, /* Opcode routine */
8147 PPC_INDIRECT = 1, /* Indirect opcode table */
8148 };
8149
8150 static inline int is_indirect_opcode (void *handler)
8151 {
8152 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
8153 }
8154
8155 static inline opc_handler_t **ind_table(void *handler)
8156 {
8157 return (opc_handler_t **)((uintptr_t)handler & ~3);
8158 }
8159
8160 /* Instruction table creation */
8161 /* Opcodes tables creation */
8162 static void fill_new_table (opc_handler_t **table, int len)
8163 {
8164 int i;
8165
8166 for (i = 0; i < len; i++)
8167 table[i] = &invalid_handler;
8168 }
8169
8170 static int create_new_table (opc_handler_t **table, unsigned char idx)
8171 {
8172 opc_handler_t **tmp;
8173
8174 tmp = g_new(opc_handler_t *, 0x20);
8175 fill_new_table(tmp, 0x20);
8176 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8177
8178 return 0;
8179 }
8180
8181 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8182 opc_handler_t *handler)
8183 {
8184 if (table[idx] != &invalid_handler)
8185 return -1;
8186 table[idx] = handler;
8187
8188 return 0;
8189 }
8190
8191 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8192 unsigned char idx, opc_handler_t *handler)
8193 {
8194 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8195 printf("*** ERROR: opcode %02x already assigned in main "
8196 "opcode table\n", idx);
8197 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8198 printf(" Registered handler '%s' - new handler '%s'\n",
8199 ppc_opcodes[idx]->oname, handler->oname);
8200 #endif
8201 return -1;
8202 }
8203
8204 return 0;
8205 }
8206
8207 static int register_ind_in_table (opc_handler_t **table,
8208 unsigned char idx1, unsigned char idx2,
8209 opc_handler_t *handler)
8210 {
8211 if (table[idx1] == &invalid_handler) {
8212 if (create_new_table(table, idx1) < 0) {
8213 printf("*** ERROR: unable to create indirect table "
8214 "idx=%02x\n", idx1);
8215 return -1;
8216 }
8217 } else {
8218 if (!is_indirect_opcode(table[idx1])) {
8219 printf("*** ERROR: idx %02x already assigned to a direct "
8220 "opcode\n", idx1);
8221 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8222 printf(" Registered handler '%s' - new handler '%s'\n",
8223 ind_table(table[idx1])[idx2]->oname, handler->oname);
8224 #endif
8225 return -1;
8226 }
8227 }
8228 if (handler != NULL &&
8229 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8230 printf("*** ERROR: opcode %02x already assigned in "
8231 "opcode table %02x\n", idx2, idx1);
8232 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8233 printf(" Registered handler '%s' - new handler '%s'\n",
8234 ind_table(table[idx1])[idx2]->oname, handler->oname);
8235 #endif
8236 return -1;
8237 }
8238
8239 return 0;
8240 }
8241
8242 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8243 unsigned char idx1, unsigned char idx2,
8244 opc_handler_t *handler)
8245 {
8246 int ret;
8247
8248 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8249
8250 return ret;
8251 }
8252
8253 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8254 unsigned char idx1, unsigned char idx2,
8255 unsigned char idx3, opc_handler_t *handler)
8256 {
8257 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8258 printf("*** ERROR: unable to join indirect table idx "
8259 "[%02x-%02x]\n", idx1, idx2);
8260 return -1;
8261 }
8262 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8263 handler) < 0) {
8264 printf("*** ERROR: unable to insert opcode "
8265 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8266 return -1;
8267 }
8268
8269 return 0;
8270 }
8271
8272 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8273 {
8274 if (insn->opc2 != 0xFF) {
8275 if (insn->opc3 != 0xFF) {
8276 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8277 insn->opc3, &insn->handler) < 0)
8278 return -1;
8279 } else {
8280 if (register_ind_insn(ppc_opcodes, insn->opc1,
8281 insn->opc2, &insn->handler) < 0)
8282 return -1;
8283 }
8284 } else {
8285 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8286 return -1;
8287 }
8288
8289 return 0;
8290 }
8291
8292 static int test_opcode_table (opc_handler_t **table, int len)
8293 {
8294 int i, count, tmp;
8295
8296 for (i = 0, count = 0; i < len; i++) {
8297 /* Consistency fixup */
8298 if (table[i] == NULL)
8299 table[i] = &invalid_handler;
8300 if (table[i] != &invalid_handler) {
8301 if (is_indirect_opcode(table[i])) {
8302 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8303 if (tmp == 0) {
8304 free(table[i]);
8305 table[i] = &invalid_handler;
8306 } else {
8307 count++;
8308 }
8309 } else {
8310 count++;
8311 }
8312 }
8313 }
8314
8315 return count;
8316 }
8317
8318 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8319 {
8320 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8321 printf("*** WARNING: no opcode defined !\n");
8322 }
8323
8324 /*****************************************************************************/
8325 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8326 {
8327 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8328 CPUPPCState *env = &cpu->env;
8329 opcode_t *opc;
8330
8331 fill_new_table(env->opcodes, 0x40);
8332 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8333 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8334 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8335 if (register_insn(env->opcodes, opc) < 0) {
8336 error_setg(errp, "ERROR initializing PowerPC instruction "
8337 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8338 opc->opc3);
8339 return;
8340 }
8341 }
8342 }
8343 fix_opcode_tables(env->opcodes);
8344 fflush(stdout);
8345 fflush(stderr);
8346 }
8347
8348 #if defined(PPC_DUMP_CPU)
8349 static void dump_ppc_insns (CPUPPCState *env)
8350 {
8351 opc_handler_t **table, *handler;
8352 const char *p, *q;
8353 uint8_t opc1, opc2, opc3;
8354
8355 printf("Instructions set:\n");
8356 /* opc1 is 6 bits long */
8357 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8358 table = env->opcodes;
8359 handler = table[opc1];
8360 if (is_indirect_opcode(handler)) {
8361 /* opc2 is 5 bits long */
8362 for (opc2 = 0; opc2 < 0x20; opc2++) {
8363 table = env->opcodes;
8364 handler = env->opcodes[opc1];
8365 table = ind_table(handler);
8366 handler = table[opc2];
8367 if (is_indirect_opcode(handler)) {
8368 table = ind_table(handler);
8369 /* opc3 is 5 bits long */
8370 for (opc3 = 0; opc3 < 0x20; opc3++) {
8371 handler = table[opc3];
8372 if (handler->handler != &gen_invalid) {
8373 /* Special hack to properly dump SPE insns */
8374 p = strchr(handler->oname, '_');
8375 if (p == NULL) {
8376 printf("INSN: %02x %02x %02x (%02d %04d) : "
8377 "%s\n",
8378 opc1, opc2, opc3, opc1,
8379 (opc3 << 5) | opc2,
8380 handler->oname);
8381 } else {
8382 q = "speundef";
8383 if ((p - handler->oname) != strlen(q) ||
8384 memcmp(handler->oname, q, strlen(q)) != 0) {
8385 /* First instruction */
8386 printf("INSN: %02x %02x %02x (%02d %04d) : "
8387 "%.*s\n",
8388 opc1, opc2 << 1, opc3, opc1,
8389 (opc3 << 6) | (opc2 << 1),
8390 (int)(p - handler->oname),
8391 handler->oname);
8392 }
8393 if (strcmp(p + 1, q) != 0) {
8394 /* Second instruction */
8395 printf("INSN: %02x %02x %02x (%02d %04d) : "
8396 "%s\n",
8397 opc1, (opc2 << 1) | 1, opc3, opc1,
8398 (opc3 << 6) | (opc2 << 1) | 1,
8399 p + 1);
8400 }
8401 }
8402 }
8403 }
8404 } else {
8405 if (handler->handler != &gen_invalid) {
8406 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8407 opc1, opc2, opc1, opc2, handler->oname);
8408 }
8409 }
8410 }
8411 } else {
8412 if (handler->handler != &gen_invalid) {
8413 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8414 opc1, opc1, handler->oname);
8415 }
8416 }
8417 }
8418 }
8419 #endif
8420
8421 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8422 {
8423 if (n < 32) {
8424 stfq_p(mem_buf, env->fpr[n]);
8425 return 8;
8426 }
8427 if (n == 32) {
8428 stl_p(mem_buf, env->fpscr);
8429 return 4;
8430 }
8431 return 0;
8432 }
8433
8434 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8435 {
8436 if (n < 32) {
8437 env->fpr[n] = ldfq_p(mem_buf);
8438 return 8;
8439 }
8440 if (n == 32) {
8441 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
8442 return 4;
8443 }
8444 return 0;
8445 }
8446
8447 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8448 {
8449 if (n < 32) {
8450 #ifdef HOST_WORDS_BIGENDIAN
8451 stq_p(mem_buf, env->avr[n].u64[0]);
8452 stq_p(mem_buf+8, env->avr[n].u64[1]);
8453 #else
8454 stq_p(mem_buf, env->avr[n].u64[1]);
8455 stq_p(mem_buf+8, env->avr[n].u64[0]);
8456 #endif
8457 return 16;
8458 }
8459 if (n == 32) {
8460 stl_p(mem_buf, env->vscr);
8461 return 4;
8462 }
8463 if (n == 33) {
8464 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
8465 return 4;
8466 }
8467 return 0;
8468 }
8469
8470 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8471 {
8472 if (n < 32) {
8473 #ifdef HOST_WORDS_BIGENDIAN
8474 env->avr[n].u64[0] = ldq_p(mem_buf);
8475 env->avr[n].u64[1] = ldq_p(mem_buf+8);
8476 #else
8477 env->avr[n].u64[1] = ldq_p(mem_buf);
8478 env->avr[n].u64[0] = ldq_p(mem_buf+8);
8479 #endif
8480 return 16;
8481 }
8482 if (n == 32) {
8483 env->vscr = ldl_p(mem_buf);
8484 return 4;
8485 }
8486 if (n == 33) {
8487 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
8488 return 4;
8489 }
8490 return 0;
8491 }
8492
8493 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8494 {
8495 if (n < 32) {
8496 #if defined(TARGET_PPC64)
8497 stl_p(mem_buf, env->gpr[n] >> 32);
8498 #else
8499 stl_p(mem_buf, env->gprh[n]);
8500 #endif
8501 return 4;
8502 }
8503 if (n == 32) {
8504 stq_p(mem_buf, env->spe_acc);
8505 return 8;
8506 }
8507 if (n == 33) {
8508 stl_p(mem_buf, env->spe_fscr);
8509 return 4;
8510 }
8511 return 0;
8512 }
8513
8514 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8515 {
8516 if (n < 32) {
8517 #if defined(TARGET_PPC64)
8518 target_ulong lo = (uint32_t)env->gpr[n];
8519 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
8520 env->gpr[n] = lo | hi;
8521 #else
8522 env->gprh[n] = ldl_p(mem_buf);
8523 #endif
8524 return 4;
8525 }
8526 if (n == 32) {
8527 env->spe_acc = ldq_p(mem_buf);
8528 return 8;
8529 }
8530 if (n == 33) {
8531 env->spe_fscr = ldl_p(mem_buf);
8532 return 4;
8533 }
8534 return 0;
8535 }
8536
8537 static int ppc_fixup_cpu(PowerPCCPU *cpu)
8538 {
8539 CPUPPCState *env = &cpu->env;
8540
8541 /* TCG doesn't (yet) emulate some groups of instructions that
8542 * are implemented on some otherwise supported CPUs (e.g. VSX
8543 * and decimal floating point instructions on POWER7). We
8544 * remove unsupported instruction groups from the cpu state's
8545 * instruction masks and hope the guest can cope. For at
8546 * least the pseries machine, the unavailability of these
8547 * instructions can be advertised to the guest via the device
8548 * tree. */
8549 if ((env->insns_flags & ~PPC_TCG_INSNS)
8550 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
8551 fprintf(stderr, "Warning: Disabling some instructions which are not "
8552 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
8553 env->insns_flags & ~PPC_TCG_INSNS,
8554 env->insns_flags2 & ~PPC_TCG_INSNS2);
8555 }
8556 env->insns_flags &= PPC_TCG_INSNS;
8557 env->insns_flags2 &= PPC_TCG_INSNS2;
8558 return 0;
8559 }
8560
8561 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
8562 {
8563 #ifdef TARGET_PPCEMB
8564 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
8565 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
8566 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
8567 #else
8568 return true;
8569 #endif
8570 }
8571
8572 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
8573 {
8574 CPUState *cs = CPU(dev);
8575 PowerPCCPU *cpu = POWERPC_CPU(dev);
8576 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8577 Error *local_err = NULL;
8578 #if !defined(CONFIG_USER_ONLY)
8579 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
8580 #endif
8581
8582 #if !defined(CONFIG_USER_ONLY)
8583 if (smp_threads > max_smt) {
8584 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
8585 max_smt, kvm_enabled() ? "KVM" : "TCG");
8586 return;
8587 }
8588 if (!is_power_of_2(smp_threads)) {
8589 error_setg(errp, "Cannot support %d threads on PPC with %s, "
8590 "threads count must be a power of 2.",
8591 smp_threads, kvm_enabled() ? "KVM" : "TCG");
8592 return;
8593 }
8594
8595 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
8596 + (cs->cpu_index % smp_threads);
8597 #endif
8598
8599 if (tcg_enabled()) {
8600 if (ppc_fixup_cpu(cpu) != 0) {
8601 error_setg(errp, "Unable to emulate selected CPU with TCG");
8602 return;
8603 }
8604 }
8605
8606 #if defined(TARGET_PPCEMB)
8607 if (!ppc_cpu_is_valid(pcc)) {
8608 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
8609 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
8610 "or choose another CPU model.");
8611 return;
8612 }
8613 #endif
8614
8615 create_ppc_opcodes(cpu, &local_err);
8616 if (local_err != NULL) {
8617 error_propagate(errp, local_err);
8618 return;
8619 }
8620 init_ppc_proc(cpu);
8621
8622 if (pcc->insns_flags & PPC_FLOAT) {
8623 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
8624 33, "power-fpu.xml", 0);
8625 }
8626 if (pcc->insns_flags & PPC_ALTIVEC) {
8627 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
8628 34, "power-altivec.xml", 0);
8629 }
8630 if (pcc->insns_flags & PPC_SPE) {
8631 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
8632 34, "power-spe.xml", 0);
8633 }
8634
8635 qemu_init_vcpu(cs);
8636
8637 pcc->parent_realize(dev, errp);
8638
8639 #if defined(PPC_DUMP_CPU)
8640 {
8641 CPUPPCState *env = &cpu->env;
8642 const char *mmu_model, *excp_model, *bus_model;
8643 switch (env->mmu_model) {
8644 case POWERPC_MMU_32B:
8645 mmu_model = "PowerPC 32";
8646 break;
8647 case POWERPC_MMU_SOFT_6xx:
8648 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8649 break;
8650 case POWERPC_MMU_SOFT_74xx:
8651 mmu_model = "PowerPC 74xx with software driven TLBs";
8652 break;
8653 case POWERPC_MMU_SOFT_4xx:
8654 mmu_model = "PowerPC 4xx with software driven TLBs";
8655 break;
8656 case POWERPC_MMU_SOFT_4xx_Z:
8657 mmu_model = "PowerPC 4xx with software driven TLBs "
8658 "and zones protections";
8659 break;
8660 case POWERPC_MMU_REAL:
8661 mmu_model = "PowerPC real mode only";
8662 break;
8663 case POWERPC_MMU_MPC8xx:
8664 mmu_model = "PowerPC MPC8xx";
8665 break;
8666 case POWERPC_MMU_BOOKE:
8667 mmu_model = "PowerPC BookE";
8668 break;
8669 case POWERPC_MMU_BOOKE206:
8670 mmu_model = "PowerPC BookE 2.06";
8671 break;
8672 case POWERPC_MMU_601:
8673 mmu_model = "PowerPC 601";
8674 break;
8675 #if defined (TARGET_PPC64)
8676 case POWERPC_MMU_64B:
8677 mmu_model = "PowerPC 64";
8678 break;
8679 #endif
8680 default:
8681 mmu_model = "Unknown or invalid";
8682 break;
8683 }
8684 switch (env->excp_model) {
8685 case POWERPC_EXCP_STD:
8686 excp_model = "PowerPC";
8687 break;
8688 case POWERPC_EXCP_40x:
8689 excp_model = "PowerPC 40x";
8690 break;
8691 case POWERPC_EXCP_601:
8692 excp_model = "PowerPC 601";
8693 break;
8694 case POWERPC_EXCP_602:
8695 excp_model = "PowerPC 602";
8696 break;
8697 case POWERPC_EXCP_603:
8698 excp_model = "PowerPC 603";
8699 break;
8700 case POWERPC_EXCP_603E:
8701 excp_model = "PowerPC 603e";
8702 break;
8703 case POWERPC_EXCP_604:
8704 excp_model = "PowerPC 604";
8705 break;
8706 case POWERPC_EXCP_7x0:
8707 excp_model = "PowerPC 740/750";
8708 break;
8709 case POWERPC_EXCP_7x5:
8710 excp_model = "PowerPC 745/755";
8711 break;
8712 case POWERPC_EXCP_74xx:
8713 excp_model = "PowerPC 74xx";
8714 break;
8715 case POWERPC_EXCP_BOOKE:
8716 excp_model = "PowerPC BookE";
8717 break;
8718 #if defined (TARGET_PPC64)
8719 case POWERPC_EXCP_970:
8720 excp_model = "PowerPC 970";
8721 break;
8722 #endif
8723 default:
8724 excp_model = "Unknown or invalid";
8725 break;
8726 }
8727 switch (env->bus_model) {
8728 case PPC_FLAGS_INPUT_6xx:
8729 bus_model = "PowerPC 6xx";
8730 break;
8731 case PPC_FLAGS_INPUT_BookE:
8732 bus_model = "PowerPC BookE";
8733 break;
8734 case PPC_FLAGS_INPUT_405:
8735 bus_model = "PowerPC 405";
8736 break;
8737 case PPC_FLAGS_INPUT_401:
8738 bus_model = "PowerPC 401/403";
8739 break;
8740 case PPC_FLAGS_INPUT_RCPU:
8741 bus_model = "RCPU / MPC8xx";
8742 break;
8743 #if defined (TARGET_PPC64)
8744 case PPC_FLAGS_INPUT_970:
8745 bus_model = "PowerPC 970";
8746 break;
8747 #endif
8748 default:
8749 bus_model = "Unknown or invalid";
8750 break;
8751 }
8752 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8753 " MMU model : %s\n",
8754 object_class_get_name(OBJECT_CLASS(pcc)),
8755 pcc->pvr, pcc->msr_mask, mmu_model);
8756 #if !defined(CONFIG_USER_ONLY)
8757 if (env->tlb.tlb6) {
8758 printf(" %d %s TLB in %d ways\n",
8759 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8760 env->nb_ways);
8761 }
8762 #endif
8763 printf(" Exceptions model : %s\n"
8764 " Bus model : %s\n",
8765 excp_model, bus_model);
8766 printf(" MSR features :\n");
8767 if (env->flags & POWERPC_FLAG_SPE)
8768 printf(" signal processing engine enable"
8769 "\n");
8770 else if (env->flags & POWERPC_FLAG_VRE)
8771 printf(" vector processor enable\n");
8772 if (env->flags & POWERPC_FLAG_TGPR)
8773 printf(" temporary GPRs\n");
8774 else if (env->flags & POWERPC_FLAG_CE)
8775 printf(" critical input enable\n");
8776 if (env->flags & POWERPC_FLAG_SE)
8777 printf(" single-step trace mode\n");
8778 else if (env->flags & POWERPC_FLAG_DWE)
8779 printf(" debug wait enable\n");
8780 else if (env->flags & POWERPC_FLAG_UBLE)
8781 printf(" user BTB lock enable\n");
8782 if (env->flags & POWERPC_FLAG_BE)
8783 printf(" branch-step trace mode\n");
8784 else if (env->flags & POWERPC_FLAG_DE)
8785 printf(" debug interrupt enable\n");
8786 if (env->flags & POWERPC_FLAG_PX)
8787 printf(" inclusive protection\n");
8788 else if (env->flags & POWERPC_FLAG_PMM)
8789 printf(" performance monitor mark\n");
8790 if (env->flags == POWERPC_FLAG_NONE)
8791 printf(" none\n");
8792 printf(" Time-base/decrementer clock source: %s\n",
8793 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8794 dump_ppc_insns(env);
8795 dump_ppc_sprs(env);
8796 fflush(stdout);
8797 }
8798 #endif
8799 }
8800
8801 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
8802 {
8803 PowerPCCPU *cpu = POWERPC_CPU(dev);
8804 CPUPPCState *env = &cpu->env;
8805 int i;
8806
8807 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8808 if (env->opcodes[i] != &invalid_handler) {
8809 g_free(env->opcodes[i]);
8810 }
8811 }
8812 }
8813
8814 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8815 {
8816 ObjectClass *oc = (ObjectClass *)a;
8817 uint32_t pvr = *(uint32_t *)b;
8818 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8819
8820 /* -cpu host does a PVR lookup during construction */
8821 if (unlikely(strcmp(object_class_get_name(oc),
8822 TYPE_HOST_POWERPC_CPU) == 0)) {
8823 return -1;
8824 }
8825
8826 if (!ppc_cpu_is_valid(pcc)) {
8827 return -1;
8828 }
8829
8830 return pcc->pvr == pvr ? 0 : -1;
8831 }
8832
8833 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8834 {
8835 GSList *list, *item;
8836 PowerPCCPUClass *pcc = NULL;
8837
8838 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8839 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8840 if (item != NULL) {
8841 pcc = POWERPC_CPU_CLASS(item->data);
8842 }
8843 g_slist_free(list);
8844
8845 return pcc;
8846 }
8847
8848 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8849 {
8850 ObjectClass *oc = (ObjectClass *)a;
8851 uint32_t pvr = *(uint32_t *)b;
8852 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8853 gint ret;
8854
8855 /* -cpu host does a PVR lookup during construction */
8856 if (unlikely(strcmp(object_class_get_name(oc),
8857 TYPE_HOST_POWERPC_CPU) == 0)) {
8858 return -1;
8859 }
8860
8861 if (!ppc_cpu_is_valid(pcc)) {
8862 return -1;
8863 }
8864
8865 ret = (((pcc->pvr & pcc->pvr_mask) == (pvr & pcc->pvr_mask)) ? 0 : -1);
8866
8867 return ret;
8868 }
8869
8870 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8871 {
8872 GSList *list, *item;
8873 PowerPCCPUClass *pcc = NULL;
8874
8875 list = object_class_get_list(TYPE_POWERPC_CPU, true);
8876 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8877 if (item != NULL) {
8878 pcc = POWERPC_CPU_CLASS(item->data);
8879 }
8880 g_slist_free(list);
8881
8882 return pcc;
8883 }
8884
8885 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
8886 {
8887 ObjectClass *oc = (ObjectClass *)a;
8888 const char *name = b;
8889 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8890
8891 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
8892 ppc_cpu_is_valid(pcc) &&
8893 strcmp(object_class_get_name(oc) + strlen(name),
8894 "-" TYPE_POWERPC_CPU) == 0) {
8895 return 0;
8896 }
8897 return -1;
8898 }
8899
8900 #include <ctype.h>
8901
8902 static ObjectClass *ppc_cpu_class_by_name(const char *name);
8903
8904 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
8905 {
8906 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
8907
8908 /* Cache target class lookups in the alias table */
8909 if (!alias->oc) {
8910 alias->oc = ppc_cpu_class_by_name(alias->model);
8911 if (!alias->oc) {
8912 /* Fast check for non-existing aliases */
8913 alias->oc = invalid_class;
8914 }
8915 }
8916
8917 if (alias->oc == invalid_class) {
8918 return NULL;
8919 } else {
8920 return alias->oc;
8921 }
8922 }
8923
8924 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8925 {
8926 GSList *list, *item;
8927 ObjectClass *ret = NULL;
8928 const char *p;
8929 int i, len;
8930
8931 /* Check if the given name is a PVR */
8932 len = strlen(name);
8933 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8934 p = name + 2;
8935 goto check_pvr;
8936 } else if (len == 8) {
8937 p = name;
8938 check_pvr:
8939 for (i = 0; i < 8; i++) {
8940 if (!qemu_isxdigit(*p++))
8941 break;
8942 }
8943 if (i == 8) {
8944 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
8945 return ret;
8946 }
8947 }
8948
8949 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8950 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8951 if (item != NULL) {
8952 ret = OBJECT_CLASS(item->data);
8953 }
8954 g_slist_free(list);
8955
8956 if (ret) {
8957 return ret;
8958 }
8959
8960 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8961 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
8962 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
8963 }
8964 }
8965
8966 return NULL;
8967 }
8968
8969 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
8970 {
8971 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
8972 }
8973
8974 /* Sort by PVR, ordering special case "host" last. */
8975 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8976 {
8977 ObjectClass *oc_a = (ObjectClass *)a;
8978 ObjectClass *oc_b = (ObjectClass *)b;
8979 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8980 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8981 const char *name_a = object_class_get_name(oc_a);
8982 const char *name_b = object_class_get_name(oc_b);
8983
8984 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8985 return 1;
8986 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8987 return -1;
8988 } else {
8989 /* Avoid an integer overflow during subtraction */
8990 if (pcc_a->pvr < pcc_b->pvr) {
8991 return -1;
8992 } else if (pcc_a->pvr > pcc_b->pvr) {
8993 return 1;
8994 } else {
8995 return 0;
8996 }
8997 }
8998 }
8999
9000 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9001 {
9002 ObjectClass *oc = data;
9003 CPUListState *s = user_data;
9004 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9005 const char *typename = object_class_get_name(oc);
9006 char *name;
9007 int i;
9008
9009 if (!ppc_cpu_is_valid(pcc)) {
9010 return;
9011 }
9012 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9013 return;
9014 }
9015
9016 name = g_strndup(typename,
9017 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9018 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9019 name, pcc->pvr);
9020 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9021 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9022 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9023
9024 if (alias_oc != oc) {
9025 continue;
9026 }
9027 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9028 alias->alias, name);
9029 }
9030 g_free(name);
9031 }
9032
9033 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9034 {
9035 CPUListState s = {
9036 .file = f,
9037 .cpu_fprintf = cpu_fprintf,
9038 };
9039 GSList *list;
9040
9041 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9042 list = g_slist_sort(list, ppc_cpu_list_compare);
9043 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9044 g_slist_free(list);
9045
9046 #ifdef CONFIG_KVM
9047 cpu_fprintf(f, "\n");
9048 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9049 #endif
9050 }
9051
9052 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9053 {
9054 ObjectClass *oc = data;
9055 CpuDefinitionInfoList **first = user_data;
9056 const char *typename;
9057 CpuDefinitionInfoList *entry;
9058 CpuDefinitionInfo *info;
9059 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9060
9061 if (!ppc_cpu_is_valid(pcc)) {
9062 return;
9063 }
9064
9065 typename = object_class_get_name(oc);
9066 info = g_malloc0(sizeof(*info));
9067 info->name = g_strndup(typename,
9068 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9069
9070 entry = g_malloc0(sizeof(*entry));
9071 entry->value = info;
9072 entry->next = *first;
9073 *first = entry;
9074 }
9075
9076 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9077 {
9078 CpuDefinitionInfoList *cpu_list = NULL;
9079 GSList *list;
9080 int i;
9081
9082 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9083 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9084 g_slist_free(list);
9085
9086 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9087 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9088 ObjectClass *oc;
9089 CpuDefinitionInfoList *entry;
9090 CpuDefinitionInfo *info;
9091
9092 oc = ppc_cpu_class_by_alias(alias);
9093 if (oc == NULL) {
9094 continue;
9095 }
9096
9097 info = g_malloc0(sizeof(*info));
9098 info->name = g_strdup(alias->alias);
9099
9100 entry = g_malloc0(sizeof(*entry));
9101 entry->value = info;
9102 entry->next = cpu_list;
9103 cpu_list = entry;
9104 }
9105
9106 return cpu_list;
9107 }
9108
9109 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9110 {
9111 PowerPCCPU *cpu = POWERPC_CPU(cs);
9112
9113 cpu->env.nip = value;
9114 }
9115
9116 static bool ppc_cpu_has_work(CPUState *cs)
9117 {
9118 PowerPCCPU *cpu = POWERPC_CPU(cs);
9119 CPUPPCState *env = &cpu->env;
9120
9121 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9122 }
9123
9124 /* CPUClass::reset() */
9125 static void ppc_cpu_reset(CPUState *s)
9126 {
9127 PowerPCCPU *cpu = POWERPC_CPU(s);
9128 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9129 CPUPPCState *env = &cpu->env;
9130 target_ulong msr;
9131 int i;
9132
9133 pcc->parent_reset(s);
9134
9135 msr = (target_ulong)0;
9136 if (0) {
9137 /* XXX: find a suitable condition to enable the hypervisor mode */
9138 msr |= (target_ulong)MSR_HVB;
9139 }
9140 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9141 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9142 msr |= (target_ulong)1 << MSR_EP;
9143 #if defined(DO_SINGLE_STEP) && 0
9144 /* Single step trace mode */
9145 msr |= (target_ulong)1 << MSR_SE;
9146 msr |= (target_ulong)1 << MSR_BE;
9147 #endif
9148 #if defined(CONFIG_USER_ONLY)
9149 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9150 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9151 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9152 msr |= (target_ulong)1 << MSR_PR;
9153 #endif
9154
9155 #if defined(TARGET_PPC64)
9156 if (env->mmu_model & POWERPC_MMU_64) {
9157 env->msr |= (1ULL << MSR_SF);
9158 }
9159 #endif
9160
9161 hreg_store_msr(env, msr, 1);
9162
9163 #if !defined(CONFIG_USER_ONLY)
9164 env->nip = env->hreset_vector | env->excp_prefix;
9165 if (env->mmu_model != POWERPC_MMU_REAL) {
9166 ppc_tlb_invalidate_all(env);
9167 }
9168 #endif
9169
9170 hreg_compute_hflags(env);
9171 env->reserve_addr = (target_ulong)-1ULL;
9172 /* Be sure no exception or interrupt is pending */
9173 env->pending_interrupts = 0;
9174 s->exception_index = POWERPC_EXCP_NONE;
9175 env->error_code = 0;
9176
9177 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9178 env->vpa_addr = 0;
9179 env->slb_shadow_addr = 0;
9180 env->slb_shadow_size = 0;
9181 env->dtl_addr = 0;
9182 env->dtl_size = 0;
9183 #endif /* TARGET_PPC64 */
9184
9185 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9186 ppc_spr_t *spr = &env->spr_cb[i];
9187
9188 if (!spr->name) {
9189 continue;
9190 }
9191 env->spr[i] = spr->default_value;
9192 }
9193
9194 /* Flush all TLBs */
9195 tlb_flush(s, 1);
9196 }
9197
9198 static void ppc_cpu_initfn(Object *obj)
9199 {
9200 CPUState *cs = CPU(obj);
9201 PowerPCCPU *cpu = POWERPC_CPU(obj);
9202 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9203 CPUPPCState *env = &cpu->env;
9204
9205 cs->env_ptr = env;
9206 cpu_exec_init(env);
9207 cpu->cpu_dt_id = cs->cpu_index;
9208
9209 env->msr_mask = pcc->msr_mask;
9210 env->mmu_model = pcc->mmu_model;
9211 env->excp_model = pcc->excp_model;
9212 env->bus_model = pcc->bus_model;
9213 env->insns_flags = pcc->insns_flags;
9214 env->insns_flags2 = pcc->insns_flags2;
9215 env->flags = pcc->flags;
9216 env->bfd_mach = pcc->bfd_mach;
9217 env->check_pow = pcc->check_pow;
9218
9219 #if defined(TARGET_PPC64)
9220 if (pcc->sps) {
9221 env->sps = *pcc->sps;
9222 } else if (env->mmu_model & POWERPC_MMU_64) {
9223 /* Use default sets of page sizes */
9224 static const struct ppc_segment_page_sizes defsps = {
9225 .sps = {
9226 { .page_shift = 12, /* 4K */
9227 .slb_enc = 0,
9228 .enc = { { .page_shift = 12, .pte_enc = 0 } }
9229 },
9230 { .page_shift = 24, /* 16M */
9231 .slb_enc = 0x100,
9232 .enc = { { .page_shift = 24, .pte_enc = 0 } }
9233 },
9234 },
9235 };
9236 env->sps = defsps;
9237 }
9238 #endif /* defined(TARGET_PPC64) */
9239
9240 if (tcg_enabled()) {
9241 ppc_translate_init();
9242 }
9243 }
9244
9245 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9246 {
9247 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9248 CPUClass *cc = CPU_CLASS(oc);
9249 DeviceClass *dc = DEVICE_CLASS(oc);
9250
9251 pcc->parent_realize = dc->realize;
9252 pcc->pvr = CPU_POWERPC_DEFAULT_MASK;
9253 pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK;
9254 dc->realize = ppc_cpu_realizefn;
9255 dc->unrealize = ppc_cpu_unrealizefn;
9256
9257 pcc->parent_reset = cc->reset;
9258 cc->reset = ppc_cpu_reset;
9259
9260 cc->class_by_name = ppc_cpu_class_by_name;
9261 cc->has_work = ppc_cpu_has_work;
9262 cc->do_interrupt = ppc_cpu_do_interrupt;
9263 cc->dump_state = ppc_cpu_dump_state;
9264 cc->dump_statistics = ppc_cpu_dump_statistics;
9265 cc->set_pc = ppc_cpu_set_pc;
9266 cc->gdb_read_register = ppc_cpu_gdb_read_register;
9267 cc->gdb_write_register = ppc_cpu_gdb_write_register;
9268 #ifdef CONFIG_USER_ONLY
9269 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
9270 #else
9271 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
9272 cc->vmsd = &vmstate_ppc_cpu;
9273 #if defined(TARGET_PPC64)
9274 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
9275 cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote;
9276 #endif
9277 #endif
9278
9279 cc->gdb_num_core_regs = 71;
9280 #if defined(TARGET_PPC64)
9281 cc->gdb_core_xml_file = "power64-core.xml";
9282 #else
9283 cc->gdb_core_xml_file = "power-core.xml";
9284 #endif
9285
9286 dc->fw_name = "PowerPC,UNKNOWN";
9287 }
9288
9289 static const TypeInfo ppc_cpu_type_info = {
9290 .name = TYPE_POWERPC_CPU,
9291 .parent = TYPE_CPU,
9292 .instance_size = sizeof(PowerPCCPU),
9293 .instance_init = ppc_cpu_initfn,
9294 .abstract = true,
9295 .class_size = sizeof(PowerPCCPUClass),
9296 .class_init = ppc_cpu_class_init,
9297 };
9298
9299 static void ppc_cpu_register_types(void)
9300 {
9301 type_register_static(&ppc_cpu_type_info);
9302 }
9303
9304 type_init(ppc_cpu_register_types)
Ray Wang's QEMU Repository