hw/misc/eccmemctl.c

   1 /*
   2  * QEMU Sparc Sun4m ECC memory controller emulation
   3  *
   4  * Copyright (c) 2007 Robert Reif
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "trace.h"
  27
  28 /* There are 3 versions of this chip used in SMP sun4m systems:
  29  * MCC (version 0, implementation 0) SS-600MP
  30  * EMC (version 0, implementation 1) SS-10
  31  * SMC (version 0, implementation 2) SS-10SX and SS-20
  32  *
  33  * Chipset docs:
  34  * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
  35  * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
  36  */
  37
  38 #define ECC_MCC        0x00000000
  39 #define ECC_EMC        0x10000000
  40 #define ECC_SMC        0x20000000
  41
  42 /* Register indexes */
  43 #define ECC_MER        0               /* Memory Enable Register */
  44 #define ECC_MDR        1               /* Memory Delay Register */
  45 #define ECC_MFSR       2               /* Memory Fault Status Register */
  46 #define ECC_VCR        3               /* Video Configuration Register */
  47 #define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
  48 #define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
  49 #define ECC_DR         6               /* Diagnostic Register */
  50 #define ECC_ECR0       7               /* Event Count Register 0 */
  51 #define ECC_ECR1       8               /* Event Count Register 1 */
  52
  53 /* ECC fault control register */
  54 #define ECC_MER_EE     0x00000001      /* Enable ECC checking */
  55 #define ECC_MER_EI     0x00000002      /* Enable Interrupts on
  56                                           correctable errors */
  57 #define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
  58 #define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
  59 #define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
  60 #define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
  61 #define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
  62 #define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
  63 #define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
  64 #define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
  65 #define ECC_MER_REU    0x00000100      /* Memory Refresh Enable (600MP) */
  66 #define ECC_MER_MRR    0x000003fc      /* MRR mask */
  67 #define ECC_MER_A      0x00000400      /* Memory controller addr map select */
  68 #define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
  69 #define ECC_MER_VER    0x0f000000      /* Version */
  70 #define ECC_MER_IMPL   0xf0000000      /* Implementation */
  71 #define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
  72 #define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
  73 #define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */
  74
  75 /* ECC memory delay register */
  76 #define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
  77 #define ECC_MDR_MI     0x00001c00      /* MIH Delay */
  78 #define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
  79 #define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
  80 #define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
  81 #define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
  82 #define ECC_MDR_RSC    0x80000000      /* Refresh load control */
  83 #define ECC_MDR_MASK   0x7fffffff
  84
  85 /* ECC fault status register */
  86 #define ECC_MFSR_CE    0x00000001      /* Correctable error */
  87 #define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
  88 #define ECC_MFSR_TO    0x00000004      /* Timeout on write */
  89 #define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
  90 #define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
  91 #define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
  92 #define ECC_MFSR_ME    0x00010000      /* Multiple errors */
  93 #define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */
  94
  95 /* ECC fault address register 0 */
  96 #define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
  97 #define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
  98 #define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
  99 #define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
 100 #define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
 101 #define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
 102 #define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
 103 #define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
 104 #define ECC_MFARO_MID   0xf0000000     /* Module ID */
 105
 106 /* ECC diagnostic register */
 107 #define ECC_DR_CBX     0x00000001
 108 #define ECC_DR_CB0     0x00000002
 109 #define ECC_DR_CB1     0x00000004
 110 #define ECC_DR_CB2     0x00000008
 111 #define ECC_DR_CB4     0x00000010
 112 #define ECC_DR_CB8     0x00000020
 113 #define ECC_DR_CB16    0x00000040
 114 #define ECC_DR_CB32    0x00000080
 115 #define ECC_DR_DMODE   0x00000c00
 116
 117 #define ECC_NREGS      9
 118 #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
 119
 120 #define ECC_DIAG_SIZE  4
 121 #define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)
 122
 123 #define TYPE_ECC_MEMCTL "eccmemctl"
 124 #define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL)
 125
 126 typedef struct ECCState {
 127     SysBusDevice parent_obj;
 128
 129     MemoryRegion iomem, iomem_diag;
 130     qemu_irq irq;
 131     uint32_t regs[ECC_NREGS];
 132     uint8_t diag[ECC_DIAG_SIZE];
 133     uint32_t version;
 134 } ECCState;
 135
 136 static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
 137                           unsigned size)
 138 {
 139     ECCState *s = opaque;
 140
 141     switch (addr >> 2) {
 142     case ECC_MER:
 143         if (s->version == ECC_MCC)
 144             s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
 145         else if (s->version == ECC_EMC)
 146             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
 147         else if (s->version == ECC_SMC)
 148             s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
 149         trace_ecc_mem_writel_mer(val);
 150         break;
 151     case ECC_MDR:
 152         s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
 153         trace_ecc_mem_writel_mdr(val);
 154         break;
 155     case ECC_MFSR:
 156         s->regs[ECC_MFSR] =  val;
 157         qemu_irq_lower(s->irq);
 158         trace_ecc_mem_writel_mfsr(val);
 159         break;
 160     case ECC_VCR:
 161         s->regs[ECC_VCR] =  val;
 162         trace_ecc_mem_writel_vcr(val);
 163         break;
 164     case ECC_DR:
 165         s->regs[ECC_DR] =  val;
 166         trace_ecc_mem_writel_dr(val);
 167         break;
 168     case ECC_ECR0:
 169         s->regs[ECC_ECR0] =  val;
 170         trace_ecc_mem_writel_ecr0(val);
 171         break;
 172     case ECC_ECR1:
 173         s->regs[ECC_ECR0] =  val;
 174         trace_ecc_mem_writel_ecr1(val);
 175         break;
 176     }
 177 }
 178
 179 static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
 180                              unsigned size)
 181 {
 182     ECCState *s = opaque;
 183     uint32_t ret = 0;
 184
 185     switch (addr >> 2) {
 186     case ECC_MER:
 187         ret = s->regs[ECC_MER];
 188         trace_ecc_mem_readl_mer(ret);
 189         break;
 190     case ECC_MDR:
 191         ret = s->regs[ECC_MDR];
 192         trace_ecc_mem_readl_mdr(ret);
 193         break;
 194     case ECC_MFSR:
 195         ret = s->regs[ECC_MFSR];
 196         trace_ecc_mem_readl_mfsr(ret);
 197         break;
 198     case ECC_VCR:
 199         ret = s->regs[ECC_VCR];
 200         trace_ecc_mem_readl_vcr(ret);
 201         break;
 202     case ECC_MFAR0:
 203         ret = s->regs[ECC_MFAR0];
 204         trace_ecc_mem_readl_mfar0(ret);
 205         break;
 206     case ECC_MFAR1:
 207         ret = s->regs[ECC_MFAR1];
 208         trace_ecc_mem_readl_mfar1(ret);
 209         break;
 210     case ECC_DR:
 211         ret = s->regs[ECC_DR];
 212         trace_ecc_mem_readl_dr(ret);
 213         break;
 214     case ECC_ECR0:
 215         ret = s->regs[ECC_ECR0];
 216         trace_ecc_mem_readl_ecr0(ret);
 217         break;
 218     case ECC_ECR1:
 219         ret = s->regs[ECC_ECR0];
 220         trace_ecc_mem_readl_ecr1(ret);
 221         break;
 222     }
 223     return ret;
 224 }
 225
 226 static const MemoryRegionOps ecc_mem_ops = {
 227     .read = ecc_mem_read,
 228     .write = ecc_mem_write,
 229     .endianness = DEVICE_NATIVE_ENDIAN,
 230     .valid = {
 231         .min_access_size = 4,
 232         .max_access_size = 4,
 233     },
 234 };
 235
 236 static void ecc_diag_mem_write(void *opaque, hwaddr addr,
 237                                uint64_t val, unsigned size)
 238 {
 239     ECCState *s = opaque;
 240
 241     trace_ecc_diag_mem_writeb(addr, val);
 242     s->diag[addr & ECC_DIAG_MASK] = val;
 243 }
 244
 245 static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
 246                                   unsigned size)
 247 {
 248     ECCState *s = opaque;
 249     uint32_t ret = s->diag[(int)addr];
 250
 251     trace_ecc_diag_mem_readb(addr, ret);
 252     return ret;
 253 }
 254
 255 static const MemoryRegionOps ecc_diag_mem_ops = {
 256     .read = ecc_diag_mem_read,
 257     .write = ecc_diag_mem_write,
 258     .endianness = DEVICE_NATIVE_ENDIAN,
 259     .valid = {
 260         .min_access_size = 1,
 261         .max_access_size = 1,
 262     },
 263 };
 264
 265 static const VMStateDescription vmstate_ecc = {
 266     .name ="ECC",
 267     .version_id = 3,
 268     .minimum_version_id = 3,
 269     .fields = (VMStateField[]) {
 270         VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
 271         VMSTATE_BUFFER(diag, ECCState),
 272         VMSTATE_UINT32(version, ECCState),
 273         VMSTATE_END_OF_LIST()
 274     }
 275 };
 276
 277 static void ecc_reset(DeviceState *d)
 278 {
 279     ECCState *s = ECC_MEMCTL(d);
 280
 281     if (s->version == ECC_MCC) {
 282         s->regs[ECC_MER] &= ECC_MER_REU;
 283     } else {
 284         s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
 285                              ECC_MER_DCI);
 286     }
 287     s->regs[ECC_MDR] = 0x20;
 288     s->regs[ECC_MFSR] = 0;
 289     s->regs[ECC_VCR] = 0;
 290     s->regs[ECC_MFAR0] = 0x07c00000;
 291     s->regs[ECC_MFAR1] = 0;
 292     s->regs[ECC_DR] = 0;
 293     s->regs[ECC_ECR0] = 0;
 294     s->regs[ECC_ECR1] = 0;
 295 }
 296
 297 static int ecc_init1(SysBusDevice *dev)
 298 {
 299     ECCState *s = ECC_MEMCTL(dev);
 300
 301     sysbus_init_irq(dev, &s->irq);
 302     s->regs[0] = s->version;
 303     memory_region_init_io(&s->iomem, OBJECT(dev), &ecc_mem_ops, s, "ecc", ECC_SIZE);
 304     sysbus_init_mmio(dev, &s->iomem);
 305
 306     if (s->version == ECC_MCC) { // SS-600MP only
 307         memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s,
 308                               "ecc.diag", ECC_DIAG_SIZE);
 309         sysbus_init_mmio(dev, &s->iomem_diag);
 310     }
 311
 312     return 0;
 313 }
 314
 315 static Property ecc_properties[] = {
 316     DEFINE_PROP_UINT32("version", ECCState, version, -1),
 317     DEFINE_PROP_END_OF_LIST(),
 318 };
 319
 320 static void ecc_class_init(ObjectClass *klass, void *data)
 321 {
 322     DeviceClass *dc = DEVICE_CLASS(klass);
 323     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 324
 325     k->init = ecc_init1;
 326     dc->reset = ecc_reset;
 327     dc->vmsd = &vmstate_ecc;
 328     dc->props = ecc_properties;
 329 }
 330
 331 static const TypeInfo ecc_info = {
 332     .name          = TYPE_ECC_MEMCTL,
 333     .parent        = TYPE_SYS_BUS_DEVICE,
 334     .instance_size = sizeof(ECCState),
 335     .class_init    = ecc_class_init,
 336 };
 337
 338
 339 static void ecc_register_types(void)
 340 {
 341     type_register_static(&ecc_info);
 342 }
 343
 344 type_init(ecc_register_types)