target/mips/tcg/translate.h

   1 /*
   2  *  MIPS translation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * SPDX-License-Identifier: LGPL-2.1-or-later
   7  */
   8 #ifndef TARGET_MIPS_TRANSLATE_H
   9 #define TARGET_MIPS_TRANSLATE_H
  10
  11 #include "qemu/log.h"
  12 #include "exec/translator.h"
  13
  14 #define MIPS_DEBUG_DISAS 0
  15
  16 typedef struct DisasContext {
  17     DisasContextBase base;
  18     target_ulong saved_pc;
  19     target_ulong page_start;
  20     uint32_t opcode;
  21     uint64_t insn_flags;
  22     int32_t CP0_Config0;
  23     int32_t CP0_Config1;
  24     int32_t CP0_Config2;
  25     int32_t CP0_Config3;
  26     int32_t CP0_Config5;
  27     /* Routine used to access memory */
  28     int mem_idx;
  29     MemOp default_tcg_memop_mask;
  30     uint32_t hflags, saved_hflags;
  31     target_ulong btarget;
  32     bool ulri;
  33     int kscrexist;
  34     bool rxi;
  35     int ie;
  36     bool bi;
  37     bool bp;
  38     uint64_t PAMask;
  39     bool mvh;
  40     bool eva;
  41     bool sc;
  42     int CP0_LLAddr_shift;
  43     bool ps;
  44     bool vp;
  45     bool cmgcr;
  46     bool mrp;
  47     bool nan2008;
  48     bool abs2008;
  49     bool saar;
  50     bool mi;
  51     int gi;
  52 } DisasContext;
  53
  54 /* MIPS major opcodes */
  55 #define MASK_OP_MAJOR(op)   (op & (0x3F << 26))
  56
  57 #define OPC_CP1 (0x11 << 26)
  58
  59 /* Coprocessor 1 (rs field) */
  60 #define MASK_CP1(op)                (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
  61
  62 /* Values for the fmt field in FP instructions */
  63 enum {
  64     /* 0 - 15 are reserved */
  65     FMT_S = 16,          /* single fp */
  66     FMT_D = 17,          /* double fp */
  67     FMT_E = 18,          /* extended fp */
  68     FMT_Q = 19,          /* quad fp */
  69     FMT_W = 20,          /* 32-bit fixed */
  70     FMT_L = 21,          /* 64-bit fixed */
  71     FMT_PS = 22,         /* paired single fp */
  72     /* 23 - 31 are reserved */
  73 };
  74
  75 enum {
  76     OPC_MFC1     = (0x00 << 21) | OPC_CP1,
  77     OPC_DMFC1    = (0x01 << 21) | OPC_CP1,
  78     OPC_CFC1     = (0x02 << 21) | OPC_CP1,
  79     OPC_MFHC1    = (0x03 << 21) | OPC_CP1,
  80     OPC_MTC1     = (0x04 << 21) | OPC_CP1,
  81     OPC_DMTC1    = (0x05 << 21) | OPC_CP1,
  82     OPC_CTC1     = (0x06 << 21) | OPC_CP1,
  83     OPC_MTHC1    = (0x07 << 21) | OPC_CP1,
  84     OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */
  85     OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,
  86     OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,
  87     OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,
  88     OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,
  89     OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,
  90     OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,
  91     OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,
  92     OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,
  93     OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,
  94     OPC_BC1EQZ   = (0x09 << 21) | OPC_CP1,
  95     OPC_BC1NEZ   = (0x0D << 21) | OPC_CP1,
  96 };
  97
  98 #define MASK_CP1_FUNC(op)           (MASK_CP1(op) | (op & 0x3F))
  99 #define MASK_BC1(op)                (MASK_CP1(op) | (op & (0x3 << 16)))
 100
 101 enum {
 102     OPC_BC1F     = (0x00 << 16) | OPC_BC1,
 103     OPC_BC1T     = (0x01 << 16) | OPC_BC1,
 104     OPC_BC1FL    = (0x02 << 16) | OPC_BC1,
 105     OPC_BC1TL    = (0x03 << 16) | OPC_BC1,
 106 };
 107
 108 enum {
 109     OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,
 110     OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,
 111 };
 112
 113 enum {
 114     OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,
 115     OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,
 116 };
 117
 118 #define gen_helper_0e1i(name, arg1, arg2) do { \
 119     gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \
 120     } while (0)
 121
 122 #define gen_helper_1e0i(name, ret, arg1) do { \
 123     gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \
 124     } while (0)
 125
 126 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \
 127     gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\
 128     } while (0)
 129
 130 void generate_exception(DisasContext *ctx, int excp);
 131 void generate_exception_err(DisasContext *ctx, int excp, int err);
 132 void generate_exception_end(DisasContext *ctx, int excp);
 133 void generate_exception_break(DisasContext *ctx, int code);
 134 void gen_reserved_instruction(DisasContext *ctx);
 135
 136 void check_insn(DisasContext *ctx, uint64_t flags);
 137 void check_mips_64(DisasContext *ctx);
 138 /**
 139  * check_cp0_enabled:
 140  * Return %true if CP0 is enabled, otherwise return %false
 141  * and emit a 'coprocessor unusable' exception.
 142  */
 143 bool check_cp0_enabled(DisasContext *ctx);
 144 void check_cp1_enabled(DisasContext *ctx);
 145 void check_cp1_64bitmode(DisasContext *ctx);
 146 void check_cp1_registers(DisasContext *ctx, int regs);
 147 void check_cop1x(DisasContext *ctx);
 148
 149 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
 150 void gen_move_low32(TCGv ret, TCGv_i64 arg);
 151 void gen_move_high32(TCGv ret, TCGv_i64 arg);
 152 void gen_load_gpr(TCGv t, int reg);
 153 void gen_store_gpr(TCGv t, int reg);
 154 #if defined(TARGET_MIPS64)
 155 void gen_load_gpr_hi(TCGv_i64 t, int reg);
 156 void gen_store_gpr_hi(TCGv_i64 t, int reg);
 157 #endif /* TARGET_MIPS64 */
 158 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 159 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 160 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 161 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 162 int get_fp_bit(int cc);
 163
 164 void gen_ldxs(DisasContext *ctx, int base, int index, int rd);
 165 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp);
 166 void gen_addiupc(DisasContext *ctx, int rx, int imm,
 167                  int is_64_bit, int extended);
 168
 169 /*
 170  * Address Computation and Large Constant Instructions
 171  */
 172 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
 173 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 174 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 175
 176 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
 177
 178 extern TCGv cpu_gpr[32], cpu_PC;
 179 #if defined(TARGET_MIPS64)
 180 extern TCGv_i64 cpu_gpr_hi[32];
 181 #endif
 182 extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 183 extern TCGv_i32 fpu_fcr0, fpu_fcr31;
 184 extern TCGv_i64 fpu_f64[32];
 185 extern TCGv bcond;
 186
 187 #define LOG_DISAS(...)                                                        \
 188     do {                                                                      \
 189         if (MIPS_DEBUG_DISAS) {                                               \
 190             qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__);                 \
 191         }                                                                     \
 192     } while (0)
 193
 194 #define MIPS_INVAL(op)                                                        \
 195     do {                                                                      \
 196         if (MIPS_DEBUG_DISAS) {                                               \
 197             qemu_log_mask(CPU_LOG_TB_IN_ASM,                                  \
 198                           TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
 199                           ctx->base.pc_next, ctx->opcode, op,                 \
 200                           ctx->opcode >> 26, ctx->opcode & 0x3F,              \
 201                           ((ctx->opcode >> 16) & 0x1F));                      \
 202         }                                                                     \
 203     } while (0)
 204
 205 /* MSA */
 206 void msa_translate_init(void);
 207
 208 /* MXU */
 209 void mxu_translate_init(void);
 210 bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
 211
 212 /* decodetree generated */
 213 bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
 214 bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
 215 bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
 216 #if defined(TARGET_MIPS64)
 217 bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
 218 #endif
 219 bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
 220
 221 /*
 222  * Helpers for implementing sets of trans_* functions.
 223  * Defer the implementation of NAME to FUNC, with optional extra arguments.
 224  */
 225 #define TRANS(NAME, FUNC, ...) \
 226     static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
 227     { return FUNC(ctx, a, __VA_ARGS__); }
 228
 229 static inline bool cpu_is_bigendian(DisasContext *ctx)
 230 {
 231     return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
 232 }
 233
 234 #endif