2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
26 #include "target/ppc/cpu.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
39 #include "hw/ppc/xics.h"
40 #include "hw/ppc/pnv_xscom.h"
42 #include "hw/isa/isa.h"
43 #include "hw/char/serial.h"
44 #include "hw/timer/mc146818rtc.h"
48 #define FDT_MAX_SIZE 0x00100000
50 #define FW_FILE_NAME "skiboot.lid"
51 #define FW_LOAD_ADDR 0x0
52 #define FW_MAX_SIZE 0x00400000
54 #define KERNEL_LOAD_ADDR 0x20000000
55 #define INITRD_LOAD_ADDR 0x40000000
58 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
59 * 4 * 4 sockets * 12 cores * 8 threads = 1536
65 * Memory nodes are created by hostboot, one for each range of memory
66 * that has a different "affinity". In practice, it means one range
69 static void powernv_populate_memory_node(void *fdt
, int chip_id
, hwaddr start
,
73 uint64_t mem_reg_property
[2];
76 mem_reg_property
[0] = cpu_to_be64(start
);
77 mem_reg_property
[1] = cpu_to_be64(size
);
79 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
80 off
= fdt_add_subnode(fdt
, 0, mem_name
);
83 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
84 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
85 sizeof(mem_reg_property
))));
86 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
89 static int get_cpus_node(void *fdt
)
91 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
93 if (cpus_offset
< 0) {
94 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
97 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
98 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
106 * The PowerNV cores (and threads) need to use real HW ids and not an
107 * incremental index like it has been done on other platforms. This HW
108 * id is stored in the CPU PIR, it is used to create cpu nodes in the
109 * device tree, used in XSCOM to address cores and in interrupt
112 static void powernv_create_core_node(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
114 CPUState
*cs
= CPU(DEVICE(pc
->threads
));
115 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
116 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
117 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
118 CPUPPCState
*env
= &cpu
->env
;
119 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
120 uint32_t servers_prop
[smt_threads
];
122 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
123 0xffffffff, 0xffffffff};
124 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
125 uint32_t cpufreq
= 1000000000;
126 uint32_t page_sizes_prop
[64];
127 size_t page_sizes_prop_size
;
128 const uint8_t pa_features
[] = { 24, 0,
129 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
130 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
131 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
132 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
135 int cpus_offset
= get_cpus_node(fdt
);
137 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
138 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
142 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
144 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
145 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
146 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
148 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
149 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
150 env
->dcache_line_size
)));
151 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
152 env
->dcache_line_size
)));
153 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
154 env
->icache_line_size
)));
155 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
156 env
->icache_line_size
)));
158 if (pcc
->l1_dcache_size
) {
159 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
160 pcc
->l1_dcache_size
)));
162 error_report("Warning: Unknown L1 dcache size for cpu");
164 if (pcc
->l1_icache_size
) {
165 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
166 pcc
->l1_icache_size
)));
168 error_report("Warning: Unknown L1 icache size for cpu");
171 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
172 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", env
->slb_nr
)));
174 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
175 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
177 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
178 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
181 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
182 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
183 segs
, sizeof(segs
))));
186 /* Advertise VMX/VSX (vector extensions) if available
187 * 0 / no property == no vector extensions
188 * 1 == VMX / Altivec available
189 * 2 == VSX available */
190 if (env
->insns_flags
& PPC_ALTIVEC
) {
191 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
193 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
196 /* Advertise DFP (Decimal Floating Point) if available
197 * 0 / no property == no DFP
198 * 1 == DFP available */
199 if (env
->insns_flags2
& PPC2_DFP
) {
200 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
203 page_sizes_prop_size
= ppc_create_page_sizes_prop(env
, page_sizes_prop
,
204 sizeof(page_sizes_prop
));
205 if (page_sizes_prop_size
) {
206 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
207 page_sizes_prop
, page_sizes_prop_size
)));
210 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
211 pa_features
, sizeof(pa_features
))));
213 /* Build interrupt servers properties */
214 for (i
= 0; i
< smt_threads
; i
++) {
215 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
217 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
218 servers_prop
, sizeof(servers_prop
))));
221 static void powernv_populate_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
224 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
226 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
227 uint32_t irange
[2], i
, rsize
;
231 irange
[0] = cpu_to_be32(pir
);
232 irange
[1] = cpu_to_be32(nr_threads
);
234 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
235 reg
= g_malloc(rsize
);
236 for (i
= 0; i
< nr_threads
; i
++) {
237 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
238 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
241 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
242 offset
= fdt_add_subnode(fdt
, 0, name
);
246 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
247 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
248 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
249 "PowerPC-External-Interrupt-Presentation")));
250 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
251 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
252 irange
, sizeof(irange
))));
253 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
254 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
258 static int pnv_chip_lpc_offset(PnvChip
*chip
, void *fdt
)
263 name
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
264 (uint64_t) PNV_XSCOM_BASE(chip
), PNV_XSCOM_LPC_BASE
);
265 offset
= fdt_path_offset(fdt
, name
);
270 static void powernv_populate_chip(PnvChip
*chip
, void *fdt
)
272 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
273 char *typename
= pnv_core_typename(pcc
->cpu_model
);
274 size_t typesize
= object_type_get_instance_size(typename
);
277 pnv_xscom_populate(chip
, fdt
, 0);
279 /* The default LPC bus of a multichip system is on chip 0. It's
280 * recognized by the firmware (skiboot) using a "primary"
283 if (chip
->chip_id
== 0x0) {
284 int lpc_offset
= pnv_chip_lpc_offset(chip
, fdt
);
286 _FDT((fdt_setprop(fdt
, lpc_offset
, "primary", NULL
, 0)));
289 for (i
= 0; i
< chip
->nr_cores
; i
++) {
290 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
292 powernv_create_core_node(chip
, pnv_core
, fdt
);
294 /* Interrupt Control Presenters (ICP). One per core. */
295 powernv_populate_icp(chip
, fdt
, pnv_core
->pir
,
296 CPU_CORE(pnv_core
)->nr_threads
);
299 if (chip
->ram_size
) {
300 powernv_populate_memory_node(fdt
, chip
->chip_id
, chip
->ram_start
,
306 static void powernv_populate_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
308 uint32_t io_base
= d
->ioport_id
;
309 uint32_t io_regs
[] = {
311 cpu_to_be32(io_base
),
317 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
318 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
322 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
323 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
326 static void powernv_populate_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
328 const char compatible
[] = "ns16550\0pnpPNP,501";
329 uint32_t io_base
= d
->ioport_id
;
330 uint32_t io_regs
[] = {
332 cpu_to_be32(io_base
),
338 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
339 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
343 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
344 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
345 sizeof(compatible
))));
347 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
348 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
349 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
350 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
351 fdt_get_phandle(fdt
, lpc_off
))));
353 /* This is needed by Linux */
354 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
357 typedef struct ForeachPopulateArgs
{
360 } ForeachPopulateArgs
;
362 static int powernv_populate_isa_device(DeviceState
*dev
, void *opaque
)
364 ForeachPopulateArgs
*args
= opaque
;
365 ISADevice
*d
= ISA_DEVICE(dev
);
367 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
368 powernv_populate_rtc(d
, args
->fdt
, args
->offset
);
369 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
370 powernv_populate_serial(d
, args
->fdt
, args
->offset
);
372 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
379 static void powernv_populate_isa(ISABus
*bus
, void *fdt
, int lpc_offset
)
381 ForeachPopulateArgs args
= {
383 .offset
= lpc_offset
,
386 /* ISA devices are not necessarily parented to the ISA bus so we
387 * can not use object_child_foreach() */
388 qbus_walk_children(BUS(bus
), powernv_populate_isa_device
,
389 NULL
, NULL
, NULL
, &args
);
392 static void *powernv_create_fdt(MachineState
*machine
)
394 const char plat_compat
[] = "qemu,powernv\0ibm,powernv";
395 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
402 fdt
= g_malloc0(FDT_MAX_SIZE
);
403 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
406 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
407 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
408 _FDT((fdt_setprop_string(fdt
, 0, "model",
409 "IBM PowerNV (emulated by qemu)")));
410 _FDT((fdt_setprop(fdt
, 0, "compatible", plat_compat
,
411 sizeof(plat_compat
))));
413 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
414 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
416 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
420 off
= fdt_add_subnode(fdt
, 0, "chosen");
421 if (machine
->kernel_cmdline
) {
422 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
423 machine
->kernel_cmdline
)));
426 if (pnv
->initrd_size
) {
427 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
428 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
430 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
431 &start_prop
, sizeof(start_prop
))));
432 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
433 &end_prop
, sizeof(end_prop
))));
436 /* Populate device tree for each chip */
437 for (i
= 0; i
< pnv
->num_chips
; i
++) {
438 powernv_populate_chip(pnv
->chips
[i
], fdt
);
441 /* Populate ISA devices on chip 0 */
442 lpc_offset
= pnv_chip_lpc_offset(pnv
->chips
[0], fdt
);
443 powernv_populate_isa(pnv
->isa_bus
, fdt
, lpc_offset
);
447 static void ppc_powernv_reset(void)
449 MachineState
*machine
= MACHINE(qdev_get_machine());
452 qemu_devices_reset();
454 fdt
= powernv_create_fdt(machine
);
456 /* Pack resulting tree */
457 _FDT((fdt_pack(fdt
)));
459 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
462 static ISABus
*pnv_isa_create(PnvChip
*chip
)
464 PnvLpcController
*lpc
= &chip
->lpc
;
467 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
469 /* let isa_bus_new() create its own bridge on SysBus otherwise
470 * devices speficied on the command line won't find the bus and
471 * will fail to create.
473 isa_bus
= isa_bus_new(NULL
, &lpc
->isa_mem
, &lpc
->isa_io
,
476 irqs
= pnv_lpc_isa_irq_create(lpc
, pcc
->chip_type
, ISA_NUM_IRQS
);
478 isa_bus_irqs(isa_bus
, irqs
);
482 static void ppc_powernv_init(MachineState
*machine
)
484 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
492 if (machine
->ram_size
< (1 * G_BYTE
)) {
493 error_report("Warning: skiboot may not work with < 1GB of RAM");
496 ram
= g_new(MemoryRegion
, 1);
497 memory_region_allocate_system_memory(ram
, NULL
, "ppc_powernv.ram",
499 memory_region_add_subregion(get_system_memory(), 0, ram
);
501 /* load skiboot firmware */
502 if (bios_name
== NULL
) {
503 bios_name
= FW_FILE_NAME
;
506 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
508 fw_size
= load_image_targphys(fw_filename
, FW_LOAD_ADDR
, FW_MAX_SIZE
);
510 error_report("Could not load OPAL '%s'", fw_filename
);
516 if (machine
->kernel_filename
) {
519 kernel_size
= load_image_targphys(machine
->kernel_filename
,
520 KERNEL_LOAD_ADDR
, 0x2000000);
521 if (kernel_size
< 0) {
522 error_report("Could not load kernel '%s'",
523 machine
->kernel_filename
);
529 if (machine
->initrd_filename
) {
530 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
531 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
532 pnv
->initrd_base
, 0x10000000); /* 128MB max */
533 if (pnv
->initrd_size
< 0) {
534 error_report("Could not load initial ram disk '%s'",
535 machine
->initrd_filename
);
540 /* We need some cpu model to instantiate the PnvChip class */
541 if (machine
->cpu_model
== NULL
) {
542 machine
->cpu_model
= "POWER8";
545 /* Create the processor chips */
546 chip_typename
= g_strdup_printf(TYPE_PNV_CHIP
"-%s", machine
->cpu_model
);
547 if (!object_class_by_name(chip_typename
)) {
548 error_report("qemu: invalid CPU model '%s' for %s machine",
549 machine
->cpu_model
, MACHINE_GET_CLASS(machine
)->name
);
553 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
554 for (i
= 0; i
< pnv
->num_chips
; i
++) {
556 Object
*chip
= object_new(chip_typename
);
558 pnv
->chips
[i
] = PNV_CHIP(chip
);
560 /* TODO: put all the memory in one node on chip 0 until we find a
561 * way to specify different ranges for each chip
564 object_property_set_int(chip
, machine
->ram_size
, "ram-size",
568 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
569 object_property_add_child(OBJECT(pnv
), chip_name
, chip
, &error_fatal
);
570 object_property_set_int(chip
, PNV_CHIP_HWID(i
), "chip-id",
572 object_property_set_int(chip
, smp_cores
, "nr-cores", &error_fatal
);
573 object_property_set_bool(chip
, true, "realized", &error_fatal
);
575 g_free(chip_typename
);
577 /* Instantiate ISA bus on chip 0 */
578 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0]);
580 /* Create serial port */
581 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_SERIAL_PORTS
);
583 /* Create an RTC ISA device too */
584 rtc_init(pnv
->isa_bus
, 2000, NULL
);
588 * 0:21 Reserved - Read as zeros
593 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
595 return (chip
->chip_id
<< 7) | (core_id
<< 3);
599 * 0:48 Reserved - Read as zeroes
602 * 56 Reserved - Read as zero
606 * We only care about the lower bits. uint32_t is fine for the moment.
608 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
610 return (chip
->chip_id
<< 8) | (core_id
<< 2);
613 /* Allowed core identifiers on a POWER8 Processor Chip :
622 * <EX7,8 reserved> <reserved>
631 #define POWER8E_CORE_MASK (0x7070ull)
632 #define POWER8_CORE_MASK (0x7e7eull)
635 * POWER9 has 24 cores, ids starting at 0x20
637 #define POWER9_CORE_MASK (0xffffff00000000ull)
639 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
641 DeviceClass
*dc
= DEVICE_CLASS(klass
);
642 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
644 k
->cpu_model
= "POWER8E";
645 k
->chip_type
= PNV_CHIP_POWER8E
;
646 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
647 k
->cores_mask
= POWER8E_CORE_MASK
;
648 k
->core_pir
= pnv_chip_core_pir_p8
;
649 k
->xscom_base
= 0x003fc0000000000ull
;
650 k
->xscom_core_base
= 0x10000000ull
;
651 dc
->desc
= "PowerNV Chip POWER8E";
654 static const TypeInfo pnv_chip_power8e_info
= {
655 .name
= TYPE_PNV_CHIP_POWER8E
,
656 .parent
= TYPE_PNV_CHIP
,
657 .instance_size
= sizeof(PnvChip
),
658 .class_init
= pnv_chip_power8e_class_init
,
661 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
663 DeviceClass
*dc
= DEVICE_CLASS(klass
);
664 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
666 k
->cpu_model
= "POWER8";
667 k
->chip_type
= PNV_CHIP_POWER8
;
668 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
669 k
->cores_mask
= POWER8_CORE_MASK
;
670 k
->core_pir
= pnv_chip_core_pir_p8
;
671 k
->xscom_base
= 0x003fc0000000000ull
;
672 k
->xscom_core_base
= 0x10000000ull
;
673 dc
->desc
= "PowerNV Chip POWER8";
676 static const TypeInfo pnv_chip_power8_info
= {
677 .name
= TYPE_PNV_CHIP_POWER8
,
678 .parent
= TYPE_PNV_CHIP
,
679 .instance_size
= sizeof(PnvChip
),
680 .class_init
= pnv_chip_power8_class_init
,
683 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
685 DeviceClass
*dc
= DEVICE_CLASS(klass
);
686 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
688 k
->cpu_model
= "POWER8NVL";
689 k
->chip_type
= PNV_CHIP_POWER8NVL
;
690 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
691 k
->cores_mask
= POWER8_CORE_MASK
;
692 k
->core_pir
= pnv_chip_core_pir_p8
;
693 k
->xscom_base
= 0x003fc0000000000ull
;
694 k
->xscom_core_base
= 0x10000000ull
;
695 dc
->desc
= "PowerNV Chip POWER8NVL";
698 static const TypeInfo pnv_chip_power8nvl_info
= {
699 .name
= TYPE_PNV_CHIP_POWER8NVL
,
700 .parent
= TYPE_PNV_CHIP
,
701 .instance_size
= sizeof(PnvChip
),
702 .class_init
= pnv_chip_power8nvl_class_init
,
705 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
707 DeviceClass
*dc
= DEVICE_CLASS(klass
);
708 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
710 k
->cpu_model
= "POWER9";
711 k
->chip_type
= PNV_CHIP_POWER9
;
712 k
->chip_cfam_id
= 0x100d104980000000ull
; /* P9 Nimbus DD1.0 */
713 k
->cores_mask
= POWER9_CORE_MASK
;
714 k
->core_pir
= pnv_chip_core_pir_p9
;
715 k
->xscom_base
= 0x00603fc00000000ull
;
716 k
->xscom_core_base
= 0x0ull
;
717 dc
->desc
= "PowerNV Chip POWER9";
720 static const TypeInfo pnv_chip_power9_info
= {
721 .name
= TYPE_PNV_CHIP_POWER9
,
722 .parent
= TYPE_PNV_CHIP
,
723 .instance_size
= sizeof(PnvChip
),
724 .class_init
= pnv_chip_power9_class_init
,
727 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
729 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
733 * No custom mask for this chip, let's use the default one from *
736 if (!chip
->cores_mask
) {
737 chip
->cores_mask
= pcc
->cores_mask
;
740 /* filter alien core ids ! some are reserved */
741 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
742 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
746 chip
->cores_mask
&= pcc
->cores_mask
;
748 /* now that we have a sane layout, let check the number of cores */
749 cores_max
= ctpop64(chip
->cores_mask
);
750 if (chip
->nr_cores
> cores_max
) {
751 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
757 static void pnv_chip_init(Object
*obj
)
759 PnvChip
*chip
= PNV_CHIP(obj
);
760 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
762 chip
->xscom_base
= pcc
->xscom_base
;
764 object_initialize(&chip
->lpc
, sizeof(chip
->lpc
), TYPE_PNV_LPC
);
765 object_property_add_child(obj
, "lpc", OBJECT(&chip
->lpc
), NULL
);
767 object_initialize(&chip
->psi
, sizeof(chip
->psi
), TYPE_PNV_PSI
);
768 object_property_add_child(obj
, "psi", OBJECT(&chip
->psi
), NULL
);
769 object_property_add_const_link(OBJECT(&chip
->psi
), "xics",
770 OBJECT(qdev_get_machine()), &error_abort
);
772 object_initialize(&chip
->occ
, sizeof(chip
->occ
), TYPE_PNV_OCC
);
773 object_property_add_child(obj
, "occ", OBJECT(&chip
->occ
), NULL
);
774 object_property_add_const_link(OBJECT(&chip
->occ
), "psi",
775 OBJECT(&chip
->psi
), &error_abort
);
777 /* The LPC controller needs PSI to generate interrupts */
778 object_property_add_const_link(OBJECT(&chip
->lpc
), "psi",
779 OBJECT(&chip
->psi
), &error_abort
);
782 static void pnv_chip_icp_realize(PnvChip
*chip
, Error
**errp
)
784 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
785 char *typename
= pnv_core_typename(pcc
->cpu_model
);
786 size_t typesize
= object_type_get_instance_size(typename
);
789 XICSFabric
*xi
= XICS_FABRIC(qdev_get_machine());
791 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
792 memory_region_init(&chip
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
793 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip
->icp_mmio
);
796 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
798 /* Map the ICP registers for each thread */
799 for (i
= 0; i
< chip
->nr_cores
; i
++) {
800 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
801 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
803 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
804 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
805 PnvICPState
*icp
= PNV_ICP(xics_icp_get(xi
, pir
));
807 memory_region_add_subregion(&chip
->icp_mmio
, pir
<< 12, &icp
->mmio
);
814 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
816 PnvChip
*chip
= PNV_CHIP(dev
);
818 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
819 char *typename
= pnv_core_typename(pcc
->cpu_model
);
820 size_t typesize
= object_type_get_instance_size(typename
);
823 if (!object_class_by_name(typename
)) {
824 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
829 pnv_xscom_realize(chip
, &error
);
831 error_propagate(errp
, error
);
834 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
837 pnv_chip_core_sanitize(chip
, &error
);
839 error_propagate(errp
, error
);
843 chip
->cores
= g_malloc0(typesize
* chip
->nr_cores
);
845 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
846 && (i
< chip
->nr_cores
); core_hwid
++) {
848 void *pnv_core
= chip
->cores
+ i
* typesize
;
850 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
854 object_initialize(pnv_core
, typesize
, typename
);
855 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
856 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
),
858 object_property_set_int(OBJECT(pnv_core
), smp_threads
, "nr-threads",
860 object_property_set_int(OBJECT(pnv_core
), core_hwid
,
861 CPU_CORE_PROP_CORE_ID
, &error_fatal
);
862 object_property_set_int(OBJECT(pnv_core
),
863 pcc
->core_pir(chip
, core_hwid
),
864 "pir", &error_fatal
);
865 object_property_add_const_link(OBJECT(pnv_core
), "xics",
866 qdev_get_machine(), &error_fatal
);
867 object_property_set_bool(OBJECT(pnv_core
), true, "realized",
869 object_unref(OBJECT(pnv_core
));
871 /* Each core has an XSCOM MMIO region */
872 pnv_xscom_add_subregion(chip
,
873 PNV_XSCOM_EX_CORE_BASE(pcc
->xscom_core_base
,
875 &PNV_CORE(pnv_core
)->xscom_regs
);
880 /* Create LPC controller */
881 object_property_set_bool(OBJECT(&chip
->lpc
), true, "realized",
883 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip
->lpc
.xscom_regs
);
885 /* Interrupt Management Area. This is the memory region holding
886 * all the Interrupt Control Presenter (ICP) registers */
887 pnv_chip_icp_realize(chip
, &error
);
889 error_propagate(errp
, error
);
893 /* Processor Service Interface (PSI) Host Bridge */
894 object_property_set_int(OBJECT(&chip
->psi
), PNV_PSIHB_BASE(chip
),
895 "bar", &error_fatal
);
896 object_property_set_bool(OBJECT(&chip
->psi
), true, "realized", &error
);
898 error_propagate(errp
, error
);
901 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
, &chip
->psi
.xscom_regs
);
903 /* Create the simplified OCC model */
904 object_property_set_bool(OBJECT(&chip
->occ
), true, "realized", &error
);
906 error_propagate(errp
, error
);
909 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip
->occ
.xscom_regs
);
912 static Property pnv_chip_properties
[] = {
913 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
914 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
915 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
916 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
917 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
918 DEFINE_PROP_END_OF_LIST(),
921 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
923 DeviceClass
*dc
= DEVICE_CLASS(klass
);
925 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
926 dc
->realize
= pnv_chip_realize
;
927 dc
->props
= pnv_chip_properties
;
928 dc
->desc
= "PowerNV Chip";
931 static const TypeInfo pnv_chip_info
= {
932 .name
= TYPE_PNV_CHIP
,
933 .parent
= TYPE_SYS_BUS_DEVICE
,
934 .class_init
= pnv_chip_class_init
,
935 .instance_init
= pnv_chip_init
,
936 .class_size
= sizeof(PnvChipClass
),
940 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
942 PnvMachineState
*pnv
= POWERNV_MACHINE(xi
);
945 for (i
= 0; i
< pnv
->num_chips
; i
++) {
946 if (ics_valid_irq(&pnv
->chips
[i
]->psi
.ics
, irq
)) {
947 return &pnv
->chips
[i
]->psi
.ics
;
953 static void pnv_ics_resend(XICSFabric
*xi
)
955 PnvMachineState
*pnv
= POWERNV_MACHINE(xi
);
958 for (i
= 0; i
< pnv
->num_chips
; i
++) {
959 ics_resend(&pnv
->chips
[i
]->psi
.ics
);
963 static PowerPCCPU
*ppc_get_vcpu_by_pir(int pir
)
968 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
969 CPUPPCState
*env
= &cpu
->env
;
971 if (env
->spr_cb
[SPR_PIR
].default_value
== pir
) {
979 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
981 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
983 return cpu
? ICP(cpu
->intc
) : NULL
;
986 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
989 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
994 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
996 icp_pic_print_info(ICP(cpu
->intc
), mon
);
999 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1000 ics_pic_print_info(&pnv
->chips
[i
]->psi
.ics
, mon
);
1004 static void pnv_get_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1005 void *opaque
, Error
**errp
)
1007 visit_type_uint32(v
, name
, &POWERNV_MACHINE(obj
)->num_chips
, errp
);
1010 static void pnv_set_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1011 void *opaque
, Error
**errp
)
1013 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1015 Error
*local_err
= NULL
;
1017 visit_type_uint32(v
, name
, &num_chips
, &local_err
);
1019 error_propagate(errp
, local_err
);
1024 * TODO: should we decide on how many chips we can create based
1025 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1027 if (!is_power_of_2(num_chips
) || num_chips
> 4) {
1028 error_setg(errp
, "invalid number of chips: '%d'", num_chips
);
1032 pnv
->num_chips
= num_chips
;
1035 static void powernv_machine_initfn(Object
*obj
)
1037 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1041 static void powernv_machine_class_props_init(ObjectClass
*oc
)
1043 object_class_property_add(oc
, "num-chips", "uint32_t",
1044 pnv_get_num_chips
, pnv_set_num_chips
,
1046 object_class_property_set_description(oc
, "num-chips",
1047 "Specifies the number of processor chips",
1051 static void powernv_machine_class_init(ObjectClass
*oc
, void *data
)
1053 MachineClass
*mc
= MACHINE_CLASS(oc
);
1054 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1055 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1057 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1058 mc
->init
= ppc_powernv_init
;
1059 mc
->reset
= ppc_powernv_reset
;
1060 mc
->max_cpus
= MAX_CPUS
;
1061 mc
->block_default_type
= IF_IDE
; /* Pnv provides a AHCI device for
1063 mc
->no_parallel
= 1;
1064 mc
->default_boot_order
= NULL
;
1065 mc
->default_ram_size
= 1 * G_BYTE
;
1066 xic
->icp_get
= pnv_icp_get
;
1067 xic
->ics_get
= pnv_ics_get
;
1068 xic
->ics_resend
= pnv_ics_resend
;
1069 ispc
->print_info
= pnv_pic_print_info
;
1071 powernv_machine_class_props_init(oc
);
1074 static const TypeInfo powernv_machine_info
= {
1075 .name
= TYPE_POWERNV_MACHINE
,
1076 .parent
= TYPE_MACHINE
,
1077 .instance_size
= sizeof(PnvMachineState
),
1078 .instance_init
= powernv_machine_initfn
,
1079 .class_init
= powernv_machine_class_init
,
1080 .interfaces
= (InterfaceInfo
[]) {
1081 { TYPE_XICS_FABRIC
},
1082 { TYPE_INTERRUPT_STATS_PROVIDER
},
1087 static void powernv_machine_register_types(void)
1089 type_register_static(&powernv_machine_info
);
1090 type_register_static(&pnv_chip_info
);
1091 type_register_static(&pnv_chip_power8e_info
);
1092 type_register_static(&pnv_chip_power8_info
);
1093 type_register_static(&pnv_chip_power8nvl_info
);
1094 type_register_static(&pnv_chip_power9_info
);
1097 type_init(powernv_machine_register_types
)