hw/arm/exynos4210.c

   1 /*
   2  *  Samsung exynos4210 SoC emulation
   3  *
   4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5  *    Maksim Kozlov <m.kozlov@samsung.com>
   6  *    Evgeny Voevodin <e.voevodin@samsung.com>
   7  *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License as published by the
  11  *  Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "cpu.h"
  27 #include "hw/cpu/a9mpcore.h"
  28 #include "hw/irq.h"
  29 #include "sysemu/blockdev.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/sysbus.h"
  32 #include "hw/arm/boot.h"
  33 #include "hw/loader.h"
  34 #include "hw/qdev-properties.h"
  35 #include "hw/arm/exynos4210.h"
  36 #include "hw/sd/sdhci.h"
  37 #include "hw/usb/hcd-ehci.h"
  38
  39 #define EXYNOS4210_CHIPID_ADDR         0x10000000
  40
  41 /* PWM */
  42 #define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  43
  44 /* RTC */
  45 #define EXYNOS4210_RTC_BASE_ADDR       0x10070000
  46
  47 /* MCT */
  48 #define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  49
  50 /* I2C */
  51 #define EXYNOS4210_I2C_SHIFT           0x00010000
  52 #define EXYNOS4210_I2C_BASE_ADDR       0x13860000
  53 /* Interrupt Group of External Interrupt Combiner for I2C */
  54 #define EXYNOS4210_I2C_INTG            27
  55 #define EXYNOS4210_HDMI_INTG           16
  56
  57 /* UART's definitions */
  58 #define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  59 #define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  60 #define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  61 #define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  62 #define EXYNOS4210_UART0_FIFO_SIZE     256
  63 #define EXYNOS4210_UART1_FIFO_SIZE     64
  64 #define EXYNOS4210_UART2_FIFO_SIZE     16
  65 #define EXYNOS4210_UART3_FIFO_SIZE     16
  66 /* Interrupt Group of External Interrupt Combiner for UART */
  67 #define EXYNOS4210_UART_INT_GRP        26
  68
  69 /* External GIC */
  70 #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  71 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  72
  73 /* Combiner */
  74 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  75 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  76
  77 /* SD/MMC host controllers */
  78 #define EXYNOS4210_SDHCI_CAPABILITIES       0x05E80080
  79 #define EXYNOS4210_SDHCI_BASE_ADDR          0x12510000
  80 #define EXYNOS4210_SDHCI_ADDR(n)            (EXYNOS4210_SDHCI_BASE_ADDR + \
  81                                                 0x00010000 * (n))
  82 #define EXYNOS4210_SDHCI_NUMBER             4
  83
  84 /* PMU SFR base address */
  85 #define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  86
  87 /* Clock controller SFR base address */
  88 #define EXYNOS4210_CLK_BASE_ADDR            0x10030000
  89
  90 /* PRNG/HASH SFR base address */
  91 #define EXYNOS4210_RNG_BASE_ADDR            0x10830400
  92
  93 /* Display controllers (FIMD) */
  94 #define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  95
  96 /* EHCI */
  97 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
  98
  99 /* DMA */
 100 #define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
 101 #define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
 102 #define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
 103
 104 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
 105                                     0x09, 0x00, 0x00, 0x00 };
 106
 107 static uint64_t exynos4210_chipid_and_omr_read(void *opaque, hwaddr offset,
 108                                                unsigned size)
 109 {
 110     assert(offset < sizeof(chipid_and_omr));
 111     return chipid_and_omr[offset];
 112 }
 113
 114 static void exynos4210_chipid_and_omr_write(void *opaque, hwaddr offset,
 115                                             uint64_t value, unsigned size)
 116 {
 117     return;
 118 }
 119
 120 static const MemoryRegionOps exynos4210_chipid_and_omr_ops = {
 121     .read = exynos4210_chipid_and_omr_read,
 122     .write = exynos4210_chipid_and_omr_write,
 123     .endianness = DEVICE_NATIVE_ENDIAN,
 124     .impl = {
 125         .max_access_size = 1,
 126     }
 127 };
 128
 129 void exynos4210_write_secondary(ARMCPU *cpu,
 130         const struct arm_boot_info *info)
 131 {
 132     int n;
 133     uint32_t smpboot[] = {
 134         0xe59f3034, /* ldr r3, External gic_cpu_if */
 135         0xe59f2034, /* ldr r2, Internal gic_cpu_if */
 136         0xe59f0034, /* ldr r0, startaddr */
 137         0xe3a01001, /* mov r1, #1 */
 138         0xe5821000, /* str r1, [r2] */
 139         0xe5831000, /* str r1, [r3] */
 140         0xe3a010ff, /* mov r1, #0xff */
 141         0xe5821004, /* str r1, [r2, #4] */
 142         0xe5831004, /* str r1, [r3, #4] */
 143         0xf57ff04f, /* dsb */
 144         0xe320f003, /* wfi */
 145         0xe5901000, /* ldr     r1, [r0] */
 146         0xe1110001, /* tst     r1, r1 */
 147         0x0afffffb, /* beq     <wfi> */
 148         0xe12fff11, /* bx      r1 */
 149         EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
 150         0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
 151         0           /* bootreg: Boot register address is held here */
 152     };
 153     smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
 154     smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
 155     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
 156         smpboot[n] = tswap32(smpboot[n]);
 157     }
 158     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
 159                        info->smp_loader_start);
 160 }
 161
 162 static uint64_t exynos4210_calc_affinity(int cpu)
 163 {
 164     /* Exynos4210 has 0x9 as cluster ID */
 165     return (0x9 << ARM_AFF1_SHIFT) | cpu;
 166 }
 167
 168 static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
 169                                  qemu_irq irq, int nreq, int nevents, int width)
 170 {
 171     SysBusDevice *busdev;
 172     DeviceState *dev;
 173     int i;
 174
 175     dev = qdev_new("pl330");
 176     object_property_set_link(OBJECT(dev), "memory",
 177                              OBJECT(get_system_memory()),
 178                              &error_fatal);
 179     qdev_prop_set_uint8(dev, "num_events", nevents);
 180     qdev_prop_set_uint8(dev, "num_chnls",  8);
 181     qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
 182
 183     qdev_prop_set_uint8(dev, "wr_cap", 4);
 184     qdev_prop_set_uint8(dev, "wr_q_dep", 8);
 185     qdev_prop_set_uint8(dev, "rd_cap", 4);
 186     qdev_prop_set_uint8(dev, "rd_q_dep", 8);
 187     qdev_prop_set_uint8(dev, "data_width", width);
 188     qdev_prop_set_uint16(dev, "data_buffer_dep", width);
 189     busdev = SYS_BUS_DEVICE(dev);
 190     sysbus_realize_and_unref(busdev, &error_fatal);
 191     sysbus_mmio_map(busdev, 0, base);
 192
 193     object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1,
 194                             &error_abort);
 195     qdev_realize(DEVICE(orgate), NULL, &error_abort);
 196
 197     for (i = 0; i < nevents + 1; i++) {
 198         sysbus_connect_irq(busdev, i, qdev_get_gpio_in(DEVICE(orgate), i));
 199     }
 200     qdev_connect_gpio_out(DEVICE(orgate), 0, irq);
 201     return dev;
 202 }
 203
 204 static void exynos4210_realize(DeviceState *socdev, Error **errp)
 205 {
 206     Exynos4210State *s = EXYNOS4210_SOC(socdev);
 207     MemoryRegion *system_mem = get_system_memory();
 208     SysBusDevice *busdev;
 209     DeviceState *dev, *uart[4], *pl330[3];
 210     int i, n;
 211
 212     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 213         Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
 214
 215         /* By default A9 CPUs have EL3 enabled.  This board does not currently
 216          * support EL3 so the CPU EL3 property is disabled before realization.
 217          */
 218         if (object_property_find(cpuobj, "has_el3")) {
 219             object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
 220         }
 221
 222         s->cpu[n] = ARM_CPU(cpuobj);
 223         object_property_set_int(cpuobj, "mp-affinity",
 224                                 exynos4210_calc_affinity(n), &error_abort);
 225         object_property_set_int(cpuobj, "reset-cbar",
 226                                 EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
 227                                 &error_abort);
 228         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 229     }
 230
 231     /*** IRQs ***/
 232
 233     s->irq_table = exynos4210_init_irq(&s->irqs);
 234
 235     /* IRQ Gate */
 236     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
 237         DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
 238         object_property_set_int(OBJECT(orgate), "num-lines",
 239                                 EXYNOS4210_IRQ_GATE_NINPUTS,
 240                                 &error_abort);
 241         qdev_realize(orgate, NULL, &error_abort);
 242         qdev_connect_gpio_out(orgate, 0,
 243                               qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
 244     }
 245
 246     /* Private memory region and Internal GIC */
 247     qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
 248     busdev = SYS_BUS_DEVICE(&s->a9mpcore);
 249     sysbus_realize(busdev, &error_fatal);
 250     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 251     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 252         sysbus_connect_irq(busdev, n,
 253                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
 254     }
 255
 256     /* Cache controller */
 257     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 258
 259     /* External GIC */
 260     dev = qdev_new("exynos4210.gic");
 261     qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 262     busdev = SYS_BUS_DEVICE(dev);
 263     sysbus_realize_and_unref(busdev, &error_fatal);
 264     /* Map CPU interface */
 265     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 266     /* Map Distributer interface */
 267     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 268     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 269         sysbus_connect_irq(busdev, n,
 270                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
 271     }
 272     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 273         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 274     }
 275
 276     /* Internal Interrupt Combiner */
 277     dev = qdev_new("exynos4210.combiner");
 278     busdev = SYS_BUS_DEVICE(dev);
 279     sysbus_realize_and_unref(busdev, &error_fatal);
 280     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 281         sysbus_connect_irq(busdev, n,
 282                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
 283     }
 284     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 285     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 286
 287     /* External Interrupt Combiner */
 288     dev = qdev_new("exynos4210.combiner");
 289     qdev_prop_set_uint32(dev, "external", 1);
 290     busdev = SYS_BUS_DEVICE(dev);
 291     sysbus_realize_and_unref(busdev, &error_fatal);
 292     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 293         sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 294     }
 295     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 296     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 297
 298     /* Initialize board IRQs. */
 299     exynos4210_init_board_irqs(&s->irqs);
 300
 301     /*** Memory ***/
 302
 303     /* Chip-ID and OMR */
 304     memory_region_init_io(&s->chipid_mem, OBJECT(socdev),
 305                           &exynos4210_chipid_and_omr_ops, NULL,
 306                           "exynos4210.chipid", sizeof(chipid_and_omr));
 307     memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 308                                 &s->chipid_mem);
 309
 310     /* Internal ROM */
 311     memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom",
 312                            EXYNOS4210_IROM_SIZE, &error_fatal);
 313     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 314                                 &s->irom_mem);
 315     /* mirror of iROM */
 316     memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev),
 317                              "exynos4210.irom_alias", &s->irom_mem, 0,
 318                              EXYNOS4210_IROM_SIZE);
 319     memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 320                                 &s->irom_alias_mem);
 321
 322     /* Internal RAM */
 323     memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram",
 324                            EXYNOS4210_IRAM_SIZE, &error_fatal);
 325     memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 326                                 &s->iram_mem);
 327
 328    /* PMU.
 329     * The only reason of existence at the moment is that secondary CPU boot
 330     * loader uses PMU INFORM5 register as a holding pen.
 331     */
 332     sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 333
 334     sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);
 335     sysbus_create_simple("exynos4210.rng", EXYNOS4210_RNG_BASE_ADDR, NULL);
 336
 337     /* PWM */
 338     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 339                           s->irq_table[exynos4210_get_irq(22, 0)],
 340                           s->irq_table[exynos4210_get_irq(22, 1)],
 341                           s->irq_table[exynos4210_get_irq(22, 2)],
 342                           s->irq_table[exynos4210_get_irq(22, 3)],
 343                           s->irq_table[exynos4210_get_irq(22, 4)],
 344                           NULL);
 345     /* RTC */
 346     sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
 347                           s->irq_table[exynos4210_get_irq(23, 0)],
 348                           s->irq_table[exynos4210_get_irq(23, 1)],
 349                           NULL);
 350
 351     /* Multi Core Timer */
 352     dev = qdev_new("exynos4210.mct");
 353     busdev = SYS_BUS_DEVICE(dev);
 354     sysbus_realize_and_unref(busdev, &error_fatal);
 355     for (n = 0; n < 4; n++) {
 356         /* Connect global timer interrupts to Combiner gpio_in */
 357         sysbus_connect_irq(busdev, n,
 358                 s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 359     }
 360     /* Connect local timer interrupts to Combiner gpio_in */
 361     sysbus_connect_irq(busdev, 4,
 362             s->irq_table[exynos4210_get_irq(51, 0)]);
 363     sysbus_connect_irq(busdev, 5,
 364             s->irq_table[exynos4210_get_irq(35, 3)]);
 365     sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 366
 367     /*** I2C ***/
 368     for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
 369         uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
 370         qemu_irq i2c_irq;
 371
 372         if (n < 8) {
 373             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
 374         } else {
 375             i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
 376         }
 377
 378         dev = qdev_new("exynos4210.i2c");
 379         busdev = SYS_BUS_DEVICE(dev);
 380         sysbus_realize_and_unref(busdev, &error_fatal);
 381         sysbus_connect_irq(busdev, 0, i2c_irq);
 382         sysbus_mmio_map(busdev, 0, addr);
 383         s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 384     }
 385
 386
 387     /*** UARTs ***/
 388     uart[0] = exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 389                            EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
 390                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 391
 392     uart[1] = exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 393                            EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
 394                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 395
 396     uart[2] = exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 397                            EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
 398                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 399
 400     uart[3] = exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 401                            EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
 402                   s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 403
 404     /*** SD/MMC host controllers ***/
 405     for (n = 0; n < EXYNOS4210_SDHCI_NUMBER; n++) {
 406         DeviceState *carddev;
 407         BlockBackend *blk;
 408         DriveInfo *di;
 409
 410         /* Compatible with:
 411          * - SD Host Controller Specification Version 2.0
 412          * - SDIO Specification Version 2.0
 413          * - MMC Specification Version 4.3
 414          * - SDMA
 415          * - ADMA2
 416          *
 417          * As this part of the Exynos4210 is not publically available,
 418          * we used the "HS-MMC Controller S3C2416X RISC Microprocessor"
 419          * public datasheet which is very similar (implementing
 420          * MMC Specification Version 4.0 being the only difference noted)
 421          */
 422         dev = qdev_new(TYPE_S3C_SDHCI);
 423         qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);
 424
 425         busdev = SYS_BUS_DEVICE(dev);
 426         sysbus_realize_and_unref(busdev, &error_fatal);
 427         sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
 428         sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
 429
 430         di = drive_get(IF_SD, 0, n);
 431         blk = di ? blk_by_legacy_dinfo(di) : NULL;
 432         carddev = qdev_new(TYPE_SD_CARD);
 433         qdev_prop_set_drive(carddev, "drive", blk);
 434         qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
 435                                &error_fatal);
 436     }
 437
 438     /*** Display controller (FIMD) ***/
 439     sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 440             s->irq_table[exynos4210_get_irq(11, 0)],
 441             s->irq_table[exynos4210_get_irq(11, 1)],
 442             s->irq_table[exynos4210_get_irq(11, 2)],
 443             NULL);
 444
 445     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
 446             s->irq_table[exynos4210_get_irq(28, 3)]);
 447
 448     /*** DMA controllers ***/
 449     pl330[0] = pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
 450                             &s->pl330_irq_orgate[0],
 451                             s->irq_table[exynos4210_get_irq(21, 0)],
 452                             32, 32, 32);
 453     pl330[1] = pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
 454                             &s->pl330_irq_orgate[1],
 455                             s->irq_table[exynos4210_get_irq(21, 1)],
 456                             32, 32, 32);
 457     pl330[2] = pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
 458                             &s->pl330_irq_orgate[2],
 459                             s->irq_table[exynos4210_get_irq(20, 1)],
 460                             1, 31, 64);
 461
 462     sysbus_connect_irq(SYS_BUS_DEVICE(uart[0]), 1,
 463                        qdev_get_gpio_in(pl330[0], 15));
 464     sysbus_connect_irq(SYS_BUS_DEVICE(uart[1]), 1,
 465                        qdev_get_gpio_in(pl330[1], 15));
 466     sysbus_connect_irq(SYS_BUS_DEVICE(uart[2]), 1,
 467                        qdev_get_gpio_in(pl330[0], 17));
 468     sysbus_connect_irq(SYS_BUS_DEVICE(uart[3]), 1,
 469                        qdev_get_gpio_in(pl330[1], 17));
 470 }
 471
 472 static void exynos4210_init(Object *obj)
 473 {
 474     Exynos4210State *s = EXYNOS4210_SOC(obj);
 475     int i;
 476
 477     for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) {
 478         char *name = g_strdup_printf("pl330-irq-orgate%d", i);
 479         qemu_or_irq *orgate = &s->pl330_irq_orgate[i];
 480
 481         object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
 482         g_free(name);
 483     }
 484
 485     for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
 486         g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
 487         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
 488     }
 489
 490     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
 491 }
 492
 493 static void exynos4210_class_init(ObjectClass *klass, void *data)
 494 {
 495     DeviceClass *dc = DEVICE_CLASS(klass);
 496
 497     dc->realize = exynos4210_realize;
 498 }
 499
 500 static const TypeInfo exynos4210_info = {
 501     .name = TYPE_EXYNOS4210_SOC,
 502     .parent = TYPE_SYS_BUS_DEVICE,
 503     .instance_size = sizeof(Exynos4210State),
 504     .instance_init = exynos4210_init,
 505     .class_init = exynos4210_class_init,
 506 };
 507
 508 static void exynos4210_register_types(void)
 509 {
 510     type_register_static(&exynos4210_info);
 511 }
 512
 513 type_init(exynos4210_register_types)