include/hw/ppc/pnv.h

   1 /*
   2  * QEMU PowerPC PowerNV various definitions
   3  *
   4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_PNV_H
  21 #define PPC_PNV_H
  22
  23 #include "hw/boards.h"
  24 #include "hw/sysbus.h"
  25 #include "hw/ipmi/ipmi.h"
  26 #include "hw/ppc/pnv_lpc.h"
  27 #include "hw/ppc/pnv_pnor.h"
  28 #include "hw/ppc/pnv_psi.h"
  29 #include "hw/ppc/pnv_occ.h"
  30 #include "hw/ppc/pnv_homer.h"
  31 #include "hw/ppc/pnv_xive.h"
  32 #include "hw/ppc/pnv_core.h"
  33
  34 #define TYPE_PNV_CHIP "pnv-chip"
  35 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
  36 #define PNV_CHIP_CLASS(klass) \
  37      OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
  38 #define PNV_CHIP_GET_CLASS(obj) \
  39      OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
  40
  41 typedef enum PnvChipType {
  42     PNV_CHIP_POWER8E,     /* AKA Murano (default) */
  43     PNV_CHIP_POWER8,      /* AKA Venice */
  44     PNV_CHIP_POWER8NVL,   /* AKA Naples */
  45     PNV_CHIP_POWER9,      /* AKA Nimbus */
  46     PNV_CHIP_POWER10,     /* AKA TBD */
  47 } PnvChipType;
  48
  49 typedef struct PnvChip {
  50     /*< private >*/
  51     SysBusDevice parent_obj;
  52
  53     /*< public >*/
  54     uint32_t     chip_id;
  55     uint64_t     ram_start;
  56     uint64_t     ram_size;
  57
  58     uint32_t     nr_cores;
  59     uint64_t     cores_mask;
  60     PnvCore      **cores;
  61
  62     MemoryRegion xscom_mmio;
  63     MemoryRegion xscom;
  64     AddressSpace xscom_as;
  65
  66     gchar        *dt_isa_nodename;
  67 } PnvChip;
  68
  69 #define TYPE_PNV8_CHIP "pnv8-chip"
  70 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
  71
  72 typedef struct Pnv8Chip {
  73     /*< private >*/
  74     PnvChip      parent_obj;
  75
  76     /*< public >*/
  77     MemoryRegion icp_mmio;
  78
  79     PnvLpcController lpc;
  80     Pnv8Psi      psi;
  81     PnvOCC       occ;
  82     PnvHomer     homer;
  83 } Pnv8Chip;
  84
  85 #define TYPE_PNV9_CHIP "pnv9-chip"
  86 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
  87
  88 typedef struct Pnv9Chip {
  89     /*< private >*/
  90     PnvChip      parent_obj;
  91
  92     /*< public >*/
  93     PnvXive      xive;
  94     Pnv9Psi      psi;
  95     PnvLpcController lpc;
  96     PnvOCC       occ;
  97     PnvHomer     homer;
  98
  99     uint32_t     nr_quads;
 100     PnvQuad      *quads;
 101 } Pnv9Chip;
 102
 103 /*
 104  * A SMT8 fused core is a pair of SMT4 cores.
 105  */
 106 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
 107 #define PNV9_PIR2CHIP(pir)      (((pir) >> 8) & 0x7f)
 108
 109 #define TYPE_PNV10_CHIP "pnv10-chip"
 110 #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP)
 111
 112 typedef struct Pnv10Chip {
 113     /*< private >*/
 114     PnvChip      parent_obj;
 115
 116     /*< public >*/
 117     Pnv9Psi      psi;
 118     PnvLpcController lpc;
 119 } Pnv10Chip;
 120
 121 typedef struct PnvChipClass {
 122     /*< private >*/
 123     SysBusDeviceClass parent_class;
 124
 125     /*< public >*/
 126     PnvChipType  chip_type;
 127     uint64_t     chip_cfam_id;
 128     uint64_t     cores_mask;
 129
 130     DeviceRealize parent_realize;
 131
 132     uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
 133     void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
 134     void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
 135     void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
 136     void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
 137     ISABus *(*isa_create)(PnvChip *chip, Error **errp);
 138     void (*dt_populate)(PnvChip *chip, void *fdt);
 139     void (*pic_print_info)(PnvChip *chip, Monitor *mon);
 140     uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
 141 } PnvChipClass;
 142
 143 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
 144 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
 145
 146 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
 147 #define PNV_CHIP_POWER8E(obj) \
 148     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
 149
 150 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
 151 #define PNV_CHIP_POWER8(obj) \
 152     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
 153
 154 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
 155 #define PNV_CHIP_POWER8NVL(obj) \
 156     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
 157
 158 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
 159 #define PNV_CHIP_POWER9(obj) \
 160     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
 161
 162 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
 163 #define PNV_CHIP_POWER10(obj) \
 164     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10)
 165
 166 /*
 167  * This generates a HW chip id depending on an index, as found on a
 168  * two socket system with dual chip modules :
 169  *
 170  *    0x0, 0x1, 0x10, 0x11
 171  *
 172  * 4 chips should be the maximum
 173  *
 174  * TODO: use a machine property to define the chip ids
 175  */
 176 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
 177
 178 /*
 179  * Converts back a HW chip id to an index. This is useful to calculate
 180  * the MMIO addresses of some controllers which depend on the chip id.
 181  */
 182 #define PNV_CHIP_INDEX(chip)                                    \
 183     (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
 184
 185 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
 186
 187 #define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
 188 #define PNV_MACHINE(obj) \
 189     OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
 190 #define PNV_MACHINE_GET_CLASS(obj) \
 191     OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE)
 192 #define PNV_MACHINE_CLASS(klass) \
 193     OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE)
 194
 195 typedef struct PnvMachineState PnvMachineState;
 196
 197 typedef struct PnvMachineClass {
 198     /*< private >*/
 199     MachineClass parent_class;
 200
 201     /*< public >*/
 202     const char *compat;
 203     int compat_size;
 204
 205     void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
 206 } PnvMachineClass;
 207
 208 struct PnvMachineState {
 209     /*< private >*/
 210     MachineState parent_obj;
 211
 212     uint32_t     initrd_base;
 213     long         initrd_size;
 214
 215     uint32_t     num_chips;
 216     PnvChip      **chips;
 217
 218     ISABus       *isa_bus;
 219     uint32_t     cpld_irqstate;
 220
 221     IPMIBmc      *bmc;
 222     Notifier     powerdown_notifier;
 223
 224     PnvPnor      *pnor;
 225 };
 226
 227 static inline bool pnv_chip_is_power9(const PnvChip *chip)
 228 {
 229     return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9;
 230 }
 231
 232 PnvChip *pnv_get_chip(uint32_t chip_id);
 233
 234 #define PNV_FDT_ADDR          0x01000000
 235 #define PNV_TIMEBASE_FREQ     512000000ULL
 236
 237 static inline bool pnv_chip_is_power10(const PnvChip *chip)
 238 {
 239     return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10;
 240 }
 241
 242 /*
 243  * BMC helpers
 244  */
 245 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
 246 void pnv_bmc_powerdown(IPMIBmc *bmc);
 247 IPMIBmc *pnv_bmc_create(void);
 248
 249 /*
 250  * POWER8 MMIO base addresses
 251  */
 252 #define PNV_XSCOM_SIZE        0x800000000ull
 253 #define PNV_XSCOM_BASE(chip)                                            \
 254     (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
 255
 256 #define PNV_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
 257 #define PNV_OCC_COMMON_AREA_BASE    0x7fff800000ull
 258 #define PNV_OCC_SENSOR_BASE(chip)   (PNV_OCC_COMMON_AREA_BASE + \
 259     PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
 260
 261 #define PNV_HOMER_SIZE              0x0000000000400000ull
 262 #define PNV_HOMER_BASE(chip)                                            \
 263     (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
 264
 265
 266 /*
 267  * XSCOM 0x20109CA defines the ICP BAR:
 268  *
 269  * 0:29   : bits 14 to 43 of address to define 1 MB region.
 270  * 30     : 1 to enable ICP to receive loads/stores against its BAR region
 271  * 31:63  : Constant 0
 272  *
 273  * Usually defined as :
 274  *
 275  *      0xffffe00200000000 -> 0x0003ffff80000000
 276  *      0xffffe00600000000 -> 0x0003ffff80100000
 277  *      0xffffe02200000000 -> 0x0003ffff80800000
 278  *      0xffffe02600000000 -> 0x0003ffff80900000
 279  */
 280 #define PNV_ICP_SIZE         0x0000000000100000ull
 281 #define PNV_ICP_BASE(chip)                                              \
 282     (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
 283
 284
 285 #define PNV_PSIHB_SIZE       0x0000000000100000ull
 286 #define PNV_PSIHB_BASE(chip) \
 287     (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
 288
 289 #define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
 290 #define PNV_PSIHB_FSP_BASE(chip) \
 291     (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
 292      PNV_PSIHB_FSP_SIZE)
 293
 294 /*
 295  * POWER9 MMIO base addresses
 296  */
 297 #define PNV9_CHIP_BASE(chip, base)   \
 298     ((base) + ((uint64_t) (chip)->chip_id << 42))
 299
 300 #define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
 301 #define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
 302
 303 #define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
 304 #define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
 305
 306 #define PNV9_LPCM_SIZE               0x0000000100000000ull
 307 #define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
 308
 309 #define PNV9_PSIHB_SIZE              0x0000000000100000ull
 310 #define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
 311
 312 #define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
 313 #define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
 314
 315 #define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
 316 #define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
 317
 318 #define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
 319 #define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
 320
 321 #define PNV9_XSCOM_SIZE              0x0000000400000000ull
 322 #define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
 323
 324 #define PNV9_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
 325 #define PNV9_OCC_COMMON_AREA_BASE    0x203fff800000ull
 326 #define PNV9_OCC_SENSOR_BASE(chip)   (PNV9_OCC_COMMON_AREA_BASE +       \
 327     PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
 328
 329 #define PNV9_HOMER_SIZE              0x0000000000400000ull
 330 #define PNV9_HOMER_BASE(chip)                                           \
 331     (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
 332
 333 /*
 334  * POWER10 MMIO base addresses - 16TB stride per chip
 335  */
 336 #define PNV10_CHIP_BASE(chip, base)   \
 337     ((base) + ((uint64_t) (chip)->chip_id << 44))
 338
 339 #define PNV10_XSCOM_SIZE             0x0000000400000000ull
 340 #define PNV10_XSCOM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
 341
 342 #define PNV10_LPCM_SIZE             0x0000000100000000ull
 343 #define PNV10_LPCM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
 344
 345 #define PNV10_PSIHB_ESB_SIZE        0x0000000000100000ull
 346 #define PNV10_PSIHB_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
 347
 348 #define PNV10_PSIHB_SIZE            0x0000000000100000ull
 349 #define PNV10_PSIHB_BASE(chip)      PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
 350
 351 #endif /* PPC_PNV_H */