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hw/ppc/pegasos2: Fix a typo in a comment
[qemu/rayw.git] / hw / ppc / pegasos2.c
bloba9563f4fb2a4f3c6680ffce65b1619647998b7dc
1 /*
2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
3 *
4 * Copyright (c) 2018-2021 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/units.h"
12 #include "qapi/error.h"
13 #include "hw/hw.h"
14 #include "hw/ppc/ppc.h"
15 #include "hw/sysbus.h"
16 #include "hw/pci/pci_host.h"
17 #include "hw/irq.h"
18 #include "hw/pci-host/mv64361.h"
19 #include "hw/isa/vt82c686.h"
20 #include "hw/ide/pci.h"
21 #include "hw/i2c/smbus_eeprom.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/reset.h"
24 #include "sysemu/runstate.h"
25 #include "sysemu/qtest.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/fw-path-provider.h"
29 #include "elf.h"
30 #include "qemu/log.h"
31 #include "qemu/error-report.h"
32 #include "sysemu/kvm.h"
33 #include "kvm_ppc.h"
34 #include "exec/address-spaces.h"
35 #include "qom/qom-qobject.h"
36 #include "qapi/qmp/qdict.h"
37 #include "trace.h"
38 #include "qemu/datadir.h"
39 #include "sysemu/device_tree.h"
40 #include "hw/ppc/vof.h"
41
42 #include <libfdt.h>
43
44 #define PROM_FILENAME "vof.bin"
45 #define PROM_ADDR 0xfff00000
46 #define PROM_SIZE 0x80000
47
48 #define KVMPPC_HCALL_BASE 0xf000
49 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
50 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
51
52 #define H_SUCCESS 0
53 #define H_PRIVILEGE -3 /* Caller not privileged */
54 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
55
56 #define BUS_FREQ_HZ 133333333
57
58 #define PCI0_CFG_ADDR 0xcf8
59 #define PCI0_MEM_BASE 0xc0000000
60 #define PCI0_MEM_SIZE 0x20000000
61 #define PCI0_IO_BASE 0xf8000000
62 #define PCI0_IO_SIZE 0x10000
63
64 #define PCI1_CFG_ADDR 0xc78
65 #define PCI1_MEM_BASE 0x80000000
66 #define PCI1_MEM_SIZE 0x40000000
67 #define PCI1_IO_BASE 0xfe000000
68 #define PCI1_IO_SIZE 0x10000
69
70 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2")
71 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
72
73 struct Pegasos2MachineState {
74 MachineState parent_obj;
75 PowerPCCPU *cpu;
76 DeviceState *mv;
77 Vof *vof;
78 void *fdt_blob;
79 uint64_t kernel_addr;
80 uint64_t kernel_entry;
81 uint64_t kernel_size;
82 };
83
84 static void *build_fdt(MachineState *machine, int *fdt_size);
85
86 static void pegasos2_cpu_reset(void *opaque)
87 {
88 PowerPCCPU *cpu = opaque;
89 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine);
90
91 cpu_reset(CPU(cpu));
92 cpu->env.spr[SPR_HID1] = 7ULL << 28;
93 if (pm->vof) {
94 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
95 cpu->env.nip = 0x100;
96 }
97 }
98
99 static void pegasos2_init(MachineState *machine)
100 {
101 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
102 CPUPPCState *env;
103 MemoryRegion *rom = g_new(MemoryRegion, 1);
104 PCIBus *pci_bus;
105 Object *via;
106 PCIDevice *dev;
107 I2CBus *i2c_bus;
108 const char *fwname = machine->firmware ?: PROM_FILENAME;
109 char *filename;
110 int sz;
111 uint8_t *spd_data;
112
113 /* init CPU */
114 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
115 env = &pm->cpu->env;
116 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
117 error_report("Incompatible CPU, only 6xx bus supported");
118 exit(1);
119 }
120
121 /* Set time-base frequency */
122 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
123 qemu_register_reset(pegasos2_cpu_reset, pm->cpu);
124
125 /* RAM */
126 if (machine->ram_size > 2 * GiB) {
127 error_report("RAM size more than 2 GiB is not supported");
128 exit(1);
129 }
130 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
131
132 /* allocate and load firmware */
133 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
134 if (!filename) {
135 error_report("Could not find firmware '%s'", fwname);
136 exit(1);
137 }
138 if (!machine->firmware && !pm->vof) {
139 pm->vof = g_malloc0(sizeof(*pm->vof));
140 }
141 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
142 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
143 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1,
144 PPC_ELF_MACHINE, 0, 0);
145 if (sz <= 0) {
146 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE);
147 }
148 if (sz <= 0 || sz > PROM_SIZE) {
149 error_report("Could not load firmware '%s'", filename);
150 exit(1);
151 }
152 g_free(filename);
153 if (pm->vof) {
154 pm->vof->fw_size = sz;
155 }
156
157 /* Marvell Discovery II system controller */
158 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
159 qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
160 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
161
162 /* VIA VT8231 South Bridge (multifunction PCI device) */
163 via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0),
164 true, TYPE_VT8231_ISA));
165 object_property_add_alias(OBJECT(machine), "rtc-time",
166 object_resolve_path_component(via, "rtc"),
167 "date");
168 qdev_connect_gpio_out(DEVICE(via), 0,
169 qdev_get_gpio_in_named(pm->mv, "gpp", 31));
170
171 dev = PCI_DEVICE(object_resolve_path_component(via, "ide"));
172 pci_ide_create_devs(dev);
173
174 dev = PCI_DEVICE(object_resolve_path_component(via, "pm"));
175 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
176 spd_data = spd_data_generate(DDR, machine->ram_size);
177 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
178
179 /* other PC hardware */
180 pci_vga_init(pci_bus);
181
182 if (machine->kernel_filename) {
183 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
184 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,
185 PPC_ELF_MACHINE, 0, 0);
186 if (sz <= 0) {
187 error_report("Could not load kernel '%s'",
188 machine->kernel_filename);
189 exit(1);
190 }
191 pm->kernel_size = sz;
192 if (!pm->vof) {
193 warn_report("Option -kernel may be ineffective with -bios.");
194 }
195 } else if (pm->vof && !qtest_enabled()) {
196 warn_report("Using Virtual OpenFirmware but no -kernel option.");
197 }
198
199 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
200 warn_report("Option -append may be ineffective with -bios.");
201 }
202 }
203
204 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm,
205 uint32_t addr, uint32_t len)
206 {
207 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
208 uint64_t val = 0xffffffffULL;
209 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE,
210 MEMTXATTRS_UNSPECIFIED);
211 return val;
212 }
213
214 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr,
215 uint32_t len, uint32_t val)
216 {
217 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
218 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE,
219 MEMTXATTRS_UNSPECIFIED);
220 }
221
222 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus,
223 uint32_t addr, uint32_t len)
224 {
225 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
226 uint64_t val = 0xffffffffULL;
227
228 if (len <= 4) {
229 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
230 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len);
231 }
232 return val;
233 }
234
235 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus,
236 uint32_t addr, uint32_t len, uint32_t val)
237 {
238 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR;
239
240 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
241 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
242 }
243
244 static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason)
245 {
246 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
247 void *fdt;
248 uint64_t d[2];
249 int sz;
250
251 qemu_devices_reset(reason);
252 if (!pm->vof) {
253 return; /* Firmware should set up machine so nothing to do */
254 }
255
256 /* Otherwise, set up devices that board firmware would normally do */
257 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
258 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc);
259 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400);
260 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000);
261 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000);
262 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
263 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
264 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
265 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
266
267 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
268 PCI_INTERRUPT_LINE, 2, 0x9);
269 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
270 0x50, 1, 0x2);
271
272 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
273 PCI_INTERRUPT_LINE, 2, 0x109);
274 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
275 PCI_CLASS_PROG, 1, 0xf);
276 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
277 0x40, 1, 0xb);
278 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
279 0x50, 4, 0x17171717);
280 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
281 PCI_COMMAND, 2, 0x87);
282
283 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
284 PCI_INTERRUPT_LINE, 2, 0x409);
285
286 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
287 PCI_INTERRUPT_LINE, 2, 0x409);
288
289 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
290 PCI_INTERRUPT_LINE, 2, 0x9);
291 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
292 0x48, 4, 0xf00);
293 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
294 0x40, 4, 0x558020);
295 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
296 0x90, 4, 0xd00);
297
298 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) |
299 PCI_INTERRUPT_LINE, 2, 0x309);
300
301 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) |
302 PCI_INTERRUPT_LINE, 2, 0x309);
303
304 /* Device tree and VOF set up */
305 vof_init(pm->vof, machine->ram_size, &error_fatal);
306 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
307 error_report("Memory allocation for stack failed");
308 exit(1);
309 }
310 if (pm->kernel_size &&
311 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
312 error_report("Memory for kernel is in use");
313 exit(1);
314 }
315 fdt = build_fdt(machine, &sz);
316 /* FIXME: VOF assumes entry is same as load address */
317 d[0] = cpu_to_be64(pm->kernel_entry);
318 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
319 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
320
321 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
322 g_free(pm->fdt_blob);
323 pm->fdt_blob = fdt;
324
325 vof_build_dt(fdt, pm->vof);
326 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
327
328 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
329 machine->fdt = fdt;
330
331 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
332 }
333
334 enum pegasos2_rtas_tokens {
335 RTAS_RESTART_RTAS = 0,
336 RTAS_NVRAM_FETCH = 1,
337 RTAS_NVRAM_STORE = 2,
338 RTAS_GET_TIME_OF_DAY = 3,
339 RTAS_SET_TIME_OF_DAY = 4,
340 RTAS_EVENT_SCAN = 6,
341 RTAS_CHECK_EXCEPTION = 7,
342 RTAS_READ_PCI_CONFIG = 8,
343 RTAS_WRITE_PCI_CONFIG = 9,
344 RTAS_DISPLAY_CHARACTER = 10,
345 RTAS_SET_INDICATOR = 11,
346 RTAS_POWER_OFF = 17,
347 RTAS_SUSPEND = 18,
348 RTAS_HIBERNATE = 19,
349 RTAS_SYSTEM_REBOOT = 20,
350 };
351
352 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm,
353 target_ulong args_real)
354 {
355 AddressSpace *as = CPU(cpu)->as;
356 uint32_t token = ldl_be_phys(as, args_real);
357 uint32_t nargs = ldl_be_phys(as, args_real + 4);
358 uint32_t nrets = ldl_be_phys(as, args_real + 8);
359 uint32_t args = args_real + 12;
360 uint32_t rets = args_real + 12 + nargs * 4;
361
362 if (nrets < 1) {
363 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n");
364 return H_PARAMETER;
365 }
366 switch (token) {
367 case RTAS_GET_TIME_OF_DAY:
368 {
369 QObject *qo = object_property_get_qobject(qdev_get_machine(),
370 "rtc-time", &error_fatal);
371 QDict *qd = qobject_to(QDict, qo);
372
373 if (nargs != 0 || nrets != 8 || !qd) {
374 stl_be_phys(as, rets, -1);
375 qobject_unref(qo);
376 return H_PARAMETER;
377 }
378
379 stl_be_phys(as, rets, 0);
380 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
381 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
382 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
383 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
384 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
385 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
386 stl_be_phys(as, rets + 28, 0);
387 qobject_unref(qo);
388 return H_SUCCESS;
389 }
390 case RTAS_READ_PCI_CONFIG:
391 {
392 uint32_t addr, len, val;
393
394 if (nargs != 2 || nrets != 2) {
395 stl_be_phys(as, rets, -1);
396 return H_PARAMETER;
397 }
398 addr = ldl_be_phys(as, args);
399 len = ldl_be_phys(as, args + 4);
400 val = pegasos2_pci_config_read(pm, !(addr >> 24),
401 addr & 0x0fffffff, len);
402 stl_be_phys(as, rets, 0);
403 stl_be_phys(as, rets + 4, val);
404 return H_SUCCESS;
405 }
406 case RTAS_WRITE_PCI_CONFIG:
407 {
408 uint32_t addr, len, val;
409
410 if (nargs != 3 || nrets != 1) {
411 stl_be_phys(as, rets, -1);
412 return H_PARAMETER;
413 }
414 addr = ldl_be_phys(as, args);
415 len = ldl_be_phys(as, args + 4);
416 val = ldl_be_phys(as, args + 8);
417 pegasos2_pci_config_write(pm, !(addr >> 24),
418 addr & 0x0fffffff, len, val);
419 stl_be_phys(as, rets, 0);
420 return H_SUCCESS;
421 }
422 case RTAS_DISPLAY_CHARACTER:
423 if (nargs != 1 || nrets != 1) {
424 stl_be_phys(as, rets, -1);
425 return H_PARAMETER;
426 }
427 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
428 stl_be_phys(as, rets, 0);
429 return H_SUCCESS;
430 case RTAS_POWER_OFF:
431 {
432 if (nargs != 2 || nrets != 1) {
433 stl_be_phys(as, rets, -1);
434 return H_PARAMETER;
435 }
436 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
437 stl_be_phys(as, rets, 0);
438 return H_SUCCESS;
439 }
440 default:
441 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
442 token, nargs, nrets);
443 stl_be_phys(as, rets, 0);
444 return H_SUCCESS;
445 }
446 }
447
448 static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu)
449 {
450 return false;
451 }
452
453 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
454 {
455 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
456 CPUPPCState *env = &cpu->env;
457
458 /* The TCG path should also be holding the BQL at this point */
459 g_assert(qemu_mutex_iothread_locked());
460
461 if (FIELD_EX64(env->msr, MSR, PR)) {
462 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
463 env->gpr[3] = H_PRIVILEGE;
464 } else if (env->gpr[3] == KVMPPC_H_RTAS) {
465 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]);
466 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
467 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob,
468 env->gpr[4]);
469 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
470 } else {
471 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
472 "\n", env->gpr[3]);
473 env->gpr[3] = -1;
474 }
475 }
476
477 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
478 {
479 }
480
481 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
482 {
483 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
484 }
485
486 static bool pegasos2_setprop(MachineState *ms, const char *path,
487 const char *propname, void *val, int vallen)
488 {
489 return true;
490 }
491
492 static void pegasos2_machine_class_init(ObjectClass *oc, void *data)
493 {
494 MachineClass *mc = MACHINE_CLASS(oc);
495 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
496 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc);
497
498 mc->desc = "Genesi/bPlan Pegasos II";
499 mc->init = pegasos2_init;
500 mc->reset = pegasos2_machine_reset;
501 mc->block_default_type = IF_IDE;
502 mc->default_boot_order = "cd";
503 mc->default_display = "std";
504 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
505 mc->default_ram_id = "pegasos2.ram";
506 mc->default_ram_size = 512 * MiB;
507
508 vhc->cpu_in_nested = pegasos2_cpu_in_nested;
509 vhc->hypercall = pegasos2_hypercall;
510 vhc->cpu_exec_enter = vhyp_nop;
511 vhc->cpu_exec_exit = vhyp_nop;
512 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
513
514 vmc->setprop = pegasos2_setprop;
515 }
516
517 static const TypeInfo pegasos2_machine_info = {
518 .name = TYPE_PEGASOS2_MACHINE,
519 .parent = TYPE_MACHINE,
520 .class_init = pegasos2_machine_class_init,
521 .instance_size = sizeof(Pegasos2MachineState),
522 .interfaces = (InterfaceInfo[]) {
523 { TYPE_PPC_VIRTUAL_HYPERVISOR },
524 { TYPE_VOF_MACHINE_IF },
525 { }
526 },
527 };
528
529 static void pegasos2_machine_register_types(void)
530 {
531 type_register_static(&pegasos2_machine_info);
532 }
533
534 type_init(pegasos2_machine_register_types)
535
536 /* FDT creation for passing to firmware */
537
538 typedef struct {
539 void *fdt;
540 const char *path;
541 } FDTInfo;
542
543 /* We do everything in reverse order so it comes out right in the tree */
544
545 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
546 {
547 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
548 }
549
550 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
551 {
552 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
553 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
554 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
555 }
556
557 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
558 {
559 GString *name = g_string_sized_new(64);
560 uint32_t cells[3];
561
562 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1);
563 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2);
564 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
565 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
566
567 /* additional devices */
568 g_string_printf(name, "%s/lpt@i3bc", fi->path);
569 qemu_fdt_add_subnode(fi->fdt, name->str);
570 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
571 cells[0] = cpu_to_be32(7);
572 cells[1] = 0;
573 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
574 cells, 2 * sizeof(cells[0]));
575 cells[0] = cpu_to_be32(1);
576 cells[1] = cpu_to_be32(0x3bc);
577 cells[2] = cpu_to_be32(8);
578 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
579 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt");
580 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt");
581
582 g_string_printf(name, "%s/fdc@i3f0", fi->path);
583 qemu_fdt_add_subnode(fi->fdt, name->str);
584 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
585 cells[0] = cpu_to_be32(6);
586 cells[1] = 0;
587 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
588 cells, 2 * sizeof(cells[0]));
589 cells[0] = cpu_to_be32(1);
590 cells[1] = cpu_to_be32(0x3f0);
591 cells[2] = cpu_to_be32(8);
592 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
593 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc");
594 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc");
595
596 g_string_printf(name, "%s/timer@i40", fi->path);
597 qemu_fdt_add_subnode(fi->fdt, name->str);
598 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
599 cells[0] = cpu_to_be32(1);
600 cells[1] = cpu_to_be32(0x40);
601 cells[2] = cpu_to_be32(8);
602 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
603 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer");
604 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer");
605
606 g_string_printf(name, "%s/rtc@i70", fi->path);
607 qemu_fdt_add_subnode(fi->fdt, name->str);
608 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc");
609 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
610 cells[0] = cpu_to_be32(8);
611 cells[1] = 0;
612 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
613 cells, 2 * sizeof(cells[0]));
614 cells[0] = cpu_to_be32(1);
615 cells[1] = cpu_to_be32(0x70);
616 cells[2] = cpu_to_be32(2);
617 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
618 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc");
619 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc");
620
621 g_string_printf(name, "%s/keyboard@i60", fi->path);
622 qemu_fdt_add_subnode(fi->fdt, name->str);
623 cells[0] = cpu_to_be32(1);
624 cells[1] = 0;
625 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
626 cells, 2 * sizeof(cells[0]));
627 cells[0] = cpu_to_be32(1);
628 cells[1] = cpu_to_be32(0x60);
629 cells[2] = cpu_to_be32(5);
630 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
631 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard");
632 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard");
633
634 g_string_printf(name, "%s/8042@i60", fi->path);
635 qemu_fdt_add_subnode(fi->fdt, name->str);
636 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2);
637 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0);
638 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1);
639 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", "");
640 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
641 cells[0] = cpu_to_be32(1);
642 cells[1] = cpu_to_be32(0x60);
643 cells[2] = cpu_to_be32(5);
644 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
645 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "");
646 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042");
647
648 g_string_printf(name, "%s/serial@i2f8", fi->path);
649 qemu_fdt_add_subnode(fi->fdt, name->str);
650 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
651 cells[0] = cpu_to_be32(3);
652 cells[1] = 0;
653 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
654 cells, 2 * sizeof(cells[0]));
655 cells[0] = cpu_to_be32(1);
656 cells[1] = cpu_to_be32(0x2f8);
657 cells[2] = cpu_to_be32(8);
658 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
659 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial");
660 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial");
661
662 g_string_free(name, TRUE);
663 }
664
665 static struct {
666 const char *id;
667 const char *name;
668 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
669 } device_map[] = {
670 { "pci11ab,6460", "host", NULL },
671 { "pci1106,8231", "isa", dt_isa },
672 { "pci1106,571", "ide", dt_ide },
673 { "pci1106,3044", "firewire", NULL },
674 { "pci1106,3038", "usb", dt_usb },
675 { "pci1106,8235", "other", NULL },
676 { "pci1106,3058", "sound", NULL },
677 { NULL, NULL }
678 };
679
680 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
681 {
682 FDTInfo *fi = opaque;
683 GString *node = g_string_new(NULL);
684 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
685 int i, j;
686 const char *name = NULL;
687 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
688 pci_get_word(&d->config[PCI_VENDOR_ID]),
689 pci_get_word(&d->config[PCI_DEVICE_ID]));
690
691 for (i = 0; device_map[i].id; i++) {
692 if (!strcmp(pn, device_map[i].id)) {
693 name = device_map[i].name;
694 break;
695 }
696 }
697 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
698 PCI_SLOT(d->devfn));
699 if (PCI_FUNC(d->devfn)) {
700 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
701 }
702
703 qemu_fdt_add_subnode(fi->fdt, node->str);
704 if (device_map[i].dtf) {
705 FDTInfo cfi = { fi->fdt, node->str };
706 device_map[i].dtf(bus, d, &cfi);
707 }
708 cells[0] = cpu_to_be32(d->devfn << 8);
709 cells[1] = 0;
710 cells[2] = 0;
711 cells[3] = 0;
712 cells[4] = 0;
713 j = 5;
714 for (i = 0; i < PCI_NUM_REGIONS; i++) {
715 if (!d->io_regions[i].size) {
716 continue;
717 }
718 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
719 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
720 cells[j] |= cpu_to_be32(1 << 24);
721 } else {
722 cells[j] |= cpu_to_be32(2 << 24);
723 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
724 cells[j] |= cpu_to_be32(4 << 28);
725 }
726 }
727 cells[j + 1] = 0;
728 cells[j + 2] = 0;
729 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
730 cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
731 j += 5;
732 }
733 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
734 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn);
735 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
736 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
737 pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
738 }
739 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
740 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
741 pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
742 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
743 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
744 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
745 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
746 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
747 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
748 pci_get_word(&d->config[PCI_DEVICE_ID]));
749 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
750 pci_get_word(&d->config[PCI_VENDOR_ID]));
751
752 g_string_free(node, TRUE);
753 }
754
755 static void *build_fdt(MachineState *machine, int *fdt_size)
756 {
757 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
758 PowerPCCPU *cpu = pm->cpu;
759 PCIBus *pci_bus;
760 FDTInfo fi;
761 uint32_t cells[16];
762 void *fdt = create_device_tree(fdt_size);
763
764 fi.fdt = fdt;
765
766 /* root node */
767 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description",
768 "Pegasos CHRP PowerPC System");
769 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2");
770 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH");
771 qemu_fdt_setprop_string(fdt, "/", "revision", "2B");
772 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2");
773 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp");
774 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1);
775 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
776
777 /* pci@c0000000 */
778 qemu_fdt_add_subnode(fdt, "/pci@c0000000");
779 cells[0] = 0;
780 cells[1] = 0;
781 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range",
782 cells, 2 * sizeof(cells[0]));
783 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1);
784 cells[0] = cpu_to_be32(PCI0_MEM_BASE);
785 cells[1] = cpu_to_be32(PCI0_MEM_SIZE);
786 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0]));
787 cells[0] = cpu_to_be32(0x01000000);
788 cells[1] = 0;
789 cells[2] = 0;
790 cells[3] = cpu_to_be32(PCI0_IO_BASE);
791 cells[4] = 0;
792 cells[5] = cpu_to_be32(PCI0_IO_SIZE);
793 cells[6] = cpu_to_be32(0x02000000);
794 cells[7] = 0;
795 cells[8] = cpu_to_be32(PCI0_MEM_BASE);
796 cells[9] = cpu_to_be32(PCI0_MEM_BASE);
797 cells[10] = 0;
798 cells[11] = cpu_to_be32(PCI0_MEM_SIZE);
799 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges",
800 cells, 12 * sizeof(cells[0]));
801 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2);
802 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3);
803 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci");
804 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci");
805
806 fi.path = "/pci@c0000000";
807 pci_bus = mv64361_get_pci_bus(pm->mv, 0);
808 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
809
810 /* pci@80000000 */
811 qemu_fdt_add_subnode(fdt, "/pci@80000000");
812 cells[0] = 0;
813 cells[1] = 0;
814 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range",
815 cells, 2 * sizeof(cells[0]));
816 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0);
817 cells[0] = cpu_to_be32(PCI1_MEM_BASE);
818 cells[1] = cpu_to_be32(PCI1_MEM_SIZE);
819 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0]));
820 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge",
821 0xf1000cb4);
822 cells[0] = cpu_to_be32(0x01000000);
823 cells[1] = 0;
824 cells[2] = 0;
825 cells[3] = cpu_to_be32(PCI1_IO_BASE);
826 cells[4] = 0;
827 cells[5] = cpu_to_be32(PCI1_IO_SIZE);
828 cells[6] = cpu_to_be32(0x02000000);
829 cells[7] = 0;
830 cells[8] = cpu_to_be32(PCI1_MEM_BASE);
831 cells[9] = cpu_to_be32(PCI1_MEM_BASE);
832 cells[10] = 0;
833 cells[11] = cpu_to_be32(PCI1_MEM_SIZE);
834 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges",
835 cells, 12 * sizeof(cells[0]));
836 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2);
837 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3);
838 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci");
839 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci");
840
841 fi.path = "/pci@80000000";
842 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
843 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
844
845 qemu_fdt_add_subnode(fdt, "/failsafe");
846 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial");
847 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe");
848
849 qemu_fdt_add_subnode(fdt, "/rtas");
850 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT);
851 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE);
852 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND);
853 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF);
854 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR);
855 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character",
856 RTAS_DISPLAY_CHARACTER);
857 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config",
858 RTAS_WRITE_PCI_CONFIG);
859 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config",
860 RTAS_READ_PCI_CONFIG);
861 /* Pegasos2 firmware misspells check-exception and guests use that */
862 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption",
863 RTAS_CHECK_EXCEPTION);
864 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN);
865 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day",
866 RTAS_SET_TIME_OF_DAY);
867 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day",
868 RTAS_GET_TIME_OF_DAY);
869 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE);
870 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH);
871 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS);
872 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0);
873 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0);
874 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0);
875 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20);
876 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1);
877
878 /* cpus */
879 qemu_fdt_add_subnode(fdt, "/cpus");
880 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1);
881 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
882 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
883 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus");
884
885 /* FIXME Get CPU name from CPU object */
886 const char *cp = "/cpus/PowerPC,G4";
887 qemu_fdt_add_subnode(fdt, cp);
888 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
889 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
890 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
891 cpu->env.dcache_line_size);
892 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
893 cpu->env.dcache_line_size);
894 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
895 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
896 cpu->env.icache_line_size);
897 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
898 cpu->env.icache_line_size);
899 if (cpu->env.id_tlbs) {
900 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
901 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
902 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
903 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
904 qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
905 }
906 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
907 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
908 qemu_fdt_setprop_string(fdt, cp, "state", "running");
909 if (cpu->env.insns_flags & PPC_ALTIVEC) {
910 qemu_fdt_setprop_string(fdt, cp, "altivec", "");
911 qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
912 }
913 /*
914 * FIXME What flags do data-streams, external-control and
915 * performance-monitor depend on?
916 */
917 qemu_fdt_setprop_string(fdt, cp, "external-control", "");
918 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
919 qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
920 }
921 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
922 if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
923 qemu_fdt_setprop_string(fdt, cp, "graphics", "");
924 }
925 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
926 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
927 cpu->env.tb_env->tb_freq);
928 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ);
929 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5);
930 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
931 cells[0] = 0;
932 cells[1] = 0;
933 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
934 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
935 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1);
936
937 /* memory */
938 qemu_fdt_add_subnode(fdt, "/memory@0");
939 cells[0] = 0;
940 cells[1] = cpu_to_be32(machine->ram_size);
941 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0]));
942 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory");
943 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
944
945 qemu_fdt_add_subnode(fdt, "/chosen");
946 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
947 machine->kernel_cmdline ?: "");
948 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
949
950 qemu_fdt_add_subnode(fdt, "/openprom");
951 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1");
952
953 return fdt;
954 }
Ray Wang's QEMU Repository