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ppc/pegasos2: Access MV64361 registers via their memory region
[qemu/rayw.git] / hw / ppc / pegasos2.c
bloba861bf16b8f072878a74bd508ab54e0b999fc18c
1 /*
2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
3 *
4 * Copyright (c) 2018-2021 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu-common.h"
12 #include "qemu/units.h"
13 #include "qapi/error.h"
14 #include "hw/hw.h"
15 #include "hw/ppc/ppc.h"
16 #include "hw/sysbus.h"
17 #include "hw/pci/pci_host.h"
18 #include "hw/irq.h"
19 #include "hw/pci-host/mv64361.h"
20 #include "hw/isa/vt82c686.h"
21 #include "hw/ide/pci.h"
22 #include "hw/i2c/smbus_eeprom.h"
23 #include "hw/qdev-properties.h"
24 #include "sysemu/reset.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/fw-path-provider.h"
28 #include "elf.h"
29 #include "qemu/log.h"
30 #include "qemu/error-report.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33 #include "exec/address-spaces.h"
34 #include "qom/qom-qobject.h"
35 #include "qapi/qmp/qdict.h"
36 #include "trace.h"
37 #include "qemu/datadir.h"
38 #include "sysemu/device_tree.h"
39 #include "hw/ppc/vof.h"
40
41 #include <libfdt.h>
42
43 #define PROM_FILENAME "vof.bin"
44 #define PROM_ADDR 0xfff00000
45 #define PROM_SIZE 0x80000
46
47 #define KVMPPC_HCALL_BASE 0xf000
48 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
49 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
50
51 #define H_SUCCESS 0
52 #define H_PRIVILEGE -3 /* Caller not privileged */
53 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
54
55 #define BUS_FREQ_HZ 133333333
56
57 #define PCI0_MEM_BASE 0xc0000000
58 #define PCI0_MEM_SIZE 0x20000000
59 #define PCI0_IO_BASE 0xf8000000
60 #define PCI0_IO_SIZE 0x10000
61
62 #define PCI1_MEM_BASE 0x80000000
63 #define PCI1_MEM_SIZE 0x40000000
64 #define PCI1_IO_BASE 0xfe000000
65 #define PCI1_IO_SIZE 0x10000
66
67 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2")
68 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE)
69
70 struct Pegasos2MachineState {
71 MachineState parent_obj;
72 PowerPCCPU *cpu;
73 DeviceState *mv;
74 Vof *vof;
75 void *fdt_blob;
76 uint64_t kernel_addr;
77 uint64_t kernel_entry;
78 uint64_t kernel_size;
79 };
80
81 static void *build_fdt(MachineState *machine, int *fdt_size);
82
83 static void pegasos2_cpu_reset(void *opaque)
84 {
85 PowerPCCPU *cpu = opaque;
86 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine);
87
88 cpu_reset(CPU(cpu));
89 cpu->env.spr[SPR_HID1] = 7ULL << 28;
90 if (pm->vof) {
91 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20;
92 cpu->env.nip = 0x100;
93 }
94 }
95
96 static void pegasos2_init(MachineState *machine)
97 {
98 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
99 CPUPPCState *env;
100 MemoryRegion *rom = g_new(MemoryRegion, 1);
101 PCIBus *pci_bus;
102 PCIDevice *dev;
103 I2CBus *i2c_bus;
104 const char *fwname = machine->firmware ?: PROM_FILENAME;
105 char *filename;
106 int sz;
107 uint8_t *spd_data;
108
109 /* init CPU */
110 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
111 env = &pm->cpu->env;
112 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
113 error_report("Incompatible CPU, only 6xx bus supported");
114 exit(1);
115 }
116
117 /* Set time-base frequency */
118 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
119 qemu_register_reset(pegasos2_cpu_reset, pm->cpu);
120
121 /* RAM */
122 if (machine->ram_size > 2 * GiB) {
123 error_report("RAM size more than 2 GiB is not supported");
124 exit(1);
125 }
126 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
127
128 /* allocate and load firmware */
129 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
130 if (!filename) {
131 error_report("Could not find firmware '%s'", fwname);
132 exit(1);
133 }
134 if (!machine->firmware && !pm->vof) {
135 pm->vof = g_malloc0(sizeof(*pm->vof));
136 }
137 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
138 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
139 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1,
140 PPC_ELF_MACHINE, 0, 0);
141 if (sz <= 0) {
142 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE);
143 }
144 if (sz <= 0 || sz > PROM_SIZE) {
145 error_report("Could not load firmware '%s'", filename);
146 exit(1);
147 }
148 g_free(filename);
149 if (pm->vof) {
150 pm->vof->fw_size = sz;
151 }
152
153 /* Marvell Discovery II system controller */
154 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
155 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]));
156 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
157
158 /* VIA VT8231 South Bridge (multifunction PCI device) */
159 /* VT8231 function 0: PCI-to-ISA Bridge */
160 dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
161 TYPE_VT8231_ISA);
162 qdev_connect_gpio_out(DEVICE(dev), 0,
163 qdev_get_gpio_in_named(pm->mv, "gpp", 31));
164
165 /* VT8231 function 1: IDE Controller */
166 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide");
167 pci_ide_create_devs(dev);
168
169 /* VT8231 function 2-3: USB Ports */
170 pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci");
171 pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci");
172
173 /* VT8231 function 4: Power Management Controller */
174 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM);
175 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
176 spd_data = spd_data_generate(DDR, machine->ram_size);
177 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
178
179 /* VT8231 function 5-6: AC97 Audio & Modem */
180 pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97);
181 pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97);
182
183 /* other PC hardware */
184 pci_vga_init(pci_bus);
185
186 if (machine->kernel_filename) {
187 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
188 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,
189 PPC_ELF_MACHINE, 0, 0);
190 if (sz <= 0) {
191 error_report("Could not load kernel '%s'",
192 machine->kernel_filename);
193 exit(1);
194 }
195 pm->kernel_size = sz;
196 if (!pm->vof) {
197 warn_report("Option -kernel may be ineffective with -bios.");
198 }
199 } else if (pm->vof) {
200 warn_report("Using Virtual OpenFirmware but no -kernel option.");
201 }
202
203 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
204 warn_report("Option -append may be ineffective with -bios.");
205 }
206 }
207
208 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm,
209 uint32_t addr, uint32_t len)
210 {
211 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
212 uint64_t val = 0xffffffffULL;
213 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE,
214 MEMTXATTRS_UNSPECIFIED);
215 return val;
216 }
217
218 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr,
219 uint32_t len, uint32_t val)
220 {
221 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0);
222 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE,
223 MEMTXATTRS_UNSPECIFIED);
224 }
225
226 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus,
227 uint32_t addr, uint32_t len)
228 {
229 hwaddr pcicfg = bus ? 0xc78 : 0xcf8;
230 uint64_t val = 0xffffffffULL;
231
232 if (len <= 4) {
233 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
234 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len);
235 }
236 return val;
237 }
238
239 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus,
240 uint32_t addr, uint32_t len, uint32_t val)
241 {
242 hwaddr pcicfg = bus ? 0xc78 : 0xcf8;
243
244 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31));
245 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val);
246 }
247
248 static void pegasos2_machine_reset(MachineState *machine)
249 {
250 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
251 void *fdt;
252 uint64_t d[2];
253 int sz;
254
255 qemu_devices_reset();
256 if (!pm->vof) {
257 return; /* Firmware should set up machine so nothing to do */
258 }
259
260 /* Otherwise, set up devices that board firmware would normally do */
261 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff);
262 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc);
263 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400);
264 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000);
265 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000);
266 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO |
267 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
268 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO |
269 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
270
271 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
272 PCI_INTERRUPT_LINE, 2, 0x9);
273 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |
274 0x50, 1, 0x2);
275
276 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
277 PCI_INTERRUPT_LINE, 2, 0x109);
278 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
279 PCI_CLASS_PROG, 1, 0xf);
280 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
281 0x40, 1, 0xb);
282 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
283 0x50, 4, 0x17171717);
284 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) |
285 PCI_COMMAND, 2, 0x87);
286
287 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
288 PCI_INTERRUPT_LINE, 2, 0x409);
289
290 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
291 PCI_INTERRUPT_LINE, 2, 0x409);
292
293 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
294 PCI_INTERRUPT_LINE, 2, 0x9);
295 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
296 0x48, 4, 0xf00);
297 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
298 0x40, 4, 0x558020);
299 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
300 0x90, 4, 0xd00);
301
302 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) |
303 PCI_INTERRUPT_LINE, 2, 0x309);
304
305 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) |
306 PCI_INTERRUPT_LINE, 2, 0x309);
307
308 /* Device tree and VOF set up */
309 vof_init(pm->vof, machine->ram_size, &error_fatal);
310 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) {
311 error_report("Memory allocation for stack failed");
312 exit(1);
313 }
314 if (pm->kernel_size &&
315 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) {
316 error_report("Memory for kernel is in use");
317 exit(1);
318 }
319 fdt = build_fdt(machine, &sz);
320 /* FIXME: VOF assumes entry is same as load address */
321 d[0] = cpu_to_be64(pm->kernel_entry);
322 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr));
323 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d));
324
325 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
326 g_free(pm->fdt_blob);
327 pm->fdt_blob = fdt;
328
329 vof_build_dt(fdt, pm->vof);
330 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe");
331 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine);
332 }
333
334 enum pegasos2_rtas_tokens {
335 RTAS_RESTART_RTAS = 0,
336 RTAS_NVRAM_FETCH = 1,
337 RTAS_NVRAM_STORE = 2,
338 RTAS_GET_TIME_OF_DAY = 3,
339 RTAS_SET_TIME_OF_DAY = 4,
340 RTAS_EVENT_SCAN = 6,
341 RTAS_CHECK_EXCEPTION = 7,
342 RTAS_READ_PCI_CONFIG = 8,
343 RTAS_WRITE_PCI_CONFIG = 9,
344 RTAS_DISPLAY_CHARACTER = 10,
345 RTAS_SET_INDICATOR = 11,
346 RTAS_POWER_OFF = 17,
347 RTAS_SUSPEND = 18,
348 RTAS_HIBERNATE = 19,
349 RTAS_SYSTEM_REBOOT = 20,
350 };
351
352 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm,
353 target_ulong args_real)
354 {
355 AddressSpace *as = CPU(cpu)->as;
356 uint32_t token = ldl_be_phys(as, args_real);
357 uint32_t nargs = ldl_be_phys(as, args_real + 4);
358 uint32_t nrets = ldl_be_phys(as, args_real + 8);
359 uint32_t args = args_real + 12;
360 uint32_t rets = args_real + 12 + nargs * 4;
361
362 if (nrets < 1) {
363 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n");
364 return H_PARAMETER;
365 }
366 switch (token) {
367 case RTAS_GET_TIME_OF_DAY:
368 {
369 QObject *qo = object_property_get_qobject(qdev_get_machine(),
370 "rtc-time", &error_fatal);
371 QDict *qd = qobject_to(QDict, qo);
372
373 if (nargs != 0 || nrets != 8 || !qd) {
374 stl_be_phys(as, rets, -1);
375 qobject_unref(qo);
376 return H_PARAMETER;
377 }
378
379 stl_be_phys(as, rets, 0);
380 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900);
381 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1);
382 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday"));
383 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour"));
384 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min"));
385 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec"));
386 stl_be_phys(as, rets + 28, 0);
387 qobject_unref(qo);
388 return H_SUCCESS;
389 }
390 case RTAS_READ_PCI_CONFIG:
391 {
392 uint32_t addr, len, val;
393
394 if (nargs != 2 || nrets != 2) {
395 stl_be_phys(as, rets, -1);
396 return H_PARAMETER;
397 }
398 addr = ldl_be_phys(as, args);
399 len = ldl_be_phys(as, args + 4);
400 val = pegasos2_pci_config_read(pm, !(addr >> 24),
401 addr & 0x0fffffff, len);
402 stl_be_phys(as, rets, 0);
403 stl_be_phys(as, rets + 4, val);
404 return H_SUCCESS;
405 }
406 case RTAS_WRITE_PCI_CONFIG:
407 {
408 uint32_t addr, len, val;
409
410 if (nargs != 3 || nrets != 1) {
411 stl_be_phys(as, rets, -1);
412 return H_PARAMETER;
413 }
414 addr = ldl_be_phys(as, args);
415 len = ldl_be_phys(as, args + 4);
416 val = ldl_be_phys(as, args + 8);
417 pegasos2_pci_config_write(pm, !(addr >> 24),
418 addr & 0x0fffffff, len, val);
419 stl_be_phys(as, rets, 0);
420 return H_SUCCESS;
421 }
422 case RTAS_DISPLAY_CHARACTER:
423 if (nargs != 1 || nrets != 1) {
424 stl_be_phys(as, rets, -1);
425 return H_PARAMETER;
426 }
427 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args));
428 stl_be_phys(as, rets, 0);
429 return H_SUCCESS;
430 default:
431 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n",
432 token, nargs, nrets);
433 stl_be_phys(as, rets, 0);
434 return H_SUCCESS;
435 }
436 }
437
438 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
439 {
440 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
441 CPUPPCState *env = &cpu->env;
442
443 /* The TCG path should also be holding the BQL at this point */
444 g_assert(qemu_mutex_iothread_locked());
445
446 if (msr_pr) {
447 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
448 env->gpr[3] = H_PRIVILEGE;
449 } else if (env->gpr[3] == KVMPPC_H_RTAS) {
450 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]);
451 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) {
452 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob,
453 env->gpr[4]);
454 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS);
455 } else {
456 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx
457 "\n", env->gpr[3]);
458 env->gpr[3] = -1;
459 }
460 }
461
462 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
463 {
464 }
465
466 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
467 {
468 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1];
469 }
470
471 static bool pegasos2_setprop(MachineState *ms, const char *path,
472 const char *propname, void *val, int vallen)
473 {
474 return true;
475 }
476
477 static void pegasos2_machine_class_init(ObjectClass *oc, void *data)
478 {
479 MachineClass *mc = MACHINE_CLASS(oc);
480 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
481 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc);
482
483 mc->desc = "Genesi/bPlan Pegasos II";
484 mc->init = pegasos2_init;
485 mc->reset = pegasos2_machine_reset;
486 mc->block_default_type = IF_IDE;
487 mc->default_boot_order = "cd";
488 mc->default_display = "std";
489 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
490 mc->default_ram_id = "pegasos2.ram";
491 mc->default_ram_size = 512 * MiB;
492
493 vhc->hypercall = pegasos2_hypercall;
494 vhc->cpu_exec_enter = vhyp_nop;
495 vhc->cpu_exec_exit = vhyp_nop;
496 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr;
497
498 vmc->setprop = pegasos2_setprop;
499 }
500
501 static const TypeInfo pegasos2_machine_info = {
502 .name = TYPE_PEGASOS2_MACHINE,
503 .parent = TYPE_MACHINE,
504 .class_init = pegasos2_machine_class_init,
505 .instance_size = sizeof(Pegasos2MachineState),
506 .interfaces = (InterfaceInfo[]) {
507 { TYPE_PPC_VIRTUAL_HYPERVISOR },
508 { TYPE_VOF_MACHINE_IF },
509 { }
510 },
511 };
512
513 static void pegasos2_machine_register_types(void)
514 {
515 type_register_static(&pegasos2_machine_info);
516 }
517
518 type_init(pegasos2_machine_register_types)
519
520 /* FDT creation for passing to firmware */
521
522 typedef struct {
523 void *fdt;
524 const char *path;
525 } FDTInfo;
526
527 /* We do everything in reverse order so it comes out right in the tree */
528
529 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
530 {
531 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi");
532 }
533
534 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
535 {
536 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0);
537 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1);
538 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb");
539 }
540
541 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi)
542 {
543 GString *name = g_string_sized_new(64);
544 uint32_t cells[3];
545
546 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1);
547 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2);
548 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa");
549 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa");
550
551 /* addional devices */
552 g_string_printf(name, "%s/lpt@i3bc", fi->path);
553 qemu_fdt_add_subnode(fi->fdt, name->str);
554 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
555 cells[0] = cpu_to_be32(7);
556 cells[1] = 0;
557 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
558 cells, 2 * sizeof(cells[0]));
559 cells[0] = cpu_to_be32(1);
560 cells[1] = cpu_to_be32(0x3bc);
561 cells[2] = cpu_to_be32(8);
562 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
563 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt");
564 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt");
565
566 g_string_printf(name, "%s/fdc@i3f0", fi->path);
567 qemu_fdt_add_subnode(fi->fdt, name->str);
568 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
569 cells[0] = cpu_to_be32(6);
570 cells[1] = 0;
571 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
572 cells, 2 * sizeof(cells[0]));
573 cells[0] = cpu_to_be32(1);
574 cells[1] = cpu_to_be32(0x3f0);
575 cells[2] = cpu_to_be32(8);
576 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
577 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc");
578 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc");
579
580 g_string_printf(name, "%s/timer@i40", fi->path);
581 qemu_fdt_add_subnode(fi->fdt, name->str);
582 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
583 cells[0] = cpu_to_be32(1);
584 cells[1] = cpu_to_be32(0x40);
585 cells[2] = cpu_to_be32(8);
586 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
587 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer");
588 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer");
589
590 g_string_printf(name, "%s/rtc@i70", fi->path);
591 qemu_fdt_add_subnode(fi->fdt, name->str);
592 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc");
593 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
594 cells[0] = cpu_to_be32(8);
595 cells[1] = 0;
596 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
597 cells, 2 * sizeof(cells[0]));
598 cells[0] = cpu_to_be32(1);
599 cells[1] = cpu_to_be32(0x70);
600 cells[2] = cpu_to_be32(2);
601 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
602 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc");
603 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc");
604
605 g_string_printf(name, "%s/keyboard@i60", fi->path);
606 qemu_fdt_add_subnode(fi->fdt, name->str);
607 cells[0] = cpu_to_be32(1);
608 cells[1] = 0;
609 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
610 cells, 2 * sizeof(cells[0]));
611 cells[0] = cpu_to_be32(1);
612 cells[1] = cpu_to_be32(0x60);
613 cells[2] = cpu_to_be32(5);
614 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
615 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard");
616 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard");
617
618 g_string_printf(name, "%s/8042@i60", fi->path);
619 qemu_fdt_add_subnode(fi->fdt, name->str);
620 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2);
621 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0);
622 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1);
623 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", "");
624 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
625 cells[0] = cpu_to_be32(1);
626 cells[1] = cpu_to_be32(0x60);
627 cells[2] = cpu_to_be32(5);
628 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
629 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "");
630 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042");
631
632 g_string_printf(name, "%s/serial@i2f8", fi->path);
633 qemu_fdt_add_subnode(fi->fdt, name->str);
634 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0);
635 cells[0] = cpu_to_be32(3);
636 cells[1] = 0;
637 qemu_fdt_setprop(fi->fdt, name->str, "interrupts",
638 cells, 2 * sizeof(cells[0]));
639 cells[0] = cpu_to_be32(1);
640 cells[1] = cpu_to_be32(0x2f8);
641 cells[2] = cpu_to_be32(8);
642 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0]));
643 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial");
644 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial");
645
646 g_string_free(name, TRUE);
647 }
648
649 static struct {
650 const char *id;
651 const char *name;
652 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi);
653 } device_map[] = {
654 { "pci11ab,6460", "host", NULL },
655 { "pci1106,8231", "isa", dt_isa },
656 { "pci1106,571", "ide", dt_ide },
657 { "pci1106,3044", "firewire", NULL },
658 { "pci1106,3038", "usb", dt_usb },
659 { "pci1106,8235", "other", NULL },
660 { "pci1106,3058", "sound", NULL },
661 { NULL, NULL }
662 };
663
664 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
665 {
666 FDTInfo *fi = opaque;
667 GString *node = g_string_new(NULL);
668 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5];
669 int i, j;
670 const char *name = NULL;
671 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x",
672 pci_get_word(&d->config[PCI_VENDOR_ID]),
673 pci_get_word(&d->config[PCI_DEVICE_ID]));
674
675 for (i = 0; device_map[i].id; i++) {
676 if (!strcmp(pn, device_map[i].id)) {
677 name = device_map[i].name;
678 break;
679 }
680 }
681 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn),
682 PCI_SLOT(d->devfn));
683 if (PCI_FUNC(d->devfn)) {
684 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn));
685 }
686
687 qemu_fdt_add_subnode(fi->fdt, node->str);
688 if (device_map[i].dtf) {
689 FDTInfo cfi = { fi->fdt, node->str };
690 device_map[i].dtf(bus, d, &cfi);
691 }
692 cells[0] = cpu_to_be32(d->devfn << 8);
693 cells[1] = 0;
694 cells[2] = 0;
695 cells[3] = 0;
696 cells[4] = 0;
697 j = 5;
698 for (i = 0; i < PCI_NUM_REGIONS; i++) {
699 if (!d->io_regions[i].size) {
700 continue;
701 }
702 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
703 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
704 cells[j] |= cpu_to_be32(1 << 24);
705 } else {
706 cells[j] |= cpu_to_be32(2 << 24);
707 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
708 cells[j] |= cpu_to_be32(4 << 28);
709 }
710 }
711 cells[j + 1] = 0;
712 cells[j + 2] = 0;
713 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32);
714 cells[j + 4] = cpu_to_be32(d->io_regions[i].size);
715 j += 5;
716 }
717 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0]));
718 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn);
719 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) {
720 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts",
721 pci_get_byte(&d->config[PCI_INTERRUPT_PIN]));
722 }
723 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */
724 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id",
725 pci_get_word(&d->config[PCI_SUBSYSTEM_ID]));
726 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id",
727 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID]));
728 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]);
729 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8);
730 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff);
731 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id",
732 pci_get_word(&d->config[PCI_DEVICE_ID]));
733 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id",
734 pci_get_word(&d->config[PCI_VENDOR_ID]));
735
736 g_string_free(node, TRUE);
737 }
738
739 static void *build_fdt(MachineState *machine, int *fdt_size)
740 {
741 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine);
742 PowerPCCPU *cpu = pm->cpu;
743 PCIBus *pci_bus;
744 FDTInfo fi;
745 uint32_t cells[16];
746 void *fdt = create_device_tree(fdt_size);
747
748 fi.fdt = fdt;
749
750 /* root node */
751 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description",
752 "Pegasos CHRP PowerPC System");
753 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2");
754 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH");
755 qemu_fdt_setprop_string(fdt, "/", "revision", "2B");
756 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2");
757 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp");
758 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1);
759 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2");
760
761 /* pci@c0000000 */
762 qemu_fdt_add_subnode(fdt, "/pci@c0000000");
763 cells[0] = 0;
764 cells[1] = 0;
765 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range",
766 cells, 2 * sizeof(cells[0]));
767 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1);
768 cells[0] = cpu_to_be32(PCI0_MEM_BASE);
769 cells[1] = cpu_to_be32(PCI0_MEM_SIZE);
770 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0]));
771 cells[0] = cpu_to_be32(0x01000000);
772 cells[1] = 0;
773 cells[2] = 0;
774 cells[3] = cpu_to_be32(PCI0_IO_BASE);
775 cells[4] = 0;
776 cells[5] = cpu_to_be32(PCI0_IO_SIZE);
777 cells[6] = cpu_to_be32(0x02000000);
778 cells[7] = 0;
779 cells[8] = cpu_to_be32(PCI0_MEM_BASE);
780 cells[9] = cpu_to_be32(PCI0_MEM_BASE);
781 cells[10] = 0;
782 cells[11] = cpu_to_be32(PCI0_MEM_SIZE);
783 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges",
784 cells, 12 * sizeof(cells[0]));
785 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2);
786 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3);
787 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci");
788 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci");
789
790 fi.path = "/pci@c0000000";
791 pci_bus = mv64361_get_pci_bus(pm->mv, 0);
792 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
793
794 /* pci@80000000 */
795 qemu_fdt_add_subnode(fdt, "/pci@80000000");
796 cells[0] = 0;
797 cells[1] = 0;
798 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range",
799 cells, 2 * sizeof(cells[0]));
800 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0);
801 cells[0] = cpu_to_be32(PCI1_MEM_BASE);
802 cells[1] = cpu_to_be32(PCI1_MEM_SIZE);
803 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0]));
804 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge",
805 0xf1000cb4);
806 cells[0] = cpu_to_be32(0x01000000);
807 cells[1] = 0;
808 cells[2] = 0;
809 cells[3] = cpu_to_be32(PCI1_IO_BASE);
810 cells[4] = 0;
811 cells[5] = cpu_to_be32(PCI1_IO_SIZE);
812 cells[6] = cpu_to_be32(0x02000000);
813 cells[7] = 0;
814 cells[8] = cpu_to_be32(PCI1_MEM_BASE);
815 cells[9] = cpu_to_be32(PCI1_MEM_BASE);
816 cells[10] = 0;
817 cells[11] = cpu_to_be32(PCI1_MEM_SIZE);
818 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges",
819 cells, 12 * sizeof(cells[0]));
820 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2);
821 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3);
822 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci");
823 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci");
824
825 fi.path = "/pci@80000000";
826 pci_bus = mv64361_get_pci_bus(pm->mv, 1);
827 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi);
828
829 qemu_fdt_add_subnode(fdt, "/failsafe");
830 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial");
831 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe");
832
833 qemu_fdt_add_subnode(fdt, "/rtas");
834 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT);
835 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE);
836 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND);
837 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF);
838 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR);
839 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character",
840 RTAS_DISPLAY_CHARACTER);
841 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config",
842 RTAS_WRITE_PCI_CONFIG);
843 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config",
844 RTAS_READ_PCI_CONFIG);
845 /* Pegasos2 firmware misspells check-exception and guests use that */
846 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption",
847 RTAS_CHECK_EXCEPTION);
848 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN);
849 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day",
850 RTAS_SET_TIME_OF_DAY);
851 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day",
852 RTAS_GET_TIME_OF_DAY);
853 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE);
854 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH);
855 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS);
856 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0);
857 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0);
858 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0);
859 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20);
860 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1);
861
862 /* cpus */
863 qemu_fdt_add_subnode(fdt, "/cpus");
864 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1);
865 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
866 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
867 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus");
868
869 /* FIXME Get CPU name from CPU object */
870 const char *cp = "/cpus/PowerPC,G4";
871 qemu_fdt_add_subnode(fdt, cp);
872 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0);
873 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000);
874 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size",
875 cpu->env.dcache_line_size);
876 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size",
877 cpu->env.dcache_line_size);
878 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000);
879 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size",
880 cpu->env.icache_line_size);
881 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
882 cpu->env.icache_line_size);
883 if (cpu->env.id_tlbs) {
884 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways);
885 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way);
886 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways);
887 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way);
888 qemu_fdt_setprop_string(fdt, cp, "tlb-split", "");
889 }
890 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways);
891 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb);
892 qemu_fdt_setprop_string(fdt, cp, "state", "running");
893 if (cpu->env.insns_flags & PPC_ALTIVEC) {
894 qemu_fdt_setprop_string(fdt, cp, "altivec", "");
895 qemu_fdt_setprop_string(fdt, cp, "data-streams", "");
896 }
897 /*
898 * FIXME What flags do data-streams, external-control and
899 * performance-monitor depend on?
900 */
901 qemu_fdt_setprop_string(fdt, cp, "external-control", "");
902 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) {
903 qemu_fdt_setprop_string(fdt, cp, "general-purpose", "");
904 }
905 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", "");
906 if (cpu->env.insns_flags & PPC_FLOAT_FRES) {
907 qemu_fdt_setprop_string(fdt, cp, "graphics", "");
908 }
909 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4);
910 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency",
911 cpu->env.tb_env->tb_freq);
912 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ);
913 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5);
914 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]);
915 cells[0] = 0;
916 cells[1] = 0;
917 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0]));
918 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu");
919 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1);
920
921 /* memory */
922 qemu_fdt_add_subnode(fdt, "/memory@0");
923 cells[0] = 0;
924 cells[1] = cpu_to_be32(machine->ram_size);
925 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0]));
926 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory");
927 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
928
929 qemu_fdt_add_subnode(fdt, "/chosen");
930 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
931 machine->kernel_cmdline ?: "");
932 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
933
934 qemu_fdt_add_subnode(fdt, "/openprom");
935 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1");
936
937 return fdt;
938 }
Ray Wang's QEMU Repository