include/hw/ppc/xics.h

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #ifndef XICS_H
  29 #define XICS_H
  30
  31 #include "hw/sysbus.h"
  32
  33 #define TYPE_XICS_COMMON "xics-common"
  34 #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
  35
  36 /*
  37  * Retain xics as the type name to be compatible for migration. Rest all the
  38  * functions, class and variables are renamed as xics_spapr.
  39  */
  40 #define TYPE_XICS_SPAPR "xics"
  41 #define XICS_SPAPR(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR)
  42
  43 #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
  44 #define XICS_SPAPR_KVM(obj) \
  45      OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
  46
  47 #define XICS_COMMON_CLASS(klass) \
  48      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
  49 #define XICS_SPAPR_CLASS(klass) \
  50      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_SPAPR)
  51 #define XICS_COMMON_GET_CLASS(obj) \
  52      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
  53 #define XICS_SPAPR_GET_CLASS(obj) \
  54      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
  55
  56 #define XICS_IPI        0x2
  57 #define XICS_BUID       0x1
  58 #define XICS_IRQ_BASE   (XICS_BUID << 12)
  59
  60 /*
  61  * We currently only support one BUID which is our interrupt base
  62  * (the kernel implementation supports more but we don't exploit
  63  *  that yet)
  64  */
  65 typedef struct XICSStateClass XICSStateClass;
  66 typedef struct XICSState XICSState;
  67 typedef struct ICPStateClass ICPStateClass;
  68 typedef struct ICPState ICPState;
  69 typedef struct ICSStateClass ICSStateClass;
  70 typedef struct ICSState ICSState;
  71 typedef struct ICSIRQState ICSIRQState;
  72 typedef struct XICSFabric XICSFabric;
  73
  74 struct XICSStateClass {
  75     DeviceClass parent_class;
  76
  77     void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu);
  78 };
  79
  80 struct XICSState {
  81     /*< private >*/
  82     DeviceState parent_obj;
  83     /*< public >*/
  84     uint32_t nr_servers;
  85     ICPState *ss;
  86 };
  87
  88 #define TYPE_ICP "icp"
  89 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
  90
  91 #define TYPE_KVM_ICP "icp-kvm"
  92 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
  93
  94 #define ICP_CLASS(klass) \
  95      OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
  96 #define ICP_GET_CLASS(obj) \
  97      OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
  98
  99 struct ICPStateClass {
 100     DeviceClass parent_class;
 101
 102     void (*pre_save)(ICPState *s);
 103     int (*post_load)(ICPState *s, int version_id);
 104 };
 105
 106 struct ICPState {
 107     /*< private >*/
 108     DeviceState parent_obj;
 109     /*< public >*/
 110     CPUState *cs;
 111     ICSState *xirr_owner;
 112     uint32_t xirr;
 113     uint8_t pending_priority;
 114     uint8_t mfrr;
 115     qemu_irq output;
 116     bool cap_irq_xics_enabled;
 117
 118     XICSFabric *xics;
 119 };
 120
 121 #define TYPE_ICS_BASE "ics-base"
 122 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
 123
 124 /* Retain ics for sPAPR for migration from existing sPAPR guests */
 125 #define TYPE_ICS_SIMPLE "ics"
 126 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
 127
 128 #define TYPE_ICS_KVM "icskvm"
 129 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM)
 130
 131 #define ICS_BASE_CLASS(klass) \
 132      OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
 133 #define ICS_BASE_GET_CLASS(obj) \
 134      OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
 135
 136 struct ICSStateClass {
 137     DeviceClass parent_class;
 138
 139     void (*realize)(DeviceState *dev, Error **errp);
 140     void (*pre_save)(ICSState *s);
 141     int (*post_load)(ICSState *s, int version_id);
 142     void (*reject)(ICSState *s, uint32_t irq);
 143     void (*resend)(ICSState *s);
 144     void (*eoi)(ICSState *s, uint32_t irq);
 145 };
 146
 147 struct ICSState {
 148     /*< private >*/
 149     DeviceState parent_obj;
 150     /*< public >*/
 151     uint32_t nr_irqs;
 152     uint32_t offset;
 153     qemu_irq *qirqs;
 154     ICSIRQState *irqs;
 155     XICSState *xics;
 156 };
 157
 158 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
 159 {
 160     return (ics->offset != 0) && (nr >= ics->offset)
 161         && (nr < (ics->offset + ics->nr_irqs));
 162 }
 163
 164 struct ICSIRQState {
 165     uint32_t server;
 166     uint8_t priority;
 167     uint8_t saved_priority;
 168 #define XICS_STATUS_ASSERTED           0x1
 169 #define XICS_STATUS_SENT               0x2
 170 #define XICS_STATUS_REJECTED           0x4
 171 #define XICS_STATUS_MASKED_PENDING     0x8
 172     uint8_t status;
 173 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
 174 #define XICS_FLAGS_IRQ_LSI             0x1
 175 #define XICS_FLAGS_IRQ_MSI             0x2
 176 #define XICS_FLAGS_IRQ_MASK            0x3
 177     uint8_t flags;
 178 };
 179
 180 typedef struct XICSFabric {
 181     Object parent;
 182 } XICSFabric;
 183
 184 #define TYPE_XICS_FABRIC "xics-fabric"
 185 #define XICS_FABRIC(obj)                                     \
 186     OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
 187 #define XICS_FABRIC_CLASS(klass)                                     \
 188     OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
 189 #define XICS_FABRIC_GET_CLASS(obj)                                   \
 190     OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
 191
 192 typedef struct XICSFabricClass {
 193     InterfaceClass parent;
 194     ICSState *(*ics_get)(XICSFabric *xi, int irq);
 195     void (*ics_resend)(XICSFabric *xi);
 196     ICPState *(*icp_get)(XICSFabric *xi, int server);
 197     void (*icp_resend)(XICSFabric *xi);
 198 } XICSFabricClass;
 199
 200 #define XICS_IRQS_SPAPR               1024
 201
 202 qemu_irq xics_get_qirq(XICSFabric *xi, int irq);
 203
 204 int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp);
 205 int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align,
 206                            Error **errp);
 207 void spapr_ics_free(ICSState *ics, int irq, int num);
 208 void spapr_dt_xics(XICSState *xics, void *fdt, uint32_t phandle);
 209
 210 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
 211 void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
 212
 213 /* Internal XICS interfaces */
 214 int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
 215
 216 void icp_set_cppr(ICPState *icp, uint8_t cppr);
 217 void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
 218 uint32_t icp_accept(ICPState *ss);
 219 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
 220 void icp_eoi(ICPState *icp, uint32_t xirr);
 221
 222 void ics_simple_write_xive(ICSState *ics, int nr, int server,
 223                            uint8_t priority, uint8_t saved_priority);
 224
 225 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 226
 227 void ics_resend(ICSState *ics);
 228 void icp_resend(ICPState *ss);
 229
 230 #endif /* XICS_H */