2 * RISC-V Emulation Helpers for QEMU.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/main-loop.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
26 /* Exceptions processing helpers */
27 G_NORETURN
void riscv_raise_exception(CPURISCVState
*env
,
28 uint32_t exception
, uintptr_t pc
)
30 CPUState
*cs
= env_cpu(env
);
31 cs
->exception_index
= exception
;
32 cpu_loop_exit_restore(cs
, pc
);
35 void helper_raise_exception(CPURISCVState
*env
, uint32_t exception
)
37 riscv_raise_exception(env
, exception
, 0);
40 target_ulong
helper_csrr(CPURISCVState
*env
, int csr
)
43 * The seed CSR must be accessed with a read-write instruction. A
44 * read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/
45 * CSRRCI with uimm=0 will raise an illegal instruction exception.
47 if (csr
== CSR_SEED
) {
48 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
52 RISCVException ret
= riscv_csrrw(env
, csr
, &val
, 0, 0);
54 if (ret
!= RISCV_EXCP_NONE
) {
55 riscv_raise_exception(env
, ret
, GETPC());
60 void helper_csrw(CPURISCVState
*env
, int csr
, target_ulong src
)
62 target_ulong mask
= env
->xl
== MXL_RV32
? UINT32_MAX
: (target_ulong
)-1;
63 RISCVException ret
= riscv_csrrw(env
, csr
, NULL
, src
, mask
);
65 if (ret
!= RISCV_EXCP_NONE
) {
66 riscv_raise_exception(env
, ret
, GETPC());
70 target_ulong
helper_csrrw(CPURISCVState
*env
, int csr
,
71 target_ulong src
, target_ulong write_mask
)
74 RISCVException ret
= riscv_csrrw(env
, csr
, &val
, src
, write_mask
);
76 if (ret
!= RISCV_EXCP_NONE
) {
77 riscv_raise_exception(env
, ret
, GETPC());
82 target_ulong
helper_csrr_i128(CPURISCVState
*env
, int csr
)
84 Int128 rv
= int128_zero();
85 RISCVException ret
= riscv_csrrw_i128(env
, csr
, &rv
,
89 if (ret
!= RISCV_EXCP_NONE
) {
90 riscv_raise_exception(env
, ret
, GETPC());
93 env
->retxh
= int128_gethi(rv
);
94 return int128_getlo(rv
);
97 void helper_csrw_i128(CPURISCVState
*env
, int csr
,
98 target_ulong srcl
, target_ulong srch
)
100 RISCVException ret
= riscv_csrrw_i128(env
, csr
, NULL
,
101 int128_make128(srcl
, srch
),
104 if (ret
!= RISCV_EXCP_NONE
) {
105 riscv_raise_exception(env
, ret
, GETPC());
109 target_ulong
helper_csrrw_i128(CPURISCVState
*env
, int csr
,
110 target_ulong srcl
, target_ulong srch
,
111 target_ulong maskl
, target_ulong maskh
)
113 Int128 rv
= int128_zero();
114 RISCVException ret
= riscv_csrrw_i128(env
, csr
, &rv
,
115 int128_make128(srcl
, srch
),
116 int128_make128(maskl
, maskh
));
118 if (ret
!= RISCV_EXCP_NONE
) {
119 riscv_raise_exception(env
, ret
, GETPC());
122 env
->retxh
= int128_gethi(rv
);
123 return int128_getlo(rv
);
126 #ifndef CONFIG_USER_ONLY
128 target_ulong
helper_sret(CPURISCVState
*env
)
131 target_ulong prev_priv
, prev_virt
;
133 if (!(env
->priv
>= PRV_S
)) {
134 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
137 target_ulong retpc
= env
->sepc
;
138 if (!riscv_has_ext(env
, RVC
) && (retpc
& 0x3)) {
139 riscv_raise_exception(env
, RISCV_EXCP_INST_ADDR_MIS
, GETPC());
142 if (get_field(env
->mstatus
, MSTATUS_TSR
) && !(env
->priv
>= PRV_M
)) {
143 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
146 if (riscv_has_ext(env
, RVH
) && riscv_cpu_virt_enabled(env
) &&
147 get_field(env
->hstatus
, HSTATUS_VTSR
)) {
148 riscv_raise_exception(env
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
, GETPC());
151 mstatus
= env
->mstatus
;
153 if (riscv_has_ext(env
, RVH
) && !riscv_cpu_virt_enabled(env
)) {
154 /* We support Hypervisor extensions and virtulisation is disabled */
155 target_ulong hstatus
= env
->hstatus
;
157 prev_priv
= get_field(mstatus
, MSTATUS_SPP
);
158 prev_virt
= get_field(hstatus
, HSTATUS_SPV
);
160 hstatus
= set_field(hstatus
, HSTATUS_SPV
, 0);
161 mstatus
= set_field(mstatus
, MSTATUS_SPP
, 0);
162 mstatus
= set_field(mstatus
, SSTATUS_SIE
,
163 get_field(mstatus
, SSTATUS_SPIE
));
164 mstatus
= set_field(mstatus
, SSTATUS_SPIE
, 1);
166 env
->mstatus
= mstatus
;
167 env
->hstatus
= hstatus
;
170 riscv_cpu_swap_hypervisor_regs(env
);
173 riscv_cpu_set_virt_enabled(env
, prev_virt
);
175 prev_priv
= get_field(mstatus
, MSTATUS_SPP
);
177 mstatus
= set_field(mstatus
, MSTATUS_SIE
,
178 get_field(mstatus
, MSTATUS_SPIE
));
179 mstatus
= set_field(mstatus
, MSTATUS_SPIE
, 1);
180 mstatus
= set_field(mstatus
, MSTATUS_SPP
, PRV_U
);
181 env
->mstatus
= mstatus
;
184 riscv_cpu_set_mode(env
, prev_priv
);
189 target_ulong
helper_mret(CPURISCVState
*env
)
191 if (!(env
->priv
>= PRV_M
)) {
192 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
195 target_ulong retpc
= env
->mepc
;
196 if (!riscv_has_ext(env
, RVC
) && (retpc
& 0x3)) {
197 riscv_raise_exception(env
, RISCV_EXCP_INST_ADDR_MIS
, GETPC());
200 uint64_t mstatus
= env
->mstatus
;
201 target_ulong prev_priv
= get_field(mstatus
, MSTATUS_MPP
);
203 if (riscv_feature(env
, RISCV_FEATURE_PMP
) &&
204 !pmp_get_num_rules(env
) && (prev_priv
!= PRV_M
)) {
205 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
208 target_ulong prev_virt
= get_field(env
->mstatus
, MSTATUS_MPV
);
209 mstatus
= set_field(mstatus
, MSTATUS_MIE
,
210 get_field(mstatus
, MSTATUS_MPIE
));
211 mstatus
= set_field(mstatus
, MSTATUS_MPIE
, 1);
212 mstatus
= set_field(mstatus
, MSTATUS_MPP
, PRV_U
);
213 mstatus
= set_field(mstatus
, MSTATUS_MPV
, 0);
214 env
->mstatus
= mstatus
;
215 riscv_cpu_set_mode(env
, prev_priv
);
217 if (riscv_has_ext(env
, RVH
)) {
219 riscv_cpu_swap_hypervisor_regs(env
);
222 riscv_cpu_set_virt_enabled(env
, prev_virt
);
228 void helper_wfi(CPURISCVState
*env
)
230 CPUState
*cs
= env_cpu(env
);
231 bool rvs
= riscv_has_ext(env
, RVS
);
232 bool prv_u
= env
->priv
== PRV_U
;
233 bool prv_s
= env
->priv
== PRV_S
;
235 if (((prv_s
|| (!rvs
&& prv_u
)) && get_field(env
->mstatus
, MSTATUS_TW
)) ||
236 (rvs
&& prv_u
&& !riscv_cpu_virt_enabled(env
))) {
237 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
238 } else if (riscv_cpu_virt_enabled(env
) && (prv_u
||
239 (prv_s
&& get_field(env
->hstatus
, HSTATUS_VTW
)))) {
240 riscv_raise_exception(env
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
, GETPC());
243 cs
->exception_index
= EXCP_HLT
;
248 void helper_tlb_flush(CPURISCVState
*env
)
250 CPUState
*cs
= env_cpu(env
);
251 if (!(env
->priv
>= PRV_S
) ||
252 (env
->priv
== PRV_S
&&
253 get_field(env
->mstatus
, MSTATUS_TVM
))) {
254 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
255 } else if (riscv_has_ext(env
, RVH
) && riscv_cpu_virt_enabled(env
) &&
256 get_field(env
->hstatus
, HSTATUS_VTVM
)) {
257 riscv_raise_exception(env
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
, GETPC());
263 void helper_hyp_tlb_flush(CPURISCVState
*env
)
265 CPUState
*cs
= env_cpu(env
);
267 if (env
->priv
== PRV_S
&& riscv_cpu_virt_enabled(env
)) {
268 riscv_raise_exception(env
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
, GETPC());
271 if (env
->priv
== PRV_M
||
272 (env
->priv
== PRV_S
&& !riscv_cpu_virt_enabled(env
))) {
277 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
280 void helper_hyp_gvma_tlb_flush(CPURISCVState
*env
)
282 if (env
->priv
== PRV_S
&& !riscv_cpu_virt_enabled(env
) &&
283 get_field(env
->mstatus
, MSTATUS_TVM
)) {
284 riscv_raise_exception(env
, RISCV_EXCP_ILLEGAL_INST
, GETPC());
287 helper_hyp_tlb_flush(env
);
290 target_ulong
helper_hyp_hlvx_hu(CPURISCVState
*env
, target_ulong address
)
292 int mmu_idx
= cpu_mmu_index(env
, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK
;
294 return cpu_lduw_mmuidx_ra(env
, address
, mmu_idx
, GETPC());
297 target_ulong
helper_hyp_hlvx_wu(CPURISCVState
*env
, target_ulong address
)
299 int mmu_idx
= cpu_mmu_index(env
, true) | TB_FLAGS_PRIV_HYP_ACCESS_MASK
;
301 return cpu_ldl_mmuidx_ra(env
, address
, mmu_idx
, GETPC());
304 #endif /* !CONFIG_USER_ONLY */