target/riscv/internals.h

   1 /*
   2  * QEMU RISC-V CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef RISCV_CPU_INTERNALS_H
  20 #define RISCV_CPU_INTERNALS_H
  21
  22 #include "hw/registerfields.h"
  23
  24 /* share data between vector helpers and decode code */
  25 FIELD(VDATA, VM, 0, 1)
  26 FIELD(VDATA, LMUL, 1, 3)
  27 FIELD(VDATA, VTA, 4, 1)
  28 FIELD(VDATA, VTA_ALL_1S, 5, 1)
  29 FIELD(VDATA, NF, 6, 4)
  30 FIELD(VDATA, WD, 6, 1)
  31
  32 /* float point classify helpers */
  33 target_ulong fclass_h(uint64_t frs1);
  34 target_ulong fclass_s(uint64_t frs1);
  35 target_ulong fclass_d(uint64_t frs1);
  36
  37 #ifndef CONFIG_USER_ONLY
  38 extern const VMStateDescription vmstate_riscv_cpu;
  39 #endif
  40
  41 enum {
  42     RISCV_FRM_RNE = 0,  /* Round to Nearest, ties to Even */
  43     RISCV_FRM_RTZ = 1,  /* Round towards Zero */
  44     RISCV_FRM_RDN = 2,  /* Round Down */
  45     RISCV_FRM_RUP = 3,  /* Round Up */
  46     RISCV_FRM_RMM = 4,  /* Round to Nearest, ties to Max Magnitude */
  47     RISCV_FRM_DYN = 7,  /* Dynamic rounding mode */
  48     RISCV_FRM_ROD = 8,  /* Round to Odd */
  49 };
  50
  51 static inline uint64_t nanbox_s(CPURISCVState *env, float32 f)
  52 {
  53     /* the value is sign-extended instead of NaN-boxing for zfinx */
  54     if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  55         return (int32_t)f;
  56     } else {
  57         return f | MAKE_64BIT_MASK(32, 32);
  58     }
  59 }
  60
  61 static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
  62 {
  63     /* Disable NaN-boxing check when enable zfinx */
  64     if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  65         return (uint32_t)f;
  66     }
  67
  68     uint64_t mask = MAKE_64BIT_MASK(32, 32);
  69
  70     if (likely((f & mask) == mask)) {
  71         return (uint32_t)f;
  72     } else {
  73         return 0x7fc00000u; /* default qnan */
  74     }
  75 }
  76
  77 static inline uint64_t nanbox_h(CPURISCVState *env, float16 f)
  78 {
  79     /* the value is sign-extended instead of NaN-boxing for zfinx */
  80     if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  81         return (int16_t)f;
  82     } else {
  83         return f | MAKE_64BIT_MASK(16, 48);
  84     }
  85 }
  86
  87 static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
  88 {
  89     /* Disable nanbox check when enable zfinx */
  90     if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
  91         return (uint16_t)f;
  92     }
  93
  94     uint64_t mask = MAKE_64BIT_MASK(16, 48);
  95
  96     if (likely((f & mask) == mask)) {
  97         return (uint16_t)f;
  98     } else {
  99         return 0x7E00u; /* default qnan */
 100     }
 101 }
 102
 103 #endif