4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
19 #include "qemu/thread.h"
20 #include "hw/i386/apic_internal.h"
21 #include "hw/i386/apic.h"
22 #include "hw/i386/ioapic.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/host-utils.h"
26 #include "hw/i386/pc.h"
27 #include "hw/i386/apic-msidef.h"
29 #define MAX_APIC_WORDS 8
31 #define SYNC_FROM_VAPIC 0x1
32 #define SYNC_TO_VAPIC 0x2
33 #define SYNC_ISR_IRR_TO_VAPIC 0x4
35 static APICCommonState
*local_apics
[MAX_APICS
+ 1];
37 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
);
38 static void apic_update_irq(APICCommonState
*s
);
39 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
40 uint8_t dest
, uint8_t dest_mode
);
42 /* Find first bit starting from msb */
43 static int apic_fls_bit(uint32_t value
)
45 return 31 - clz32(value
);
48 /* Find first bit starting from lsb */
49 static int apic_ffs_bit(uint32_t value
)
54 static inline void apic_set_bit(uint32_t *tab
, int index
)
58 mask
= 1 << (index
& 0x1f);
62 static inline void apic_reset_bit(uint32_t *tab
, int index
)
66 mask
= 1 << (index
& 0x1f);
70 static inline int apic_get_bit(uint32_t *tab
, int index
)
74 mask
= 1 << (index
& 0x1f);
75 return !!(tab
[i
] & mask
);
78 /* return -1 if no bit is set */
79 static int get_highest_priority_int(uint32_t *tab
)
82 for (i
= 7; i
>= 0; i
--) {
84 return i
* 32 + apic_fls_bit(tab
[i
]);
90 static void apic_sync_vapic(APICCommonState
*s
, int sync_type
)
92 VAPICState vapic_state
;
97 if (!s
->vapic_paddr
) {
100 if (sync_type
& SYNC_FROM_VAPIC
) {
101 cpu_physical_memory_rw(s
->vapic_paddr
, (void *)&vapic_state
,
102 sizeof(vapic_state
), 0);
103 s
->tpr
= vapic_state
.tpr
;
105 if (sync_type
& (SYNC_TO_VAPIC
| SYNC_ISR_IRR_TO_VAPIC
)) {
106 start
= offsetof(VAPICState
, isr
);
107 length
= offsetof(VAPICState
, enabled
) - offsetof(VAPICState
, isr
);
109 if (sync_type
& SYNC_TO_VAPIC
) {
110 assert(qemu_cpu_is_self(CPU(s
->cpu
)));
112 vapic_state
.tpr
= s
->tpr
;
113 vapic_state
.enabled
= 1;
115 length
= sizeof(VAPICState
);
118 vector
= get_highest_priority_int(s
->isr
);
122 vapic_state
.isr
= vector
& 0xf0;
124 vapic_state
.zero
= 0;
126 vector
= get_highest_priority_int(s
->irr
);
130 vapic_state
.irr
= vector
& 0xff;
132 cpu_physical_memory_write_rom(&address_space_memory
,
133 s
->vapic_paddr
+ start
,
134 ((void *)&vapic_state
) + start
, length
);
138 static void apic_vapic_base_update(APICCommonState
*s
)
140 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
143 static void apic_local_deliver(APICCommonState
*s
, int vector
)
145 uint32_t lvt
= s
->lvt
[vector
];
148 trace_apic_local_deliver(vector
, (lvt
>> 8) & 7);
150 if (lvt
& APIC_LVT_MASKED
)
153 switch ((lvt
>> 8) & 7) {
155 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SMI
);
159 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_NMI
);
163 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HARD
);
167 trigger_mode
= APIC_TRIGGER_EDGE
;
168 if ((vector
== APIC_LVT_LINT0
|| vector
== APIC_LVT_LINT1
) &&
169 (lvt
& APIC_LVT_LEVEL_TRIGGER
))
170 trigger_mode
= APIC_TRIGGER_LEVEL
;
171 apic_set_irq(s
, lvt
& 0xff, trigger_mode
);
175 void apic_deliver_pic_intr(DeviceState
*dev
, int level
)
177 APICCommonState
*s
= APIC_COMMON(dev
);
180 apic_local_deliver(s
, APIC_LVT_LINT0
);
182 uint32_t lvt
= s
->lvt
[APIC_LVT_LINT0
];
184 switch ((lvt
>> 8) & 7) {
186 if (!(lvt
& APIC_LVT_LEVEL_TRIGGER
))
188 apic_reset_bit(s
->irr
, lvt
& 0xff);
191 cpu_reset_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HARD
);
197 static void apic_external_nmi(APICCommonState
*s
)
199 apic_local_deliver(s
, APIC_LVT_LINT1
);
202 #define foreach_apic(apic, deliver_bitmask, code) \
204 int __i, __j, __mask;\
205 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
206 __mask = deliver_bitmask[__i];\
208 for(__j = 0; __j < 32; __j++) {\
209 if (__mask & (1 << __j)) {\
210 apic = local_apics[__i * 32 + __j];\
220 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
221 uint8_t delivery_mode
, uint8_t vector_num
,
222 uint8_t trigger_mode
)
224 APICCommonState
*apic_iter
;
226 switch (delivery_mode
) {
228 /* XXX: search for focus processor, arbitration */
232 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
233 if (deliver_bitmask
[i
]) {
234 d
= i
* 32 + apic_ffs_bit(deliver_bitmask
[i
]);
239 apic_iter
= local_apics
[d
];
241 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
251 foreach_apic(apic_iter
, deliver_bitmask
,
252 cpu_interrupt(CPU(apic_iter
->cpu
), CPU_INTERRUPT_SMI
)
257 foreach_apic(apic_iter
, deliver_bitmask
,
258 cpu_interrupt(CPU(apic_iter
->cpu
), CPU_INTERRUPT_NMI
)
263 /* normal INIT IPI sent to processors */
264 foreach_apic(apic_iter
, deliver_bitmask
,
265 cpu_interrupt(CPU(apic_iter
->cpu
),
271 /* handled in I/O APIC code */
278 foreach_apic(apic_iter
, deliver_bitmask
,
279 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
282 void apic_deliver_irq(uint8_t dest
, uint8_t dest_mode
, uint8_t delivery_mode
,
283 uint8_t vector_num
, uint8_t trigger_mode
)
285 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
287 trace_apic_deliver_irq(dest
, dest_mode
, delivery_mode
, vector_num
,
290 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
291 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
294 static void apic_set_base(APICCommonState
*s
, uint64_t val
)
296 s
->apicbase
= (val
& 0xfffff000) |
297 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
298 /* if disabled, cannot be enabled again */
299 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
300 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
301 cpu_clear_apic_feature(&s
->cpu
->env
);
302 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
306 static void apic_set_tpr(APICCommonState
*s
, uint8_t val
)
308 /* Updates from cr8 are ignored while the VAPIC is active */
309 if (!s
->vapic_paddr
) {
315 static uint8_t apic_get_tpr(APICCommonState
*s
)
317 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
321 static int apic_get_ppr(APICCommonState
*s
)
326 isrv
= get_highest_priority_int(s
->isr
);
337 static int apic_get_arb_pri(APICCommonState
*s
)
339 /* XXX: arbitration */
345 * <0 - low prio interrupt,
347 * >0 - interrupt number
349 static int apic_irq_pending(APICCommonState
*s
)
352 irrv
= get_highest_priority_int(s
->irr
);
356 ppr
= apic_get_ppr(s
);
357 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0)) {
364 /* signal the CPU if an irq is pending */
365 static void apic_update_irq(APICCommonState
*s
)
369 if (!(s
->spurious_vec
& APIC_SV_ENABLE
)) {
373 if (!qemu_cpu_is_self(cpu
)) {
374 cpu_interrupt(cpu
, CPU_INTERRUPT_POLL
);
375 } else if (apic_irq_pending(s
) > 0) {
376 cpu_interrupt(cpu
, CPU_INTERRUPT_HARD
);
380 void apic_poll_irq(DeviceState
*dev
)
382 APICCommonState
*s
= APIC_COMMON(dev
);
384 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
388 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
)
390 apic_report_irq_delivered(!apic_get_bit(s
->irr
, vector_num
));
392 apic_set_bit(s
->irr
, vector_num
);
394 apic_set_bit(s
->tmr
, vector_num
);
396 apic_reset_bit(s
->tmr
, vector_num
);
397 if (s
->vapic_paddr
) {
398 apic_sync_vapic(s
, SYNC_ISR_IRR_TO_VAPIC
);
400 * The vcpu thread needs to see the new IRR before we pull its current
401 * TPR value. That way, if we miss a lowering of the TRP, the guest
402 * has the chance to notice the new IRR and poll for IRQs on its own.
405 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
410 static void apic_eoi(APICCommonState
*s
)
413 isrv
= get_highest_priority_int(s
->isr
);
416 apic_reset_bit(s
->isr
, isrv
);
417 if (!(s
->spurious_vec
& APIC_SV_DIRECTED_IO
) && apic_get_bit(s
->tmr
, isrv
)) {
418 ioapic_eoi_broadcast(isrv
);
420 apic_sync_vapic(s
, SYNC_FROM_VAPIC
| SYNC_TO_VAPIC
);
424 static int apic_find_dest(uint8_t dest
)
426 APICCommonState
*apic
= local_apics
[dest
];
429 if (apic
&& apic
->id
== dest
)
430 return dest
; /* shortcut in case apic->id == apic->idx */
432 for (i
= 0; i
< MAX_APICS
; i
++) {
433 apic
= local_apics
[i
];
434 if (apic
&& apic
->id
== dest
)
443 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
444 uint8_t dest
, uint8_t dest_mode
)
446 APICCommonState
*apic_iter
;
449 if (dest_mode
== 0) {
451 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
453 int idx
= apic_find_dest(dest
);
454 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
456 apic_set_bit(deliver_bitmask
, idx
);
459 /* XXX: cluster mode */
460 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
461 for(i
= 0; i
< MAX_APICS
; i
++) {
462 apic_iter
= local_apics
[i
];
464 if (apic_iter
->dest_mode
== 0xf) {
465 if (dest
& apic_iter
->log_dest
)
466 apic_set_bit(deliver_bitmask
, i
);
467 } else if (apic_iter
->dest_mode
== 0x0) {
468 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
469 (dest
& apic_iter
->log_dest
& 0x0f)) {
470 apic_set_bit(deliver_bitmask
, i
);
480 static void apic_startup(APICCommonState
*s
, int vector_num
)
482 s
->sipi_vector
= vector_num
;
483 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SIPI
);
486 void apic_sipi(DeviceState
*dev
)
488 APICCommonState
*s
= APIC_COMMON(dev
);
490 cpu_reset_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SIPI
);
492 if (!s
->wait_for_sipi
)
494 cpu_x86_load_seg_cache_sipi(s
->cpu
, s
->sipi_vector
);
495 s
->wait_for_sipi
= 0;
498 static void apic_deliver(DeviceState
*dev
, uint8_t dest
, uint8_t dest_mode
,
499 uint8_t delivery_mode
, uint8_t vector_num
,
500 uint8_t trigger_mode
)
502 APICCommonState
*s
= APIC_COMMON(dev
);
503 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
504 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
505 APICCommonState
*apic_iter
;
507 switch (dest_shorthand
) {
509 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
512 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
513 apic_set_bit(deliver_bitmask
, s
->idx
);
516 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
519 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
520 apic_reset_bit(deliver_bitmask
, s
->idx
);
524 switch (delivery_mode
) {
527 int trig_mode
= (s
->icr
[0] >> 15) & 1;
528 int level
= (s
->icr
[0] >> 14) & 1;
529 if (level
== 0 && trig_mode
== 1) {
530 foreach_apic(apic_iter
, deliver_bitmask
,
531 apic_iter
->arb_id
= apic_iter
->id
);
538 foreach_apic(apic_iter
, deliver_bitmask
,
539 apic_startup(apic_iter
, vector_num
) );
543 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
546 static bool apic_check_pic(APICCommonState
*s
)
548 if (!apic_accept_pic_intr(&s
->busdev
.qdev
) || !pic_get_output(isa_pic
)) {
551 apic_deliver_pic_intr(&s
->busdev
.qdev
, 1);
555 int apic_get_interrupt(DeviceState
*dev
)
557 APICCommonState
*s
= APIC_COMMON(dev
);
560 /* if the APIC is installed or enabled, we let the 8259 handle the
564 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
567 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
568 intno
= apic_irq_pending(s
);
571 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
573 } else if (intno
< 0) {
574 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
575 return s
->spurious_vec
& 0xff;
577 apic_reset_bit(s
->irr
, intno
);
578 apic_set_bit(s
->isr
, intno
);
579 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
581 /* re-inject if there is still a pending PIC interrupt */
589 int apic_accept_pic_intr(DeviceState
*dev
)
591 APICCommonState
*s
= APIC_COMMON(dev
);
597 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
599 if ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
600 (lvt0
& APIC_LVT_MASKED
) == 0)
606 static uint32_t apic_get_current_count(APICCommonState
*s
)
610 d
= (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - s
->initial_count_load_time
) >>
612 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
614 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
616 if (d
>= s
->initial_count
)
619 val
= s
->initial_count
- d
;
624 static void apic_timer_update(APICCommonState
*s
, int64_t current_time
)
626 if (apic_next_timer(s
, current_time
)) {
627 timer_mod(s
->timer
, s
->next_time
);
633 static void apic_timer(void *opaque
)
635 APICCommonState
*s
= opaque
;
637 apic_local_deliver(s
, APIC_LVT_TIMER
);
638 apic_timer_update(s
, s
->next_time
);
641 static uint32_t apic_mem_readb(void *opaque
, hwaddr addr
)
646 static uint32_t apic_mem_readw(void *opaque
, hwaddr addr
)
651 static void apic_mem_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
655 static void apic_mem_writew(void *opaque
, hwaddr addr
, uint32_t val
)
659 static uint32_t apic_mem_readl(void *opaque
, hwaddr addr
)
666 dev
= cpu_get_current_apic();
670 s
= APIC_COMMON(dev
);
672 index
= (addr
>> 4) & 0xff;
677 case 0x03: /* version */
678 val
= 0x11 | ((APIC_LVT_NB
- 1) << 16); /* version 0x11 */
681 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
682 if (apic_report_tpr_access
) {
683 cpu_report_tpr_access(&s
->cpu
->env
, TPR_ACCESS_READ
);
688 val
= apic_get_arb_pri(s
);
692 val
= apic_get_ppr(s
);
698 val
= s
->log_dest
<< 24;
701 val
= s
->dest_mode
<< 28;
704 val
= s
->spurious_vec
;
707 val
= s
->isr
[index
& 7];
710 val
= s
->tmr
[index
& 7];
713 val
= s
->irr
[index
& 7];
720 val
= s
->icr
[index
& 1];
723 val
= s
->lvt
[index
- 0x32];
726 val
= s
->initial_count
;
729 val
= apic_get_current_count(s
);
732 val
= s
->divide_conf
;
735 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
739 trace_apic_mem_readl(addr
, val
);
743 static void apic_send_msi(hwaddr addr
, uint32_t data
)
745 uint8_t dest
= (addr
& MSI_ADDR_DEST_ID_MASK
) >> MSI_ADDR_DEST_ID_SHIFT
;
746 uint8_t vector
= (data
& MSI_DATA_VECTOR_MASK
) >> MSI_DATA_VECTOR_SHIFT
;
747 uint8_t dest_mode
= (addr
>> MSI_ADDR_DEST_MODE_SHIFT
) & 0x1;
748 uint8_t trigger_mode
= (data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
749 uint8_t delivery
= (data
>> MSI_DATA_DELIVERY_MODE_SHIFT
) & 0x7;
750 /* XXX: Ignore redirection hint. */
751 apic_deliver_irq(dest
, dest_mode
, delivery
, vector
, trigger_mode
);
754 static void apic_mem_writel(void *opaque
, hwaddr addr
, uint32_t val
)
758 int index
= (addr
>> 4) & 0xff;
759 if (addr
> 0xfff || !index
) {
760 /* MSI and MMIO APIC are at the same memory location,
761 * but actually not on the global bus: MSI is on PCI bus
762 * APIC is connected directly to the CPU.
763 * Mapping them on the global bus happens to work because
764 * MSI registers are reserved in APIC MMIO and vice versa. */
765 apic_send_msi(addr
, val
);
769 dev
= cpu_get_current_apic();
773 s
= APIC_COMMON(dev
);
775 trace_apic_mem_writel(addr
, val
);
784 if (apic_report_tpr_access
) {
785 cpu_report_tpr_access(&s
->cpu
->env
, TPR_ACCESS_WRITE
);
788 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
798 s
->log_dest
= val
>> 24;
801 s
->dest_mode
= val
>> 28;
804 s
->spurious_vec
= val
& 0x1ff;
814 apic_deliver(dev
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
815 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
816 (s
->icr
[0] >> 15) & 1);
823 int n
= index
- 0x32;
825 if (n
== APIC_LVT_TIMER
) {
826 apic_timer_update(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
827 } else if (n
== APIC_LVT_LINT0
&& apic_check_pic(s
)) {
833 s
->initial_count
= val
;
834 s
->initial_count_load_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
835 apic_timer_update(s
, s
->initial_count_load_time
);
842 s
->divide_conf
= val
& 0xb;
843 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
844 s
->count_shift
= (v
+ 1) & 7;
848 s
->esr
|= ESR_ILLEGAL_ADDRESS
;
853 static void apic_pre_save(APICCommonState
*s
)
855 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
858 static void apic_post_load(APICCommonState
*s
)
860 if (s
->timer_expiry
!= -1) {
861 timer_mod(s
->timer
, s
->timer_expiry
);
867 static const MemoryRegionOps apic_io_ops
= {
869 .read
= { apic_mem_readb
, apic_mem_readw
, apic_mem_readl
, },
870 .write
= { apic_mem_writeb
, apic_mem_writew
, apic_mem_writel
, },
872 .endianness
= DEVICE_NATIVE_ENDIAN
,
875 static void apic_realize(DeviceState
*dev
, Error
**errp
)
877 APICCommonState
*s
= APIC_COMMON(dev
);
879 memory_region_init_io(&s
->io_memory
, OBJECT(s
), &apic_io_ops
, s
, "apic-msi",
882 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, apic_timer
, s
);
883 local_apics
[s
->idx
] = s
;
885 msi_supported
= true;
888 static void apic_class_init(ObjectClass
*klass
, void *data
)
890 APICCommonClass
*k
= APIC_COMMON_CLASS(klass
);
892 k
->realize
= apic_realize
;
893 k
->set_base
= apic_set_base
;
894 k
->set_tpr
= apic_set_tpr
;
895 k
->get_tpr
= apic_get_tpr
;
896 k
->vapic_base_update
= apic_vapic_base_update
;
897 k
->external_nmi
= apic_external_nmi
;
898 k
->pre_save
= apic_pre_save
;
899 k
->post_load
= apic_post_load
;
902 static const TypeInfo apic_info
= {
904 .instance_size
= sizeof(APICCommonState
),
905 .parent
= TYPE_APIC_COMMON
,
906 .class_init
= apic_class_init
,
909 static void apic_register_types(void)
911 type_register_static(&apic_info
);
914 type_init(apic_register_types
)