| blob | 80748d892e7b16e17bca973d45feb72d42732436 |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
27 #include "../tcg-ldst.c.inc"
29 #if HOST_BIG_ENDIAN
30 # define MIPS_BE 1
31 #else
32 # define MIPS_BE 0
33 #endif
35 #if TCG_TARGET_REG_BITS == 32
36 # define LO_OFF (MIPS_BE * 4)
37 # define HI_OFF (4 - LO_OFF)
38 #else
39 /* To assert at compile-time that these values are never used
40 for TCG_TARGET_REG_BITS == 64. */
41 int link_error(void);
42 # define LO_OFF link_error()
43 # define HI_OFF link_error()
44 #endif
46 #ifdef CONFIG_DEBUG_TCG
47 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
48 "zero",
49 "at",
50 "v0",
51 "v1",
52 "a0",
53 "a1",
54 "a2",
55 "a3",
56 "t0",
57 "t1",
58 "t2",
59 "t3",
60 "t4",
61 "t5",
62 "t6",
63 "t7",
64 "s0",
65 "s1",
66 "s2",
67 "s3",
68 "s4",
69 "s5",
70 "s6",
71 "s7",
72 "t8",
73 "t9",
74 "k0",
75 "k1",
76 "gp",
77 "sp",
78 "s8",
79 "ra",
80 };
81 #endif
83 #define TCG_TMP0 TCG_REG_AT
84 #define TCG_TMP1 TCG_REG_T9
85 #define TCG_TMP2 TCG_REG_T8
86 #define TCG_TMP3 TCG_REG_T7
88 #ifndef CONFIG_SOFTMMU
89 #define TCG_GUEST_BASE_REG TCG_REG_S1
90 #endif
92 /* check if we really need so many registers :P */
93 static const int tcg_target_reg_alloc_order[] = {
94 /* Call saved registers. */
95 TCG_REG_S0,
96 TCG_REG_S1,
97 TCG_REG_S2,
98 TCG_REG_S3,
99 TCG_REG_S4,
100 TCG_REG_S5,
101 TCG_REG_S6,
102 TCG_REG_S7,
103 TCG_REG_S8,
105 /* Call clobbered registers. */
106 TCG_REG_T4,
107 TCG_REG_T5,
108 TCG_REG_T6,
109 TCG_REG_T7,
110 TCG_REG_T8,
111 TCG_REG_T9,
112 TCG_REG_V1,
113 TCG_REG_V0,
115 /* Argument registers, opposite order of allocation. */
116 TCG_REG_T3,
117 TCG_REG_T2,
118 TCG_REG_T1,
119 TCG_REG_T0,
120 TCG_REG_A3,
121 TCG_REG_A2,
122 TCG_REG_A1,
123 TCG_REG_A0,
124 };
126 static const TCGReg tcg_target_call_iarg_regs[] = {
127 TCG_REG_A0,
128 TCG_REG_A1,
129 TCG_REG_A2,
130 TCG_REG_A3,
131 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
132 TCG_REG_T0,
133 TCG_REG_T1,
134 TCG_REG_T2,
135 TCG_REG_T3,
136 #endif
137 };
139 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
140 {
141 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
142 tcg_debug_assert(slot >= 0 && slot <= 1);
143 return TCG_REG_V0 + slot;
144 }
146 static const tcg_insn_unit *tb_ret_addr;
147 static const tcg_insn_unit *bswap32_addr;
148 static const tcg_insn_unit *bswap32u_addr;
149 static const tcg_insn_unit *bswap64_addr;
151 static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
152 {
153 /* Let the compiler perform the right-shift as part of the arithmetic. */
154 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
155 ptrdiff_t disp = target - (src_rx + 1);
156 if (disp == (int16_t)disp) {
157 *src_rw = deposit32(*src_rw, 0, 16, disp);
158 return true;
159 }
160 return false;
161 }
163 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
164 intptr_t value, intptr_t addend)
165 {
166 tcg_debug_assert(type == R_MIPS_PC16);
167 tcg_debug_assert(addend == 0);
168 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
169 }
171 #define TCG_CT_CONST_ZERO 0x100
172 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
173 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
174 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
175 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
176 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
178 #define ALL_GENERAL_REGS 0xffffffffu
179 #define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
181 #ifdef CONFIG_SOFTMMU
182 #define ALL_QLOAD_REGS \
183 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
184 #define ALL_QSTORE_REGS \
185 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
186 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
187 : (1 << TCG_REG_A1)))
188 #else
189 #define ALL_QLOAD_REGS NOA0_REGS
190 #define ALL_QSTORE_REGS NOA0_REGS
191 #endif
194 static bool is_p2m1(tcg_target_long val)
195 {
196 return val && ((val + 1) & val) == 0;
197 }
199 /* test if a constant matches the constraint */
200 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
201 {
202 if (ct & TCG_CT_CONST) {
203 return 1;
204 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
205 return 1;
206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
207 return 1;
208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
209 return 1;
210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
211 return 1;
212 } else if ((ct & TCG_CT_CONST_P2M1)
213 && use_mips32r2_instructions && is_p2m1(val)) {
214 return 1;
215 } else if ((ct & TCG_CT_CONST_WSZ)
216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
217 return 1;
218 }
219 return 0;
220 }
222 /* instruction opcodes */
223 typedef enum {
224 OPC_J = 002 << 26,
225 OPC_JAL = 003 << 26,
226 OPC_BEQ = 004 << 26,
227 OPC_BNE = 005 << 26,
228 OPC_BLEZ = 006 << 26,
229 OPC_BGTZ = 007 << 26,
230 OPC_ADDIU = 011 << 26,
231 OPC_SLTI = 012 << 26,
232 OPC_SLTIU = 013 << 26,
233 OPC_ANDI = 014 << 26,
234 OPC_ORI = 015 << 26,
235 OPC_XORI = 016 << 26,
236 OPC_LUI = 017 << 26,
237 OPC_BNEL = 025 << 26,
238 OPC_BNEZALC_R6 = 030 << 26,
239 OPC_DADDIU = 031 << 26,
240 OPC_LDL = 032 << 26,
241 OPC_LDR = 033 << 26,
242 OPC_LB = 040 << 26,
243 OPC_LH = 041 << 26,
244 OPC_LWL = 042 << 26,
245 OPC_LW = 043 << 26,
246 OPC_LBU = 044 << 26,
247 OPC_LHU = 045 << 26,
248 OPC_LWR = 046 << 26,
249 OPC_LWU = 047 << 26,
250 OPC_SB = 050 << 26,
251 OPC_SH = 051 << 26,
252 OPC_SWL = 052 << 26,
253 OPC_SW = 053 << 26,
254 OPC_SDL = 054 << 26,
255 OPC_SDR = 055 << 26,
256 OPC_SWR = 056 << 26,
257 OPC_LD = 067 << 26,
258 OPC_SD = 077 << 26,
260 OPC_SPECIAL = 000 << 26,
261 OPC_SLL = OPC_SPECIAL | 000,
262 OPC_SRL = OPC_SPECIAL | 002,
263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
264 OPC_SRA = OPC_SPECIAL | 003,
265 OPC_SLLV = OPC_SPECIAL | 004,
266 OPC_SRLV = OPC_SPECIAL | 006,
267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
268 OPC_SRAV = OPC_SPECIAL | 007,
269 OPC_JR_R5 = OPC_SPECIAL | 010,
270 OPC_JALR = OPC_SPECIAL | 011,
271 OPC_MOVZ = OPC_SPECIAL | 012,
272 OPC_MOVN = OPC_SPECIAL | 013,
273 OPC_SYNC = OPC_SPECIAL | 017,
274 OPC_MFHI = OPC_SPECIAL | 020,
275 OPC_MFLO = OPC_SPECIAL | 022,
276 OPC_DSLLV = OPC_SPECIAL | 024,
277 OPC_DSRLV = OPC_SPECIAL | 026,
278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
279 OPC_DSRAV = OPC_SPECIAL | 027,
280 OPC_MULT = OPC_SPECIAL | 030,
281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
282 OPC_MUH = OPC_SPECIAL | 030 | 0300,
283 OPC_MULTU = OPC_SPECIAL | 031,
284 OPC_MULU = OPC_SPECIAL | 031 | 0200,
285 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
286 OPC_DIV = OPC_SPECIAL | 032,
287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
288 OPC_MOD = OPC_SPECIAL | 032 | 0300,
289 OPC_DIVU = OPC_SPECIAL | 033,
290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
291 OPC_MODU = OPC_SPECIAL | 033 | 0300,
292 OPC_DMULT = OPC_SPECIAL | 034,
293 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
294 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
295 OPC_DMULTU = OPC_SPECIAL | 035,
296 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
298 OPC_DDIV = OPC_SPECIAL | 036,
299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
300 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
301 OPC_DDIVU = OPC_SPECIAL | 037,
302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
303 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
304 OPC_ADDU = OPC_SPECIAL | 041,
305 OPC_SUBU = OPC_SPECIAL | 043,
306 OPC_AND = OPC_SPECIAL | 044,
307 OPC_OR = OPC_SPECIAL | 045,
308 OPC_XOR = OPC_SPECIAL | 046,
309 OPC_NOR = OPC_SPECIAL | 047,
310 OPC_SLT = OPC_SPECIAL | 052,
311 OPC_SLTU = OPC_SPECIAL | 053,
312 OPC_DADDU = OPC_SPECIAL | 055,
313 OPC_DSUBU = OPC_SPECIAL | 057,
314 OPC_SELEQZ = OPC_SPECIAL | 065,
315 OPC_SELNEZ = OPC_SPECIAL | 067,
316 OPC_DSLL = OPC_SPECIAL | 070,
317 OPC_DSRL = OPC_SPECIAL | 072,
318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
319 OPC_DSRA = OPC_SPECIAL | 073,
320 OPC_DSLL32 = OPC_SPECIAL | 074,
321 OPC_DSRL32 = OPC_SPECIAL | 076,
322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
323 OPC_DSRA32 = OPC_SPECIAL | 077,
324 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
327 OPC_REGIMM = 001 << 26,
328 OPC_BLTZ = OPC_REGIMM | (000 << 16),
329 OPC_BGEZ = OPC_REGIMM | (001 << 16),
331 OPC_SPECIAL2 = 034 << 26,
332 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
333 OPC_CLZ = OPC_SPECIAL2 | 040,
334 OPC_DCLZ = OPC_SPECIAL2 | 044,
336 OPC_SPECIAL3 = 037 << 26,
337 OPC_EXT = OPC_SPECIAL3 | 000,
338 OPC_DEXTM = OPC_SPECIAL3 | 001,
339 OPC_DEXTU = OPC_SPECIAL3 | 002,
340 OPC_DEXT = OPC_SPECIAL3 | 003,
341 OPC_INS = OPC_SPECIAL3 | 004,
342 OPC_DINSM = OPC_SPECIAL3 | 005,
343 OPC_DINSU = OPC_SPECIAL3 | 006,
344 OPC_DINS = OPC_SPECIAL3 | 007,
345 OPC_WSBH = OPC_SPECIAL3 | 00240,
346 OPC_DSBH = OPC_SPECIAL3 | 00244,
347 OPC_DSHD = OPC_SPECIAL3 | 00544,
348 OPC_SEB = OPC_SPECIAL3 | 02040,
349 OPC_SEH = OPC_SPECIAL3 | 03040,
351 /* MIPS r6 doesn't have JR, JALR should be used instead */
352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
354 /*
355 * MIPS r6 replaces MUL with an alternative encoding which is
356 * backwards-compatible at the assembly level.
357 */
358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
360 /* MIPS r6 introduced names for weaker variants of SYNC. These are
361 backward compatible to previous architecture revisions. */
362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
368 /* Aliases for convenience. */
369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
371 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
372 ? OPC_SRL : OPC_DSRL,
373 } MIPSInsn;
375 /*
376 * Type reg
377 */
378 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
379 TCGReg rd, TCGReg rs, TCGReg rt)
380 {
381 int32_t inst;
383 inst = opc;
384 inst |= (rs & 0x1F) << 21;
385 inst |= (rt & 0x1F) << 16;
386 inst |= (rd & 0x1F) << 11;
387 tcg_out32(s, inst);
388 }
390 /*
391 * Type immediate
392 */
393 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
394 TCGReg rt, TCGReg rs, TCGArg imm)
395 {
396 int32_t inst;
398 inst = opc;
399 inst |= (rs & 0x1F) << 21;
400 inst |= (rt & 0x1F) << 16;
401 inst |= (imm & 0xffff);
402 tcg_out32(s, inst);
403 }
405 /*
406 * Type bitfield
407 */
408 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
409 TCGReg rs, int msb, int lsb)
410 {
411 int32_t inst;
413 inst = opc;
414 inst |= (rs & 0x1F) << 21;
415 inst |= (rt & 0x1F) << 16;
416 inst |= (msb & 0x1F) << 11;
417 inst |= (lsb & 0x1F) << 6;
418 tcg_out32(s, inst);
419 }
421 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
422 MIPSInsn oph, TCGReg rt, TCGReg rs,
423 int msb, int lsb)
424 {
425 if (lsb >= 32) {
426 opc = oph;
427 msb -= 32;
428 lsb -= 32;
429 } else if (msb >= 32) {
430 opc = opm;
431 msb -= 32;
432 }
433 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
434 }
436 /*
437 * Type branch
438 */
439 static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
440 {
441 tcg_out_opc_imm(s, opc, rt, rs, 0);
442 }
444 /*
445 * Type sa
446 */
447 static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
448 TCGReg rd, TCGReg rt, TCGArg sa)
449 {
450 int32_t inst;
452 inst = opc;
453 inst |= (rt & 0x1F) << 16;
454 inst |= (rd & 0x1F) << 11;
455 inst |= (sa & 0x1F) << 6;
456 tcg_out32(s, inst);
458 }
460 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
461 TCGReg rd, TCGReg rt, TCGArg sa)
462 {
463 int32_t inst;
465 inst = (sa & 32 ? opc2 : opc1);
466 inst |= (rt & 0x1F) << 16;
467 inst |= (rd & 0x1F) << 11;
468 inst |= (sa & 0x1F) << 6;
469 tcg_out32(s, inst);
470 }
472 /*
473 * Type jump.
474 * Returns true if the branch was in range and the insn was emitted.
475 */
476 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
477 {
478 uintptr_t dest = (uintptr_t)target;
479 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
480 int32_t inst;
482 /* The pc-region branch happens within the 256MB region of
483 the delay slot (thus the +4). */
484 if ((from ^ dest) & -(1 << 28)) {
485 return false;
486 }
487 tcg_debug_assert((dest & 3) == 0);
489 inst = opc;
490 inst |= (dest >> 2) & 0x3ffffff;
491 tcg_out32(s, inst);
492 return true;
493 }
495 static void tcg_out_nop(TCGContext *s)
496 {
497 tcg_out32(s, 0);
498 }
500 static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
501 {
502 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
503 }
505 static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
506 {
507 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
508 }
510 static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
511 {
512 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
513 }
515 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
516 {
517 /* Simple reg-reg move, optimising out the 'do nothing' case */
518 if (ret != arg) {
519 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
520 }
521 return true;
522 }
524 static void tcg_out_movi(TCGContext *s, TCGType type,
525 TCGReg ret, tcg_target_long arg)
526 {
527 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
528 arg = (int32_t)arg;
529 }
530 if (arg == (int16_t)arg) {
531 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
532 return;
533 }
534 if (arg == (uint16_t)arg) {
535 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
536 return;
537 }
538 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
539 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
540 } else {
541 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
542 if (arg & 0xffff0000ull) {
543 tcg_out_dsll(s, ret, ret, 16);
544 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
545 tcg_out_dsll(s, ret, ret, 16);
546 } else {
547 tcg_out_dsll(s, ret, ret, 32);
548 }
549 }
550 if (arg & 0xffff) {
551 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
552 }
553 }
555 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
556 tcg_target_long imm)
557 {
558 /* This function is only used for passing structs by reference. */
559 g_assert_not_reached();
560 }
562 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
563 {
564 /* ret and arg can't be register tmp0 */
565 tcg_debug_assert(ret != TCG_TMP0);
566 tcg_debug_assert(arg != TCG_TMP0);
568 /* With arg = abcd: */
569 if (use_mips32r2_instructions) {
570 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
571 if (flags & TCG_BSWAP_OS) {
572 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
573 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
574 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
575 }
576 return;
577 }
579 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
580 if (!(flags & TCG_BSWAP_IZ)) {
581 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
582 }
583 if (flags & TCG_BSWAP_OS) {
584 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
585 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
586 } else {
587 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
588 if (flags & TCG_BSWAP_OZ) {
589 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
590 }
591 }
592 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
593 }
595 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
596 {
597 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
598 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
599 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
600 }
601 }
603 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
604 {
605 if (use_mips32r2_instructions) {
606 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
607 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
608 if (flags & TCG_BSWAP_OZ) {
609 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
610 }
611 } else {
612 if (flags & TCG_BSWAP_OZ) {
613 tcg_out_bswap_subr(s, bswap32u_addr);
614 } else {
615 tcg_out_bswap_subr(s, bswap32_addr);
616 }
617 /* delay slot -- never omit the insn, like tcg_out_mov might. */
618 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
619 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
620 }
621 }
623 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
624 {
625 if (use_mips32r2_instructions) {
626 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
627 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
628 } else {
629 tcg_out_bswap_subr(s, bswap64_addr);
630 /* delay slot -- never omit the insn, like tcg_out_mov might. */
631 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
632 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
633 }
634 }
636 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
637 {
638 if (use_mips32r2_instructions) {
639 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
640 } else {
641 tcg_out_dsll(s, ret, arg, 32);
642 tcg_out_dsrl(s, ret, ret, 32);
643 }
644 }
646 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
647 TCGReg addr, intptr_t ofs)
648 {
649 int16_t lo = ofs;
650 if (ofs != lo) {
651 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
652 if (addr != TCG_REG_ZERO) {
653 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
654 }
655 addr = TCG_TMP0;
656 }
657 tcg_out_opc_imm(s, opc, data, addr, lo);
658 }
660 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
661 TCGReg arg1, intptr_t arg2)
662 {
663 MIPSInsn opc = OPC_LD;
664 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
665 opc = OPC_LW;
666 }
667 tcg_out_ldst(s, opc, arg, arg1, arg2);
668 }
670 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
671 TCGReg arg1, intptr_t arg2)
672 {
673 MIPSInsn opc = OPC_SD;
674 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
675 opc = OPC_SW;
676 }
677 tcg_out_ldst(s, opc, arg, arg1, arg2);
678 }
680 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
681 TCGReg base, intptr_t ofs)
682 {
683 if (val == 0) {
684 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
685 return true;
686 }
687 return false;
688 }
690 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
691 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
692 bool cbh, bool is_sub)
693 {
694 TCGReg th = TCG_TMP1;
696 /* If we have a negative constant such that negating it would
697 make the high part zero, we can (usually) eliminate one insn. */
698 if (cbl && cbh && bh == -1 && bl != 0) {
699 bl = -bl;
700 bh = 0;
701 is_sub = !is_sub;
702 }
704 /* By operating on the high part first, we get to use the final
705 carry operation to move back from the temporary. */
706 if (!cbh) {
707 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
708 } else if (bh != 0 || ah == rl) {
709 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
710 } else {
711 th = ah;
712 }
714 /* Note that tcg optimization should eliminate the bl == 0 case. */
715 if (is_sub) {
716 if (cbl) {
717 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
718 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
719 } else {
720 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
721 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
722 }
723 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
724 } else {
725 if (cbl) {
726 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
727 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
728 } else if (rl == al && rl == bl) {
729 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
730 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
731 } else {
732 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
733 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
734 }
735 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
736 }
737 }
739 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
740 #define MIPS_CMP_INV 1
741 #define MIPS_CMP_SWAP 2
743 static const uint8_t mips_cmp_map[16] = {
744 [TCG_COND_LT] = 0,
745 [TCG_COND_LTU] = 0,
746 [TCG_COND_GE] = MIPS_CMP_INV,
747 [TCG_COND_GEU] = MIPS_CMP_INV,
748 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
749 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
750 [TCG_COND_GT] = MIPS_CMP_SWAP,
751 [TCG_COND_GTU] = MIPS_CMP_SWAP,
752 };
754 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
755 TCGReg arg1, TCGReg arg2)
756 {
757 MIPSInsn s_opc = OPC_SLTU;
758 int cmp_map;
760 switch (cond) {
761 case TCG_COND_EQ:
762 if (arg2 != 0) {
763 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
764 arg1 = ret;
765 }
766 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
767 break;
769 case TCG_COND_NE:
770 if (arg2 != 0) {
771 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
772 arg1 = ret;
773 }
774 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
775 break;
777 case TCG_COND_LT:
778 case TCG_COND_GE:
779 case TCG_COND_LE:
780 case TCG_COND_GT:
781 s_opc = OPC_SLT;
782 /* FALLTHRU */
784 case TCG_COND_LTU:
785 case TCG_COND_GEU:
786 case TCG_COND_LEU:
787 case TCG_COND_GTU:
788 cmp_map = mips_cmp_map[cond];
789 if (cmp_map & MIPS_CMP_SWAP) {
790 TCGReg t = arg1;
791 arg1 = arg2;
792 arg2 = t;
793 }
794 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
795 if (cmp_map & MIPS_CMP_INV) {
796 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
797 }
798 break;
800 default:
801 tcg_abort();
802 break;
803 }
804 }
806 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
807 TCGReg arg2, TCGLabel *l)
808 {
809 static const MIPSInsn b_zero[16] = {
810 [TCG_COND_LT] = OPC_BLTZ,
811 [TCG_COND_GT] = OPC_BGTZ,
812 [TCG_COND_LE] = OPC_BLEZ,
813 [TCG_COND_GE] = OPC_BGEZ,
814 };
816 MIPSInsn s_opc = OPC_SLTU;
817 MIPSInsn b_opc;
818 int cmp_map;
820 switch (cond) {
821 case TCG_COND_EQ:
822 b_opc = OPC_BEQ;
823 break;
824 case TCG_COND_NE:
825 b_opc = OPC_BNE;
826 break;
828 case TCG_COND_LT:
829 case TCG_COND_GT:
830 case TCG_COND_LE:
831 case TCG_COND_GE:
832 if (arg2 == 0) {
833 b_opc = b_zero[cond];
834 arg2 = arg1;
835 arg1 = 0;
836 break;
837 }
838 s_opc = OPC_SLT;
839 /* FALLTHRU */
841 case TCG_COND_LTU:
842 case TCG_COND_GTU:
843 case TCG_COND_LEU:
844 case TCG_COND_GEU:
845 cmp_map = mips_cmp_map[cond];
846 if (cmp_map & MIPS_CMP_SWAP) {
847 TCGReg t = arg1;
848 arg1 = arg2;
849 arg2 = t;
850 }
851 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
852 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
853 arg1 = TCG_TMP0;
854 arg2 = TCG_REG_ZERO;
855 break;
857 default:
858 tcg_abort();
859 break;
860 }
862 tcg_out_opc_br(s, b_opc, arg1, arg2);
863 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
864 tcg_out_nop(s);
865 }
867 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
868 TCGReg al, TCGReg ah,
869 TCGReg bl, TCGReg bh)
870 {
871 /* Merge highpart comparison into AH. */
872 if (bh != 0) {
873 if (ah != 0) {
874 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
875 ah = tmp0;
876 } else {
877 ah = bh;
878 }
879 }
880 /* Merge lowpart comparison into AL. */
881 if (bl != 0) {
882 if (al != 0) {
883 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
884 al = tmp1;
885 } else {
886 al = bl;
887 }
888 }
889 /* Merge high and low part comparisons into AL. */
890 if (ah != 0) {
891 if (al != 0) {
892 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
893 al = tmp0;
894 } else {
895 al = ah;
896 }
897 }
898 return al;
899 }
901 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
902 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
903 {
904 TCGReg tmp0 = TCG_TMP0;
905 TCGReg tmp1 = ret;
907 tcg_debug_assert(ret != TCG_TMP0);
908 if (ret == ah || ret == bh) {
909 tcg_debug_assert(ret != TCG_TMP1);
910 tmp1 = TCG_TMP1;
911 }
913 switch (cond) {
914 case TCG_COND_EQ:
915 case TCG_COND_NE:
916 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
917 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
918 break;
920 default:
921 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
922 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
923 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
924 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
925 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
926 break;
927 }
928 }
930 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
931 TCGReg bl, TCGReg bh, TCGLabel *l)
932 {
933 TCGCond b_cond = TCG_COND_NE;
934 TCGReg tmp = TCG_TMP1;
936 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
937 With setcond, we emit between 3 and 10 insns and only 1 branch,
938 which ought to get better branch prediction. */
939 switch (cond) {
940 case TCG_COND_EQ:
941 case TCG_COND_NE:
942 b_cond = cond;
943 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
944 break;
946 default:
947 /* Minimize code size by preferring a compare not requiring INV. */
948 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
949 cond = tcg_invert_cond(cond);
950 b_cond = TCG_COND_EQ;
951 }
952 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
953 break;
954 }
956 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
957 }
959 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
960 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
961 {
962 bool eqz = false;
964 /* If one of the values is zero, put it last to match SEL*Z instructions */
965 if (use_mips32r6_instructions && v1 == 0) {
966 v1 = v2;
967 v2 = 0;
968 cond = tcg_invert_cond(cond);
969 }
971 switch (cond) {
972 case TCG_COND_EQ:
973 eqz = true;
974 /* FALLTHRU */
975 case TCG_COND_NE:
976 if (c2 != 0) {
977 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
978 c1 = TCG_TMP0;
979 }
980 break;
982 default:
983 /* Minimize code size by preferring a compare not requiring INV. */
984 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
985 cond = tcg_invert_cond(cond);
986 eqz = true;
987 }
988 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
989 c1 = TCG_TMP0;
990 break;
991 }
993 if (use_mips32r6_instructions) {
994 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
995 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
997 if (v2 != 0) {
998 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
999 }
1000 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1001 if (v2 != 0) {
1002 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1003 }
1004 } else {
1005 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1007 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1009 /* This should be guaranteed via constraints */
1010 tcg_debug_assert(v2 == ret);
1011 }
1012 }
1014 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
1015 {
1016 /* Note that the ABI requires the called function's address to be
1017 loaded into T9, even if a direct branch is in range. */
1018 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1020 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1021 if (tail) {
1022 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1023 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1024 }
1025 } else {
1026 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1027 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1028 }
1029 }
1030 }
1032 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1033 const TCGHelperInfo *info)
1034 {
1035 tcg_out_call_int(s, arg, false);
1036 tcg_out_nop(s);
1037 }
1039 #if defined(CONFIG_SOFTMMU)
1040 static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
1041 [MO_UB] = helper_ret_ldub_mmu,
1042 [MO_SB] = helper_ret_ldsb_mmu,
1043 [MO_LEUW] = helper_le_lduw_mmu,
1044 [MO_LESW] = helper_le_ldsw_mmu,
1045 [MO_LEUL] = helper_le_ldul_mmu,
1046 [MO_LEUQ] = helper_le_ldq_mmu,
1047 [MO_BEUW] = helper_be_lduw_mmu,
1048 [MO_BESW] = helper_be_ldsw_mmu,
1049 [MO_BEUL] = helper_be_ldul_mmu,
1050 [MO_BEUQ] = helper_be_ldq_mmu,
1051 #if TCG_TARGET_REG_BITS == 64
1052 [MO_LESL] = helper_le_ldsl_mmu,
1053 [MO_BESL] = helper_be_ldsl_mmu,
1054 #endif
1055 };
1057 static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
1058 [MO_UB] = helper_ret_stb_mmu,
1059 [MO_LEUW] = helper_le_stw_mmu,
1060 [MO_LEUL] = helper_le_stl_mmu,
1061 [MO_LEUQ] = helper_le_stq_mmu,
1062 [MO_BEUW] = helper_be_stw_mmu,
1063 [MO_BEUL] = helper_be_stl_mmu,
1064 [MO_BEUQ] = helper_be_stq_mmu,
1065 };
1067 /* Helper routines for marshalling helper function arguments into
1068 * the correct registers and stack.
1069 * I is where we want to put this argument, and is updated and returned
1070 * for the next call. ARG is the argument itself.
1071 *
1072 * We provide routines for arguments which are: immediate, 32 bit
1073 * value in register, 16 and 8 bit values in register (which must be zero
1074 * extended before use) and 64 bit value in a lo:hi register pair.
1075 */
1077 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1078 {
1079 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1080 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1081 } else {
1082 /* For N32 and N64, the initial offset is different. But there
1083 we also have 8 argument register so we don't run out here. */
1084 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1085 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1086 }
1087 return i + 1;
1088 }
1090 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1091 {
1092 TCGReg tmp = TCG_TMP0;
1093 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1094 tmp = tcg_target_call_iarg_regs[i];
1095 }
1096 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1097 return tcg_out_call_iarg_reg(s, i, tmp);
1098 }
1100 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1101 {
1102 TCGReg tmp = TCG_TMP0;
1103 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1104 tmp = tcg_target_call_iarg_regs[i];
1105 }
1106 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1107 return tcg_out_call_iarg_reg(s, i, tmp);
1108 }
1110 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1111 {
1112 TCGReg tmp = TCG_TMP0;
1113 if (arg == 0) {
1114 tmp = TCG_REG_ZERO;
1115 } else {
1116 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1117 tmp = tcg_target_call_iarg_regs[i];
1118 }
1119 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1120 }
1121 return tcg_out_call_iarg_reg(s, i, tmp);
1122 }
1124 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1125 {
1126 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1127 i = (i + 1) & ~1;
1128 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1129 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1130 return i;
1131 }
1133 /* We expect to use a 16-bit negative offset from ENV. */
1134 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1135 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1137 /*
1138 * Perform the tlb comparison operation.
1139 * The complete host address is placed in BASE.
1140 * Clobbers TMP0, TMP1, TMP2, TMP3.
1141 */
1142 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1143 TCGReg addrh, MemOpIdx oi,
1144 tcg_insn_unit *label_ptr[2], bool is_load)
1145 {
1146 MemOp opc = get_memop(oi);
1147 unsigned a_bits = get_alignment_bits(opc);
1148 unsigned s_bits = opc & MO_SIZE;
1149 unsigned a_mask = (1 << a_bits) - 1;
1150 unsigned s_mask = (1 << s_bits) - 1;
1151 int mem_index = get_mmuidx(oi);
1152 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1153 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1154 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1155 int add_off = offsetof(CPUTLBEntry, addend);
1156 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1157 : offsetof(CPUTLBEntry, addr_write));
1158 target_ulong tlb_mask;
1160 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1161 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1162 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1164 /* Extract the TLB index from the address into TMP3. */
1165 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1166 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1167 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1169 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1170 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1172 /* Load the (low-half) tlb comparator. */
1173 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1174 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
1175 } else {
1176 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1177 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1178 TCG_TMP0, TCG_TMP3, cmp_off);
1179 }
1181 /* Zero extend a 32-bit guest address for a 64-bit host. */
1182 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1183 tcg_out_ext32u(s, base, addrl);
1184 addrl = base;
1185 }
1187 /*
1188 * Mask the page bits, keeping the alignment bits to compare against.
1189 * For unaligned accesses, compare against the end of the access to
1190 * verify that it does not cross a page boundary.
1191 */
1192 tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
1193 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask);
1194 if (a_mask >= s_mask) {
1195 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1196 } else {
1197 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask);
1198 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
1199 }
1201 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1202 /* Load the tlb addend for the fast path. */
1203 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1204 }
1206 label_ptr[0] = s->code_ptr;
1207 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1209 /* Load and test the high half tlb comparator. */
1210 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1211 /* delay slot */
1212 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1214 /* Load the tlb addend for the fast path. */
1215 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1217 label_ptr[1] = s->code_ptr;
1218 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1219 }
1221 /* delay slot */
1222 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1223 }
1225 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
1226 TCGType ext,
1227 TCGReg datalo, TCGReg datahi,
1228 TCGReg addrlo, TCGReg addrhi,
1229 void *raddr, tcg_insn_unit *label_ptr[2])
1230 {
1231 TCGLabelQemuLdst *label = new_ldst_label(s);
1233 label->is_ld = is_ld;
1234 label->oi = oi;
1235 label->type = ext;
1236 label->datalo_reg = datalo;
1237 label->datahi_reg = datahi;
1238 label->addrlo_reg = addrlo;
1239 label->addrhi_reg = addrhi;
1240 label->raddr = tcg_splitwx_to_rx(raddr);
1241 label->label_ptr[0] = label_ptr[0];
1242 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1243 label->label_ptr[1] = label_ptr[1];
1244 }
1245 }
1247 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1248 {
1249 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1250 MemOpIdx oi = l->oi;
1251 MemOp opc = get_memop(oi);
1252 TCGReg v0;
1253 int i;
1255 /* resolve label address */
1256 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1257 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1258 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1259 return false;
1260 }
1262 i = 1;
1263 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1264 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1265 } else {
1266 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1267 }
1268 i = tcg_out_call_iarg_imm(s, i, oi);
1269 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1270 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1271 /* delay slot */
1272 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1274 v0 = l->datalo_reg;
1275 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1276 /* We eliminated V0 from the possible output registers, so it
1277 cannot be clobbered here. So we must move V1 first. */
1278 if (MIPS_BE) {
1279 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1280 v0 = l->datahi_reg;
1281 } else {
1282 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1283 }
1284 }
1286 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1287 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1288 return false;
1289 }
1291 /* delay slot */
1292 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1293 /* we always sign-extend 32-bit loads */
1294 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1295 } else {
1296 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1297 }
1298 return true;
1299 }
1301 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1302 {
1303 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1304 MemOpIdx oi = l->oi;
1305 MemOp opc = get_memop(oi);
1306 MemOp s_bits = opc & MO_SIZE;
1307 int i;
1309 /* resolve label address */
1310 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1311 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS
1312 && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1313 return false;
1314 }
1316 i = 1;
1317 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1318 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1319 } else {
1320 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1321 }
1322 switch (s_bits) {
1323 case MO_8:
1324 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1325 break;
1326 case MO_16:
1327 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1328 break;
1329 case MO_32:
1330 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1331 break;
1332 case MO_64:
1333 if (TCG_TARGET_REG_BITS == 32) {
1334 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1335 } else {
1336 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1337 }
1338 break;
1339 default:
1340 tcg_abort();
1341 }
1342 i = tcg_out_call_iarg_imm(s, i, oi);
1344 /* Tail call to the store helper. Thus force the return address
1345 computation to take place in the return address register. */
1346 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1347 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1348 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1349 /* delay slot */
1350 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1351 return true;
1352 }
1354 #else
1356 static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
1357 TCGReg addrhi, unsigned a_bits)
1358 {
1359 unsigned a_mask = (1 << a_bits) - 1;
1360 TCGLabelQemuLdst *l = new_ldst_label(s);
1362 l->is_ld = is_ld;
1363 l->addrlo_reg = addrlo;
1364 l->addrhi_reg = addrhi;
1366 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
1367 tcg_debug_assert(a_bits < 16);
1368 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
1370 l->label_ptr[0] = s->code_ptr;
1371 if (use_mips32r6_instructions) {
1372 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
1373 } else {
1374 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
1375 tcg_out_nop(s);
1376 }
1378 l->raddr = tcg_splitwx_to_rx(s->code_ptr);
1379 }
1381 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
1382 {
1383 void *target;
1385 if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1386 return false;
1387 }
1389 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1390 /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */
1391 TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg;
1392 TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg;
1394 if (a3 != TCG_REG_A2) {
1395 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1396 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1397 } else if (a2 != TCG_REG_A3) {
1398 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3);
1399 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2);
1400 } else {
1401 tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2);
1402 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3);
1403 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0);
1404 }
1405 } else {
1406 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg);
1407 }
1408 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0);
1410 /*
1411 * Tail call to the helper, with the return address back inline.
1412 * We have arrived here via BNEL, so $31 is already set.
1413 */
1414 target = (l->is_ld ? helper_unaligned_ld : helper_unaligned_st);
1415 tcg_out_call_int(s, target, true);
1416 return true;
1417 }
1419 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1420 {
1421 return tcg_out_fail_alignment(s, l);
1422 }
1424 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1425 {
1426 return tcg_out_fail_alignment(s, l);
1427 }
1428 #endif /* SOFTMMU */
1430 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1431 TCGReg base, MemOp opc, bool is_64)
1432 {
1433 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1434 case MO_UB:
1435 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1436 break;
1437 case MO_SB:
1438 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1439 break;
1440 case MO_UW | MO_BSWAP:
1441 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1442 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1443 break;
1444 case MO_UW:
1445 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1446 break;
1447 case MO_SW | MO_BSWAP:
1448 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1449 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS);
1450 break;
1451 case MO_SW:
1452 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1453 break;
1454 case MO_UL | MO_BSWAP:
1455 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1456 if (use_mips32r2_instructions) {
1457 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1458 tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
1459 } else {
1460 tcg_out_bswap_subr(s, bswap32u_addr);
1461 /* delay slot */
1462 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1463 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1464 }
1465 break;
1466 }
1467 /* FALLTHRU */
1468 case MO_SL | MO_BSWAP:
1469 if (use_mips32r2_instructions) {
1470 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1471 tcg_out_bswap32(s, lo, lo, 0);
1472 } else {
1473 tcg_out_bswap_subr(s, bswap32_addr);
1474 /* delay slot */
1475 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1476 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1477 }
1478 break;
1479 case MO_UL:
1480 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1481 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1482 break;
1483 }
1484 /* FALLTHRU */
1485 case MO_SL:
1486 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1487 break;
1488 case MO_UQ | MO_BSWAP:
1489 if (TCG_TARGET_REG_BITS == 64) {
1490 if (use_mips32r2_instructions) {
1491 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1492 tcg_out_bswap64(s, lo, lo);
1493 } else {
1494 tcg_out_bswap_subr(s, bswap64_addr);
1495 /* delay slot */
1496 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1497 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1498 }
1499 } else if (use_mips32r2_instructions) {
1500 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1501 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1502 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1503 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1504 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1505 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1506 } else {
1507 tcg_out_bswap_subr(s, bswap32_addr);
1508 /* delay slot */
1509 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1510 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1511 tcg_out_bswap_subr(s, bswap32_addr);
1512 /* delay slot */
1513 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1514 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1515 }
1516 break;
1517 case MO_UQ:
1518 /* Prefer to load from offset 0 first, but allow for overlap. */
1519 if (TCG_TARGET_REG_BITS == 64) {
1520 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1521 } else if (MIPS_BE ? hi != base : lo == base) {
1522 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1523 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1524 } else {
1525 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1526 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1527 }
1528 break;
1529 default:
1530 tcg_abort();
1531 }
1532 }
1534 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1535 TCGReg base, MemOp opc, bool is_64)
1536 {
1537 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR;
1538 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL;
1539 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR;
1540 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL;
1542 bool sgn = (opc & MO_SIGN);
1544 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1545 case MO_SW | MO_BE:
1546 case MO_UW | MO_BE:
1547 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0);
1548 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1);
1549 if (use_mips32r2_instructions) {
1550 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1551 } else {
1552 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
1553 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1554 }
1555 break;
1557 case MO_SW | MO_LE:
1558 case MO_UW | MO_LE:
1559 if (use_mips32r2_instructions && lo != base) {
1560 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1561 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1);
1562 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1563 } else {
1564 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0);
1565 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1);
1566 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8);
1567 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1568 }
1569 break;
1571 case MO_SL:
1572 case MO_UL:
1573 tcg_out_opc_imm(s, lw1, lo, base, 0);
1574 tcg_out_opc_imm(s, lw2, lo, base, 3);
1575 if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) {
1576 tcg_out_ext32u(s, lo, lo);
1577 }
1578 break;
1580 case MO_UL | MO_BSWAP:
1581 case MO_SL | MO_BSWAP:
1582 if (use_mips32r2_instructions) {
1583 tcg_out_opc_imm(s, lw1, lo, base, 0);
1584 tcg_out_opc_imm(s, lw2, lo, base, 3);
1585 tcg_out_bswap32(s, lo, lo,
1586 TCG_TARGET_REG_BITS == 64 && is_64
1587 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0);
1588 } else {
1589 const tcg_insn_unit *subr =
1590 (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn
1591 ? bswap32u_addr : bswap32_addr);
1593 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0);
1594 tcg_out_bswap_subr(s, subr);
1595 /* delay slot */
1596 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3);
1597 tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3);
1598 }
1599 break;
1601 case MO_UQ:
1602 if (TCG_TARGET_REG_BITS == 64) {
1603 tcg_out_opc_imm(s, ld1, lo, base, 0);
1604 tcg_out_opc_imm(s, ld2, lo, base, 7);
1605 } else {
1606 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0);
1607 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3);
1608 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0);
1609 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3);
1610 }
1611 break;
1613 case MO_UQ | MO_BSWAP:
1614 if (TCG_TARGET_REG_BITS == 64) {
1615 if (use_mips32r2_instructions) {
1616 tcg_out_opc_imm(s, ld1, lo, base, 0);
1617 tcg_out_opc_imm(s, ld2, lo, base, 7);
1618 tcg_out_bswap64(s, lo, lo);
1619 } else {
1620 tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0);
1621 tcg_out_bswap_subr(s, bswap64_addr);
1622 /* delay slot */
1623 tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7);
1624 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1625 }
1626 } else if (use_mips32r2_instructions) {
1627 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0);
1628 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3);
1629 tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0);
1630 tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3);
1631 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1632 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1633 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1634 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1635 } else {
1636 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0);
1637 tcg_out_bswap_subr(s, bswap32_addr);
1638 /* delay slot */
1639 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3);
1640 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0);
1641 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1642 tcg_out_bswap_subr(s, bswap32_addr);
1643 /* delay slot */
1644 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3);
1645 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1646 }
1647 break;
1649 default:
1650 g_assert_not_reached();
1651 }
1652 }
1654 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1655 {
1656 TCGReg addr_regl, addr_regh __attribute__((unused));
1657 TCGReg data_regl, data_regh;
1658 MemOpIdx oi;
1659 MemOp opc;
1660 #if defined(CONFIG_SOFTMMU)
1661 tcg_insn_unit *label_ptr[2];
1662 #else
1663 #endif
1664 unsigned a_bits, s_bits;
1665 TCGReg base = TCG_REG_A0;
1667 data_regl = *args++;
1668 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1669 addr_regl = *args++;
1670 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1671 oi = *args++;
1672 opc = get_memop(oi);
1673 a_bits = get_alignment_bits(opc);
1674 s_bits = opc & MO_SIZE;
1676 /*
1677 * R6 removes the left/right instructions but requires the
1678 * system to support misaligned memory accesses.
1679 */
1680 #if defined(CONFIG_SOFTMMU)
1681 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1682 if (use_mips32r6_instructions || a_bits >= s_bits) {
1683 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1684 } else {
1685 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
1686 }
1687 add_qemu_ldst_label(s, 1, oi,
1688 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1689 data_regl, data_regh, addr_regl, addr_regh,
1690 s->code_ptr, label_ptr);
1691 #else
1692 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1693 tcg_out_ext32u(s, base, addr_regl);
1694 addr_regl = base;
1695 }
1696 if (guest_base == 0 && data_regl != addr_regl) {
1697 base = addr_regl;
1698 } else if (guest_base == (int16_t)guest_base) {
1699 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1700 } else {
1701 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1702 }
1703 if (use_mips32r6_instructions) {
1704 if (a_bits) {
1705 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1706 }
1707 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1708 } else {
1709 if (a_bits && a_bits != s_bits) {
1710 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1711 }
1712 if (a_bits >= s_bits) {
1713 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1714 } else {
1715 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64);
1716 }
1717 }
1718 #endif
1719 }
1721 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1722 TCGReg base, MemOp opc)
1723 {
1724 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1725 if ((lo | hi) == 0) {
1726 opc &= ~MO_BSWAP;
1727 }
1729 switch (opc & (MO_SIZE | MO_BSWAP)) {
1730 case MO_8:
1731 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1732 break;
1734 case MO_16 | MO_BSWAP:
1735 tcg_out_bswap16(s, TCG_TMP1, lo, 0);
1736 lo = TCG_TMP1;
1737 /* FALLTHRU */
1738 case MO_16:
1739 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1740 break;
1742 case MO_32 | MO_BSWAP:
1743 tcg_out_bswap32(s, TCG_TMP3, lo, 0);
1744 lo = TCG_TMP3;
1745 /* FALLTHRU */
1746 case MO_32:
1747 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1748 break;
1750 case MO_64 | MO_BSWAP:
1751 if (TCG_TARGET_REG_BITS == 64) {
1752 tcg_out_bswap64(s, TCG_TMP3, lo);
1753 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1754 } else if (use_mips32r2_instructions) {
1755 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1756 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1757 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1758 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1759 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1760 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1761 } else {
1762 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
1763 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1764 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
1765 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1766 }
1767 break;
1768 case MO_64:
1769 if (TCG_TARGET_REG_BITS == 64) {
1770 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1771 } else {
1772 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1773 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1774 }
1775 break;
1777 default:
1778 tcg_abort();
1779 }
1780 }
1782 static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1783 TCGReg base, MemOp opc)
1784 {
1785 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR;
1786 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL;
1787 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR;
1788 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL;
1790 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1791 if ((lo | hi) == 0) {
1792 opc &= ~MO_BSWAP;
1793 }
1795 switch (opc & (MO_SIZE | MO_BSWAP)) {
1796 case MO_16 | MO_BE:
1797 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1798 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0);
1799 tcg_out_opc_imm(s, OPC_SB, lo, base, 1);
1800 break;
1802 case MO_16 | MO_LE:
1803 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1804 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1805 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1);
1806 break;
1808 case MO_32 | MO_BSWAP:
1809 tcg_out_bswap32(s, TCG_TMP3, lo, 0);
1810 lo = TCG_TMP3;
1811 /* fall through */
1812 case MO_32:
1813 tcg_out_opc_imm(s, sw1, lo, base, 0);
1814 tcg_out_opc_imm(s, sw2, lo, base, 3);
1815 break;
1817 case MO_64 | MO_BSWAP:
1818 if (TCG_TARGET_REG_BITS == 64) {
1819 tcg_out_bswap64(s, TCG_TMP3, lo);
1820 lo = TCG_TMP3;
1821 } else if (use_mips32r2_instructions) {
1822 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo);
1823 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi);
1824 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1825 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1826 hi = MIPS_BE ? TCG_TMP0 : TCG_TMP1;
1827 lo = MIPS_BE ? TCG_TMP1 : TCG_TMP0;
1828 } else {
1829 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
1830 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0);
1831 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3);
1832 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
1833 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0);
1834 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3);
1835 break;
1836 }
1837 /* fall through */
1838 case MO_64:
1839 if (TCG_TARGET_REG_BITS == 64) {
1840 tcg_out_opc_imm(s, sd1, lo, base, 0);
1841 tcg_out_opc_imm(s, sd2, lo, base, 7);
1842 } else {
1843 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0);
1844 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3);
1845 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0);
1846 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3);
1847 }
1848 break;
1850 default:
1851 tcg_abort();
1852 }
1853 }
1854 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1855 {
1856 TCGReg addr_regl, addr_regh __attribute__((unused));
1857 TCGReg data_regl, data_regh;
1858 MemOpIdx oi;
1859 MemOp opc;
1860 #if defined(CONFIG_SOFTMMU)
1861 tcg_insn_unit *label_ptr[2];
1862 #endif
1863 unsigned a_bits, s_bits;
1864 TCGReg base = TCG_REG_A0;
1866 data_regl = *args++;
1867 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1868 addr_regl = *args++;
1869 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1870 oi = *args++;
1871 opc = get_memop(oi);
1872 a_bits = get_alignment_bits(opc);
1873 s_bits = opc & MO_SIZE;
1875 /*
1876 * R6 removes the left/right instructions but requires the
1877 * system to support misaligned memory accesses.
1878 */
1879 #if defined(CONFIG_SOFTMMU)
1880 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1881 if (use_mips32r6_instructions || a_bits >= s_bits) {
1882 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1883 } else {
1884 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
1885 }
1886 add_qemu_ldst_label(s, 0, oi,
1887 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1888 data_regl, data_regh, addr_regl, addr_regh,
1889 s->code_ptr, label_ptr);
1890 #else
1891 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1892 tcg_out_ext32u(s, base, addr_regl);
1893 addr_regl = base;
1894 }
1895 if (guest_base == 0) {
1896 base = addr_regl;
1897 } else if (guest_base == (int16_t)guest_base) {
1898 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1899 } else {
1900 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1901 }
1902 if (use_mips32r6_instructions) {
1903 if (a_bits) {
1904 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1905 }
1906 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1907 } else {
1908 if (a_bits && a_bits != s_bits) {
1909 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits);
1910 }
1911 if (a_bits >= s_bits) {
1912 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1913 } else {
1914 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc);
1915 }
1916 }
1917 #endif
1918 }
1920 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1921 {
1922 static const MIPSInsn sync[] = {
1923 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1924 as the former is an ordering barrier and the latter
1925 is a completion barrier. */
1926 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1927 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1928 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1929 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1930 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1931 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1932 };
1933 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1934 }
1936 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1937 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1938 {
1939 if (use_mips32r6_instructions) {
1940 if (a2 == width) {
1941 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1942 } else {
1943 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1944 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1945 }
1946 } else {
1947 if (a2 == width) {
1948 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1949 } else if (a0 == a2) {
1950 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1951 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1952 } else if (a0 != a1) {
1953 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1954 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1955 } else {
1956 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1957 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1958 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1959 }
1960 }
1961 }
1963 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1964 {
1965 TCGReg b0 = TCG_REG_ZERO;
1967 if (a0 & ~0xffff) {
1968 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1969 b0 = TCG_REG_V0;
1970 }
1971 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1972 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
1973 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1974 }
1975 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1976 }
1978 static void tcg_out_goto_tb(TCGContext *s, int which)
1979 {
1980 /* indirect jump method */
1981 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1982 get_jmp_target_addr(s, which));
1983 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1984 tcg_out_nop(s);
1985 set_jmp_reset_offset(s, which);
1986 }
1988 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1989 uintptr_t jmp_rx, uintptr_t jmp_rw)
1990 {
1991 /* Always indirect, nothing to do */
1992 }
1994 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1995 const TCGArg args[TCG_MAX_OP_ARGS],
1996 const int const_args[TCG_MAX_OP_ARGS])
1997 {
1998 MIPSInsn i1, i2;
1999 TCGArg a0, a1, a2;
2000 int c2;
2002 /*
2003 * Note that many operands use the constraint set "rZ".
2004 * We make use of the fact that 0 is the ZERO register,
2005 * and hence such cases need not check for const_args.
2006 */
2007 a0 = args[0];
2008 a1 = args[1];
2009 a2 = args[2];
2010 c2 = const_args[2];
2012 switch (opc) {
2013 case INDEX_op_goto_ptr:
2014 /* jmp to the given host address (could be epilogue) */
2015 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
2016 tcg_out_nop(s);
2017 break;
2018 case INDEX_op_br:
2019 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
2020 arg_label(a0));
2021 break;
2023 case INDEX_op_ld8u_i32:
2024 case INDEX_op_ld8u_i64:
2025 i1 = OPC_LBU;
2026 goto do_ldst;
2027 case INDEX_op_ld8s_i32:
2028 case INDEX_op_ld8s_i64:
2029 i1 = OPC_LB;
2030 goto do_ldst;
2031 case INDEX_op_ld16u_i32:
2032 case INDEX_op_ld16u_i64:
2033 i1 = OPC_LHU;
2034 goto do_ldst;
2035 case INDEX_op_ld16s_i32:
2036 case INDEX_op_ld16s_i64:
2037 i1 = OPC_LH;
2038 goto do_ldst;
2039 case INDEX_op_ld_i32:
2040 case INDEX_op_ld32s_i64:
2041 i1 = OPC_LW;
2042 goto do_ldst;
2043 case INDEX_op_ld32u_i64:
2044 i1 = OPC_LWU;
2045 goto do_ldst;
2046 case INDEX_op_ld_i64:
2047 i1 = OPC_LD;
2048 goto do_ldst;
2049 case INDEX_op_st8_i32:
2050 case INDEX_op_st8_i64:
2051 i1 = OPC_SB;
2052 goto do_ldst;
2053 case INDEX_op_st16_i32:
2054 case INDEX_op_st16_i64:
2055 i1 = OPC_SH;
2056 goto do_ldst;
2057 case INDEX_op_st_i32:
2058 case INDEX_op_st32_i64:
2059 i1 = OPC_SW;
2060 goto do_ldst;
2061 case INDEX_op_st_i64:
2062 i1 = OPC_SD;
2063 do_ldst:
2064 tcg_out_ldst(s, i1, a0, a1, a2);
2065 break;
2067 case INDEX_op_add_i32:
2068 i1 = OPC_ADDU, i2 = OPC_ADDIU;
2069 goto do_binary;
2070 case INDEX_op_add_i64:
2071 i1 = OPC_DADDU, i2 = OPC_DADDIU;
2072 goto do_binary;
2073 case INDEX_op_or_i32:
2074 case INDEX_op_or_i64:
2075 i1 = OPC_OR, i2 = OPC_ORI;
2076 goto do_binary;
2077 case INDEX_op_xor_i32:
2078 case INDEX_op_xor_i64:
2079 i1 = OPC_XOR, i2 = OPC_XORI;
2080 do_binary:
2081 if (c2) {
2082 tcg_out_opc_imm(s, i2, a0, a1, a2);
2083 break;
2084 }
2085 do_binaryv:
2086 tcg_out_opc_reg(s, i1, a0, a1, a2);
2087 break;
2089 case INDEX_op_sub_i32:
2090 i1 = OPC_SUBU, i2 = OPC_ADDIU;
2091 goto do_subtract;
2092 case INDEX_op_sub_i64:
2093 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
2094 do_subtract:
2095 if (c2) {
2096 tcg_out_opc_imm(s, i2, a0, a1, -a2);
2097 break;
2098 }
2099 goto do_binaryv;
2100 case INDEX_op_and_i32:
2101 if (c2 && a2 != (uint16_t)a2) {
2102 int msb = ctz32(~a2) - 1;
2103 tcg_debug_assert(use_mips32r2_instructions);
2104 tcg_debug_assert(is_p2m1(a2));
2105 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
2106 break;
2107 }
2108 i1 = OPC_AND, i2 = OPC_ANDI;
2109 goto do_binary;
2110 case INDEX_op_and_i64:
2111 if (c2 && a2 != (uint16_t)a2) {
2112 int msb = ctz64(~a2) - 1;
2113 tcg_debug_assert(use_mips32r2_instructions);
2114 tcg_debug_assert(is_p2m1(a2));
2115 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
2116 break;
2117 }
2118 i1 = OPC_AND, i2 = OPC_ANDI;
2119 goto do_binary;
2120 case INDEX_op_nor_i32:
2121 case INDEX_op_nor_i64:
2122 i1 = OPC_NOR;
2123 goto do_binaryv;
2125 case INDEX_op_mul_i32:
2126 if (use_mips32_instructions) {
2127 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
2128 break;
2129 }
2130 i1 = OPC_MULT, i2 = OPC_MFLO;
2131 goto do_hilo1;
2132 case INDEX_op_mulsh_i32:
2133 if (use_mips32r6_instructions) {
2134 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
2135 break;
2136 }
2137 i1 = OPC_MULT, i2 = OPC_MFHI;
2138 goto do_hilo1;
2139 case INDEX_op_muluh_i32:
2140 if (use_mips32r6_instructions) {
2141 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
2142 break;
2143 }
2144 i1 = OPC_MULTU, i2 = OPC_MFHI;
2145 goto do_hilo1;
2146 case INDEX_op_div_i32:
2147 if (use_mips32r6_instructions) {
2148 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
2149 break;
2150 }
2151 i1 = OPC_DIV, i2 = OPC_MFLO;
2152 goto do_hilo1;
2153 case INDEX_op_divu_i32:
2154 if (use_mips32r6_instructions) {
2155 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
2156 break;
2157 }
2158 i1 = OPC_DIVU, i2 = OPC_MFLO;
2159 goto do_hilo1;
2160 case INDEX_op_rem_i32:
2161 if (use_mips32r6_instructions) {
2162 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
2163 break;
2164 }
2165 i1 = OPC_DIV, i2 = OPC_MFHI;
2166 goto do_hilo1;
2167 case INDEX_op_remu_i32:
2168 if (use_mips32r6_instructions) {
2169 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
2170 break;
2171 }
2172 i1 = OPC_DIVU, i2 = OPC_MFHI;
2173 goto do_hilo1;
2174 case INDEX_op_mul_i64:
2175 if (use_mips32r6_instructions) {
2176 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
2177 break;
2178 }
2179 i1 = OPC_DMULT, i2 = OPC_MFLO;
2180 goto do_hilo1;
2181 case INDEX_op_mulsh_i64:
2182 if (use_mips32r6_instructions) {
2183 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
2184 break;
2185 }
2186 i1 = OPC_DMULT, i2 = OPC_MFHI;
2187 goto do_hilo1;
2188 case INDEX_op_muluh_i64:
2189 if (use_mips32r6_instructions) {
2190 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
2191 break;
2192 }
2193 i1 = OPC_DMULTU, i2 = OPC_MFHI;
2194 goto do_hilo1;
2195 case INDEX_op_div_i64:
2196 if (use_mips32r6_instructions) {
2197 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
2198 break;
2199 }
2200 i1 = OPC_DDIV, i2 = OPC_MFLO;
2201 goto do_hilo1;
2202 case INDEX_op_divu_i64:
2203 if (use_mips32r6_instructions) {
2204 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
2205 break;
2206 }
2207 i1 = OPC_DDIVU, i2 = OPC_MFLO;
2208 goto do_hilo1;
2209 case INDEX_op_rem_i64:
2210 if (use_mips32r6_instructions) {
2211 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
2212 break;
2213 }
2214 i1 = OPC_DDIV, i2 = OPC_MFHI;
2215 goto do_hilo1;
2216 case INDEX_op_remu_i64:
2217 if (use_mips32r6_instructions) {
2218 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
2219 break;
2220 }
2221 i1 = OPC_DDIVU, i2 = OPC_MFHI;
2222 do_hilo1:
2223 tcg_out_opc_reg(s, i1, 0, a1, a2);
2224 tcg_out_opc_reg(s, i2, a0, 0, 0);
2225 break;
2227 case INDEX_op_muls2_i32:
2228 i1 = OPC_MULT;
2229 goto do_hilo2;
2230 case INDEX_op_mulu2_i32:
2231 i1 = OPC_MULTU;
2232 goto do_hilo2;
2233 case INDEX_op_muls2_i64:
2234 i1 = OPC_DMULT;
2235 goto do_hilo2;
2236 case INDEX_op_mulu2_i64:
2237 i1 = OPC_DMULTU;
2238 do_hilo2:
2239 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
2240 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
2241 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
2242 break;
2244 case INDEX_op_not_i32:
2245 case INDEX_op_not_i64:
2246 i1 = OPC_NOR;
2247 goto do_unary;
2248 case INDEX_op_ext8s_i32:
2249 case INDEX_op_ext8s_i64:
2250 i1 = OPC_SEB;
2251 goto do_unary;
2252 case INDEX_op_ext16s_i32:
2253 case INDEX_op_ext16s_i64:
2254 i1 = OPC_SEH;
2255 do_unary:
2256 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
2257 break;
2259 case INDEX_op_bswap16_i32:
2260 case INDEX_op_bswap16_i64:
2261 tcg_out_bswap16(s, a0, a1, a2);
2262 break;
2263 case INDEX_op_bswap32_i32:
2264 tcg_out_bswap32(s, a0, a1, 0);
2265 break;
2266 case INDEX_op_bswap32_i64:
2267 tcg_out_bswap32(s, a0, a1, a2);
2268 break;
2269 case INDEX_op_bswap64_i64:
2270 tcg_out_bswap64(s, a0, a1);
2271 break;
2272 case INDEX_op_extrh_i64_i32:
2273 tcg_out_dsra(s, a0, a1, 32);
2274 break;
2275 case INDEX_op_ext32s_i64:
2276 case INDEX_op_ext_i32_i64:
2277 case INDEX_op_extrl_i64_i32:
2278 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2279 break;
2280 case INDEX_op_ext32u_i64:
2281 case INDEX_op_extu_i32_i64:
2282 tcg_out_ext32u(s, a0, a1);
2283 break;
2285 case INDEX_op_sar_i32:
2286 i1 = OPC_SRAV, i2 = OPC_SRA;
2287 goto do_shift;
2288 case INDEX_op_shl_i32:
2289 i1 = OPC_SLLV, i2 = OPC_SLL;
2290 goto do_shift;
2291 case INDEX_op_shr_i32:
2292 i1 = OPC_SRLV, i2 = OPC_SRL;
2293 goto do_shift;
2294 case INDEX_op_rotr_i32:
2295 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2296 do_shift:
2297 if (c2) {
2298 tcg_out_opc_sa(s, i2, a0, a1, a2);
2299 break;
2300 }
2301 do_shiftv:
2302 tcg_out_opc_reg(s, i1, a0, a2, a1);
2303 break;
2304 case INDEX_op_rotl_i32:
2305 if (c2) {
2306 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
2307 } else {
2308 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2309 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
2310 }
2311 break;
2312 case INDEX_op_sar_i64:
2313 if (c2) {
2314 tcg_out_dsra(s, a0, a1, a2);
2315 break;
2316 }
2317 i1 = OPC_DSRAV;
2318 goto do_shiftv;
2319 case INDEX_op_shl_i64:
2320 if (c2) {
2321 tcg_out_dsll(s, a0, a1, a2);
2322 break;
2323 }
2324 i1 = OPC_DSLLV;
2325 goto do_shiftv;
2326 case INDEX_op_shr_i64:
2327 if (c2) {
2328 tcg_out_dsrl(s, a0, a1, a2);
2329 break;
2330 }
2331 i1 = OPC_DSRLV;
2332 goto do_shiftv;
2333 case INDEX_op_rotr_i64:
2334 if (c2) {
2335 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2336 break;
2337 }
2338 i1 = OPC_DROTRV;
2339 goto do_shiftv;
2340 case INDEX_op_rotl_i64:
2341 if (c2) {
2342 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2343 } else {
2344 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2345 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2346 }
2347 break;
2349 case INDEX_op_clz_i32:
2350 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2351 break;
2352 case INDEX_op_clz_i64:
2353 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2354 break;
2356 case INDEX_op_deposit_i32:
2357 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2358 break;
2359 case INDEX_op_deposit_i64:
2360 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2361 args[3] + args[4] - 1, args[3]);
2362 break;
2363 case INDEX_op_extract_i32:
2364 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2365 break;
2366 case INDEX_op_extract_i64:
2367 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2368 args[3] - 1, a2);
2369 break;
2371 case INDEX_op_brcond_i32:
2372 case INDEX_op_brcond_i64:
2373 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2374 break;
2375 case INDEX_op_brcond2_i32:
2376 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2377 break;
2379 case INDEX_op_movcond_i32:
2380 case INDEX_op_movcond_i64:
2381 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2382 break;
2384 case INDEX_op_setcond_i32:
2385 case INDEX_op_setcond_i64:
2386 tcg_out_setcond(s, args[3], a0, a1, a2);
2387 break;
2388 case INDEX_op_setcond2_i32:
2389 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2390 break;
2392 case INDEX_op_qemu_ld_i32:
2393 tcg_out_qemu_ld(s, args, false);
2394 break;
2395 case INDEX_op_qemu_ld_i64:
2396 tcg_out_qemu_ld(s, args, true);
2397 break;
2398 case INDEX_op_qemu_st_i32:
2399 tcg_out_qemu_st(s, args, false);
2400 break;
2401 case INDEX_op_qemu_st_i64:
2402 tcg_out_qemu_st(s, args, true);
2403 break;
2405 case INDEX_op_add2_i32:
2406 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2407 const_args[4], const_args[5], false);
2408 break;
2409 case INDEX_op_sub2_i32:
2410 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2411 const_args[4], const_args[5], true);
2412 break;
2414 case INDEX_op_mb:
2415 tcg_out_mb(s, a0);
2416 break;
2417 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2418 case INDEX_op_mov_i64:
2419 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2420 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
2421 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
2422 default:
2423 tcg_abort();
2424 }
2425 }
2427 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2428 {
2429 switch (op) {
2430 case INDEX_op_goto_ptr:
2431 return C_O0_I1(r);
2433 case INDEX_op_ld8u_i32:
2434 case INDEX_op_ld8s_i32:
2435 case INDEX_op_ld16u_i32:
2436 case INDEX_op_ld16s_i32:
2437 case INDEX_op_ld_i32:
2438 case INDEX_op_not_i32:
2439 case INDEX_op_bswap16_i32:
2440 case INDEX_op_bswap32_i32:
2441 case INDEX_op_ext8s_i32:
2442 case INDEX_op_ext16s_i32:
2443 case INDEX_op_extract_i32:
2444 case INDEX_op_ld8u_i64:
2445 case INDEX_op_ld8s_i64:
2446 case INDEX_op_ld16u_i64:
2447 case INDEX_op_ld16s_i64:
2448 case INDEX_op_ld32s_i64:
2449 case INDEX_op_ld32u_i64:
2450 case INDEX_op_ld_i64:
2451 case INDEX_op_not_i64:
2452 case INDEX_op_bswap16_i64:
2453 case INDEX_op_bswap32_i64:
2454 case INDEX_op_bswap64_i64:
2455 case INDEX_op_ext8s_i64:
2456 case INDEX_op_ext16s_i64:
2457 case INDEX_op_ext32s_i64:
2458 case INDEX_op_ext32u_i64:
2459 case INDEX_op_ext_i32_i64:
2460 case INDEX_op_extu_i32_i64:
2461 case INDEX_op_extrl_i64_i32:
2462 case INDEX_op_extrh_i64_i32:
2463 case INDEX_op_extract_i64:
2464 return C_O1_I1(r, r);
2466 case INDEX_op_st8_i32:
2467 case INDEX_op_st16_i32:
2468 case INDEX_op_st_i32:
2469 case INDEX_op_st8_i64:
2470 case INDEX_op_st16_i64:
2471 case INDEX_op_st32_i64:
2472 case INDEX_op_st_i64:
2473 return C_O0_I2(rZ, r);
2475 case INDEX_op_add_i32:
2476 case INDEX_op_add_i64:
2477 return C_O1_I2(r, r, rJ);
2478 case INDEX_op_sub_i32:
2479 case INDEX_op_sub_i64:
2480 return C_O1_I2(r, rZ, rN);
2481 case INDEX_op_mul_i32:
2482 case INDEX_op_mulsh_i32:
2483 case INDEX_op_muluh_i32:
2484 case INDEX_op_div_i32:
2485 case INDEX_op_divu_i32:
2486 case INDEX_op_rem_i32:
2487 case INDEX_op_remu_i32:
2488 case INDEX_op_nor_i32:
2489 case INDEX_op_setcond_i32:
2490 case INDEX_op_mul_i64:
2491 case INDEX_op_mulsh_i64:
2492 case INDEX_op_muluh_i64:
2493 case INDEX_op_div_i64:
2494 case INDEX_op_divu_i64:
2495 case INDEX_op_rem_i64:
2496 case INDEX_op_remu_i64:
2497 case INDEX_op_nor_i64:
2498 case INDEX_op_setcond_i64:
2499 return C_O1_I2(r, rZ, rZ);
2500 case INDEX_op_muls2_i32:
2501 case INDEX_op_mulu2_i32:
2502 case INDEX_op_muls2_i64:
2503 case INDEX_op_mulu2_i64:
2504 return C_O2_I2(r, r, r, r);
2505 case INDEX_op_and_i32:
2506 case INDEX_op_and_i64:
2507 return C_O1_I2(r, r, rIK);
2508 case INDEX_op_or_i32:
2509 case INDEX_op_xor_i32:
2510 case INDEX_op_or_i64:
2511 case INDEX_op_xor_i64:
2512 return C_O1_I2(r, r, rI);
2513 case INDEX_op_shl_i32:
2514 case INDEX_op_shr_i32:
2515 case INDEX_op_sar_i32:
2516 case INDEX_op_rotr_i32:
2517 case INDEX_op_rotl_i32:
2518 case INDEX_op_shl_i64:
2519 case INDEX_op_shr_i64:
2520 case INDEX_op_sar_i64:
2521 case INDEX_op_rotr_i64:
2522 case INDEX_op_rotl_i64:
2523 return C_O1_I2(r, r, ri);
2524 case INDEX_op_clz_i32:
2525 case INDEX_op_clz_i64:
2526 return C_O1_I2(r, r, rWZ);
2528 case INDEX_op_deposit_i32:
2529 case INDEX_op_deposit_i64:
2530 return C_O1_I2(r, 0, rZ);
2531 case INDEX_op_brcond_i32:
2532 case INDEX_op_brcond_i64:
2533 return C_O0_I2(rZ, rZ);
2534 case INDEX_op_movcond_i32:
2535 case INDEX_op_movcond_i64:
2536 return (use_mips32r6_instructions
2537 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2538 : C_O1_I4(r, rZ, rZ, rZ, 0));
2539 case INDEX_op_add2_i32:
2540 case INDEX_op_sub2_i32:
2541 return C_O2_I4(r, r, rZ, rZ, rN, rN);
2542 case INDEX_op_setcond2_i32:
2543 return C_O1_I4(r, rZ, rZ, rZ, rZ);
2544 case INDEX_op_brcond2_i32:
2545 return C_O0_I4(rZ, rZ, rZ, rZ);
2547 case INDEX_op_qemu_ld_i32:
2548 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2549 ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
2550 case INDEX_op_qemu_st_i32:
2551 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2552 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
2553 case INDEX_op_qemu_ld_i64:
2554 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
2555 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
2556 : C_O2_I2(r, r, L, L));
2557 case INDEX_op_qemu_st_i64:
2558 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
2559 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
2560 : C_O0_I4(SZ, SZ, S, S));
2562 default:
2563 g_assert_not_reached();
2564 }
2565 }
2567 static const int tcg_target_callee_save_regs[] = {
2568 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2569 TCG_REG_S1,
2570 TCG_REG_S2,
2571 TCG_REG_S3,
2572 TCG_REG_S4,
2573 TCG_REG_S5,
2574 TCG_REG_S6,
2575 TCG_REG_S7,
2576 TCG_REG_S8,
2577 TCG_REG_RA, /* should be last for ABI compliance */
2578 };
2580 /* The Linux kernel doesn't provide any information about the available
2581 instruction set. Probe it using a signal handler. */
2584 #ifndef use_movnz_instructions
2585 bool use_movnz_instructions = false;
2586 #endif
2588 #ifndef use_mips32_instructions
2589 bool use_mips32_instructions = false;
2590 #endif
2592 #ifndef use_mips32r2_instructions
2593 bool use_mips32r2_instructions = false;
2594 #endif
2596 static volatile sig_atomic_t got_sigill;
2598 static void sigill_handler(int signo, siginfo_t *si, void *data)
2599 {
2600 /* Skip the faulty instruction */
2601 ucontext_t *uc = (ucontext_t *)data;
2602 uc->uc_mcontext.pc += 4;
2604 got_sigill = 1;
2605 }
2607 static void tcg_target_detect_isa(void)
2608 {
2609 struct sigaction sa_old, sa_new;
2611 memset(&sa_new, 0, sizeof(sa_new));
2612 sa_new.sa_flags = SA_SIGINFO;
2613 sa_new.sa_sigaction = sigill_handler;
2614 sigaction(SIGILL, &sa_new, &sa_old);
2616 /* Probe for movn/movz, necessary to implement movcond. */
2617 #ifndef use_movnz_instructions
2618 got_sigill = 0;
2619 asm volatile(".set push\n"
2620 ".set mips32\n"
2621 "movn $zero, $zero, $zero\n"
2622 "movz $zero, $zero, $zero\n"
2623 ".set pop\n"
2624 : : : );
2625 use_movnz_instructions = !got_sigill;
2626 #endif
2628 /* Probe for MIPS32 instructions. As no subsetting is allowed
2629 by the specification, it is only necessary to probe for one
2630 of the instructions. */
2631 #ifndef use_mips32_instructions
2632 got_sigill = 0;
2633 asm volatile(".set push\n"
2634 ".set mips32\n"
2635 "mul $zero, $zero\n"
2636 ".set pop\n"
2637 : : : );
2638 use_mips32_instructions = !got_sigill;
2639 #endif
2641 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2642 available. As no subsetting is allowed by the specification,
2643 it is only necessary to probe for one of the instructions. */
2644 #ifndef use_mips32r2_instructions
2645 if (use_mips32_instructions) {
2646 got_sigill = 0;
2647 asm volatile(".set push\n"
2648 ".set mips32r2\n"
2649 "seb $zero, $zero\n"
2650 ".set pop\n"
2651 : : : );
2652 use_mips32r2_instructions = !got_sigill;
2653 }
2654 #endif
2656 sigaction(SIGILL, &sa_old, NULL);
2657 }
2659 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2660 {
2661 uintptr_t p = (uintptr_t)s->code_ptr;
2662 if (p & 15) {
2663 p = (p + 15) & -16;
2664 s->code_ptr = (void *)p;
2665 }
2666 return s->code_ptr;
2667 }
2669 /* Stack frame parameters. */
2670 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2671 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2672 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2674 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2675 + TCG_TARGET_STACK_ALIGN - 1) \
2676 & -TCG_TARGET_STACK_ALIGN)
2677 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2679 /* We're expecting to be able to use an immediate for frame allocation. */
2680 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2682 /* Generate global QEMU prologue and epilogue code */
2683 static void tcg_target_qemu_prologue(TCGContext *s)
2684 {
2685 int i;
2687 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2689 /* TB prologue */
2690 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2691 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2692 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2693 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2694 }
2696 #ifndef CONFIG_SOFTMMU
2697 if (guest_base) {
2698 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2699 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2700 }
2701 #endif
2703 /* Call generated code */
2704 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2705 /* delay slot */
2706 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2708 /*
2709 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2710 * and fall through to the rest of the epilogue.
2711 */
2712 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2713 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2715 /* TB epilogue */
2716 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2717 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2718 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2719 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2720 }
2722 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2723 /* delay slot */
2724 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2726 if (use_mips32r2_instructions) {
2727 return;
2728 }
2730 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2731 clobbers TCG_TMP1, TCG_TMP2. */
2733 /*
2734 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2735 */
2736 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2737 /* t3 = (ssss)d000 */
2738 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2739 /* t1 = 000a */
2740 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2741 /* t2 = 00c0 */
2742 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2743 /* t3 = d00a */
2744 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2745 /* t1 = 0abc */
2746 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2747 /* t2 = 0c00 */
2748 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2749 /* t1 = 00b0 */
2750 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2751 /* t3 = dc0a */
2752 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2753 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2754 /* t3 = dcba -- delay slot */
2755 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2757 if (TCG_TARGET_REG_BITS == 32) {
2758 return;
2759 }
2761 /*
2762 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2763 */
2764 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2765 /* t1 = (0000)000d */
2766 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2767 /* t3 = 000a */
2768 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2769 /* t1 = (0000)d000 */
2770 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2771 /* t2 = 00c0 */
2772 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2773 /* t3 = d00a */
2774 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2775 /* t1 = 0abc */
2776 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2777 /* t2 = 0c00 */
2778 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2779 /* t1 = 00b0 */
2780 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2781 /* t3 = dc0a */
2782 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2783 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2784 /* t3 = dcba -- delay slot */
2785 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2787 /*
2788 * bswap64 -- 64-bit swap. a0 = abcdefgh
2789 */
2790 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2791 /* t3 = h0000000 */
2792 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2793 /* t1 = 0000000a */
2794 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2796 /* t2 = 000000g0 */
2797 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2798 /* t3 = h000000a */
2799 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2800 /* t1 = 00000abc */
2801 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2802 /* t2 = 0g000000 */
2803 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2804 /* t1 = 000000b0 */
2805 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2807 /* t3 = hg00000a */
2808 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2809 /* t2 = 0000abcd */
2810 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2811 /* t3 = hg0000ba */
2812 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2814 /* t1 = 000000c0 */
2815 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2816 /* t2 = 0000000d */
2817 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2818 /* t1 = 00000c00 */
2819 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2820 /* t2 = 0000d000 */
2821 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2823 /* t3 = hg000cba */
2824 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2825 /* t1 = 00abcdef */
2826 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2827 /* t3 = hg00dcba */
2828 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2830 /* t2 = 0000000f */
2831 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2832 /* t1 = 000000e0 */
2833 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2834 /* t2 = 00f00000 */
2835 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2836 /* t1 = 000e0000 */
2837 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2839 /* t3 = hgf0dcba */
2840 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2841 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2842 /* t3 = hgfedcba -- delay slot */
2843 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2844 }
2846 static void tcg_target_init(TCGContext *s)
2847 {
2848 tcg_target_detect_isa();
2849 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2850 if (TCG_TARGET_REG_BITS == 64) {
2851 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2852 }
2854 tcg_target_call_clobber_regs = 0;
2855 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2856 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2857 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2858 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2859 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2860 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2861 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2862 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2863 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2864 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2865 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2866 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2867 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2868 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2869 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2870 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2872 s->reserved_regs = 0;
2873 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2874 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2875 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2876 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2877 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2878 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2879 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2880 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2881 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2882 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2883 }
2885 typedef struct {
2886 DebugFrameHeader h;
2887 uint8_t fde_def_cfa[4];
2888 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2889 } DebugFrame;
2891 #define ELF_HOST_MACHINE EM_MIPS
2892 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2893 which is good because they're really quite complicated for MIPS. */
2895 static const DebugFrame debug_frame = {
2896 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2897 .h.cie.id = -1,
2898 .h.cie.version = 1,
2899 .h.cie.code_align = 1,
2900 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2901 .h.cie.return_column = TCG_REG_RA,
2903 /* Total FDE size does not include the "len" member. */
2904 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2906 .fde_def_cfa = {
2907 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2908 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2909 (FRAME_SIZE >> 7)
2910 },
2911 .fde_reg_ofs = {
2912 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2913 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2914 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2915 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2916 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2917 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2918 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2919 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2920 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2921 }
2922 };
2924 void tcg_register_jit(const void *buf, size_t buf_size)
2925 {
2926 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2927 }