4 * Copyright (c) 2019 Yoshinori Sato
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/qemu-print.h"
21 #include "qapi/error.h"
23 #include "migration/vmstate.h"
24 #include "exec/exec-all.h"
25 #include "hw/loader.h"
26 #include "fpu/softfloat.h"
28 static void rx_cpu_set_pc(CPUState
*cs
, vaddr value
)
30 RXCPU
*cpu
= RX_CPU(cs
);
35 static vaddr
rx_cpu_get_pc(CPUState
*cs
)
37 RXCPU
*cpu
= RX_CPU(cs
);
42 static void rx_cpu_synchronize_from_tb(CPUState
*cs
,
43 const TranslationBlock
*tb
)
45 RXCPU
*cpu
= RX_CPU(cs
);
47 cpu
->env
.pc
= tb_pc(tb
);
50 static void rx_restore_state_to_opc(CPUState
*cs
,
51 const TranslationBlock
*tb
,
54 RXCPU
*cpu
= RX_CPU(cs
);
56 cpu
->env
.pc
= data
[0];
59 static bool rx_cpu_has_work(CPUState
*cs
)
61 return cs
->interrupt_request
&
62 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_FIR
);
65 static void rx_cpu_reset_hold(Object
*obj
)
67 RXCPU
*cpu
= RX_CPU(obj
);
68 RXCPUClass
*rcc
= RX_CPU_GET_CLASS(cpu
);
69 CPURXState
*env
= &cpu
->env
;
72 if (rcc
->parent_phases
.hold
) {
73 rcc
->parent_phases
.hold(obj
);
76 memset(env
, 0, offsetof(CPURXState
, end_reset_fields
));
78 resetvec
= rom_ptr(0xfffffffc, 4);
80 /* In the case of kernel, it is ignored because it is not set. */
81 env
->pc
= ldl_p(resetvec
);
83 rx_cpu_unpack_psw(env
, 0, 1);
84 env
->regs
[0] = env
->isp
= env
->usp
= 0;
86 set_flush_to_zero(1, &env
->fp_status
);
87 set_flush_inputs_to_zero(1, &env
->fp_status
);
90 static void rx_cpu_list_entry(gpointer data
, gpointer user_data
)
92 ObjectClass
*oc
= data
;
94 qemu_printf(" %s\n", object_class_get_name(oc
));
97 void rx_cpu_list(void)
100 list
= object_class_get_list_sorted(TYPE_RX_CPU
, false);
101 qemu_printf("Available CPUs:\n");
102 g_slist_foreach(list
, rx_cpu_list_entry
, NULL
);
106 static ObjectClass
*rx_cpu_class_by_name(const char *cpu_model
)
111 oc
= object_class_by_name(cpu_model
);
112 if (oc
!= NULL
&& object_class_dynamic_cast(oc
, TYPE_RX_CPU
) != NULL
&&
113 !object_class_is_abstract(oc
)) {
116 typename
= g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model
);
117 oc
= object_class_by_name(typename
);
119 if (oc
!= NULL
&& object_class_is_abstract(oc
)) {
126 static void rx_cpu_realize(DeviceState
*dev
, Error
**errp
)
128 CPUState
*cs
= CPU(dev
);
129 RXCPUClass
*rcc
= RX_CPU_GET_CLASS(dev
);
130 Error
*local_err
= NULL
;
132 cpu_exec_realizefn(cs
, &local_err
);
133 if (local_err
!= NULL
) {
134 error_propagate(errp
, local_err
);
141 rcc
->parent_realize(dev
, errp
);
144 static void rx_cpu_set_irq(void *opaque
, int no
, int request
)
147 CPUState
*cs
= CPU(cpu
);
148 int irq
= request
& 0xff;
150 static const int mask
[] = {
151 [RX_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
152 [RX_CPU_FIR
] = CPU_INTERRUPT_FIR
,
155 cpu
->env
.req_irq
= irq
;
156 cpu
->env
.req_ipl
= (request
>> 8) & 0x0f;
157 cpu_interrupt(cs
, mask
[no
]);
159 cpu_reset_interrupt(cs
, mask
[no
]);
163 static void rx_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
165 info
->mach
= bfd_mach_rx
;
166 info
->print_insn
= print_insn_rx
;
169 static bool rx_cpu_tlb_fill(CPUState
*cs
, vaddr addr
, int size
,
170 MMUAccessType access_type
, int mmu_idx
,
171 bool probe
, uintptr_t retaddr
)
173 uint32_t address
, physical
, prot
;
176 address
= physical
= addr
& TARGET_PAGE_MASK
;
177 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
178 tlb_set_page(cs
, address
, physical
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
182 static void rx_cpu_init(Object
*obj
)
184 CPUState
*cs
= CPU(obj
);
185 RXCPU
*cpu
= RX_CPU(obj
);
186 CPURXState
*env
= &cpu
->env
;
188 cpu_set_cpustate_pointers(cpu
);
190 qdev_init_gpio_in(DEVICE(cpu
), rx_cpu_set_irq
, 2);
193 #ifndef CONFIG_USER_ONLY
194 #include "hw/core/sysemu-cpu-ops.h"
196 static const struct SysemuCPUOps rx_sysemu_ops
= {
197 .get_phys_page_debug
= rx_cpu_get_phys_page_debug
,
201 #include "hw/core/tcg-cpu-ops.h"
203 static const struct TCGCPUOps rx_tcg_ops
= {
204 .initialize
= rx_translate_init
,
205 .synchronize_from_tb
= rx_cpu_synchronize_from_tb
,
206 .restore_state_to_opc
= rx_restore_state_to_opc
,
207 .tlb_fill
= rx_cpu_tlb_fill
,
209 #ifndef CONFIG_USER_ONLY
210 .cpu_exec_interrupt
= rx_cpu_exec_interrupt
,
211 .do_interrupt
= rx_cpu_do_interrupt
,
212 #endif /* !CONFIG_USER_ONLY */
215 static void rx_cpu_class_init(ObjectClass
*klass
, void *data
)
217 DeviceClass
*dc
= DEVICE_CLASS(klass
);
218 CPUClass
*cc
= CPU_CLASS(klass
);
219 RXCPUClass
*rcc
= RX_CPU_CLASS(klass
);
220 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
222 device_class_set_parent_realize(dc
, rx_cpu_realize
,
223 &rcc
->parent_realize
);
224 resettable_class_set_parent_phases(rc
, NULL
, rx_cpu_reset_hold
, NULL
,
225 &rcc
->parent_phases
);
227 cc
->class_by_name
= rx_cpu_class_by_name
;
228 cc
->has_work
= rx_cpu_has_work
;
229 cc
->dump_state
= rx_cpu_dump_state
;
230 cc
->set_pc
= rx_cpu_set_pc
;
231 cc
->get_pc
= rx_cpu_get_pc
;
233 #ifndef CONFIG_USER_ONLY
234 cc
->sysemu_ops
= &rx_sysemu_ops
;
236 cc
->gdb_read_register
= rx_cpu_gdb_read_register
;
237 cc
->gdb_write_register
= rx_cpu_gdb_write_register
;
238 cc
->disas_set_info
= rx_cpu_disas_set_info
;
240 cc
->gdb_num_core_regs
= 26;
241 cc
->gdb_core_xml_file
= "rx-core.xml";
242 cc
->tcg_ops
= &rx_tcg_ops
;
245 static const TypeInfo rx_cpu_info
= {
248 .instance_size
= sizeof(RXCPU
),
249 .instance_init
= rx_cpu_init
,
251 .class_size
= sizeof(RXCPUClass
),
252 .class_init
= rx_cpu_class_init
,
255 static const TypeInfo rx62n_rx_cpu_info
= {
256 .name
= TYPE_RX62N_CPU
,
257 .parent
= TYPE_RX_CPU
,
260 static void rx_cpu_register_types(void)
262 type_register_static(&rx_cpu_info
);
263 type_register_static(&rx62n_rx_cpu_info
);
266 type_init(rx_cpu_register_types
)