target/microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/log.h"
  26 #include "qapi/error.h"
  27 #include "cpu.h"
  28 #include "qemu/module.h"
  29 #include "hw/qdev-properties.h"
  30 #include "exec/exec-all.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 static const struct {
  34     const char *name;
  35     uint8_t version_id;
  36 } mb_cpu_lookup[] = {
  37     /* These key value are as per MBV field in PVR0 */
  38     {"5.00.a", 0x01},
  39     {"5.00.b", 0x02},
  40     {"5.00.c", 0x03},
  41     {"6.00.a", 0x04},
  42     {"6.00.b", 0x06},
  43     {"7.00.a", 0x05},
  44     {"7.00.b", 0x07},
  45     {"7.10.a", 0x08},
  46     {"7.10.b", 0x09},
  47     {"7.10.c", 0x0a},
  48     {"7.10.d", 0x0b},
  49     {"7.20.a", 0x0c},
  50     {"7.20.b", 0x0d},
  51     {"7.20.c", 0x0e},
  52     {"7.20.d", 0x0f},
  53     {"7.30.a", 0x10},
  54     {"7.30.b", 0x11},
  55     {"8.00.a", 0x12},
  56     {"8.00.b", 0x13},
  57     {"8.10.a", 0x14},
  58     {"8.20.a", 0x15},
  59     {"8.20.b", 0x16},
  60     {"8.30.a", 0x17},
  61     {"8.40.a", 0x18},
  62     {"8.40.b", 0x19},
  63     {"8.50.a", 0x1A},
  64     {"9.0", 0x1B},
  65     {"9.1", 0x1D},
  66     {"9.2", 0x1F},
  67     {"9.3", 0x20},
  68     {"9.4", 0x21},
  69     {"9.5", 0x22},
  70     {"9.6", 0x23},
  71     {"10.0", 0x24},
  72     {NULL, 0},
  73 };
  74
  75 /* If no specific version gets selected, default to the following.  */
  76 #define DEFAULT_CPU_VERSION "10.0"
  77
  78 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  79 {
  80     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  81
  82     cpu->env.pc = value;
  83     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
  84     cpu->env.iflags = 0;
  85 }
  86
  87 static vaddr mb_cpu_get_pc(CPUState *cs)
  88 {
  89     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  90
  91     return cpu->env.pc;
  92 }
  93
  94 static void mb_cpu_synchronize_from_tb(CPUState *cs,
  95                                        const TranslationBlock *tb)
  96 {
  97     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  98
  99     cpu->env.pc = tb_pc(tb);
 100     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
 101 }
 102
 103 static void mb_restore_state_to_opc(CPUState *cs,
 104                                     const TranslationBlock *tb,
 105                                     const uint64_t *data)
 106 {
 107     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 108
 109     cpu->env.pc = data[0];
 110     cpu->env.iflags = data[1];
 111 }
 112
 113 static bool mb_cpu_has_work(CPUState *cs)
 114 {
 115     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
 116 }
 117
 118 #ifndef CONFIG_USER_ONLY
 119 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
 120 {
 121     MicroBlazeCPU *cpu = opaque;
 122     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
 123
 124     cpu->ns_axi_dp = level & en;
 125 }
 126
 127 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
 128 {
 129     MicroBlazeCPU *cpu = opaque;
 130     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
 131
 132     cpu->ns_axi_ip = level & en;
 133 }
 134
 135 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
 136 {
 137     MicroBlazeCPU *cpu = opaque;
 138     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
 139
 140     cpu->ns_axi_dc = level & en;
 141 }
 142
 143 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
 144 {
 145     MicroBlazeCPU *cpu = opaque;
 146     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
 147
 148     cpu->ns_axi_ic = level & en;
 149 }
 150
 151 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
 152 {
 153     MicroBlazeCPU *cpu = opaque;
 154     CPUState *cs = CPU(cpu);
 155     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 156
 157     if (level) {
 158         cpu_interrupt(cs, type);
 159     } else {
 160         cpu_reset_interrupt(cs, type);
 161     }
 162 }
 163 #endif
 164
 165 static void mb_cpu_reset_hold(Object *obj)
 166 {
 167     CPUState *s = CPU(obj);
 168     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
 169     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
 170     CPUMBState *env = &cpu->env;
 171
 172     if (mcc->parent_phases.hold) {
 173         mcc->parent_phases.hold(obj);
 174     }
 175
 176     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
 177     env->res_addr = RES_ADDR_NONE;
 178
 179     /* Disable stack protector.  */
 180     env->shr = ~0;
 181
 182     env->pc = cpu->cfg.base_vectors;
 183
 184 #if defined(CONFIG_USER_ONLY)
 185     /* start in user mode with interrupts enabled.  */
 186     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
 187 #else
 188     mb_cpu_write_msr(env, 0);
 189     mmu_init(&env->mmu);
 190 #endif
 191 }
 192
 193 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 194 {
 195     info->mach = bfd_arch_microblaze;
 196     info->print_insn = print_insn_microblaze;
 197 }
 198
 199 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 200 {
 201     CPUState *cs = CPU(dev);
 202     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 203     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 204     uint8_t version_code = 0;
 205     const char *version;
 206     int i = 0;
 207     Error *local_err = NULL;
 208
 209     cpu_exec_realizefn(cs, &local_err);
 210     if (local_err != NULL) {
 211         error_propagate(errp, local_err);
 212         return;
 213     }
 214
 215     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
 216         error_setg(errp, "addr-size %d is out of range (32 - 64)",
 217                    cpu->cfg.addr_size);
 218         return;
 219     }
 220
 221     qemu_init_vcpu(cs);
 222
 223     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
 224     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
 225         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
 226             version_code = mb_cpu_lookup[i].version_id;
 227             break;
 228         }
 229     }
 230
 231     if (!version_code) {
 232         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 233     }
 234
 235     cpu->cfg.pvr_regs[0] =
 236         (PVR0_USE_EXC_MASK |
 237          PVR0_USE_ICACHE_MASK |
 238          PVR0_USE_DCACHE_MASK |
 239          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 240          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 241          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
 242          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
 243          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
 244          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 245          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 246          (version_code << PVR0_VERSION_SHIFT) |
 247          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
 248          cpu->cfg.pvr_user1);
 249
 250     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
 251
 252     cpu->cfg.pvr_regs[2] =
 253         (PVR2_D_OPB_MASK |
 254          PVR2_D_LMB_MASK |
 255          PVR2_I_OPB_MASK |
 256          PVR2_I_LMB_MASK |
 257          PVR2_FPU_EXC_MASK |
 258          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 259          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
 260          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
 261          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
 262          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
 263          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
 264          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
 265          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
 266          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
 267          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
 268          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
 269          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
 270          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
 271          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
 272
 273     cpu->cfg.pvr_regs[5] |=
 274         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
 275
 276     cpu->cfg.pvr_regs[10] =
 277         (0x0c000000 | /* Default to spartan 3a dsp family.  */
 278          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
 279
 280     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
 281                              16 << 17);
 282
 283     cpu->cfg.mmu = 3;
 284     cpu->cfg.mmu_tlb_access = 3;
 285     cpu->cfg.mmu_zones = 16;
 286     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
 287
 288     mcc->parent_realize(dev, errp);
 289 }
 290
 291 static void mb_cpu_initfn(Object *obj)
 292 {
 293     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 294     CPUMBState *env = &cpu->env;
 295
 296     cpu_set_cpustate_pointers(cpu);
 297
 298     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 299
 300 #ifndef CONFIG_USER_ONLY
 301     /* Inbound IRQ and FIR lines */
 302     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 303     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
 304     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
 305     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
 306     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
 307 #endif
 308 }
 309
 310 static Property mb_properties[] = {
 311     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 312     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 313                      false),
 314     /*
 315      * This is the C_ADDR_SIZE synth-time configuration option of the
 316      * MicroBlaze cores. Supported values range between 32 and 64.
 317      *
 318      * When set to > 32, 32bit MicroBlaze can emit load/stores
 319      * with extended addressing.
 320      */
 321     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
 322     /* If use-fpu > 0 - FPU is enabled
 323      * If use-fpu = 2 - Floating point conversion and square root instructions
 324      *                  are enabled
 325      */
 326     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 327     /* If use-hw-mul > 0 - Multiplier is enabled
 328      * If use-hw-mul = 2 - 64-bit multiplier is enabled
 329      */
 330     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
 331     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
 332     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
 333     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
 334     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
 335     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 336     /*
 337      * use-non-secure enables/disables the use of the non_secure[3:0] signals.
 338      * It is a bitfield where 1 = non-secure for the following bits and their
 339      * corresponding interfaces:
 340      * 0x1 - M_AXI_DP
 341      * 0x2 - M_AXI_IP
 342      * 0x4 - M_AXI_DC
 343      * 0x8 - M_AXI_IC
 344      */
 345     DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
 346     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 347                      false),
 348     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 349     /* Enables bus exceptions on failed data accesses (load/stores).  */
 350     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
 351                      cfg.dopb_bus_exception, false),
 352     /* Enables bus exceptions on failed instruction fetches.  */
 353     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
 354                      cfg.iopb_bus_exception, false),
 355     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
 356                      cfg.illegal_opcode_exception, false),
 357     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
 358                      cfg.div_zero_exception, false),
 359     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
 360                      cfg.unaligned_exceptions, false),
 361     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
 362                      cfg.opcode_0_illegal, false),
 363     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 364     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 365     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
 366     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
 367     DEFINE_PROP_END_OF_LIST(),
 368 };
 369
 370 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
 371 {
 372     return object_class_by_name(TYPE_MICROBLAZE_CPU);
 373 }
 374
 375 #ifndef CONFIG_USER_ONLY
 376 #include "hw/core/sysemu-cpu-ops.h"
 377
 378 static const struct SysemuCPUOps mb_sysemu_ops = {
 379     .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
 380 };
 381 #endif
 382
 383 #include "hw/core/tcg-cpu-ops.h"
 384
 385 static const struct TCGCPUOps mb_tcg_ops = {
 386     .initialize = mb_tcg_init,
 387     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
 388     .restore_state_to_opc = mb_restore_state_to_opc,
 389
 390 #ifndef CONFIG_USER_ONLY
 391     .tlb_fill = mb_cpu_tlb_fill,
 392     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
 393     .do_interrupt = mb_cpu_do_interrupt,
 394     .do_transaction_failed = mb_cpu_transaction_failed,
 395     .do_unaligned_access = mb_cpu_do_unaligned_access,
 396 #endif /* !CONFIG_USER_ONLY */
 397 };
 398
 399 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 400 {
 401     DeviceClass *dc = DEVICE_CLASS(oc);
 402     CPUClass *cc = CPU_CLASS(oc);
 403     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 404     ResettableClass *rc = RESETTABLE_CLASS(oc);
 405
 406     device_class_set_parent_realize(dc, mb_cpu_realizefn,
 407                                     &mcc->parent_realize);
 408     resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
 409                                        &mcc->parent_phases);
 410
 411     cc->class_by_name = mb_cpu_class_by_name;
 412     cc->has_work = mb_cpu_has_work;
 413
 414     cc->dump_state = mb_cpu_dump_state;
 415     cc->set_pc = mb_cpu_set_pc;
 416     cc->get_pc = mb_cpu_get_pc;
 417     cc->gdb_read_register = mb_cpu_gdb_read_register;
 418     cc->gdb_write_register = mb_cpu_gdb_write_register;
 419
 420 #ifndef CONFIG_USER_ONLY
 421     dc->vmsd = &vmstate_mb_cpu;
 422     cc->sysemu_ops = &mb_sysemu_ops;
 423 #endif
 424     device_class_set_props(dc, mb_properties);
 425     cc->gdb_num_core_regs = 32 + 27;
 426
 427     cc->disas_set_info = mb_disas_set_info;
 428     cc->tcg_ops = &mb_tcg_ops;
 429 }
 430
 431 static const TypeInfo mb_cpu_type_info = {
 432     .name = TYPE_MICROBLAZE_CPU,
 433     .parent = TYPE_CPU,
 434     .instance_size = sizeof(MicroBlazeCPU),
 435     .instance_init = mb_cpu_initfn,
 436     .class_size = sizeof(MicroBlazeCPUClass),
 437     .class_init = mb_cpu_class_init,
 438 };
 439
 440 static void mb_cpu_register_types(void)
 441 {
 442     type_register_static(&mb_cpu_type_info);
 443 }
 444
 445 type_init(mb_cpu_register_types)