1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
6 * Anup Patel <anup.patel@wdc.com>
9 #ifndef __LINUX_KVM_RISCV_H
10 #define __LINUX_KVM_RISCV_H
14 #include <linux/types.h>
15 #include <asm/ptrace.h>
17 #define __KVM_HAVE_READONLY_MEM
19 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
21 #define KVM_INTERRUPT_SET -1U
22 #define KVM_INTERRUPT_UNSET -2U
24 /* for KVM_GET_REGS and KVM_SET_REGS */
28 /* for KVM_GET_FPU and KVM_SET_FPU */
32 /* KVM Debug exit structure */
33 struct kvm_debug_exit_arch
{
36 /* for KVM_SET_GUEST_DEBUG */
37 struct kvm_guest_debug_arch
{
40 /* definition of registers in kvm_run */
41 struct kvm_sync_regs
{
44 /* for KVM_GET_SREGS and KVM_SET_SREGS */
48 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
49 struct kvm_riscv_config
{
53 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
54 struct kvm_riscv_core
{
55 struct user_regs_struct regs
;
59 /* Possible privilege modes for kvm_riscv_core */
60 #define KVM_RISCV_MODE_S 1
61 #define KVM_RISCV_MODE_U 0
63 /* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
64 struct kvm_riscv_csr
{
65 unsigned long sstatus
;
68 unsigned long sscratch
;
74 unsigned long scounteren
;
77 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
78 struct kvm_riscv_timer
{
86 * ISA extension IDs specific to KVM. This is not the same as the host ISA
87 * extension IDs as that is internal to the host and should not be exposed
88 * to the guest. This should always be contiguous to keep the mapping simple
89 * in KVM implementation.
91 enum KVM_RISCV_ISA_EXT_ID
{
92 KVM_RISCV_ISA_EXT_A
= 0,
99 KVM_RISCV_ISA_EXT_SVPBMT
,
100 KVM_RISCV_ISA_EXT_SSTC
,
101 KVM_RISCV_ISA_EXT_MAX
,
104 /* Possible states for kvm_riscv_timer */
105 #define KVM_RISCV_TIMER_STATE_OFF 0
106 #define KVM_RISCV_TIMER_STATE_ON 1
108 #define KVM_REG_SIZE(id) \
109 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
111 /* If you need to interpret the index values, here is the key: */
112 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
113 #define KVM_REG_RISCV_TYPE_SHIFT 24
115 /* Config registers are mapped as type 1 */
116 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
117 #define KVM_REG_RISCV_CONFIG_REG(name) \
118 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
120 /* Core registers are mapped as type 2 */
121 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
122 #define KVM_REG_RISCV_CORE_REG(name) \
123 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
125 /* Control and status registers are mapped as type 3 */
126 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
127 #define KVM_REG_RISCV_CSR_REG(name) \
128 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
130 /* Timer registers are mapped as type 4 */
131 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
132 #define KVM_REG_RISCV_TIMER_REG(name) \
133 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
135 /* F extension registers are mapped as type 5 */
136 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
137 #define KVM_REG_RISCV_FP_F_REG(name) \
138 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
140 /* D extension registers are mapped as type 6 */
141 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
142 #define KVM_REG_RISCV_FP_D_REG(name) \
143 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
145 /* ISA Extension registers are mapped as type 7 */
146 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
150 #endif /* __LINUX_KVM_RISCV_H */