Merge tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu into staging
[qemu/rayw.git] / include / hw / pci / pcie_port.h
blob6c40e3733fd391a3de14bedf8ea382a552f6cfc0
1 /*
2 * pcie_port.h
4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef QEMU_PCIE_PORT_H
22 #define QEMU_PCIE_PORT_H
24 #include "hw/pci/pci_bridge.h"
25 #include "hw/pci/pci_bus.h"
26 #include "hw/pci/pci_device.h"
27 #include "qom/object.h"
29 #define TYPE_PCIE_PORT "pcie-port"
30 OBJECT_DECLARE_SIMPLE_TYPE(PCIEPort, PCIE_PORT)
32 struct PCIEPort {
33 /*< private >*/
34 PCIBridge parent_obj;
35 /*< public >*/
37 /* pci express switch port */
38 uint8_t port;
41 void pcie_port_init_reg(PCIDevice *d);
43 PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn);
45 #define TYPE_PCIE_SLOT "pcie-slot"
46 OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT)
48 struct PCIESlot {
49 /*< private >*/
50 PCIEPort parent_obj;
51 /*< public >*/
53 /* pci express switch port with slot */
54 uint8_t chassis;
55 uint16_t slot;
57 PCIExpLinkSpeed speed;
58 PCIExpLinkWidth width;
60 /* Disable ACS (really for a pcie_root_port) */
61 bool disable_acs;
63 /* Indicates whether any type of hot-plug is allowed on the slot */
64 bool hotplug;
66 /* broken ACPI hotplug compat knob to preserve 6.1 ABI intact */
67 bool hide_native_hotplug_cap;
69 QLIST_ENTRY(PCIESlot) next;
72 void pcie_chassis_create(uint8_t chassis_number);
73 PCIESlot *pcie_chassis_find_slot(uint8_t chassis, uint16_t slot);
74 int pcie_chassis_add_slot(struct PCIESlot *slot);
75 void pcie_chassis_del_slot(PCIESlot *s);
77 #define TYPE_PCIE_ROOT_PORT "pcie-root-port-base"
78 typedef struct PCIERootPortClass PCIERootPortClass;
79 DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT,
80 TYPE_PCIE_ROOT_PORT)
82 struct PCIERootPortClass {
83 PCIDeviceClass parent_class;
84 DeviceRealize parent_realize;
85 ResettablePhases parent_phases;
87 uint8_t (*aer_vector)(const PCIDevice *dev);
88 int (*interrupts_init)(PCIDevice *dev, Error **errp);
89 void (*interrupts_uninit)(PCIDevice *dev);
91 int exp_offset;
92 int aer_offset;
93 int ssvid_offset;
94 int acs_offset; /* If nonzero, optional ACS capability offset */
95 int ssid;
98 #endif /* QEMU_PCIE_PORT_H */