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target/ppc: cpu_init: Reuse init_proc_603 for the e300
[qemu/rayw.git] / target / ppc / cpu_init.c
blob794486dd3a4d66ad17e5015773a35df1c8ede791
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_tcg.h"
48 #include "power8-pmu.h"
49
50 /* #define PPC_DEBUG_SPR */
51 /* #define USE_APPLE_GDB */
52
53 static inline void vscr_init(CPUPPCState *env, uint32_t val)
54 {
55 /* Altivec always uses round-to-nearest */
56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
57 ppc_store_vscr(env, val);
58 }
59
60 /**
61 * _spr_register
62 *
63 * Register an SPR with all the callbacks required for tcg,
64 * and the ID number for KVM.
65 *
66 * The reason for the conditional compilation is that the tcg functions
67 * may be compiled out, and the system kvm header may not be available
68 * for supplying the ID numbers. This is ugly, but the best we can do.
69 */
70
71 #ifdef CONFIG_TCG
72 # define USR_ARG(X) X,
73 # ifdef CONFIG_USER_ONLY
74 # define SYS_ARG(X)
75 # else
76 # define SYS_ARG(X) X,
77 # endif
78 #else
79 # define USR_ARG(X)
80 # define SYS_ARG(X)
81 #endif
82 #ifdef CONFIG_KVM
83 # define KVM_ARG(X) X,
84 #else
85 # define KVM_ARG(X)
86 #endif
87
88 typedef void spr_callback(DisasContext *, int, int);
89
90 static void _spr_register(CPUPPCState *env, int num, const char *name,
91 USR_ARG(spr_callback *uea_read)
92 USR_ARG(spr_callback *uea_write)
93 SYS_ARG(spr_callback *oea_read)
94 SYS_ARG(spr_callback *oea_write)
95 SYS_ARG(spr_callback *hea_read)
96 SYS_ARG(spr_callback *hea_write)
97 KVM_ARG(uint64_t one_reg_id)
98 target_ulong initial_value)
99 {
100 ppc_spr_t *spr = &env->spr_cb[num];
101
102 /* No SPR should be registered twice. */
103 assert(spr->name == NULL);
104 assert(name != NULL);
105
106 spr->name = name;
107 spr->default_value = initial_value;
108 env->spr[num] = initial_value;
109
110 #ifdef CONFIG_TCG
111 spr->uea_read = uea_read;
112 spr->uea_write = uea_write;
113 # ifndef CONFIG_USER_ONLY
114 spr->oea_read = oea_read;
115 spr->oea_write = oea_write;
116 spr->hea_read = hea_read;
117 spr->hea_write = hea_write;
118 # endif
119 #endif
120 #ifdef CONFIG_KVM
121 spr->one_reg_id = one_reg_id;
122 #endif
123 }
124
125 /* spr_register_kvm_hv passes all required arguments. */
126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
127 oea_read, oea_write, hea_read, hea_write, \
128 one_reg_id, initial_value) \
129 _spr_register(env, num, name, \
130 USR_ARG(uea_read) USR_ARG(uea_write) \
131 SYS_ARG(oea_read) SYS_ARG(oea_write) \
132 SYS_ARG(hea_read) SYS_ARG(hea_write) \
133 KVM_ARG(one_reg_id) initial_value)
134
135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
137 oea_read, oea_write, one_reg_id, ival) \
138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
139 oea_write, oea_read, oea_write, one_reg_id, ival)
140
141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
142 #define spr_register_hv(env, num, name, uea_read, uea_write, \
143 oea_read, oea_write, hea_read, hea_write, ival) \
144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
145 oea_write, hea_read, hea_write, 0, ival)
146
147 #define spr_register(env, num, name, uea_read, uea_write, \
148 oea_read, oea_write, ival) \
149 spr_register_kvm(env, num, name, uea_read, uea_write, \
150 oea_read, oea_write, 0, ival)
151
152 /* Generic PowerPC SPRs */
153 static void register_generic_sprs(PowerPCCPU *cpu)
154 {
155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
156 CPUPPCState *env = &cpu->env;
157
158 /* Integer processing */
159 spr_register(env, SPR_XER, "XER",
160 &spr_read_xer, &spr_write_xer,
161 &spr_read_xer, &spr_write_xer,
162 0x00000000);
163 /* Branch control */
164 spr_register(env, SPR_LR, "LR",
165 &spr_read_lr, &spr_write_lr,
166 &spr_read_lr, &spr_write_lr,
167 0x00000000);
168 spr_register(env, SPR_CTR, "CTR",
169 &spr_read_ctr, &spr_write_ctr,
170 &spr_read_ctr, &spr_write_ctr,
171 0x00000000);
172 /* Interrupt processing */
173 spr_register(env, SPR_SRR0, "SRR0",
174 SPR_NOACCESS, SPR_NOACCESS,
175 &spr_read_generic, &spr_write_generic,
176 0x00000000);
177 spr_register(env, SPR_SRR1, "SRR1",
178 SPR_NOACCESS, SPR_NOACCESS,
179 &spr_read_generic, &spr_write_generic,
180 0x00000000);
181 /* Processor control */
182 spr_register(env, SPR_SPRG0, "SPRG0",
183 SPR_NOACCESS, SPR_NOACCESS,
184 &spr_read_generic, &spr_write_generic,
185 0x00000000);
186 spr_register(env, SPR_SPRG1, "SPRG1",
187 SPR_NOACCESS, SPR_NOACCESS,
188 &spr_read_generic, &spr_write_generic,
189 0x00000000);
190 spr_register(env, SPR_SPRG2, "SPRG2",
191 SPR_NOACCESS, SPR_NOACCESS,
192 &spr_read_generic, &spr_write_generic,
193 0x00000000);
194 spr_register(env, SPR_SPRG3, "SPRG3",
195 SPR_NOACCESS, SPR_NOACCESS,
196 &spr_read_generic, &spr_write_generic,
197 0x00000000);
198
199 spr_register(env, SPR_PVR, "PVR",
200 /* Linux permits userspace to read PVR */
201 #if defined(CONFIG_LINUX_USER)
202 &spr_read_generic,
203 #else
204 SPR_NOACCESS,
205 #endif
206 SPR_NOACCESS,
207 &spr_read_generic, SPR_NOACCESS,
208 pcc->pvr);
209
210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
211 if (pcc->svr != POWERPC_SVR_NONE) {
212 if (pcc->svr & POWERPC_SVR_E500) {
213 spr_register(env, SPR_E500_SVR, "SVR",
214 SPR_NOACCESS, SPR_NOACCESS,
215 &spr_read_generic, SPR_NOACCESS,
216 pcc->svr & ~POWERPC_SVR_E500);
217 } else {
218 spr_register(env, SPR_SVR, "SVR",
219 SPR_NOACCESS, SPR_NOACCESS,
220 &spr_read_generic, SPR_NOACCESS,
221 pcc->svr);
222 }
223 }
224
225 /* Time base */
226 spr_register(env, SPR_VTBL, "TBL",
227 &spr_read_tbl, SPR_NOACCESS,
228 &spr_read_tbl, SPR_NOACCESS,
229 0x00000000);
230 spr_register(env, SPR_TBL, "TBL",
231 &spr_read_tbl, SPR_NOACCESS,
232 &spr_read_tbl, &spr_write_tbl,
233 0x00000000);
234 spr_register(env, SPR_VTBU, "TBU",
235 &spr_read_tbu, SPR_NOACCESS,
236 &spr_read_tbu, SPR_NOACCESS,
237 0x00000000);
238 spr_register(env, SPR_TBU, "TBU",
239 &spr_read_tbu, SPR_NOACCESS,
240 &spr_read_tbu, &spr_write_tbu,
241 0x00000000);
242 }
243
244 /* SPR common to all non-embedded PowerPC, including 601 */
245 static void register_ne_601_sprs(CPUPPCState *env)
246 {
247 /* Exception processing */
248 spr_register_kvm(env, SPR_DSISR, "DSISR",
249 SPR_NOACCESS, SPR_NOACCESS,
250 &spr_read_generic, &spr_write_generic,
251 KVM_REG_PPC_DSISR, 0x00000000);
252 spr_register_kvm(env, SPR_DAR, "DAR",
253 SPR_NOACCESS, SPR_NOACCESS,
254 &spr_read_generic, &spr_write_generic,
255 KVM_REG_PPC_DAR, 0x00000000);
256 /* Timer */
257 spr_register(env, SPR_DECR, "DECR",
258 SPR_NOACCESS, SPR_NOACCESS,
259 &spr_read_decr, &spr_write_decr,
260 0x00000000);
261 }
262
263 /* Storage Description Register 1 */
264 static void register_sdr1_sprs(CPUPPCState *env)
265 {
266 #ifndef CONFIG_USER_ONLY
267 if (env->has_hv_mode) {
268 /*
269 * SDR1 is a hypervisor resource on CPUs which have a
270 * hypervisor mode
271 */
272 spr_register_hv(env, SPR_SDR1, "SDR1",
273 SPR_NOACCESS, SPR_NOACCESS,
274 SPR_NOACCESS, SPR_NOACCESS,
275 &spr_read_generic, &spr_write_sdr1,
276 0x00000000);
277 } else {
278 spr_register(env, SPR_SDR1, "SDR1",
279 SPR_NOACCESS, SPR_NOACCESS,
280 &spr_read_generic, &spr_write_sdr1,
281 0x00000000);
282 }
283 #endif
284 }
285
286 /* BATs 0-3 */
287 static void register_low_BATs(CPUPPCState *env)
288 {
289 #if !defined(CONFIG_USER_ONLY)
290 spr_register(env, SPR_IBAT0U, "IBAT0U",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_ibat, &spr_write_ibatu,
293 0x00000000);
294 spr_register(env, SPR_IBAT0L, "IBAT0L",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_ibat, &spr_write_ibatl,
297 0x00000000);
298 spr_register(env, SPR_IBAT1U, "IBAT1U",
299 SPR_NOACCESS, SPR_NOACCESS,
300 &spr_read_ibat, &spr_write_ibatu,
301 0x00000000);
302 spr_register(env, SPR_IBAT1L, "IBAT1L",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_ibat, &spr_write_ibatl,
305 0x00000000);
306 spr_register(env, SPR_IBAT2U, "IBAT2U",
307 SPR_NOACCESS, SPR_NOACCESS,
308 &spr_read_ibat, &spr_write_ibatu,
309 0x00000000);
310 spr_register(env, SPR_IBAT2L, "IBAT2L",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_ibat, &spr_write_ibatl,
313 0x00000000);
314 spr_register(env, SPR_IBAT3U, "IBAT3U",
315 SPR_NOACCESS, SPR_NOACCESS,
316 &spr_read_ibat, &spr_write_ibatu,
317 0x00000000);
318 spr_register(env, SPR_IBAT3L, "IBAT3L",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_ibat, &spr_write_ibatl,
321 0x00000000);
322 spr_register(env, SPR_DBAT0U, "DBAT0U",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_dbat, &spr_write_dbatu,
325 0x00000000);
326 spr_register(env, SPR_DBAT0L, "DBAT0L",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_dbat, &spr_write_dbatl,
329 0x00000000);
330 spr_register(env, SPR_DBAT1U, "DBAT1U",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_dbat, &spr_write_dbatu,
333 0x00000000);
334 spr_register(env, SPR_DBAT1L, "DBAT1L",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_dbat, &spr_write_dbatl,
337 0x00000000);
338 spr_register(env, SPR_DBAT2U, "DBAT2U",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_dbat, &spr_write_dbatu,
341 0x00000000);
342 spr_register(env, SPR_DBAT2L, "DBAT2L",
343 SPR_NOACCESS, SPR_NOACCESS,
344 &spr_read_dbat, &spr_write_dbatl,
345 0x00000000);
346 spr_register(env, SPR_DBAT3U, "DBAT3U",
347 SPR_NOACCESS, SPR_NOACCESS,
348 &spr_read_dbat, &spr_write_dbatu,
349 0x00000000);
350 spr_register(env, SPR_DBAT3L, "DBAT3L",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_dbat, &spr_write_dbatl,
353 0x00000000);
354 env->nb_BATs += 4;
355 #endif
356 }
357
358 /* BATs 4-7 */
359 static void register_high_BATs(CPUPPCState *env)
360 {
361 #if !defined(CONFIG_USER_ONLY)
362 spr_register(env, SPR_IBAT4U, "IBAT4U",
363 SPR_NOACCESS, SPR_NOACCESS,
364 &spr_read_ibat_h, &spr_write_ibatu_h,
365 0x00000000);
366 spr_register(env, SPR_IBAT4L, "IBAT4L",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_ibat_h, &spr_write_ibatl_h,
369 0x00000000);
370 spr_register(env, SPR_IBAT5U, "IBAT5U",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_ibat_h, &spr_write_ibatu_h,
373 0x00000000);
374 spr_register(env, SPR_IBAT5L, "IBAT5L",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_ibat_h, &spr_write_ibatl_h,
377 0x00000000);
378 spr_register(env, SPR_IBAT6U, "IBAT6U",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_ibat_h, &spr_write_ibatu_h,
381 0x00000000);
382 spr_register(env, SPR_IBAT6L, "IBAT6L",
383 SPR_NOACCESS, SPR_NOACCESS,
384 &spr_read_ibat_h, &spr_write_ibatl_h,
385 0x00000000);
386 spr_register(env, SPR_IBAT7U, "IBAT7U",
387 SPR_NOACCESS, SPR_NOACCESS,
388 &spr_read_ibat_h, &spr_write_ibatu_h,
389 0x00000000);
390 spr_register(env, SPR_IBAT7L, "IBAT7L",
391 SPR_NOACCESS, SPR_NOACCESS,
392 &spr_read_ibat_h, &spr_write_ibatl_h,
393 0x00000000);
394 spr_register(env, SPR_DBAT4U, "DBAT4U",
395 SPR_NOACCESS, SPR_NOACCESS,
396 &spr_read_dbat_h, &spr_write_dbatu_h,
397 0x00000000);
398 spr_register(env, SPR_DBAT4L, "DBAT4L",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_dbat_h, &spr_write_dbatl_h,
401 0x00000000);
402 spr_register(env, SPR_DBAT5U, "DBAT5U",
403 SPR_NOACCESS, SPR_NOACCESS,
404 &spr_read_dbat_h, &spr_write_dbatu_h,
405 0x00000000);
406 spr_register(env, SPR_DBAT5L, "DBAT5L",
407 SPR_NOACCESS, SPR_NOACCESS,
408 &spr_read_dbat_h, &spr_write_dbatl_h,
409 0x00000000);
410 spr_register(env, SPR_DBAT6U, "DBAT6U",
411 SPR_NOACCESS, SPR_NOACCESS,
412 &spr_read_dbat_h, &spr_write_dbatu_h,
413 0x00000000);
414 spr_register(env, SPR_DBAT6L, "DBAT6L",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_dbat_h, &spr_write_dbatl_h,
417 0x00000000);
418 spr_register(env, SPR_DBAT7U, "DBAT7U",
419 SPR_NOACCESS, SPR_NOACCESS,
420 &spr_read_dbat_h, &spr_write_dbatu_h,
421 0x00000000);
422 spr_register(env, SPR_DBAT7L, "DBAT7L",
423 SPR_NOACCESS, SPR_NOACCESS,
424 &spr_read_dbat_h, &spr_write_dbatl_h,
425 0x00000000);
426 env->nb_BATs += 4;
427 #endif
428 }
429
430 /* Softare table search registers */
431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
432 {
433 #if !defined(CONFIG_USER_ONLY)
434 env->nb_tlb = nb_tlbs;
435 env->nb_ways = nb_ways;
436 env->id_tlbs = 1;
437 env->tlb_type = TLB_6XX;
438 spr_register(env, SPR_DMISS, "DMISS",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, SPR_NOACCESS,
441 0x00000000);
442 spr_register(env, SPR_DCMP, "DCMP",
443 SPR_NOACCESS, SPR_NOACCESS,
444 &spr_read_generic, SPR_NOACCESS,
445 0x00000000);
446 spr_register(env, SPR_HASH1, "HASH1",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, SPR_NOACCESS,
449 0x00000000);
450 spr_register(env, SPR_HASH2, "HASH2",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, SPR_NOACCESS,
453 0x00000000);
454 spr_register(env, SPR_IMISS, "IMISS",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, SPR_NOACCESS,
457 0x00000000);
458 spr_register(env, SPR_ICMP, "ICMP",
459 SPR_NOACCESS, SPR_NOACCESS,
460 &spr_read_generic, SPR_NOACCESS,
461 0x00000000);
462 spr_register(env, SPR_RPA, "RPA",
463 SPR_NOACCESS, SPR_NOACCESS,
464 &spr_read_generic, &spr_write_generic,
465 0x00000000);
466 #endif
467 }
468
469 static void register_745_sprs(CPUPPCState *env)
470 {
471 /* SGPRs */
472 spr_register(env, SPR_SPRG4, "SPRG4",
473 SPR_NOACCESS, SPR_NOACCESS,
474 &spr_read_generic, &spr_write_generic,
475 0x00000000);
476 spr_register(env, SPR_SPRG5, "SPRG5",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 spr_register(env, SPR_SPRG6, "SPRG6",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 spr_register(env, SPR_SPRG7, "SPRG7",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
487 0x00000000);
488
489 /* Hardware implementation registers */
490 spr_register(env, SPR_HID0, "HID0",
491 SPR_NOACCESS, SPR_NOACCESS,
492 &spr_read_generic, &spr_write_generic,
493 0x00000000);
494
495 spr_register(env, SPR_HID1, "HID1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499
500 spr_register(env, SPR_HID2, "HID2",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_generic, &spr_write_generic,
503 0x00000000);
504 }
505
506 static void register_755_sprs(CPUPPCState *env)
507 {
508 /* L2 cache control */
509 spr_register(env, SPR_L2CR, "L2CR",
510 SPR_NOACCESS, SPR_NOACCESS,
511 &spr_read_generic, spr_access_nop,
512 0x00000000);
513
514 spr_register(env, SPR_L2PMCR, "L2PMCR",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518 }
519
520 /* SPR common to all 7xx PowerPC implementations */
521 static void register_7xx_sprs(CPUPPCState *env)
522 {
523 /* Breakpoints */
524 spr_register_kvm(env, SPR_DABR, "DABR",
525 SPR_NOACCESS, SPR_NOACCESS,
526 &spr_read_generic, &spr_write_generic,
527 KVM_REG_PPC_DABR, 0x00000000);
528
529 spr_register(env, SPR_IABR, "IABR",
530 SPR_NOACCESS, SPR_NOACCESS,
531 &spr_read_generic, &spr_write_generic,
532 0x00000000);
533 /* Cache management */
534 spr_register(env, SPR_ICTC, "ICTC",
535 SPR_NOACCESS, SPR_NOACCESS,
536 &spr_read_generic, &spr_write_generic,
537 0x00000000);
538 /* Performance monitors */
539 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_generic, &spr_write_generic,
542 0x00000000);
543
544 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
545 SPR_NOACCESS, SPR_NOACCESS,
546 &spr_read_generic, &spr_write_generic,
547 0x00000000);
548
549 spr_register(env, SPR_7XX_PMC1, "PMC1",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_generic, &spr_write_generic,
552 0x00000000);
553
554 spr_register(env, SPR_7XX_PMC2, "PMC2",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_generic, &spr_write_generic,
557 0x00000000);
558
559 spr_register(env, SPR_7XX_PMC3, "PMC3",
560 SPR_NOACCESS, SPR_NOACCESS,
561 &spr_read_generic, &spr_write_generic,
562 0x00000000);
563
564 spr_register(env, SPR_7XX_PMC4, "PMC4",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_generic, &spr_write_generic,
567 0x00000000);
568
569 spr_register(env, SPR_7XX_SIAR, "SIAR",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_generic, SPR_NOACCESS,
572 0x00000000);
573
574 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
575 &spr_read_ureg, SPR_NOACCESS,
576 &spr_read_ureg, SPR_NOACCESS,
577 0x00000000);
578
579 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
580 &spr_read_ureg, SPR_NOACCESS,
581 &spr_read_ureg, SPR_NOACCESS,
582 0x00000000);
583
584 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
585 &spr_read_ureg, SPR_NOACCESS,
586 &spr_read_ureg, SPR_NOACCESS,
587 0x00000000);
588
589 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
590 &spr_read_ureg, SPR_NOACCESS,
591 &spr_read_ureg, SPR_NOACCESS,
592 0x00000000);
593
594 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
595 &spr_read_ureg, SPR_NOACCESS,
596 &spr_read_ureg, SPR_NOACCESS,
597 0x00000000);
598
599 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
600 &spr_read_ureg, SPR_NOACCESS,
601 &spr_read_ureg, SPR_NOACCESS,
602 0x00000000);
603
604 spr_register(env, SPR_7XX_USIAR, "USIAR",
605 &spr_read_ureg, SPR_NOACCESS,
606 &spr_read_ureg, SPR_NOACCESS,
607 0x00000000);
608 /* External access control */
609 spr_register(env, SPR_EAR, "EAR",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_generic, &spr_write_generic,
612 0x00000000);
613
614 /* Hardware implementation registers */
615 spr_register(env, SPR_HID0, "HID0",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_generic, &spr_write_generic,
618 0x00000000);
619
620 spr_register(env, SPR_HID1, "HID1",
621 SPR_NOACCESS, SPR_NOACCESS,
622 &spr_read_generic, &spr_write_generic,
623 0x00000000);
624 }
625
626 #ifdef TARGET_PPC64
627 static void register_amr_sprs(CPUPPCState *env)
628 {
629 #ifndef CONFIG_USER_ONLY
630 /*
631 * Virtual Page Class Key protection
632 *
633 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
634 * userspace accessible, 29 is privileged. So we only need to set
635 * the kvm ONE_REG id on one of them, we use 29
636 */
637 spr_register(env, SPR_UAMR, "UAMR",
638 &spr_read_generic, &spr_write_amr,
639 &spr_read_generic, &spr_write_amr,
640 0);
641 spr_register_kvm_hv(env, SPR_AMR, "AMR",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_amr,
644 &spr_read_generic, &spr_write_generic,
645 KVM_REG_PPC_AMR, 0);
646 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_uamor,
649 &spr_read_generic, &spr_write_generic,
650 KVM_REG_PPC_UAMOR, 0);
651 spr_register_hv(env, SPR_AMOR, "AMOR",
652 SPR_NOACCESS, SPR_NOACCESS,
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0);
656 #endif /* !CONFIG_USER_ONLY */
657 }
658
659 static void register_iamr_sprs(CPUPPCState *env)
660 {
661 #ifndef CONFIG_USER_ONLY
662 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_generic, &spr_write_iamr,
665 &spr_read_generic, &spr_write_generic,
666 KVM_REG_PPC_IAMR, 0);
667 #endif /* !CONFIG_USER_ONLY */
668 }
669 #endif /* TARGET_PPC64 */
670
671 static void register_thrm_sprs(CPUPPCState *env)
672 {
673 /* Thermal management */
674 spr_register(env, SPR_THRM1, "THRM1",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_thrm, &spr_write_generic,
677 0x00000000);
678
679 spr_register(env, SPR_THRM2, "THRM2",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_thrm, &spr_write_generic,
682 0x00000000);
683
684 spr_register(env, SPR_THRM3, "THRM3",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_thrm, &spr_write_generic,
687 0x00000000);
688 }
689
690 /* SPR specific to PowerPC 604 implementation */
691 static void register_604_sprs(CPUPPCState *env)
692 {
693 /* Processor identification */
694 spr_register(env, SPR_PIR, "PIR",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_generic, &spr_write_pir,
697 0x00000000);
698 /* Breakpoints */
699 spr_register(env, SPR_IABR, "IABR",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
702 0x00000000);
703
704 spr_register_kvm(env, SPR_DABR, "DABR",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, &spr_write_generic,
707 KVM_REG_PPC_DABR, 0x00000000);
708 /* Performance counters */
709 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713
714 spr_register(env, SPR_7XX_PMC1, "PMC1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718
719 spr_register(env, SPR_7XX_PMC2, "PMC2",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723
724 spr_register(env, SPR_7XX_SIAR, "SIAR",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, SPR_NOACCESS,
727 0x00000000);
728
729 spr_register(env, SPR_SDA, "SDA",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, SPR_NOACCESS,
732 0x00000000);
733 /* External access control */
734 spr_register(env, SPR_EAR, "EAR",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738
739 /* Hardware implementation registers */
740 spr_register(env, SPR_HID0, "HID0",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 }
745
746 static void register_604e_sprs(CPUPPCState *env)
747 {
748 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_generic,
751 0x00000000);
752
753 spr_register(env, SPR_7XX_PMC3, "PMC3",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_generic, &spr_write_generic,
756 0x00000000);
757
758 spr_register(env, SPR_7XX_PMC4, "PMC4",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
762 /* Hardware implementation registers */
763 spr_register(env, SPR_HID1, "HID1",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic,
766 0x00000000);
767 }
768
769 /* SPR specific to PowerPC 603 implementation */
770 static void register_603_sprs(CPUPPCState *env)
771 {
772 /* External access control */
773 spr_register(env, SPR_EAR, "EAR",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_generic, &spr_write_generic,
776 0x00000000);
777 /* Breakpoints */
778 spr_register(env, SPR_IABR, "IABR",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_generic,
781 0x00000000);
782
783 spr_register(env, SPR_HID0, "HID0",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, &spr_write_generic,
786 0x00000000);
787
788 spr_register(env, SPR_HID1, "HID1",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_generic, &spr_write_generic,
791 0x00000000);
792 }
793
794 static void register_e300_sprs(CPUPPCState *env)
795 {
796 /* hardware implementation registers */
797 spr_register(env, SPR_HID2, "HID2",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_generic, &spr_write_generic,
800 0x00000000);
801 /* Breakpoints */
802 spr_register(env, SPR_DABR, "DABR",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
806
807 spr_register(env, SPR_DABR2, "DABR2",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
811
812 spr_register(env, SPR_IABR2, "IABR2",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_generic, &spr_write_generic,
815 0x00000000);
816
817 spr_register(env, SPR_IBCR, "IBCR",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_generic, &spr_write_generic,
820 0x00000000);
821
822 spr_register(env, SPR_DBCR, "DBCR",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
826 }
827
828 /* SPR specific to PowerPC G2 implementation */
829 static void register_G2_sprs(CPUPPCState *env)
830 {
831 /* Memory base address */
832 /* MBAR */
833 spr_register(env, SPR_MBAR, "MBAR",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_generic, &spr_write_generic,
836 0x00000000);
837 /* Exception processing */
838 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_generic, &spr_write_generic,
841 0x00000000);
842 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_generic, &spr_write_generic,
845 0x00000000);
846 /* Breakpoints */
847 spr_register(env, SPR_DABR, "DABR",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, &spr_write_generic,
850 0x00000000);
851
852 spr_register(env, SPR_DABR2, "DABR2",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, &spr_write_generic,
855 0x00000000);
856
857 spr_register(env, SPR_IABR, "IABR",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic, &spr_write_generic,
860 0x00000000);
861
862 spr_register(env, SPR_IABR2, "IABR2",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_generic,
865 0x00000000);
866
867 spr_register(env, SPR_IBCR, "IBCR",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, &spr_write_generic,
870 0x00000000);
871
872 spr_register(env, SPR_DBCR, "DBCR",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876
877 /* External access control */
878 spr_register(env, SPR_EAR, "EAR",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_generic,
881 0x00000000);
882 /* Hardware implementation register */
883 spr_register(env, SPR_HID0, "HID0",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887
888 spr_register(env, SPR_HID1, "HID1",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, &spr_write_generic,
891 0x00000000);
892
893 spr_register(env, SPR_HID2, "HID2",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_generic,
896 0x00000000);
897
898 /* SGPRs */
899 spr_register(env, SPR_SPRG4, "SPRG4",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, &spr_write_generic,
902 0x00000000);
903 spr_register(env, SPR_SPRG5, "SPRG5",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 spr_register(env, SPR_SPRG6, "SPRG6",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 spr_register(env, SPR_SPRG7, "SPRG7",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 }
916
917 static void register_74xx_sprs(CPUPPCState *env)
918 {
919 /* Breakpoints */
920 spr_register_kvm(env, SPR_DABR, "DABR",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 KVM_REG_PPC_DABR, 0x00000000);
924
925 spr_register(env, SPR_IABR, "IABR",
926 SPR_NOACCESS, SPR_NOACCESS,
927 &spr_read_generic, &spr_write_generic,
928 0x00000000);
929 /* Cache management */
930 spr_register(env, SPR_ICTC, "ICTC",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* Performance monitors */
935 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939
940 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944
945 spr_register(env, SPR_7XX_PMC1, "PMC1",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949
950 spr_register(env, SPR_7XX_PMC2, "PMC2",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954
955 spr_register(env, SPR_7XX_PMC3, "PMC3",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959
960 spr_register(env, SPR_7XX_PMC4, "PMC4",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964
965 spr_register(env, SPR_7XX_SIAR, "SIAR",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, SPR_NOACCESS,
968 0x00000000);
969
970 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
971 &spr_read_ureg, SPR_NOACCESS,
972 &spr_read_ureg, SPR_NOACCESS,
973 0x00000000);
974
975 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
976 &spr_read_ureg, SPR_NOACCESS,
977 &spr_read_ureg, SPR_NOACCESS,
978 0x00000000);
979
980 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
984
985 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
989
990 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
994
995 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
999
1000 spr_register(env, SPR_7XX_USIAR, "USIAR",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
1004 /* External access control */
1005 spr_register(env, SPR_EAR, "EAR",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009
1010 /* Processor identification */
1011 spr_register(env, SPR_PIR, "PIR",
1012 SPR_NOACCESS, SPR_NOACCESS,
1013 &spr_read_generic, &spr_write_pir,
1014 0x00000000);
1015
1016 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020
1021 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1022 &spr_read_ureg, SPR_NOACCESS,
1023 &spr_read_ureg, SPR_NOACCESS,
1024 0x00000000);
1025
1026 spr_register(env, SPR_BAMR, "BAMR",
1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030
1031 spr_register(env, SPR_MSSCR0, "MSSCR0",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* Hardware implementation registers */
1036 spr_register(env, SPR_HID0, "HID0",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040
1041 spr_register(env, SPR_HID1, "HID1",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* Altivec */
1046 spr_register(env, SPR_VRSAVE, "VRSAVE",
1047 &spr_read_generic, &spr_write_generic,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050
1051 spr_register(env, SPR_L2CR, "L2CR",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, spr_access_nop,
1054 0x00000000);
1055 }
1056
1057 static void register_l3_ctrl(CPUPPCState *env)
1058 {
1059 /* L3CR */
1060 spr_register(env, SPR_L3CR, "L3CR",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 /* L3ITCR0 */
1065 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1066 SPR_NOACCESS, SPR_NOACCESS,
1067 &spr_read_generic, &spr_write_generic,
1068 0x00000000);
1069 /* L3PM */
1070 spr_register(env, SPR_L3PM, "L3PM",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 &spr_read_generic, &spr_write_generic,
1073 0x00000000);
1074 }
1075
1076 static void register_usprg3_sprs(CPUPPCState *env)
1077 {
1078 spr_register(env, SPR_USPRG3, "USPRG3",
1079 &spr_read_ureg, SPR_NOACCESS,
1080 &spr_read_ureg, SPR_NOACCESS,
1081 0x00000000);
1082 }
1083
1084 static void register_usprgh_sprs(CPUPPCState *env)
1085 {
1086 spr_register(env, SPR_USPRG4, "USPRG4",
1087 &spr_read_ureg, SPR_NOACCESS,
1088 &spr_read_ureg, SPR_NOACCESS,
1089 0x00000000);
1090 spr_register(env, SPR_USPRG5, "USPRG5",
1091 &spr_read_ureg, SPR_NOACCESS,
1092 &spr_read_ureg, SPR_NOACCESS,
1093 0x00000000);
1094 spr_register(env, SPR_USPRG6, "USPRG6",
1095 &spr_read_ureg, SPR_NOACCESS,
1096 &spr_read_ureg, SPR_NOACCESS,
1097 0x00000000);
1098 spr_register(env, SPR_USPRG7, "USPRG7",
1099 &spr_read_ureg, SPR_NOACCESS,
1100 &spr_read_ureg, SPR_NOACCESS,
1101 0x00000000);
1102 }
1103
1104 /* PowerPC BookE SPR */
1105 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
1106 {
1107 const char *ivor_names[64] = {
1108 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1109 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1110 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1111 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1112 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1113 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1114 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1115 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1116 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1117 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1118 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1119 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1120 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1121 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1122 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1123 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1124 };
1125 #define SPR_BOOKE_IVORxx (-1)
1126 int ivor_sprn[64] = {
1127 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1128 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1129 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1130 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1131 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1132 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1133 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1134 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1135 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1136 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1137 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1138 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1139 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1140 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1141 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1142 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1143 };
1144 int i;
1145
1146 /* Interrupt processing */
1147 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* Debug */
1156 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160
1161 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165
1166 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 &spr_read_generic, &spr_write_generic,
1169 0x00000000);
1170
1171 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1174 0x00000000);
1175
1176 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_40x_dbcr0,
1179 0x00000000);
1180
1181 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185
1186 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
1190 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198
1199 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_clear,
1202 0x00000000);
1203 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 &spr_read_generic, &spr_write_generic,
1206 0x00000000);
1207 spr_register(env, SPR_BOOKE_ESR, "ESR",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_excp_prefix,
1214 0x00000000);
1215 /* Exception vectors */
1216 for (i = 0; i < 64; i++) {
1217 if (ivor_mask & (1ULL << i)) {
1218 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1219 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1220 exit(1);
1221 }
1222 spr_register(env, ivor_sprn[i], ivor_names[i],
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_excp_vector,
1225 0x00000000);
1226 }
1227 }
1228 spr_register(env, SPR_BOOKE_PID, "PID",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_booke_pid,
1231 0x00000000);
1232 spr_register(env, SPR_BOOKE_TCR, "TCR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_booke_tcr,
1235 0x00000000);
1236 spr_register(env, SPR_BOOKE_TSR, "TSR",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_generic, &spr_write_booke_tsr,
1239 0x00000000);
1240 /* Timer */
1241 spr_register(env, SPR_DECR, "DECR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_decr, &spr_write_decr,
1244 0x00000000);
1245 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 SPR_NOACCESS, &spr_write_generic,
1248 0x00000000);
1249 /* SPRGs */
1250 spr_register(env, SPR_USPRG0, "USPRG0",
1251 &spr_read_generic, &spr_write_generic,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 spr_register(env, SPR_SPRG4, "SPRG4",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 spr_register(env, SPR_SPRG5, "SPRG5",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
1262 spr_register(env, SPR_SPRG6, "SPRG6",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 0x00000000);
1266 spr_register(env, SPR_SPRG7, "SPRG7",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
1274 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 }
1279
1280 #if !defined(CONFIG_USER_ONLY)
1281 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1282 uint32_t maxsize, uint32_t flags,
1283 uint32_t nentries)
1284 {
1285 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1286 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1287 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1288 flags | nentries;
1289 }
1290 #endif /* !CONFIG_USER_ONLY */
1291
1292 /* BookE 2.06 storage control registers */
1293 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1294 uint32_t *tlbncfg, uint32_t mmucfg)
1295 {
1296 #if !defined(CONFIG_USER_ONLY)
1297 const char *mas_names[8] = {
1298 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1299 };
1300 int mas_sprn[8] = {
1301 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1302 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1303 };
1304 int i;
1305
1306 /* TLB assist registers */
1307 for (i = 0; i < 8; i++) {
1308 if (mas_mask & (1 << i)) {
1309 spr_register(env, mas_sprn[i], mas_names[i],
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic,
1312 (i == 2 && (env->insns_flags & PPC_64B))
1313 ? &spr_write_generic : &spr_write_generic32,
1314 0x00000000);
1315 }
1316 }
1317 if (env->nb_pids > 1) {
1318 spr_register(env, SPR_BOOKE_PID1, "PID1",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_booke_pid,
1321 0x00000000);
1322 }
1323 if (env->nb_pids > 2) {
1324 spr_register(env, SPR_BOOKE_PID2, "PID2",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_booke_pid,
1327 0x00000000);
1328 }
1329
1330 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_eplc,
1333 0x00000000);
1334 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_epsc,
1337 0x00000000);
1338
1339 spr_register(env, SPR_MMUCFG, "MMUCFG",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, SPR_NOACCESS,
1342 mmucfg);
1343 switch (env->nb_ways) {
1344 case 4:
1345 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, SPR_NOACCESS,
1348 tlbncfg[3]);
1349 /* Fallthru */
1350 case 3:
1351 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, SPR_NOACCESS,
1354 tlbncfg[2]);
1355 /* Fallthru */
1356 case 2:
1357 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, SPR_NOACCESS,
1360 tlbncfg[1]);
1361 /* Fallthru */
1362 case 1:
1363 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, SPR_NOACCESS,
1366 tlbncfg[0]);
1367 /* Fallthru */
1368 case 0:
1369 default:
1370 break;
1371 }
1372 #endif
1373 }
1374
1375 /* SPR specific to PowerPC 440 implementation */
1376 static void register_440_sprs(CPUPPCState *env)
1377 {
1378 /* Cache control */
1379 spr_register(env, SPR_440_DNV0, "DNV0",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383
1384 spr_register(env, SPR_440_DNV1, "DNV1",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388
1389 spr_register(env, SPR_440_DNV2, "DNV2",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393
1394 spr_register(env, SPR_440_DNV3, "DNV3",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398
1399 spr_register(env, SPR_440_DTV0, "DTV0",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403
1404 spr_register(env, SPR_440_DTV1, "DTV1",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
1408
1409 spr_register(env, SPR_440_DTV2, "DTV2",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413
1414 spr_register(env, SPR_440_DTV3, "DTV3",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
1418
1419 spr_register(env, SPR_440_DVLIM, "DVLIM",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423
1424 spr_register(env, SPR_440_INV0, "INV0",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428
1429 spr_register(env, SPR_440_INV1, "INV1",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433
1434 spr_register(env, SPR_440_INV2, "INV2",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438
1439 spr_register(env, SPR_440_INV3, "INV3",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443
1444 spr_register(env, SPR_440_ITV0, "ITV0",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448
1449 spr_register(env, SPR_440_ITV1, "ITV1",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453
1454 spr_register(env, SPR_440_ITV2, "ITV2",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458
1459 spr_register(env, SPR_440_ITV3, "ITV3",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463
1464 spr_register(env, SPR_440_IVLIM, "IVLIM",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468 /* Cache debug */
1469 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, SPR_NOACCESS,
1472 0x00000000);
1473
1474 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, SPR_NOACCESS,
1477 0x00000000);
1478
1479 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, SPR_NOACCESS,
1482 0x00000000);
1483
1484 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, SPR_NOACCESS,
1487 0x00000000);
1488
1489 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, SPR_NOACCESS,
1492 0x00000000);
1493
1494 spr_register(env, SPR_440_DBDR, "DBDR",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* Processor control */
1499 spr_register(env, SPR_4xx_CCR0, "CCR0",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, SPR_NOACCESS,
1506 0x00000000);
1507 /* Storage control */
1508 spr_register(env, SPR_440_MMUCR, "MMUCR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512
1513 /* Processor identification */
1514 spr_register(env, SPR_BOOKE_PIR, "PIR",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_pir,
1517 0x00000000);
1518
1519 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523
1524 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
1528
1529 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_generic,
1532 0x00000000);
1533
1534 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 }
1539
1540 /* SPR shared between PowerPC 40x implementations */
1541 static void register_40x_sprs(CPUPPCState *env)
1542 {
1543 /* Cache */
1544 /* not emulated, as QEMU do not emulate caches */
1545 spr_register(env, SPR_40x_DCCR, "DCCR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 /* not emulated, as QEMU do not emulate caches */
1550 spr_register(env, SPR_40x_ICCR, "ICCR",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
1554 /* not emulated, as QEMU do not emulate caches */
1555 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, SPR_NOACCESS,
1558 0x00000000);
1559 /* Exception */
1560 spr_register(env, SPR_40x_DEAR, "DEAR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 spr_register(env, SPR_40x_ESR, "ESR",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 0x00000000);
1568 spr_register(env, SPR_40x_EVPR, "EVPR",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_excp_prefix,
1571 0x00000000);
1572 spr_register(env, SPR_40x_SRR2, "SRR2",
1573 &spr_read_generic, &spr_write_generic,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 spr_register(env, SPR_40x_SRR3, "SRR3",
1577 &spr_read_generic, &spr_write_generic,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580 /* Timers */
1581 spr_register(env, SPR_40x_PIT, "PIT",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_40x_pit, &spr_write_40x_pit,
1584 0x00000000);
1585 spr_register(env, SPR_40x_TCR, "TCR",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_40x_tcr,
1588 0x00000000);
1589 spr_register(env, SPR_40x_TSR, "TSR",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_40x_tsr,
1592 0x00000000);
1593 }
1594
1595 /* SPR specific to PowerPC 405 implementation */
1596 static void register_405_sprs(CPUPPCState *env)
1597 {
1598 /* MMU */
1599 spr_register(env, SPR_40x_PID, "PID",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_40x_pid,
1602 0x00000000);
1603 spr_register(env, SPR_4xx_CCR0, "CCR0",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00700000);
1607 /* Debug interface */
1608 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_40x_dbcr0,
1611 0x00000000);
1612
1613 spr_register(env, SPR_405_DBCR1, "DBCR1",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic,
1616 0x00000000);
1617
1618 spr_register(env, SPR_40x_DBSR, "DBSR",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_clear,
1621 /* Last reset was system reset */
1622 0x00000300);
1623
1624 spr_register(env, SPR_40x_DAC1, "DAC1",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 spr_register(env, SPR_40x_DAC2, "DAC2",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, &spr_write_generic,
1631 0x00000000);
1632
1633 spr_register(env, SPR_405_DVC1, "DVC1",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, &spr_write_generic,
1636 0x00000000);
1637
1638 spr_register(env, SPR_405_DVC2, "DVC2",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642
1643 spr_register(env, SPR_40x_IAC1, "IAC1",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 spr_register(env, SPR_40x_IAC2, "IAC2",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651
1652 spr_register(env, SPR_405_IAC3, "IAC3",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656
1657 spr_register(env, SPR_405_IAC4, "IAC4",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* Storage control */
1662 spr_register(env, SPR_405_SLER, "SLER",
1663 SPR_NOACCESS, SPR_NOACCESS,
1664 &spr_read_generic, &spr_write_40x_sler,
1665 0x00000000);
1666 spr_register(env, SPR_40x_ZPR, "ZPR",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1669 0x00000000);
1670
1671 spr_register(env, SPR_405_SU0R, "SU0R",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 /* SPRG */
1676 spr_register(env, SPR_USPRG0, "USPRG0",
1677 &spr_read_ureg, SPR_NOACCESS,
1678 &spr_read_ureg, SPR_NOACCESS,
1679 0x00000000);
1680 spr_register(env, SPR_SPRG4, "SPRG4",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684 spr_register(env, SPR_SPRG5, "SPRG5",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 spr_register(env, SPR_SPRG6, "SPRG6",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 spr_register(env, SPR_SPRG7, "SPRG7",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 spr_read_generic, &spr_write_generic,
1695 0x00000000);
1696
1697 /* Bus access control */
1698 /* not emulated, as QEMU never does speculative access */
1699 spr_register(env, SPR_40x_SGR, "SGR",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0xFFFFFFFF);
1703 /* not emulated, as QEMU do not emulate caches */
1704 spr_register(env, SPR_40x_DCWR, "DCWR",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 }
1709
1710
1711 static void register_5xx_8xx_sprs(CPUPPCState *env)
1712 {
1713 /* Exception processing */
1714 spr_register_kvm(env, SPR_DSISR, "DSISR",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 KVM_REG_PPC_DSISR, 0x00000000);
1718 spr_register_kvm(env, SPR_DAR, "DAR",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 KVM_REG_PPC_DAR, 0x00000000);
1722 /* Timer */
1723 spr_register(env, SPR_DECR, "DECR",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_decr, &spr_write_decr,
1726 0x00000000);
1727
1728 spr_register(env, SPR_MPC_EIE, "EIE",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732
1733 spr_register(env, SPR_MPC_EID, "EID",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737
1738 spr_register(env, SPR_MPC_NRI, "NRI",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742
1743 spr_register(env, SPR_MPC_CMPA, "CMPA",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747
1748 spr_register(env, SPR_MPC_CMPB, "CMPB",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752
1753 spr_register(env, SPR_MPC_CMPC, "CMPC",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757
1758 spr_register(env, SPR_MPC_CMPD, "CMPD",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762
1763 spr_register(env, SPR_MPC_ECR, "ECR",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767
1768 spr_register(env, SPR_MPC_DER, "DER",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772
1773 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777
1778 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782
1783 spr_register(env, SPR_MPC_CMPE, "CMPE",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787
1788 spr_register(env, SPR_MPC_CMPF, "CMPF",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792
1793 spr_register(env, SPR_MPC_CMPG, "CMPG",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
1797
1798 spr_register(env, SPR_MPC_CMPH, "CMPH",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802
1803 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
1807
1808 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812
1813 spr_register(env, SPR_MPC_BAR, "BAR",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817
1818 spr_register(env, SPR_MPC_DPDR, "DPDR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822
1823 spr_register(env, SPR_MPC_IMMR, "IMMR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 }
1828
1829 static void register_5xx_sprs(CPUPPCState *env)
1830 {
1831 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835
1836 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, &spr_write_generic,
1839 0x00000000);
1840
1841 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_generic,
1844 0x00000000);
1845
1846 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1847 SPR_NOACCESS, SPR_NOACCESS,
1848 &spr_read_generic, &spr_write_generic,
1849 0x00000000);
1850
1851 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
1855
1856 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, &spr_write_generic,
1859 0x00000000);
1860
1861 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_generic, &spr_write_generic,
1864 0x00000000);
1865
1866 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870
1871 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1872 SPR_NOACCESS, SPR_NOACCESS,
1873 &spr_read_generic, &spr_write_generic,
1874 0x00000000);
1875
1876 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1877 SPR_NOACCESS, SPR_NOACCESS,
1878 &spr_read_generic, &spr_write_generic,
1879 0x00000000);
1880
1881 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
1885
1886 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
1889 0x00000000);
1890
1891 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895
1896 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
1900
1901 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, &spr_write_generic,
1904 0x00000000);
1905
1906 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1907 SPR_NOACCESS, SPR_NOACCESS,
1908 &spr_read_generic, &spr_write_generic,
1909 0x00000000);
1910
1911 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, &spr_write_generic,
1914 0x00000000);
1915
1916 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1917 SPR_NOACCESS, SPR_NOACCESS,
1918 &spr_read_generic, &spr_write_generic,
1919 0x00000000);
1920
1921 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925
1926 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1927 SPR_NOACCESS, SPR_NOACCESS,
1928 &spr_read_generic, &spr_write_generic,
1929 0x00000000);
1930
1931 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1932 SPR_NOACCESS, SPR_NOACCESS,
1933 &spr_read_generic, &spr_write_generic,
1934 0x00000000);
1935 }
1936
1937 static void register_8xx_sprs(CPUPPCState *env)
1938 {
1939
1940 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944
1945 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 &spr_read_generic, &spr_write_generic,
1948 0x00000000);
1949
1950 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1951 SPR_NOACCESS, SPR_NOACCESS,
1952 &spr_read_generic, &spr_write_generic,
1953 0x00000000);
1954
1955 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959
1960 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
1964
1965 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_generic,
1968 0x00000000);
1969
1970 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974
1975 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979
1980 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, &spr_write_generic,
1983 0x00000000);
1984
1985 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989
1990 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994
1995 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999
2000 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004
2005 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009
2010 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014
2015 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0x00000000);
2019
2020 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024
2025 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029
2030 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034
2035 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039
2040 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0x00000000);
2044
2045 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2049
2050 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0x00000000);
2054
2055 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059
2060 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 }
2065
2066 /*
2067 * AMR => SPR 29 (Power 2.04)
2068 * CTRL => SPR 136 (Power 2.04)
2069 * CTRL => SPR 152 (Power 2.04)
2070 * SCOMC => SPR 276 (64 bits ?)
2071 * SCOMD => SPR 277 (64 bits ?)
2072 * TBU40 => SPR 286 (Power 2.04 hypv)
2073 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2074 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2075 * HDSISR => SPR 306 (Power 2.04 hypv)
2076 * HDAR => SPR 307 (Power 2.04 hypv)
2077 * PURR => SPR 309 (Power 2.04 hypv)
2078 * HDEC => SPR 310 (Power 2.04 hypv)
2079 * HIOR => SPR 311 (hypv)
2080 * RMOR => SPR 312 (970)
2081 * HRMOR => SPR 313 (Power 2.04 hypv)
2082 * HSRR0 => SPR 314 (Power 2.04 hypv)
2083 * HSRR1 => SPR 315 (Power 2.04 hypv)
2084 * LPIDR => SPR 317 (970)
2085 * EPR => SPR 702 (Power 2.04 emb)
2086 * perf => 768-783 (Power 2.04)
2087 * perf => 784-799 (Power 2.04)
2088 * PPR => SPR 896 (Power 2.04)
2089 * DABRX => 1015 (Power 2.04 hypv)
2090 * FPECR => SPR 1022 (?)
2091 * ... and more (thermal management, performance counters, ...)
2092 */
2093
2094 /*****************************************************************************/
2095 /* Exception vectors models */
2096 static void init_excp_4xx_softmmu(CPUPPCState *env)
2097 {
2098 #if !defined(CONFIG_USER_ONLY)
2099 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2100 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2101 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2102 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2103 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2104 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2105 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2106 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2107 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2108 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2109 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2110 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2111 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2112 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2113 env->ivor_mask = 0x0000FFF0UL;
2114 env->ivpr_mask = 0xFFFF0000UL;
2115 /* Hardware reset vector */
2116 env->hreset_vector = 0xFFFFFFFCUL;
2117 #endif
2118 }
2119
2120 static void init_excp_MPC5xx(CPUPPCState *env)
2121 {
2122 #if !defined(CONFIG_USER_ONLY)
2123 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2125 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2126 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2127 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2128 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2129 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2130 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2131 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2132 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2133 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2134 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2135 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2136 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2137 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2138 env->ivor_mask = 0x0000FFF0UL;
2139 env->ivpr_mask = 0xFFFF0000UL;
2140 /* Hardware reset vector */
2141 env->hreset_vector = 0x00000100UL;
2142 #endif
2143 }
2144
2145 static void init_excp_MPC8xx(CPUPPCState *env)
2146 {
2147 #if !defined(CONFIG_USER_ONLY)
2148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2149 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2150 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2151 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2152 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2153 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2154 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2155 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2156 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2158 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2159 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2160 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2161 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2162 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2163 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2164 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2165 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2166 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2167 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2168 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2169 env->ivor_mask = 0x0000FFF0UL;
2170 env->ivpr_mask = 0xFFFF0000UL;
2171 /* Hardware reset vector */
2172 env->hreset_vector = 0x00000100UL;
2173 #endif
2174 }
2175
2176 static void init_excp_G2(CPUPPCState *env)
2177 {
2178 #if !defined(CONFIG_USER_ONLY)
2179 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2180 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2181 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2182 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2183 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2184 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2185 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2186 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2187 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2188 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2189 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2190 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2191 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2192 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2193 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2194 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2195 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2196 /* Hardware reset vector */
2197 env->hreset_vector = 0x00000100UL;
2198 #endif
2199 }
2200
2201 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2202 {
2203 #if !defined(CONFIG_USER_ONLY)
2204 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2205 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2206 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2207 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2208 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2209 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2210 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2211 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2212 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2213 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2214 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2215 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2216 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2217 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2218 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2219 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2220 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2221 /*
2222 * These two are the same IVOR as POWERPC_EXCP_VPU and
2223 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
2224 * powerpc_excp().
2225 */
2226 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2227 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2228
2229 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2230 env->ivor_mask = 0x0000FFF7UL;
2231 env->ivpr_mask = ivpr_mask;
2232 /* Hardware reset vector */
2233 env->hreset_vector = 0xFFFFFFFCUL;
2234 #endif
2235 }
2236
2237 static void init_excp_BookE(CPUPPCState *env)
2238 {
2239 #if !defined(CONFIG_USER_ONLY)
2240 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2241 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2242 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2243 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2244 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2245 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2246 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2247 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2248 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2249 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2250 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2251 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2252 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2253 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2254 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2255 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2256 env->ivor_mask = 0x0000FFF0UL;
2257 env->ivpr_mask = 0xFFFF0000UL;
2258 /* Hardware reset vector */
2259 env->hreset_vector = 0xFFFFFFFCUL;
2260 #endif
2261 }
2262
2263 static void init_excp_603(CPUPPCState *env)
2264 {
2265 #if !defined(CONFIG_USER_ONLY)
2266 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2267 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2268 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2269 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2270 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2271 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2272 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2273 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2274 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2275 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2276 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2277 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2278 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2279 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2280 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2281 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2282 /* Hardware reset vector */
2283 env->hreset_vector = 0x00000100UL;
2284 #endif
2285 }
2286
2287 static void init_excp_604(CPUPPCState *env)
2288 {
2289 #if !defined(CONFIG_USER_ONLY)
2290 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2291 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2292 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2293 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2294 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2295 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2296 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2297 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2298 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2299 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2300 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2301 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2302 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2303 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2304 /* Hardware reset vector */
2305 env->hreset_vector = 0x00000100UL;
2306 #endif
2307 }
2308
2309 static void init_excp_7x0(CPUPPCState *env)
2310 {
2311 #if !defined(CONFIG_USER_ONLY)
2312 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2313 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2314 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2315 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2321 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2322 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2323 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2324 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2325 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2326 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2327 /* Hardware reset vector */
2328 env->hreset_vector = 0x00000100UL;
2329 #endif
2330 }
2331
2332 static void init_excp_750cl(CPUPPCState *env)
2333 {
2334 #if !defined(CONFIG_USER_ONLY)
2335 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2336 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2337 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2338 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2339 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2340 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2341 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2342 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2343 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2344 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2345 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2346 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2349 /* Hardware reset vector */
2350 env->hreset_vector = 0x00000100UL;
2351 #endif
2352 }
2353
2354 static void init_excp_750cx(CPUPPCState *env)
2355 {
2356 #if !defined(CONFIG_USER_ONLY)
2357 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2358 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2359 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2360 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2361 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2362 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2363 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2364 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2365 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2366 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2367 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2368 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2369 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2370 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2371 /* Hardware reset vector */
2372 env->hreset_vector = 0x00000100UL;
2373 #endif
2374 }
2375
2376 /* XXX: Check if this is correct */
2377 static void init_excp_7x5(CPUPPCState *env)
2378 {
2379 #if !defined(CONFIG_USER_ONLY)
2380 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2381 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2382 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2383 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2384 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2385 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2386 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2387 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2388 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2389 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2390 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2391 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2392 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2393 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2394 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2395 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2396 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2397 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2398 /* Hardware reset vector */
2399 env->hreset_vector = 0x00000100UL;
2400 #endif
2401 }
2402
2403 static void init_excp_7400(CPUPPCState *env)
2404 {
2405 #if !defined(CONFIG_USER_ONLY)
2406 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2407 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2408 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2409 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2410 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2411 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2412 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2413 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2414 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2415 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2416 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2417 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2418 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2419 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2420 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2421 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2422 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2423 /* Hardware reset vector */
2424 env->hreset_vector = 0x00000100UL;
2425 #endif
2426 }
2427
2428 static void init_excp_7450(CPUPPCState *env)
2429 {
2430 #if !defined(CONFIG_USER_ONLY)
2431 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2432 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2433 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2434 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2435 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2436 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2437 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2438 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2439 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2440 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2441 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2442 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2443 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2444 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2445 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2446 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2447 /* Hardware reset vector */
2448 env->hreset_vector = 0x00000100UL;
2449 #endif
2450 }
2451
2452 #if defined(TARGET_PPC64)
2453 static void init_excp_970(CPUPPCState *env)
2454 {
2455 #if !defined(CONFIG_USER_ONLY)
2456 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2457 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2458 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2459 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2460 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2461 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2462 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2463 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2464 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2465 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2466 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2467 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2468 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2469 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2470 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2471 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2472 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2473 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2474 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2475 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2476 /* Hardware reset vector */
2477 env->hreset_vector = 0x0000000000000100ULL;
2478 #endif
2479 }
2480
2481 static void init_excp_POWER7(CPUPPCState *env)
2482 {
2483 #if !defined(CONFIG_USER_ONLY)
2484 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2485 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2486 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2487 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2488 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2489 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2490 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2491 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2492 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2493 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2494 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2495 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2496 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2497 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2498 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2499 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2500 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2501 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2502 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2503 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2504 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2505 /* Hardware reset vector */
2506 env->hreset_vector = 0x0000000000000100ULL;
2507 #endif
2508 }
2509
2510 static void init_excp_POWER8(CPUPPCState *env)
2511 {
2512 init_excp_POWER7(env);
2513
2514 #if !defined(CONFIG_USER_ONLY)
2515 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2516 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2517 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2518 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2519 #endif
2520 }
2521
2522 static void init_excp_POWER9(CPUPPCState *env)
2523 {
2524 init_excp_POWER8(env);
2525
2526 #if !defined(CONFIG_USER_ONLY)
2527 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2528 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2529 #endif
2530 }
2531
2532 static void init_excp_POWER10(CPUPPCState *env)
2533 {
2534 init_excp_POWER9(env);
2535 }
2536
2537 #endif
2538
2539 /*****************************************************************************/
2540 /* Power management enable checks */
2541 static int check_pow_none(CPUPPCState *env)
2542 {
2543 return 0;
2544 }
2545
2546 static int check_pow_nocheck(CPUPPCState *env)
2547 {
2548 return 1;
2549 }
2550
2551 static int check_pow_hid0(CPUPPCState *env)
2552 {
2553 if (env->spr[SPR_HID0] & 0x00E00000) {
2554 return 1;
2555 }
2556
2557 return 0;
2558 }
2559
2560 static int check_pow_hid0_74xx(CPUPPCState *env)
2561 {
2562 if (env->spr[SPR_HID0] & 0x00600000) {
2563 return 1;
2564 }
2565
2566 return 0;
2567 }
2568
2569 /*****************************************************************************/
2570 /* PowerPC implementations definitions */
2571
2572 #define POWERPC_FAMILY(_name) \
2573 static void \
2574 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2575 \
2576 static const TypeInfo \
2577 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2578 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2579 .parent = TYPE_POWERPC_CPU, \
2580 .abstract = true, \
2581 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2582 }; \
2583 \
2584 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2585 { \
2586 type_register_static( \
2587 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2588 } \
2589 \
2590 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2591 \
2592 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2593
2594 static void init_proc_405(CPUPPCState *env)
2595 {
2596 register_40x_sprs(env);
2597 register_405_sprs(env);
2598 register_usprgh_sprs(env);
2599
2600 /* Memory management */
2601 #if !defined(CONFIG_USER_ONLY)
2602 env->nb_tlb = 64;
2603 env->nb_ways = 1;
2604 env->id_tlbs = 0;
2605 env->tlb_type = TLB_EMB;
2606 #endif
2607 init_excp_4xx_softmmu(env);
2608 env->dcache_line_size = 32;
2609 env->icache_line_size = 32;
2610 /* Allocate hardware IRQ controller */
2611 ppc40x_irq_init(env_archcpu(env));
2612
2613 SET_FIT_PERIOD(8, 12, 16, 20);
2614 SET_WDT_PERIOD(16, 20, 24, 28);
2615 }
2616
2617 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2618 {
2619 DeviceClass *dc = DEVICE_CLASS(oc);
2620 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2621
2622 dc->desc = "PowerPC 405";
2623 pcc->init_proc = init_proc_405;
2624 pcc->check_pow = check_pow_nocheck;
2625 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2626 PPC_DCR | PPC_WRTEE |
2627 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2628 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2629 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2630 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2631 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2632 pcc->msr_mask = (1ull << MSR_WE) |
2633 (1ull << MSR_CE) |
2634 (1ull << MSR_EE) |
2635 (1ull << MSR_PR) |
2636 (1ull << MSR_FP) |
2637 (1ull << MSR_ME) |
2638 (1ull << MSR_DWE) |
2639 (1ull << MSR_DE) |
2640 (1ull << MSR_IR) |
2641 (1ull << MSR_DR);
2642 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2643 pcc->excp_model = POWERPC_EXCP_40x;
2644 pcc->bus_model = PPC_FLAGS_INPUT_405;
2645 pcc->bfd_mach = bfd_mach_ppc_403;
2646 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2647 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2648 }
2649
2650 static void init_proc_440EP(CPUPPCState *env)
2651 {
2652 register_BookE_sprs(env, 0x000000000000FFFFULL);
2653 register_440_sprs(env);
2654 register_usprgh_sprs(env);
2655
2656 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2661 SPR_NOACCESS, SPR_NOACCESS,
2662 &spr_read_generic, &spr_write_generic,
2663 0x00000000);
2664 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2665 SPR_NOACCESS, SPR_NOACCESS,
2666 &spr_read_generic, &spr_write_generic,
2667 0x00000000);
2668
2669 spr_register(env, SPR_440_CCR1, "CCR1",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 /* Memory management */
2674 #if !defined(CONFIG_USER_ONLY)
2675 env->nb_tlb = 64;
2676 env->nb_ways = 1;
2677 env->id_tlbs = 0;
2678 env->tlb_type = TLB_EMB;
2679 #endif
2680 init_excp_BookE(env);
2681 env->dcache_line_size = 32;
2682 env->icache_line_size = 32;
2683 ppc40x_irq_init(env_archcpu(env));
2684
2685 SET_FIT_PERIOD(12, 16, 20, 24);
2686 SET_WDT_PERIOD(20, 24, 28, 32);
2687 }
2688
2689 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2690 {
2691 DeviceClass *dc = DEVICE_CLASS(oc);
2692 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2693
2694 dc->desc = "PowerPC 440 EP";
2695 pcc->init_proc = init_proc_440EP;
2696 pcc->check_pow = check_pow_nocheck;
2697 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2698 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2699 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2700 PPC_FLOAT_STFIWX |
2701 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2702 PPC_CACHE | PPC_CACHE_ICBI |
2703 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2704 PPC_MEM_TLBSYNC | PPC_MFTB |
2705 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2706 PPC_440_SPEC;
2707 pcc->msr_mask = (1ull << MSR_POW) |
2708 (1ull << MSR_CE) |
2709 (1ull << MSR_EE) |
2710 (1ull << MSR_PR) |
2711 (1ull << MSR_FP) |
2712 (1ull << MSR_ME) |
2713 (1ull << MSR_FE0) |
2714 (1ull << MSR_DWE) |
2715 (1ull << MSR_DE) |
2716 (1ull << MSR_FE1) |
2717 (1ull << MSR_IR) |
2718 (1ull << MSR_DR);
2719 pcc->mmu_model = POWERPC_MMU_BOOKE;
2720 pcc->excp_model = POWERPC_EXCP_BOOKE;
2721 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2722 pcc->bfd_mach = bfd_mach_ppc_403;
2723 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2724 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2725 }
2726
2727 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2728 {
2729 DeviceClass *dc = DEVICE_CLASS(oc);
2730 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2731
2732 dc->desc = "PowerPC 460 EX";
2733 pcc->init_proc = init_proc_440EP;
2734 pcc->check_pow = check_pow_nocheck;
2735 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2736 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2737 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2738 PPC_FLOAT_STFIWX |
2739 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2740 PPC_CACHE | PPC_CACHE_ICBI |
2741 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2742 PPC_MEM_TLBSYNC | PPC_MFTB |
2743 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2744 PPC_440_SPEC;
2745 pcc->msr_mask = (1ull << MSR_POW) |
2746 (1ull << MSR_CE) |
2747 (1ull << MSR_EE) |
2748 (1ull << MSR_PR) |
2749 (1ull << MSR_FP) |
2750 (1ull << MSR_ME) |
2751 (1ull << MSR_FE0) |
2752 (1ull << MSR_DWE) |
2753 (1ull << MSR_DE) |
2754 (1ull << MSR_FE1) |
2755 (1ull << MSR_IR) |
2756 (1ull << MSR_DR);
2757 pcc->mmu_model = POWERPC_MMU_BOOKE;
2758 pcc->excp_model = POWERPC_EXCP_BOOKE;
2759 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2760 pcc->bfd_mach = bfd_mach_ppc_403;
2761 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2762 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2763 }
2764
2765 static void init_proc_440GP(CPUPPCState *env)
2766 {
2767 register_BookE_sprs(env, 0x000000000000FFFFULL);
2768 register_440_sprs(env);
2769 register_usprgh_sprs(env);
2770
2771 /* Memory management */
2772 #if !defined(CONFIG_USER_ONLY)
2773 env->nb_tlb = 64;
2774 env->nb_ways = 1;
2775 env->id_tlbs = 0;
2776 env->tlb_type = TLB_EMB;
2777 #endif
2778 init_excp_BookE(env);
2779 env->dcache_line_size = 32;
2780 env->icache_line_size = 32;
2781 /* XXX: TODO: allocate internal IRQ controller */
2782
2783 SET_FIT_PERIOD(12, 16, 20, 24);
2784 SET_WDT_PERIOD(20, 24, 28, 32);
2785 }
2786
2787 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2788 {
2789 DeviceClass *dc = DEVICE_CLASS(oc);
2790 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2791
2792 dc->desc = "PowerPC 440 GP";
2793 pcc->init_proc = init_proc_440GP;
2794 pcc->check_pow = check_pow_nocheck;
2795 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2796 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2797 PPC_CACHE | PPC_CACHE_ICBI |
2798 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2799 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2800 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2801 PPC_440_SPEC;
2802 pcc->msr_mask = (1ull << MSR_POW) |
2803 (1ull << MSR_CE) |
2804 (1ull << MSR_EE) |
2805 (1ull << MSR_PR) |
2806 (1ull << MSR_FP) |
2807 (1ull << MSR_ME) |
2808 (1ull << MSR_FE0) |
2809 (1ull << MSR_DWE) |
2810 (1ull << MSR_DE) |
2811 (1ull << MSR_FE1) |
2812 (1ull << MSR_IR) |
2813 (1ull << MSR_DR);
2814 pcc->mmu_model = POWERPC_MMU_BOOKE;
2815 pcc->excp_model = POWERPC_EXCP_BOOKE;
2816 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2817 pcc->bfd_mach = bfd_mach_ppc_403;
2818 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2819 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2820 }
2821
2822 static void init_proc_440x5(CPUPPCState *env)
2823 {
2824 register_BookE_sprs(env, 0x000000000000FFFFULL);
2825 register_440_sprs(env);
2826 register_usprgh_sprs(env);
2827
2828 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2829 SPR_NOACCESS, SPR_NOACCESS,
2830 &spr_read_generic, &spr_write_generic,
2831 0x00000000);
2832 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2833 SPR_NOACCESS, SPR_NOACCESS,
2834 &spr_read_generic, &spr_write_generic,
2835 0x00000000);
2836 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2837 SPR_NOACCESS, SPR_NOACCESS,
2838 &spr_read_generic, &spr_write_generic,
2839 0x00000000);
2840
2841 spr_register(env, SPR_440_CCR1, "CCR1",
2842 SPR_NOACCESS, SPR_NOACCESS,
2843 &spr_read_generic, &spr_write_generic,
2844 0x00000000);
2845 /* Memory management */
2846 #if !defined(CONFIG_USER_ONLY)
2847 env->nb_tlb = 64;
2848 env->nb_ways = 1;
2849 env->id_tlbs = 0;
2850 env->tlb_type = TLB_EMB;
2851 #endif
2852 init_excp_BookE(env);
2853 env->dcache_line_size = 32;
2854 env->icache_line_size = 32;
2855 ppc40x_irq_init(env_archcpu(env));
2856
2857 SET_FIT_PERIOD(12, 16, 20, 24);
2858 SET_WDT_PERIOD(20, 24, 28, 32);
2859 }
2860
2861 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2862 {
2863 DeviceClass *dc = DEVICE_CLASS(oc);
2864 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2865
2866 dc->desc = "PowerPC 440x5";
2867 pcc->init_proc = init_proc_440x5;
2868 pcc->check_pow = check_pow_nocheck;
2869 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2870 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2871 PPC_CACHE | PPC_CACHE_ICBI |
2872 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2873 PPC_MEM_TLBSYNC | PPC_MFTB |
2874 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2875 PPC_440_SPEC;
2876 pcc->msr_mask = (1ull << MSR_POW) |
2877 (1ull << MSR_CE) |
2878 (1ull << MSR_EE) |
2879 (1ull << MSR_PR) |
2880 (1ull << MSR_FP) |
2881 (1ull << MSR_ME) |
2882 (1ull << MSR_FE0) |
2883 (1ull << MSR_DWE) |
2884 (1ull << MSR_DE) |
2885 (1ull << MSR_FE1) |
2886 (1ull << MSR_IR) |
2887 (1ull << MSR_DR);
2888 pcc->mmu_model = POWERPC_MMU_BOOKE;
2889 pcc->excp_model = POWERPC_EXCP_BOOKE;
2890 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2891 pcc->bfd_mach = bfd_mach_ppc_403;
2892 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2893 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2894 }
2895
2896 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2897 {
2898 DeviceClass *dc = DEVICE_CLASS(oc);
2899 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2900
2901 dc->desc = "PowerPC 440x5 with double precision FPU";
2902 pcc->init_proc = init_proc_440x5;
2903 pcc->check_pow = check_pow_nocheck;
2904 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2905 PPC_FLOAT | PPC_FLOAT_FSQRT |
2906 PPC_FLOAT_STFIWX |
2907 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2908 PPC_CACHE | PPC_CACHE_ICBI |
2909 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2910 PPC_MEM_TLBSYNC | PPC_MFTB |
2911 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2912 PPC_440_SPEC;
2913 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2914 pcc->msr_mask = (1ull << MSR_POW) |
2915 (1ull << MSR_CE) |
2916 (1ull << MSR_EE) |
2917 (1ull << MSR_PR) |
2918 (1ull << MSR_FP) |
2919 (1ull << MSR_ME) |
2920 (1ull << MSR_FE0) |
2921 (1ull << MSR_DWE) |
2922 (1ull << MSR_DE) |
2923 (1ull << MSR_FE1) |
2924 (1ull << MSR_IR) |
2925 (1ull << MSR_DR);
2926 pcc->mmu_model = POWERPC_MMU_BOOKE;
2927 pcc->excp_model = POWERPC_EXCP_BOOKE;
2928 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2929 pcc->bfd_mach = bfd_mach_ppc_403;
2930 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2931 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2932 }
2933
2934 static void init_proc_MPC5xx(CPUPPCState *env)
2935 {
2936 register_5xx_8xx_sprs(env);
2937 register_5xx_sprs(env);
2938 init_excp_MPC5xx(env);
2939 env->dcache_line_size = 32;
2940 env->icache_line_size = 32;
2941 /* XXX: TODO: allocate internal IRQ controller */
2942 }
2943
2944 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2945 {
2946 DeviceClass *dc = DEVICE_CLASS(oc);
2947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2948
2949 dc->desc = "Freescale 5xx cores (aka RCPU)";
2950 pcc->init_proc = init_proc_MPC5xx;
2951 pcc->check_pow = check_pow_none;
2952 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2953 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2954 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2955 PPC_MFTB;
2956 pcc->msr_mask = (1ull << MSR_ILE) |
2957 (1ull << MSR_EE) |
2958 (1ull << MSR_PR) |
2959 (1ull << MSR_FP) |
2960 (1ull << MSR_ME) |
2961 (1ull << MSR_FE0) |
2962 (1ull << MSR_SE) |
2963 (1ull << MSR_DE) |
2964 (1ull << MSR_FE1) |
2965 (1ull << MSR_EP) |
2966 (1ull << MSR_RI) |
2967 (1ull << MSR_LE);
2968 pcc->mmu_model = POWERPC_MMU_REAL;
2969 pcc->excp_model = POWERPC_EXCP_6xx;
2970 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2971 pcc->bfd_mach = bfd_mach_ppc_505;
2972 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2973 POWERPC_FLAG_BUS_CLK;
2974 }
2975
2976 static void init_proc_MPC8xx(CPUPPCState *env)
2977 {
2978 register_5xx_8xx_sprs(env);
2979 register_8xx_sprs(env);
2980 init_excp_MPC8xx(env);
2981 env->dcache_line_size = 32;
2982 env->icache_line_size = 32;
2983 /* XXX: TODO: allocate internal IRQ controller */
2984 }
2985
2986 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2987 {
2988 DeviceClass *dc = DEVICE_CLASS(oc);
2989 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2990
2991 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2992 pcc->init_proc = init_proc_MPC8xx;
2993 pcc->check_pow = check_pow_none;
2994 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2995 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2996 PPC_CACHE_ICBI | PPC_MFTB;
2997 pcc->msr_mask = (1ull << MSR_ILE) |
2998 (1ull << MSR_EE) |
2999 (1ull << MSR_PR) |
3000 (1ull << MSR_FP) |
3001 (1ull << MSR_ME) |
3002 (1ull << MSR_SE) |
3003 (1ull << MSR_DE) |
3004 (1ull << MSR_EP) |
3005 (1ull << MSR_IR) |
3006 (1ull << MSR_DR) |
3007 (1ull << MSR_RI) |
3008 (1ull << MSR_LE);
3009 pcc->mmu_model = POWERPC_MMU_MPC8xx;
3010 pcc->excp_model = POWERPC_EXCP_6xx;
3011 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3012 pcc->bfd_mach = bfd_mach_ppc_860;
3013 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3014 POWERPC_FLAG_BUS_CLK;
3015 }
3016
3017 /* Freescale 82xx cores (aka PowerQUICC-II) */
3018
3019 static void init_proc_G2(CPUPPCState *env)
3020 {
3021 register_ne_601_sprs(env);
3022 register_sdr1_sprs(env);
3023 register_G2_sprs(env);
3024
3025 /* Memory management */
3026 register_low_BATs(env);
3027 register_high_BATs(env);
3028 register_6xx_7xx_soft_tlb(env, 64, 2);
3029 init_excp_G2(env);
3030 env->dcache_line_size = 32;
3031 env->icache_line_size = 32;
3032 /* Allocate hardware IRQ controller */
3033 ppc6xx_irq_init(env_archcpu(env));
3034 }
3035
3036 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3037 {
3038 DeviceClass *dc = DEVICE_CLASS(oc);
3039 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3040
3041 dc->desc = "PowerPC G2";
3042 pcc->init_proc = init_proc_G2;
3043 pcc->check_pow = check_pow_hid0;
3044 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3045 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3046 PPC_FLOAT_STFIWX |
3047 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3048 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3049 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3050 PPC_SEGMENT | PPC_EXTERN;
3051 pcc->msr_mask = (1ull << MSR_POW) |
3052 (1ull << MSR_TGPR) |
3053 (1ull << MSR_EE) |
3054 (1ull << MSR_PR) |
3055 (1ull << MSR_FP) |
3056 (1ull << MSR_ME) |
3057 (1ull << MSR_FE0) |
3058 (1ull << MSR_SE) |
3059 (1ull << MSR_DE) |
3060 (1ull << MSR_FE1) |
3061 (1ull << MSR_AL) |
3062 (1ull << MSR_EP) |
3063 (1ull << MSR_IR) |
3064 (1ull << MSR_DR) |
3065 (1ull << MSR_RI);
3066 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3067 pcc->excp_model = POWERPC_EXCP_6xx;
3068 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3069 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3070 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3071 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3072 }
3073
3074 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3075 {
3076 DeviceClass *dc = DEVICE_CLASS(oc);
3077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3078
3079 dc->desc = "PowerPC G2LE";
3080 pcc->init_proc = init_proc_G2;
3081 pcc->check_pow = check_pow_hid0;
3082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3084 PPC_FLOAT_STFIWX |
3085 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3086 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3087 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3088 PPC_SEGMENT | PPC_EXTERN;
3089 pcc->msr_mask = (1ull << MSR_POW) |
3090 (1ull << MSR_TGPR) |
3091 (1ull << MSR_ILE) |
3092 (1ull << MSR_EE) |
3093 (1ull << MSR_PR) |
3094 (1ull << MSR_FP) |
3095 (1ull << MSR_ME) |
3096 (1ull << MSR_FE0) |
3097 (1ull << MSR_SE) |
3098 (1ull << MSR_DE) |
3099 (1ull << MSR_FE1) |
3100 (1ull << MSR_AL) |
3101 (1ull << MSR_EP) |
3102 (1ull << MSR_IR) |
3103 (1ull << MSR_DR) |
3104 (1ull << MSR_RI) |
3105 (1ull << MSR_LE);
3106 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3107 pcc->excp_model = POWERPC_EXCP_6xx;
3108 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3109 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3110 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3111 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3112 }
3113
3114 static void init_proc_e200(CPUPPCState *env)
3115 {
3116 register_BookE_sprs(env, 0x000000070000FFFFULL);
3117
3118 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3119 &spr_read_spefscr, &spr_write_spefscr,
3120 &spr_read_spefscr, &spr_write_spefscr,
3121 0x00000000);
3122 /* Memory management */
3123 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3124 register_usprgh_sprs(env);
3125
3126 spr_register(env, SPR_HID0, "HID0",
3127 SPR_NOACCESS, SPR_NOACCESS,
3128 &spr_read_generic, &spr_write_generic,
3129 0x00000000);
3130
3131 spr_register(env, SPR_HID1, "HID1",
3132 SPR_NOACCESS, SPR_NOACCESS,
3133 &spr_read_generic, &spr_write_generic,
3134 0x00000000);
3135
3136 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3137 SPR_NOACCESS, SPR_NOACCESS,
3138 &spr_read_generic, &spr_write_generic,
3139 0x00000000);
3140
3141 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3142 SPR_NOACCESS, SPR_NOACCESS,
3143 &spr_read_generic, &spr_write_generic,
3144 0x00000000);
3145
3146 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3147 SPR_NOACCESS, SPR_NOACCESS,
3148 &spr_read_generic, &spr_write_generic,
3149 0x00000000);
3150
3151 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3152 SPR_NOACCESS, SPR_NOACCESS,
3153 &spr_read_generic, &spr_write_generic,
3154 0x00000000);
3155
3156 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3157 SPR_NOACCESS, SPR_NOACCESS,
3158 &spr_read_generic, &spr_write_generic,
3159 0x00000000);
3160
3161 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3162 &spr_read_generic, SPR_NOACCESS,
3163 &spr_read_generic, SPR_NOACCESS,
3164 0x00000000);
3165
3166 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3167 SPR_NOACCESS, SPR_NOACCESS,
3168 &spr_read_generic, &spr_write_generic,
3169 0x00000000);
3170
3171 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3172 SPR_NOACCESS, SPR_NOACCESS,
3173 &spr_read_generic, &spr_write_generic,
3174 0x00000000);
3175
3176 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3177 SPR_NOACCESS, SPR_NOACCESS,
3178 &spr_read_generic, &spr_write_generic,
3179 0x00000000);
3180
3181 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3182 SPR_NOACCESS, SPR_NOACCESS,
3183 &spr_read_generic, &spr_write_generic,
3184 0x00000000);
3185
3186 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3187 SPR_NOACCESS, SPR_NOACCESS,
3188 &spr_read_generic, &spr_write_generic,
3189 0x00000000);
3190
3191 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3192 SPR_NOACCESS, SPR_NOACCESS,
3193 &spr_read_generic, &spr_write_generic,
3194 0x00000000);
3195
3196 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3197 SPR_NOACCESS, SPR_NOACCESS,
3198 &spr_read_generic, &spr_write_generic,
3199 0x00000000); /* TOFIX */
3200 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3201 SPR_NOACCESS, SPR_NOACCESS,
3202 &spr_read_generic, &spr_write_generic,
3203 0x00000000);
3204 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3205 SPR_NOACCESS, SPR_NOACCESS,
3206 &spr_read_generic, &spr_write_generic,
3207 0x00000000);
3208 #if !defined(CONFIG_USER_ONLY)
3209 env->nb_tlb = 64;
3210 env->nb_ways = 1;
3211 env->id_tlbs = 0;
3212 env->tlb_type = TLB_EMB;
3213 #endif
3214 init_excp_e200(env, 0xFFFF0000UL);
3215 env->dcache_line_size = 32;
3216 env->icache_line_size = 32;
3217 /* XXX: TODO: allocate internal IRQ controller */
3218 }
3219
3220 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3221 {
3222 DeviceClass *dc = DEVICE_CLASS(oc);
3223 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3224
3225 dc->desc = "e200 core";
3226 pcc->init_proc = init_proc_e200;
3227 pcc->check_pow = check_pow_hid0;
3228 /*
3229 * XXX: unimplemented instructions:
3230 * dcblc
3231 * dcbtlst
3232 * dcbtstls
3233 * icblc
3234 * icbtls
3235 * tlbivax
3236 * all SPE multiply-accumulate instructions
3237 */
3238 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3239 PPC_SPE | PPC_SPE_SINGLE |
3240 PPC_WRTEE | PPC_RFDI |
3241 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3242 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3243 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3244 PPC_BOOKE;
3245 pcc->msr_mask = (1ull << MSR_UCLE) |
3246 (1ull << MSR_SPE) |
3247 (1ull << MSR_POW) |
3248 (1ull << MSR_CE) |
3249 (1ull << MSR_EE) |
3250 (1ull << MSR_PR) |
3251 (1ull << MSR_FP) |
3252 (1ull << MSR_ME) |
3253 (1ull << MSR_FE0) |
3254 (1ull << MSR_DWE) |
3255 (1ull << MSR_DE) |
3256 (1ull << MSR_FE1) |
3257 (1ull << MSR_IR) |
3258 (1ull << MSR_DR);
3259 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3260 pcc->excp_model = POWERPC_EXCP_BOOKE;
3261 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3262 pcc->bfd_mach = bfd_mach_ppc_860;
3263 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3264 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3265 POWERPC_FLAG_BUS_CLK;
3266 }
3267
3268 enum fsl_e500_version {
3269 fsl_e500v1,
3270 fsl_e500v2,
3271 fsl_e500mc,
3272 fsl_e5500,
3273 fsl_e6500,
3274 };
3275
3276 static void init_proc_e500(CPUPPCState *env, int version)
3277 {
3278 uint32_t tlbncfg[2];
3279 uint64_t ivor_mask;
3280 uint64_t ivpr_mask = 0xFFFF0000ULL;
3281 uint32_t l1cfg0 = 0x3800 /* 8 ways */
3282 | 0x0020; /* 32 kb */
3283 uint32_t l1cfg1 = 0x3800 /* 8 ways */
3284 | 0x0020; /* 32 kb */
3285 uint32_t mmucfg = 0;
3286 #if !defined(CONFIG_USER_ONLY)
3287 int i;
3288 #endif
3289
3290 /*
3291 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
3292 * complain when accessing them.
3293 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
3294 */
3295 switch (version) {
3296 case fsl_e500v1:
3297 case fsl_e500v2:
3298 default:
3299 ivor_mask = 0x0000000F0000FFFFULL;
3300 break;
3301 case fsl_e500mc:
3302 case fsl_e5500:
3303 ivor_mask = 0x000003FE0000FFFFULL;
3304 break;
3305 case fsl_e6500:
3306 ivor_mask = 0x000003FF0000FFFFULL;
3307 break;
3308 }
3309 register_BookE_sprs(env, ivor_mask);
3310 register_usprg3_sprs(env);
3311 /* Processor identification */
3312 spr_register(env, SPR_BOOKE_PIR, "PIR",
3313 SPR_NOACCESS, SPR_NOACCESS,
3314 &spr_read_generic, &spr_write_pir,
3315 0x00000000);
3316
3317 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3318 &spr_read_spefscr, &spr_write_spefscr,
3319 &spr_read_spefscr, &spr_write_spefscr,
3320 0x00000000);
3321 #if !defined(CONFIG_USER_ONLY)
3322 /* Memory management */
3323 env->nb_pids = 3;
3324 env->nb_ways = 2;
3325 env->id_tlbs = 0;
3326 switch (version) {
3327 case fsl_e500v1:
3328 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
3329 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3330 break;
3331 case fsl_e500v2:
3332 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3333 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3334 break;
3335 case fsl_e500mc:
3336 case fsl_e5500:
3337 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3338 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
3339 break;
3340 case fsl_e6500:
3341 mmucfg = 0x6510B45;
3342 env->nb_pids = 1;
3343 tlbncfg[0] = 0x08052400;
3344 tlbncfg[1] = 0x40028040;
3345 break;
3346 default:
3347 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3348 env->spr[SPR_PVR]);
3349 }
3350 #endif
3351 /* Cache sizes */
3352 switch (version) {
3353 case fsl_e500v1:
3354 case fsl_e500v2:
3355 env->dcache_line_size = 32;
3356 env->icache_line_size = 32;
3357 break;
3358 case fsl_e500mc:
3359 case fsl_e5500:
3360 env->dcache_line_size = 64;
3361 env->icache_line_size = 64;
3362 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
3363 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
3364 break;
3365 case fsl_e6500:
3366 env->dcache_line_size = 32;
3367 env->icache_line_size = 32;
3368 l1cfg0 |= 0x0F83820;
3369 l1cfg1 |= 0x0B83820;
3370 break;
3371 default:
3372 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3373 env->spr[SPR_PVR]);
3374 }
3375 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
3376 register_usprgh_sprs(env);
3377
3378 spr_register(env, SPR_HID0, "HID0",
3379 SPR_NOACCESS, SPR_NOACCESS,
3380 &spr_read_generic, &spr_write_generic,
3381 0x00000000);
3382
3383 spr_register(env, SPR_HID1, "HID1",
3384 SPR_NOACCESS, SPR_NOACCESS,
3385 &spr_read_generic, &spr_write_generic,
3386 0x00000000);
3387
3388 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
3389 SPR_NOACCESS, SPR_NOACCESS,
3390 &spr_read_generic, &spr_write_generic,
3391 0x00000000);
3392
3393 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
3394 SPR_NOACCESS, SPR_NOACCESS,
3395 &spr_read_generic, &spr_write_generic,
3396 0x00000000);
3397
3398 spr_register(env, SPR_Exxx_MCAR, "MCAR",
3399 SPR_NOACCESS, SPR_NOACCESS,
3400 &spr_read_generic, &spr_write_generic,
3401 0x00000000);
3402
3403 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3404 SPR_NOACCESS, SPR_NOACCESS,
3405 &spr_read_generic, &spr_write_generic,
3406 0x00000000);
3407
3408 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
3409 SPR_NOACCESS, SPR_NOACCESS,
3410 &spr_read_generic, &spr_write_generic,
3411 0x00000000);
3412
3413 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3414 SPR_NOACCESS, SPR_NOACCESS,
3415 &spr_read_generic, &spr_write_generic,
3416 0x00000000);
3417
3418 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3419 &spr_read_generic, SPR_NOACCESS,
3420 &spr_read_generic, SPR_NOACCESS,
3421 l1cfg0);
3422 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
3423 &spr_read_generic, SPR_NOACCESS,
3424 &spr_read_generic, SPR_NOACCESS,
3425 l1cfg1);
3426 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3427 SPR_NOACCESS, SPR_NOACCESS,
3428 &spr_read_generic, &spr_write_e500_l1csr0,
3429 0x00000000);
3430 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
3431 SPR_NOACCESS, SPR_NOACCESS,
3432 &spr_read_generic, &spr_write_e500_l1csr1,
3433 0x00000000);
3434 if (version != fsl_e500v1 && version != fsl_e500v2) {
3435 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
3436 SPR_NOACCESS, SPR_NOACCESS,
3437 &spr_read_generic, &spr_write_e500_l2csr0,
3438 0x00000000);
3439 }
3440 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0x00000000);
3444 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3445 SPR_NOACCESS, SPR_NOACCESS,
3446 &spr_read_generic, &spr_write_generic,
3447 0x00000000);
3448 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3449 SPR_NOACCESS, SPR_NOACCESS,
3450 &spr_read_generic, &spr_write_booke206_mmucsr0,
3451 0x00000000);
3452 spr_register(env, SPR_BOOKE_EPR, "EPR",
3453 SPR_NOACCESS, SPR_NOACCESS,
3454 &spr_read_generic, SPR_NOACCESS,
3455 0x00000000);
3456 /* XXX better abstract into Emb.xxx features */
3457 if ((version == fsl_e5500) || (version == fsl_e6500)) {
3458 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
3459 SPR_NOACCESS, SPR_NOACCESS,
3460 &spr_read_generic, &spr_write_generic,
3461 0x00000000);
3462 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
3463 SPR_NOACCESS, SPR_NOACCESS,
3464 &spr_read_mas73, &spr_write_mas73,
3465 0x00000000);
3466 ivpr_mask = (target_ulong)~0xFFFFULL;
3467 }
3468
3469 if (version == fsl_e6500) {
3470 /* Thread identification */
3471 spr_register(env, SPR_TIR, "TIR",
3472 SPR_NOACCESS, SPR_NOACCESS,
3473 &spr_read_generic, SPR_NOACCESS,
3474 0x00000000);
3475 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3476 SPR_NOACCESS, SPR_NOACCESS,
3477 &spr_read_generic, SPR_NOACCESS,
3478 0x00000004);
3479 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3480 SPR_NOACCESS, SPR_NOACCESS,
3481 &spr_read_generic, SPR_NOACCESS,
3482 0x7FFFFFFC);
3483 }
3484
3485 #if !defined(CONFIG_USER_ONLY)
3486 env->nb_tlb = 0;
3487 env->tlb_type = TLB_MAS;
3488 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3489 env->nb_tlb += booke206_tlb_size(env, i);
3490 }
3491 #endif
3492
3493 init_excp_e200(env, ivpr_mask);
3494 /* Allocate hardware IRQ controller */
3495 ppce500_irq_init(env_archcpu(env));
3496 }
3497
3498 static void init_proc_e500v1(CPUPPCState *env)
3499 {
3500 init_proc_e500(env, fsl_e500v1);
3501 }
3502
3503 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3504 {
3505 DeviceClass *dc = DEVICE_CLASS(oc);
3506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3507
3508 dc->desc = "e500v1 core";
3509 pcc->init_proc = init_proc_e500v1;
3510 pcc->check_pow = check_pow_hid0;
3511 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3512 PPC_SPE | PPC_SPE_SINGLE |
3513 PPC_WRTEE | PPC_RFDI |
3514 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3515 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3516 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3517 pcc->insns_flags2 = PPC2_BOOKE206;
3518 pcc->msr_mask = (1ull << MSR_UCLE) |
3519 (1ull << MSR_SPE) |
3520 (1ull << MSR_POW) |
3521 (1ull << MSR_CE) |
3522 (1ull << MSR_EE) |
3523 (1ull << MSR_PR) |
3524 (1ull << MSR_FP) |
3525 (1ull << MSR_ME) |
3526 (1ull << MSR_FE0) |
3527 (1ull << MSR_DWE) |
3528 (1ull << MSR_DE) |
3529 (1ull << MSR_FE1) |
3530 (1ull << MSR_IR) |
3531 (1ull << MSR_DR);
3532 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3533 pcc->excp_model = POWERPC_EXCP_BOOKE;
3534 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3535 pcc->bfd_mach = bfd_mach_ppc_860;
3536 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3537 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3538 POWERPC_FLAG_BUS_CLK;
3539 }
3540
3541 static void init_proc_e500v2(CPUPPCState *env)
3542 {
3543 init_proc_e500(env, fsl_e500v2);
3544 }
3545
3546 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3547 {
3548 DeviceClass *dc = DEVICE_CLASS(oc);
3549 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3550
3551 dc->desc = "e500v2 core";
3552 pcc->init_proc = init_proc_e500v2;
3553 pcc->check_pow = check_pow_hid0;
3554 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3555 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3556 PPC_WRTEE | PPC_RFDI |
3557 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3558 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3559 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3560 pcc->insns_flags2 = PPC2_BOOKE206;
3561 pcc->msr_mask = (1ull << MSR_UCLE) |
3562 (1ull << MSR_SPE) |
3563 (1ull << MSR_POW) |
3564 (1ull << MSR_CE) |
3565 (1ull << MSR_EE) |
3566 (1ull << MSR_PR) |
3567 (1ull << MSR_FP) |
3568 (1ull << MSR_ME) |
3569 (1ull << MSR_FE0) |
3570 (1ull << MSR_DWE) |
3571 (1ull << MSR_DE) |
3572 (1ull << MSR_FE1) |
3573 (1ull << MSR_IR) |
3574 (1ull << MSR_DR);
3575 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3576 pcc->excp_model = POWERPC_EXCP_BOOKE;
3577 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3578 pcc->bfd_mach = bfd_mach_ppc_860;
3579 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3580 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3581 POWERPC_FLAG_BUS_CLK;
3582 }
3583
3584 static void init_proc_e500mc(CPUPPCState *env)
3585 {
3586 init_proc_e500(env, fsl_e500mc);
3587 }
3588
3589 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3590 {
3591 DeviceClass *dc = DEVICE_CLASS(oc);
3592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3593
3594 dc->desc = "e500mc core";
3595 pcc->init_proc = init_proc_e500mc;
3596 pcc->check_pow = check_pow_none;
3597 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3598 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3599 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3600 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3601 PPC_FLOAT | PPC_FLOAT_FRES |
3602 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3603 PPC_FLOAT_STFIWX | PPC_WAIT |
3604 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3605 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3606 pcc->msr_mask = (1ull << MSR_GS) |
3607 (1ull << MSR_UCLE) |
3608 (1ull << MSR_CE) |
3609 (1ull << MSR_EE) |
3610 (1ull << MSR_PR) |
3611 (1ull << MSR_FP) |
3612 (1ull << MSR_ME) |
3613 (1ull << MSR_FE0) |
3614 (1ull << MSR_DE) |
3615 (1ull << MSR_FE1) |
3616 (1ull << MSR_IR) |
3617 (1ull << MSR_DR) |
3618 (1ull << MSR_PX) |
3619 (1ull << MSR_RI);
3620 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3621 pcc->excp_model = POWERPC_EXCP_BOOKE;
3622 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3623 /* FIXME: figure out the correct flag for e500mc */
3624 pcc->bfd_mach = bfd_mach_ppc_e500;
3625 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3626 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3627 }
3628
3629 #ifdef TARGET_PPC64
3630 static void init_proc_e5500(CPUPPCState *env)
3631 {
3632 init_proc_e500(env, fsl_e5500);
3633 }
3634
3635 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3636 {
3637 DeviceClass *dc = DEVICE_CLASS(oc);
3638 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3639
3640 dc->desc = "e5500 core";
3641 pcc->init_proc = init_proc_e5500;
3642 pcc->check_pow = check_pow_none;
3643 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3644 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3645 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3646 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3647 PPC_FLOAT | PPC_FLOAT_FRES |
3648 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3649 PPC_FLOAT_STFIWX | PPC_WAIT |
3650 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3651 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3652 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3653 PPC2_FP_CVT_S64;
3654 pcc->msr_mask = (1ull << MSR_CM) |
3655 (1ull << MSR_GS) |
3656 (1ull << MSR_UCLE) |
3657 (1ull << MSR_CE) |
3658 (1ull << MSR_EE) |
3659 (1ull << MSR_PR) |
3660 (1ull << MSR_FP) |
3661 (1ull << MSR_ME) |
3662 (1ull << MSR_FE0) |
3663 (1ull << MSR_DE) |
3664 (1ull << MSR_FE1) |
3665 (1ull << MSR_IR) |
3666 (1ull << MSR_DR) |
3667 (1ull << MSR_PX) |
3668 (1ull << MSR_RI);
3669 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3670 pcc->excp_model = POWERPC_EXCP_BOOKE;
3671 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3672 /* FIXME: figure out the correct flag for e5500 */
3673 pcc->bfd_mach = bfd_mach_ppc_e500;
3674 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3675 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3676 }
3677
3678 static void init_proc_e6500(CPUPPCState *env)
3679 {
3680 init_proc_e500(env, fsl_e6500);
3681 }
3682
3683 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3684 {
3685 DeviceClass *dc = DEVICE_CLASS(oc);
3686 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3687
3688 dc->desc = "e6500 core";
3689 pcc->init_proc = init_proc_e6500;
3690 pcc->check_pow = check_pow_none;
3691 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3692 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3693 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3694 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3695 PPC_FLOAT | PPC_FLOAT_FRES |
3696 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3697 PPC_FLOAT_STFIWX | PPC_WAIT |
3698 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3699 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3700 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3701 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3702 pcc->msr_mask = (1ull << MSR_CM) |
3703 (1ull << MSR_GS) |
3704 (1ull << MSR_UCLE) |
3705 (1ull << MSR_CE) |
3706 (1ull << MSR_EE) |
3707 (1ull << MSR_PR) |
3708 (1ull << MSR_FP) |
3709 (1ull << MSR_ME) |
3710 (1ull << MSR_FE0) |
3711 (1ull << MSR_DE) |
3712 (1ull << MSR_FE1) |
3713 (1ull << MSR_IS) |
3714 (1ull << MSR_DS) |
3715 (1ull << MSR_PX) |
3716 (1ull << MSR_RI) |
3717 (1ull << MSR_VR);
3718 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3719 pcc->excp_model = POWERPC_EXCP_BOOKE;
3720 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3721 pcc->bfd_mach = bfd_mach_ppc_e500;
3722 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3723 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3724 }
3725
3726 #endif
3727
3728 /* Non-embedded PowerPC */
3729 static void init_proc_603(CPUPPCState *env)
3730 {
3731 register_ne_601_sprs(env);
3732 register_sdr1_sprs(env);
3733 register_603_sprs(env);
3734
3735 /* Memory management */
3736 register_low_BATs(env);
3737 register_6xx_7xx_soft_tlb(env, 64, 2);
3738 init_excp_603(env);
3739 env->dcache_line_size = 32;
3740 env->icache_line_size = 32;
3741 /* Allocate hardware IRQ controller */
3742 ppc6xx_irq_init(env_archcpu(env));
3743 }
3744
3745 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3746 {
3747 DeviceClass *dc = DEVICE_CLASS(oc);
3748 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3749
3750 dc->desc = "PowerPC 603";
3751 pcc->init_proc = init_proc_603;
3752 pcc->check_pow = check_pow_hid0;
3753 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3754 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3755 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3756 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3757 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3758 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3759 PPC_SEGMENT | PPC_EXTERN;
3760 pcc->msr_mask = (1ull << MSR_POW) |
3761 (1ull << MSR_TGPR) |
3762 (1ull << MSR_ILE) |
3763 (1ull << MSR_EE) |
3764 (1ull << MSR_PR) |
3765 (1ull << MSR_FP) |
3766 (1ull << MSR_ME) |
3767 (1ull << MSR_FE0) |
3768 (1ull << MSR_SE) |
3769 (1ull << MSR_DE) |
3770 (1ull << MSR_FE1) |
3771 (1ull << MSR_EP) |
3772 (1ull << MSR_IR) |
3773 (1ull << MSR_DR) |
3774 (1ull << MSR_RI) |
3775 (1ull << MSR_LE);
3776 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3777 pcc->excp_model = POWERPC_EXCP_6xx;
3778 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3779 pcc->bfd_mach = bfd_mach_ppc_603;
3780 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3781 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3782 }
3783
3784 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3785 {
3786 DeviceClass *dc = DEVICE_CLASS(oc);
3787 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3788
3789 dc->desc = "PowerPC 603e";
3790 pcc->init_proc = init_proc_603;
3791 pcc->check_pow = check_pow_hid0;
3792 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3793 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3794 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3795 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3796 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3797 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3798 PPC_SEGMENT | PPC_EXTERN;
3799 pcc->msr_mask = (1ull << MSR_POW) |
3800 (1ull << MSR_TGPR) |
3801 (1ull << MSR_ILE) |
3802 (1ull << MSR_EE) |
3803 (1ull << MSR_PR) |
3804 (1ull << MSR_FP) |
3805 (1ull << MSR_ME) |
3806 (1ull << MSR_FE0) |
3807 (1ull << MSR_SE) |
3808 (1ull << MSR_DE) |
3809 (1ull << MSR_FE1) |
3810 (1ull << MSR_EP) |
3811 (1ull << MSR_IR) |
3812 (1ull << MSR_DR) |
3813 (1ull << MSR_RI) |
3814 (1ull << MSR_LE);
3815 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3816 pcc->excp_model = POWERPC_EXCP_6xx;
3817 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3818 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3819 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3820 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3821 }
3822
3823 static void init_proc_e300(CPUPPCState *env)
3824 {
3825 init_proc_603(env);
3826 register_e300_sprs(env);
3827 }
3828
3829 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3830 {
3831 DeviceClass *dc = DEVICE_CLASS(oc);
3832 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3833
3834 dc->desc = "e300 core";
3835 pcc->init_proc = init_proc_e300;
3836 pcc->check_pow = check_pow_hid0;
3837 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3838 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3839 PPC_FLOAT_STFIWX |
3840 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3841 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3842 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3843 PPC_SEGMENT | PPC_EXTERN;
3844 pcc->msr_mask = (1ull << MSR_POW) |
3845 (1ull << MSR_TGPR) |
3846 (1ull << MSR_ILE) |
3847 (1ull << MSR_EE) |
3848 (1ull << MSR_PR) |
3849 (1ull << MSR_FP) |
3850 (1ull << MSR_ME) |
3851 (1ull << MSR_FE0) |
3852 (1ull << MSR_SE) |
3853 (1ull << MSR_DE) |
3854 (1ull << MSR_FE1) |
3855 (1ull << MSR_AL) |
3856 (1ull << MSR_EP) |
3857 (1ull << MSR_IR) |
3858 (1ull << MSR_DR) |
3859 (1ull << MSR_RI) |
3860 (1ull << MSR_LE);
3861 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3862 pcc->excp_model = POWERPC_EXCP_6xx;
3863 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3864 pcc->bfd_mach = bfd_mach_ppc_603;
3865 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3866 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3867 }
3868
3869 static void init_proc_604(CPUPPCState *env)
3870 {
3871 register_ne_601_sprs(env);
3872 register_sdr1_sprs(env);
3873 register_604_sprs(env);
3874
3875 /* Memory management */
3876 register_low_BATs(env);
3877 init_excp_604(env);
3878 env->dcache_line_size = 32;
3879 env->icache_line_size = 32;
3880 /* Allocate hardware IRQ controller */
3881 ppc6xx_irq_init(env_archcpu(env));
3882 }
3883
3884 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3885 {
3886 DeviceClass *dc = DEVICE_CLASS(oc);
3887 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3888
3889 dc->desc = "PowerPC 604";
3890 pcc->init_proc = init_proc_604;
3891 pcc->check_pow = check_pow_nocheck;
3892 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3893 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3894 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3895 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3896 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3897 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3898 PPC_SEGMENT | PPC_EXTERN;
3899 pcc->msr_mask = (1ull << MSR_POW) |
3900 (1ull << MSR_ILE) |
3901 (1ull << MSR_EE) |
3902 (1ull << MSR_PR) |
3903 (1ull << MSR_FP) |
3904 (1ull << MSR_ME) |
3905 (1ull << MSR_FE0) |
3906 (1ull << MSR_SE) |
3907 (1ull << MSR_DE) |
3908 (1ull << MSR_FE1) |
3909 (1ull << MSR_EP) |
3910 (1ull << MSR_IR) |
3911 (1ull << MSR_DR) |
3912 (1ull << MSR_PMM) |
3913 (1ull << MSR_RI) |
3914 (1ull << MSR_LE);
3915 pcc->mmu_model = POWERPC_MMU_32B;
3916 pcc->excp_model = POWERPC_EXCP_6xx;
3917 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3918 pcc->bfd_mach = bfd_mach_ppc_604;
3919 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3920 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3921 }
3922
3923 static void init_proc_604E(CPUPPCState *env)
3924 {
3925 register_ne_601_sprs(env);
3926 register_sdr1_sprs(env);
3927 register_604_sprs(env);
3928 register_604e_sprs(env);
3929
3930 /* Memory management */
3931 register_low_BATs(env);
3932 init_excp_604(env);
3933 env->dcache_line_size = 32;
3934 env->icache_line_size = 32;
3935 /* Allocate hardware IRQ controller */
3936 ppc6xx_irq_init(env_archcpu(env));
3937 }
3938
3939 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3940 {
3941 DeviceClass *dc = DEVICE_CLASS(oc);
3942 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3943
3944 dc->desc = "PowerPC 604E";
3945 pcc->init_proc = init_proc_604E;
3946 pcc->check_pow = check_pow_nocheck;
3947 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3948 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3949 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3950 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3951 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3952 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3953 PPC_SEGMENT | PPC_EXTERN;
3954 pcc->msr_mask = (1ull << MSR_POW) |
3955 (1ull << MSR_ILE) |
3956 (1ull << MSR_EE) |
3957 (1ull << MSR_PR) |
3958 (1ull << MSR_FP) |
3959 (1ull << MSR_ME) |
3960 (1ull << MSR_FE0) |
3961 (1ull << MSR_SE) |
3962 (1ull << MSR_DE) |
3963 (1ull << MSR_FE1) |
3964 (1ull << MSR_EP) |
3965 (1ull << MSR_IR) |
3966 (1ull << MSR_DR) |
3967 (1ull << MSR_PMM) |
3968 (1ull << MSR_RI) |
3969 (1ull << MSR_LE);
3970 pcc->mmu_model = POWERPC_MMU_32B;
3971 pcc->excp_model = POWERPC_EXCP_6xx;
3972 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3973 pcc->bfd_mach = bfd_mach_ppc_604;
3974 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3975 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3976 }
3977
3978 static void init_proc_740(CPUPPCState *env)
3979 {
3980 register_ne_601_sprs(env);
3981 register_sdr1_sprs(env);
3982 register_7xx_sprs(env);
3983 /* Thermal management */
3984 register_thrm_sprs(env);
3985
3986 /* Memory management */
3987 register_low_BATs(env);
3988 init_excp_7x0(env);
3989 env->dcache_line_size = 32;
3990 env->icache_line_size = 32;
3991 /* Allocate hardware IRQ controller */
3992 ppc6xx_irq_init(env_archcpu(env));
3993 }
3994
3995 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3996 {
3997 DeviceClass *dc = DEVICE_CLASS(oc);
3998 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3999
4000 dc->desc = "PowerPC 740";
4001 pcc->init_proc = init_proc_740;
4002 pcc->check_pow = check_pow_hid0;
4003 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4004 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4005 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4006 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4007 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4008 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4009 PPC_SEGMENT | PPC_EXTERN;
4010 pcc->msr_mask = (1ull << MSR_POW) |
4011 (1ull << MSR_ILE) |
4012 (1ull << MSR_EE) |
4013 (1ull << MSR_PR) |
4014 (1ull << MSR_FP) |
4015 (1ull << MSR_ME) |
4016 (1ull << MSR_FE0) |
4017 (1ull << MSR_SE) |
4018 (1ull << MSR_DE) |
4019 (1ull << MSR_FE1) |
4020 (1ull << MSR_EP) |
4021 (1ull << MSR_IR) |
4022 (1ull << MSR_DR) |
4023 (1ull << MSR_PMM) |
4024 (1ull << MSR_RI) |
4025 (1ull << MSR_LE);
4026 pcc->mmu_model = POWERPC_MMU_32B;
4027 pcc->excp_model = POWERPC_EXCP_7xx;
4028 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4029 pcc->bfd_mach = bfd_mach_ppc_750;
4030 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4031 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4032 }
4033
4034 static void init_proc_750(CPUPPCState *env)
4035 {
4036 register_ne_601_sprs(env);
4037 register_sdr1_sprs(env);
4038 register_7xx_sprs(env);
4039
4040 spr_register(env, SPR_L2CR, "L2CR",
4041 SPR_NOACCESS, SPR_NOACCESS,
4042 &spr_read_generic, spr_access_nop,
4043 0x00000000);
4044 /* Thermal management */
4045 register_thrm_sprs(env);
4046
4047 /* Memory management */
4048 register_low_BATs(env);
4049 /*
4050 * XXX: high BATs are also present but are known to be bugged on
4051 * die version 1.x
4052 */
4053 init_excp_7x0(env);
4054 env->dcache_line_size = 32;
4055 env->icache_line_size = 32;
4056 /* Allocate hardware IRQ controller */
4057 ppc6xx_irq_init(env_archcpu(env));
4058 }
4059
4060 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
4061 {
4062 DeviceClass *dc = DEVICE_CLASS(oc);
4063 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4064
4065 dc->desc = "PowerPC 750";
4066 pcc->init_proc = init_proc_750;
4067 pcc->check_pow = check_pow_hid0;
4068 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4069 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4070 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4071 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4072 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4073 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4074 PPC_SEGMENT | PPC_EXTERN;
4075 pcc->msr_mask = (1ull << MSR_POW) |
4076 (1ull << MSR_ILE) |
4077 (1ull << MSR_EE) |
4078 (1ull << MSR_PR) |
4079 (1ull << MSR_FP) |
4080 (1ull << MSR_ME) |
4081 (1ull << MSR_FE0) |
4082 (1ull << MSR_SE) |
4083 (1ull << MSR_DE) |
4084 (1ull << MSR_FE1) |
4085 (1ull << MSR_EP) |
4086 (1ull << MSR_IR) |
4087 (1ull << MSR_DR) |
4088 (1ull << MSR_PMM) |
4089 (1ull << MSR_RI) |
4090 (1ull << MSR_LE);
4091 pcc->mmu_model = POWERPC_MMU_32B;
4092 pcc->excp_model = POWERPC_EXCP_7xx;
4093 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4094 pcc->bfd_mach = bfd_mach_ppc_750;
4095 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4096 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4097 }
4098
4099 static void init_proc_750cl(CPUPPCState *env)
4100 {
4101 register_ne_601_sprs(env);
4102 register_sdr1_sprs(env);
4103 register_7xx_sprs(env);
4104
4105 spr_register(env, SPR_L2CR, "L2CR",
4106 SPR_NOACCESS, SPR_NOACCESS,
4107 &spr_read_generic, spr_access_nop,
4108 0x00000000);
4109 /* Thermal management */
4110 /* Those registers are fake on 750CL */
4111 spr_register(env, SPR_THRM1, "THRM1",
4112 SPR_NOACCESS, SPR_NOACCESS,
4113 &spr_read_generic, &spr_write_generic,
4114 0x00000000);
4115 spr_register(env, SPR_THRM2, "THRM2",
4116 SPR_NOACCESS, SPR_NOACCESS,
4117 &spr_read_generic, &spr_write_generic,
4118 0x00000000);
4119 spr_register(env, SPR_THRM3, "THRM3",
4120 SPR_NOACCESS, SPR_NOACCESS,
4121 &spr_read_generic, &spr_write_generic,
4122 0x00000000);
4123
4124 spr_register(env, SPR_750_TDCL, "TDCL",
4125 SPR_NOACCESS, SPR_NOACCESS,
4126 &spr_read_generic, &spr_write_generic,
4127 0x00000000);
4128 spr_register(env, SPR_750_TDCH, "TDCH",
4129 SPR_NOACCESS, SPR_NOACCESS,
4130 &spr_read_generic, &spr_write_generic,
4131 0x00000000);
4132 /* DMA */
4133 spr_register(env, SPR_750_WPAR, "WPAR",
4134 SPR_NOACCESS, SPR_NOACCESS,
4135 &spr_read_generic, &spr_write_generic,
4136 0x00000000);
4137 spr_register(env, SPR_750_DMAL, "DMAL",
4138 SPR_NOACCESS, SPR_NOACCESS,
4139 &spr_read_generic, &spr_write_generic,
4140 0x00000000);
4141 spr_register(env, SPR_750_DMAU, "DMAU",
4142 SPR_NOACCESS, SPR_NOACCESS,
4143 &spr_read_generic, &spr_write_generic,
4144 0x00000000);
4145 /* Hardware implementation registers */
4146 spr_register(env, SPR_750CL_HID2, "HID2",
4147 SPR_NOACCESS, SPR_NOACCESS,
4148 &spr_read_generic, &spr_write_generic,
4149 0x00000000);
4150
4151 spr_register(env, SPR_750CL_HID4, "HID4",
4152 SPR_NOACCESS, SPR_NOACCESS,
4153 &spr_read_generic, &spr_write_generic,
4154 0x00000000);
4155 /* Quantization registers */
4156 spr_register(env, SPR_750_GQR0, "GQR0",
4157 SPR_NOACCESS, SPR_NOACCESS,
4158 &spr_read_generic, &spr_write_generic,
4159 0x00000000);
4160
4161 spr_register(env, SPR_750_GQR1, "GQR1",
4162 SPR_NOACCESS, SPR_NOACCESS,
4163 &spr_read_generic, &spr_write_generic,
4164 0x00000000);
4165
4166 spr_register(env, SPR_750_GQR2, "GQR2",
4167 SPR_NOACCESS, SPR_NOACCESS,
4168 &spr_read_generic, &spr_write_generic,
4169 0x00000000);
4170
4171 spr_register(env, SPR_750_GQR3, "GQR3",
4172 SPR_NOACCESS, SPR_NOACCESS,
4173 &spr_read_generic, &spr_write_generic,
4174 0x00000000);
4175
4176 spr_register(env, SPR_750_GQR4, "GQR4",
4177 SPR_NOACCESS, SPR_NOACCESS,
4178 &spr_read_generic, &spr_write_generic,
4179 0x00000000);
4180
4181 spr_register(env, SPR_750_GQR5, "GQR5",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, &spr_write_generic,
4184 0x00000000);
4185
4186 spr_register(env, SPR_750_GQR6, "GQR6",
4187 SPR_NOACCESS, SPR_NOACCESS,
4188 &spr_read_generic, &spr_write_generic,
4189 0x00000000);
4190
4191 spr_register(env, SPR_750_GQR7, "GQR7",
4192 SPR_NOACCESS, SPR_NOACCESS,
4193 &spr_read_generic, &spr_write_generic,
4194 0x00000000);
4195 /* Memory management */
4196 register_low_BATs(env);
4197 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4198 register_high_BATs(env);
4199 init_excp_750cl(env);
4200 env->dcache_line_size = 32;
4201 env->icache_line_size = 32;
4202 /* Allocate hardware IRQ controller */
4203 ppc6xx_irq_init(env_archcpu(env));
4204 }
4205
4206 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
4207 {
4208 DeviceClass *dc = DEVICE_CLASS(oc);
4209 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4210
4211 dc->desc = "PowerPC 750 CL";
4212 pcc->init_proc = init_proc_750cl;
4213 pcc->check_pow = check_pow_hid0;
4214 /*
4215 * XXX: not implemented:
4216 * cache lock instructions:
4217 * dcbz_l
4218 * floating point paired instructions
4219 * psq_lux
4220 * psq_lx
4221 * psq_stux
4222 * psq_stx
4223 * ps_abs
4224 * ps_add
4225 * ps_cmpo0
4226 * ps_cmpo1
4227 * ps_cmpu0
4228 * ps_cmpu1
4229 * ps_div
4230 * ps_madd
4231 * ps_madds0
4232 * ps_madds1
4233 * ps_merge00
4234 * ps_merge01
4235 * ps_merge10
4236 * ps_merge11
4237 * ps_mr
4238 * ps_msub
4239 * ps_mul
4240 * ps_muls0
4241 * ps_muls1
4242 * ps_nabs
4243 * ps_neg
4244 * ps_nmadd
4245 * ps_nmsub
4246 * ps_res
4247 * ps_rsqrte
4248 * ps_sel
4249 * ps_sub
4250 * ps_sum0
4251 * ps_sum1
4252 */
4253 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4254 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4255 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4256 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4257 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4258 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4259 PPC_SEGMENT | PPC_EXTERN;
4260 pcc->msr_mask = (1ull << MSR_POW) |
4261 (1ull << MSR_ILE) |
4262 (1ull << MSR_EE) |
4263 (1ull << MSR_PR) |
4264 (1ull << MSR_FP) |
4265 (1ull << MSR_ME) |
4266 (1ull << MSR_FE0) |
4267 (1ull << MSR_SE) |
4268 (1ull << MSR_DE) |
4269 (1ull << MSR_FE1) |
4270 (1ull << MSR_EP) |
4271 (1ull << MSR_IR) |
4272 (1ull << MSR_DR) |
4273 (1ull << MSR_PMM) |
4274 (1ull << MSR_RI) |
4275 (1ull << MSR_LE);
4276 pcc->mmu_model = POWERPC_MMU_32B;
4277 pcc->excp_model = POWERPC_EXCP_7xx;
4278 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4279 pcc->bfd_mach = bfd_mach_ppc_750;
4280 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4281 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4282 }
4283
4284 static void init_proc_750cx(CPUPPCState *env)
4285 {
4286 register_ne_601_sprs(env);
4287 register_sdr1_sprs(env);
4288 register_7xx_sprs(env);
4289
4290 spr_register(env, SPR_L2CR, "L2CR",
4291 SPR_NOACCESS, SPR_NOACCESS,
4292 &spr_read_generic, spr_access_nop,
4293 0x00000000);
4294 /* Thermal management */
4295 register_thrm_sprs(env);
4296
4297 spr_register(env, SPR_SDA, "SDA",
4298 SPR_NOACCESS, SPR_NOACCESS,
4299 &spr_read_generic, &spr_write_generic,
4300 0x00000000);
4301
4302 /* Memory management */
4303 register_low_BATs(env);
4304 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4305 register_high_BATs(env);
4306 init_excp_750cx(env);
4307 env->dcache_line_size = 32;
4308 env->icache_line_size = 32;
4309 /* Allocate hardware IRQ controller */
4310 ppc6xx_irq_init(env_archcpu(env));
4311 }
4312
4313 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
4314 {
4315 DeviceClass *dc = DEVICE_CLASS(oc);
4316 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4317
4318 dc->desc = "PowerPC 750CX";
4319 pcc->init_proc = init_proc_750cx;
4320 pcc->check_pow = check_pow_hid0;
4321 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4322 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4323 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4324 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4325 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4326 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4327 PPC_SEGMENT | PPC_EXTERN;
4328 pcc->msr_mask = (1ull << MSR_POW) |
4329 (1ull << MSR_ILE) |
4330 (1ull << MSR_EE) |
4331 (1ull << MSR_PR) |
4332 (1ull << MSR_FP) |
4333 (1ull << MSR_ME) |
4334 (1ull << MSR_FE0) |
4335 (1ull << MSR_SE) |
4336 (1ull << MSR_DE) |
4337 (1ull << MSR_FE1) |
4338 (1ull << MSR_EP) |
4339 (1ull << MSR_IR) |
4340 (1ull << MSR_DR) |
4341 (1ull << MSR_PMM) |
4342 (1ull << MSR_RI) |
4343 (1ull << MSR_LE);
4344 pcc->mmu_model = POWERPC_MMU_32B;
4345 pcc->excp_model = POWERPC_EXCP_7xx;
4346 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4347 pcc->bfd_mach = bfd_mach_ppc_750;
4348 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4349 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4350 }
4351
4352 static void init_proc_750fx(CPUPPCState *env)
4353 {
4354 register_ne_601_sprs(env);
4355 register_sdr1_sprs(env);
4356 register_7xx_sprs(env);
4357
4358 spr_register(env, SPR_L2CR, "L2CR",
4359 SPR_NOACCESS, SPR_NOACCESS,
4360 &spr_read_generic, spr_access_nop,
4361 0x00000000);
4362 /* Thermal management */
4363 register_thrm_sprs(env);
4364
4365 spr_register(env, SPR_750_THRM4, "THRM4",
4366 SPR_NOACCESS, SPR_NOACCESS,
4367 &spr_read_generic, &spr_write_generic,
4368 0x00000000);
4369 /* Hardware implementation registers */
4370 spr_register(env, SPR_750FX_HID2, "HID2",
4371 SPR_NOACCESS, SPR_NOACCESS,
4372 &spr_read_generic, &spr_write_generic,
4373 0x00000000);
4374 /* Memory management */
4375 register_low_BATs(env);
4376 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4377 register_high_BATs(env);
4378 init_excp_7x0(env);
4379 env->dcache_line_size = 32;
4380 env->icache_line_size = 32;
4381 /* Allocate hardware IRQ controller */
4382 ppc6xx_irq_init(env_archcpu(env));
4383 }
4384
4385 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
4386 {
4387 DeviceClass *dc = DEVICE_CLASS(oc);
4388 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4389
4390 dc->desc = "PowerPC 750FX";
4391 pcc->init_proc = init_proc_750fx;
4392 pcc->check_pow = check_pow_hid0;
4393 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4394 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4395 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4396 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4397 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4398 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4399 PPC_SEGMENT | PPC_EXTERN;
4400 pcc->msr_mask = (1ull << MSR_POW) |
4401 (1ull << MSR_ILE) |
4402 (1ull << MSR_EE) |
4403 (1ull << MSR_PR) |
4404 (1ull << MSR_FP) |
4405 (1ull << MSR_ME) |
4406 (1ull << MSR_FE0) |
4407 (1ull << MSR_SE) |
4408 (1ull << MSR_DE) |
4409 (1ull << MSR_FE1) |
4410 (1ull << MSR_EP) |
4411 (1ull << MSR_IR) |
4412 (1ull << MSR_DR) |
4413 (1ull << MSR_PMM) |
4414 (1ull << MSR_RI) |
4415 (1ull << MSR_LE);
4416 pcc->mmu_model = POWERPC_MMU_32B;
4417 pcc->excp_model = POWERPC_EXCP_7xx;
4418 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4419 pcc->bfd_mach = bfd_mach_ppc_750;
4420 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4421 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4422 }
4423
4424 static void init_proc_750gx(CPUPPCState *env)
4425 {
4426 register_ne_601_sprs(env);
4427 register_sdr1_sprs(env);
4428 register_7xx_sprs(env);
4429
4430 spr_register(env, SPR_L2CR, "L2CR",
4431 SPR_NOACCESS, SPR_NOACCESS,
4432 &spr_read_generic, spr_access_nop,
4433 0x00000000);
4434 /* Thermal management */
4435 register_thrm_sprs(env);
4436
4437 spr_register(env, SPR_750_THRM4, "THRM4",
4438 SPR_NOACCESS, SPR_NOACCESS,
4439 &spr_read_generic, &spr_write_generic,
4440 0x00000000);
4441 /* Hardware implementation registers */
4442 spr_register(env, SPR_750FX_HID2, "HID2",
4443 SPR_NOACCESS, SPR_NOACCESS,
4444 &spr_read_generic, &spr_write_generic,
4445 0x00000000);
4446 /* Memory management */
4447 register_low_BATs(env);
4448 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4449 register_high_BATs(env);
4450 init_excp_7x0(env);
4451 env->dcache_line_size = 32;
4452 env->icache_line_size = 32;
4453 /* Allocate hardware IRQ controller */
4454 ppc6xx_irq_init(env_archcpu(env));
4455 }
4456
4457 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
4458 {
4459 DeviceClass *dc = DEVICE_CLASS(oc);
4460 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4461
4462 dc->desc = "PowerPC 750GX";
4463 pcc->init_proc = init_proc_750gx;
4464 pcc->check_pow = check_pow_hid0;
4465 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4466 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4467 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4468 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4469 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4470 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4471 PPC_SEGMENT | PPC_EXTERN;
4472 pcc->msr_mask = (1ull << MSR_POW) |
4473 (1ull << MSR_ILE) |
4474 (1ull << MSR_EE) |
4475 (1ull << MSR_PR) |
4476 (1ull << MSR_FP) |
4477 (1ull << MSR_ME) |
4478 (1ull << MSR_FE0) |
4479 (1ull << MSR_SE) |
4480 (1ull << MSR_DE) |
4481 (1ull << MSR_FE1) |
4482 (1ull << MSR_EP) |
4483 (1ull << MSR_IR) |
4484 (1ull << MSR_DR) |
4485 (1ull << MSR_PMM) |
4486 (1ull << MSR_RI) |
4487 (1ull << MSR_LE);
4488 pcc->mmu_model = POWERPC_MMU_32B;
4489 pcc->excp_model = POWERPC_EXCP_7xx;
4490 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4491 pcc->bfd_mach = bfd_mach_ppc_750;
4492 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4493 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4494 }
4495
4496 static void init_proc_745(CPUPPCState *env)
4497 {
4498 register_ne_601_sprs(env);
4499 register_sdr1_sprs(env);
4500 register_7xx_sprs(env);
4501 register_745_sprs(env);
4502 /* Thermal management */
4503 register_thrm_sprs(env);
4504
4505 /* Memory management */
4506 register_low_BATs(env);
4507 register_high_BATs(env);
4508 register_6xx_7xx_soft_tlb(env, 64, 2);
4509 init_excp_7x5(env);
4510 env->dcache_line_size = 32;
4511 env->icache_line_size = 32;
4512 /* Allocate hardware IRQ controller */
4513 ppc6xx_irq_init(env_archcpu(env));
4514 }
4515
4516 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4517 {
4518 DeviceClass *dc = DEVICE_CLASS(oc);
4519 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4520
4521 dc->desc = "PowerPC 745";
4522 pcc->init_proc = init_proc_745;
4523 pcc->check_pow = check_pow_hid0;
4524 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4525 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4526 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4527 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4528 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4529 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4530 PPC_SEGMENT | PPC_EXTERN;
4531 pcc->msr_mask = (1ull << MSR_POW) |
4532 (1ull << MSR_ILE) |
4533 (1ull << MSR_EE) |
4534 (1ull << MSR_PR) |
4535 (1ull << MSR_FP) |
4536 (1ull << MSR_ME) |
4537 (1ull << MSR_FE0) |
4538 (1ull << MSR_SE) |
4539 (1ull << MSR_DE) |
4540 (1ull << MSR_FE1) |
4541 (1ull << MSR_EP) |
4542 (1ull << MSR_IR) |
4543 (1ull << MSR_DR) |
4544 (1ull << MSR_PMM) |
4545 (1ull << MSR_RI) |
4546 (1ull << MSR_LE);
4547 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4548 pcc->excp_model = POWERPC_EXCP_7xx;
4549 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4550 pcc->bfd_mach = bfd_mach_ppc_750;
4551 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4552 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4553 }
4554
4555 static void init_proc_755(CPUPPCState *env)
4556 {
4557 register_ne_601_sprs(env);
4558 register_sdr1_sprs(env);
4559 register_7xx_sprs(env);
4560 register_745_sprs(env);
4561 register_755_sprs(env);
4562
4563 /* Thermal management */
4564 register_thrm_sprs(env);
4565
4566 /* Memory management */
4567 register_low_BATs(env);
4568 register_high_BATs(env);
4569 register_6xx_7xx_soft_tlb(env, 64, 2);
4570 init_excp_7x5(env);
4571 env->dcache_line_size = 32;
4572 env->icache_line_size = 32;
4573 /* Allocate hardware IRQ controller */
4574 ppc6xx_irq_init(env_archcpu(env));
4575 }
4576
4577 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4578 {
4579 DeviceClass *dc = DEVICE_CLASS(oc);
4580 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4581
4582 dc->desc = "PowerPC 755";
4583 pcc->init_proc = init_proc_755;
4584 pcc->check_pow = check_pow_hid0;
4585 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4586 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4587 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4588 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4589 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4590 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4591 PPC_SEGMENT | PPC_EXTERN;
4592 pcc->msr_mask = (1ull << MSR_POW) |
4593 (1ull << MSR_ILE) |
4594 (1ull << MSR_EE) |
4595 (1ull << MSR_PR) |
4596 (1ull << MSR_FP) |
4597 (1ull << MSR_ME) |
4598 (1ull << MSR_FE0) |
4599 (1ull << MSR_SE) |
4600 (1ull << MSR_DE) |
4601 (1ull << MSR_FE1) |
4602 (1ull << MSR_EP) |
4603 (1ull << MSR_IR) |
4604 (1ull << MSR_DR) |
4605 (1ull << MSR_PMM) |
4606 (1ull << MSR_RI) |
4607 (1ull << MSR_LE);
4608 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4609 pcc->excp_model = POWERPC_EXCP_7xx;
4610 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4611 pcc->bfd_mach = bfd_mach_ppc_750;
4612 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4613 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4614 }
4615
4616 static void init_proc_7400(CPUPPCState *env)
4617 {
4618 register_ne_601_sprs(env);
4619 register_sdr1_sprs(env);
4620 register_74xx_sprs(env);
4621 vscr_init(env, 0x00010000);
4622
4623 spr_register(env, SPR_UBAMR, "UBAMR",
4624 &spr_read_ureg, SPR_NOACCESS,
4625 &spr_read_ureg, SPR_NOACCESS,
4626 0x00000000);
4627
4628 spr_register(env, SPR_MSSCR1, "MSSCR1",
4629 SPR_NOACCESS, SPR_NOACCESS,
4630 &spr_read_generic, &spr_write_generic,
4631 0x00000000);
4632 /* Thermal management */
4633 register_thrm_sprs(env);
4634 /* Memory management */
4635 register_low_BATs(env);
4636 init_excp_7400(env);
4637 env->dcache_line_size = 32;
4638 env->icache_line_size = 32;
4639 /* Allocate hardware IRQ controller */
4640 ppc6xx_irq_init(env_archcpu(env));
4641 }
4642
4643 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4644 {
4645 DeviceClass *dc = DEVICE_CLASS(oc);
4646 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4647
4648 dc->desc = "PowerPC 7400 (aka G4)";
4649 pcc->init_proc = init_proc_7400;
4650 pcc->check_pow = check_pow_hid0;
4651 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4652 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4653 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4654 PPC_FLOAT_STFIWX |
4655 PPC_CACHE | PPC_CACHE_ICBI |
4656 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4657 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4658 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4659 PPC_MEM_TLBIA |
4660 PPC_SEGMENT | PPC_EXTERN |
4661 PPC_ALTIVEC;
4662 pcc->msr_mask = (1ull << MSR_VR) |
4663 (1ull << MSR_POW) |
4664 (1ull << MSR_ILE) |
4665 (1ull << MSR_EE) |
4666 (1ull << MSR_PR) |
4667 (1ull << MSR_FP) |
4668 (1ull << MSR_ME) |
4669 (1ull << MSR_FE0) |
4670 (1ull << MSR_SE) |
4671 (1ull << MSR_DE) |
4672 (1ull << MSR_FE1) |
4673 (1ull << MSR_EP) |
4674 (1ull << MSR_IR) |
4675 (1ull << MSR_DR) |
4676 (1ull << MSR_PMM) |
4677 (1ull << MSR_RI) |
4678 (1ull << MSR_LE);
4679 pcc->mmu_model = POWERPC_MMU_32B;
4680 pcc->excp_model = POWERPC_EXCP_74xx;
4681 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4682 pcc->bfd_mach = bfd_mach_ppc_7400;
4683 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4684 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4685 POWERPC_FLAG_BUS_CLK;
4686 }
4687
4688 static void init_proc_7410(CPUPPCState *env)
4689 {
4690 register_ne_601_sprs(env);
4691 register_sdr1_sprs(env);
4692 register_74xx_sprs(env);
4693 vscr_init(env, 0x00010000);
4694
4695 spr_register(env, SPR_UBAMR, "UBAMR",
4696 &spr_read_ureg, SPR_NOACCESS,
4697 &spr_read_ureg, SPR_NOACCESS,
4698 0x00000000);
4699 /* Thermal management */
4700 register_thrm_sprs(env);
4701 /* L2PMCR */
4702
4703 spr_register(env, SPR_L2PMCR, "L2PMCR",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 /* LDSTDB */
4708
4709 spr_register(env, SPR_LDSTDB, "LDSTDB",
4710 SPR_NOACCESS, SPR_NOACCESS,
4711 &spr_read_generic, &spr_write_generic,
4712 0x00000000);
4713 /* Memory management */
4714 register_low_BATs(env);
4715 init_excp_7400(env);
4716 env->dcache_line_size = 32;
4717 env->icache_line_size = 32;
4718 /* Allocate hardware IRQ controller */
4719 ppc6xx_irq_init(env_archcpu(env));
4720 }
4721
4722 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4723 {
4724 DeviceClass *dc = DEVICE_CLASS(oc);
4725 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4726
4727 dc->desc = "PowerPC 7410 (aka G4)";
4728 pcc->init_proc = init_proc_7410;
4729 pcc->check_pow = check_pow_hid0;
4730 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4731 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4732 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4733 PPC_FLOAT_STFIWX |
4734 PPC_CACHE | PPC_CACHE_ICBI |
4735 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4736 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4737 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4738 PPC_MEM_TLBIA |
4739 PPC_SEGMENT | PPC_EXTERN |
4740 PPC_ALTIVEC;
4741 pcc->msr_mask = (1ull << MSR_VR) |
4742 (1ull << MSR_POW) |
4743 (1ull << MSR_ILE) |
4744 (1ull << MSR_EE) |
4745 (1ull << MSR_PR) |
4746 (1ull << MSR_FP) |
4747 (1ull << MSR_ME) |
4748 (1ull << MSR_FE0) |
4749 (1ull << MSR_SE) |
4750 (1ull << MSR_DE) |
4751 (1ull << MSR_FE1) |
4752 (1ull << MSR_EP) |
4753 (1ull << MSR_IR) |
4754 (1ull << MSR_DR) |
4755 (1ull << MSR_PMM) |
4756 (1ull << MSR_RI) |
4757 (1ull << MSR_LE);
4758 pcc->mmu_model = POWERPC_MMU_32B;
4759 pcc->excp_model = POWERPC_EXCP_74xx;
4760 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4761 pcc->bfd_mach = bfd_mach_ppc_7400;
4762 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4763 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4764 POWERPC_FLAG_BUS_CLK;
4765 }
4766
4767 static void init_proc_7440(CPUPPCState *env)
4768 {
4769 register_ne_601_sprs(env);
4770 register_sdr1_sprs(env);
4771 register_74xx_sprs(env);
4772 vscr_init(env, 0x00010000);
4773
4774 spr_register(env, SPR_UBAMR, "UBAMR",
4775 &spr_read_ureg, SPR_NOACCESS,
4776 &spr_read_ureg, SPR_NOACCESS,
4777 0x00000000);
4778 /* LDSTCR */
4779 spr_register(env, SPR_LDSTCR, "LDSTCR",
4780 SPR_NOACCESS, SPR_NOACCESS,
4781 &spr_read_generic, &spr_write_generic,
4782 0x00000000);
4783 /* ICTRL */
4784 spr_register(env, SPR_ICTRL, "ICTRL",
4785 SPR_NOACCESS, SPR_NOACCESS,
4786 &spr_read_generic, &spr_write_generic,
4787 0x00000000);
4788 /* MSSSR0 */
4789 spr_register(env, SPR_MSSSR0, "MSSSR0",
4790 SPR_NOACCESS, SPR_NOACCESS,
4791 &spr_read_generic, &spr_write_generic,
4792 0x00000000);
4793 /* PMC */
4794 spr_register(env, SPR_7XX_PMC5, "PMC5",
4795 SPR_NOACCESS, SPR_NOACCESS,
4796 &spr_read_generic, &spr_write_generic,
4797 0x00000000);
4798
4799 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4800 &spr_read_ureg, SPR_NOACCESS,
4801 &spr_read_ureg, SPR_NOACCESS,
4802 0x00000000);
4803
4804 spr_register(env, SPR_7XX_PMC6, "PMC6",
4805 SPR_NOACCESS, SPR_NOACCESS,
4806 &spr_read_generic, &spr_write_generic,
4807 0x00000000);
4808
4809 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4810 &spr_read_ureg, SPR_NOACCESS,
4811 &spr_read_ureg, SPR_NOACCESS,
4812 0x00000000);
4813 /* Memory management */
4814 register_low_BATs(env);
4815 init_excp_7450(env);
4816 env->dcache_line_size = 32;
4817 env->icache_line_size = 32;
4818 /* Allocate hardware IRQ controller */
4819 ppc6xx_irq_init(env_archcpu(env));
4820 }
4821
4822 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4823 {
4824 DeviceClass *dc = DEVICE_CLASS(oc);
4825 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4826
4827 dc->desc = "PowerPC 7440 (aka G4)";
4828 pcc->init_proc = init_proc_7440;
4829 pcc->check_pow = check_pow_hid0_74xx;
4830 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4831 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4832 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4833 PPC_FLOAT_STFIWX |
4834 PPC_CACHE | PPC_CACHE_ICBI |
4835 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4836 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4837 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4838 PPC_MEM_TLBIA |
4839 PPC_SEGMENT | PPC_EXTERN |
4840 PPC_ALTIVEC;
4841 pcc->msr_mask = (1ull << MSR_VR) |
4842 (1ull << MSR_POW) |
4843 (1ull << MSR_ILE) |
4844 (1ull << MSR_EE) |
4845 (1ull << MSR_PR) |
4846 (1ull << MSR_FP) |
4847 (1ull << MSR_ME) |
4848 (1ull << MSR_FE0) |
4849 (1ull << MSR_SE) |
4850 (1ull << MSR_DE) |
4851 (1ull << MSR_FE1) |
4852 (1ull << MSR_EP) |
4853 (1ull << MSR_IR) |
4854 (1ull << MSR_DR) |
4855 (1ull << MSR_PMM) |
4856 (1ull << MSR_RI) |
4857 (1ull << MSR_LE);
4858 pcc->mmu_model = POWERPC_MMU_32B;
4859 pcc->excp_model = POWERPC_EXCP_74xx;
4860 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4861 pcc->bfd_mach = bfd_mach_ppc_7400;
4862 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4863 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4864 POWERPC_FLAG_BUS_CLK;
4865 }
4866
4867 static void init_proc_7450(CPUPPCState *env)
4868 {
4869 register_ne_601_sprs(env);
4870 register_sdr1_sprs(env);
4871 register_74xx_sprs(env);
4872 vscr_init(env, 0x00010000);
4873 /* Level 3 cache control */
4874 register_l3_ctrl(env);
4875 /* L3ITCR1 */
4876 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4877 SPR_NOACCESS, SPR_NOACCESS,
4878 &spr_read_generic, &spr_write_generic,
4879 0x00000000);
4880 /* L3ITCR2 */
4881 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4882 SPR_NOACCESS, SPR_NOACCESS,
4883 &spr_read_generic, &spr_write_generic,
4884 0x00000000);
4885 /* L3ITCR3 */
4886 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4887 SPR_NOACCESS, SPR_NOACCESS,
4888 &spr_read_generic, &spr_write_generic,
4889 0x00000000);
4890 /* L3OHCR */
4891 spr_register(env, SPR_L3OHCR, "L3OHCR",
4892 SPR_NOACCESS, SPR_NOACCESS,
4893 &spr_read_generic, &spr_write_generic,
4894 0x00000000);
4895
4896 spr_register(env, SPR_UBAMR, "UBAMR",
4897 &spr_read_ureg, SPR_NOACCESS,
4898 &spr_read_ureg, SPR_NOACCESS,
4899 0x00000000);
4900 /* LDSTCR */
4901 spr_register(env, SPR_LDSTCR, "LDSTCR",
4902 SPR_NOACCESS, SPR_NOACCESS,
4903 &spr_read_generic, &spr_write_generic,
4904 0x00000000);
4905 /* ICTRL */
4906 spr_register(env, SPR_ICTRL, "ICTRL",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910 /* MSSSR0 */
4911 spr_register(env, SPR_MSSSR0, "MSSSR0",
4912 SPR_NOACCESS, SPR_NOACCESS,
4913 &spr_read_generic, &spr_write_generic,
4914 0x00000000);
4915 /* PMC */
4916 spr_register(env, SPR_7XX_PMC5, "PMC5",
4917 SPR_NOACCESS, SPR_NOACCESS,
4918 &spr_read_generic, &spr_write_generic,
4919 0x00000000);
4920
4921 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4922 &spr_read_ureg, SPR_NOACCESS,
4923 &spr_read_ureg, SPR_NOACCESS,
4924 0x00000000);
4925
4926 spr_register(env, SPR_7XX_PMC6, "PMC6",
4927 SPR_NOACCESS, SPR_NOACCESS,
4928 &spr_read_generic, &spr_write_generic,
4929 0x00000000);
4930
4931 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4932 &spr_read_ureg, SPR_NOACCESS,
4933 &spr_read_ureg, SPR_NOACCESS,
4934 0x00000000);
4935 /* Memory management */
4936 register_low_BATs(env);
4937 init_excp_7450(env);
4938 env->dcache_line_size = 32;
4939 env->icache_line_size = 32;
4940 /* Allocate hardware IRQ controller */
4941 ppc6xx_irq_init(env_archcpu(env));
4942 }
4943
4944 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4945 {
4946 DeviceClass *dc = DEVICE_CLASS(oc);
4947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4948
4949 dc->desc = "PowerPC 7450 (aka G4)";
4950 pcc->init_proc = init_proc_7450;
4951 pcc->check_pow = check_pow_hid0_74xx;
4952 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4953 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4954 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4955 PPC_FLOAT_STFIWX |
4956 PPC_CACHE | PPC_CACHE_ICBI |
4957 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4958 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4959 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4960 PPC_MEM_TLBIA |
4961 PPC_SEGMENT | PPC_EXTERN |
4962 PPC_ALTIVEC;
4963 pcc->msr_mask = (1ull << MSR_VR) |
4964 (1ull << MSR_POW) |
4965 (1ull << MSR_ILE) |
4966 (1ull << MSR_EE) |
4967 (1ull << MSR_PR) |
4968 (1ull << MSR_FP) |
4969 (1ull << MSR_ME) |
4970 (1ull << MSR_FE0) |
4971 (1ull << MSR_SE) |
4972 (1ull << MSR_DE) |
4973 (1ull << MSR_FE1) |
4974 (1ull << MSR_EP) |
4975 (1ull << MSR_IR) |
4976 (1ull << MSR_DR) |
4977 (1ull << MSR_PMM) |
4978 (1ull << MSR_RI) |
4979 (1ull << MSR_LE);
4980 pcc->mmu_model = POWERPC_MMU_32B;
4981 pcc->excp_model = POWERPC_EXCP_74xx;
4982 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4983 pcc->bfd_mach = bfd_mach_ppc_7400;
4984 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4985 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4986 POWERPC_FLAG_BUS_CLK;
4987 }
4988
4989 static void init_proc_7445(CPUPPCState *env)
4990 {
4991 register_ne_601_sprs(env);
4992 register_sdr1_sprs(env);
4993 register_74xx_sprs(env);
4994 vscr_init(env, 0x00010000);
4995 /* LDSTCR */
4996 spr_register(env, SPR_LDSTCR, "LDSTCR",
4997 SPR_NOACCESS, SPR_NOACCESS,
4998 &spr_read_generic, &spr_write_generic,
4999 0x00000000);
5000 /* ICTRL */
5001 spr_register(env, SPR_ICTRL, "ICTRL",
5002 SPR_NOACCESS, SPR_NOACCESS,
5003 &spr_read_generic, &spr_write_generic,
5004 0x00000000);
5005 /* MSSSR0 */
5006 spr_register(env, SPR_MSSSR0, "MSSSR0",
5007 SPR_NOACCESS, SPR_NOACCESS,
5008 &spr_read_generic, &spr_write_generic,
5009 0x00000000);
5010 /* PMC */
5011 spr_register(env, SPR_7XX_PMC5, "PMC5",
5012 SPR_NOACCESS, SPR_NOACCESS,
5013 &spr_read_generic, &spr_write_generic,
5014 0x00000000);
5015
5016 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5017 &spr_read_ureg, SPR_NOACCESS,
5018 &spr_read_ureg, SPR_NOACCESS,
5019 0x00000000);
5020
5021 spr_register(env, SPR_7XX_PMC6, "PMC6",
5022 SPR_NOACCESS, SPR_NOACCESS,
5023 &spr_read_generic, &spr_write_generic,
5024 0x00000000);
5025
5026 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5027 &spr_read_ureg, SPR_NOACCESS,
5028 &spr_read_ureg, SPR_NOACCESS,
5029 0x00000000);
5030 /* SPRGs */
5031 spr_register(env, SPR_SPRG4, "SPRG4",
5032 SPR_NOACCESS, SPR_NOACCESS,
5033 &spr_read_generic, &spr_write_generic,
5034 0x00000000);
5035 spr_register(env, SPR_USPRG4, "USPRG4",
5036 &spr_read_ureg, SPR_NOACCESS,
5037 &spr_read_ureg, SPR_NOACCESS,
5038 0x00000000);
5039 spr_register(env, SPR_SPRG5, "SPRG5",
5040 SPR_NOACCESS, SPR_NOACCESS,
5041 &spr_read_generic, &spr_write_generic,
5042 0x00000000);
5043 spr_register(env, SPR_USPRG5, "USPRG5",
5044 &spr_read_ureg, SPR_NOACCESS,
5045 &spr_read_ureg, SPR_NOACCESS,
5046 0x00000000);
5047 spr_register(env, SPR_SPRG6, "SPRG6",
5048 SPR_NOACCESS, SPR_NOACCESS,
5049 &spr_read_generic, &spr_write_generic,
5050 0x00000000);
5051 spr_register(env, SPR_USPRG6, "USPRG6",
5052 &spr_read_ureg, SPR_NOACCESS,
5053 &spr_read_ureg, SPR_NOACCESS,
5054 0x00000000);
5055 spr_register(env, SPR_SPRG7, "SPRG7",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 0x00000000);
5059 spr_register(env, SPR_USPRG7, "USPRG7",
5060 &spr_read_ureg, SPR_NOACCESS,
5061 &spr_read_ureg, SPR_NOACCESS,
5062 0x00000000);
5063 /* Memory management */
5064 register_low_BATs(env);
5065 register_high_BATs(env);
5066 init_excp_7450(env);
5067 env->dcache_line_size = 32;
5068 env->icache_line_size = 32;
5069 /* Allocate hardware IRQ controller */
5070 ppc6xx_irq_init(env_archcpu(env));
5071 }
5072
5073 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
5074 {
5075 DeviceClass *dc = DEVICE_CLASS(oc);
5076 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5077
5078 dc->desc = "PowerPC 7445 (aka G4)";
5079 pcc->init_proc = init_proc_7445;
5080 pcc->check_pow = check_pow_hid0_74xx;
5081 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5082 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5083 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5084 PPC_FLOAT_STFIWX |
5085 PPC_CACHE | PPC_CACHE_ICBI |
5086 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5087 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5088 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5089 PPC_MEM_TLBIA |
5090 PPC_SEGMENT | PPC_EXTERN |
5091 PPC_ALTIVEC;
5092 pcc->msr_mask = (1ull << MSR_VR) |
5093 (1ull << MSR_POW) |
5094 (1ull << MSR_ILE) |
5095 (1ull << MSR_EE) |
5096 (1ull << MSR_PR) |
5097 (1ull << MSR_FP) |
5098 (1ull << MSR_ME) |
5099 (1ull << MSR_FE0) |
5100 (1ull << MSR_SE) |
5101 (1ull << MSR_DE) |
5102 (1ull << MSR_FE1) |
5103 (1ull << MSR_EP) |
5104 (1ull << MSR_IR) |
5105 (1ull << MSR_DR) |
5106 (1ull << MSR_PMM) |
5107 (1ull << MSR_RI) |
5108 (1ull << MSR_LE);
5109 pcc->mmu_model = POWERPC_MMU_32B;
5110 pcc->excp_model = POWERPC_EXCP_74xx;
5111 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5112 pcc->bfd_mach = bfd_mach_ppc_7400;
5113 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5114 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5115 POWERPC_FLAG_BUS_CLK;
5116 }
5117
5118 static void init_proc_7455(CPUPPCState *env)
5119 {
5120 register_ne_601_sprs(env);
5121 register_sdr1_sprs(env);
5122 register_74xx_sprs(env);
5123 vscr_init(env, 0x00010000);
5124 /* Level 3 cache control */
5125 register_l3_ctrl(env);
5126 /* LDSTCR */
5127 spr_register(env, SPR_LDSTCR, "LDSTCR",
5128 SPR_NOACCESS, SPR_NOACCESS,
5129 &spr_read_generic, &spr_write_generic,
5130 0x00000000);
5131 /* ICTRL */
5132 spr_register(env, SPR_ICTRL, "ICTRL",
5133 SPR_NOACCESS, SPR_NOACCESS,
5134 &spr_read_generic, &spr_write_generic,
5135 0x00000000);
5136 /* MSSSR0 */
5137 spr_register(env, SPR_MSSSR0, "MSSSR0",
5138 SPR_NOACCESS, SPR_NOACCESS,
5139 &spr_read_generic, &spr_write_generic,
5140 0x00000000);
5141 /* PMC */
5142 spr_register(env, SPR_7XX_PMC5, "PMC5",
5143 SPR_NOACCESS, SPR_NOACCESS,
5144 &spr_read_generic, &spr_write_generic,
5145 0x00000000);
5146
5147 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5148 &spr_read_ureg, SPR_NOACCESS,
5149 &spr_read_ureg, SPR_NOACCESS,
5150 0x00000000);
5151
5152 spr_register(env, SPR_7XX_PMC6, "PMC6",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 0x00000000);
5156
5157 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5158 &spr_read_ureg, SPR_NOACCESS,
5159 &spr_read_ureg, SPR_NOACCESS,
5160 0x00000000);
5161 /* SPRGs */
5162 spr_register(env, SPR_SPRG4, "SPRG4",
5163 SPR_NOACCESS, SPR_NOACCESS,
5164 &spr_read_generic, &spr_write_generic,
5165 0x00000000);
5166 spr_register(env, SPR_USPRG4, "USPRG4",
5167 &spr_read_ureg, SPR_NOACCESS,
5168 &spr_read_ureg, SPR_NOACCESS,
5169 0x00000000);
5170 spr_register(env, SPR_SPRG5, "SPRG5",
5171 SPR_NOACCESS, SPR_NOACCESS,
5172 &spr_read_generic, &spr_write_generic,
5173 0x00000000);
5174 spr_register(env, SPR_USPRG5, "USPRG5",
5175 &spr_read_ureg, SPR_NOACCESS,
5176 &spr_read_ureg, SPR_NOACCESS,
5177 0x00000000);
5178 spr_register(env, SPR_SPRG6, "SPRG6",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 spr_register(env, SPR_USPRG6, "USPRG6",
5183 &spr_read_ureg, SPR_NOACCESS,
5184 &spr_read_ureg, SPR_NOACCESS,
5185 0x00000000);
5186 spr_register(env, SPR_SPRG7, "SPRG7",
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_generic,
5189 0x00000000);
5190 spr_register(env, SPR_USPRG7, "USPRG7",
5191 &spr_read_ureg, SPR_NOACCESS,
5192 &spr_read_ureg, SPR_NOACCESS,
5193 0x00000000);
5194 /* Memory management */
5195 register_low_BATs(env);
5196 register_high_BATs(env);
5197 init_excp_7450(env);
5198 env->dcache_line_size = 32;
5199 env->icache_line_size = 32;
5200 /* Allocate hardware IRQ controller */
5201 ppc6xx_irq_init(env_archcpu(env));
5202 }
5203
5204 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
5205 {
5206 DeviceClass *dc = DEVICE_CLASS(oc);
5207 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5208
5209 dc->desc = "PowerPC 7455 (aka G4)";
5210 pcc->init_proc = init_proc_7455;
5211 pcc->check_pow = check_pow_hid0_74xx;
5212 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5213 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5214 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5215 PPC_FLOAT_STFIWX |
5216 PPC_CACHE | PPC_CACHE_ICBI |
5217 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5218 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5219 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5220 PPC_MEM_TLBIA |
5221 PPC_SEGMENT | PPC_EXTERN |
5222 PPC_ALTIVEC;
5223 pcc->msr_mask = (1ull << MSR_VR) |
5224 (1ull << MSR_POW) |
5225 (1ull << MSR_ILE) |
5226 (1ull << MSR_EE) |
5227 (1ull << MSR_PR) |
5228 (1ull << MSR_FP) |
5229 (1ull << MSR_ME) |
5230 (1ull << MSR_FE0) |
5231 (1ull << MSR_SE) |
5232 (1ull << MSR_DE) |
5233 (1ull << MSR_FE1) |
5234 (1ull << MSR_EP) |
5235 (1ull << MSR_IR) |
5236 (1ull << MSR_DR) |
5237 (1ull << MSR_PMM) |
5238 (1ull << MSR_RI) |
5239 (1ull << MSR_LE);
5240 pcc->mmu_model = POWERPC_MMU_32B;
5241 pcc->excp_model = POWERPC_EXCP_74xx;
5242 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5243 pcc->bfd_mach = bfd_mach_ppc_7400;
5244 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5245 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5246 POWERPC_FLAG_BUS_CLK;
5247 }
5248
5249 static void init_proc_7457(CPUPPCState *env)
5250 {
5251 register_ne_601_sprs(env);
5252 register_sdr1_sprs(env);
5253 register_74xx_sprs(env);
5254 vscr_init(env, 0x00010000);
5255 /* Level 3 cache control */
5256 register_l3_ctrl(env);
5257 /* L3ITCR1 */
5258 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5259 SPR_NOACCESS, SPR_NOACCESS,
5260 &spr_read_generic, &spr_write_generic,
5261 0x00000000);
5262 /* L3ITCR2 */
5263 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 /* L3ITCR3 */
5268 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 0x00000000);
5272 /* L3OHCR */
5273 spr_register(env, SPR_L3OHCR, "L3OHCR",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 0x00000000);
5277 /* LDSTCR */
5278 spr_register(env, SPR_LDSTCR, "LDSTCR",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 /* ICTRL */
5283 spr_register(env, SPR_ICTRL, "ICTRL",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287 /* MSSSR0 */
5288 spr_register(env, SPR_MSSSR0, "MSSSR0",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 0x00000000);
5292 /* PMC */
5293 spr_register(env, SPR_7XX_PMC5, "PMC5",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297
5298 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5299 &spr_read_ureg, SPR_NOACCESS,
5300 &spr_read_ureg, SPR_NOACCESS,
5301 0x00000000);
5302
5303 spr_register(env, SPR_7XX_PMC6, "PMC6",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307
5308 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5309 &spr_read_ureg, SPR_NOACCESS,
5310 &spr_read_ureg, SPR_NOACCESS,
5311 0x00000000);
5312 /* SPRGs */
5313 spr_register(env, SPR_SPRG4, "SPRG4",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 0x00000000);
5317 spr_register(env, SPR_USPRG4, "USPRG4",
5318 &spr_read_ureg, SPR_NOACCESS,
5319 &spr_read_ureg, SPR_NOACCESS,
5320 0x00000000);
5321 spr_register(env, SPR_SPRG5, "SPRG5",
5322 SPR_NOACCESS, SPR_NOACCESS,
5323 &spr_read_generic, &spr_write_generic,
5324 0x00000000);
5325 spr_register(env, SPR_USPRG5, "USPRG5",
5326 &spr_read_ureg, SPR_NOACCESS,
5327 &spr_read_ureg, SPR_NOACCESS,
5328 0x00000000);
5329 spr_register(env, SPR_SPRG6, "SPRG6",
5330 SPR_NOACCESS, SPR_NOACCESS,
5331 &spr_read_generic, &spr_write_generic,
5332 0x00000000);
5333 spr_register(env, SPR_USPRG6, "USPRG6",
5334 &spr_read_ureg, SPR_NOACCESS,
5335 &spr_read_ureg, SPR_NOACCESS,
5336 0x00000000);
5337 spr_register(env, SPR_SPRG7, "SPRG7",
5338 SPR_NOACCESS, SPR_NOACCESS,
5339 &spr_read_generic, &spr_write_generic,
5340 0x00000000);
5341 spr_register(env, SPR_USPRG7, "USPRG7",
5342 &spr_read_ureg, SPR_NOACCESS,
5343 &spr_read_ureg, SPR_NOACCESS,
5344 0x00000000);
5345 /* Memory management */
5346 register_low_BATs(env);
5347 register_high_BATs(env);
5348 init_excp_7450(env);
5349 env->dcache_line_size = 32;
5350 env->icache_line_size = 32;
5351 /* Allocate hardware IRQ controller */
5352 ppc6xx_irq_init(env_archcpu(env));
5353 }
5354
5355 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
5356 {
5357 DeviceClass *dc = DEVICE_CLASS(oc);
5358 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5359
5360 dc->desc = "PowerPC 7457 (aka G4)";
5361 pcc->init_proc = init_proc_7457;
5362 pcc->check_pow = check_pow_hid0_74xx;
5363 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5364 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5365 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5366 PPC_FLOAT_STFIWX |
5367 PPC_CACHE | PPC_CACHE_ICBI |
5368 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5369 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5370 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5371 PPC_MEM_TLBIA |
5372 PPC_SEGMENT | PPC_EXTERN |
5373 PPC_ALTIVEC;
5374 pcc->msr_mask = (1ull << MSR_VR) |
5375 (1ull << MSR_POW) |
5376 (1ull << MSR_ILE) |
5377 (1ull << MSR_EE) |
5378 (1ull << MSR_PR) |
5379 (1ull << MSR_FP) |
5380 (1ull << MSR_ME) |
5381 (1ull << MSR_FE0) |
5382 (1ull << MSR_SE) |
5383 (1ull << MSR_DE) |
5384 (1ull << MSR_FE1) |
5385 (1ull << MSR_EP) |
5386 (1ull << MSR_IR) |
5387 (1ull << MSR_DR) |
5388 (1ull << MSR_PMM) |
5389 (1ull << MSR_RI) |
5390 (1ull << MSR_LE);
5391 pcc->mmu_model = POWERPC_MMU_32B;
5392 pcc->excp_model = POWERPC_EXCP_74xx;
5393 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5394 pcc->bfd_mach = bfd_mach_ppc_7400;
5395 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5396 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5397 POWERPC_FLAG_BUS_CLK;
5398 }
5399
5400 static void init_proc_e600(CPUPPCState *env)
5401 {
5402 register_ne_601_sprs(env);
5403 register_sdr1_sprs(env);
5404 register_74xx_sprs(env);
5405 vscr_init(env, 0x00010000);
5406
5407 spr_register(env, SPR_UBAMR, "UBAMR",
5408 &spr_read_ureg, SPR_NOACCESS,
5409 &spr_read_ureg, SPR_NOACCESS,
5410 0x00000000);
5411
5412 spr_register(env, SPR_LDSTCR, "LDSTCR",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 &spr_read_generic, &spr_write_generic,
5415 0x00000000);
5416
5417 spr_register(env, SPR_ICTRL, "ICTRL",
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 &spr_read_generic, &spr_write_generic,
5420 0x00000000);
5421
5422 spr_register(env, SPR_MSSSR0, "MSSSR0",
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 &spr_read_generic, &spr_write_generic,
5425 0x00000000);
5426
5427 spr_register(env, SPR_7XX_PMC5, "PMC5",
5428 SPR_NOACCESS, SPR_NOACCESS,
5429 &spr_read_generic, &spr_write_generic,
5430 0x00000000);
5431
5432 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5433 &spr_read_ureg, SPR_NOACCESS,
5434 &spr_read_ureg, SPR_NOACCESS,
5435 0x00000000);
5436
5437 spr_register(env, SPR_7XX_PMC6, "PMC6",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441
5442 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5443 &spr_read_ureg, SPR_NOACCESS,
5444 &spr_read_ureg, SPR_NOACCESS,
5445 0x00000000);
5446 /* SPRGs */
5447 spr_register(env, SPR_SPRG4, "SPRG4",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 spr_register(env, SPR_USPRG4, "USPRG4",
5452 &spr_read_ureg, SPR_NOACCESS,
5453 &spr_read_ureg, SPR_NOACCESS,
5454 0x00000000);
5455 spr_register(env, SPR_SPRG5, "SPRG5",
5456 SPR_NOACCESS, SPR_NOACCESS,
5457 &spr_read_generic, &spr_write_generic,
5458 0x00000000);
5459 spr_register(env, SPR_USPRG5, "USPRG5",
5460 &spr_read_ureg, SPR_NOACCESS,
5461 &spr_read_ureg, SPR_NOACCESS,
5462 0x00000000);
5463 spr_register(env, SPR_SPRG6, "SPRG6",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 &spr_read_generic, &spr_write_generic,
5466 0x00000000);
5467 spr_register(env, SPR_USPRG6, "USPRG6",
5468 &spr_read_ureg, SPR_NOACCESS,
5469 &spr_read_ureg, SPR_NOACCESS,
5470 0x00000000);
5471 spr_register(env, SPR_SPRG7, "SPRG7",
5472 SPR_NOACCESS, SPR_NOACCESS,
5473 &spr_read_generic, &spr_write_generic,
5474 0x00000000);
5475 spr_register(env, SPR_USPRG7, "USPRG7",
5476 &spr_read_ureg, SPR_NOACCESS,
5477 &spr_read_ureg, SPR_NOACCESS,
5478 0x00000000);
5479 /* Memory management */
5480 register_low_BATs(env);
5481 register_high_BATs(env);
5482 init_excp_7450(env);
5483 env->dcache_line_size = 32;
5484 env->icache_line_size = 32;
5485 /* Allocate hardware IRQ controller */
5486 ppc6xx_irq_init(env_archcpu(env));
5487 }
5488
5489 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
5490 {
5491 DeviceClass *dc = DEVICE_CLASS(oc);
5492 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5493
5494 dc->desc = "PowerPC e600";
5495 pcc->init_proc = init_proc_e600;
5496 pcc->check_pow = check_pow_hid0_74xx;
5497 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5498 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5499 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5500 PPC_FLOAT_STFIWX |
5501 PPC_CACHE | PPC_CACHE_ICBI |
5502 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5503 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5504 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5505 PPC_MEM_TLBIA |
5506 PPC_SEGMENT | PPC_EXTERN |
5507 PPC_ALTIVEC;
5508 pcc->insns_flags2 = PPC_NONE;
5509 pcc->msr_mask = (1ull << MSR_VR) |
5510 (1ull << MSR_POW) |
5511 (1ull << MSR_ILE) |
5512 (1ull << MSR_EE) |
5513 (1ull << MSR_PR) |
5514 (1ull << MSR_FP) |
5515 (1ull << MSR_ME) |
5516 (1ull << MSR_FE0) |
5517 (1ull << MSR_SE) |
5518 (1ull << MSR_DE) |
5519 (1ull << MSR_FE1) |
5520 (1ull << MSR_EP) |
5521 (1ull << MSR_IR) |
5522 (1ull << MSR_DR) |
5523 (1ull << MSR_PMM) |
5524 (1ull << MSR_RI) |
5525 (1ull << MSR_LE);
5526 pcc->mmu_model = POWERPC_MMU_32B;
5527 pcc->excp_model = POWERPC_EXCP_74xx;
5528 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5529 pcc->bfd_mach = bfd_mach_ppc_7400;
5530 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5531 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5532 POWERPC_FLAG_BUS_CLK;
5533 }
5534
5535 #if defined(TARGET_PPC64)
5536 #if defined(CONFIG_USER_ONLY)
5537 #define POWERPC970_HID5_INIT 0x00000080
5538 #else
5539 #define POWERPC970_HID5_INIT 0x00000000
5540 #endif
5541
5542 static int check_pow_970(CPUPPCState *env)
5543 {
5544 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5545 return 1;
5546 }
5547
5548 return 0;
5549 }
5550
5551 static void register_970_hid_sprs(CPUPPCState *env)
5552 {
5553 /* Hardware implementation registers */
5554 spr_register(env, SPR_HID0, "HID0",
5555 SPR_NOACCESS, SPR_NOACCESS,
5556 &spr_read_generic, &spr_write_clear,
5557 0x60000000);
5558 spr_register(env, SPR_HID1, "HID1",
5559 SPR_NOACCESS, SPR_NOACCESS,
5560 &spr_read_generic, &spr_write_generic,
5561 0x00000000);
5562 spr_register(env, SPR_970_HID5, "HID5",
5563 SPR_NOACCESS, SPR_NOACCESS,
5564 &spr_read_generic, &spr_write_generic,
5565 POWERPC970_HID5_INIT);
5566 }
5567
5568 static void register_970_hior_sprs(CPUPPCState *env)
5569 {
5570 spr_register(env, SPR_HIOR, "SPR_HIOR",
5571 SPR_NOACCESS, SPR_NOACCESS,
5572 &spr_read_hior, &spr_write_hior,
5573 0x00000000);
5574 }
5575
5576 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5577 {
5578 spr_register(env, SPR_CTRL, "SPR_CTRL",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 SPR_NOACCESS, &spr_write_CTRL,
5581 0x00000000);
5582 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5583 &spr_read_ureg, SPR_NOACCESS,
5584 &spr_read_ureg, SPR_NOACCESS,
5585 0x00000000);
5586 }
5587
5588 static void register_book3s_altivec_sprs(CPUPPCState *env)
5589 {
5590 if (!(env->insns_flags & PPC_ALTIVEC)) {
5591 return;
5592 }
5593
5594 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5595 &spr_read_generic, &spr_write_generic,
5596 &spr_read_generic, &spr_write_generic,
5597 KVM_REG_PPC_VRSAVE, 0x00000000);
5598
5599 }
5600
5601 static void register_book3s_dbg_sprs(CPUPPCState *env)
5602 {
5603 /*
5604 * TODO: different specs define different scopes for these,
5605 * will have to address this:
5606 * 970: super/write and super/read
5607 * powerisa 2.03..2.04: hypv/write and super/read.
5608 * powerisa 2.05 and newer: hypv/write and hypv/read.
5609 */
5610 spr_register_kvm(env, SPR_DABR, "DABR",
5611 SPR_NOACCESS, SPR_NOACCESS,
5612 &spr_read_generic, &spr_write_generic,
5613 KVM_REG_PPC_DABR, 0x00000000);
5614 spr_register_kvm(env, SPR_DABRX, "DABRX",
5615 SPR_NOACCESS, SPR_NOACCESS,
5616 &spr_read_generic, &spr_write_generic,
5617 KVM_REG_PPC_DABRX, 0x00000000);
5618 }
5619
5620 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5621 {
5622 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5623 SPR_NOACCESS, SPR_NOACCESS,
5624 SPR_NOACCESS, SPR_NOACCESS,
5625 &spr_read_generic, &spr_write_generic,
5626 KVM_REG_PPC_DAWR, 0x00000000);
5627 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5628 SPR_NOACCESS, SPR_NOACCESS,
5629 SPR_NOACCESS, SPR_NOACCESS,
5630 &spr_read_generic, &spr_write_generic,
5631 KVM_REG_PPC_DAWRX, 0x00000000);
5632 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5633 SPR_NOACCESS, SPR_NOACCESS,
5634 SPR_NOACCESS, SPR_NOACCESS,
5635 &spr_read_generic, &spr_write_generic,
5636 KVM_REG_PPC_CIABR, 0x00000000);
5637 }
5638
5639 static void register_970_dbg_sprs(CPUPPCState *env)
5640 {
5641 /* Breakpoints */
5642 spr_register(env, SPR_IABR, "IABR",
5643 SPR_NOACCESS, SPR_NOACCESS,
5644 &spr_read_generic, &spr_write_generic,
5645 0x00000000);
5646 }
5647
5648 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5649 {
5650 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5651 SPR_NOACCESS, SPR_NOACCESS,
5652 &spr_read_generic, &spr_write_MMCR0,
5653 KVM_REG_PPC_MMCR0, 0x80000000);
5654 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5655 SPR_NOACCESS, SPR_NOACCESS,
5656 &spr_read_generic, &spr_write_MMCR1,
5657 KVM_REG_PPC_MMCR1, 0x00000000);
5658 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, &spr_write_generic,
5661 KVM_REG_PPC_MMCRA, 0x00000000);
5662 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5663 SPR_NOACCESS, SPR_NOACCESS,
5664 &spr_read_PMC, &spr_write_PMC,
5665 KVM_REG_PPC_PMC1, 0x00000000);
5666 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_PMC, &spr_write_PMC,
5669 KVM_REG_PPC_PMC2, 0x00000000);
5670 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5671 SPR_NOACCESS, SPR_NOACCESS,
5672 &spr_read_PMC, &spr_write_PMC,
5673 KVM_REG_PPC_PMC3, 0x00000000);
5674 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5675 SPR_NOACCESS, SPR_NOACCESS,
5676 &spr_read_PMC, &spr_write_PMC,
5677 KVM_REG_PPC_PMC4, 0x00000000);
5678 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_PMC, &spr_write_PMC,
5681 KVM_REG_PPC_PMC5, 0x00000000);
5682 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5683 SPR_NOACCESS, SPR_NOACCESS,
5684 &spr_read_PMC, &spr_write_PMC,
5685 KVM_REG_PPC_PMC6, 0x00000000);
5686 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 KVM_REG_PPC_SIAR, 0x00000000);
5690 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5691 SPR_NOACCESS, SPR_NOACCESS,
5692 &spr_read_generic, &spr_write_generic,
5693 KVM_REG_PPC_SDAR, 0x00000000);
5694 }
5695
5696 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5697 {
5698 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5699 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5700 &spr_read_ureg, &spr_write_ureg,
5701 0x80000000);
5702 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5703 &spr_read_ureg, SPR_NOACCESS,
5704 &spr_read_ureg, &spr_write_ureg,
5705 0x00000000);
5706 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5707 &spr_read_ureg, SPR_NOACCESS,
5708 &spr_read_ureg, &spr_write_ureg,
5709 0x00000000);
5710 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5711 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5712 &spr_read_ureg, &spr_write_ureg,
5713 0x00000000);
5714 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5715 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5716 &spr_read_ureg, &spr_write_ureg,
5717 0x00000000);
5718 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5719 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5720 &spr_read_ureg, &spr_write_ureg,
5721 0x00000000);
5722 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5723 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5724 &spr_read_ureg, &spr_write_ureg,
5725 0x00000000);
5726 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5727 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5728 &spr_read_ureg, &spr_write_ureg,
5729 0x00000000);
5730 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5731 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5732 &spr_read_ureg, &spr_write_ureg,
5733 0x00000000);
5734 spr_register(env, SPR_POWER_USIAR, "USIAR",
5735 &spr_read_ureg, SPR_NOACCESS,
5736 &spr_read_ureg, &spr_write_ureg,
5737 0x00000000);
5738 spr_register(env, SPR_POWER_USDAR, "USDAR",
5739 &spr_read_ureg, SPR_NOACCESS,
5740 &spr_read_ureg, &spr_write_ureg,
5741 0x00000000);
5742 }
5743
5744 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5745 {
5746 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 &spr_read_generic, &spr_write_generic,
5749 KVM_REG_PPC_PMC7, 0x00000000);
5750 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5751 SPR_NOACCESS, SPR_NOACCESS,
5752 &spr_read_generic, &spr_write_generic,
5753 KVM_REG_PPC_PMC8, 0x00000000);
5754 }
5755
5756 static void register_970_pmu_user_sprs(CPUPPCState *env)
5757 {
5758 spr_register(env, SPR_970_UPMC7, "UPMC7",
5759 &spr_read_ureg, SPR_NOACCESS,
5760 &spr_read_ureg, &spr_write_ureg,
5761 0x00000000);
5762 spr_register(env, SPR_970_UPMC8, "UPMC8",
5763 &spr_read_ureg, SPR_NOACCESS,
5764 &spr_read_ureg, &spr_write_ureg,
5765 0x00000000);
5766 }
5767
5768 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5769 {
5770 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5771 SPR_NOACCESS, SPR_NOACCESS,
5772 &spr_read_generic, &spr_write_generic,
5773 KVM_REG_PPC_MMCR2, 0x00000000);
5774 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5775 SPR_NOACCESS, SPR_NOACCESS,
5776 &spr_read_generic, &spr_write_generic,
5777 KVM_REG_PPC_MMCRS, 0x00000000);
5778 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5779 SPR_NOACCESS, SPR_NOACCESS,
5780 &spr_read_generic, &spr_write_generic,
5781 KVM_REG_PPC_SIER, 0x00000000);
5782 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5783 SPR_NOACCESS, SPR_NOACCESS,
5784 &spr_read_generic, &spr_write_generic,
5785 KVM_REG_PPC_SPMC1, 0x00000000);
5786 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5787 SPR_NOACCESS, SPR_NOACCESS,
5788 &spr_read_generic, &spr_write_generic,
5789 KVM_REG_PPC_SPMC2, 0x00000000);
5790 spr_register_kvm(env, SPR_TACR, "TACR",
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 &spr_read_generic, &spr_write_generic,
5793 KVM_REG_PPC_TACR, 0x00000000);
5794 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5795 SPR_NOACCESS, SPR_NOACCESS,
5796 &spr_read_generic, &spr_write_generic,
5797 KVM_REG_PPC_TCSCR, 0x00000000);
5798 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5799 SPR_NOACCESS, SPR_NOACCESS,
5800 &spr_read_generic, &spr_write_generic,
5801 KVM_REG_PPC_CSIGR, 0x00000000);
5802 }
5803
5804 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5805 {
5806 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5807 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5808 &spr_read_ureg, &spr_write_ureg,
5809 0x00000000);
5810 spr_register(env, SPR_POWER_USIER, "USIER",
5811 &spr_read_generic, SPR_NOACCESS,
5812 &spr_read_generic, &spr_write_generic,
5813 0x00000000);
5814 }
5815
5816 static void register_power5p_ear_sprs(CPUPPCState *env)
5817 {
5818 /* External access control */
5819 spr_register(env, SPR_EAR, "EAR",
5820 SPR_NOACCESS, SPR_NOACCESS,
5821 &spr_read_generic, &spr_write_generic,
5822 0x00000000);
5823 }
5824
5825 static void register_power5p_tb_sprs(CPUPPCState *env)
5826 {
5827 /* TBU40 (High 40 bits of the Timebase register */
5828 spr_register_hv(env, SPR_TBU40, "TBU40",
5829 SPR_NOACCESS, SPR_NOACCESS,
5830 SPR_NOACCESS, SPR_NOACCESS,
5831 SPR_NOACCESS, &spr_write_tbu40,
5832 0x00000000);
5833 }
5834
5835 static void register_970_lpar_sprs(CPUPPCState *env)
5836 {
5837 #if !defined(CONFIG_USER_ONLY)
5838 /*
5839 * PPC970: HID4 covers things later controlled by the LPCR and
5840 * RMOR in later CPUs, but with a different encoding. We only
5841 * support the 970 in "Apple mode" which has all hypervisor
5842 * facilities disabled by strapping, so we can basically just
5843 * ignore it
5844 */
5845 spr_register(env, SPR_970_HID4, "HID4",
5846 SPR_NOACCESS, SPR_NOACCESS,
5847 &spr_read_generic, &spr_write_generic,
5848 0x00000000);
5849 #endif
5850 }
5851
5852 static void register_power5p_lpar_sprs(CPUPPCState *env)
5853 {
5854 #if !defined(CONFIG_USER_ONLY)
5855 /* Logical partitionning */
5856 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 SPR_NOACCESS, SPR_NOACCESS,
5859 &spr_read_generic, &spr_write_lpcr,
5860 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5861 spr_register_hv(env, SPR_HDEC, "HDEC",
5862 SPR_NOACCESS, SPR_NOACCESS,
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_hdecr, &spr_write_hdecr, 0);
5865 #endif
5866 }
5867
5868 static void register_book3s_ids_sprs(CPUPPCState *env)
5869 {
5870 /* FIXME: Will need to deal with thread vs core only SPRs */
5871
5872 /* Processor identification */
5873 spr_register_hv(env, SPR_PIR, "PIR",
5874 SPR_NOACCESS, SPR_NOACCESS,
5875 &spr_read_generic, SPR_NOACCESS,
5876 &spr_read_generic, NULL,
5877 0x00000000);
5878 spr_register_hv(env, SPR_HID0, "HID0",
5879 SPR_NOACCESS, SPR_NOACCESS,
5880 SPR_NOACCESS, SPR_NOACCESS,
5881 &spr_read_generic, &spr_write_generic,
5882 0x00000000);
5883 spr_register_hv(env, SPR_TSCR, "TSCR",
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 SPR_NOACCESS, SPR_NOACCESS,
5886 &spr_read_generic, &spr_write_generic,
5887 0x00000000);
5888 spr_register_hv(env, SPR_HMER, "HMER",
5889 SPR_NOACCESS, SPR_NOACCESS,
5890 SPR_NOACCESS, SPR_NOACCESS,
5891 &spr_read_generic, &spr_write_hmer,
5892 0x00000000);
5893 spr_register_hv(env, SPR_HMEER, "HMEER",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 SPR_NOACCESS, SPR_NOACCESS,
5896 &spr_read_generic, &spr_write_generic,
5897 0x00000000);
5898 spr_register_hv(env, SPR_TFMR, "TFMR",
5899 SPR_NOACCESS, SPR_NOACCESS,
5900 SPR_NOACCESS, SPR_NOACCESS,
5901 &spr_read_generic, &spr_write_generic,
5902 0x00000000);
5903 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5904 SPR_NOACCESS, SPR_NOACCESS,
5905 SPR_NOACCESS, SPR_NOACCESS,
5906 &spr_read_generic, &spr_write_lpidr,
5907 0x00000000);
5908 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 SPR_NOACCESS, SPR_NOACCESS,
5911 &spr_read_generic, &spr_write_generic,
5912 0x00000000);
5913 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5914 SPR_NOACCESS, SPR_NOACCESS,
5915 SPR_NOACCESS, SPR_NOACCESS,
5916 &spr_read_generic, &spr_write_generic,
5917 0x00000000);
5918 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 SPR_NOACCESS, SPR_NOACCESS,
5921 &spr_read_generic, &spr_write_generic,
5922 0x00000000);
5923 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5924 SPR_NOACCESS, SPR_NOACCESS,
5925 SPR_NOACCESS, SPR_NOACCESS,
5926 &spr_read_generic, &spr_write_generic,
5927 0x00000000);
5928 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5929 SPR_NOACCESS, SPR_NOACCESS,
5930 SPR_NOACCESS, SPR_NOACCESS,
5931 &spr_read_generic, &spr_write_generic,
5932 0x00000000);
5933 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5934 SPR_NOACCESS, SPR_NOACCESS,
5935 SPR_NOACCESS, SPR_NOACCESS,
5936 &spr_read_generic, &spr_write_generic,
5937 0x00000000);
5938 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5939 SPR_NOACCESS, SPR_NOACCESS,
5940 SPR_NOACCESS, SPR_NOACCESS,
5941 &spr_read_generic, &spr_write_generic,
5942 0x00000000);
5943 spr_register_hv(env, SPR_HDAR, "HDAR",
5944 SPR_NOACCESS, SPR_NOACCESS,
5945 SPR_NOACCESS, SPR_NOACCESS,
5946 &spr_read_generic, &spr_write_generic,
5947 0x00000000);
5948 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5949 SPR_NOACCESS, SPR_NOACCESS,
5950 SPR_NOACCESS, SPR_NOACCESS,
5951 &spr_read_generic, &spr_write_generic,
5952 0x00000000);
5953 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 SPR_NOACCESS, SPR_NOACCESS,
5956 &spr_read_generic, &spr_write_generic,
5957 0x00000000);
5958 }
5959
5960 static void register_rmor_sprs(CPUPPCState *env)
5961 {
5962 spr_register_hv(env, SPR_RMOR, "RMOR",
5963 SPR_NOACCESS, SPR_NOACCESS,
5964 SPR_NOACCESS, SPR_NOACCESS,
5965 &spr_read_generic, &spr_write_generic,
5966 0x00000000);
5967 }
5968
5969 static void register_power8_ids_sprs(CPUPPCState *env)
5970 {
5971 /* Thread identification */
5972 spr_register(env, SPR_TIR, "TIR",
5973 SPR_NOACCESS, SPR_NOACCESS,
5974 &spr_read_generic, SPR_NOACCESS,
5975 0x00000000);
5976 }
5977
5978 static void register_book3s_purr_sprs(CPUPPCState *env)
5979 {
5980 #if !defined(CONFIG_USER_ONLY)
5981 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5982 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5983 &spr_read_purr, SPR_NOACCESS,
5984 &spr_read_purr, SPR_NOACCESS,
5985 &spr_read_purr, &spr_write_purr,
5986 KVM_REG_PPC_PURR, 0x00000000);
5987 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5988 &spr_read_purr, SPR_NOACCESS,
5989 &spr_read_purr, SPR_NOACCESS,
5990 &spr_read_purr, &spr_write_purr,
5991 KVM_REG_PPC_SPURR, 0x00000000);
5992 #endif
5993 }
5994
5995 static void register_power6_dbg_sprs(CPUPPCState *env)
5996 {
5997 #if !defined(CONFIG_USER_ONLY)
5998 spr_register(env, SPR_CFAR, "SPR_CFAR",
5999 SPR_NOACCESS, SPR_NOACCESS,
6000 &spr_read_cfar, &spr_write_cfar,
6001 0x00000000);
6002 #endif
6003 }
6004
6005 static void register_power5p_common_sprs(CPUPPCState *env)
6006 {
6007 spr_register_kvm(env, SPR_PPR, "PPR",
6008 &spr_read_generic, &spr_write_generic,
6009 &spr_read_generic, &spr_write_generic,
6010 KVM_REG_PPC_PPR, 0x00000000);
6011 }
6012
6013 static void register_power6_common_sprs(CPUPPCState *env)
6014 {
6015 #if !defined(CONFIG_USER_ONLY)
6016 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6017 SPR_NOACCESS, SPR_NOACCESS,
6018 &spr_read_generic, &spr_write_generic,
6019 KVM_REG_PPC_DSCR, 0x00000000);
6020 #endif
6021 /*
6022 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
6023 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
6024 */
6025 spr_register_hv(env, SPR_PCR, "PCR",
6026 SPR_NOACCESS, SPR_NOACCESS,
6027 SPR_NOACCESS, SPR_NOACCESS,
6028 &spr_read_generic, &spr_write_pcr,
6029 0x00000000);
6030 }
6031
6032 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
6033 {
6034 spr_register_kvm(env, SPR_TAR, "TAR",
6035 &spr_read_tar, &spr_write_tar,
6036 &spr_read_generic, &spr_write_generic,
6037 KVM_REG_PPC_TAR, 0x00000000);
6038 }
6039
6040 static void register_power8_tm_sprs(CPUPPCState *env)
6041 {
6042 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
6043 &spr_read_tm, &spr_write_tm,
6044 &spr_read_tm, &spr_write_tm,
6045 KVM_REG_PPC_TFHAR, 0x00000000);
6046 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
6047 &spr_read_tm, &spr_write_tm,
6048 &spr_read_tm, &spr_write_tm,
6049 KVM_REG_PPC_TFIAR, 0x00000000);
6050 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
6051 &spr_read_tm, &spr_write_tm,
6052 &spr_read_tm, &spr_write_tm,
6053 KVM_REG_PPC_TEXASR, 0x00000000);
6054 spr_register(env, SPR_TEXASRU, "TEXASRU",
6055 &spr_read_tm_upper32, &spr_write_tm_upper32,
6056 &spr_read_tm_upper32, &spr_write_tm_upper32,
6057 0x00000000);
6058 }
6059
6060 static void register_power8_ebb_sprs(CPUPPCState *env)
6061 {
6062 spr_register(env, SPR_BESCRS, "BESCRS",
6063 &spr_read_ebb, &spr_write_ebb,
6064 &spr_read_generic, &spr_write_generic,
6065 0x00000000);
6066 spr_register(env, SPR_BESCRSU, "BESCRSU",
6067 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6068 &spr_read_prev_upper32, &spr_write_prev_upper32,
6069 0x00000000);
6070 spr_register(env, SPR_BESCRR, "BESCRR",
6071 &spr_read_ebb, &spr_write_ebb,
6072 &spr_read_generic, &spr_write_generic,
6073 0x00000000);
6074 spr_register(env, SPR_BESCRRU, "BESCRRU",
6075 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6076 &spr_read_prev_upper32, &spr_write_prev_upper32,
6077 0x00000000);
6078 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
6079 &spr_read_ebb, &spr_write_ebb,
6080 &spr_read_generic, &spr_write_generic,
6081 KVM_REG_PPC_EBBHR, 0x00000000);
6082 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
6083 &spr_read_ebb, &spr_write_ebb,
6084 &spr_read_generic, &spr_write_generic,
6085 KVM_REG_PPC_EBBRR, 0x00000000);
6086 spr_register_kvm(env, SPR_BESCR, "BESCR",
6087 &spr_read_ebb, &spr_write_ebb,
6088 &spr_read_generic, &spr_write_generic,
6089 KVM_REG_PPC_BESCR, 0x00000000);
6090 }
6091
6092 /* Virtual Time Base */
6093 static void register_vtb_sprs(CPUPPCState *env)
6094 {
6095 spr_register_kvm_hv(env, SPR_VTB, "VTB",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 &spr_read_vtb, SPR_NOACCESS,
6098 &spr_read_vtb, &spr_write_vtb,
6099 KVM_REG_PPC_VTB, 0x00000000);
6100 }
6101
6102 static void register_power8_fscr_sprs(CPUPPCState *env)
6103 {
6104 #if defined(CONFIG_USER_ONLY)
6105 target_ulong initval = 1ULL << FSCR_TAR;
6106 #else
6107 target_ulong initval = 0;
6108 #endif
6109 spr_register_kvm(env, SPR_FSCR, "FSCR",
6110 SPR_NOACCESS, SPR_NOACCESS,
6111 &spr_read_generic, &spr_write_generic,
6112 KVM_REG_PPC_FSCR, initval);
6113 }
6114
6115 static void register_power8_pspb_sprs(CPUPPCState *env)
6116 {
6117 spr_register_kvm(env, SPR_PSPB, "PSPB",
6118 SPR_NOACCESS, SPR_NOACCESS,
6119 &spr_read_generic, &spr_write_generic32,
6120 KVM_REG_PPC_PSPB, 0);
6121 }
6122
6123 static void register_power8_dpdes_sprs(CPUPPCState *env)
6124 {
6125 #if !defined(CONFIG_USER_ONLY)
6126 /* Directed Privileged Door-bell Exception State, used for IPI */
6127 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
6128 SPR_NOACCESS, SPR_NOACCESS,
6129 &spr_read_dpdes, SPR_NOACCESS,
6130 &spr_read_dpdes, &spr_write_dpdes,
6131 KVM_REG_PPC_DPDES, 0x00000000);
6132 #endif
6133 }
6134
6135 static void register_power8_ic_sprs(CPUPPCState *env)
6136 {
6137 #if !defined(CONFIG_USER_ONLY)
6138 spr_register_hv(env, SPR_IC, "IC",
6139 SPR_NOACCESS, SPR_NOACCESS,
6140 &spr_read_generic, SPR_NOACCESS,
6141 &spr_read_generic, &spr_write_generic,
6142 0);
6143 #endif
6144 }
6145
6146 static void register_power8_book4_sprs(CPUPPCState *env)
6147 {
6148 /* Add a number of P8 book4 registers */
6149 #if !defined(CONFIG_USER_ONLY)
6150 spr_register_kvm(env, SPR_ACOP, "ACOP",
6151 SPR_NOACCESS, SPR_NOACCESS,
6152 &spr_read_generic, &spr_write_generic,
6153 KVM_REG_PPC_ACOP, 0);
6154 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6155 SPR_NOACCESS, SPR_NOACCESS,
6156 &spr_read_generic, &spr_write_pidr,
6157 KVM_REG_PPC_PID, 0);
6158 spr_register_kvm(env, SPR_WORT, "WORT",
6159 SPR_NOACCESS, SPR_NOACCESS,
6160 &spr_read_generic, &spr_write_generic,
6161 KVM_REG_PPC_WORT, 0);
6162 #endif
6163 }
6164
6165 static void register_power7_book4_sprs(CPUPPCState *env)
6166 {
6167 /* Add a number of P7 book4 registers */
6168 #if !defined(CONFIG_USER_ONLY)
6169 spr_register_kvm(env, SPR_ACOP, "ACOP",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, &spr_write_generic,
6172 KVM_REG_PPC_ACOP, 0);
6173 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6174 SPR_NOACCESS, SPR_NOACCESS,
6175 &spr_read_generic, &spr_write_generic,
6176 KVM_REG_PPC_PID, 0);
6177 #endif
6178 }
6179
6180 static void register_power8_rpr_sprs(CPUPPCState *env)
6181 {
6182 #if !defined(CONFIG_USER_ONLY)
6183 spr_register_hv(env, SPR_RPR, "RPR",
6184 SPR_NOACCESS, SPR_NOACCESS,
6185 SPR_NOACCESS, SPR_NOACCESS,
6186 &spr_read_generic, &spr_write_generic,
6187 0x00000103070F1F3F);
6188 #endif
6189 }
6190
6191 static void register_power9_mmu_sprs(CPUPPCState *env)
6192 {
6193 #if !defined(CONFIG_USER_ONLY)
6194 /* Partition Table Control */
6195 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
6196 SPR_NOACCESS, SPR_NOACCESS,
6197 SPR_NOACCESS, SPR_NOACCESS,
6198 &spr_read_generic, &spr_write_ptcr,
6199 KVM_REG_PPC_PTCR, 0x00000000);
6200 /* Address Segment Descriptor Register */
6201 spr_register_hv(env, SPR_ASDR, "ASDR",
6202 SPR_NOACCESS, SPR_NOACCESS,
6203 SPR_NOACCESS, SPR_NOACCESS,
6204 &spr_read_generic, &spr_write_generic,
6205 0x0000000000000000);
6206 #endif
6207 }
6208
6209 /*
6210 * Initialize PMU counter overflow timers for Power8 and
6211 * newer Power chips when using TCG.
6212 */
6213 static void init_tcg_pmu_power8(CPUPPCState *env)
6214 {
6215 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
6216 /* Init PMU overflow timers */
6217 if (!kvm_enabled()) {
6218 cpu_ppc_pmu_init(env);
6219 }
6220 #endif
6221 }
6222
6223 static void init_proc_book3s_common(CPUPPCState *env)
6224 {
6225 register_ne_601_sprs(env);
6226 register_usprg3_sprs(env);
6227 register_book3s_altivec_sprs(env);
6228 register_book3s_pmu_sup_sprs(env);
6229 register_book3s_pmu_user_sprs(env);
6230 register_book3s_ctrl_sprs(env);
6231 /*
6232 * Can't find information on what this should be on reset. This
6233 * value is the one used by 74xx processors.
6234 */
6235 vscr_init(env, 0x00010000);
6236 }
6237
6238 static void init_proc_970(CPUPPCState *env)
6239 {
6240 /* Common Registers */
6241 init_proc_book3s_common(env);
6242 register_sdr1_sprs(env);
6243 register_book3s_dbg_sprs(env);
6244
6245 /* 970 Specific Registers */
6246 register_970_hid_sprs(env);
6247 register_970_hior_sprs(env);
6248 register_low_BATs(env);
6249 register_970_pmu_sup_sprs(env);
6250 register_970_pmu_user_sprs(env);
6251 register_970_lpar_sprs(env);
6252 register_970_dbg_sprs(env);
6253
6254 /* env variables */
6255 env->dcache_line_size = 128;
6256 env->icache_line_size = 128;
6257
6258 /* Allocate hardware IRQ controller */
6259 init_excp_970(env);
6260 ppc970_irq_init(env_archcpu(env));
6261 }
6262
6263 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6264 {
6265 DeviceClass *dc = DEVICE_CLASS(oc);
6266 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6267
6268 dc->desc = "PowerPC 970";
6269 pcc->init_proc = init_proc_970;
6270 pcc->check_pow = check_pow_970;
6271 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6272 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6273 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6274 PPC_FLOAT_STFIWX |
6275 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6276 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6277 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6278 PPC_64B | PPC_ALTIVEC |
6279 PPC_SEGMENT_64B | PPC_SLBI;
6280 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6281 pcc->msr_mask = (1ull << MSR_SF) |
6282 (1ull << MSR_VR) |
6283 (1ull << MSR_POW) |
6284 (1ull << MSR_EE) |
6285 (1ull << MSR_PR) |
6286 (1ull << MSR_FP) |
6287 (1ull << MSR_ME) |
6288 (1ull << MSR_FE0) |
6289 (1ull << MSR_SE) |
6290 (1ull << MSR_DE) |
6291 (1ull << MSR_FE1) |
6292 (1ull << MSR_IR) |
6293 (1ull << MSR_DR) |
6294 (1ull << MSR_PMM) |
6295 (1ull << MSR_RI);
6296 pcc->mmu_model = POWERPC_MMU_64B;
6297 #if defined(CONFIG_SOFTMMU)
6298 pcc->hash64_opts = &ppc_hash64_opts_basic;
6299 #endif
6300 pcc->excp_model = POWERPC_EXCP_970;
6301 pcc->bus_model = PPC_FLAGS_INPUT_970;
6302 pcc->bfd_mach = bfd_mach_ppc64;
6303 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6304 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6305 POWERPC_FLAG_BUS_CLK;
6306 pcc->l1_dcache_size = 0x8000;
6307 pcc->l1_icache_size = 0x10000;
6308 }
6309
6310 static void init_proc_power5plus(CPUPPCState *env)
6311 {
6312 /* Common Registers */
6313 init_proc_book3s_common(env);
6314 register_sdr1_sprs(env);
6315 register_book3s_dbg_sprs(env);
6316
6317 /* POWER5+ Specific Registers */
6318 register_970_hid_sprs(env);
6319 register_970_hior_sprs(env);
6320 register_low_BATs(env);
6321 register_970_pmu_sup_sprs(env);
6322 register_970_pmu_user_sprs(env);
6323 register_power5p_common_sprs(env);
6324 register_power5p_lpar_sprs(env);
6325 register_power5p_ear_sprs(env);
6326 register_power5p_tb_sprs(env);
6327
6328 /* env variables */
6329 env->dcache_line_size = 128;
6330 env->icache_line_size = 128;
6331
6332 /* Allocate hardware IRQ controller */
6333 init_excp_970(env);
6334 ppc970_irq_init(env_archcpu(env));
6335 }
6336
6337 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6338 {
6339 DeviceClass *dc = DEVICE_CLASS(oc);
6340 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6341
6342 dc->fw_name = "PowerPC,POWER5";
6343 dc->desc = "POWER5+";
6344 pcc->init_proc = init_proc_power5plus;
6345 pcc->check_pow = check_pow_970;
6346 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6347 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6348 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6349 PPC_FLOAT_STFIWX |
6350 PPC_FLOAT_EXT |
6351 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6352 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6353 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6354 PPC_64B |
6355 PPC_POPCNTB |
6356 PPC_SEGMENT_64B | PPC_SLBI;
6357 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6358 pcc->msr_mask = (1ull << MSR_SF) |
6359 (1ull << MSR_VR) |
6360 (1ull << MSR_POW) |
6361 (1ull << MSR_EE) |
6362 (1ull << MSR_PR) |
6363 (1ull << MSR_FP) |
6364 (1ull << MSR_ME) |
6365 (1ull << MSR_FE0) |
6366 (1ull << MSR_SE) |
6367 (1ull << MSR_DE) |
6368 (1ull << MSR_FE1) |
6369 (1ull << MSR_IR) |
6370 (1ull << MSR_DR) |
6371 (1ull << MSR_PMM) |
6372 (1ull << MSR_RI);
6373 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6374 LPCR_RMI | LPCR_HDICE;
6375 pcc->mmu_model = POWERPC_MMU_2_03;
6376 #if defined(CONFIG_SOFTMMU)
6377 pcc->hash64_opts = &ppc_hash64_opts_basic;
6378 pcc->lrg_decr_bits = 32;
6379 #endif
6380 pcc->excp_model = POWERPC_EXCP_970;
6381 pcc->bus_model = PPC_FLAGS_INPUT_970;
6382 pcc->bfd_mach = bfd_mach_ppc64;
6383 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6384 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6385 POWERPC_FLAG_BUS_CLK;
6386 pcc->l1_dcache_size = 0x8000;
6387 pcc->l1_icache_size = 0x10000;
6388 }
6389
6390 static void init_proc_POWER7(CPUPPCState *env)
6391 {
6392 /* Common Registers */
6393 init_proc_book3s_common(env);
6394 register_sdr1_sprs(env);
6395 register_book3s_dbg_sprs(env);
6396
6397 /* POWER7 Specific Registers */
6398 register_book3s_ids_sprs(env);
6399 register_rmor_sprs(env);
6400 register_amr_sprs(env);
6401 register_book3s_purr_sprs(env);
6402 register_power5p_common_sprs(env);
6403 register_power5p_lpar_sprs(env);
6404 register_power5p_ear_sprs(env);
6405 register_power5p_tb_sprs(env);
6406 register_power6_common_sprs(env);
6407 register_power6_dbg_sprs(env);
6408 register_power7_book4_sprs(env);
6409
6410 /* env variables */
6411 env->dcache_line_size = 128;
6412 env->icache_line_size = 128;
6413
6414 /* Allocate hardware IRQ controller */
6415 init_excp_POWER7(env);
6416 ppcPOWER7_irq_init(env_archcpu(env));
6417 }
6418
6419 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
6420 {
6421 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
6422 return true;
6423 }
6424 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
6425 return true;
6426 }
6427 return false;
6428 }
6429
6430 static bool cpu_has_work_POWER7(CPUState *cs)
6431 {
6432 PowerPCCPU *cpu = POWERPC_CPU(cs);
6433 CPUPPCState *env = &cpu->env;
6434
6435 if (cs->halted) {
6436 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6437 return false;
6438 }
6439 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6440 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
6441 return true;
6442 }
6443 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6444 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
6445 return true;
6446 }
6447 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6448 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6449 return true;
6450 }
6451 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6452 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6453 return true;
6454 }
6455 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6456 return true;
6457 }
6458 return false;
6459 } else {
6460 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6461 }
6462 }
6463
6464 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6465 {
6466 DeviceClass *dc = DEVICE_CLASS(oc);
6467 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6468 CPUClass *cc = CPU_CLASS(oc);
6469
6470 dc->fw_name = "PowerPC,POWER7";
6471 dc->desc = "POWER7";
6472 pcc->pvr_match = ppc_pvr_match_power7;
6473 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6474 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6475 pcc->init_proc = init_proc_POWER7;
6476 pcc->check_pow = check_pow_nocheck;
6477 cc->has_work = cpu_has_work_POWER7;
6478 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6479 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6480 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6481 PPC_FLOAT_FRSQRTES |
6482 PPC_FLOAT_STFIWX |
6483 PPC_FLOAT_EXT |
6484 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6485 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6486 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6487 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6488 PPC_SEGMENT_64B | PPC_SLBI |
6489 PPC_POPCNTB | PPC_POPCNTWD |
6490 PPC_CILDST;
6491 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6492 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6493 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6494 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6495 PPC2_PM_ISA206;
6496 pcc->msr_mask = (1ull << MSR_SF) |
6497 (1ull << MSR_VR) |
6498 (1ull << MSR_VSX) |
6499 (1ull << MSR_EE) |
6500 (1ull << MSR_PR) |
6501 (1ull << MSR_FP) |
6502 (1ull << MSR_ME) |
6503 (1ull << MSR_FE0) |
6504 (1ull << MSR_SE) |
6505 (1ull << MSR_DE) |
6506 (1ull << MSR_FE1) |
6507 (1ull << MSR_IR) |
6508 (1ull << MSR_DR) |
6509 (1ull << MSR_PMM) |
6510 (1ull << MSR_RI) |
6511 (1ull << MSR_LE);
6512 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6513 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6514 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6515 LPCR_MER | LPCR_TC |
6516 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6517 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6518 pcc->mmu_model = POWERPC_MMU_2_06;
6519 #if defined(CONFIG_SOFTMMU)
6520 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6521 pcc->lrg_decr_bits = 32;
6522 #endif
6523 pcc->excp_model = POWERPC_EXCP_POWER7;
6524 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6525 pcc->bfd_mach = bfd_mach_ppc64;
6526 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6527 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6528 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6529 POWERPC_FLAG_VSX;
6530 pcc->l1_dcache_size = 0x8000;
6531 pcc->l1_icache_size = 0x8000;
6532 }
6533
6534 static void init_proc_POWER8(CPUPPCState *env)
6535 {
6536 /* Common Registers */
6537 init_proc_book3s_common(env);
6538 register_sdr1_sprs(env);
6539 register_book3s_207_dbg_sprs(env);
6540
6541 /* Common TCG PMU */
6542 init_tcg_pmu_power8(env);
6543
6544 /* POWER8 Specific Registers */
6545 register_book3s_ids_sprs(env);
6546 register_rmor_sprs(env);
6547 register_amr_sprs(env);
6548 register_iamr_sprs(env);
6549 register_book3s_purr_sprs(env);
6550 register_power5p_common_sprs(env);
6551 register_power5p_lpar_sprs(env);
6552 register_power5p_ear_sprs(env);
6553 register_power5p_tb_sprs(env);
6554 register_power6_common_sprs(env);
6555 register_power6_dbg_sprs(env);
6556 register_power8_tce_address_control_sprs(env);
6557 register_power8_ids_sprs(env);
6558 register_power8_ebb_sprs(env);
6559 register_power8_fscr_sprs(env);
6560 register_power8_pmu_sup_sprs(env);
6561 register_power8_pmu_user_sprs(env);
6562 register_power8_tm_sprs(env);
6563 register_power8_pspb_sprs(env);
6564 register_power8_dpdes_sprs(env);
6565 register_vtb_sprs(env);
6566 register_power8_ic_sprs(env);
6567 register_power8_book4_sprs(env);
6568 register_power8_rpr_sprs(env);
6569
6570 /* env variables */
6571 env->dcache_line_size = 128;
6572 env->icache_line_size = 128;
6573
6574 /* Allocate hardware IRQ controller */
6575 init_excp_POWER8(env);
6576 ppcPOWER7_irq_init(env_archcpu(env));
6577 }
6578
6579 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
6580 {
6581 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
6582 return true;
6583 }
6584 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
6585 return true;
6586 }
6587 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
6588 return true;
6589 }
6590 return false;
6591 }
6592
6593 static bool cpu_has_work_POWER8(CPUState *cs)
6594 {
6595 PowerPCCPU *cpu = POWERPC_CPU(cs);
6596 CPUPPCState *env = &cpu->env;
6597
6598 if (cs->halted) {
6599 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6600 return false;
6601 }
6602 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6603 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6604 return true;
6605 }
6606 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6607 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6608 return true;
6609 }
6610 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6611 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6612 return true;
6613 }
6614 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6615 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6616 return true;
6617 }
6618 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6619 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6620 return true;
6621 }
6622 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6623 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6624 return true;
6625 }
6626 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6627 return true;
6628 }
6629 return false;
6630 } else {
6631 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6632 }
6633 }
6634
6635 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6636 {
6637 DeviceClass *dc = DEVICE_CLASS(oc);
6638 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6639 CPUClass *cc = CPU_CLASS(oc);
6640
6641 dc->fw_name = "PowerPC,POWER8";
6642 dc->desc = "POWER8";
6643 pcc->pvr_match = ppc_pvr_match_power8;
6644 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6645 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6646 pcc->init_proc = init_proc_POWER8;
6647 pcc->check_pow = check_pow_nocheck;
6648 cc->has_work = cpu_has_work_POWER8;
6649 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6650 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6651 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6652 PPC_FLOAT_FRSQRTES |
6653 PPC_FLOAT_STFIWX |
6654 PPC_FLOAT_EXT |
6655 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6656 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6657 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6658 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6659 PPC_SEGMENT_64B | PPC_SLBI |
6660 PPC_POPCNTB | PPC_POPCNTWD |
6661 PPC_CILDST;
6662 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6663 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6664 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6665 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6666 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6667 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6668 PPC2_TM | PPC2_PM_ISA206;
6669 pcc->msr_mask = (1ull << MSR_SF) |
6670 (1ull << MSR_HV) |
6671 (1ull << MSR_TM) |
6672 (1ull << MSR_VR) |
6673 (1ull << MSR_VSX) |
6674 (1ull << MSR_EE) |
6675 (1ull << MSR_PR) |
6676 (1ull << MSR_FP) |
6677 (1ull << MSR_ME) |
6678 (1ull << MSR_FE0) |
6679 (1ull << MSR_SE) |
6680 (1ull << MSR_DE) |
6681 (1ull << MSR_FE1) |
6682 (1ull << MSR_IR) |
6683 (1ull << MSR_DR) |
6684 (1ull << MSR_PMM) |
6685 (1ull << MSR_RI) |
6686 (1ull << MSR_TS0) |
6687 (1ull << MSR_TS1) |
6688 (1ull << MSR_LE);
6689 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6690 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6691 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6692 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6693 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6694 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6695 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6696 pcc->mmu_model = POWERPC_MMU_2_07;
6697 #if defined(CONFIG_SOFTMMU)
6698 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6699 pcc->lrg_decr_bits = 32;
6700 pcc->n_host_threads = 8;
6701 #endif
6702 pcc->excp_model = POWERPC_EXCP_POWER8;
6703 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6704 pcc->bfd_mach = bfd_mach_ppc64;
6705 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6706 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6707 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6708 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6709 pcc->l1_dcache_size = 0x8000;
6710 pcc->l1_icache_size = 0x8000;
6711 }
6712
6713 #ifdef CONFIG_SOFTMMU
6714 /*
6715 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6716 * Encoded as array of int_32s in the form:
6717 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6718 * x -> AP encoding
6719 * y -> radix mode supported page size (encoded as a shift)
6720 */
6721 static struct ppc_radix_page_info POWER9_radix_page_info = {
6722 .count = 4,
6723 .entries = {
6724 0x0000000c, /* 4K - enc: 0x0 */
6725 0xa0000010, /* 64K - enc: 0x5 */
6726 0x20000015, /* 2M - enc: 0x1 */
6727 0x4000001e /* 1G - enc: 0x2 */
6728 }
6729 };
6730 #endif /* CONFIG_SOFTMMU */
6731
6732 static void init_proc_POWER9(CPUPPCState *env)
6733 {
6734 /* Common Registers */
6735 init_proc_book3s_common(env);
6736 register_book3s_207_dbg_sprs(env);
6737
6738 /* Common TCG PMU */
6739 init_tcg_pmu_power8(env);
6740
6741 /* POWER8 Specific Registers */
6742 register_book3s_ids_sprs(env);
6743 register_amr_sprs(env);
6744 register_iamr_sprs(env);
6745 register_book3s_purr_sprs(env);
6746 register_power5p_common_sprs(env);
6747 register_power5p_lpar_sprs(env);
6748 register_power5p_ear_sprs(env);
6749 register_power5p_tb_sprs(env);
6750 register_power6_common_sprs(env);
6751 register_power6_dbg_sprs(env);
6752 register_power8_tce_address_control_sprs(env);
6753 register_power8_ids_sprs(env);
6754 register_power8_ebb_sprs(env);
6755 register_power8_fscr_sprs(env);
6756 register_power8_pmu_sup_sprs(env);
6757 register_power8_pmu_user_sprs(env);
6758 register_power8_tm_sprs(env);
6759 register_power8_pspb_sprs(env);
6760 register_power8_dpdes_sprs(env);
6761 register_vtb_sprs(env);
6762 register_power8_ic_sprs(env);
6763 register_power8_book4_sprs(env);
6764 register_power8_rpr_sprs(env);
6765 register_power9_mmu_sprs(env);
6766
6767 /* POWER9 Specific registers */
6768 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6769 spr_read_generic, spr_write_generic,
6770 KVM_REG_PPC_TIDR, 0);
6771
6772 /* FIXME: Filter fields properly based on privilege level */
6773 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6774 spr_read_generic, spr_write_generic,
6775 KVM_REG_PPC_PSSCR, 0);
6776
6777 /* env variables */
6778 env->dcache_line_size = 128;
6779 env->icache_line_size = 128;
6780
6781 /* Allocate hardware IRQ controller */
6782 init_excp_POWER9(env);
6783 ppcPOWER9_irq_init(env_archcpu(env));
6784 }
6785
6786 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
6787 {
6788 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
6789 return true;
6790 }
6791 return false;
6792 }
6793
6794 static bool cpu_has_work_POWER9(CPUState *cs)
6795 {
6796 PowerPCCPU *cpu = POWERPC_CPU(cs);
6797 CPUPPCState *env = &cpu->env;
6798
6799 if (cs->halted) {
6800 uint64_t psscr = env->spr[SPR_PSSCR];
6801
6802 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6803 return false;
6804 }
6805
6806 /* If EC is clear, just return true on any pending interrupt */
6807 if (!(psscr & PSSCR_EC)) {
6808 return true;
6809 }
6810 /* External Exception */
6811 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6812 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6813 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6814 if (heic == 0 || !msr_hv || msr_pr) {
6815 return true;
6816 }
6817 }
6818 /* Decrementer Exception */
6819 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6820 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6821 return true;
6822 }
6823 /* Machine Check or Hypervisor Maintenance Exception */
6824 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6825 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6826 return true;
6827 }
6828 /* Privileged Doorbell Exception */
6829 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6830 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6831 return true;
6832 }
6833 /* Hypervisor Doorbell Exception */
6834 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6835 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6836 return true;
6837 }
6838 /* Hypervisor virtualization exception */
6839 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6840 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6841 return true;
6842 }
6843 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6844 return true;
6845 }
6846 return false;
6847 } else {
6848 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6849 }
6850 }
6851
6852 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6853 {
6854 DeviceClass *dc = DEVICE_CLASS(oc);
6855 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6856 CPUClass *cc = CPU_CLASS(oc);
6857
6858 dc->fw_name = "PowerPC,POWER9";
6859 dc->desc = "POWER9";
6860 pcc->pvr_match = ppc_pvr_match_power9;
6861 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6862 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6863 PCR_COMPAT_2_05;
6864 pcc->init_proc = init_proc_POWER9;
6865 pcc->check_pow = check_pow_nocheck;
6866 cc->has_work = cpu_has_work_POWER9;
6867 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6868 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6869 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6870 PPC_FLOAT_FRSQRTES |
6871 PPC_FLOAT_STFIWX |
6872 PPC_FLOAT_EXT |
6873 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6874 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6875 PPC_MEM_TLBSYNC |
6876 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6877 PPC_SEGMENT_64B | PPC_SLBI |
6878 PPC_POPCNTB | PPC_POPCNTWD |
6879 PPC_CILDST;
6880 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6881 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6882 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6883 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6884 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6885 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6886 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
6887 pcc->msr_mask = (1ull << MSR_SF) |
6888 (1ull << MSR_HV) |
6889 (1ull << MSR_TM) |
6890 (1ull << MSR_VR) |
6891 (1ull << MSR_VSX) |
6892 (1ull << MSR_EE) |
6893 (1ull << MSR_PR) |
6894 (1ull << MSR_FP) |
6895 (1ull << MSR_ME) |
6896 (1ull << MSR_FE0) |
6897 (1ull << MSR_SE) |
6898 (1ull << MSR_DE) |
6899 (1ull << MSR_FE1) |
6900 (1ull << MSR_IR) |
6901 (1ull << MSR_DR) |
6902 (1ull << MSR_PMM) |
6903 (1ull << MSR_RI) |
6904 (1ull << MSR_LE);
6905 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6906 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6907 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6908 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6909 LPCR_DEE | LPCR_OEE))
6910 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6911 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6912 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6913 pcc->mmu_model = POWERPC_MMU_3_00;
6914 #if defined(CONFIG_SOFTMMU)
6915 /* segment page size remain the same */
6916 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6917 pcc->radix_page_info = &POWER9_radix_page_info;
6918 pcc->lrg_decr_bits = 56;
6919 pcc->n_host_threads = 4;
6920 #endif
6921 pcc->excp_model = POWERPC_EXCP_POWER9;
6922 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6923 pcc->bfd_mach = bfd_mach_ppc64;
6924 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6925 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6926 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6927 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6928 pcc->l1_dcache_size = 0x8000;
6929 pcc->l1_icache_size = 0x8000;
6930 }
6931
6932 #ifdef CONFIG_SOFTMMU
6933 /*
6934 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6935 * Encoded as array of int_32s in the form:
6936 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6937 * x -> AP encoding
6938 * y -> radix mode supported page size (encoded as a shift)
6939 */
6940 static struct ppc_radix_page_info POWER10_radix_page_info = {
6941 .count = 4,
6942 .entries = {
6943 0x0000000c, /* 4K - enc: 0x0 */
6944 0xa0000010, /* 64K - enc: 0x5 */
6945 0x20000015, /* 2M - enc: 0x1 */
6946 0x4000001e /* 1G - enc: 0x2 */
6947 }
6948 };
6949 #endif /* CONFIG_SOFTMMU */
6950
6951 static void init_proc_POWER10(CPUPPCState *env)
6952 {
6953 /* Common Registers */
6954 init_proc_book3s_common(env);
6955 register_book3s_207_dbg_sprs(env);
6956
6957 /* Common TCG PMU */
6958 init_tcg_pmu_power8(env);
6959
6960 /* POWER8 Specific Registers */
6961 register_book3s_ids_sprs(env);
6962 register_amr_sprs(env);
6963 register_iamr_sprs(env);
6964 register_book3s_purr_sprs(env);
6965 register_power5p_common_sprs(env);
6966 register_power5p_lpar_sprs(env);
6967 register_power5p_ear_sprs(env);
6968 register_power6_common_sprs(env);
6969 register_power6_dbg_sprs(env);
6970 register_power8_tce_address_control_sprs(env);
6971 register_power8_ids_sprs(env);
6972 register_power8_ebb_sprs(env);
6973 register_power8_fscr_sprs(env);
6974 register_power8_pmu_sup_sprs(env);
6975 register_power8_pmu_user_sprs(env);
6976 register_power8_tm_sprs(env);
6977 register_power8_pspb_sprs(env);
6978 register_vtb_sprs(env);
6979 register_power8_ic_sprs(env);
6980 register_power8_book4_sprs(env);
6981 register_power8_rpr_sprs(env);
6982 register_power9_mmu_sprs(env);
6983
6984 /* FIXME: Filter fields properly based on privilege level */
6985 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6986 spr_read_generic, spr_write_generic,
6987 KVM_REG_PPC_PSSCR, 0);
6988
6989 /* env variables */
6990 env->dcache_line_size = 128;
6991 env->icache_line_size = 128;
6992
6993 /* Allocate hardware IRQ controller */
6994 init_excp_POWER10(env);
6995 ppcPOWER9_irq_init(env_archcpu(env));
6996 }
6997
6998 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
6999 {
7000 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
7001 return true;
7002 }
7003 return false;
7004 }
7005
7006 static bool cpu_has_work_POWER10(CPUState *cs)
7007 {
7008 PowerPCCPU *cpu = POWERPC_CPU(cs);
7009 CPUPPCState *env = &cpu->env;
7010
7011 if (cs->halted) {
7012 uint64_t psscr = env->spr[SPR_PSSCR];
7013
7014 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7015 return false;
7016 }
7017
7018 /* If EC is clear, just return true on any pending interrupt */
7019 if (!(psscr & PSSCR_EC)) {
7020 return true;
7021 }
7022 /* External Exception */
7023 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7024 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7025 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7026 if (heic == 0 || !msr_hv || msr_pr) {
7027 return true;
7028 }
7029 }
7030 /* Decrementer Exception */
7031 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7032 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7033 return true;
7034 }
7035 /* Machine Check or Hypervisor Maintenance Exception */
7036 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7037 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7038 return true;
7039 }
7040 /* Privileged Doorbell Exception */
7041 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7042 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7043 return true;
7044 }
7045 /* Hypervisor Doorbell Exception */
7046 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7047 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7048 return true;
7049 }
7050 /* Hypervisor virtualization exception */
7051 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7052 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7053 return true;
7054 }
7055 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7056 return true;
7057 }
7058 return false;
7059 } else {
7060 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7061 }
7062 }
7063
7064 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
7065 {
7066 DeviceClass *dc = DEVICE_CLASS(oc);
7067 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7068 CPUClass *cc = CPU_CLASS(oc);
7069
7070 dc->fw_name = "PowerPC,POWER10";
7071 dc->desc = "POWER10";
7072 pcc->pvr_match = ppc_pvr_match_power10;
7073 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
7074 PCR_COMPAT_3_00;
7075 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
7076 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7077 pcc->init_proc = init_proc_POWER10;
7078 pcc->check_pow = check_pow_nocheck;
7079 cc->has_work = cpu_has_work_POWER10;
7080 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7081 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7082 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7083 PPC_FLOAT_FRSQRTES |
7084 PPC_FLOAT_STFIWX |
7085 PPC_FLOAT_EXT |
7086 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7087 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7088 PPC_MEM_TLBSYNC |
7089 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7090 PPC_SEGMENT_64B | PPC_SLBI |
7091 PPC_POPCNTB | PPC_POPCNTWD |
7092 PPC_CILDST;
7093 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7094 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7095 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7096 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7097 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7098 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7099 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
7100 pcc->msr_mask = (1ull << MSR_SF) |
7101 (1ull << MSR_HV) |
7102 (1ull << MSR_TM) |
7103 (1ull << MSR_VR) |
7104 (1ull << MSR_VSX) |
7105 (1ull << MSR_EE) |
7106 (1ull << MSR_PR) |
7107 (1ull << MSR_FP) |
7108 (1ull << MSR_ME) |
7109 (1ull << MSR_FE0) |
7110 (1ull << MSR_SE) |
7111 (1ull << MSR_DE) |
7112 (1ull << MSR_FE1) |
7113 (1ull << MSR_IR) |
7114 (1ull << MSR_DR) |
7115 (1ull << MSR_PMM) |
7116 (1ull << MSR_RI) |
7117 (1ull << MSR_LE);
7118 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7119 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7120 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7121 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7122 LPCR_DEE | LPCR_OEE))
7123 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7124 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7125 /* DD2 adds an extra HAIL bit */
7126 pcc->lpcr_mask |= LPCR_HAIL;
7127
7128 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7129 pcc->mmu_model = POWERPC_MMU_3_00;
7130 #if defined(CONFIG_SOFTMMU)
7131 /* segment page size remain the same */
7132 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7133 pcc->radix_page_info = &POWER10_radix_page_info;
7134 pcc->lrg_decr_bits = 56;
7135 #endif
7136 pcc->excp_model = POWERPC_EXCP_POWER10;
7137 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7138 pcc->bfd_mach = bfd_mach_ppc64;
7139 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7140 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7141 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7142 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7143 pcc->l1_dcache_size = 0x8000;
7144 pcc->l1_icache_size = 0x8000;
7145 }
7146
7147 #if !defined(CONFIG_USER_ONLY)
7148 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
7149 {
7150 CPUPPCState *env = &cpu->env;
7151
7152 cpu->vhyp = vhyp;
7153
7154 /*
7155 * With a virtual hypervisor mode we never allow the CPU to go
7156 * hypervisor mode itself
7157 */
7158 env->msr_mask &= ~MSR_HVB;
7159 }
7160
7161 #endif /* !defined(CONFIG_USER_ONLY) */
7162
7163 #endif /* defined(TARGET_PPC64) */
7164
7165 /*****************************************************************************/
7166 /* Generic CPU instantiation routine */
7167 static void init_ppc_proc(PowerPCCPU *cpu)
7168 {
7169 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7170 CPUPPCState *env = &cpu->env;
7171 #if !defined(CONFIG_USER_ONLY)
7172 int i;
7173
7174 env->irq_inputs = NULL;
7175 /* Set all exception vectors to an invalid address */
7176 for (i = 0; i < POWERPC_EXCP_NB; i++) {
7177 env->excp_vectors[i] = (target_ulong)(-1ULL);
7178 }
7179 env->ivor_mask = 0x00000000;
7180 env->ivpr_mask = 0x00000000;
7181 /* Default MMU definitions */
7182 env->nb_BATs = 0;
7183 env->nb_tlb = 0;
7184 env->nb_ways = 0;
7185 env->tlb_type = TLB_NONE;
7186 #endif
7187 /* Register SPR common to all PowerPC implementations */
7188 register_generic_sprs(cpu);
7189
7190 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7191 (*pcc->init_proc)(env);
7192
7193 #if !defined(CONFIG_USER_ONLY)
7194 ppc_gdb_gen_spr_xml(cpu);
7195 #endif
7196
7197 /* MSR bits & flags consistency checks */
7198 if (env->msr_mask & (1 << 25)) {
7199 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7200 case POWERPC_FLAG_SPE:
7201 case POWERPC_FLAG_VRE:
7202 break;
7203 default:
7204 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7205 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7206 exit(1);
7207 }
7208 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7209 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7210 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7211 exit(1);
7212 }
7213 if (env->msr_mask & (1 << 17)) {
7214 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7215 case POWERPC_FLAG_TGPR:
7216 case POWERPC_FLAG_CE:
7217 break;
7218 default:
7219 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7220 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7221 exit(1);
7222 }
7223 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7224 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7225 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7226 exit(1);
7227 }
7228 if (env->msr_mask & (1 << 10)) {
7229 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7230 POWERPC_FLAG_UBLE)) {
7231 case POWERPC_FLAG_SE:
7232 case POWERPC_FLAG_DWE:
7233 case POWERPC_FLAG_UBLE:
7234 break;
7235 default:
7236 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7237 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7238 "POWERPC_FLAG_UBLE\n");
7239 exit(1);
7240 }
7241 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7242 POWERPC_FLAG_UBLE)) {
7243 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7244 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7245 "POWERPC_FLAG_UBLE\n");
7246 exit(1);
7247 }
7248 if (env->msr_mask & (1 << 9)) {
7249 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7250 case POWERPC_FLAG_BE:
7251 case POWERPC_FLAG_DE:
7252 break;
7253 default:
7254 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7255 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7256 exit(1);
7257 }
7258 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7259 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7260 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7261 exit(1);
7262 }
7263 if (env->msr_mask & (1 << 2)) {
7264 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7265 case POWERPC_FLAG_PX:
7266 case POWERPC_FLAG_PMM:
7267 break;
7268 default:
7269 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7270 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7271 exit(1);
7272 }
7273 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7274 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7275 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7276 exit(1);
7277 }
7278 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
7279 fprintf(stderr, "PowerPC flags inconsistency\n"
7280 "Should define the time-base and decrementer clock source\n");
7281 exit(1);
7282 }
7283 /* Allocate TLBs buffer when needed */
7284 #if !defined(CONFIG_USER_ONLY)
7285 if (env->nb_tlb != 0) {
7286 int nb_tlb = env->nb_tlb;
7287 if (env->id_tlbs != 0) {
7288 nb_tlb *= 2;
7289 }
7290 switch (env->tlb_type) {
7291 case TLB_6XX:
7292 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
7293 break;
7294 case TLB_EMB:
7295 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
7296 break;
7297 case TLB_MAS:
7298 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
7299 break;
7300 }
7301 /* Pre-compute some useful values */
7302 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7303 }
7304 if (env->irq_inputs == NULL) {
7305 warn_report("no internal IRQ controller registered."
7306 " Attempt QEMU to crash very soon !");
7307 }
7308 #endif
7309 if (env->check_pow == NULL) {
7310 warn_report("no power management check handler registered."
7311 " Attempt QEMU to crash very soon !");
7312 }
7313 }
7314
7315
7316 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
7317 {
7318 CPUState *cs = CPU(dev);
7319 PowerPCCPU *cpu = POWERPC_CPU(dev);
7320 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7321 Error *local_err = NULL;
7322
7323 cpu_exec_realizefn(cs, &local_err);
7324 if (local_err != NULL) {
7325 error_propagate(errp, local_err);
7326 return;
7327 }
7328 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
7329 cpu->vcpu_id = cs->cpu_index;
7330 }
7331
7332 if (tcg_enabled()) {
7333 if (ppc_fixup_cpu(cpu) != 0) {
7334 error_setg(errp, "Unable to emulate selected CPU with TCG");
7335 goto unrealize;
7336 }
7337 }
7338
7339 create_ppc_opcodes(cpu, &local_err);
7340 if (local_err != NULL) {
7341 error_propagate(errp, local_err);
7342 goto unrealize;
7343 }
7344 init_ppc_proc(cpu);
7345
7346 ppc_gdb_init(cs, pcc);
7347 qemu_init_vcpu(cs);
7348
7349 pcc->parent_realize(dev, errp);
7350
7351 return;
7352
7353 unrealize:
7354 cpu_exec_unrealizefn(cs);
7355 }
7356
7357 static void ppc_cpu_unrealize(DeviceState *dev)
7358 {
7359 PowerPCCPU *cpu = POWERPC_CPU(dev);
7360 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7361
7362 pcc->parent_unrealize(dev);
7363
7364 cpu_remove_sync(CPU(cpu));
7365
7366 destroy_ppc_opcodes(cpu);
7367 }
7368
7369 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7370 {
7371 ObjectClass *oc = (ObjectClass *)a;
7372 uint32_t pvr = *(uint32_t *)b;
7373 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7374
7375 /* -cpu host does a PVR lookup during construction */
7376 if (unlikely(strcmp(object_class_get_name(oc),
7377 TYPE_HOST_POWERPC_CPU) == 0)) {
7378 return -1;
7379 }
7380
7381 return pcc->pvr == pvr ? 0 : -1;
7382 }
7383
7384 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7385 {
7386 GSList *list, *item;
7387 PowerPCCPUClass *pcc = NULL;
7388
7389 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7390 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7391 if (item != NULL) {
7392 pcc = POWERPC_CPU_CLASS(item->data);
7393 }
7394 g_slist_free(list);
7395
7396 return pcc;
7397 }
7398
7399 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7400 {
7401 ObjectClass *oc = (ObjectClass *)a;
7402 uint32_t pvr = *(uint32_t *)b;
7403 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7404
7405 /* -cpu host does a PVR lookup during construction */
7406 if (unlikely(strcmp(object_class_get_name(oc),
7407 TYPE_HOST_POWERPC_CPU) == 0)) {
7408 return -1;
7409 }
7410
7411 if (pcc->pvr_match(pcc, pvr)) {
7412 return 0;
7413 }
7414
7415 return -1;
7416 }
7417
7418 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
7419 {
7420 GSList *list, *item;
7421 PowerPCCPUClass *pcc = NULL;
7422
7423 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7424 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7425 if (item != NULL) {
7426 pcc = POWERPC_CPU_CLASS(item->data);
7427 }
7428 g_slist_free(list);
7429
7430 return pcc;
7431 }
7432
7433 static const char *ppc_cpu_lookup_alias(const char *alias)
7434 {
7435 int ai;
7436
7437 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7438 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7439 return ppc_cpu_aliases[ai].model;
7440 }
7441 }
7442
7443 return NULL;
7444 }
7445
7446 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7447 {
7448 char *cpu_model, *typename;
7449 ObjectClass *oc;
7450 const char *p;
7451 unsigned long pvr;
7452
7453 /*
7454 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7455 * 0x prefix if present)
7456 */
7457 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7458 int len = p - name;
7459 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7460 if ((len == 8) && (*p == '\0')) {
7461 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7462 }
7463 }
7464
7465 cpu_model = g_ascii_strdown(name, -1);
7466 p = ppc_cpu_lookup_alias(cpu_model);
7467 if (p) {
7468 g_free(cpu_model);
7469 cpu_model = g_strdup(p);
7470 }
7471
7472 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7473 oc = object_class_by_name(typename);
7474 g_free(typename);
7475 g_free(cpu_model);
7476
7477 return oc;
7478 }
7479
7480 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7481 {
7482 ObjectClass *oc = OBJECT_CLASS(pcc);
7483
7484 while (oc && !object_class_is_abstract(oc)) {
7485 oc = object_class_get_parent(oc);
7486 }
7487 assert(oc);
7488
7489 return POWERPC_CPU_CLASS(oc);
7490 }
7491
7492 /* Sort by PVR, ordering special case "host" last. */
7493 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7494 {
7495 ObjectClass *oc_a = (ObjectClass *)a;
7496 ObjectClass *oc_b = (ObjectClass *)b;
7497 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7498 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7499 const char *name_a = object_class_get_name(oc_a);
7500 const char *name_b = object_class_get_name(oc_b);
7501
7502 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7503 return 1;
7504 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7505 return -1;
7506 } else {
7507 /* Avoid an integer overflow during subtraction */
7508 if (pcc_a->pvr < pcc_b->pvr) {
7509 return -1;
7510 } else if (pcc_a->pvr > pcc_b->pvr) {
7511 return 1;
7512 } else {
7513 return 0;
7514 }
7515 }
7516 }
7517
7518 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7519 {
7520 ObjectClass *oc = data;
7521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7522 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7523 const char *typename = object_class_get_name(oc);
7524 char *name;
7525 int i;
7526
7527 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7528 return;
7529 }
7530
7531 name = g_strndup(typename,
7532 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7533 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7534 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7535 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7536 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7537
7538 if (alias_oc != oc) {
7539 continue;
7540 }
7541 /*
7542 * If running with KVM, we might update the family alias later, so
7543 * avoid printing the wrong alias here and use "preferred" instead
7544 */
7545 if (strcmp(alias->alias, family->desc) == 0) {
7546 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7547 alias->alias, family->desc);
7548 } else {
7549 qemu_printf("PowerPC %-16s (alias for %s)\n",
7550 alias->alias, name);
7551 }
7552 }
7553 g_free(name);
7554 }
7555
7556 void ppc_cpu_list(void)
7557 {
7558 GSList *list;
7559
7560 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7561 list = g_slist_sort(list, ppc_cpu_list_compare);
7562 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7563 g_slist_free(list);
7564
7565 #ifdef CONFIG_KVM
7566 qemu_printf("\n");
7567 qemu_printf("PowerPC %s\n", "host");
7568 #endif
7569 }
7570
7571 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7572 {
7573 ObjectClass *oc = data;
7574 CpuDefinitionInfoList **first = user_data;
7575 const char *typename;
7576 CpuDefinitionInfo *info;
7577
7578 typename = object_class_get_name(oc);
7579 info = g_malloc0(sizeof(*info));
7580 info->name = g_strndup(typename,
7581 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7582
7583 QAPI_LIST_PREPEND(*first, info);
7584 }
7585
7586 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7587 {
7588 CpuDefinitionInfoList *cpu_list = NULL;
7589 GSList *list;
7590 int i;
7591
7592 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7593 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7594 g_slist_free(list);
7595
7596 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7597 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7598 ObjectClass *oc;
7599 CpuDefinitionInfo *info;
7600
7601 oc = ppc_cpu_class_by_name(alias->model);
7602 if (oc == NULL) {
7603 continue;
7604 }
7605
7606 info = g_malloc0(sizeof(*info));
7607 info->name = g_strdup(alias->alias);
7608 info->q_typename = g_strdup(object_class_get_name(oc));
7609
7610 QAPI_LIST_PREPEND(cpu_list, info);
7611 }
7612
7613 return cpu_list;
7614 }
7615
7616 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7617 {
7618 PowerPCCPU *cpu = POWERPC_CPU(cs);
7619
7620 cpu->env.nip = value;
7621 }
7622
7623 static bool ppc_cpu_has_work(CPUState *cs)
7624 {
7625 PowerPCCPU *cpu = POWERPC_CPU(cs);
7626 CPUPPCState *env = &cpu->env;
7627
7628 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7629 }
7630
7631 static void ppc_cpu_reset(DeviceState *dev)
7632 {
7633 CPUState *s = CPU(dev);
7634 PowerPCCPU *cpu = POWERPC_CPU(s);
7635 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7636 CPUPPCState *env = &cpu->env;
7637 target_ulong msr;
7638 int i;
7639
7640 pcc->parent_reset(dev);
7641
7642 msr = (target_ulong)0;
7643 msr |= (target_ulong)MSR_HVB;
7644 msr |= (target_ulong)1 << MSR_EP;
7645 #if defined(DO_SINGLE_STEP) && 0
7646 /* Single step trace mode */
7647 msr |= (target_ulong)1 << MSR_SE;
7648 msr |= (target_ulong)1 << MSR_BE;
7649 #endif
7650 #if defined(CONFIG_USER_ONLY)
7651 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7652 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7653 msr |= (target_ulong)1 << MSR_FE1;
7654 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7655 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7656 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7657 msr |= (target_ulong)1 << MSR_PR;
7658 #if defined(TARGET_PPC64)
7659 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7660 #endif
7661 #if !defined(TARGET_WORDS_BIGENDIAN)
7662 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7663 if (!((env->msr_mask >> MSR_LE) & 1)) {
7664 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7665 exit(1);
7666 }
7667 #endif
7668 #endif
7669
7670 #if defined(TARGET_PPC64)
7671 if (mmu_is_64bit(env->mmu_model)) {
7672 msr |= (1ULL << MSR_SF);
7673 }
7674 #endif
7675
7676 hreg_store_msr(env, msr, 1);
7677
7678 #if !defined(CONFIG_USER_ONLY)
7679 env->nip = env->hreset_vector | env->excp_prefix;
7680 #if defined(CONFIG_TCG)
7681 if (env->mmu_model != POWERPC_MMU_REAL) {
7682 ppc_tlb_invalidate_all(env);
7683 }
7684 #endif /* CONFIG_TCG */
7685 #endif
7686
7687 pmu_update_summaries(env);
7688 hreg_compute_hflags(env);
7689 env->reserve_addr = (target_ulong)-1ULL;
7690 /* Be sure no exception or interrupt is pending */
7691 env->pending_interrupts = 0;
7692 s->exception_index = POWERPC_EXCP_NONE;
7693 env->error_code = 0;
7694 ppc_irq_reset(cpu);
7695
7696 /* tininess for underflow is detected before rounding */
7697 set_float_detect_tininess(float_tininess_before_rounding,
7698 &env->fp_status);
7699
7700 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7701 ppc_spr_t *spr = &env->spr_cb[i];
7702
7703 if (!spr->name) {
7704 continue;
7705 }
7706 env->spr[i] = spr->default_value;
7707 }
7708 }
7709
7710 #ifndef CONFIG_USER_ONLY
7711
7712 static bool ppc_cpu_is_big_endian(CPUState *cs)
7713 {
7714 PowerPCCPU *cpu = POWERPC_CPU(cs);
7715 CPUPPCState *env = &cpu->env;
7716
7717 cpu_synchronize_state(cs);
7718
7719 return !msr_le;
7720 }
7721
7722 #ifdef CONFIG_TCG
7723 static void ppc_cpu_exec_enter(CPUState *cs)
7724 {
7725 PowerPCCPU *cpu = POWERPC_CPU(cs);
7726
7727 if (cpu->vhyp) {
7728 PPCVirtualHypervisorClass *vhc =
7729 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7730 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7731 }
7732 }
7733
7734 static void ppc_cpu_exec_exit(CPUState *cs)
7735 {
7736 PowerPCCPU *cpu = POWERPC_CPU(cs);
7737
7738 if (cpu->vhyp) {
7739 PPCVirtualHypervisorClass *vhc =
7740 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7741 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7742 }
7743 }
7744 #endif /* CONFIG_TCG */
7745
7746 #endif /* !CONFIG_USER_ONLY */
7747
7748 static void ppc_cpu_instance_init(Object *obj)
7749 {
7750 PowerPCCPU *cpu = POWERPC_CPU(obj);
7751 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7752 CPUPPCState *env = &cpu->env;
7753
7754 cpu_set_cpustate_pointers(cpu);
7755 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7756
7757 env->msr_mask = pcc->msr_mask;
7758 env->mmu_model = pcc->mmu_model;
7759 env->excp_model = pcc->excp_model;
7760 env->bus_model = pcc->bus_model;
7761 env->insns_flags = pcc->insns_flags;
7762 env->insns_flags2 = pcc->insns_flags2;
7763 env->flags = pcc->flags;
7764 env->bfd_mach = pcc->bfd_mach;
7765 env->check_pow = pcc->check_pow;
7766
7767 /*
7768 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7769 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7770 * mode support will remain, thus enforcing that we cannot use
7771 * priv. instructions in guest in PAPR mode. For 970 we currently
7772 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7773 * 970. If we ever want to support 970 HV mode, we'll have to add
7774 * a processor attribute of some sort.
7775 */
7776 #if !defined(CONFIG_USER_ONLY)
7777 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7778 #endif
7779
7780 ppc_hash64_init(cpu);
7781 }
7782
7783 static void ppc_cpu_instance_finalize(Object *obj)
7784 {
7785 PowerPCCPU *cpu = POWERPC_CPU(obj);
7786
7787 ppc_hash64_finalize(cpu);
7788 }
7789
7790 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
7791 {
7792 return pcc->pvr == pvr;
7793 }
7794
7795 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7796 {
7797 PowerPCCPU *cpu = POWERPC_CPU(cs);
7798 CPUPPCState *env = &cpu->env;
7799
7800 if ((env->hflags >> MSR_LE) & 1) {
7801 info->endian = BFD_ENDIAN_LITTLE;
7802 }
7803 info->mach = env->bfd_mach;
7804 if (!env->bfd_mach) {
7805 #ifdef TARGET_PPC64
7806 info->mach = bfd_mach_ppc64;
7807 #else
7808 info->mach = bfd_mach_ppc;
7809 #endif
7810 }
7811 info->disassembler_options = (char *)"any";
7812 info->print_insn = print_insn_ppc;
7813
7814 info->cap_arch = CS_ARCH_PPC;
7815 #ifdef TARGET_PPC64
7816 info->cap_mode = CS_MODE_64;
7817 #endif
7818 }
7819
7820 static Property ppc_cpu_properties[] = {
7821 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7822 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7823 false),
7824 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7825 false),
7826 DEFINE_PROP_END_OF_LIST(),
7827 };
7828
7829 #ifndef CONFIG_USER_ONLY
7830 #include "hw/core/sysemu-cpu-ops.h"
7831
7832 static const struct SysemuCPUOps ppc_sysemu_ops = {
7833 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7834 .write_elf32_note = ppc32_cpu_write_elf32_note,
7835 .write_elf64_note = ppc64_cpu_write_elf64_note,
7836 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7837 .legacy_vmsd = &vmstate_ppc_cpu,
7838 };
7839 #endif
7840
7841 #ifdef CONFIG_TCG
7842 #include "hw/core/tcg-cpu-ops.h"
7843
7844 static const struct TCGCPUOps ppc_tcg_ops = {
7845 .initialize = ppc_translate_init,
7846
7847 #ifdef CONFIG_USER_ONLY
7848 .record_sigsegv = ppc_cpu_record_sigsegv,
7849 #else
7850 .tlb_fill = ppc_cpu_tlb_fill,
7851 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7852 .do_interrupt = ppc_cpu_do_interrupt,
7853 .cpu_exec_enter = ppc_cpu_exec_enter,
7854 .cpu_exec_exit = ppc_cpu_exec_exit,
7855 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7856 #endif /* !CONFIG_USER_ONLY */
7857 };
7858 #endif /* CONFIG_TCG */
7859
7860 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7861 {
7862 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7863 CPUClass *cc = CPU_CLASS(oc);
7864 DeviceClass *dc = DEVICE_CLASS(oc);
7865
7866 device_class_set_parent_realize(dc, ppc_cpu_realize,
7867 &pcc->parent_realize);
7868 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7869 &pcc->parent_unrealize);
7870 pcc->pvr_match = ppc_pvr_match_default;
7871 device_class_set_props(dc, ppc_cpu_properties);
7872
7873 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
7874
7875 cc->class_by_name = ppc_cpu_class_by_name;
7876 cc->has_work = ppc_cpu_has_work;
7877 cc->dump_state = ppc_cpu_dump_state;
7878 cc->set_pc = ppc_cpu_set_pc;
7879 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7880 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7881 #ifndef CONFIG_USER_ONLY
7882 cc->sysemu_ops = &ppc_sysemu_ops;
7883 #endif
7884
7885 cc->gdb_num_core_regs = 71;
7886 #ifndef CONFIG_USER_ONLY
7887 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7888 #endif
7889 #ifdef USE_APPLE_GDB
7890 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7891 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7892 cc->gdb_num_core_regs = 71 + 32;
7893 #endif
7894
7895 cc->gdb_arch_name = ppc_gdb_arch_name;
7896 #if defined(TARGET_PPC64)
7897 cc->gdb_core_xml_file = "power64-core.xml";
7898 #else
7899 cc->gdb_core_xml_file = "power-core.xml";
7900 #endif
7901 cc->disas_set_info = ppc_disas_set_info;
7902
7903 dc->fw_name = "PowerPC,UNKNOWN";
7904
7905 #ifdef CONFIG_TCG
7906 cc->tcg_ops = &ppc_tcg_ops;
7907 #endif /* CONFIG_TCG */
7908 }
7909
7910 static const TypeInfo ppc_cpu_type_info = {
7911 .name = TYPE_POWERPC_CPU,
7912 .parent = TYPE_CPU,
7913 .instance_size = sizeof(PowerPCCPU),
7914 .instance_align = __alignof__(PowerPCCPU),
7915 .instance_init = ppc_cpu_instance_init,
7916 .instance_finalize = ppc_cpu_instance_finalize,
7917 .abstract = true,
7918 .class_size = sizeof(PowerPCCPUClass),
7919 .class_init = ppc_cpu_class_init,
7920 };
7921
7922 #ifndef CONFIG_USER_ONLY
7923 static const TypeInfo ppc_vhyp_type_info = {
7924 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7925 .parent = TYPE_INTERFACE,
7926 .class_size = sizeof(PPCVirtualHypervisorClass),
7927 };
7928 #endif
7929
7930 static void ppc_cpu_register_types(void)
7931 {
7932 type_register_static(&ppc_cpu_type_info);
7933 #ifndef CONFIG_USER_ONLY
7934 type_register_static(&ppc_vhyp_type_info);
7935 #endif
7936 }
7937
7938 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7939 {
7940 #define RGPL 4
7941 #define RFPL 4
7942
7943 PowerPCCPU *cpu = POWERPC_CPU(cs);
7944 CPUPPCState *env = &cpu->env;
7945 int i;
7946
7947 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7948 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7949 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7950 cs->cpu_index);
7951 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7952 "%08x iidx %d didx %d\n",
7953 env->msr, env->spr[SPR_HID0], env->hflags,
7954 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
7955 #if !defined(NO_TIMER_DUMP)
7956 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7957 #if !defined(CONFIG_USER_ONLY)
7958 " DECR " TARGET_FMT_lu
7959 #endif
7960 "\n",
7961 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7962 #if !defined(CONFIG_USER_ONLY)
7963 , cpu_ppc_load_decr(env)
7964 #endif
7965 );
7966 #endif
7967 for (i = 0; i < 32; i++) {
7968 if ((i & (RGPL - 1)) == 0) {
7969 qemu_fprintf(f, "GPR%02d", i);
7970 }
7971 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7972 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7973 qemu_fprintf(f, "\n");
7974 }
7975 }
7976 qemu_fprintf(f, "CR ");
7977 for (i = 0; i < 8; i++)
7978 qemu_fprintf(f, "%01x", env->crf[i]);
7979 qemu_fprintf(f, " [");
7980 for (i = 0; i < 8; i++) {
7981 char a = '-';
7982 if (env->crf[i] & 0x08) {
7983 a = 'L';
7984 } else if (env->crf[i] & 0x04) {
7985 a = 'G';
7986 } else if (env->crf[i] & 0x02) {
7987 a = 'E';
7988 }
7989 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7990 }
7991 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7992 env->reserve_addr);
7993
7994 if (flags & CPU_DUMP_FPU) {
7995 for (i = 0; i < 32; i++) {
7996 if ((i & (RFPL - 1)) == 0) {
7997 qemu_fprintf(f, "FPR%02d", i);
7998 }
7999 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
8000 if ((i & (RFPL - 1)) == (RFPL - 1)) {
8001 qemu_fprintf(f, "\n");
8002 }
8003 }
8004 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
8005 }
8006
8007 #if !defined(CONFIG_USER_ONLY)
8008 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
8009 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
8010 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
8011 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
8012
8013 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
8014 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
8015 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
8016 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
8017
8018 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
8019 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
8020 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
8021 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
8022
8023 switch (env->excp_model) {
8024 #if defined(TARGET_PPC64)
8025 case POWERPC_EXCP_POWER7:
8026 case POWERPC_EXCP_POWER8:
8027 case POWERPC_EXCP_POWER9:
8028 case POWERPC_EXCP_POWER10:
8029 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
8030 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
8031 break;
8032 #endif
8033 case POWERPC_EXCP_BOOKE:
8034 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
8035 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
8036 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
8037 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
8038
8039 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8040 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8041 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
8042 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
8043
8044 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
8045 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
8046 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
8047 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
8048
8049 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
8050 " EPR " TARGET_FMT_lx "\n",
8051 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
8052 env->spr[SPR_BOOKE_EPR]);
8053
8054 /* FSL-specific */
8055 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
8056 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
8057 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
8058 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
8059
8060 /*
8061 * IVORs are left out as they are large and do not change often --
8062 * they can be read with "p $ivor0", "p $ivor1", etc.
8063 */
8064 break;
8065 case POWERPC_EXCP_40x:
8066 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8067 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8068 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
8069 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
8070
8071 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
8072 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8073 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
8074 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
8075 break;
8076 default:
8077 break;
8078 }
8079
8080 #if defined(TARGET_PPC64)
8081 if (env->flags & POWERPC_FLAG_CFAR) {
8082 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
8083 }
8084 #endif
8085
8086 if (env->spr_cb[SPR_LPCR].name) {
8087 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
8088 }
8089
8090 switch (env->mmu_model) {
8091 case POWERPC_MMU_32B:
8092 case POWERPC_MMU_SOFT_6xx:
8093 #if defined(TARGET_PPC64)
8094 case POWERPC_MMU_64B:
8095 case POWERPC_MMU_2_03:
8096 case POWERPC_MMU_2_06:
8097 case POWERPC_MMU_2_07:
8098 case POWERPC_MMU_3_00:
8099 #endif
8100 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
8101 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
8102 }
8103 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
8104 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
8105 }
8106 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
8107 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
8108 break;
8109 case POWERPC_MMU_BOOKE206:
8110 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
8111 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
8112 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
8113 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
8114
8115 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
8116 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8117 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
8118 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
8119
8120 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
8121 " TLB1CFG " TARGET_FMT_lx "\n",
8122 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
8123 env->spr[SPR_BOOKE_TLB1CFG]);
8124 break;
8125 default:
8126 break;
8127 }
8128 #endif
8129
8130 #undef RGPL
8131 #undef RFPL
8132 }
8133 type_init(ppc_cpu_register_types)
Ray Wang's QEMU Repository