4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
14 #include "internals.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/host-utils.h"
17 #include "qemu/main-loop.h"
18 #include "qemu/timer.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "qemu/range.h"
30 #include "qapi/qapi-commands-machine-target.h"
31 #include "qapi/error.h"
32 #include "qemu/guest-random.h"
35 #include "exec/cpu_ldst.h"
36 #include "semihosting/common-semi.h"
40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
42 static void switch_mode(CPUARMState
*env
, int mode
);
44 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
46 assert(ri
->fieldoffset
);
47 if (cpreg_field_is_64bit(ri
)) {
48 return CPREG_FIELD64(env
, ri
);
50 return CPREG_FIELD32(env
, ri
);
54 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
57 assert(ri
->fieldoffset
);
58 if (cpreg_field_is_64bit(ri
)) {
59 CPREG_FIELD64(env
, ri
) = value
;
61 CPREG_FIELD32(env
, ri
) = value
;
65 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
67 return (char *)env
+ ri
->fieldoffset
;
70 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
72 /* Raw read of a coprocessor register (as needed for migration, etc). */
73 if (ri
->type
& ARM_CP_CONST
) {
74 return ri
->resetvalue
;
75 } else if (ri
->raw_readfn
) {
76 return ri
->raw_readfn(env
, ri
);
77 } else if (ri
->readfn
) {
78 return ri
->readfn(env
, ri
);
80 return raw_read(env
, ri
);
84 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
87 /* Raw write of a coprocessor register (as needed for migration, etc).
88 * Note that constant registers are treated as write-ignored; the
89 * caller should check for success by whether a readback gives the
92 if (ri
->type
& ARM_CP_CONST
) {
94 } else if (ri
->raw_writefn
) {
95 ri
->raw_writefn(env
, ri
, v
);
96 } else if (ri
->writefn
) {
97 ri
->writefn(env
, ri
, v
);
99 raw_write(env
, ri
, v
);
103 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
105 /* Return true if the regdef would cause an assertion if you called
106 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
107 * program bug for it not to have the NO_RAW flag).
108 * NB that returning false here doesn't necessarily mean that calling
109 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
110 * read/write access functions which are safe for raw use" from "has
111 * read/write access functions which have side effects but has forgotten
112 * to provide raw access functions".
113 * The tests here line up with the conditions in read/write_raw_cp_reg()
114 * and assertions in raw_read()/raw_write().
116 if ((ri
->type
& ARM_CP_CONST
) ||
118 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
124 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
126 /* Write the coprocessor state from cpu->env to the (index,value) list. */
130 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
131 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
132 const ARMCPRegInfo
*ri
;
135 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
140 if (ri
->type
& ARM_CP_NO_RAW
) {
144 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
147 * Only sync if the previous list->cpustate sync succeeded.
148 * Rather than tracking the success/failure state for every
149 * item in the list, we just recheck "does the raw write we must
150 * have made in write_list_to_cpustate() read back OK" here.
152 uint64_t oldval
= cpu
->cpreg_values
[i
];
154 if (oldval
== newval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
159 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
163 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
165 cpu
->cpreg_values
[i
] = newval
;
170 bool write_list_to_cpustate(ARMCPU
*cpu
)
175 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
176 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
177 uint64_t v
= cpu
->cpreg_values
[i
];
178 const ARMCPRegInfo
*ri
;
180 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
185 if (ri
->type
& ARM_CP_NO_RAW
) {
188 /* Write value and confirm it reads back as written
189 * (to catch read-only registers and partially read-only
190 * registers where the incoming migration value doesn't match)
192 write_raw_cp_reg(&cpu
->env
, ri
, v
);
193 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
200 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
202 ARMCPU
*cpu
= opaque
;
203 uint32_t regidx
= (uintptr_t)key
;
204 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
206 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
207 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
208 /* The value array need not be initialized at this point */
209 cpu
->cpreg_array_len
++;
213 static void count_cpreg(gpointer key
, gpointer opaque
)
215 ARMCPU
*cpu
= opaque
;
216 const ARMCPRegInfo
*ri
;
218 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
220 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
221 cpu
->cpreg_array_len
++;
225 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
227 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
228 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
239 void init_cpreg_list(ARMCPU
*cpu
)
241 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
242 * Note that we require cpreg_tuples[] to be sorted by key ID.
247 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
248 keys
= g_list_sort(keys
, cpreg_key_compare
);
250 cpu
->cpreg_array_len
= 0;
252 g_list_foreach(keys
, count_cpreg
, cpu
);
254 arraylen
= cpu
->cpreg_array_len
;
255 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
257 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
258 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
259 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
260 cpu
->cpreg_array_len
= 0;
262 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
264 assert(cpu
->cpreg_array_len
== arraylen
);
270 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
272 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
273 const ARMCPRegInfo
*ri
,
276 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
277 arm_is_secure_below_el3(env
)) {
278 return CP_ACCESS_TRAP_UNCATEGORIZED
;
283 /* Some secure-only AArch32 registers trap to EL3 if used from
284 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
285 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
286 * We assume that the .access field is set to PL1_RW.
288 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
289 const ARMCPRegInfo
*ri
,
292 if (arm_current_el(env
) == 3) {
295 if (arm_is_secure_below_el3(env
)) {
296 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
297 return CP_ACCESS_TRAP_EL2
;
299 return CP_ACCESS_TRAP_EL3
;
301 /* This will be EL1 NS and EL2 NS, which just UNDEF */
302 return CP_ACCESS_TRAP_UNCATEGORIZED
;
305 static uint64_t arm_mdcr_el2_eff(CPUARMState
*env
)
307 return arm_is_el2_enabled(env
) ? env
->cp15
.mdcr_el2
: 0;
310 /* Check for traps to "powerdown debug" registers, which are controlled
313 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
316 int el
= arm_current_el(env
);
317 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
318 bool mdcr_el2_tdosa
= (mdcr_el2
& MDCR_TDOSA
) || (mdcr_el2
& MDCR_TDE
) ||
319 (arm_hcr_el2_eff(env
) & HCR_TGE
);
321 if (el
< 2 && mdcr_el2_tdosa
) {
322 return CP_ACCESS_TRAP_EL2
;
324 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
325 return CP_ACCESS_TRAP_EL3
;
330 /* Check for traps to "debug ROM" registers, which are controlled
331 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
333 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
336 int el
= arm_current_el(env
);
337 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
338 bool mdcr_el2_tdra
= (mdcr_el2
& MDCR_TDRA
) || (mdcr_el2
& MDCR_TDE
) ||
339 (arm_hcr_el2_eff(env
) & HCR_TGE
);
341 if (el
< 2 && mdcr_el2_tdra
) {
342 return CP_ACCESS_TRAP_EL2
;
344 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
345 return CP_ACCESS_TRAP_EL3
;
350 /* Check for traps to general debug registers, which are controlled
351 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
353 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
356 int el
= arm_current_el(env
);
357 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
358 bool mdcr_el2_tda
= (mdcr_el2
& MDCR_TDA
) || (mdcr_el2
& MDCR_TDE
) ||
359 (arm_hcr_el2_eff(env
) & HCR_TGE
);
361 if (el
< 2 && mdcr_el2_tda
) {
362 return CP_ACCESS_TRAP_EL2
;
364 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
365 return CP_ACCESS_TRAP_EL3
;
370 /* Check for traps to performance monitor registers, which are controlled
371 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
373 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
376 int el
= arm_current_el(env
);
377 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
379 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
380 return CP_ACCESS_TRAP_EL2
;
382 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
383 return CP_ACCESS_TRAP_EL3
;
388 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
389 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
392 if (arm_current_el(env
) == 1) {
393 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
394 if (arm_hcr_el2_eff(env
) & trap
) {
395 return CP_ACCESS_TRAP_EL2
;
401 /* Check for traps from EL1 due to HCR_EL2.TSW. */
402 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
405 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
406 return CP_ACCESS_TRAP_EL2
;
411 /* Check for traps from EL1 due to HCR_EL2.TACR. */
412 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
415 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
416 return CP_ACCESS_TRAP_EL2
;
421 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
422 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
425 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
426 return CP_ACCESS_TRAP_EL2
;
431 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
433 ARMCPU
*cpu
= env_archcpu(env
);
435 raw_write(env
, ri
, value
);
436 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
439 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
441 ARMCPU
*cpu
= env_archcpu(env
);
443 if (raw_read(env
, ri
) != value
) {
444 /* Unlike real hardware the qemu TLB uses virtual addresses,
445 * not modified virtual addresses, so this causes a TLB flush.
448 raw_write(env
, ri
, value
);
452 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
455 ARMCPU
*cpu
= env_archcpu(env
);
457 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
458 && !extended_addresses_enabled(env
)) {
459 /* For VMSA (when not using the LPAE long descriptor page table
460 * format) this register includes the ASID, so do a TLB flush.
461 * For PMSA it is purely a process ID and no action is needed.
465 raw_write(env
, ri
, value
);
468 /* IS variants of TLB operations must affect all cores */
469 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
472 CPUState
*cs
= env_cpu(env
);
474 tlb_flush_all_cpus_synced(cs
);
477 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
480 CPUState
*cs
= env_cpu(env
);
482 tlb_flush_all_cpus_synced(cs
);
485 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
488 CPUState
*cs
= env_cpu(env
);
490 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
493 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
496 CPUState
*cs
= env_cpu(env
);
498 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
502 * Non-IS variants of TLB operations are upgraded to
503 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
504 * force broadcast of these operations.
506 static bool tlb_force_broadcast(CPUARMState
*env
)
508 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
511 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
514 /* Invalidate all (TLBIALL) */
515 CPUState
*cs
= env_cpu(env
);
517 if (tlb_force_broadcast(env
)) {
518 tlb_flush_all_cpus_synced(cs
);
524 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
527 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
528 CPUState
*cs
= env_cpu(env
);
530 value
&= TARGET_PAGE_MASK
;
531 if (tlb_force_broadcast(env
)) {
532 tlb_flush_page_all_cpus_synced(cs
, value
);
534 tlb_flush_page(cs
, value
);
538 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 /* Invalidate by ASID (TLBIASID) */
542 CPUState
*cs
= env_cpu(env
);
544 if (tlb_force_broadcast(env
)) {
545 tlb_flush_all_cpus_synced(cs
);
551 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
554 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
555 CPUState
*cs
= env_cpu(env
);
557 value
&= TARGET_PAGE_MASK
;
558 if (tlb_force_broadcast(env
)) {
559 tlb_flush_page_all_cpus_synced(cs
, value
);
561 tlb_flush_page(cs
, value
);
565 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
568 CPUState
*cs
= env_cpu(env
);
570 tlb_flush_by_mmuidx(cs
,
572 ARMMMUIdxBit_E10_1_PAN
|
576 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
579 CPUState
*cs
= env_cpu(env
);
581 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
583 ARMMMUIdxBit_E10_1_PAN
|
588 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
591 CPUState
*cs
= env_cpu(env
);
593 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
596 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
599 CPUState
*cs
= env_cpu(env
);
601 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
604 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
607 CPUState
*cs
= env_cpu(env
);
608 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
610 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
613 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 CPUState
*cs
= env_cpu(env
);
617 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
619 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
623 static const ARMCPRegInfo cp_reginfo
[] = {
624 /* Define the secure and non-secure FCSE identifier CP registers
625 * separately because there is no secure bank in V8 (no _EL3). This allows
626 * the secure register to be properly reset and migrated. There is also no
627 * v8 EL1 version of the register so the non-secure instance stands alone.
630 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
631 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
633 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
634 { .name
= "FCSEIDR_S",
635 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
636 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
637 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
638 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
639 /* Define the secure and non-secure context identifier CP registers
640 * separately because there is no secure bank in V8 (no _EL3). This allows
641 * the secure register to be properly reset and migrated. In the
642 * non-secure case, the 32-bit register will have reset and migration
643 * disabled during registration as it is handled by the 64-bit instance.
645 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
646 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
647 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
648 .secure
= ARM_CP_SECSTATE_NS
,
649 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
650 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
651 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
652 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
653 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
654 .secure
= ARM_CP_SECSTATE_S
,
655 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
656 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
659 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
660 /* NB: Some of these registers exist in v8 but with more precise
661 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
663 /* MMU Domain access control / MPU write buffer control */
665 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
666 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
667 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
668 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
669 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
670 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
671 * For v6 and v5, these mappings are overly broad.
673 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
674 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
675 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
676 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
677 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
678 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
679 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
680 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
681 /* Cache maintenance ops; some of this space may be overridden later. */
682 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
683 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
684 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
687 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
688 /* Not all pre-v6 cores implemented this WFI, so this is slightly
691 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
692 .access
= PL1_W
, .type
= ARM_CP_WFI
},
695 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
696 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
697 * is UNPREDICTABLE; we choose to NOP as most implementations do).
699 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
700 .access
= PL1_W
, .type
= ARM_CP_WFI
},
701 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
702 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
703 * OMAPCP will override this space.
705 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
706 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
708 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
709 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
711 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
712 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
713 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
715 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
716 * implementing it as RAZ means the "debug architecture version" bits
717 * will read as a reserved value, which should cause Linux to not try
718 * to use the debug hardware.
720 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
721 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
722 /* MMU TLB control. Note that the wildcarding means we cover not just
723 * the unified TLB ops but also the dside/iside/inner-shareable variants.
725 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
726 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
727 .type
= ARM_CP_NO_RAW
},
728 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
729 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
730 .type
= ARM_CP_NO_RAW
},
731 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
732 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
733 .type
= ARM_CP_NO_RAW
},
734 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
735 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
736 .type
= ARM_CP_NO_RAW
},
737 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
738 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
739 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
740 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
743 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
748 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
749 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
750 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
751 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
752 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
754 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
755 /* VFP coprocessor: cp10 & cp11 [23:20] */
756 mask
|= R_CPACR_ASEDIS_MASK
|
757 R_CPACR_D32DIS_MASK
|
761 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
762 /* ASEDIS [31] bit is RAO/WI */
763 value
|= R_CPACR_ASEDIS_MASK
;
766 /* VFPv3 and upwards with NEON implement 32 double precision
767 * registers (D0-D31).
769 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
770 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
771 value
|= R_CPACR_D32DIS_MASK
;
778 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
779 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
781 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
782 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
783 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
784 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
787 env
->cp15
.cpacr_el1
= value
;
790 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
793 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
794 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
796 uint64_t value
= env
->cp15
.cpacr_el1
;
798 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
799 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
800 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
806 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
808 /* Call cpacr_write() so that we reset with the correct RAO bits set
809 * for our CPU features.
811 cpacr_write(env
, ri
, 0);
814 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
817 if (arm_feature(env
, ARM_FEATURE_V8
)) {
818 /* Check if CPACR accesses are to be trapped to EL2 */
819 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
820 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
821 return CP_ACCESS_TRAP_EL2
;
822 /* Check if CPACR accesses are to be trapped to EL3 */
823 } else if (arm_current_el(env
) < 3 &&
824 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
825 return CP_ACCESS_TRAP_EL3
;
832 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
835 /* Check if CPTR accesses are set to trap to EL3 */
836 if (arm_current_el(env
) == 2 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
844 static const ARMCPRegInfo v6_cp_reginfo
[] = {
845 /* prefetch by MVA in v6, NOP in v7 */
846 { .name
= "MVA_prefetch",
847 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
849 /* We need to break the TB after ISB to execute self-modifying code
850 * correctly and also to take any pending interrupts immediately.
851 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
853 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
854 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
855 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
856 .access
= PL0_W
, .type
= ARM_CP_NOP
},
857 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
858 .access
= PL0_W
, .type
= ARM_CP_NOP
},
859 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
860 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
861 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
862 offsetof(CPUARMState
, cp15
.ifar_ns
) },
864 /* Watchpoint Fault Address Register : should actually only be present
865 * for 1136, 1176, 11MPCore.
867 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
868 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
869 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
870 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
871 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
872 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
875 typedef struct pm_event
{
876 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
877 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
878 bool (*supported
)(CPUARMState
*);
880 * Retrieve the current count of the underlying event. The programmed
881 * counters hold a difference from the return value from this function
883 uint64_t (*get_count
)(CPUARMState
*);
885 * Return how many nanoseconds it will take (at a minimum) for count events
886 * to occur. A negative value indicates the counter will never overflow, or
887 * that the counter has otherwise arranged for the overflow bit to be set
888 * and the PMU interrupt to be raised on overflow.
890 int64_t (*ns_per_count
)(uint64_t);
893 static bool event_always_supported(CPUARMState
*env
)
898 static uint64_t swinc_get_count(CPUARMState
*env
)
901 * SW_INCR events are written directly to the pmevcntr's by writes to
902 * PMSWINC, so there is no underlying count maintained by the PMU itself
907 static int64_t swinc_ns_per(uint64_t ignored
)
913 * Return the underlying cycle count for the PMU cycle counters. If we're in
914 * usermode, simply return 0.
916 static uint64_t cycles_get_count(CPUARMState
*env
)
918 #ifndef CONFIG_USER_ONLY
919 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
920 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
922 return cpu_get_host_ticks();
926 #ifndef CONFIG_USER_ONLY
927 static int64_t cycles_ns_per(uint64_t cycles
)
929 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
932 static bool instructions_supported(CPUARMState
*env
)
934 return icount_enabled() == 1; /* Precise instruction counting */
937 static uint64_t instructions_get_count(CPUARMState
*env
)
939 return (uint64_t)icount_get_raw();
942 static int64_t instructions_ns_per(uint64_t icount
)
944 return icount_to_ns((int64_t)icount
);
948 static bool pmu_8_1_events_supported(CPUARMState
*env
)
950 /* For events which are supported in any v8.1 PMU */
951 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
954 static bool pmu_8_4_events_supported(CPUARMState
*env
)
956 /* For events which are supported in any v8.1 PMU */
957 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
960 static uint64_t zero_event_get_count(CPUARMState
*env
)
962 /* For events which on QEMU never fire, so their count is always zero */
966 static int64_t zero_event_ns_per(uint64_t cycles
)
968 /* An event which never fires can never overflow */
972 static const pm_event pm_events
[] = {
973 { .number
= 0x000, /* SW_INCR */
974 .supported
= event_always_supported
,
975 .get_count
= swinc_get_count
,
976 .ns_per_count
= swinc_ns_per
,
978 #ifndef CONFIG_USER_ONLY
979 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
980 .supported
= instructions_supported
,
981 .get_count
= instructions_get_count
,
982 .ns_per_count
= instructions_ns_per
,
984 { .number
= 0x011, /* CPU_CYCLES, Cycle */
985 .supported
= event_always_supported
,
986 .get_count
= cycles_get_count
,
987 .ns_per_count
= cycles_ns_per
,
990 { .number
= 0x023, /* STALL_FRONTEND */
991 .supported
= pmu_8_1_events_supported
,
992 .get_count
= zero_event_get_count
,
993 .ns_per_count
= zero_event_ns_per
,
995 { .number
= 0x024, /* STALL_BACKEND */
996 .supported
= pmu_8_1_events_supported
,
997 .get_count
= zero_event_get_count
,
998 .ns_per_count
= zero_event_ns_per
,
1000 { .number
= 0x03c, /* STALL */
1001 .supported
= pmu_8_4_events_supported
,
1002 .get_count
= zero_event_get_count
,
1003 .ns_per_count
= zero_event_ns_per
,
1008 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1009 * events (i.e. the statistical profiling extension), this implementation
1010 * should first be updated to something sparse instead of the current
1011 * supported_event_map[] array.
1013 #define MAX_EVENT_ID 0x3c
1014 #define UNSUPPORTED_EVENT UINT16_MAX
1015 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1018 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1019 * of ARM event numbers to indices in our pm_events array.
1021 * Note: Events in the 0x40XX range are not currently supported.
1023 void pmu_init(ARMCPU
*cpu
)
1028 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1031 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1032 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1037 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1038 const pm_event
*cnt
= &pm_events
[i
];
1039 assert(cnt
->number
<= MAX_EVENT_ID
);
1040 /* We do not currently support events in the 0x40xx range */
1041 assert(cnt
->number
<= 0x3f);
1043 if (cnt
->supported(&cpu
->env
)) {
1044 supported_event_map
[cnt
->number
] = i
;
1045 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1046 if (cnt
->number
& 0x20) {
1047 cpu
->pmceid1
|= event_mask
;
1049 cpu
->pmceid0
|= event_mask
;
1056 * Check at runtime whether a PMU event is supported for the current machine
1058 static bool event_supported(uint16_t number
)
1060 if (number
> MAX_EVENT_ID
) {
1063 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1066 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1069 /* Performance monitor registers user accessibility is controlled
1070 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1071 * trapping to EL2 or EL3 for other accesses.
1073 int el
= arm_current_el(env
);
1074 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1076 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1077 return CP_ACCESS_TRAP
;
1079 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1080 return CP_ACCESS_TRAP_EL2
;
1082 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1083 return CP_ACCESS_TRAP_EL3
;
1086 return CP_ACCESS_OK
;
1089 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1090 const ARMCPRegInfo
*ri
,
1093 /* ER: event counter read trap control */
1094 if (arm_feature(env
, ARM_FEATURE_V8
)
1095 && arm_current_el(env
) == 0
1096 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1098 return CP_ACCESS_OK
;
1101 return pmreg_access(env
, ri
, isread
);
1104 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1105 const ARMCPRegInfo
*ri
,
1108 /* SW: software increment write trap control */
1109 if (arm_feature(env
, ARM_FEATURE_V8
)
1110 && arm_current_el(env
) == 0
1111 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1113 return CP_ACCESS_OK
;
1116 return pmreg_access(env
, ri
, isread
);
1119 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1120 const ARMCPRegInfo
*ri
,
1123 /* ER: event counter read trap control */
1124 if (arm_feature(env
, ARM_FEATURE_V8
)
1125 && arm_current_el(env
) == 0
1126 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1127 return CP_ACCESS_OK
;
1130 return pmreg_access(env
, ri
, isread
);
1133 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1134 const ARMCPRegInfo
*ri
,
1137 /* CR: cycle counter read trap control */
1138 if (arm_feature(env
, ARM_FEATURE_V8
)
1139 && arm_current_el(env
) == 0
1140 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1142 return CP_ACCESS_OK
;
1145 return pmreg_access(env
, ri
, isread
);
1148 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1149 * the current EL, security state, and register configuration.
1151 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1154 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1155 bool enabled
, prohibited
, filtered
;
1156 bool secure
= arm_is_secure(env
);
1157 int el
= arm_current_el(env
);
1158 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1159 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1161 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1165 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1166 (counter
< hpmn
|| counter
== 31)) {
1167 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1169 e
= mdcr_el2
& MDCR_HPME
;
1171 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1174 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1175 prohibited
= mdcr_el2
& MDCR_HPMD
;
1180 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1181 !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1184 if (prohibited
&& counter
== 31) {
1185 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1188 if (counter
== 31) {
1189 filter
= env
->cp15
.pmccfiltr_el0
;
1191 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1194 p
= filter
& PMXEVTYPER_P
;
1195 u
= filter
& PMXEVTYPER_U
;
1196 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1197 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1198 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1199 m
= arm_el_is_aa64(env
, 1) &&
1200 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1203 filtered
= secure
? u
: u
!= nsu
;
1204 } else if (el
== 1) {
1205 filtered
= secure
? p
: p
!= nsk
;
1206 } else if (el
== 2) {
1212 if (counter
!= 31) {
1214 * If not checking PMCCNTR, ensure the counter is setup to an event we
1217 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1218 if (!event_supported(event
)) {
1223 return enabled
&& !prohibited
&& !filtered
;
1226 static void pmu_update_irq(CPUARMState
*env
)
1228 ARMCPU
*cpu
= env_archcpu(env
);
1229 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1230 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1234 * Ensure c15_ccnt is the guest-visible count so that operations such as
1235 * enabling/disabling the counter or filtering, modifying the count itself,
1236 * etc. can be done logically. This is essentially a no-op if the counter is
1237 * not enabled at the time of the call.
1239 static void pmccntr_op_start(CPUARMState
*env
)
1241 uint64_t cycles
= cycles_get_count(env
);
1243 if (pmu_counter_enabled(env
, 31)) {
1244 uint64_t eff_cycles
= cycles
;
1245 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1246 /* Increment once every 64 processor clock cycles */
1250 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1252 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1253 1ull << 63 : 1ull << 31;
1254 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1255 env
->cp15
.c9_pmovsr
|= (1 << 31);
1256 pmu_update_irq(env
);
1259 env
->cp15
.c15_ccnt
= new_pmccntr
;
1261 env
->cp15
.c15_ccnt_delta
= cycles
;
1265 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1266 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1269 static void pmccntr_op_finish(CPUARMState
*env
)
1271 if (pmu_counter_enabled(env
, 31)) {
1272 #ifndef CONFIG_USER_ONLY
1273 /* Calculate when the counter will next overflow */
1274 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1275 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1276 remaining_cycles
= (uint32_t)remaining_cycles
;
1278 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1280 if (overflow_in
> 0) {
1281 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1283 ARMCPU
*cpu
= env_archcpu(env
);
1284 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1288 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1289 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1290 /* Increment once every 64 processor clock cycles */
1293 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1297 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1300 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1302 if (event_supported(event
)) {
1303 uint16_t event_idx
= supported_event_map
[event
];
1304 count
= pm_events
[event_idx
].get_count(env
);
1307 if (pmu_counter_enabled(env
, counter
)) {
1308 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1310 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1311 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1312 pmu_update_irq(env
);
1314 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1316 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1319 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1321 if (pmu_counter_enabled(env
, counter
)) {
1322 #ifndef CONFIG_USER_ONLY
1323 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1324 uint16_t event_idx
= supported_event_map
[event
];
1325 uint64_t delta
= UINT32_MAX
-
1326 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1327 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1329 if (overflow_in
> 0) {
1330 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1332 ARMCPU
*cpu
= env_archcpu(env
);
1333 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1337 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1338 env
->cp15
.c14_pmevcntr
[counter
];
1342 void pmu_op_start(CPUARMState
*env
)
1345 pmccntr_op_start(env
);
1346 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1347 pmevcntr_op_start(env
, i
);
1351 void pmu_op_finish(CPUARMState
*env
)
1354 pmccntr_op_finish(env
);
1355 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1356 pmevcntr_op_finish(env
, i
);
1360 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1362 pmu_op_start(&cpu
->env
);
1365 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1367 pmu_op_finish(&cpu
->env
);
1370 void arm_pmu_timer_cb(void *opaque
)
1372 ARMCPU
*cpu
= opaque
;
1375 * Update all the counter values based on the current underlying counts,
1376 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1377 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1378 * counter may expire.
1380 pmu_op_start(&cpu
->env
);
1381 pmu_op_finish(&cpu
->env
);
1384 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1389 if (value
& PMCRC
) {
1390 /* The counter has been reset */
1391 env
->cp15
.c15_ccnt
= 0;
1394 if (value
& PMCRP
) {
1396 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1397 env
->cp15
.c14_pmevcntr
[i
] = 0;
1401 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1402 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1407 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1411 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1412 /* Increment a counter's count iff: */
1413 if ((value
& (1 << i
)) && /* counter's bit is set */
1414 /* counter is enabled and not filtered */
1415 pmu_counter_enabled(env
, i
) &&
1416 /* counter is SW_INCR */
1417 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1418 pmevcntr_op_start(env
, i
);
1421 * Detect if this write causes an overflow since we can't predict
1422 * PMSWINC overflows like we can for other events
1424 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1426 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1427 env
->cp15
.c9_pmovsr
|= (1 << i
);
1428 pmu_update_irq(env
);
1431 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1433 pmevcntr_op_finish(env
, i
);
1438 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1441 pmccntr_op_start(env
);
1442 ret
= env
->cp15
.c15_ccnt
;
1443 pmccntr_op_finish(env
);
1447 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1450 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1451 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1452 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1455 env
->cp15
.c9_pmselr
= value
& 0x1f;
1458 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1461 pmccntr_op_start(env
);
1462 env
->cp15
.c15_ccnt
= value
;
1463 pmccntr_op_finish(env
);
1466 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1469 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1471 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1474 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1477 pmccntr_op_start(env
);
1478 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1479 pmccntr_op_finish(env
);
1482 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1485 pmccntr_op_start(env
);
1486 /* M is not accessible from AArch32 */
1487 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1488 (value
& PMCCFILTR
);
1489 pmccntr_op_finish(env
);
1492 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1494 /* M is not visible in AArch32 */
1495 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1498 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1501 value
&= pmu_counter_mask(env
);
1502 env
->cp15
.c9_pmcnten
|= value
;
1505 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1508 value
&= pmu_counter_mask(env
);
1509 env
->cp15
.c9_pmcnten
&= ~value
;
1512 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1515 value
&= pmu_counter_mask(env
);
1516 env
->cp15
.c9_pmovsr
&= ~value
;
1517 pmu_update_irq(env
);
1520 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1523 value
&= pmu_counter_mask(env
);
1524 env
->cp15
.c9_pmovsr
|= value
;
1525 pmu_update_irq(env
);
1528 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1529 uint64_t value
, const uint8_t counter
)
1531 if (counter
== 31) {
1532 pmccfiltr_write(env
, ri
, value
);
1533 } else if (counter
< pmu_num_counters(env
)) {
1534 pmevcntr_op_start(env
, counter
);
1537 * If this counter's event type is changing, store the current
1538 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1539 * pmevcntr_op_finish has the correct baseline when it converts back to
1542 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1543 PMXEVTYPER_EVTCOUNT
;
1544 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1545 if (old_event
!= new_event
) {
1547 if (event_supported(new_event
)) {
1548 uint16_t event_idx
= supported_event_map
[new_event
];
1549 count
= pm_events
[event_idx
].get_count(env
);
1551 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1554 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1555 pmevcntr_op_finish(env
, counter
);
1557 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1558 * PMSELR value is equal to or greater than the number of implemented
1559 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1563 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1564 const uint8_t counter
)
1566 if (counter
== 31) {
1567 return env
->cp15
.pmccfiltr_el0
;
1568 } else if (counter
< pmu_num_counters(env
)) {
1569 return env
->cp15
.c14_pmevtyper
[counter
];
1572 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1573 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1579 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1582 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1583 pmevtyper_write(env
, ri
, value
, counter
);
1586 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1589 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1590 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1593 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1594 * pmu_op_finish calls when loading saved state for a migration. Because
1595 * we're potentially updating the type of event here, the value written to
1596 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1597 * different counter type. Therefore, we need to set this value to the
1598 * current count for the counter type we're writing so that pmu_op_finish
1599 * has the correct count for its calculation.
1601 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1602 if (event_supported(event
)) {
1603 uint16_t event_idx
= supported_event_map
[event
];
1604 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1605 pm_events
[event_idx
].get_count(env
);
1609 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1611 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1612 return pmevtyper_read(env
, ri
, counter
);
1615 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1618 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1621 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1623 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1626 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1627 uint64_t value
, uint8_t counter
)
1629 if (counter
< pmu_num_counters(env
)) {
1630 pmevcntr_op_start(env
, counter
);
1631 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1632 pmevcntr_op_finish(env
, counter
);
1635 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1636 * are CONSTRAINED UNPREDICTABLE.
1640 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1643 if (counter
< pmu_num_counters(env
)) {
1645 pmevcntr_op_start(env
, counter
);
1646 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1647 pmevcntr_op_finish(env
, counter
);
1650 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1651 * are CONSTRAINED UNPREDICTABLE. */
1656 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1659 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1660 pmevcntr_write(env
, ri
, value
, counter
);
1663 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1665 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1666 return pmevcntr_read(env
, ri
, counter
);
1669 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1672 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1673 assert(counter
< pmu_num_counters(env
));
1674 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1675 pmevcntr_write(env
, ri
, value
, counter
);
1678 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1680 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1681 assert(counter
< pmu_num_counters(env
));
1682 return env
->cp15
.c14_pmevcntr
[counter
];
1685 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1688 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1691 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1693 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1696 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1699 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1700 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1702 env
->cp15
.c9_pmuserenr
= value
& 1;
1706 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1709 /* We have no event counters so only the C bit can be changed */
1710 value
&= pmu_counter_mask(env
);
1711 env
->cp15
.c9_pminten
|= value
;
1712 pmu_update_irq(env
);
1715 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1718 value
&= pmu_counter_mask(env
);
1719 env
->cp15
.c9_pminten
&= ~value
;
1720 pmu_update_irq(env
);
1723 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1726 /* Note that even though the AArch64 view of this register has bits
1727 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1728 * architectural requirements for bits which are RES0 only in some
1729 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1730 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1732 raw_write(env
, ri
, value
& ~0x1FULL
);
1735 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1737 /* Begin with base v8.0 state. */
1738 uint32_t valid_mask
= 0x3fff;
1739 ARMCPU
*cpu
= env_archcpu(env
);
1742 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1743 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1744 * Instead, choose the format based on the mode of EL3.
1746 if (arm_el_is_aa64(env
, 3)) {
1747 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1748 valid_mask
&= ~SCR_NET
; /* RES0 */
1750 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1751 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1752 value
|= SCR_RW
; /* RAO/WI */
1754 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1755 valid_mask
|= SCR_TERR
;
1757 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1758 valid_mask
|= SCR_TLOR
;
1760 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1761 valid_mask
|= SCR_API
| SCR_APK
;
1763 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1764 valid_mask
|= SCR_EEL2
;
1766 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1767 valid_mask
|= SCR_ATA
;
1769 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1770 valid_mask
|= SCR_ENSCXT
;
1772 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1773 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1776 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1777 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1778 valid_mask
|= SCR_TERR
;
1782 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1783 valid_mask
&= ~SCR_HCE
;
1785 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1786 * supported if EL2 exists. The bit is UNK/SBZP when
1787 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1788 * when EL2 is unavailable.
1789 * On ARMv8, this bit is always available.
1791 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1792 !arm_feature(env
, ARM_FEATURE_V8
)) {
1793 valid_mask
&= ~SCR_SMD
;
1797 /* Clear all-context RES0 bits. */
1798 value
&= valid_mask
;
1799 raw_write(env
, ri
, value
);
1802 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1805 * scr_write will set the RES1 bits on an AArch64-only CPU.
1806 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1808 scr_write(env
, ri
, 0);
1811 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
1812 const ARMCPRegInfo
*ri
,
1815 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
1816 return CP_ACCESS_TRAP_EL2
;
1819 return CP_ACCESS_OK
;
1822 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1824 ARMCPU
*cpu
= env_archcpu(env
);
1826 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1829 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1830 ri
->secure
& ARM_CP_SECSTATE_S
);
1832 return cpu
->ccsidr
[index
];
1835 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1838 raw_write(env
, ri
, value
& 0xf);
1841 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1843 CPUState
*cs
= env_cpu(env
);
1844 bool el1
= arm_current_el(env
) == 1;
1845 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1848 if (hcr_el2
& HCR_IMO
) {
1849 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1853 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1858 if (hcr_el2
& HCR_FMO
) {
1859 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1863 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1868 if (hcr_el2
& HCR_AMO
) {
1869 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
1877 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1880 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
1881 return CP_ACCESS_TRAP_EL2
;
1884 return CP_ACCESS_OK
;
1887 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1890 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1891 return access_aa64_tid1(env
, ri
, isread
);
1894 return CP_ACCESS_OK
;
1897 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1898 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1899 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1900 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1901 /* Performance monitors are implementation defined in v7,
1902 * but with an ARM recommended set of registers, which we
1905 * Performance registers fall into three categories:
1906 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1907 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1908 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1909 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1910 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1912 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1913 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1914 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1915 .writefn
= pmcntenset_write
,
1916 .accessfn
= pmreg_access
,
1917 .raw_writefn
= raw_write
},
1918 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1919 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1920 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1921 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1922 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1923 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1925 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1926 .accessfn
= pmreg_access
,
1927 .writefn
= pmcntenclr_write
,
1928 .type
= ARM_CP_ALIAS
},
1929 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1930 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1931 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1932 .type
= ARM_CP_ALIAS
,
1933 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1934 .writefn
= pmcntenclr_write
},
1935 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1936 .access
= PL0_RW
, .type
= ARM_CP_IO
,
1937 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
1938 .accessfn
= pmreg_access
,
1939 .writefn
= pmovsr_write
,
1940 .raw_writefn
= raw_write
},
1941 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1942 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1943 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1944 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1945 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1946 .writefn
= pmovsr_write
,
1947 .raw_writefn
= raw_write
},
1948 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1949 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1950 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1951 .writefn
= pmswinc_write
},
1952 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
1953 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
1954 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
1955 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1956 .writefn
= pmswinc_write
},
1957 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1958 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1959 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1960 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1961 .raw_writefn
= raw_write
},
1962 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1963 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1964 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1965 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1966 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1967 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1968 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1969 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1970 .accessfn
= pmreg_access_ccntr
},
1971 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1972 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1973 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1975 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
1976 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
1977 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
1978 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
1979 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
1980 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1981 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
1983 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1984 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1985 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
1986 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1988 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1990 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1991 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1992 .accessfn
= pmreg_access
,
1993 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1994 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1995 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1996 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
1997 .accessfn
= pmreg_access
,
1998 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1999 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2000 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2001 .accessfn
= pmreg_access_xevcntr
,
2002 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2003 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2004 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2005 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2006 .accessfn
= pmreg_access_xevcntr
,
2007 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2008 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2009 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2010 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2012 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2013 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2014 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2015 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2016 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2018 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2019 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2020 .access
= PL1_RW
, .accessfn
= access_tpm
,
2021 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2022 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2024 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2025 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2026 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2027 .access
= PL1_RW
, .accessfn
= access_tpm
,
2029 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2030 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2031 .resetvalue
= 0x0 },
2032 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2033 .access
= PL1_RW
, .accessfn
= access_tpm
,
2034 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2035 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2036 .writefn
= pmintenclr_write
, },
2037 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2038 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2039 .access
= PL1_RW
, .accessfn
= access_tpm
,
2040 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2041 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2042 .writefn
= pmintenclr_write
},
2043 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2044 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2046 .accessfn
= access_aa64_tid2
,
2047 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2048 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2049 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2051 .accessfn
= access_aa64_tid2
,
2052 .writefn
= csselr_write
, .resetvalue
= 0,
2053 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2054 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2055 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2056 * just RAZ for all cores:
2058 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2059 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2060 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2061 .accessfn
= access_aa64_tid1
,
2063 /* Auxiliary fault status registers: these also are IMPDEF, and we
2064 * choose to RAZ/WI for all cores.
2066 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2067 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2068 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2069 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2070 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2071 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2072 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2073 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2074 /* MAIR can just read-as-written because we don't implement caches
2075 * and so don't need to care about memory attributes.
2077 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2078 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2079 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2080 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2082 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2083 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2084 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2086 /* For non-long-descriptor page tables these are PRRR and NMRR;
2087 * regardless they still act as reads-as-written for QEMU.
2089 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2090 * allows them to assign the correct fieldoffset based on the endianness
2091 * handled in the field definitions.
2093 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2094 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2095 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2096 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2097 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2098 .resetfn
= arm_cp_reset_ignore
},
2099 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2100 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2101 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2102 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2103 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2104 .resetfn
= arm_cp_reset_ignore
},
2105 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2106 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2107 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2108 /* 32 bit ITLB invalidates */
2109 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2110 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2111 .writefn
= tlbiall_write
},
2112 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2113 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2114 .writefn
= tlbimva_write
},
2115 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2116 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2117 .writefn
= tlbiasid_write
},
2118 /* 32 bit DTLB invalidates */
2119 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2120 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2121 .writefn
= tlbiall_write
},
2122 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2123 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2124 .writefn
= tlbimva_write
},
2125 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2126 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2127 .writefn
= tlbiasid_write
},
2128 /* 32 bit TLB invalidates */
2129 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2130 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2131 .writefn
= tlbiall_write
},
2132 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2133 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2134 .writefn
= tlbimva_write
},
2135 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2136 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2137 .writefn
= tlbiasid_write
},
2138 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2139 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2140 .writefn
= tlbimvaa_write
},
2143 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2144 /* 32 bit TLB invalidates, Inner Shareable */
2145 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2146 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2147 .writefn
= tlbiall_is_write
},
2148 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2149 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2150 .writefn
= tlbimva_is_write
},
2151 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2152 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2153 .writefn
= tlbiasid_is_write
},
2154 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2155 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2156 .writefn
= tlbimvaa_is_write
},
2159 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2160 /* PMOVSSET is not implemented in v7 before v7ve */
2161 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2162 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2163 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2164 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2165 .writefn
= pmovsset_write
,
2166 .raw_writefn
= raw_write
},
2167 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2168 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2169 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2170 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2171 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2172 .writefn
= pmovsset_write
,
2173 .raw_writefn
= raw_write
},
2176 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2183 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2187 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2188 * at all, so we don't need to check whether we're v8A.
2190 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2191 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2192 return CP_ACCESS_TRAP_EL2
;
2194 return CP_ACCESS_OK
;
2197 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2200 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2201 return CP_ACCESS_TRAP
;
2203 return teecr_access(env
, ri
, isread
);
2206 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2207 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2208 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2210 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2211 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2212 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2213 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2216 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2217 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2218 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2220 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2221 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2223 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2224 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2225 .resetfn
= arm_cp_reset_ignore
},
2226 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2227 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2228 .access
= PL0_R
|PL1_W
,
2229 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2231 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2232 .access
= PL0_R
|PL1_W
,
2233 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2234 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2235 .resetfn
= arm_cp_reset_ignore
},
2236 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2237 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2239 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2240 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2242 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2243 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2247 #ifndef CONFIG_USER_ONLY
2249 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2252 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2253 * Writable only at the highest implemented exception level.
2255 int el
= arm_current_el(env
);
2261 hcr
= arm_hcr_el2_eff(env
);
2262 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2263 cntkctl
= env
->cp15
.cnthctl_el2
;
2265 cntkctl
= env
->cp15
.c14_cntkctl
;
2267 if (!extract32(cntkctl
, 0, 2)) {
2268 return CP_ACCESS_TRAP
;
2272 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2273 arm_is_secure_below_el3(env
)) {
2274 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2275 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2283 if (!isread
&& el
< arm_highest_el(env
)) {
2284 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2287 return CP_ACCESS_OK
;
2290 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2293 unsigned int cur_el
= arm_current_el(env
);
2294 bool has_el2
= arm_is_el2_enabled(env
);
2295 uint64_t hcr
= arm_hcr_el2_eff(env
);
2299 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2300 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2301 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2302 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2305 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2306 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2307 return CP_ACCESS_TRAP
;
2310 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2311 if (hcr
& HCR_E2H
) {
2312 if (timeridx
== GTIMER_PHYS
&&
2313 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2314 return CP_ACCESS_TRAP_EL2
;
2317 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2318 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2319 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2320 return CP_ACCESS_TRAP_EL2
;
2326 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2327 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2329 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2330 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2331 return CP_ACCESS_TRAP_EL2
;
2335 return CP_ACCESS_OK
;
2338 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2341 unsigned int cur_el
= arm_current_el(env
);
2342 bool has_el2
= arm_is_el2_enabled(env
);
2343 uint64_t hcr
= arm_hcr_el2_eff(env
);
2347 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2348 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2349 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2350 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2354 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2355 * EL0 if EL0[PV]TEN is zero.
2357 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2358 return CP_ACCESS_TRAP
;
2363 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2364 if (hcr
& HCR_E2H
) {
2365 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2366 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2367 return CP_ACCESS_TRAP_EL2
;
2370 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2371 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2372 return CP_ACCESS_TRAP_EL2
;
2378 return CP_ACCESS_OK
;
2381 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2382 const ARMCPRegInfo
*ri
,
2385 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2388 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2389 const ARMCPRegInfo
*ri
,
2392 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2395 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2398 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2401 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2404 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2407 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2408 const ARMCPRegInfo
*ri
,
2411 /* The AArch64 register view of the secure physical timer is
2412 * always accessible from EL3, and configurably accessible from
2415 switch (arm_current_el(env
)) {
2417 if (!arm_is_secure(env
)) {
2418 return CP_ACCESS_TRAP
;
2420 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2421 return CP_ACCESS_TRAP_EL3
;
2423 return CP_ACCESS_OK
;
2426 return CP_ACCESS_TRAP
;
2428 return CP_ACCESS_OK
;
2430 g_assert_not_reached();
2434 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2436 ARMCPU
*cpu
= env_archcpu(env
);
2438 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2441 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2443 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2446 /* Timer enabled: calculate and set current ISTATUS, irq, and
2447 * reset timer to when ISTATUS next has to change
2449 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2450 cpu
->env
.cp15
.cntvoff_el2
: 0;
2451 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2452 /* Note that this must be unsigned 64 bit arithmetic: */
2453 int istatus
= count
- offset
>= gt
->cval
;
2457 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2459 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2460 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2463 /* Next transition is when count rolls back over to zero */
2464 nexttick
= UINT64_MAX
;
2466 /* Next transition is when we hit cval */
2467 nexttick
= gt
->cval
+ offset
;
2469 /* Note that the desired next expiry time might be beyond the
2470 * signed-64-bit range of a QEMUTimer -- in this case we just
2471 * set the timer for as far in the future as possible. When the
2472 * timer expires we will reset the timer for any remaining period.
2474 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2475 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2477 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2479 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2481 /* Timer disabled: ISTATUS and timer output always clear */
2483 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2484 timer_del(cpu
->gt_timer
[timeridx
]);
2485 trace_arm_gt_recalc_disabled(timeridx
);
2489 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2492 ARMCPU
*cpu
= env_archcpu(env
);
2494 timer_del(cpu
->gt_timer
[timeridx
]);
2497 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2499 return gt_get_countervalue(env
);
2502 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2506 switch (arm_current_el(env
)) {
2508 hcr
= arm_hcr_el2_eff(env
);
2509 if (hcr
& HCR_E2H
) {
2514 hcr
= arm_hcr_el2_eff(env
);
2515 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2521 return env
->cp15
.cntvoff_el2
;
2524 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2526 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2529 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2533 trace_arm_gt_cval_write(timeridx
, value
);
2534 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2535 gt_recalc_timer(env_archcpu(env
), timeridx
);
2538 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2541 uint64_t offset
= 0;
2545 case GTIMER_HYPVIRT
:
2546 offset
= gt_virt_cnt_offset(env
);
2550 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2551 (gt_get_countervalue(env
) - offset
));
2554 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2558 uint64_t offset
= 0;
2562 case GTIMER_HYPVIRT
:
2563 offset
= gt_virt_cnt_offset(env
);
2567 trace_arm_gt_tval_write(timeridx
, value
);
2568 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2569 sextract64(value
, 0, 32);
2570 gt_recalc_timer(env_archcpu(env
), timeridx
);
2573 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2577 ARMCPU
*cpu
= env_archcpu(env
);
2578 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2580 trace_arm_gt_ctl_write(timeridx
, value
);
2581 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2582 if ((oldval
^ value
) & 1) {
2583 /* Enable toggled */
2584 gt_recalc_timer(cpu
, timeridx
);
2585 } else if ((oldval
^ value
) & 2) {
2586 /* IMASK toggled: don't need to recalculate,
2587 * just set the interrupt line based on ISTATUS
2589 int irqstate
= (oldval
& 4) && !(value
& 2);
2591 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2592 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2596 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2598 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2601 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2604 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2607 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2609 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2612 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2615 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2618 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2621 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2624 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2626 switch (arm_mmu_idx(env
)) {
2627 case ARMMMUIdx_E20_0
:
2628 case ARMMMUIdx_E20_2
:
2629 case ARMMMUIdx_E20_2_PAN
:
2630 case ARMMMUIdx_SE20_0
:
2631 case ARMMMUIdx_SE20_2
:
2632 case ARMMMUIdx_SE20_2_PAN
:
2639 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2641 switch (arm_mmu_idx(env
)) {
2642 case ARMMMUIdx_E20_0
:
2643 case ARMMMUIdx_E20_2
:
2644 case ARMMMUIdx_E20_2_PAN
:
2645 case ARMMMUIdx_SE20_0
:
2646 case ARMMMUIdx_SE20_2
:
2647 case ARMMMUIdx_SE20_2_PAN
:
2648 return GTIMER_HYPVIRT
;
2654 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2655 const ARMCPRegInfo
*ri
)
2657 int timeridx
= gt_phys_redir_timeridx(env
);
2658 return env
->cp15
.c14_timer
[timeridx
].cval
;
2661 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2664 int timeridx
= gt_phys_redir_timeridx(env
);
2665 gt_cval_write(env
, ri
, timeridx
, value
);
2668 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2669 const ARMCPRegInfo
*ri
)
2671 int timeridx
= gt_phys_redir_timeridx(env
);
2672 return gt_tval_read(env
, ri
, timeridx
);
2675 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2678 int timeridx
= gt_phys_redir_timeridx(env
);
2679 gt_tval_write(env
, ri
, timeridx
, value
);
2682 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2683 const ARMCPRegInfo
*ri
)
2685 int timeridx
= gt_phys_redir_timeridx(env
);
2686 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2689 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2692 int timeridx
= gt_phys_redir_timeridx(env
);
2693 gt_ctl_write(env
, ri
, timeridx
, value
);
2696 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2698 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2701 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2704 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2707 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2709 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2712 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2715 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2718 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2721 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2724 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2727 ARMCPU
*cpu
= env_archcpu(env
);
2729 trace_arm_gt_cntvoff_write(value
);
2730 raw_write(env
, ri
, value
);
2731 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2734 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2735 const ARMCPRegInfo
*ri
)
2737 int timeridx
= gt_virt_redir_timeridx(env
);
2738 return env
->cp15
.c14_timer
[timeridx
].cval
;
2741 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2744 int timeridx
= gt_virt_redir_timeridx(env
);
2745 gt_cval_write(env
, ri
, timeridx
, value
);
2748 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2749 const ARMCPRegInfo
*ri
)
2751 int timeridx
= gt_virt_redir_timeridx(env
);
2752 return gt_tval_read(env
, ri
, timeridx
);
2755 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2758 int timeridx
= gt_virt_redir_timeridx(env
);
2759 gt_tval_write(env
, ri
, timeridx
, value
);
2762 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2763 const ARMCPRegInfo
*ri
)
2765 int timeridx
= gt_virt_redir_timeridx(env
);
2766 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2769 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2772 int timeridx
= gt_virt_redir_timeridx(env
);
2773 gt_ctl_write(env
, ri
, timeridx
, value
);
2776 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2778 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2781 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2784 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2787 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2789 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2792 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2795 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2798 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2801 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2804 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2806 gt_timer_reset(env
, ri
, GTIMER_SEC
);
2809 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2812 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
2815 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2817 return gt_tval_read(env
, ri
, GTIMER_SEC
);
2820 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2823 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
2826 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2829 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
2832 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2834 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
2837 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2840 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2843 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2845 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
2848 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2851 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2854 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2857 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
2860 void arm_gt_ptimer_cb(void *opaque
)
2862 ARMCPU
*cpu
= opaque
;
2864 gt_recalc_timer(cpu
, GTIMER_PHYS
);
2867 void arm_gt_vtimer_cb(void *opaque
)
2869 ARMCPU
*cpu
= opaque
;
2871 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2874 void arm_gt_htimer_cb(void *opaque
)
2876 ARMCPU
*cpu
= opaque
;
2878 gt_recalc_timer(cpu
, GTIMER_HYP
);
2881 void arm_gt_stimer_cb(void *opaque
)
2883 ARMCPU
*cpu
= opaque
;
2885 gt_recalc_timer(cpu
, GTIMER_SEC
);
2888 void arm_gt_hvtimer_cb(void *opaque
)
2890 ARMCPU
*cpu
= opaque
;
2892 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
2895 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2897 ARMCPU
*cpu
= env_archcpu(env
);
2899 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
2902 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2903 /* Note that CNTFRQ is purely reads-as-written for the benefit
2904 * of software; writing it doesn't actually change the timer frequency.
2905 * Our reset value matches the fixed frequency we implement the timer at.
2907 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
2908 .type
= ARM_CP_ALIAS
,
2909 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2910 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
2912 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
2913 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
2914 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
2915 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
2916 .resetfn
= arm_gt_cntfrq_reset
,
2918 /* overall control: mostly access permissions */
2919 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
2920 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
2922 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
2925 /* per-timer control */
2926 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2927 .secure
= ARM_CP_SECSTATE_NS
,
2928 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2929 .accessfn
= gt_ptimer_access
,
2930 .fieldoffset
= offsetoflow32(CPUARMState
,
2931 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2932 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2933 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2935 { .name
= "CNTP_CTL_S",
2936 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
2937 .secure
= ARM_CP_SECSTATE_S
,
2938 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2939 .accessfn
= gt_ptimer_access
,
2940 .fieldoffset
= offsetoflow32(CPUARMState
,
2941 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2942 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2944 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2945 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
2946 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2947 .accessfn
= gt_ptimer_access
,
2948 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
2950 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
2951 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
2953 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
2954 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
2955 .accessfn
= gt_vtimer_access
,
2956 .fieldoffset
= offsetoflow32(CPUARMState
,
2957 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2958 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2959 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2961 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
2962 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
2963 .type
= ARM_CP_IO
, .access
= PL0_RW
,
2964 .accessfn
= gt_vtimer_access
,
2965 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
2967 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
2968 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
2970 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2971 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2972 .secure
= ARM_CP_SECSTATE_NS
,
2973 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2974 .accessfn
= gt_ptimer_access
,
2975 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2977 { .name
= "CNTP_TVAL_S",
2978 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2979 .secure
= ARM_CP_SECSTATE_S
,
2980 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2981 .accessfn
= gt_ptimer_access
,
2982 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2984 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2985 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2986 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2987 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2988 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
2990 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2991 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2992 .accessfn
= gt_vtimer_access
,
2993 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
2995 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2996 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2997 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
2998 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2999 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3001 /* The counter itself */
3002 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3003 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3004 .accessfn
= gt_pct_access
,
3005 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3007 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3008 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3009 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3010 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3012 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3013 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3014 .accessfn
= gt_vct_access
,
3015 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3017 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3018 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3019 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3020 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3022 /* Comparison value, indicating when the timer goes off */
3023 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3024 .secure
= ARM_CP_SECSTATE_NS
,
3026 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3027 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3028 .accessfn
= gt_ptimer_access
,
3029 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3030 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3032 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3033 .secure
= ARM_CP_SECSTATE_S
,
3035 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3036 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3037 .accessfn
= gt_ptimer_access
,
3038 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3040 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3041 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3045 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3046 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3047 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3049 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3051 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3052 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3053 .accessfn
= gt_vtimer_access
,
3054 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3055 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3057 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3058 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3061 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3062 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3063 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3064 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3066 /* Secure timer -- this is actually restricted to only EL3
3067 * and configurably Secure-EL1 via the accessfn.
3069 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3070 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3071 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3072 .accessfn
= gt_stimer_access
,
3073 .readfn
= gt_sec_tval_read
,
3074 .writefn
= gt_sec_tval_write
,
3075 .resetfn
= gt_sec_timer_reset
,
3077 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3078 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3079 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3080 .accessfn
= gt_stimer_access
,
3081 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3083 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3085 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3086 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3087 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3088 .accessfn
= gt_stimer_access
,
3089 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3090 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3094 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3097 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3098 return CP_ACCESS_TRAP
;
3100 return CP_ACCESS_OK
;
3105 /* In user-mode most of the generic timer registers are inaccessible
3106 * however modern kernels (4.12+) allow access to cntvct_el0
3109 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3111 ARMCPU
*cpu
= env_archcpu(env
);
3113 /* Currently we have no support for QEMUTimer in linux-user so we
3114 * can't call gt_get_countervalue(env), instead we directly
3115 * call the lower level functions.
3117 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3120 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3121 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3122 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3123 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3124 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3125 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3127 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3128 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3129 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3130 .readfn
= gt_virt_cnt_read
,
3136 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3138 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3139 raw_write(env
, ri
, value
);
3140 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3141 raw_write(env
, ri
, value
& 0xfffff6ff);
3143 raw_write(env
, ri
, value
& 0xfffff1ff);
3147 #ifndef CONFIG_USER_ONLY
3148 /* get_phys_addr() isn't present for user-mode-only targets */
3150 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3154 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3155 * Secure EL1 (which can only happen if EL3 is AArch64).
3156 * They are simply UNDEF if executed from NS EL1.
3157 * They function normally from EL2 or EL3.
3159 if (arm_current_el(env
) == 1) {
3160 if (arm_is_secure_below_el3(env
)) {
3161 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3162 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2
;
3164 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3166 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3169 return CP_ACCESS_OK
;
3173 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3174 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3177 target_ulong page_size
;
3181 bool format64
= false;
3182 MemTxAttrs attrs
= {};
3183 ARMMMUFaultInfo fi
= {};
3184 ARMCacheAttrs cacheattrs
= {};
3186 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3187 &prot
, &page_size
, &fi
, &cacheattrs
);
3190 * ATS operations only do S1 or S1+S2 translations, so we never
3191 * have to deal with the ARMCacheAttrs format for S2 only.
3193 assert(!cacheattrs
.is_s2_format
);
3197 * Some kinds of translation fault must cause exceptions rather
3198 * than being reported in the PAR.
3200 int current_el
= arm_current_el(env
);
3202 uint32_t syn
, fsr
, fsc
;
3203 bool take_exc
= false;
3205 if (fi
.s1ptw
&& current_el
== 1
3206 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3208 * Synchronous stage 2 fault on an access made as part of the
3209 * translation table walk for AT S1E0* or AT S1E1* insn
3210 * executed from NS EL1. If this is a synchronous external abort
3211 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3212 * to EL3. Otherwise the fault is taken as an exception to EL2,
3213 * and HPFAR_EL2 holds the faulting IPA.
3215 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3216 (env
->cp15
.scr_el3
& SCR_EA
)) {
3219 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3220 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3221 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3226 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3228 * Synchronous external aborts during a translation table walk
3229 * are taken as Data Abort exceptions.
3232 if (current_el
== 3) {
3238 target_el
= exception_target_el(env
);
3244 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3245 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3246 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3247 fsr
= arm_fi_to_lfsc(&fi
);
3248 fsc
= extract32(fsr
, 0, 6);
3250 fsr
= arm_fi_to_sfsc(&fi
);
3254 * Report exception with ESR indicating a fault due to a
3255 * translation table walk for a cache maintenance instruction.
3257 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3258 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3259 env
->exception
.vaddress
= value
;
3260 env
->exception
.fsr
= fsr
;
3261 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3267 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3270 * * TTBCR.EAE determines whether the result is returned using the
3271 * 32-bit or the 64-bit PAR format
3272 * * Instructions executed in Hyp mode always use the 64bit format
3274 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3275 * * The Non-secure TTBCR.EAE bit is set to 1
3276 * * The implementation includes EL2, and the value of HCR.VM is 1
3278 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3280 * ATS1Hx always uses the 64bit format.
3282 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3284 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3285 if (mmu_idx
== ARMMMUIdx_E10_0
||
3286 mmu_idx
== ARMMMUIdx_E10_1
||
3287 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3288 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3290 format64
|= arm_current_el(env
) == 2;
3296 /* Create a 64-bit PAR */
3297 par64
= (1 << 11); /* LPAE bit always set */
3299 par64
|= phys_addr
& ~0xfffULL
;
3300 if (!attrs
.secure
) {
3301 par64
|= (1 << 9); /* NS */
3303 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3304 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3306 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3309 par64
|= (fsr
& 0x3f) << 1; /* FS */
3311 par64
|= (1 << 9); /* S */
3314 par64
|= (1 << 8); /* PTW */
3318 /* fsr is a DFSR/IFSR value for the short descriptor
3319 * translation table format (with WnR always clear).
3320 * Convert it to a 32-bit PAR.
3323 /* We do not set any attribute bits in the PAR */
3324 if (page_size
== (1 << 24)
3325 && arm_feature(env
, ARM_FEATURE_V7
)) {
3326 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3328 par64
= phys_addr
& 0xfffff000;
3330 if (!attrs
.secure
) {
3331 par64
|= (1 << 9); /* NS */
3334 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3336 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3337 ((fsr
& 0xf) << 1) | 1;
3342 #endif /* CONFIG_TCG */
3344 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3347 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3350 int el
= arm_current_el(env
);
3351 bool secure
= arm_is_secure_below_el3(env
);
3353 switch (ri
->opc2
& 6) {
3355 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3358 mmu_idx
= ARMMMUIdx_SE3
;
3361 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3364 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3365 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3366 : ARMMMUIdx_Stage1_E1_PAN
);
3368 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3372 g_assert_not_reached();
3376 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3379 mmu_idx
= ARMMMUIdx_SE10_0
;
3382 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3383 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3386 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3389 g_assert_not_reached();
3393 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3394 mmu_idx
= ARMMMUIdx_E10_1
;
3397 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3398 mmu_idx
= ARMMMUIdx_E10_0
;
3401 g_assert_not_reached();
3404 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3406 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3408 /* Handled by hardware accelerator. */
3409 g_assert_not_reached();
3410 #endif /* CONFIG_TCG */
3413 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3417 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3420 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3422 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3424 /* Handled by hardware accelerator. */
3425 g_assert_not_reached();
3426 #endif /* CONFIG_TCG */
3429 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3432 if (arm_current_el(env
) == 3 &&
3433 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3434 return CP_ACCESS_TRAP
;
3436 return CP_ACCESS_OK
;
3439 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3443 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3445 int secure
= arm_is_secure_below_el3(env
);
3447 switch (ri
->opc2
& 6) {
3450 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3451 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3452 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3453 : ARMMMUIdx_Stage1_E1_PAN
);
3455 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3458 case 4: /* AT S1E2R, AT S1E2W */
3459 mmu_idx
= secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
;
3461 case 6: /* AT S1E3R, AT S1E3W */
3462 mmu_idx
= ARMMMUIdx_SE3
;
3465 g_assert_not_reached();
3468 case 2: /* AT S1E0R, AT S1E0W */
3469 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3471 case 4: /* AT S12E1R, AT S12E1W */
3472 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3474 case 6: /* AT S12E0R, AT S12E0W */
3475 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3478 g_assert_not_reached();
3481 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3483 /* Handled by hardware accelerator. */
3484 g_assert_not_reached();
3485 #endif /* CONFIG_TCG */
3489 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3490 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3491 .access
= PL1_RW
, .resetvalue
= 0,
3492 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3493 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3494 .writefn
= par_write
},
3495 #ifndef CONFIG_USER_ONLY
3496 /* This underdecoding is safe because the reginfo is NO_RAW. */
3497 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3498 .access
= PL1_W
, .accessfn
= ats_access
,
3499 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3503 /* Return basic MPU access permission bits. */
3504 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3511 for (i
= 0; i
< 16; i
+= 2) {
3512 ret
|= (val
>> i
) & mask
;
3518 /* Pad basic MPU access permission bits to extended format. */
3519 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3526 for (i
= 0; i
< 16; i
+= 2) {
3527 ret
|= (val
& mask
) << i
;
3533 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3536 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3539 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3541 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3544 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3547 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3550 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3552 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3555 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3557 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3563 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3567 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3570 ARMCPU
*cpu
= env_archcpu(env
);
3571 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3577 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3578 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3582 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3585 ARMCPU
*cpu
= env_archcpu(env
);
3586 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3588 if (value
>= nrgs
) {
3589 qemu_log_mask(LOG_GUEST_ERROR
,
3590 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3591 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3595 raw_write(env
, ri
, value
);
3598 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3599 /* Reset for all these registers is handled in arm_cpu_reset(),
3600 * because the PMSAv7 is also used by M-profile CPUs, which do
3601 * not register cpregs but still need the state to be reset.
3603 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3604 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3605 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3606 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3607 .resetfn
= arm_cp_reset_ignore
},
3608 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3609 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3610 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3611 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3612 .resetfn
= arm_cp_reset_ignore
},
3613 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3614 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3615 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3616 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3617 .resetfn
= arm_cp_reset_ignore
},
3618 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3620 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3621 .writefn
= pmsav7_rgnr_write
,
3622 .resetfn
= arm_cp_reset_ignore
},
3625 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3626 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3627 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3628 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3629 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3630 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3631 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3632 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3633 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3634 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3636 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3638 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3640 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3642 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3644 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3645 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3647 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3648 /* Protection region base and size registers */
3649 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3650 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3651 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3652 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3653 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3654 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3655 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3656 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3657 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3658 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3659 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3660 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3661 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3662 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3663 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3664 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3665 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3666 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3667 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3668 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3669 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3670 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3671 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3672 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3675 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3678 TCR
*tcr
= raw_ptr(env
, ri
);
3679 int maskshift
= extract32(value
, 0, 3);
3681 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3682 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3683 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3684 * using Long-desciptor translation table format */
3685 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3686 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3687 /* In an implementation that includes the Security Extensions
3688 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3689 * Short-descriptor translation table format.
3691 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3697 /* Update the masks corresponding to the TCR bank being written
3698 * Note that we always calculate mask and base_mask, but
3699 * they are only used for short-descriptor tables (ie if EAE is 0);
3700 * for long-descriptor tables the TCR fields are used differently
3701 * and the mask and base_mask values are meaningless.
3703 tcr
->raw_tcr
= value
;
3704 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3705 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3708 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3711 ARMCPU
*cpu
= env_archcpu(env
);
3712 TCR
*tcr
= raw_ptr(env
, ri
);
3714 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3715 /* With LPAE the TTBCR could result in a change of ASID
3716 * via the TTBCR.A1 bit, so do a TLB flush.
3718 tlb_flush(CPU(cpu
));
3720 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3721 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3722 vmsa_ttbcr_raw_write(env
, ri
, value
);
3725 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3727 TCR
*tcr
= raw_ptr(env
, ri
);
3729 /* Reset both the TCR as well as the masks corresponding to the bank of
3730 * the TCR being reset.
3734 tcr
->base_mask
= 0xffffc000u
;
3737 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3740 ARMCPU
*cpu
= env_archcpu(env
);
3741 TCR
*tcr
= raw_ptr(env
, ri
);
3743 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3744 tlb_flush(CPU(cpu
));
3745 tcr
->raw_tcr
= value
;
3748 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3751 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3752 if (cpreg_field_is_64bit(ri
) &&
3753 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3754 ARMCPU
*cpu
= env_archcpu(env
);
3755 tlb_flush(CPU(cpu
));
3757 raw_write(env
, ri
, value
);
3760 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3764 * If we are running with E2&0 regime, then an ASID is active.
3765 * Flush if that might be changing. Note we're not checking
3766 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3767 * holds the active ASID, only checking the field that might.
3769 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
3770 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3771 uint16_t mask
= ARMMMUIdxBit_E20_2
|
3772 ARMMMUIdxBit_E20_2_PAN
|
3775 if (arm_is_secure_below_el3(env
)) {
3776 mask
>>= ARM_MMU_IDX_A_NS
;
3779 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
3781 raw_write(env
, ri
, value
);
3784 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3787 ARMCPU
*cpu
= env_archcpu(env
);
3788 CPUState
*cs
= CPU(cpu
);
3791 * A change in VMID to the stage2 page table (Stage2) invalidates
3792 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
3794 if (raw_read(env
, ri
) != value
) {
3795 uint16_t mask
= ARMMMUIdxBit_E10_1
|
3796 ARMMMUIdxBit_E10_1_PAN
|
3799 if (arm_is_secure_below_el3(env
)) {
3800 mask
>>= ARM_MMU_IDX_A_NS
;
3803 tlb_flush_by_mmuidx(cs
, mask
);
3804 raw_write(env
, ri
, value
);
3808 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
3809 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3810 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
3811 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
3812 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
3813 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3814 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3815 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
3816 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
3817 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
3818 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
3819 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
3820 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
3821 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
3822 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
3823 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3824 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
3828 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
3829 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
3830 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
3831 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3832 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
3833 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
3834 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
3835 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3836 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3837 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
3838 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
3839 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
3840 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
3841 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3842 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
3843 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
3844 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
3845 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
3846 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3847 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3848 .writefn
= vmsa_tcr_el12_write
,
3849 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
3850 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
3851 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
3852 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3853 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
3854 .raw_writefn
= vmsa_ttbcr_raw_write
,
3855 /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
3856 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.tcr_el
[3]),
3857 offsetof(CPUARMState
, cp15
.tcr_el
[1])} },
3860 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
3861 * qemu tlbs nor adjusting cached masks.
3863 static const ARMCPRegInfo ttbcr2_reginfo
= {
3864 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
3865 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
3866 .type
= ARM_CP_ALIAS
,
3867 .bank_fieldoffsets
= {
3868 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3].raw_tcr
),
3869 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1].raw_tcr
),
3873 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3876 env
->cp15
.c15_ticonfig
= value
& 0xe7;
3877 /* The OS_TYPE bit in this register changes the reported CPUID! */
3878 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
3879 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
3882 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3885 env
->cp15
.c15_threadid
= value
& 0xffff;
3888 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3891 /* Wait-for-interrupt (deprecated) */
3892 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
3895 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3898 /* On OMAP there are registers indicating the max/min index of dcache lines
3899 * containing a dirty line; cache flush operations have to reset these.
3901 env
->cp15
.c15_i_max
= 0x000;
3902 env
->cp15
.c15_i_min
= 0xff0;
3905 static const ARMCPRegInfo omap_cp_reginfo
[] = {
3906 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
3907 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
3908 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
3910 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
3911 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3912 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
3914 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
3915 .writefn
= omap_ticonfig_write
},
3916 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
3918 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
3919 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
3920 .access
= PL1_RW
, .resetvalue
= 0xff0,
3921 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
3922 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
3924 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
3925 .writefn
= omap_threadid_write
},
3926 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
3927 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3928 .type
= ARM_CP_NO_RAW
,
3929 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
3930 /* TODO: Peripheral port remap register:
3931 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
3932 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
3935 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
3936 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
3937 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
3938 .writefn
= omap_cachemaint_write
},
3939 { .name
= "C9", .cp
= 15, .crn
= 9,
3940 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
3941 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
3944 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3947 env
->cp15
.c15_cpar
= value
& 0x3fff;
3950 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
3951 { .name
= "XSCALE_CPAR",
3952 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
3953 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
3954 .writefn
= xscale_cpar_write
, },
3955 { .name
= "XSCALE_AUXCR",
3956 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
3957 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
3959 /* XScale specific cache-lockdown: since we have no cache we NOP these
3960 * and hope the guest does not really rely on cache behaviour.
3962 { .name
= "XSCALE_LOCK_ICACHE_LINE",
3963 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
3964 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3965 { .name
= "XSCALE_UNLOCK_ICACHE",
3966 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
3967 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3968 { .name
= "XSCALE_DCACHE_LOCK",
3969 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
3970 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
3971 { .name
= "XSCALE_UNLOCK_DCACHE",
3972 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
3973 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3976 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
3977 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
3978 * implementation of this implementation-defined space.
3979 * Ideally this should eventually disappear in favour of actually
3980 * implementing the correct behaviour for all cores.
3982 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
3983 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
3985 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
3989 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
3990 /* Cache status: RAZ because we have no cache so it's always clean */
3991 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
3992 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
3996 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
3997 /* We never have a a block transfer operation in progress */
3998 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
3999 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4001 /* The cache ops themselves: these all NOP for QEMU */
4002 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4003 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4004 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4005 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4006 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4007 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4008 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4009 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4010 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4011 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4012 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4013 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4016 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4017 /* The cache test-and-clean instructions always return (1 << 30)
4018 * to indicate that there are no dirty cache lines.
4020 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4021 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4022 .resetvalue
= (1 << 30) },
4023 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4024 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4025 .resetvalue
= (1 << 30) },
4028 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4029 /* Ignore ReadBuffer accesses */
4030 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4031 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4032 .access
= PL1_RW
, .resetvalue
= 0,
4033 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4036 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4038 unsigned int cur_el
= arm_current_el(env
);
4040 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4041 return env
->cp15
.vpidr_el2
;
4043 return raw_read(env
, ri
);
4046 static uint64_t mpidr_read_val(CPUARMState
*env
)
4048 ARMCPU
*cpu
= env_archcpu(env
);
4049 uint64_t mpidr
= cpu
->mp_affinity
;
4051 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4052 mpidr
|= (1U << 31);
4053 /* Cores which are uniprocessor (non-coherent)
4054 * but still implement the MP extensions set
4055 * bit 30. (For instance, Cortex-R5).
4057 if (cpu
->mp_is_up
) {
4058 mpidr
|= (1u << 30);
4064 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4066 unsigned int cur_el
= arm_current_el(env
);
4068 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4069 return env
->cp15
.vmpidr_el2
;
4071 return mpidr_read_val(env
);
4074 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4076 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4077 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4078 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4079 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4080 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4081 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4082 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4083 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4084 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4085 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4086 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4087 offsetof(CPUARMState
, cp15
.par_ns
)} },
4088 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4089 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4090 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4091 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4092 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4093 .writefn
= vmsa_ttbr_write
, },
4094 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4095 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4096 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4097 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4098 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4099 .writefn
= vmsa_ttbr_write
, },
4102 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4104 return vfp_get_fpcr(env
);
4107 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4110 vfp_set_fpcr(env
, value
);
4113 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4115 return vfp_get_fpsr(env
);
4118 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4121 vfp_set_fpsr(env
, value
);
4124 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4127 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4128 return CP_ACCESS_TRAP
;
4130 return CP_ACCESS_OK
;
4133 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4136 env
->daif
= value
& PSTATE_DAIF
;
4139 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4141 return env
->pstate
& PSTATE_PAN
;
4144 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4147 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4150 static const ARMCPRegInfo pan_reginfo
= {
4151 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4152 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4153 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4154 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4157 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4159 return env
->pstate
& PSTATE_UAO
;
4162 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4165 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4168 static const ARMCPRegInfo uao_reginfo
= {
4169 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4170 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4171 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4172 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4175 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4177 return env
->pstate
& PSTATE_DIT
;
4180 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4183 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4186 static const ARMCPRegInfo dit_reginfo
= {
4187 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4188 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4189 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4190 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4193 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4195 return env
->pstate
& PSTATE_SSBS
;
4198 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4201 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4204 static const ARMCPRegInfo ssbs_reginfo
= {
4205 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4206 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4207 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4208 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4211 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4212 const ARMCPRegInfo
*ri
,
4215 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4216 switch (arm_current_el(env
)) {
4218 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4219 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4220 return CP_ACCESS_TRAP
;
4224 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4225 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4226 return CP_ACCESS_TRAP_EL2
;
4230 return CP_ACCESS_OK
;
4233 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4234 const ARMCPRegInfo
*ri
,
4237 /* Cache invalidate/clean to Point of Unification... */
4238 switch (arm_current_el(env
)) {
4240 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4241 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4242 return CP_ACCESS_TRAP
;
4246 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4247 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4248 return CP_ACCESS_TRAP_EL2
;
4252 return CP_ACCESS_OK
;
4255 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4256 * Page D4-1736 (DDI0487A.b)
4259 static int vae1_tlbmask(CPUARMState
*env
)
4261 uint64_t hcr
= arm_hcr_el2_eff(env
);
4264 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4265 mask
= ARMMMUIdxBit_E20_2
|
4266 ARMMMUIdxBit_E20_2_PAN
|
4269 mask
= ARMMMUIdxBit_E10_1
|
4270 ARMMMUIdxBit_E10_1_PAN
|
4274 if (arm_is_secure_below_el3(env
)) {
4275 mask
>>= ARM_MMU_IDX_A_NS
;
4281 /* Return 56 if TBI is enabled, 64 otherwise. */
4282 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4285 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
4286 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4287 int select
= extract64(addr
, 55, 1);
4289 return (tbi
>> select
) & 1 ? 56 : 64;
4292 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4294 uint64_t hcr
= arm_hcr_el2_eff(env
);
4297 /* Only the regime of the mmu_idx below is significant. */
4298 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4299 mmu_idx
= ARMMMUIdx_E20_0
;
4301 mmu_idx
= ARMMMUIdx_E10_0
;
4304 if (arm_is_secure_below_el3(env
)) {
4305 mmu_idx
&= ~ARM_MMU_IDX_A_NS
;
4308 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4311 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4314 CPUState
*cs
= env_cpu(env
);
4315 int mask
= vae1_tlbmask(env
);
4317 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4320 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4323 CPUState
*cs
= env_cpu(env
);
4324 int mask
= vae1_tlbmask(env
);
4326 if (tlb_force_broadcast(env
)) {
4327 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4329 tlb_flush_by_mmuidx(cs
, mask
);
4333 static int alle1_tlbmask(CPUARMState
*env
)
4336 * Note that the 'ALL' scope must invalidate both stage 1 and
4337 * stage 2 translations, whereas most other scopes only invalidate
4338 * stage 1 translations.
4340 if (arm_is_secure_below_el3(env
)) {
4341 return ARMMMUIdxBit_SE10_1
|
4342 ARMMMUIdxBit_SE10_1_PAN
|
4343 ARMMMUIdxBit_SE10_0
;
4345 return ARMMMUIdxBit_E10_1
|
4346 ARMMMUIdxBit_E10_1_PAN
|
4351 static int e2_tlbmask(CPUARMState
*env
)
4353 if (arm_is_secure_below_el3(env
)) {
4354 return ARMMMUIdxBit_SE20_0
|
4355 ARMMMUIdxBit_SE20_2
|
4356 ARMMMUIdxBit_SE20_2_PAN
|
4359 return ARMMMUIdxBit_E20_0
|
4360 ARMMMUIdxBit_E20_2
|
4361 ARMMMUIdxBit_E20_2_PAN
|
4366 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4369 CPUState
*cs
= env_cpu(env
);
4370 int mask
= alle1_tlbmask(env
);
4372 tlb_flush_by_mmuidx(cs
, mask
);
4375 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4378 CPUState
*cs
= env_cpu(env
);
4379 int mask
= e2_tlbmask(env
);
4381 tlb_flush_by_mmuidx(cs
, mask
);
4384 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4387 ARMCPU
*cpu
= env_archcpu(env
);
4388 CPUState
*cs
= CPU(cpu
);
4390 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4393 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4396 CPUState
*cs
= env_cpu(env
);
4397 int mask
= alle1_tlbmask(env
);
4399 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4402 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4405 CPUState
*cs
= env_cpu(env
);
4406 int mask
= e2_tlbmask(env
);
4408 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4411 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4414 CPUState
*cs
= env_cpu(env
);
4416 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4419 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4422 /* Invalidate by VA, EL2
4423 * Currently handles both VAE2 and VALE2, since we don't support
4424 * flush-last-level-only.
4426 CPUState
*cs
= env_cpu(env
);
4427 int mask
= e2_tlbmask(env
);
4428 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4430 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4433 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4436 /* Invalidate by VA, EL3
4437 * Currently handles both VAE3 and VALE3, since we don't support
4438 * flush-last-level-only.
4440 ARMCPU
*cpu
= env_archcpu(env
);
4441 CPUState
*cs
= CPU(cpu
);
4442 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4444 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4447 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4450 CPUState
*cs
= env_cpu(env
);
4451 int mask
= vae1_tlbmask(env
);
4452 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4453 int bits
= vae1_tlbbits(env
, pageaddr
);
4455 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4458 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4461 /* Invalidate by VA, EL1&0 (AArch64 version).
4462 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4463 * since we don't support flush-for-specific-ASID-only or
4464 * flush-last-level-only.
4466 CPUState
*cs
= env_cpu(env
);
4467 int mask
= vae1_tlbmask(env
);
4468 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4469 int bits
= vae1_tlbbits(env
, pageaddr
);
4471 if (tlb_force_broadcast(env
)) {
4472 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4474 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4478 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4481 CPUState
*cs
= env_cpu(env
);
4482 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4483 bool secure
= arm_is_secure_below_el3(env
);
4484 int mask
= secure
? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
;
4485 int bits
= tlbbits_for_regime(env
, secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
,
4488 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4491 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4494 CPUState
*cs
= env_cpu(env
);
4495 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4496 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_SE3
, pageaddr
);
4498 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4499 ARMMMUIdxBit_SE3
, bits
);
4502 #ifdef TARGET_AARCH64
4508 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
4511 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
4512 /* Extract one bit to represent the va selector in use. */
4513 uint64_t select
= sextract64(value
, 36, 1);
4514 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true);
4515 TLBIRange ret
= { };
4517 page_size_granule
= extract64(value
, 46, 2);
4519 /* The granule encoded in value must match the granule in use. */
4520 if (page_size_granule
!= (param
.using64k
? 3 : param
.using16k
? 2 : 1)) {
4521 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
4526 page_shift
= (page_size_granule
- 1) * 2 + 12;
4527 num
= extract64(value
, 39, 5);
4528 scale
= extract64(value
, 44, 2);
4529 exponent
= (5 * scale
) + 1;
4531 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
4534 ret
.base
= sextract64(value
, 0, 37);
4536 ret
.base
= extract64(value
, 0, 37);
4540 * With DS=1, BaseADDR is always shifted 16 so that it is able
4541 * to address all 52 va bits. The input address is perforce
4542 * aligned on a 64k boundary regardless of translation granule.
4546 ret
.base
<<= page_shift
;
4551 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
4552 int idxmap
, bool synced
)
4554 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
4558 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
4559 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
4562 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
4568 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
4569 range
.length
, idxmap
, bits
);
4573 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
4574 const ARMCPRegInfo
*ri
,
4578 * Invalidate by VA range, EL1&0.
4579 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
4580 * since we don't support flush-for-specific-ASID-only or
4581 * flush-last-level-only.
4584 do_rvae_write(env
, value
, vae1_tlbmask(env
),
4585 tlb_force_broadcast(env
));
4588 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
4589 const ARMCPRegInfo
*ri
,
4593 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
4594 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
4595 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
4596 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
4597 * shareable specific flushes.
4600 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
4603 static int vae2_tlbmask(CPUARMState
*env
)
4605 return (arm_is_secure_below_el3(env
)
4606 ? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
);
4609 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
4610 const ARMCPRegInfo
*ri
,
4614 * Invalidate by VA range, EL2.
4615 * Currently handles all of RVAE2 and RVALE2,
4616 * since we don't support flush-for-specific-ASID-only or
4617 * flush-last-level-only.
4620 do_rvae_write(env
, value
, vae2_tlbmask(env
),
4621 tlb_force_broadcast(env
));
4626 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
4627 const ARMCPRegInfo
*ri
,
4631 * Invalidate by VA range, Inner/Outer Shareable, EL2.
4632 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
4633 * since we don't support flush-for-specific-ASID-only,
4634 * flush-last-level-only or inner/outer shareable specific flushes.
4637 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
4641 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
4642 const ARMCPRegInfo
*ri
,
4646 * Invalidate by VA range, EL3.
4647 * Currently handles all of RVAE3 and RVALE3,
4648 * since we don't support flush-for-specific-ASID-only or
4649 * flush-last-level-only.
4652 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
,
4653 tlb_force_broadcast(env
));
4656 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
4657 const ARMCPRegInfo
*ri
,
4661 * Invalidate by VA range, EL3, Inner/Outer Shareable.
4662 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
4663 * since we don't support flush-for-specific-ASID-only,
4664 * flush-last-level-only or inner/outer specific flushes.
4667 do_rvae_write(env
, value
, ARMMMUIdxBit_SE3
, true);
4671 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4674 int cur_el
= arm_current_el(env
);
4677 uint64_t hcr
= arm_hcr_el2_eff(env
);
4680 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4681 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4682 return CP_ACCESS_TRAP_EL2
;
4685 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4686 return CP_ACCESS_TRAP
;
4688 if (hcr
& HCR_TDZ
) {
4689 return CP_ACCESS_TRAP_EL2
;
4692 } else if (hcr
& HCR_TDZ
) {
4693 return CP_ACCESS_TRAP_EL2
;
4696 return CP_ACCESS_OK
;
4699 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4701 ARMCPU
*cpu
= env_archcpu(env
);
4702 int dzp_bit
= 1 << 4;
4704 /* DZP indicates whether DC ZVA access is allowed */
4705 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4708 return cpu
->dcz_blocksize
| dzp_bit
;
4711 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4714 if (!(env
->pstate
& PSTATE_SP
)) {
4715 /* Access to SP_EL0 is undefined if it's being used as
4716 * the stack pointer.
4718 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4720 return CP_ACCESS_OK
;
4723 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4725 return env
->pstate
& PSTATE_SP
;
4728 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4730 update_spsel(env
, val
);
4733 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4736 ARMCPU
*cpu
= env_archcpu(env
);
4738 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4739 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4743 /* ??? Lots of these bits are not implemented. */
4745 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
4746 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
4747 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
4749 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
4750 SCTLR_ATA0
| SCTLR_ATA
);
4754 if (raw_read(env
, ri
) == value
) {
4755 /* Skip the TLB flush if nothing actually changed; Linux likes
4756 * to do a lot of pointless SCTLR writes.
4761 raw_write(env
, ri
, value
);
4763 /* This may enable/disable the MMU, so do a TLB flush. */
4764 tlb_flush(CPU(cpu
));
4766 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4768 * Normally we would always end the TB on an SCTLR write; see the
4769 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4770 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4771 * of hflags from the translator, so do it here.
4773 arm_rebuild_hflags(env
);
4777 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4780 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4783 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4784 /* Minimal set of EL0-visible registers. This will need to be expanded
4785 * significantly for system emulation of AArch64 CPUs.
4787 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4788 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4789 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4790 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4791 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4792 .type
= ARM_CP_NO_RAW
,
4793 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4794 .fieldoffset
= offsetof(CPUARMState
, daif
),
4795 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4796 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4797 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4798 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4799 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4800 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4801 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4802 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4803 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4804 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4805 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4806 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4807 .readfn
= aa64_dczid_read
},
4808 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4809 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4810 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4811 #ifndef CONFIG_USER_ONLY
4812 /* Avoid overhead of an access check that always passes in user-mode */
4813 .accessfn
= aa64_zva_access
,
4816 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4817 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4818 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4819 /* Cache ops: all NOPs since we don't emulate caches */
4820 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4821 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4822 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4823 .accessfn
= aa64_cacheop_pou_access
},
4824 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4825 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4826 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4827 .accessfn
= aa64_cacheop_pou_access
},
4828 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4829 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4830 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4831 .accessfn
= aa64_cacheop_pou_access
},
4832 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4833 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4834 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
4835 .type
= ARM_CP_NOP
},
4836 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4837 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4838 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4839 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4840 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4841 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4842 .accessfn
= aa64_cacheop_poc_access
},
4843 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4844 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4845 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4846 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4847 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4848 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4849 .accessfn
= aa64_cacheop_pou_access
},
4850 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4851 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4852 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4853 .accessfn
= aa64_cacheop_poc_access
},
4854 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4855 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4856 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4857 /* TLBI operations */
4858 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4859 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4860 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4861 .writefn
= tlbi_aa64_vmalle1is_write
},
4862 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4863 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4864 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4865 .writefn
= tlbi_aa64_vae1is_write
},
4866 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4867 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4868 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4869 .writefn
= tlbi_aa64_vmalle1is_write
},
4870 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4871 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4872 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4873 .writefn
= tlbi_aa64_vae1is_write
},
4874 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4875 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4876 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4877 .writefn
= tlbi_aa64_vae1is_write
},
4878 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4879 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4880 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4881 .writefn
= tlbi_aa64_vae1is_write
},
4882 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4883 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4884 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4885 .writefn
= tlbi_aa64_vmalle1_write
},
4886 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4888 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4889 .writefn
= tlbi_aa64_vae1_write
},
4890 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4891 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4892 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4893 .writefn
= tlbi_aa64_vmalle1_write
},
4894 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4895 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4896 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4897 .writefn
= tlbi_aa64_vae1_write
},
4898 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4899 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4900 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4901 .writefn
= tlbi_aa64_vae1_write
},
4902 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4903 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4904 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4905 .writefn
= tlbi_aa64_vae1_write
},
4906 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4907 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4908 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4909 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4910 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4911 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4912 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4913 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4914 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4915 .writefn
= tlbi_aa64_alle1is_write
},
4916 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4917 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4918 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4919 .writefn
= tlbi_aa64_alle1is_write
},
4920 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4921 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4922 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4923 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4924 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4925 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4926 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4927 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4928 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4929 .writefn
= tlbi_aa64_alle1_write
},
4930 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4931 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4932 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4933 .writefn
= tlbi_aa64_alle1is_write
},
4934 #ifndef CONFIG_USER_ONLY
4935 /* 64 bit address translation operations */
4936 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4937 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4938 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4939 .writefn
= ats_write64
},
4940 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4941 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4942 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4943 .writefn
= ats_write64
},
4944 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4945 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
4946 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4947 .writefn
= ats_write64
},
4948 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
4949 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
4950 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4951 .writefn
= ats_write64
},
4952 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
4953 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
4954 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4955 .writefn
= ats_write64
},
4956 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
4957 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
4958 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4959 .writefn
= ats_write64
},
4960 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
4961 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
4962 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4963 .writefn
= ats_write64
},
4964 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
4965 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
4966 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4967 .writefn
= ats_write64
},
4968 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4969 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
4970 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
4971 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4972 .writefn
= ats_write64
},
4973 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
4974 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
4975 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4976 .writefn
= ats_write64
},
4977 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
4978 .type
= ARM_CP_ALIAS
,
4979 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
4980 .access
= PL1_RW
, .resetvalue
= 0,
4981 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
4982 .writefn
= par_write
},
4984 /* TLB invalidate last level of translation table walk */
4985 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4986 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4987 .writefn
= tlbimva_is_write
},
4988 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4989 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4990 .writefn
= tlbimvaa_is_write
},
4991 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4992 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4993 .writefn
= tlbimva_write
},
4994 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4995 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
4996 .writefn
= tlbimvaa_write
},
4997 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
4998 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
4999 .writefn
= tlbimva_hyp_write
},
5000 { .name
= "TLBIMVALHIS",
5001 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5002 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5003 .writefn
= tlbimva_hyp_is_write
},
5004 { .name
= "TLBIIPAS2",
5005 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5006 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5007 { .name
= "TLBIIPAS2IS",
5008 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5009 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5010 { .name
= "TLBIIPAS2L",
5011 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5012 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5013 { .name
= "TLBIIPAS2LIS",
5014 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5015 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5016 /* 32 bit cache operations */
5017 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5018 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5019 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5020 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5021 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5022 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5023 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5024 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5025 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5026 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5027 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5028 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5029 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5030 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5031 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5032 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5033 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5034 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5035 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5036 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5037 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5038 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5039 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5040 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5041 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5042 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5043 /* MMU Domain access control / MPU write buffer control */
5044 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5045 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5046 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5047 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5048 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5049 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5050 .type
= ARM_CP_ALIAS
,
5051 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5053 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5054 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5055 .type
= ARM_CP_ALIAS
,
5056 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5058 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5059 /* We rely on the access checks not allowing the guest to write to the
5060 * state field when SPSel indicates that it's being used as the stack
5063 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5064 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5065 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5066 .type
= ARM_CP_ALIAS
,
5067 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5068 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5069 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5070 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5071 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5072 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5073 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5074 .type
= ARM_CP_NO_RAW
,
5075 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5076 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5077 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5079 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5080 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5081 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5082 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5083 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5084 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5085 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5086 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5087 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5088 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5089 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5090 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5091 .type
= ARM_CP_ALIAS
,
5092 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5094 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5095 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5096 .type
= ARM_CP_ALIAS
,
5097 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5099 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5100 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5101 .type
= ARM_CP_ALIAS
,
5102 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5104 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5105 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5106 .type
= ARM_CP_ALIAS
,
5107 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5109 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5110 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5111 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5113 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5114 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
5115 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5116 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5117 .writefn
= sdcr_write
,
5118 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5121 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5123 ARMCPU
*cpu
= env_archcpu(env
);
5125 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5126 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5128 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5131 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5132 valid_mask
&= ~HCR_HCD
;
5133 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5134 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5135 * However, if we're using the SMC PSCI conduit then QEMU is
5136 * effectively acting like EL3 firmware and so the guest at
5137 * EL2 should retain the ability to prevent EL1 from being
5138 * able to make SMC calls into the ersatz firmware, so in
5139 * that case HCR.TSC should be read/write.
5141 valid_mask
&= ~HCR_TSC
;
5144 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5145 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5146 valid_mask
|= HCR_E2H
;
5148 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5149 valid_mask
|= HCR_TERR
| HCR_TEA
;
5151 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5152 valid_mask
|= HCR_TLOR
;
5154 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5155 valid_mask
|= HCR_API
| HCR_APK
;
5157 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5158 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5160 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5161 valid_mask
|= HCR_ENSCXT
;
5163 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5164 valid_mask
|= HCR_FWB
;
5168 /* Clear RES0 bits. */
5169 value
&= valid_mask
;
5172 * These bits change the MMU setup:
5173 * HCR_VM enables stage 2 translation
5174 * HCR_PTW forbids certain page-table setups
5175 * HCR_DC disables stage1 and enables stage2 translation
5176 * HCR_DCT enables tagging on (disabled) stage1 translation
5177 * HCR_FWB changes the interpretation of stage2 descriptor bits
5179 if ((env
->cp15
.hcr_el2
^ value
) &
5180 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5181 tlb_flush(CPU(cpu
));
5183 env
->cp15
.hcr_el2
= value
;
5186 * Updates to VI and VF require us to update the status of
5187 * virtual interrupts, which are the logical OR of these bits
5188 * and the state of the input lines from the GIC. (This requires
5189 * that we have the iothread lock, which is done by marking the
5190 * reginfo structs as ARM_CP_IO.)
5191 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5192 * possible for it to be taken immediately, because VIRQ and
5193 * VFIQ are masked unless running at EL0 or EL1, and HCR
5194 * can only be written at EL2.
5196 g_assert(qemu_mutex_iothread_locked());
5197 arm_cpu_update_virq(cpu
);
5198 arm_cpu_update_vfiq(cpu
);
5199 arm_cpu_update_vserr(cpu
);
5202 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5204 do_hcr_write(env
, value
, 0);
5207 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5210 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5211 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5212 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5215 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5218 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5219 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5220 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5224 * Return the effective value of HCR_EL2.
5225 * Bits that are not included here:
5226 * RW (read from SCR_EL3.RW as needed)
5228 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5230 uint64_t ret
= env
->cp15
.hcr_el2
;
5232 if (!arm_is_el2_enabled(env
)) {
5234 * "This register has no effect if EL2 is not enabled in the
5235 * current Security state". This is ARMv8.4-SecEL2 speak for
5236 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5238 * Prior to that, the language was "In an implementation that
5239 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5240 * as if this field is 0 for all purposes other than a direct
5241 * read or write access of HCR_EL2". With lots of enumeration
5242 * on a per-field basis. In current QEMU, this is condition
5243 * is arm_is_secure_below_el3.
5245 * Since the v8.4 language applies to the entire register, and
5246 * appears to be backward compatible, use that.
5252 * For a cpu that supports both aarch64 and aarch32, we can set bits
5253 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5254 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5256 if (!arm_el_is_aa64(env
, 2)) {
5257 uint64_t aa32_valid
;
5260 * These bits are up-to-date as of ARMv8.6.
5261 * For HCR, it's easiest to list just the 2 bits that are invalid.
5262 * For HCR2, list those that are valid.
5264 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5265 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5266 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5270 if (ret
& HCR_TGE
) {
5271 /* These bits are up-to-date as of ARMv8.6. */
5272 if (ret
& HCR_E2H
) {
5273 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5274 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5275 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5276 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5277 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5278 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5280 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5282 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5283 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5284 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5292 * Corresponds to ARM pseudocode function ELIsInHost().
5294 bool el_is_in_host(CPUARMState
*env
, int el
)
5299 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5300 * Perform the simplest bit tests first, and validate EL2 afterward.
5303 return false; /* EL1 or EL3 */
5307 * Note that hcr_write() checks isar_feature_aa64_vh(),
5308 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5310 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5311 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5315 /* TGE and/or E2H set: double check those bits are currently legal. */
5316 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5319 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5322 uint64_t valid_mask
= 0;
5324 /* No features adding bits to HCRX are implemented. */
5326 /* Clear RES0 bits. */
5327 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5330 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5333 if (arm_current_el(env
) < 3
5334 && arm_feature(env
, ARM_FEATURE_EL3
)
5335 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5336 return CP_ACCESS_TRAP_EL3
;
5338 return CP_ACCESS_OK
;
5341 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5342 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5343 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5344 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5345 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5348 /* Return the effective value of HCRX_EL2. */
5349 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5352 * The bits in this register behave as 0 for all purposes other than
5353 * direct reads of the register if:
5354 * - EL2 is not enabled in the current security state,
5355 * - SCR_EL3.HXEn is 0.
5357 if (!arm_is_el2_enabled(env
)
5358 || (arm_feature(env
, ARM_FEATURE_EL3
)
5359 && !(env
->cp15
.scr_el3
& SCR_HXEN
))) {
5362 return env
->cp15
.hcrx_el2
;
5365 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5369 * For A-profile AArch32 EL3, if NSACR.CP10
5370 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5372 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5373 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5374 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5375 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
5377 env
->cp15
.cptr_el
[2] = value
;
5380 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5383 * For A-profile AArch32 EL3, if NSACR.CP10
5384 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5386 uint64_t value
= env
->cp15
.cptr_el
[2];
5388 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5389 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5390 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
5395 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5396 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5398 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5399 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5400 .writefn
= hcr_write
},
5401 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5402 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5403 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5404 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5405 .writefn
= hcr_writelow
},
5406 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5407 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5408 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5409 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5410 .type
= ARM_CP_ALIAS
,
5411 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5413 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5414 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5415 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5416 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5417 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5418 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5419 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5420 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5421 .type
= ARM_CP_ALIAS
,
5422 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5424 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5425 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5426 .type
= ARM_CP_ALIAS
,
5427 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5429 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5430 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5431 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5432 .access
= PL2_RW
, .writefn
= vbar_write
,
5433 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5435 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5436 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5437 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5438 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5439 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5440 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5441 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5442 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5443 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5444 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5445 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5446 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5448 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5449 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5450 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5451 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5452 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5453 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5454 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5456 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5457 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5458 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5459 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5461 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5462 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5463 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5465 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5466 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5467 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5469 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5470 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5471 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5472 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5473 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5474 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5475 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5476 .type
= ARM_CP_ALIAS
,
5477 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5478 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5479 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5480 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5482 /* no .writefn needed as this can't cause an ASID change;
5483 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5485 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5486 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5487 .cp
= 15, .opc1
= 6, .crm
= 2,
5488 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5489 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5490 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5491 .writefn
= vttbr_write
},
5492 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5493 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5494 .access
= PL2_RW
, .writefn
= vttbr_write
,
5495 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5496 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5497 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5498 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5499 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5500 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5501 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5502 .access
= PL2_RW
, .resetvalue
= 0,
5503 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5504 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5505 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5506 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5507 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5508 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5509 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5510 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5511 { .name
= "TLBIALLNSNH",
5512 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5513 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5514 .writefn
= tlbiall_nsnh_write
},
5515 { .name
= "TLBIALLNSNHIS",
5516 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5517 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5518 .writefn
= tlbiall_nsnh_is_write
},
5519 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5520 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5521 .writefn
= tlbiall_hyp_write
},
5522 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5523 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5524 .writefn
= tlbiall_hyp_is_write
},
5525 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5526 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5527 .writefn
= tlbimva_hyp_write
},
5528 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5529 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5530 .writefn
= tlbimva_hyp_is_write
},
5531 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5532 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5533 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5534 .writefn
= tlbi_aa64_alle2_write
},
5535 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5536 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5537 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5538 .writefn
= tlbi_aa64_vae2_write
},
5539 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5540 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5541 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5542 .writefn
= tlbi_aa64_vae2_write
},
5543 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5544 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5545 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5546 .writefn
= tlbi_aa64_alle2is_write
},
5547 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5548 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5549 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5550 .writefn
= tlbi_aa64_vae2is_write
},
5551 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5552 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5553 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
5554 .writefn
= tlbi_aa64_vae2is_write
},
5555 #ifndef CONFIG_USER_ONLY
5556 /* Unlike the other EL2-related AT operations, these must
5557 * UNDEF from EL3 if EL2 is not implemented, which is why we
5558 * define them here rather than with the rest of the AT ops.
5560 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5561 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5562 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5563 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5564 .writefn
= ats_write64
},
5565 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5566 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5567 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5568 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
5569 .writefn
= ats_write64
},
5570 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5571 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5572 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5573 * to behave as if SCR.NS was 1.
5575 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5577 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5578 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5580 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5581 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5582 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5583 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5584 * reset values as IMPDEF. We choose to reset to 3 to comply with
5585 * both ARMv7 and ARMv8.
5587 .access
= PL2_RW
, .resetvalue
= 3,
5588 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5589 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5590 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5591 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5592 .writefn
= gt_cntvoff_write
,
5593 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5594 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5595 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5596 .writefn
= gt_cntvoff_write
,
5597 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5598 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5599 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5600 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5601 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5602 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5603 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5604 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5605 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5606 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5607 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5608 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5609 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5610 .resetfn
= gt_hyp_timer_reset
,
5611 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5612 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5614 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5616 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5618 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5620 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5621 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5622 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5623 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5624 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5625 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5627 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5628 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5629 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5631 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5634 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5635 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5636 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5637 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5639 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5640 .writefn
= hcr_writehigh
},
5643 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5646 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
5647 return CP_ACCESS_OK
;
5649 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5652 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
5653 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5654 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
5655 .access
= PL2_RW
, .accessfn
= sel2_access
,
5656 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
5657 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5658 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
5659 .access
= PL2_RW
, .accessfn
= sel2_access
,
5660 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
5663 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5666 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5667 * At Secure EL1 it traps to EL3 or EL2.
5669 if (arm_current_el(env
) == 3) {
5670 return CP_ACCESS_OK
;
5672 if (arm_is_secure_below_el3(env
)) {
5673 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
5674 return CP_ACCESS_TRAP_EL2
;
5676 return CP_ACCESS_TRAP_EL3
;
5678 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5680 return CP_ACCESS_OK
;
5682 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5685 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5686 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5687 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5688 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5689 .resetfn
= scr_reset
, .writefn
= scr_write
},
5690 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5691 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5692 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5693 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5694 .writefn
= scr_write
},
5695 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5696 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5697 .access
= PL3_RW
, .resetvalue
= 0,
5698 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5700 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5701 .access
= PL3_RW
, .resetvalue
= 0,
5702 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5703 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5704 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5705 .writefn
= vbar_write
, .resetvalue
= 0,
5706 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5707 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5708 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5709 .access
= PL3_RW
, .resetvalue
= 0,
5710 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5711 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5712 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5714 /* no .writefn needed as this can't cause an ASID change;
5715 * we must provide a .raw_writefn and .resetfn because we handle
5716 * reset and migration for the AArch32 TTBCR(S), which might be
5717 * using mask and base_mask.
5719 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5720 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5721 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5722 .type
= ARM_CP_ALIAS
,
5723 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5725 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5726 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5727 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5728 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5729 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5730 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5731 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5732 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5733 .type
= ARM_CP_ALIAS
,
5734 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5736 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5737 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5738 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5739 .access
= PL3_RW
, .writefn
= vbar_write
,
5740 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5742 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5743 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5744 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5745 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5746 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5747 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5748 .access
= PL3_RW
, .resetvalue
= 0,
5749 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5750 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5751 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5752 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5754 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5755 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5756 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5758 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5759 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5760 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5762 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5763 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5764 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5765 .writefn
= tlbi_aa64_alle3is_write
},
5766 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5767 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5768 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5769 .writefn
= tlbi_aa64_vae3is_write
},
5770 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5771 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5772 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5773 .writefn
= tlbi_aa64_vae3is_write
},
5774 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5775 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5776 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5777 .writefn
= tlbi_aa64_alle3_write
},
5778 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5779 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5780 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5781 .writefn
= tlbi_aa64_vae3_write
},
5782 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5783 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5784 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5785 .writefn
= tlbi_aa64_vae3_write
},
5788 #ifndef CONFIG_USER_ONLY
5789 /* Test if system register redirection is to occur in the current state. */
5790 static bool redirect_for_e2h(CPUARMState
*env
)
5792 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5795 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5799 if (redirect_for_e2h(env
)) {
5800 /* Switch to the saved EL2 version of the register. */
5802 readfn
= ri
->readfn
;
5804 readfn
= ri
->orig_readfn
;
5806 if (readfn
== NULL
) {
5809 return readfn(env
, ri
);
5812 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5817 if (redirect_for_e2h(env
)) {
5818 /* Switch to the saved EL2 version of the register. */
5820 writefn
= ri
->writefn
;
5822 writefn
= ri
->orig_writefn
;
5824 if (writefn
== NULL
) {
5825 writefn
= raw_write
;
5827 writefn(env
, ri
, value
);
5830 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5833 uint32_t src_key
, dst_key
, new_key
;
5834 const char *src_name
, *dst_name
, *new_name
;
5835 bool (*feature
)(const ARMISARegisters
*id
);
5838 #define K(op0, op1, crn, crm, op2) \
5839 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5841 static const struct E2HAlias aliases
[] = {
5842 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5843 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5844 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5845 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5846 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5847 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5848 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5849 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5850 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5851 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5852 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5853 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5854 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5855 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5856 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5857 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5858 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5859 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5860 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5861 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5862 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5863 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5864 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5865 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5866 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5867 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5868 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5869 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5870 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5871 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5872 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5873 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5876 * Note that redirection of ZCR is mentioned in the description
5877 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5878 * not in the summary table.
5880 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5881 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5883 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5884 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
5886 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
5887 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
5888 isar_feature_aa64_scxtnum
},
5890 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5891 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5897 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5898 const struct E2HAlias
*a
= &aliases
[i
];
5899 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
5902 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
5906 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5907 (gpointer
)(uintptr_t)a
->src_key
);
5908 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
5909 (gpointer
)(uintptr_t)a
->dst_key
);
5910 g_assert(src_reg
!= NULL
);
5911 g_assert(dst_reg
!= NULL
);
5913 /* Cross-compare names to detect typos in the keys. */
5914 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
5915 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
5917 /* None of the core system registers use opaque; we will. */
5918 g_assert(src_reg
->opaque
== NULL
);
5920 /* Create alias before redirection so we dup the right data. */
5921 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
5923 new_reg
->name
= a
->new_name
;
5924 new_reg
->type
|= ARM_CP_ALIAS
;
5925 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5926 new_reg
->access
&= PL2_RW
| PL3_RW
;
5928 ok
= g_hash_table_insert(cpu
->cp_regs
,
5929 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
5932 src_reg
->opaque
= dst_reg
;
5933 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
5934 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
5935 if (!src_reg
->raw_readfn
) {
5936 src_reg
->raw_readfn
= raw_read
;
5938 if (!src_reg
->raw_writefn
) {
5939 src_reg
->raw_writefn
= raw_write
;
5941 src_reg
->readfn
= el2_e2h_read
;
5942 src_reg
->writefn
= el2_e2h_write
;
5947 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5950 int cur_el
= arm_current_el(env
);
5953 uint64_t hcr
= arm_hcr_el2_eff(env
);
5956 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5957 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
5958 return CP_ACCESS_TRAP_EL2
;
5961 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
5962 return CP_ACCESS_TRAP
;
5964 if (hcr
& HCR_TID2
) {
5965 return CP_ACCESS_TRAP_EL2
;
5968 } else if (hcr
& HCR_TID2
) {
5969 return CP_ACCESS_TRAP_EL2
;
5973 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
5974 return CP_ACCESS_TRAP_EL2
;
5977 return CP_ACCESS_OK
;
5980 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5983 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
5984 * read via a bit in OSLSR_EL1.
5988 if (ri
->state
== ARM_CP_STATE_AA32
) {
5989 oslock
= (value
== 0xC5ACCE55);
5994 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
5997 static const ARMCPRegInfo debug_cp_reginfo
[] = {
5998 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
5999 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
6000 * unlike DBGDRAR it is never accessible from EL0.
6001 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
6004 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
6005 .access
= PL0_R
, .accessfn
= access_tdra
,
6006 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6007 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
6008 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6009 .access
= PL1_R
, .accessfn
= access_tdra
,
6010 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6011 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
6012 .access
= PL0_R
, .accessfn
= access_tdra
,
6013 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6014 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
6015 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
6016 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6017 .access
= PL1_RW
, .accessfn
= access_tda
,
6018 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
6021 * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external
6022 * Debug Communication Channel is not implemented.
6024 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_AA64
,
6025 .opc0
= 2, .opc1
= 3, .crn
= 0, .crm
= 1, .opc2
= 0,
6026 .access
= PL0_R
, .accessfn
= access_tda
,
6027 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6029 * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
6030 * it is unlikely a guest will care.
6031 * We don't implement the configurable EL0 access.
6033 { .name
= "DBGDSCRint", .state
= ARM_CP_STATE_AA32
,
6034 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6035 .type
= ARM_CP_ALIAS
,
6036 .access
= PL1_R
, .accessfn
= access_tda
,
6037 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
6038 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
6039 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
6040 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6041 .accessfn
= access_tdosa
,
6042 .writefn
= oslar_write
},
6043 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
6044 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
6045 .access
= PL1_R
, .resetvalue
= 10,
6046 .accessfn
= access_tdosa
,
6047 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
6048 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6049 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6050 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
6051 .access
= PL1_RW
, .accessfn
= access_tdosa
,
6052 .type
= ARM_CP_NOP
},
6053 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6054 * implement vector catch debug events yet.
6057 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6058 .access
= PL1_RW
, .accessfn
= access_tda
,
6059 .type
= ARM_CP_NOP
},
6060 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6061 * to save and restore a 32-bit guest's DBGVCR)
6063 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
6064 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
6065 .access
= PL2_RW
, .accessfn
= access_tda
,
6066 .type
= ARM_CP_NOP
| ARM_CP_EL3_NO_EL2_KEEP
},
6067 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6068 * Channel but Linux may try to access this register. The 32-bit
6069 * alias is DBGDCCINT.
6071 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
6072 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6073 .access
= PL1_RW
, .accessfn
= access_tda
,
6074 .type
= ARM_CP_NOP
},
6077 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
6078 /* 64 bit access versions of the (dummy) debug registers */
6079 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
6080 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6081 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
6082 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6086 * Check for traps to RAS registers, which are controlled
6087 * by HCR_EL2.TERR and SCR_EL3.TERR.
6089 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6092 int el
= arm_current_el(env
);
6094 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6095 return CP_ACCESS_TRAP_EL2
;
6097 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6098 return CP_ACCESS_TRAP_EL3
;
6100 return CP_ACCESS_OK
;
6103 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6105 int el
= arm_current_el(env
);
6107 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6108 return env
->cp15
.vdisr_el2
;
6110 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6111 return 0; /* RAZ/WI */
6113 return env
->cp15
.disr_el1
;
6116 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6118 int el
= arm_current_el(env
);
6120 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6121 env
->cp15
.vdisr_el2
= val
;
6124 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6125 return; /* RAZ/WI */
6127 env
->cp15
.disr_el1
= val
;
6131 * Minimal RAS implementation with no Error Records.
6132 * Which means that all of the Error Record registers:
6140 * ERXPFGCDN_EL1 (RASv1p1)
6141 * ERXPFGCTL_EL1 (RASv1p1)
6142 * ERXPFGF_EL1 (RASv1p1)
6146 * may generate UNDEFINED, which is the effect we get by not
6147 * listing them at all.
6149 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6150 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6151 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6152 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6153 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6154 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6155 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6156 .access
= PL1_R
, .accessfn
= access_terr
,
6157 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6158 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6159 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6160 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6161 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6162 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6163 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6167 * Return the exception level to which exceptions should be taken
6168 * via SVEAccessTrap. This excludes the check for whether the exception
6169 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6170 * be found by testing 0 < fp_exception_el < sve_exception_el.
6172 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6173 * pseudocode does *not* separate out the FP trap checks, but has them
6174 * all in one function.
6176 int sve_exception_el(CPUARMState
*env
, int el
)
6178 #ifndef CONFIG_USER_ONLY
6179 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6180 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6192 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6193 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6194 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6195 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6197 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6206 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6212 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6213 if (arm_feature(env
, ARM_FEATURE_EL3
)
6214 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6222 * Given that SVE is enabled, return the vector length for EL.
6224 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6226 ARMCPU
*cpu
= env_archcpu(env
);
6227 uint32_t len
= cpu
->sve_max_vq
- 1;
6229 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6230 len
= MIN(len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
6232 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6233 len
= MIN(len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
6235 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6236 len
= MIN(len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
6239 len
= 31 - clz32(cpu
->sve_vq_map
& MAKE_64BIT_MASK(0, len
+ 1));
6243 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6246 int cur_el
= arm_current_el(env
);
6247 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6250 /* Bits other than [3:0] are RAZ/WI. */
6251 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6252 raw_write(env
, ri
, value
& 0xf);
6255 * Because we arrived here, we know both FP and SVE are enabled;
6256 * otherwise we would have trapped access to the ZCR_ELn register.
6258 new_len
= sve_vqm1_for_el(env
, cur_el
);
6259 if (new_len
< old_len
) {
6260 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6264 static const ARMCPRegInfo zcr_reginfo
[] = {
6265 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6266 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6267 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6268 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6269 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6270 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6271 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6272 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6273 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6274 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6275 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6276 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6277 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6278 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6279 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6282 #ifdef TARGET_AARCH64
6283 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6286 int el
= arm_current_el(env
);
6289 uint64_t sctlr
= arm_sctlr(env
, el
);
6290 if (!(sctlr
& SCTLR_EnTP2
)) {
6291 return CP_ACCESS_TRAP
;
6294 /* TODO: FEAT_FGT */
6296 && arm_feature(env
, ARM_FEATURE_EL3
)
6297 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6298 return CP_ACCESS_TRAP_EL3
;
6300 return CP_ACCESS_OK
;
6303 static const ARMCPRegInfo sme_reginfo
[] = {
6304 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
6305 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
6306 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
6307 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
6309 #endif /* TARGET_AARCH64 */
6311 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
6313 CPUARMState
*env
= &cpu
->env
;
6315 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
6316 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
6318 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
6320 if (env
->cpu_watchpoint
[n
]) {
6321 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
6322 env
->cpu_watchpoint
[n
] = NULL
;
6325 if (!FIELD_EX64(wcr
, DBGWCR
, E
)) {
6326 /* E bit clear : watchpoint disabled */
6330 switch (FIELD_EX64(wcr
, DBGWCR
, LSC
)) {
6332 /* LSC 00 is reserved and must behave as if the wp is disabled */
6335 flags
|= BP_MEM_READ
;
6338 flags
|= BP_MEM_WRITE
;
6341 flags
|= BP_MEM_ACCESS
;
6345 /* Attempts to use both MASK and BAS fields simultaneously are
6346 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6347 * thus generating a watchpoint for every byte in the masked region.
6349 mask
= FIELD_EX64(wcr
, DBGWCR
, MASK
);
6350 if (mask
== 1 || mask
== 2) {
6351 /* Reserved values of MASK; we must act as if the mask value was
6352 * some non-reserved value, or as if the watchpoint were disabled.
6353 * We choose the latter.
6357 /* Watchpoint covers an aligned area up to 2GB in size */
6359 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6360 * whether the watchpoint fires when the unmasked bits match; we opt
6361 * to generate the exceptions.
6365 /* Watchpoint covers bytes defined by the byte address select bits */
6366 int bas
= FIELD_EX64(wcr
, DBGWCR
, BAS
);
6369 if (extract64(wvr
, 2, 1)) {
6370 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6371 * ignored, and BAS[3:0] define which bytes to watch.
6377 /* This must act as if the watchpoint is disabled */
6381 /* The BAS bits are supposed to be programmed to indicate a contiguous
6382 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6383 * we fire for each byte in the word/doubleword addressed by the WVR.
6384 * We choose to ignore any non-zero bits after the first range of 1s.
6386 basstart
= ctz32(bas
);
6387 len
= cto32(bas
>> basstart
);
6391 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6392 &env
->cpu_watchpoint
[n
]);
6395 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6398 CPUARMState
*env
= &cpu
->env
;
6400 /* Completely clear out existing QEMU watchpoints and our array, to
6401 * avoid possible stale entries following migration load.
6403 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6404 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6406 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6407 hw_watchpoint_update(cpu
, i
);
6411 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6414 ARMCPU
*cpu
= env_archcpu(env
);
6418 * Bits [1:0] are RES0.
6420 * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
6421 * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
6422 * they contain the value written. It is CONSTRAINED UNPREDICTABLE
6423 * whether the RESS bits are ignored when comparing an address.
6425 * Therefore we are allowed to compare the entire register, which lets
6426 * us avoid considering whether or not FEAT_LVA is actually enabled.
6430 raw_write(env
, ri
, value
);
6431 hw_watchpoint_update(cpu
, i
);
6434 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6437 ARMCPU
*cpu
= env_archcpu(env
);
6440 raw_write(env
, ri
, value
);
6441 hw_watchpoint_update(cpu
, i
);
6444 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6446 CPUARMState
*env
= &cpu
->env
;
6447 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6448 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6453 if (env
->cpu_breakpoint
[n
]) {
6454 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6455 env
->cpu_breakpoint
[n
] = NULL
;
6458 if (!extract64(bcr
, 0, 1)) {
6459 /* E bit clear : watchpoint disabled */
6463 bt
= extract64(bcr
, 20, 4);
6466 case 4: /* unlinked address mismatch (reserved if AArch64) */
6467 case 5: /* linked address mismatch (reserved if AArch64) */
6468 qemu_log_mask(LOG_UNIMP
,
6469 "arm: address mismatch breakpoint types not implemented\n");
6471 case 0: /* unlinked address match */
6472 case 1: /* linked address match */
6475 * Bits [1:0] are RES0.
6477 * It is IMPLEMENTATION DEFINED whether bits [63:49]
6478 * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
6479 * of the VA field ([48] or [52] for FEAT_LVA), or whether the
6480 * value is read as written. It is CONSTRAINED UNPREDICTABLE
6481 * whether the RESS bits are ignored when comparing an address.
6482 * Therefore we are allowed to compare the entire register, which
6483 * lets us avoid considering whether FEAT_LVA is actually enabled.
6485 * The BAS field is used to allow setting breakpoints on 16-bit
6486 * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6487 * a bp will fire if the addresses covered by the bp and the addresses
6488 * covered by the insn overlap but the insn doesn't start at the
6489 * start of the bp address range. We choose to require the insn and
6490 * the bp to have the same address. The constraints on writing to
6491 * BAS enforced in dbgbcr_write mean we have only four cases:
6492 * 0b0000 => no breakpoint
6493 * 0b0011 => breakpoint on addr
6494 * 0b1100 => breakpoint on addr + 2
6495 * 0b1111 => breakpoint on addr
6496 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6498 int bas
= extract64(bcr
, 5, 4);
6508 case 2: /* unlinked context ID match */
6509 case 8: /* unlinked VMID match (reserved if no EL2) */
6510 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6511 qemu_log_mask(LOG_UNIMP
,
6512 "arm: unlinked context breakpoint types not implemented\n");
6514 case 9: /* linked VMID match (reserved if no EL2) */
6515 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6516 case 3: /* linked context ID match */
6518 /* We must generate no events for Linked context matches (unless
6519 * they are linked to by some other bp/wp, which is handled in
6520 * updates for the linking bp/wp). We choose to also generate no events
6521 * for reserved values.
6526 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6529 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6532 CPUARMState
*env
= &cpu
->env
;
6534 /* Completely clear out existing QEMU breakpoints and our array, to
6535 * avoid possible stale entries following migration load.
6537 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6538 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6540 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6541 hw_breakpoint_update(cpu
, i
);
6545 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6548 ARMCPU
*cpu
= env_archcpu(env
);
6551 raw_write(env
, ri
, value
);
6552 hw_breakpoint_update(cpu
, i
);
6555 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6558 ARMCPU
*cpu
= env_archcpu(env
);
6561 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6564 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6565 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6567 raw_write(env
, ri
, value
);
6568 hw_breakpoint_update(cpu
, i
);
6571 static void define_debug_regs(ARMCPU
*cpu
)
6573 /* Define v7 and v8 architectural debug registers.
6574 * These are just dummy implementations for now.
6577 int wrps
, brps
, ctx_cmps
;
6580 * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
6581 * use AArch32. Given that bit 15 is RES1, if the value is 0 then
6582 * the register must not exist for this cpu.
6584 if (cpu
->isar
.dbgdidr
!= 0) {
6585 ARMCPRegInfo dbgdidr
= {
6586 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0,
6587 .opc1
= 0, .opc2
= 0,
6588 .access
= PL0_R
, .accessfn
= access_tda
,
6589 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->isar
.dbgdidr
,
6591 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6594 brps
= arm_num_brps(cpu
);
6595 wrps
= arm_num_wrps(cpu
);
6596 ctx_cmps
= arm_num_ctx_cmps(cpu
);
6598 assert(ctx_cmps
<= brps
);
6600 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6602 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6603 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6606 for (i
= 0; i
< brps
; i
++) {
6607 char *dbgbvr_el1_name
= g_strdup_printf("DBGBVR%d_EL1", i
);
6608 char *dbgbcr_el1_name
= g_strdup_printf("DBGBCR%d_EL1", i
);
6609 ARMCPRegInfo dbgregs
[] = {
6610 { .name
= dbgbvr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6611 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6612 .access
= PL1_RW
, .accessfn
= access_tda
,
6613 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6614 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6616 { .name
= dbgbcr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6617 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6618 .access
= PL1_RW
, .accessfn
= access_tda
,
6619 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6620 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6623 define_arm_cp_regs(cpu
, dbgregs
);
6624 g_free(dbgbvr_el1_name
);
6625 g_free(dbgbcr_el1_name
);
6628 for (i
= 0; i
< wrps
; i
++) {
6629 char *dbgwvr_el1_name
= g_strdup_printf("DBGWVR%d_EL1", i
);
6630 char *dbgwcr_el1_name
= g_strdup_printf("DBGWCR%d_EL1", i
);
6631 ARMCPRegInfo dbgregs
[] = {
6632 { .name
= dbgwvr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6633 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6634 .access
= PL1_RW
, .accessfn
= access_tda
,
6635 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6636 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6638 { .name
= dbgwcr_el1_name
, .state
= ARM_CP_STATE_BOTH
,
6639 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6640 .access
= PL1_RW
, .accessfn
= access_tda
,
6641 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6642 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6645 define_arm_cp_regs(cpu
, dbgregs
);
6646 g_free(dbgwvr_el1_name
);
6647 g_free(dbgwcr_el1_name
);
6651 static void define_pmu_regs(ARMCPU
*cpu
)
6654 * v7 performance monitor control register: same implementor
6655 * field as main ID register, and we implement four counters in
6656 * addition to the cycle count register.
6658 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
6659 ARMCPRegInfo pmcr
= {
6660 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6662 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6663 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6664 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6665 .raw_writefn
= raw_write
,
6667 ARMCPRegInfo pmcr64
= {
6668 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6669 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6670 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6672 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6673 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
6674 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6677 define_one_arm_cp_reg(cpu
, &pmcr
);
6678 define_one_arm_cp_reg(cpu
, &pmcr64
);
6679 for (i
= 0; i
< pmcrn
; i
++) {
6680 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6681 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6682 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6683 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6684 ARMCPRegInfo pmev_regs
[] = {
6685 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6686 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6687 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6688 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6689 .accessfn
= pmreg_access_xevcntr
},
6690 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6691 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6692 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
6694 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6695 .raw_readfn
= pmevcntr_rawread
,
6696 .raw_writefn
= pmevcntr_rawwrite
},
6697 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6698 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6699 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6700 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6701 .accessfn
= pmreg_access
},
6702 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6703 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6704 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6706 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6707 .raw_writefn
= pmevtyper_rawwrite
},
6709 define_arm_cp_regs(cpu
, pmev_regs
);
6710 g_free(pmevcntr_name
);
6711 g_free(pmevcntr_el0_name
);
6712 g_free(pmevtyper_name
);
6713 g_free(pmevtyper_el0_name
);
6715 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6716 ARMCPRegInfo v81_pmu_regs
[] = {
6717 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6718 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6719 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6720 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6721 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6722 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6723 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6724 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6726 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6728 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6729 static const ARMCPRegInfo v84_pmmir
= {
6730 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6731 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6732 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6735 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6739 /* We don't know until after realize whether there's a GICv3
6740 * attached, and that is what registers the gicv3 sysregs.
6741 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6744 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6746 ARMCPU
*cpu
= env_archcpu(env
);
6747 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6749 if (env
->gicv3state
) {
6755 #ifndef CONFIG_USER_ONLY
6756 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6758 ARMCPU
*cpu
= env_archcpu(env
);
6759 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6761 if (env
->gicv3state
) {
6768 /* Shared logic between LORID and the rest of the LOR* registers.
6769 * Secure state exclusion has already been dealt with.
6771 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6772 const ARMCPRegInfo
*ri
, bool isread
)
6774 int el
= arm_current_el(env
);
6776 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6777 return CP_ACCESS_TRAP_EL2
;
6779 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6780 return CP_ACCESS_TRAP_EL3
;
6782 return CP_ACCESS_OK
;
6785 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6786 const ARMCPRegInfo
*ri
, bool isread
)
6788 if (arm_is_secure_below_el3(env
)) {
6789 /* Access denied in secure mode. */
6790 return CP_ACCESS_TRAP
;
6792 return access_lor_ns(env
, ri
, isread
);
6796 * A trivial implementation of ARMv8.1-LOR leaves all of these
6797 * registers fixed at 0, which indicates that there are zero
6798 * supported Limited Ordering regions.
6800 static const ARMCPRegInfo lor_reginfo
[] = {
6801 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6802 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6803 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6804 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6805 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6806 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6807 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6808 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6809 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6810 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6811 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6812 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6813 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6814 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6815 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6816 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6817 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6818 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6819 .access
= PL1_R
, .accessfn
= access_lor_ns
,
6820 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6823 #ifdef TARGET_AARCH64
6824 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6827 int el
= arm_current_el(env
);
6830 arm_is_el2_enabled(env
) &&
6831 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6832 return CP_ACCESS_TRAP_EL2
;
6835 arm_feature(env
, ARM_FEATURE_EL3
) &&
6836 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6837 return CP_ACCESS_TRAP_EL3
;
6839 return CP_ACCESS_OK
;
6842 static const ARMCPRegInfo pauth_reginfo
[] = {
6843 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6844 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6845 .access
= PL1_RW
, .accessfn
= access_pauth
,
6846 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6847 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6848 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6849 .access
= PL1_RW
, .accessfn
= access_pauth
,
6850 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6851 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6852 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6853 .access
= PL1_RW
, .accessfn
= access_pauth
,
6854 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6855 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6856 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6857 .access
= PL1_RW
, .accessfn
= access_pauth
,
6858 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6859 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6860 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6861 .access
= PL1_RW
, .accessfn
= access_pauth
,
6862 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6863 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6864 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6865 .access
= PL1_RW
, .accessfn
= access_pauth
,
6866 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6867 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6868 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6869 .access
= PL1_RW
, .accessfn
= access_pauth
,
6870 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6871 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6872 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6873 .access
= PL1_RW
, .accessfn
= access_pauth
,
6874 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6875 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6876 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6877 .access
= PL1_RW
, .accessfn
= access_pauth
,
6878 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6879 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6880 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6881 .access
= PL1_RW
, .accessfn
= access_pauth
,
6882 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6885 static const ARMCPRegInfo tlbirange_reginfo
[] = {
6886 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
6887 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
6888 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6889 .writefn
= tlbi_aa64_rvae1is_write
},
6890 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
6891 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
6892 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6893 .writefn
= tlbi_aa64_rvae1is_write
},
6894 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
6895 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
6896 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6897 .writefn
= tlbi_aa64_rvae1is_write
},
6898 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
6899 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
6900 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6901 .writefn
= tlbi_aa64_rvae1is_write
},
6902 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
6903 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
6904 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6905 .writefn
= tlbi_aa64_rvae1is_write
},
6906 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
6907 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
6908 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6909 .writefn
= tlbi_aa64_rvae1is_write
},
6910 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
6911 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
6912 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6913 .writefn
= tlbi_aa64_rvae1is_write
},
6914 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
6915 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
6916 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6917 .writefn
= tlbi_aa64_rvae1is_write
},
6918 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
6919 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
6920 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6921 .writefn
= tlbi_aa64_rvae1_write
},
6922 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
6923 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
6924 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6925 .writefn
= tlbi_aa64_rvae1_write
},
6926 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
6927 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
6928 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6929 .writefn
= tlbi_aa64_rvae1_write
},
6930 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
6931 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
6932 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6933 .writefn
= tlbi_aa64_rvae1_write
},
6934 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
6935 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
6936 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6937 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
6938 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
6939 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6940 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
6941 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
6942 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6943 .writefn
= tlbi_aa64_rvae2is_write
},
6944 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
6945 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
6946 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6947 .writefn
= tlbi_aa64_rvae2is_write
},
6948 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
6949 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
6950 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6951 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
6952 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
6953 .access
= PL2_W
, .type
= ARM_CP_NOP
},
6954 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
6955 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
6956 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6957 .writefn
= tlbi_aa64_rvae2is_write
},
6958 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
6959 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
6960 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6961 .writefn
= tlbi_aa64_rvae2is_write
},
6962 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
6963 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
6964 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6965 .writefn
= tlbi_aa64_rvae2_write
},
6966 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
6967 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
6968 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6969 .writefn
= tlbi_aa64_rvae2_write
},
6970 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
6971 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
6972 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6973 .writefn
= tlbi_aa64_rvae3is_write
},
6974 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
6975 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
6976 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6977 .writefn
= tlbi_aa64_rvae3is_write
},
6978 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
6979 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
6980 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6981 .writefn
= tlbi_aa64_rvae3is_write
},
6982 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
6983 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
6984 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6985 .writefn
= tlbi_aa64_rvae3is_write
},
6986 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
6987 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
6988 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6989 .writefn
= tlbi_aa64_rvae3_write
},
6990 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
6991 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
6992 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6993 .writefn
= tlbi_aa64_rvae3_write
},
6996 static const ARMCPRegInfo tlbios_reginfo
[] = {
6997 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
6998 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
6999 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7000 .writefn
= tlbi_aa64_vmalle1is_write
},
7001 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7002 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7003 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7004 .writefn
= tlbi_aa64_vae1is_write
},
7005 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7006 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7007 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7008 .writefn
= tlbi_aa64_vmalle1is_write
},
7009 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7010 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7011 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7012 .writefn
= tlbi_aa64_vae1is_write
},
7013 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7014 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7015 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7016 .writefn
= tlbi_aa64_vae1is_write
},
7017 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7018 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7019 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
7020 .writefn
= tlbi_aa64_vae1is_write
},
7021 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7022 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7023 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7024 .writefn
= tlbi_aa64_alle2is_write
},
7025 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7026 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7027 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7028 .writefn
= tlbi_aa64_vae2is_write
},
7029 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7030 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7031 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7032 .writefn
= tlbi_aa64_alle1is_write
},
7033 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7034 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7035 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7036 .writefn
= tlbi_aa64_vae2is_write
},
7037 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7038 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7039 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7040 .writefn
= tlbi_aa64_alle1is_write
},
7041 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7042 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7043 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7044 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7045 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7046 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7047 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7048 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7049 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7050 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7051 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7052 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7053 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7054 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7055 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7056 .writefn
= tlbi_aa64_alle3is_write
},
7057 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7058 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7059 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7060 .writefn
= tlbi_aa64_vae3is_write
},
7061 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7062 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7063 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7064 .writefn
= tlbi_aa64_vae3is_write
},
7067 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7072 /* Success sets NZCV = 0000. */
7073 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7075 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7077 * ??? Failed, for unknown reasons in the crypto subsystem.
7078 * The best we can do is log the reason and return the
7079 * timed-out indication to the guest. There is no reason
7080 * we know to expect this failure to be transitory, so the
7081 * guest may well hang retrying the operation.
7083 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7084 ri
->name
, error_get_pretty(err
));
7087 env
->ZF
= 0; /* NZCF = 0100 */
7093 /* We do not support re-seeding, so the two registers operate the same. */
7094 static const ARMCPRegInfo rndr_reginfo
[] = {
7095 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7096 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7097 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7098 .access
= PL0_R
, .readfn
= rndr_readfn
},
7099 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7100 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7101 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7102 .access
= PL0_R
, .readfn
= rndr_readfn
},
7105 #ifndef CONFIG_USER_ONLY
7106 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7109 ARMCPU
*cpu
= env_archcpu(env
);
7110 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7111 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7112 uint64_t vaddr_in
= (uint64_t) value
;
7113 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7115 int mem_idx
= cpu_mmu_index(env
, false);
7117 /* This won't be crossing page boundaries */
7118 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7124 /* RCU lock is already being held */
7125 mr
= memory_region_from_host(haddr
, &offset
);
7128 memory_region_writeback(mr
, offset
, dline_size
);
7133 static const ARMCPRegInfo dcpop_reg
[] = {
7134 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7135 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7136 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7137 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7140 static const ARMCPRegInfo dcpodp_reg
[] = {
7141 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7142 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7143 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7144 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7146 #endif /*CONFIG_USER_ONLY*/
7148 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7151 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7152 return CP_ACCESS_TRAP_EL2
;
7155 return CP_ACCESS_OK
;
7158 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7161 int el
= arm_current_el(env
);
7163 if (el
< 2 && arm_is_el2_enabled(env
)) {
7164 uint64_t hcr
= arm_hcr_el2_eff(env
);
7165 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7166 return CP_ACCESS_TRAP_EL2
;
7170 arm_feature(env
, ARM_FEATURE_EL3
) &&
7171 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7172 return CP_ACCESS_TRAP_EL3
;
7174 return CP_ACCESS_OK
;
7177 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7179 return env
->pstate
& PSTATE_TCO
;
7182 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7184 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7187 static const ARMCPRegInfo mte_reginfo
[] = {
7188 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7189 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7190 .access
= PL1_RW
, .accessfn
= access_mte
,
7191 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7192 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7193 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7194 .access
= PL1_RW
, .accessfn
= access_mte
,
7195 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7196 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7197 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7198 .access
= PL2_RW
, .accessfn
= access_mte
,
7199 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7200 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7201 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7203 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7204 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7205 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7206 .access
= PL1_RW
, .accessfn
= access_mte
,
7207 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7208 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7209 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7210 .access
= PL1_RW
, .accessfn
= access_mte
,
7211 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7212 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7213 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7214 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7215 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7216 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7217 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7218 .type
= ARM_CP_NO_RAW
,
7219 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7220 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7221 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7222 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7223 .accessfn
= aa64_cacheop_poc_access
},
7224 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7225 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7226 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7227 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7228 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7229 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7230 .accessfn
= aa64_cacheop_poc_access
},
7231 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7232 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7233 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7234 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7235 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7236 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7237 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7238 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7239 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7240 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7241 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7242 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7243 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7244 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7245 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7248 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7249 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7250 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7251 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7254 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7255 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7256 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7257 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7258 .accessfn
= aa64_cacheop_poc_access
},
7259 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7260 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7261 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7262 .accessfn
= aa64_cacheop_poc_access
},
7263 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7264 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7265 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7266 .accessfn
= aa64_cacheop_poc_access
},
7267 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7268 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7269 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7270 .accessfn
= aa64_cacheop_poc_access
},
7271 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7272 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7273 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7274 .accessfn
= aa64_cacheop_poc_access
},
7275 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7276 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7277 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7278 .accessfn
= aa64_cacheop_poc_access
},
7279 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7280 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7281 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7282 .accessfn
= aa64_cacheop_poc_access
},
7283 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7284 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7285 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7286 .accessfn
= aa64_cacheop_poc_access
},
7287 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7288 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7289 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7290 #ifndef CONFIG_USER_ONLY
7291 /* Avoid overhead of an access check that always passes in user-mode */
7292 .accessfn
= aa64_zva_access
,
7295 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7296 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7297 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7298 #ifndef CONFIG_USER_ONLY
7299 /* Avoid overhead of an access check that always passes in user-mode */
7300 .accessfn
= aa64_zva_access
,
7305 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7308 uint64_t hcr
= arm_hcr_el2_eff(env
);
7309 int el
= arm_current_el(env
);
7311 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7312 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7313 if (hcr
& HCR_TGE
) {
7314 return CP_ACCESS_TRAP_EL2
;
7316 return CP_ACCESS_TRAP
;
7318 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7319 return CP_ACCESS_TRAP_EL2
;
7321 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7322 return CP_ACCESS_TRAP_EL2
;
7325 && arm_feature(env
, ARM_FEATURE_EL3
)
7326 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7327 return CP_ACCESS_TRAP_EL3
;
7329 return CP_ACCESS_OK
;
7332 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7333 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7334 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7335 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7336 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7337 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7338 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7339 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7340 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7341 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7342 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7343 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7344 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7345 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7346 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7348 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7350 #endif /* TARGET_AARCH64 */
7352 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7355 int el
= arm_current_el(env
);
7358 uint64_t sctlr
= arm_sctlr(env
, el
);
7359 if (!(sctlr
& SCTLR_EnRCTX
)) {
7360 return CP_ACCESS_TRAP
;
7362 } else if (el
== 1) {
7363 uint64_t hcr
= arm_hcr_el2_eff(env
);
7365 return CP_ACCESS_TRAP_EL2
;
7368 return CP_ACCESS_OK
;
7371 static const ARMCPRegInfo predinv_reginfo
[] = {
7372 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7373 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7374 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7375 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7376 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7377 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7378 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7379 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7380 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7382 * Note the AArch32 opcodes have a different OPC1.
7384 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7385 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7386 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7387 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7388 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7389 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7390 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7391 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7392 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7395 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7397 /* Read the high 32 bits of the current CCSIDR */
7398 return extract64(ccsidr_read(env
, ri
), 32, 32);
7401 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7402 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7403 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7405 .accessfn
= access_aa64_tid2
,
7406 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7409 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7412 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7413 return CP_ACCESS_TRAP_EL2
;
7416 return CP_ACCESS_OK
;
7419 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7422 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7423 return access_aa64_tid3(env
, ri
, isread
);
7426 return CP_ACCESS_OK
;
7429 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7432 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7433 return CP_ACCESS_TRAP_EL2
;
7436 return CP_ACCESS_OK
;
7439 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
7440 const ARMCPRegInfo
*ri
, bool isread
)
7443 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
7444 * in v7A, not in v8A.
7446 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
7447 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
7448 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
7449 return CP_ACCESS_TRAP_EL2
;
7451 return CP_ACCESS_OK
;
7454 static const ARMCPRegInfo jazelle_regs
[] = {
7456 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7457 .access
= PL1_R
, .accessfn
= access_jazelle
,
7458 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7460 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7461 .accessfn
= access_joscr_jmcr
,
7462 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7464 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7465 .accessfn
= access_joscr_jmcr
,
7466 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7469 static const ARMCPRegInfo contextidr_el2
= {
7470 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7471 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7473 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
7476 static const ARMCPRegInfo vhe_reginfo
[] = {
7477 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7478 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7479 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7480 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7481 #ifndef CONFIG_USER_ONLY
7482 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7483 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7485 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7486 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7487 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7488 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7489 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7490 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7491 .resetfn
= gt_hv_timer_reset
,
7492 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7493 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7495 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7497 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7498 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7499 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7500 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7501 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7502 .access
= PL2_RW
, .accessfn
= e2h_access
,
7503 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7504 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7505 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7506 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7507 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7508 .access
= PL2_RW
, .accessfn
= e2h_access
,
7509 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7510 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7511 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7512 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7513 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7514 .access
= PL2_RW
, .accessfn
= e2h_access
,
7515 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7516 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7517 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7518 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7519 .access
= PL2_RW
, .accessfn
= e2h_access
,
7520 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7521 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7522 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7523 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7524 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7525 .access
= PL2_RW
, .accessfn
= e2h_access
,
7526 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7527 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7528 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7529 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7530 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7531 .access
= PL2_RW
, .accessfn
= e2h_access
,
7532 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7536 #ifndef CONFIG_USER_ONLY
7537 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7538 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7539 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7540 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7541 .writefn
= ats_write64
},
7542 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7543 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7544 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7545 .writefn
= ats_write64
},
7548 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7549 { .name
= "ATS1CPRP",
7550 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7551 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7552 .writefn
= ats_write
},
7553 { .name
= "ATS1CPWP",
7554 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7555 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7556 .writefn
= ats_write
},
7561 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7562 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7563 * is non-zero, which is never for ARMv7, optionally in ARMv8
7564 * and mandatorily for ARMv8.2 and up.
7565 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7566 * implementation is RAZ/WI we can ignore this detail, as we
7569 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7570 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7571 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7572 .access
= PL1_RW
, .accessfn
= access_tacr
,
7573 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7574 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7575 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7576 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7580 void register_cp_regs_for_features(ARMCPU
*cpu
)
7582 /* Register all the coprocessor registers based on feature bits */
7583 CPUARMState
*env
= &cpu
->env
;
7584 if (arm_feature(env
, ARM_FEATURE_M
)) {
7585 /* M profile has no coprocessor registers */
7589 define_arm_cp_regs(cpu
, cp_reginfo
);
7590 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7591 /* Must go early as it is full of wildcards that may be
7592 * overridden by later definitions.
7594 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7597 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7598 /* The ID registers all have impdef reset values */
7599 ARMCPRegInfo v6_idregs
[] = {
7600 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7601 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7602 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7603 .accessfn
= access_aa32_tid3
,
7604 .resetvalue
= cpu
->isar
.id_pfr0
},
7605 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7606 * the value of the GIC field until after we define these regs.
7608 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7609 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7610 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7611 .accessfn
= access_aa32_tid3
,
7612 .readfn
= id_pfr1_read
,
7613 .writefn
= arm_cp_write_ignore
},
7614 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7615 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7616 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7617 .accessfn
= access_aa32_tid3
,
7618 .resetvalue
= cpu
->isar
.id_dfr0
},
7619 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7620 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7621 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7622 .accessfn
= access_aa32_tid3
,
7623 .resetvalue
= cpu
->id_afr0
},
7624 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7625 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7626 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7627 .accessfn
= access_aa32_tid3
,
7628 .resetvalue
= cpu
->isar
.id_mmfr0
},
7629 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7630 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7631 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7632 .accessfn
= access_aa32_tid3
,
7633 .resetvalue
= cpu
->isar
.id_mmfr1
},
7634 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7635 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7636 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7637 .accessfn
= access_aa32_tid3
,
7638 .resetvalue
= cpu
->isar
.id_mmfr2
},
7639 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7640 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7641 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7642 .accessfn
= access_aa32_tid3
,
7643 .resetvalue
= cpu
->isar
.id_mmfr3
},
7644 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7645 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7646 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7647 .accessfn
= access_aa32_tid3
,
7648 .resetvalue
= cpu
->isar
.id_isar0
},
7649 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7650 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7651 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7652 .accessfn
= access_aa32_tid3
,
7653 .resetvalue
= cpu
->isar
.id_isar1
},
7654 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7655 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7656 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7657 .accessfn
= access_aa32_tid3
,
7658 .resetvalue
= cpu
->isar
.id_isar2
},
7659 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7660 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7661 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7662 .accessfn
= access_aa32_tid3
,
7663 .resetvalue
= cpu
->isar
.id_isar3
},
7664 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7665 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7666 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7667 .accessfn
= access_aa32_tid3
,
7668 .resetvalue
= cpu
->isar
.id_isar4
},
7669 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7670 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7671 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7672 .accessfn
= access_aa32_tid3
,
7673 .resetvalue
= cpu
->isar
.id_isar5
},
7674 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7675 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7676 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7677 .accessfn
= access_aa32_tid3
,
7678 .resetvalue
= cpu
->isar
.id_mmfr4
},
7679 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7680 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7681 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7682 .accessfn
= access_aa32_tid3
,
7683 .resetvalue
= cpu
->isar
.id_isar6
},
7685 define_arm_cp_regs(cpu
, v6_idregs
);
7686 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7688 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7690 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7691 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7693 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7694 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7695 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7697 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7698 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7700 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7701 ARMCPRegInfo clidr
= {
7702 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7703 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7704 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7705 .accessfn
= access_aa64_tid2
,
7706 .resetvalue
= cpu
->clidr
7708 define_one_arm_cp_reg(cpu
, &clidr
);
7709 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7710 define_debug_regs(cpu
);
7711 define_pmu_regs(cpu
);
7713 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7715 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7716 /* AArch64 ID registers, which all have impdef reset values.
7717 * Note that within the ID register ranges the unused slots
7718 * must all RAZ, not UNDEF; future architecture versions may
7719 * define new registers here.
7721 ARMCPRegInfo v8_idregs
[] = {
7723 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7724 * emulation because we don't know the right value for the
7725 * GIC field until after we define these regs.
7727 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7728 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7730 #ifdef CONFIG_USER_ONLY
7731 .type
= ARM_CP_CONST
,
7732 .resetvalue
= cpu
->isar
.id_aa64pfr0
7734 .type
= ARM_CP_NO_RAW
,
7735 .accessfn
= access_aa64_tid3
,
7736 .readfn
= id_aa64pfr0_read
,
7737 .writefn
= arm_cp_write_ignore
7740 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7741 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7742 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7743 .accessfn
= access_aa64_tid3
,
7744 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7745 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7746 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7747 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7748 .accessfn
= access_aa64_tid3
,
7750 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7751 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7752 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7753 .accessfn
= access_aa64_tid3
,
7755 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7756 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7757 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7758 .accessfn
= access_aa64_tid3
,
7759 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
7760 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7761 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7762 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7763 .accessfn
= access_aa64_tid3
,
7764 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
7765 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7766 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7767 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7768 .accessfn
= access_aa64_tid3
,
7770 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7771 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7772 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7773 .accessfn
= access_aa64_tid3
,
7775 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7776 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7777 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7778 .accessfn
= access_aa64_tid3
,
7779 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7780 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7781 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7782 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7783 .accessfn
= access_aa64_tid3
,
7784 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7785 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7786 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7787 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7788 .accessfn
= access_aa64_tid3
,
7790 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7791 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7792 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7793 .accessfn
= access_aa64_tid3
,
7795 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7796 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7797 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7798 .accessfn
= access_aa64_tid3
,
7799 .resetvalue
= cpu
->id_aa64afr0
},
7800 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7801 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7802 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7803 .accessfn
= access_aa64_tid3
,
7804 .resetvalue
= cpu
->id_aa64afr1
},
7805 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7806 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7807 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7808 .accessfn
= access_aa64_tid3
,
7810 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7811 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7812 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7813 .accessfn
= access_aa64_tid3
,
7815 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7816 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7817 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7818 .accessfn
= access_aa64_tid3
,
7819 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7820 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7821 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7822 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7823 .accessfn
= access_aa64_tid3
,
7824 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7825 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7826 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7827 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7828 .accessfn
= access_aa64_tid3
,
7830 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7831 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7832 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7833 .accessfn
= access_aa64_tid3
,
7835 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7836 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7837 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7838 .accessfn
= access_aa64_tid3
,
7840 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7841 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7842 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7843 .accessfn
= access_aa64_tid3
,
7845 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7846 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7847 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7848 .accessfn
= access_aa64_tid3
,
7850 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7851 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7852 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7853 .accessfn
= access_aa64_tid3
,
7855 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7856 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7857 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7858 .accessfn
= access_aa64_tid3
,
7859 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7860 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7861 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7862 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7863 .accessfn
= access_aa64_tid3
,
7864 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7865 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7866 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7867 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7868 .accessfn
= access_aa64_tid3
,
7869 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7870 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7871 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7872 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7873 .accessfn
= access_aa64_tid3
,
7875 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7876 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7877 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7878 .accessfn
= access_aa64_tid3
,
7880 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7881 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7882 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7883 .accessfn
= access_aa64_tid3
,
7885 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7886 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7887 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7888 .accessfn
= access_aa64_tid3
,
7890 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7891 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7892 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7893 .accessfn
= access_aa64_tid3
,
7895 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7896 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7897 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7898 .accessfn
= access_aa64_tid3
,
7899 .resetvalue
= cpu
->isar
.mvfr0
},
7900 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7901 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7902 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7903 .accessfn
= access_aa64_tid3
,
7904 .resetvalue
= cpu
->isar
.mvfr1
},
7905 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7906 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7907 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7908 .accessfn
= access_aa64_tid3
,
7909 .resetvalue
= cpu
->isar
.mvfr2
},
7910 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7911 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7912 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7913 .accessfn
= access_aa64_tid3
,
7915 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
7916 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7917 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7918 .accessfn
= access_aa64_tid3
,
7919 .resetvalue
= cpu
->isar
.id_pfr2
},
7920 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7921 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7922 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7923 .accessfn
= access_aa64_tid3
,
7925 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7926 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7927 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7928 .accessfn
= access_aa64_tid3
,
7930 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7931 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7932 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7933 .accessfn
= access_aa64_tid3
,
7935 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7936 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7937 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7938 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7939 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7940 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7941 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7942 .resetvalue
= cpu
->pmceid0
},
7943 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7944 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7945 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7946 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7947 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7948 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7949 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7950 .resetvalue
= cpu
->pmceid1
},
7952 #ifdef CONFIG_USER_ONLY
7953 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7954 { .name
= "ID_AA64PFR0_EL1",
7955 .exported_bits
= 0x000f000f00ff0000,
7956 .fixed_bits
= 0x0000000000000011 },
7957 { .name
= "ID_AA64PFR1_EL1",
7958 .exported_bits
= 0x00000000000000f0 },
7959 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7961 { .name
= "ID_AA64ZFR0_EL1" },
7962 { .name
= "ID_AA64MMFR0_EL1",
7963 .fixed_bits
= 0x00000000ff000000 },
7964 { .name
= "ID_AA64MMFR1_EL1" },
7965 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7967 { .name
= "ID_AA64DFR0_EL1",
7968 .fixed_bits
= 0x0000000000000006 },
7969 { .name
= "ID_AA64DFR1_EL1" },
7970 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7972 { .name
= "ID_AA64AFR*",
7974 { .name
= "ID_AA64ISAR0_EL1",
7975 .exported_bits
= 0x00fffffff0fffff0 },
7976 { .name
= "ID_AA64ISAR1_EL1",
7977 .exported_bits
= 0x000000f0ffffffff },
7978 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7981 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7983 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7984 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7985 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7986 ARMCPRegInfo rvbar
= {
7987 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7988 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7990 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
7992 define_one_arm_cp_reg(cpu
, &rvbar
);
7994 define_arm_cp_regs(cpu
, v8_idregs
);
7995 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7999 * Register the base EL2 cpregs.
8000 * Pre v8, these registers are implemented only as part of the
8001 * Virtualization Extensions (EL2 present). Beginning with v8,
8002 * if EL2 is missing but EL3 is enabled, mostly these become
8003 * RES0 from EL3, with some specific exceptions.
8005 if (arm_feature(env
, ARM_FEATURE_EL2
)
8006 || (arm_feature(env
, ARM_FEATURE_EL3
)
8007 && arm_feature(env
, ARM_FEATURE_V8
))) {
8008 uint64_t vmpidr_def
= mpidr_read_val(env
);
8009 ARMCPRegInfo vpidr_regs
[] = {
8010 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8011 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8012 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8013 .resetvalue
= cpu
->midr
,
8014 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8015 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8016 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8017 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8018 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8019 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8020 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8021 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8022 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8023 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8024 .resetvalue
= vmpidr_def
,
8025 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8026 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8027 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8028 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8029 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8030 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8031 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8034 * The only field of MDCR_EL2 that has a defined architectural reset
8035 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8037 ARMCPRegInfo mdcr_el2
= {
8038 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
8039 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8040 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8041 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8043 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8044 define_arm_cp_regs(cpu
, vpidr_regs
);
8045 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8046 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8047 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8049 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8050 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8052 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
8053 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8054 ARMCPRegInfo rvbar
= {
8055 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8056 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8058 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8060 define_one_arm_cp_reg(cpu
, &rvbar
);
8064 /* Register the base EL3 cpregs. */
8065 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8066 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8067 ARMCPRegInfo el3_regs
[] = {
8068 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8069 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8071 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
),
8073 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8074 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8076 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8077 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8078 .resetvalue
= cpu
->reset_sctlr
},
8081 define_arm_cp_regs(cpu
, el3_regs
);
8083 /* The behaviour of NSACR is sufficiently various that we don't
8084 * try to describe it in a single reginfo:
8085 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8086 * reads as constant 0xc00 from NS EL1 and NS EL2
8087 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8088 * if v7 without EL3, register doesn't exist
8089 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8091 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8092 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8093 static const ARMCPRegInfo nsacr
= {
8094 .name
= "NSACR", .type
= ARM_CP_CONST
,
8095 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8096 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8099 define_one_arm_cp_reg(cpu
, &nsacr
);
8101 static const ARMCPRegInfo nsacr
= {
8103 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8104 .access
= PL3_RW
| PL1_R
,
8106 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8108 define_one_arm_cp_reg(cpu
, &nsacr
);
8111 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8112 static const ARMCPRegInfo nsacr
= {
8113 .name
= "NSACR", .type
= ARM_CP_CONST
,
8114 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8118 define_one_arm_cp_reg(cpu
, &nsacr
);
8122 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8123 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8124 /* PMSAv6 not implemented */
8125 assert(arm_feature(env
, ARM_FEATURE_V7
));
8126 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8127 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8129 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8132 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8133 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8134 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8135 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8136 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8139 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8140 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8142 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8143 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8145 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8146 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8148 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8149 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8151 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8152 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8154 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8155 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8157 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8158 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8160 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8161 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8163 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8164 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8166 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8167 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8169 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8170 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8172 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8173 define_arm_cp_regs(cpu
, jazelle_regs
);
8175 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
8176 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8177 * be read-only (ie write causes UNDEF exception).
8180 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8181 /* Pre-v8 MIDR space.
8182 * Note that the MIDR isn't a simple constant register because
8183 * of the TI925 behaviour where writes to another register can
8184 * cause the MIDR value to change.
8186 * Unimplemented registers in the c15 0 0 0 space default to
8187 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8188 * and friends override accordingly.
8191 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8192 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8193 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8194 .readfn
= midr_read
,
8195 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8196 .type
= ARM_CP_OVERRIDE
},
8197 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8199 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8200 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8202 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8203 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8205 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8206 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8208 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8209 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8211 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8212 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8214 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8215 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8216 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8217 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8218 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8219 .readfn
= midr_read
},
8220 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
8221 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8222 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8223 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8224 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8225 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8226 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8227 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8228 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8230 .accessfn
= access_aa64_tid1
,
8231 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8233 ARMCPRegInfo id_cp_reginfo
[] = {
8234 /* These are common to v8 and pre-v8 */
8236 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
8237 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8238 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8239 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8240 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8241 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8242 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8243 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8245 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8247 .accessfn
= access_aa32_tid1
,
8248 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8250 /* TLBTR is specific to VMSA */
8251 ARMCPRegInfo id_tlbtr_reginfo
= {
8253 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8255 .accessfn
= access_aa32_tid1
,
8256 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8258 /* MPUIR is specific to PMSA V6+ */
8259 ARMCPRegInfo id_mpuir_reginfo
= {
8261 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8262 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8263 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8265 static const ARMCPRegInfo crn0_wi_reginfo
= {
8266 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8267 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8268 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8270 #ifdef CONFIG_USER_ONLY
8271 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8272 { .name
= "MIDR_EL1",
8273 .exported_bits
= 0x00000000ffffffff },
8274 { .name
= "REVIDR_EL1" },
8276 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8278 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8279 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8281 /* Register the blanket "writes ignored" value first to cover the
8282 * whole space. Then update the specific ID registers to allow write
8283 * access, so that they ignore writes rather than causing them to
8286 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8287 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
8288 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
8290 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
8291 id_cp_reginfo
[i
].access
= PL1_RW
;
8293 id_mpuir_reginfo
.access
= PL1_RW
;
8294 id_tlbtr_reginfo
.access
= PL1_RW
;
8296 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8297 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8299 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8301 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8302 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8303 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8304 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8305 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8309 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8310 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8311 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8312 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8313 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8315 #ifdef CONFIG_USER_ONLY
8316 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8317 { .name
= "MPIDR_EL1",
8318 .fixed_bits
= 0x0000000080000000 },
8320 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8322 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8325 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8326 ARMCPRegInfo auxcr_reginfo
[] = {
8327 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8328 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8329 .access
= PL1_RW
, .accessfn
= access_tacr
,
8330 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8331 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8332 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8333 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8335 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8336 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8337 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8340 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8341 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8342 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8346 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8348 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8349 * There are two flavours:
8350 * (1) older 32-bit only cores have a simple 32-bit CBAR
8351 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8352 * 32-bit register visible to AArch32 at a different encoding
8353 * to the "flavour 1" register and with the bits rearranged to
8354 * be able to squash a 64-bit address into the 32-bit view.
8355 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8356 * in future if we support AArch32-only configs of some of the
8357 * AArch64 cores we might need to add a specific feature flag
8358 * to indicate cores with "flavour 2" CBAR.
8360 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8361 /* 32 bit view is [31:18] 0...0 [43:32]. */
8362 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8363 | extract64(cpu
->reset_cbar
, 32, 12);
8364 ARMCPRegInfo cbar_reginfo
[] = {
8366 .type
= ARM_CP_CONST
,
8367 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8368 .access
= PL1_R
, .resetvalue
= cbar32
},
8369 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8370 .type
= ARM_CP_CONST
,
8371 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8372 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8374 /* We don't implement a r/w 64 bit CBAR currently */
8375 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8376 define_arm_cp_regs(cpu
, cbar_reginfo
);
8378 ARMCPRegInfo cbar
= {
8380 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8381 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8382 .fieldoffset
= offsetof(CPUARMState
,
8383 cp15
.c15_config_base_address
)
8385 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8386 cbar
.access
= PL1_R
;
8387 cbar
.fieldoffset
= 0;
8388 cbar
.type
= ARM_CP_CONST
;
8390 define_one_arm_cp_reg(cpu
, &cbar
);
8394 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8395 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
8396 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8397 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8398 .access
= PL1_RW
, .writefn
= vbar_write
,
8399 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8400 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8403 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8406 /* Generic registers whose values depend on the implementation */
8408 ARMCPRegInfo sctlr
= {
8409 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8410 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8411 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8412 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8413 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8414 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8415 .raw_writefn
= raw_write
,
8417 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8418 /* Normally we would always end the TB on an SCTLR write, but Linux
8419 * arch/arm/mach-pxa/sleep.S expects two instructions following
8420 * an MMU enable to execute from cache. Imitate this behaviour.
8422 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8424 define_one_arm_cp_reg(cpu
, &sctlr
);
8427 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8428 define_arm_cp_regs(cpu
, lor_reginfo
);
8430 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8431 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8433 #ifndef CONFIG_USER_ONLY
8434 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8435 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8437 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8438 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8441 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8442 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8445 if (cpu_isar_feature(aa64_dit
, cpu
)) {
8446 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
8448 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
8449 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
8451 if (cpu_isar_feature(any_ras
, cpu
)) {
8452 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
8455 if (cpu_isar_feature(aa64_vh
, cpu
) ||
8456 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
8457 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
8459 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8460 define_arm_cp_regs(cpu
, vhe_reginfo
);
8463 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8464 define_arm_cp_regs(cpu
, zcr_reginfo
);
8467 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
8468 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
8471 #ifdef TARGET_AARCH64
8472 if (cpu_isar_feature(aa64_sme
, cpu
)) {
8473 define_arm_cp_regs(cpu
, sme_reginfo
);
8475 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8476 define_arm_cp_regs(cpu
, pauth_reginfo
);
8478 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8479 define_arm_cp_regs(cpu
, rndr_reginfo
);
8481 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
8482 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
8484 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
8485 define_arm_cp_regs(cpu
, tlbios_reginfo
);
8487 #ifndef CONFIG_USER_ONLY
8488 /* Data Cache clean instructions up to PoP */
8489 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8490 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8492 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8493 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8496 #endif /*CONFIG_USER_ONLY*/
8499 * If full MTE is enabled, add all of the system registers.
8500 * If only "instructions available at EL0" are enabled,
8501 * then define only a RAZ/WI version of PSTATE.TCO.
8503 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8504 define_arm_cp_regs(cpu
, mte_reginfo
);
8505 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8506 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8507 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8508 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8511 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
8512 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
8516 if (cpu_isar_feature(any_predinv
, cpu
)) {
8517 define_arm_cp_regs(cpu
, predinv_reginfo
);
8520 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8521 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8524 #ifndef CONFIG_USER_ONLY
8526 * Register redirections and aliases must be done last,
8527 * after the registers from the other extensions have been defined.
8529 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8530 define_arm_vh_e2h_redirects_aliases(cpu
);
8535 /* Sort alphabetically by type name, except for "any". */
8536 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8538 ObjectClass
*class_a
= (ObjectClass
*)a
;
8539 ObjectClass
*class_b
= (ObjectClass
*)b
;
8540 const char *name_a
, *name_b
;
8542 name_a
= object_class_get_name(class_a
);
8543 name_b
= object_class_get_name(class_b
);
8544 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8546 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8549 return strcmp(name_a
, name_b
);
8553 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8555 ObjectClass
*oc
= data
;
8556 const char *typename
;
8559 typename
= object_class_get_name(oc
);
8560 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8561 qemu_printf(" %s\n", name
);
8565 void arm_cpu_list(void)
8569 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8570 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8571 qemu_printf("Available CPUs:\n");
8572 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8576 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8578 ObjectClass
*oc
= data
;
8579 CpuDefinitionInfoList
**cpu_list
= user_data
;
8580 CpuDefinitionInfo
*info
;
8581 const char *typename
;
8583 typename
= object_class_get_name(oc
);
8584 info
= g_malloc0(sizeof(*info
));
8585 info
->name
= g_strndup(typename
,
8586 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8587 info
->q_typename
= g_strdup(typename
);
8589 QAPI_LIST_PREPEND(*cpu_list
, info
);
8592 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8594 CpuDefinitionInfoList
*cpu_list
= NULL
;
8597 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8598 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8605 * Private utility function for define_one_arm_cp_reg_with_opaque():
8606 * add a single reginfo struct to the hash table.
8608 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8609 void *opaque
, CPState state
,
8610 CPSecureState secstate
,
8611 int crm
, int opc1
, int opc2
,
8614 CPUARMState
*env
= &cpu
->env
;
8617 bool is64
= r
->type
& ARM_CP_64BIT
;
8618 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
8624 case ARM_CP_STATE_AA32
:
8625 /* We assume it is a cp15 register if the .cp field is left unset. */
8626 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
8629 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
8631 case ARM_CP_STATE_AA64
:
8633 * To allow abbreviation of ARMCPRegInfo definitions, we treat
8634 * cp == 0 as equivalent to the value for "standard guest-visible
8635 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
8636 * in their AArch64 view (the .cp value may be non-zero for the
8637 * benefit of the AArch32 view).
8639 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8640 cp
= CP_REG_ARM64_SYSREG_CP
;
8642 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
8645 g_assert_not_reached();
8648 /* Overriding of an existing definition must be explicitly requested. */
8649 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8650 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
8652 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
8657 * Eliminate registers that are not present because the EL is missing.
8658 * Doing this here makes it easier to put all registers for a given
8659 * feature into the same ARMCPRegInfo array and define them all at once.
8662 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8664 * An EL2 register without EL2 but with EL3 is (usually) RES0.
8665 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
8667 int min_el
= ctz32(r
->access
) / 2;
8668 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
8669 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
8672 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
8675 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
8677 if ((r
->access
& max_el
) == 0) {
8682 /* Combine cpreg and name into one allocation. */
8683 name_len
= strlen(name
) + 1;
8684 r2
= g_malloc(sizeof(*r2
) + name_len
);
8686 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
8689 * Update fields to match the instantiation, overwiting wildcards
8690 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
8697 r2
->secure
= secstate
;
8699 r2
->opaque
= opaque
;
8703 /* This should not have been a very special register to begin. */
8704 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
8705 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
8707 * Set the special function to CONST, retaining the other flags.
8708 * This is important for e.g. ARM_CP_SVE so that we still
8709 * take the SVE trap if CPTR_EL3.EZ == 0.
8711 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
8713 * Usually, these registers become RES0, but there are a few
8714 * special cases like VPIDR_EL2 which have a constant non-zero
8715 * value with writes ignored.
8717 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
8721 * ARM_CP_CONST has precedence, so removing the callbacks and
8722 * offsets are not strictly necessary, but it is potentially
8723 * less confusing to debug later.
8727 r2
->raw_readfn
= NULL
;
8728 r2
->raw_writefn
= NULL
;
8730 r2
->fieldoffset
= 0;
8731 r2
->bank_fieldoffsets
[0] = 0;
8732 r2
->bank_fieldoffsets
[1] = 0;
8734 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
8738 * Register is banked (using both entries in array).
8739 * Overwriting fieldoffset as the array is only used to define
8740 * banked registers but later only fieldoffset is used.
8742 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8744 if (state
== ARM_CP_STATE_AA32
) {
8747 * If the register is banked then we don't need to migrate or
8748 * reset the 32-bit instance in certain cases:
8750 * 1) If the register has both 32-bit and 64-bit instances
8751 * then we can count on the 64-bit instance taking care
8752 * of the non-secure bank.
8753 * 2) If ARMv8 is enabled then we can count on a 64-bit
8754 * version taking care of the secure bank. This requires
8755 * that separate 32 and 64-bit definitions are provided.
8757 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8758 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
8759 r2
->type
|= ARM_CP_ALIAS
;
8761 } else if ((secstate
!= r
->secure
) && !ns
) {
8763 * The register is not banked so we only want to allow
8764 * migration of the non-secure instance.
8766 r2
->type
|= ARM_CP_ALIAS
;
8769 if (HOST_BIG_ENDIAN
&&
8770 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
8771 r2
->fieldoffset
+= sizeof(uint32_t);
8777 * By convention, for wildcarded registers only the first
8778 * entry is used for migration; the others are marked as
8779 * ALIAS so we don't try to transfer the register
8780 * multiple times. Special registers (ie NOP/WFI) are
8781 * never migratable and not even raw-accessible.
8783 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
8784 r2
->type
|= ARM_CP_NO_RAW
;
8786 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8787 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8788 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8789 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8793 * Check that raw accesses are either forbidden or handled. Note that
8794 * we can't assert this earlier because the setup of fieldoffset for
8795 * banked registers has to be done first.
8797 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8798 assert(!raw_accessors_invalid(r2
));
8801 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
8805 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8806 const ARMCPRegInfo
*r
, void *opaque
)
8808 /* Define implementations of coprocessor registers.
8809 * We store these in a hashtable because typically
8810 * there are less than 150 registers in a space which
8811 * is 16*16*16*8*8 = 262144 in size.
8812 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8813 * If a register is defined twice then the second definition is
8814 * used, so this can be used to define some generic registers and
8815 * then override them with implementation specific variations.
8816 * At least one of the original and the second definition should
8817 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8818 * against accidental use.
8820 * The state field defines whether the register is to be
8821 * visible in the AArch32 or AArch64 execution state. If the
8822 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8823 * reginfo structure for the AArch32 view, which sees the lower
8824 * 32 bits of the 64 bit register.
8826 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8827 * be wildcarded. AArch64 registers are always considered to be 64
8828 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8829 * the register, if any.
8831 int crm
, opc1
, opc2
;
8832 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8833 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8834 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8835 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8836 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8837 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8840 /* 64 bit registers have only CRm and Opc1 fields */
8841 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8842 /* op0 only exists in the AArch64 encodings */
8843 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8844 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8845 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8847 * This API is only for Arm's system coprocessors (14 and 15) or
8848 * (M-profile or v7A-and-earlier only) for implementation defined
8849 * coprocessors in the range 0..7. Our decode assumes this, since
8850 * 8..13 can be used for other insns including VFP and Neon. See
8851 * valid_cp() in translate.c. Assert here that we haven't tried
8852 * to use an invalid coprocessor number.
8855 case ARM_CP_STATE_BOTH
:
8856 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8861 case ARM_CP_STATE_AA32
:
8862 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
8863 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
8864 assert(r
->cp
>= 14 && r
->cp
<= 15);
8866 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
8869 case ARM_CP_STATE_AA64
:
8870 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
8873 g_assert_not_reached();
8875 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8876 * encodes a minimum access level for the register. We roll this
8877 * runtime check into our general permission check code, so check
8878 * here that the reginfo's specified permissions are strict enough
8879 * to encompass the generic architectural permission check.
8881 if (r
->state
!= ARM_CP_STATE_AA32
) {
8882 CPAccessRights mask
;
8885 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8886 mask
= PL0U_R
| PL1_RW
;
8906 /* min_EL EL1, secure mode only (we don't check the latter) */
8910 /* broken reginfo with out-of-range opc1 */
8911 g_assert_not_reached();
8913 /* assert our permissions are not too lax (stricter is fine) */
8914 assert((r
->access
& ~mask
) == 0);
8917 /* Check that the register definition has enough info to handle
8918 * reads and writes if they are permitted.
8920 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
8921 if (r
->access
& PL3_R
) {
8922 assert((r
->fieldoffset
||
8923 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8926 if (r
->access
& PL3_W
) {
8927 assert((r
->fieldoffset
||
8928 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8933 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8934 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8935 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8936 for (state
= ARM_CP_STATE_AA32
;
8937 state
<= ARM_CP_STATE_AA64
; state
++) {
8938 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8941 if (state
== ARM_CP_STATE_AA32
) {
8942 /* Under AArch32 CP registers can be common
8943 * (same for secure and non-secure world) or banked.
8947 switch (r
->secure
) {
8948 case ARM_CP_SECSTATE_S
:
8949 case ARM_CP_SECSTATE_NS
:
8950 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8951 r
->secure
, crm
, opc1
, opc2
,
8954 case ARM_CP_SECSTATE_BOTH
:
8955 name
= g_strdup_printf("%s_S", r
->name
);
8956 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8958 crm
, opc1
, opc2
, name
);
8960 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8962 crm
, opc1
, opc2
, r
->name
);
8965 g_assert_not_reached();
8968 /* AArch64 registers get mapped to non-secure instance
8970 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8972 crm
, opc1
, opc2
, r
->name
);
8980 /* Define a whole list of registers */
8981 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
8982 void *opaque
, size_t len
)
8985 for (i
= 0; i
< len
; ++i
) {
8986 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
8991 * Modify ARMCPRegInfo for access from userspace.
8993 * This is a data driven modification directed by
8994 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8995 * user-space cannot alter any values and dynamic values pertaining to
8996 * execution state are hidden from user space view anyway.
8998 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
8999 const ARMCPRegUserSpaceInfo
*mods
,
9002 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
9003 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
9004 GPatternSpec
*pat
= NULL
;
9007 pat
= g_pattern_spec_new(m
->name
);
9009 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
9010 ARMCPRegInfo
*r
= regs
+ ri
;
9012 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9013 r
->type
= ARM_CP_CONST
;
9017 } else if (strcmp(r
->name
, m
->name
) == 0) {
9018 r
->type
= ARM_CP_CONST
;
9020 r
->resetvalue
&= m
->exported_bits
;
9021 r
->resetvalue
|= m
->fixed_bits
;
9026 g_pattern_spec_free(pat
);
9031 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9033 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9036 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9039 /* Helper coprocessor write function for write-ignore registers */
9042 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9044 /* Helper coprocessor write function for read-as-zero registers */
9048 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9050 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9053 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9055 /* Return true if it is not valid for us to switch to
9056 * this CPU mode (ie all the UNPREDICTABLE cases in
9057 * the ARM ARM CPSRWriteByInstr pseudocode).
9060 /* Changes to or from Hyp via MSR and CPS are illegal. */
9061 if (write_type
== CPSRWriteByInstr
&&
9062 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9063 mode
== ARM_CPU_MODE_HYP
)) {
9068 case ARM_CPU_MODE_USR
:
9070 case ARM_CPU_MODE_SYS
:
9071 case ARM_CPU_MODE_SVC
:
9072 case ARM_CPU_MODE_ABT
:
9073 case ARM_CPU_MODE_UND
:
9074 case ARM_CPU_MODE_IRQ
:
9075 case ARM_CPU_MODE_FIQ
:
9076 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
9077 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9079 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9080 * and CPS are treated as illegal mode changes.
9082 if (write_type
== CPSRWriteByInstr
&&
9083 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9084 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9088 case ARM_CPU_MODE_HYP
:
9089 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9090 case ARM_CPU_MODE_MON
:
9091 return arm_current_el(env
) < 3;
9097 uint32_t cpsr_read(CPUARMState
*env
)
9100 ZF
= (env
->ZF
== 0);
9101 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9102 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9103 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9104 | ((env
->condexec_bits
& 0xfc) << 8)
9105 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9108 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9109 CPSRWriteType write_type
)
9111 uint32_t changed_daif
;
9112 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9113 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9115 if (mask
& CPSR_NZCV
) {
9116 env
->ZF
= (~val
) & CPSR_Z
;
9118 env
->CF
= (val
>> 29) & 1;
9119 env
->VF
= (val
<< 3) & 0x80000000;
9122 env
->QF
= ((val
& CPSR_Q
) != 0);
9124 env
->thumb
= ((val
& CPSR_T
) != 0);
9125 if (mask
& CPSR_IT_0_1
) {
9126 env
->condexec_bits
&= ~3;
9127 env
->condexec_bits
|= (val
>> 25) & 3;
9129 if (mask
& CPSR_IT_2_7
) {
9130 env
->condexec_bits
&= 3;
9131 env
->condexec_bits
|= (val
>> 8) & 0xfc;
9133 if (mask
& CPSR_GE
) {
9134 env
->GE
= (val
>> 16) & 0xf;
9137 /* In a V7 implementation that includes the security extensions but does
9138 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
9139 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
9140 * bits respectively.
9142 * In a V8 implementation, it is permitted for privileged software to
9143 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
9145 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
9146 arm_feature(env
, ARM_FEATURE_EL3
) &&
9147 !arm_feature(env
, ARM_FEATURE_EL2
) &&
9148 !arm_is_secure(env
)) {
9150 changed_daif
= (env
->daif
^ val
) & mask
;
9152 if (changed_daif
& CPSR_A
) {
9153 /* Check to see if we are allowed to change the masking of async
9154 * abort exceptions from a non-secure state.
9156 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
9157 qemu_log_mask(LOG_GUEST_ERROR
,
9158 "Ignoring attempt to switch CPSR_A flag from "
9159 "non-secure world with SCR.AW bit clear\n");
9164 if (changed_daif
& CPSR_F
) {
9165 /* Check to see if we are allowed to change the masking of FIQ
9166 * exceptions from a non-secure state.
9168 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
9169 qemu_log_mask(LOG_GUEST_ERROR
,
9170 "Ignoring attempt to switch CPSR_F flag from "
9171 "non-secure world with SCR.FW bit clear\n");
9175 /* Check whether non-maskable FIQ (NMFI) support is enabled.
9176 * If this bit is set software is not allowed to mask
9177 * FIQs, but is allowed to set CPSR_F to 0.
9179 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
9181 qemu_log_mask(LOG_GUEST_ERROR
,
9182 "Ignoring attempt to enable CPSR_F flag "
9183 "(non-maskable FIQ [NMFI] support enabled)\n");
9189 env
->daif
&= ~(CPSR_AIF
& mask
);
9190 env
->daif
|= val
& CPSR_AIF
& mask
;
9192 if (write_type
!= CPSRWriteRaw
&&
9193 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
9194 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
9195 /* Note that we can only get here in USR mode if this is a
9196 * gdb stub write; for this case we follow the architectural
9197 * behaviour for guest writes in USR mode of ignoring an attempt
9198 * to switch mode. (Those are caught by translate.c for writes
9199 * triggered by guest instructions.)
9202 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
9203 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
9204 * v7, and has defined behaviour in v8:
9205 * + leave CPSR.M untouched
9206 * + allow changes to the other CPSR fields
9208 * For user changes via the GDB stub, we don't set PSTATE.IL,
9209 * as this would be unnecessarily harsh for a user error.
9212 if (write_type
!= CPSRWriteByGDBStub
&&
9213 arm_feature(env
, ARM_FEATURE_V8
)) {
9217 qemu_log_mask(LOG_GUEST_ERROR
,
9218 "Illegal AArch32 mode switch attempt from %s to %s\n",
9219 aarch32_mode_name(env
->uncached_cpsr
),
9220 aarch32_mode_name(val
));
9222 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
9223 write_type
== CPSRWriteExceptionReturn
?
9224 "Exception return from AArch32" :
9225 "AArch32 mode switch from",
9226 aarch32_mode_name(env
->uncached_cpsr
),
9227 aarch32_mode_name(val
), env
->regs
[15]);
9228 switch_mode(env
, val
& CPSR_M
);
9231 mask
&= ~CACHED_CPSR_BITS
;
9232 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
9233 if (rebuild_hflags
) {
9234 arm_rebuild_hflags(env
);
9238 /* Sign/zero extend */
9239 uint32_t HELPER(sxtb16
)(uint32_t x
)
9242 res
= (uint16_t)(int8_t)x
;
9243 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
9247 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
9250 * Take a division-by-zero exception if necessary; otherwise return
9251 * to get the usual non-trapping division behaviour (result of 0)
9253 if (arm_feature(env
, ARM_FEATURE_M
)
9254 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
9255 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
9259 uint32_t HELPER(uxtb16
)(uint32_t x
)
9262 res
= (uint16_t)(uint8_t)x
;
9263 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
9267 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
9270 handle_possible_div0_trap(env
, GETPC());
9273 if (num
== INT_MIN
&& den
== -1) {
9279 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
9282 handle_possible_div0_trap(env
, GETPC());
9288 uint32_t HELPER(rbit
)(uint32_t x
)
9293 #ifdef CONFIG_USER_ONLY
9295 static void switch_mode(CPUARMState
*env
, int mode
)
9297 ARMCPU
*cpu
= env_archcpu(env
);
9299 if (mode
!= ARM_CPU_MODE_USR
) {
9300 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
9304 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9305 uint32_t cur_el
, bool secure
)
9310 void aarch64_sync_64_to_32(CPUARMState
*env
)
9312 g_assert_not_reached();
9317 static void switch_mode(CPUARMState
*env
, int mode
)
9322 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9323 if (mode
== old_mode
)
9326 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9327 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9328 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9329 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9330 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9331 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9334 i
= bank_number(old_mode
);
9335 env
->banked_r13
[i
] = env
->regs
[13];
9336 env
->banked_spsr
[i
] = env
->spsr
;
9338 i
= bank_number(mode
);
9339 env
->regs
[13] = env
->banked_r13
[i
];
9340 env
->spsr
= env
->banked_spsr
[i
];
9342 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9343 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9346 /* Physical Interrupt Target EL Lookup Table
9348 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9350 * The below multi-dimensional table is used for looking up the target
9351 * exception level given numerous condition criteria. Specifically, the
9352 * target EL is based on SCR and HCR routing controls as well as the
9353 * currently executing EL and secure state.
9356 * target_el_table[2][2][2][2][2][4]
9357 * | | | | | +--- Current EL
9358 * | | | | +------ Non-secure(0)/Secure(1)
9359 * | | | +--------- HCR mask override
9360 * | | +------------ SCR exec state control
9361 * | +--------------- SCR mask override
9362 * +------------------ 32-bit(0)/64-bit(1) EL3
9364 * The table values are as such:
9368 * The ARM ARM target EL table includes entries indicating that an "exception
9369 * is not taken". The two cases where this is applicable are:
9370 * 1) An exception is taken from EL3 but the SCR does not have the exception
9372 * 2) An exception is taken from EL2 but the HCR does not have the exception
9374 * In these two cases, the below table contain a target of EL1. This value is
9375 * returned as it is expected that the consumer of the table data will check
9376 * for "target EL >= current EL" to ensure the exception is not taken.
9380 * BIT IRQ IMO Non-secure Secure
9381 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9383 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9384 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9385 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9386 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9387 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9388 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9389 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9390 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9391 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9392 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9393 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9394 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9395 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9396 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9397 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9398 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9399 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9403 * Determine the target EL for physical exceptions
9405 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9406 uint32_t cur_el
, bool secure
)
9408 CPUARMState
*env
= cs
->env_ptr
;
9413 /* Is the highest EL AArch64? */
9414 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9417 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9418 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9420 /* Either EL2 is the highest EL (and so the EL2 register width
9421 * is given by is64); or there is no EL2 or EL3, in which case
9422 * the value of 'rw' does not affect the table lookup anyway.
9427 hcr_el2
= arm_hcr_el2_eff(env
);
9430 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9431 hcr
= hcr_el2
& HCR_IMO
;
9434 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9435 hcr
= hcr_el2
& HCR_FMO
;
9438 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9439 hcr
= hcr_el2
& HCR_AMO
;
9444 * For these purposes, TGE and AMO/IMO/FMO both force the
9445 * interrupt to EL2. Fold TGE into the bit extracted above.
9447 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9449 /* Perform a table-lookup for the target EL given the current state */
9450 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9452 assert(target_el
> 0);
9457 void arm_log_exception(CPUState
*cs
)
9459 int idx
= cs
->exception_index
;
9461 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9462 const char *exc
= NULL
;
9463 static const char * const excnames
[] = {
9464 [EXCP_UDEF
] = "Undefined Instruction",
9466 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9467 [EXCP_DATA_ABORT
] = "Data Abort",
9470 [EXCP_BKPT
] = "Breakpoint",
9471 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9472 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9473 [EXCP_HVC
] = "Hypervisor Call",
9474 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9475 [EXCP_SMC
] = "Secure Monitor Call",
9476 [EXCP_VIRQ
] = "Virtual IRQ",
9477 [EXCP_VFIQ
] = "Virtual FIQ",
9478 [EXCP_SEMIHOST
] = "Semihosting call",
9479 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9480 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9481 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9482 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9483 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9484 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9485 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
9486 [EXCP_VSERR
] = "Virtual SERR",
9489 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9490 exc
= excnames
[idx
];
9495 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
9496 idx
, exc
, cs
->cpu_index
);
9501 * Function used to synchronize QEMU's AArch64 register set with AArch32
9502 * register set. This is necessary when switching between AArch32 and AArch64
9505 void aarch64_sync_32_to_64(CPUARMState
*env
)
9508 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9510 /* We can blanket copy R[0:7] to X[0:7] */
9511 for (i
= 0; i
< 8; i
++) {
9512 env
->xregs
[i
] = env
->regs
[i
];
9516 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9517 * Otherwise, they come from the banked user regs.
9519 if (mode
== ARM_CPU_MODE_FIQ
) {
9520 for (i
= 8; i
< 13; i
++) {
9521 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9524 for (i
= 8; i
< 13; i
++) {
9525 env
->xregs
[i
] = env
->regs
[i
];
9530 * Registers x13-x23 are the various mode SP and FP registers. Registers
9531 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9532 * from the mode banked register.
9534 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9535 env
->xregs
[13] = env
->regs
[13];
9536 env
->xregs
[14] = env
->regs
[14];
9538 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9539 /* HYP is an exception in that it is copied from r14 */
9540 if (mode
== ARM_CPU_MODE_HYP
) {
9541 env
->xregs
[14] = env
->regs
[14];
9543 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9547 if (mode
== ARM_CPU_MODE_HYP
) {
9548 env
->xregs
[15] = env
->regs
[13];
9550 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9553 if (mode
== ARM_CPU_MODE_IRQ
) {
9554 env
->xregs
[16] = env
->regs
[14];
9555 env
->xregs
[17] = env
->regs
[13];
9557 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9558 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9561 if (mode
== ARM_CPU_MODE_SVC
) {
9562 env
->xregs
[18] = env
->regs
[14];
9563 env
->xregs
[19] = env
->regs
[13];
9565 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9566 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9569 if (mode
== ARM_CPU_MODE_ABT
) {
9570 env
->xregs
[20] = env
->regs
[14];
9571 env
->xregs
[21] = env
->regs
[13];
9573 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9574 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9577 if (mode
== ARM_CPU_MODE_UND
) {
9578 env
->xregs
[22] = env
->regs
[14];
9579 env
->xregs
[23] = env
->regs
[13];
9581 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9582 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9586 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9587 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9588 * FIQ bank for r8-r14.
9590 if (mode
== ARM_CPU_MODE_FIQ
) {
9591 for (i
= 24; i
< 31; i
++) {
9592 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9595 for (i
= 24; i
< 29; i
++) {
9596 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9598 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9599 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9602 env
->pc
= env
->regs
[15];
9606 * Function used to synchronize QEMU's AArch32 register set with AArch64
9607 * register set. This is necessary when switching between AArch32 and AArch64
9610 void aarch64_sync_64_to_32(CPUARMState
*env
)
9613 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9615 /* We can blanket copy X[0:7] to R[0:7] */
9616 for (i
= 0; i
< 8; i
++) {
9617 env
->regs
[i
] = env
->xregs
[i
];
9621 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9622 * Otherwise, we copy x8-x12 into the banked user regs.
9624 if (mode
== ARM_CPU_MODE_FIQ
) {
9625 for (i
= 8; i
< 13; i
++) {
9626 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9629 for (i
= 8; i
< 13; i
++) {
9630 env
->regs
[i
] = env
->xregs
[i
];
9635 * Registers r13 & r14 depend on the current mode.
9636 * If we are in a given mode, we copy the corresponding x registers to r13
9637 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9640 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9641 env
->regs
[13] = env
->xregs
[13];
9642 env
->regs
[14] = env
->xregs
[14];
9644 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9647 * HYP is an exception in that it does not have its own banked r14 but
9648 * shares the USR r14
9650 if (mode
== ARM_CPU_MODE_HYP
) {
9651 env
->regs
[14] = env
->xregs
[14];
9653 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9657 if (mode
== ARM_CPU_MODE_HYP
) {
9658 env
->regs
[13] = env
->xregs
[15];
9660 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9663 if (mode
== ARM_CPU_MODE_IRQ
) {
9664 env
->regs
[14] = env
->xregs
[16];
9665 env
->regs
[13] = env
->xregs
[17];
9667 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9668 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9671 if (mode
== ARM_CPU_MODE_SVC
) {
9672 env
->regs
[14] = env
->xregs
[18];
9673 env
->regs
[13] = env
->xregs
[19];
9675 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9676 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9679 if (mode
== ARM_CPU_MODE_ABT
) {
9680 env
->regs
[14] = env
->xregs
[20];
9681 env
->regs
[13] = env
->xregs
[21];
9683 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9684 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9687 if (mode
== ARM_CPU_MODE_UND
) {
9688 env
->regs
[14] = env
->xregs
[22];
9689 env
->regs
[13] = env
->xregs
[23];
9691 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9692 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9695 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9696 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9697 * FIQ bank for r8-r14.
9699 if (mode
== ARM_CPU_MODE_FIQ
) {
9700 for (i
= 24; i
< 31; i
++) {
9701 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9704 for (i
= 24; i
< 29; i
++) {
9705 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9707 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9708 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9711 env
->regs
[15] = env
->pc
;
9714 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9715 uint32_t mask
, uint32_t offset
,
9720 /* Change the CPU state so as to actually take the exception. */
9721 switch_mode(env
, new_mode
);
9724 * For exceptions taken to AArch32 we must clear the SS bit in both
9725 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9727 env
->pstate
&= ~PSTATE_SS
;
9728 env
->spsr
= cpsr_read(env
);
9729 /* Clear IT bits. */
9730 env
->condexec_bits
= 0;
9731 /* Switch to the new mode, and to the correct instruction set. */
9732 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9734 /* This must be after mode switching. */
9735 new_el
= arm_current_el(env
);
9737 /* Set new mode endianness */
9738 env
->uncached_cpsr
&= ~CPSR_E
;
9739 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9740 env
->uncached_cpsr
|= CPSR_E
;
9742 /* J and IL must always be cleared for exception entry */
9743 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9746 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
9747 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
9748 env
->uncached_cpsr
|= CPSR_SSBS
;
9750 env
->uncached_cpsr
&= ~CPSR_SSBS
;
9754 if (new_mode
== ARM_CPU_MODE_HYP
) {
9755 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9756 env
->elr_el
[2] = env
->regs
[15];
9758 /* CPSR.PAN is normally preserved preserved unless... */
9759 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9762 if (!arm_is_secure_below_el3(env
)) {
9763 /* ... the target is EL3, from non-secure state. */
9764 env
->uncached_cpsr
&= ~CPSR_PAN
;
9767 /* ... the target is EL3, from secure state ... */
9770 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9771 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9772 env
->uncached_cpsr
|= CPSR_PAN
;
9778 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9779 * and we should just guard the thumb mode on V4
9781 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9783 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9785 env
->regs
[14] = env
->regs
[15] + offset
;
9787 env
->regs
[15] = newpc
;
9788 arm_rebuild_hflags(env
);
9791 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9794 * Handle exception entry to Hyp mode; this is sufficiently
9795 * different to entry to other AArch32 modes that we handle it
9798 * The vector table entry used is always the 0x14 Hyp mode entry point,
9799 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
9800 * The offset applied to the preferred return address is always zero
9801 * (see DDI0487C.a section G1.12.3).
9802 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9804 uint32_t addr
, mask
;
9805 ARMCPU
*cpu
= ARM_CPU(cs
);
9806 CPUARMState
*env
= &cpu
->env
;
9808 switch (cs
->exception_index
) {
9816 /* Fall through to prefetch abort. */
9817 case EXCP_PREFETCH_ABORT
:
9818 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9819 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9820 (uint32_t)env
->exception
.vaddress
);
9823 case EXCP_DATA_ABORT
:
9824 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9825 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9826 (uint32_t)env
->exception
.vaddress
);
9842 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9845 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9846 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9848 * QEMU syndrome values are v8-style. v7 has the IL bit
9849 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9850 * If this is a v7 CPU, squash the IL bit in those cases.
9852 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9853 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9854 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9855 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9856 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9859 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9862 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9867 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9870 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9873 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9877 addr
+= env
->cp15
.hvbar
;
9879 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9882 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9884 ARMCPU
*cpu
= ARM_CPU(cs
);
9885 CPUARMState
*env
= &cpu
->env
;
9892 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9893 switch (syn_get_ec(env
->exception
.syndrome
)) {
9895 case EC_BREAKPOINT_SAME_EL
:
9899 case EC_WATCHPOINT_SAME_EL
:
9905 case EC_VECTORCATCH
:
9914 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9917 if (env
->exception
.target_el
== 2) {
9918 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9922 switch (cs
->exception_index
) {
9924 new_mode
= ARM_CPU_MODE_UND
;
9933 new_mode
= ARM_CPU_MODE_SVC
;
9936 /* The PC already points to the next instruction. */
9940 /* Fall through to prefetch abort. */
9941 case EXCP_PREFETCH_ABORT
:
9942 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9943 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9944 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9945 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9946 new_mode
= ARM_CPU_MODE_ABT
;
9948 mask
= CPSR_A
| CPSR_I
;
9951 case EXCP_DATA_ABORT
:
9952 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9953 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9954 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9956 (uint32_t)env
->exception
.vaddress
);
9957 new_mode
= ARM_CPU_MODE_ABT
;
9959 mask
= CPSR_A
| CPSR_I
;
9963 new_mode
= ARM_CPU_MODE_IRQ
;
9965 /* Disable IRQ and imprecise data aborts. */
9966 mask
= CPSR_A
| CPSR_I
;
9968 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9969 /* IRQ routed to monitor mode */
9970 new_mode
= ARM_CPU_MODE_MON
;
9975 new_mode
= ARM_CPU_MODE_FIQ
;
9977 /* Disable FIQ, IRQ and imprecise data aborts. */
9978 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9979 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9980 /* FIQ routed to monitor mode */
9981 new_mode
= ARM_CPU_MODE_MON
;
9986 new_mode
= ARM_CPU_MODE_IRQ
;
9988 /* Disable IRQ and imprecise data aborts. */
9989 mask
= CPSR_A
| CPSR_I
;
9993 new_mode
= ARM_CPU_MODE_FIQ
;
9995 /* Disable FIQ, IRQ and imprecise data aborts. */
9996 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10002 * Note that this is reported as a data abort, but the DFAR
10003 * has an UNKNOWN value. Construct the SError syndrome from
10004 * AET and ExT fields.
10006 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10008 if (extended_addresses_enabled(env
)) {
10009 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
10011 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
10013 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
10014 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10015 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
10016 env
->exception
.fsr
);
10018 new_mode
= ARM_CPU_MODE_ABT
;
10020 mask
= CPSR_A
| CPSR_I
;
10025 new_mode
= ARM_CPU_MODE_MON
;
10027 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10031 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10032 return; /* Never happens. Keep compiler happy. */
10035 if (new_mode
== ARM_CPU_MODE_MON
) {
10036 addr
+= env
->cp15
.mvbar
;
10037 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10038 /* High vectors. When enabled, base address cannot be remapped. */
10039 addr
+= 0xffff0000;
10041 /* ARM v7 architectures provide a vector base address register to remap
10042 * the interrupt vector table.
10043 * This register is only followed in non-monitor mode, and is banked.
10044 * Note: only bits 31:5 are valid.
10046 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10049 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10050 env
->cp15
.scr_el3
&= ~SCR_NS
;
10053 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10056 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10059 * Return the register number of the AArch64 view of the AArch32
10060 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10061 * be that of the AArch32 mode the exception came from.
10063 int mode
= env
->uncached_cpsr
& CPSR_M
;
10065 switch (aarch32_reg
) {
10067 return aarch32_reg
;
10069 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10072 case ARM_CPU_MODE_USR
:
10073 case ARM_CPU_MODE_SYS
:
10075 case ARM_CPU_MODE_HYP
:
10077 case ARM_CPU_MODE_IRQ
:
10079 case ARM_CPU_MODE_SVC
:
10081 case ARM_CPU_MODE_ABT
:
10083 case ARM_CPU_MODE_UND
:
10085 case ARM_CPU_MODE_FIQ
:
10088 g_assert_not_reached();
10092 case ARM_CPU_MODE_USR
:
10093 case ARM_CPU_MODE_SYS
:
10094 case ARM_CPU_MODE_HYP
:
10096 case ARM_CPU_MODE_IRQ
:
10098 case ARM_CPU_MODE_SVC
:
10100 case ARM_CPU_MODE_ABT
:
10102 case ARM_CPU_MODE_UND
:
10104 case ARM_CPU_MODE_FIQ
:
10107 g_assert_not_reached();
10112 g_assert_not_reached();
10116 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
10118 uint32_t ret
= cpsr_read(env
);
10120 /* Move DIT to the correct location for SPSR_ELx */
10121 if (ret
& CPSR_DIT
) {
10125 /* Merge PSTATE.SS into SPSR_ELx */
10126 ret
|= env
->pstate
& PSTATE_SS
;
10131 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
10133 /* Return true if this syndrome value is a synchronous external abort */
10134 switch (syn_get_ec(syndrome
)) {
10136 case EC_INSNABORT_SAME_EL
:
10138 case EC_DATAABORT_SAME_EL
:
10139 /* Look at fault status code for all the synchronous ext abort cases */
10140 switch (syndrome
& 0x3f) {
10156 /* Handle exception entry to a target EL which is using AArch64 */
10157 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
10159 ARMCPU
*cpu
= ARM_CPU(cs
);
10160 CPUARMState
*env
= &cpu
->env
;
10161 unsigned int new_el
= env
->exception
.target_el
;
10162 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
10163 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
10164 unsigned int old_mode
;
10165 unsigned int cur_el
= arm_current_el(env
);
10169 * Note that new_el can never be 0. If cur_el is 0, then
10170 * el0_a64 is is_a64(), else el0_a64 is ignored.
10172 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
10174 if (cur_el
< new_el
) {
10175 /* Entry vector offset depends on whether the implemented EL
10176 * immediately lower than the target level is using AArch32 or AArch64
10183 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
10186 hcr
= arm_hcr_el2_eff(env
);
10187 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10188 is_aa64
= (hcr
& HCR_RW
) != 0;
10193 is_aa64
= is_a64(env
);
10196 g_assert_not_reached();
10204 } else if (pstate_read(env
) & PSTATE_SP
) {
10208 switch (cs
->exception_index
) {
10209 case EXCP_PREFETCH_ABORT
:
10210 case EXCP_DATA_ABORT
:
10212 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
10213 * to be taken to the SError vector entrypoint.
10215 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
10216 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
10219 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
10220 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
10221 env
->cp15
.far_el
[new_el
]);
10227 case EXCP_HYP_TRAP
:
10229 switch (syn_get_ec(env
->exception
.syndrome
)) {
10230 case EC_ADVSIMDFPACCESSTRAP
:
10232 * QEMU internal FP/SIMD syndromes from AArch32 include the
10233 * TA and coproc fields which are only exposed if the exception
10234 * is taken to AArch32 Hyp mode. Mask them out to get a valid
10235 * AArch64 format syndrome.
10237 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
10239 case EC_CP14RTTRAP
:
10240 case EC_CP15RTTRAP
:
10241 case EC_CP14DTTRAP
:
10243 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
10244 * the raw register field from the insn; when taking this to
10245 * AArch64 we must convert it to the AArch64 view of the register
10246 * number. Notice that we read a 4-bit AArch32 register number and
10247 * write back a 5-bit AArch64 one.
10249 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10250 rt
= aarch64_regnum(env
, rt
);
10251 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10254 case EC_CP15RRTTRAP
:
10255 case EC_CP14RRTTRAP
:
10256 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
10257 rt
= extract32(env
->exception
.syndrome
, 5, 4);
10258 rt
= aarch64_regnum(env
, rt
);
10259 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10261 rt
= extract32(env
->exception
.syndrome
, 10, 4);
10262 rt
= aarch64_regnum(env
, rt
);
10263 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
10267 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10279 /* Construct the SError syndrome from IDS and ISS fields. */
10280 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
10281 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
10284 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10288 old_mode
= pstate_read(env
);
10289 aarch64_save_sp(env
, arm_current_el(env
));
10290 env
->elr_el
[new_el
] = env
->pc
;
10292 old_mode
= cpsr_read_for_spsr_elx(env
);
10293 env
->elr_el
[new_el
] = env
->regs
[15];
10295 aarch64_sync_32_to_64(env
);
10297 env
->condexec_bits
= 0;
10299 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
10301 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
10302 env
->elr_el
[new_el
]);
10304 if (cpu_isar_feature(aa64_pan
, cpu
)) {
10305 /* The value of PSTATE.PAN is normally preserved, except when ... */
10306 new_mode
|= old_mode
& PSTATE_PAN
;
10309 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
10310 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
10311 != (HCR_E2H
| HCR_TGE
)) {
10316 /* ... the target is EL1 ... */
10317 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
10318 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
10319 new_mode
|= PSTATE_PAN
;
10324 if (cpu_isar_feature(aa64_mte
, cpu
)) {
10325 new_mode
|= PSTATE_TCO
;
10328 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
10329 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
10330 new_mode
|= PSTATE_SSBS
;
10332 new_mode
&= ~PSTATE_SSBS
;
10336 pstate_write(env
, PSTATE_DAIF
| new_mode
);
10337 env
->aarch64
= true;
10338 aarch64_restore_sp(env
, new_el
);
10339 helper_rebuild_hflags_a64(env
, new_el
);
10343 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
10344 new_el
, env
->pc
, pstate_read(env
));
10348 * Do semihosting call and set the appropriate return value. All the
10349 * permission and validity checks have been done at translate time.
10351 * We only see semihosting exceptions in TCG only as they are not
10352 * trapped to the hypervisor in KVM.
10355 static void handle_semihosting(CPUState
*cs
)
10357 ARMCPU
*cpu
= ARM_CPU(cs
);
10358 CPUARMState
*env
= &cpu
->env
;
10361 qemu_log_mask(CPU_LOG_INT
,
10362 "...handling as semihosting call 0x%" PRIx64
"\n",
10364 env
->xregs
[0] = do_common_semihosting(cs
);
10367 qemu_log_mask(CPU_LOG_INT
,
10368 "...handling as semihosting call 0x%x\n",
10370 env
->regs
[0] = do_common_semihosting(cs
);
10371 env
->regs
[15] += env
->thumb
? 2 : 4;
10376 /* Handle a CPU exception for A and R profile CPUs.
10377 * Do any appropriate logging, handle PSCI calls, and then hand off
10378 * to the AArch64-entry or AArch32-entry function depending on the
10379 * target exception level's register width.
10381 * Note: this is used for both TCG (as the do_interrupt tcg op),
10382 * and KVM to re-inject guest debug exceptions, and to
10383 * inject a Synchronous-External-Abort.
10385 void arm_cpu_do_interrupt(CPUState
*cs
)
10387 ARMCPU
*cpu
= ARM_CPU(cs
);
10388 CPUARMState
*env
= &cpu
->env
;
10389 unsigned int new_el
= env
->exception
.target_el
;
10391 assert(!arm_feature(env
, ARM_FEATURE_M
));
10393 arm_log_exception(cs
);
10394 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
10396 if (qemu_loglevel_mask(CPU_LOG_INT
)
10397 && !excp_is_internal(cs
->exception_index
)) {
10398 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
10399 syn_get_ec(env
->exception
.syndrome
),
10400 env
->exception
.syndrome
);
10403 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
10404 arm_handle_psci_call(cpu
);
10405 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
10410 * Semihosting semantics depend on the register width of the code
10411 * that caused the exception, not the target exception level, so
10412 * must be handled here.
10415 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10416 handle_semihosting(cs
);
10421 /* Hooks may change global state so BQL should be held, also the
10422 * BQL needs to be held for any modification of
10423 * cs->interrupt_request.
10425 g_assert(qemu_mutex_iothread_locked());
10427 arm_call_pre_el_change_hook(cpu
);
10429 assert(!excp_is_internal(cs
->exception_index
));
10430 if (arm_el_is_aa64(env
, new_el
)) {
10431 arm_cpu_do_interrupt_aarch64(cs
);
10433 arm_cpu_do_interrupt_aarch32(cs
);
10436 arm_call_el_change_hook(cpu
);
10438 if (!kvm_enabled()) {
10439 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10442 #endif /* !CONFIG_USER_ONLY */
10444 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10446 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10448 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10449 el
= (mmu_idx
== ARMMMUIdx_E20_0
|| mmu_idx
== ARMMMUIdx_SE20_0
)
10452 return env
->cp15
.sctlr_el
[el
];
10455 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10457 if (regime_has_2_ranges(mmu_idx
)) {
10458 return extract64(tcr
, 37, 2);
10459 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10460 return 0; /* VTCR_EL2 */
10462 /* Replicate the single TBI bit so we always have 2 bits. */
10463 return extract32(tcr
, 20, 1) * 3;
10467 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10469 if (regime_has_2_ranges(mmu_idx
)) {
10470 return extract64(tcr
, 51, 2);
10471 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10472 return 0; /* VTCR_EL2 */
10474 /* Replicate the single TBID bit so we always have 2 bits. */
10475 return extract32(tcr
, 29, 1) * 3;
10479 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10481 if (regime_has_2_ranges(mmu_idx
)) {
10482 return extract64(tcr
, 57, 2);
10484 /* Replicate the single TCMA bit so we always have 2 bits. */
10485 return extract32(tcr
, 30, 1) * 3;
10489 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10490 ARMMMUIdx mmu_idx
, bool data
)
10492 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10493 bool epd
, hpd
, using16k
, using64k
, tsz_oob
, ds
;
10494 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
10495 ARMCPU
*cpu
= env_archcpu(env
);
10497 if (!regime_has_2_ranges(mmu_idx
)) {
10499 tsz
= extract32(tcr
, 0, 6);
10500 using64k
= extract32(tcr
, 14, 1);
10501 using16k
= extract32(tcr
, 15, 1);
10502 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10506 hpd
= extract32(tcr
, 24, 1);
10509 sh
= extract32(tcr
, 12, 2);
10510 ps
= extract32(tcr
, 16, 3);
10511 ds
= extract64(tcr
, 32, 1);
10514 * Bit 55 is always between the two regions, and is canonical for
10515 * determining if address tagging is enabled.
10517 select
= extract64(va
, 55, 1);
10519 tsz
= extract32(tcr
, 0, 6);
10520 epd
= extract32(tcr
, 7, 1);
10521 sh
= extract32(tcr
, 12, 2);
10522 using64k
= extract32(tcr
, 14, 1);
10523 using16k
= extract32(tcr
, 15, 1);
10524 hpd
= extract64(tcr
, 41, 1);
10526 int tg
= extract32(tcr
, 30, 2);
10527 using16k
= tg
== 1;
10528 using64k
= tg
== 3;
10529 tsz
= extract32(tcr
, 16, 6);
10530 epd
= extract32(tcr
, 23, 1);
10531 sh
= extract32(tcr
, 28, 2);
10532 hpd
= extract64(tcr
, 42, 1);
10534 ps
= extract64(tcr
, 32, 3);
10535 ds
= extract64(tcr
, 59, 1);
10538 if (cpu_isar_feature(aa64_st
, cpu
)) {
10539 max_tsz
= 48 - using64k
;
10545 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
10546 * adjust the effective value of DS, as documented.
10550 if (cpu_isar_feature(aa64_lva
, cpu
)) {
10556 case ARMMMUIdx_Stage2
:
10557 case ARMMMUIdx_Stage2_S
:
10559 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
10561 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
10566 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
10568 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
10577 if (tsz
> max_tsz
) {
10580 } else if (tsz
< min_tsz
) {
10587 /* Present TBI as a composite with TBID. */
10588 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
10590 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
10592 tbi
= (tbi
>> select
) & 1;
10594 return (ARMVAParameters
) {
10602 .using16k
= using16k
,
10603 .using64k
= using64k
,
10604 .tsz_oob
= tsz_oob
,
10609 /* Note that signed overflow is undefined in C. The following routines are
10610 careful to use unsigned types where modulo arithmetic is required.
10611 Failure to do so _will_ break on newer gcc. */
10613 /* Signed saturating arithmetic. */
10615 /* Perform 16-bit signed saturating addition. */
10616 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10621 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10630 /* Perform 8-bit signed saturating addition. */
10631 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10636 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10645 /* Perform 16-bit signed saturating subtraction. */
10646 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10651 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10660 /* Perform 8-bit signed saturating subtraction. */
10661 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10666 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10675 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10676 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10677 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10678 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10681 #include "op_addsub.h"
10683 /* Unsigned saturating arithmetic. */
10684 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10693 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10701 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10710 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10718 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10719 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10720 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10721 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10724 #include "op_addsub.h"
10726 /* Signed modulo arithmetic. */
10727 #define SARITH16(a, b, n, op) do { \
10729 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10730 RESULT(sum, n, 16); \
10732 ge |= 3 << (n * 2); \
10735 #define SARITH8(a, b, n, op) do { \
10737 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10738 RESULT(sum, n, 8); \
10744 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10745 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10746 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10747 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10751 #include "op_addsub.h"
10753 /* Unsigned modulo arithmetic. */
10754 #define ADD16(a, b, n) do { \
10756 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10757 RESULT(sum, n, 16); \
10758 if ((sum >> 16) == 1) \
10759 ge |= 3 << (n * 2); \
10762 #define ADD8(a, b, n) do { \
10764 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10765 RESULT(sum, n, 8); \
10766 if ((sum >> 8) == 1) \
10770 #define SUB16(a, b, n) do { \
10772 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10773 RESULT(sum, n, 16); \
10774 if ((sum >> 16) == 0) \
10775 ge |= 3 << (n * 2); \
10778 #define SUB8(a, b, n) do { \
10780 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
10781 RESULT(sum, n, 8); \
10782 if ((sum >> 8) == 0) \
10789 #include "op_addsub.h"
10791 /* Halved signed arithmetic. */
10792 #define ADD16(a, b, n) \
10793 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
10794 #define SUB16(a, b, n) \
10795 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
10796 #define ADD8(a, b, n) \
10797 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
10798 #define SUB8(a, b, n) \
10799 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
10802 #include "op_addsub.h"
10804 /* Halved unsigned arithmetic. */
10805 #define ADD16(a, b, n) \
10806 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10807 #define SUB16(a, b, n) \
10808 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10809 #define ADD8(a, b, n) \
10810 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10811 #define SUB8(a, b, n) \
10812 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10815 #include "op_addsub.h"
10817 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
10825 /* Unsigned sum of absolute byte differences. */
10826 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
10829 sum
= do_usad(a
, b
);
10830 sum
+= do_usad(a
>> 8, b
>> 8);
10831 sum
+= do_usad(a
>> 16, b
>> 16);
10832 sum
+= do_usad(a
>> 24, b
>> 24);
10836 /* For ARMv6 SEL instruction. */
10837 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
10849 mask
|= 0xff000000;
10850 return (a
& mask
) | (b
& ~mask
);
10854 * The upper bytes of val (above the number specified by 'bytes') must have
10855 * been zeroed out by the caller.
10857 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10861 stl_le_p(buf
, val
);
10863 /* zlib crc32 converts the accumulator and output to one's complement. */
10864 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
10867 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10871 stl_le_p(buf
, val
);
10873 /* Linux crc32c converts the output to one's complement. */
10874 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
10877 /* Return the exception level to which FP-disabled exceptions should
10878 * be taken, or 0 if FP is enabled.
10880 int fp_exception_el(CPUARMState
*env
, int cur_el
)
10882 #ifndef CONFIG_USER_ONLY
10885 /* CPACR and the CPTR registers don't exist before v6, so FP is
10886 * always accessible
10888 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
10892 if (arm_feature(env
, ARM_FEATURE_M
)) {
10893 /* CPACR can cause a NOCP UsageFault taken to current security state */
10894 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
10898 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
10899 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
10900 /* FP insns cause a NOCP UsageFault taken to Secure */
10908 hcr_el2
= arm_hcr_el2_eff(env
);
10910 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
10911 * 0, 2 : trap EL0 and EL1/PL1 accesses
10912 * 1 : trap only EL0 accesses
10913 * 3 : trap no accesses
10914 * This register is ignored if E2H+TGE are both set.
10916 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
10917 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
10927 /* Trap from Secure PL0 or PL1 to Secure PL1. */
10928 if (!arm_el_is_aa64(env
, 3)
10929 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
10940 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
10941 * to control non-secure access to the FPU. It doesn't have any
10942 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
10944 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
10945 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
10946 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
10947 /* FP insns act as UNDEF */
10948 return cur_el
== 2 ? 2 : 1;
10953 * CPTR_EL2 is present in v7VE or v8, and changes format
10954 * with HCR_EL2.E2H (regardless of TGE).
10957 if (hcr_el2
& HCR_E2H
) {
10958 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
10960 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
10968 } else if (arm_is_el2_enabled(env
)) {
10969 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
10975 /* CPTR_EL3 : present in v8 */
10976 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
10977 /* Trap all FP ops to EL3 */
10984 /* Return the exception level we're running at if this is our mmu_idx */
10985 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
10987 if (mmu_idx
& ARM_MMU_IDX_M
) {
10988 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
10992 case ARMMMUIdx_E10_0
:
10993 case ARMMMUIdx_E20_0
:
10994 case ARMMMUIdx_SE10_0
:
10995 case ARMMMUIdx_SE20_0
:
10997 case ARMMMUIdx_E10_1
:
10998 case ARMMMUIdx_E10_1_PAN
:
10999 case ARMMMUIdx_SE10_1
:
11000 case ARMMMUIdx_SE10_1_PAN
:
11003 case ARMMMUIdx_E20_2
:
11004 case ARMMMUIdx_E20_2_PAN
:
11005 case ARMMMUIdx_SE2
:
11006 case ARMMMUIdx_SE20_2
:
11007 case ARMMMUIdx_SE20_2_PAN
:
11009 case ARMMMUIdx_SE3
:
11012 g_assert_not_reached();
11017 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
11019 g_assert_not_reached();
11023 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
11028 if (arm_feature(env
, ARM_FEATURE_M
)) {
11029 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
11032 /* See ARM pseudo-function ELIsInHost. */
11035 hcr
= arm_hcr_el2_eff(env
);
11036 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
11037 idx
= ARMMMUIdx_E20_0
;
11039 idx
= ARMMMUIdx_E10_0
;
11043 if (env
->pstate
& PSTATE_PAN
) {
11044 idx
= ARMMMUIdx_E10_1_PAN
;
11046 idx
= ARMMMUIdx_E10_1
;
11050 /* Note that TGE does not apply at EL2. */
11051 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
11052 if (env
->pstate
& PSTATE_PAN
) {
11053 idx
= ARMMMUIdx_E20_2_PAN
;
11055 idx
= ARMMMUIdx_E20_2
;
11058 idx
= ARMMMUIdx_E2
;
11062 return ARMMMUIdx_SE3
;
11064 g_assert_not_reached();
11067 if (arm_is_secure_below_el3(env
)) {
11068 idx
&= ~ARM_MMU_IDX_A_NS
;
11074 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
11076 return arm_mmu_idx_el(env
, arm_current_el(env
));
11079 static CPUARMTBFlags
rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
11081 CPUARMTBFlags flags
)
11083 DP_TBFLAG_ANY(flags
, FPEXC_EL
, fp_el
);
11084 DP_TBFLAG_ANY(flags
, MMUIDX
, arm_to_core_mmu_idx(mmu_idx
));
11086 if (arm_singlestep_active(env
)) {
11087 DP_TBFLAG_ANY(flags
, SS_ACTIVE
, 1);
11092 static CPUARMTBFlags
rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
11094 CPUARMTBFlags flags
)
11096 bool sctlr_b
= arm_sctlr_b(env
);
11099 DP_TBFLAG_A32(flags
, SCTLR__B
, 1);
11101 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
11102 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11104 DP_TBFLAG_A32(flags
, NS
, !access_secure_reg(env
));
11106 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11109 static CPUARMTBFlags
rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
11112 CPUARMTBFlags flags
= {};
11113 uint32_t ccr
= env
->v7m
.ccr
[env
->v7m
.secure
];
11115 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
11116 if (ccr
& R_V7M_CCR_UNALIGN_TRP_MASK
) {
11117 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11120 if (arm_v7m_is_handler_mode(env
)) {
11121 DP_TBFLAG_M32(flags
, HANDLER
, 1);
11125 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
11126 * is suppressing them because the requested execution priority
11129 if (arm_feature(env
, ARM_FEATURE_V8
) &&
11130 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
11131 (ccr
& R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
11132 DP_TBFLAG_M32(flags
, STACKCHECK
, 1);
11135 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11138 static CPUARMTBFlags
rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
11141 CPUARMTBFlags flags
= {};
11142 int el
= arm_current_el(env
);
11144 if (arm_sctlr(env
, el
) & SCTLR_A
) {
11145 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11148 if (arm_el_is_aa64(env
, 1)) {
11149 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11152 if (el
< 2 && env
->cp15
.hstr_el2
&&
11153 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11154 DP_TBFLAG_A32(flags
, HSTR_ACTIVE
, 1);
11157 if (env
->uncached_cpsr
& CPSR_IL
) {
11158 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11161 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
11164 static CPUARMTBFlags
rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
11167 CPUARMTBFlags flags
= {};
11168 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
11169 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11173 DP_TBFLAG_ANY(flags
, AARCH64_STATE
, 1);
11175 /* Get control bits for tagged addresses. */
11176 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11177 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11179 DP_TBFLAG_A64(flags
, TBII
, tbii
);
11180 DP_TBFLAG_A64(flags
, TBID
, tbid
);
11182 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
11183 int sve_el
= sve_exception_el(env
, el
);
11186 * If either FP or SVE are disabled, translator does not need len.
11187 * If SVE EL > FP EL, FP exception has precedence, and translator
11188 * does not need SVE EL. Save potential re-translations by forcing
11189 * the unneeded data to zero.
11192 if (sve_el
> fp_el
) {
11195 } else if (sve_el
== 0) {
11196 DP_TBFLAG_A64(flags
, VL
, sve_vqm1_for_el(env
, el
));
11198 DP_TBFLAG_A64(flags
, SVEEXC_EL
, sve_el
);
11201 sctlr
= regime_sctlr(env
, stage1
);
11203 if (sctlr
& SCTLR_A
) {
11204 DP_TBFLAG_ANY(flags
, ALIGN_MEM
, 1);
11207 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
11208 DP_TBFLAG_ANY(flags
, BE_DATA
, 1);
11211 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
11213 * In order to save space in flags, we record only whether
11214 * pauth is "inactive", meaning all insns are implemented as
11215 * a nop, or "active" when some action must be performed.
11216 * The decision of which action to take is left to a helper.
11218 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
11219 DP_TBFLAG_A64(flags
, PAUTH_ACTIVE
, 1);
11223 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11224 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
11225 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
11226 DP_TBFLAG_A64(flags
, BT
, 1);
11230 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
11231 if (!(env
->pstate
& PSTATE_UAO
)) {
11233 case ARMMMUIdx_E10_1
:
11234 case ARMMMUIdx_E10_1_PAN
:
11235 case ARMMMUIdx_SE10_1
:
11236 case ARMMMUIdx_SE10_1_PAN
:
11237 /* TODO: ARMv8.3-NV */
11238 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11240 case ARMMMUIdx_E20_2
:
11241 case ARMMMUIdx_E20_2_PAN
:
11242 case ARMMMUIdx_SE20_2
:
11243 case ARMMMUIdx_SE20_2_PAN
:
11245 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
11246 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
11248 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
11249 DP_TBFLAG_A64(flags
, UNPRIV
, 1);
11257 if (env
->pstate
& PSTATE_IL
) {
11258 DP_TBFLAG_ANY(flags
, PSTATE__IL
, 1);
11261 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
11263 * Set MTE_ACTIVE if any access may be Checked, and leave clear
11264 * if all accesses must be Unchecked:
11265 * 1) If no TBI, then there are no tags in the address to check,
11266 * 2) If Tag Check Override, then all accesses are Unchecked,
11267 * 3) If Tag Check Fail == 0, then Checked access have no effect,
11268 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
11270 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
11271 DP_TBFLAG_A64(flags
, ATA
, 1);
11273 && !(env
->pstate
& PSTATE_TCO
)
11274 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
11275 DP_TBFLAG_A64(flags
, MTE_ACTIVE
, 1);
11278 /* And again for unprivileged accesses, if required. */
11279 if (EX_TBFLAG_A64(flags
, UNPRIV
)
11281 && !(env
->pstate
& PSTATE_TCO
)
11282 && (sctlr
& SCTLR_TCF0
)
11283 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
11284 DP_TBFLAG_A64(flags
, MTE0_ACTIVE
, 1);
11286 /* Cache TCMA as well as TBI. */
11287 DP_TBFLAG_A64(flags
, TCMA
, aa64_va_parameter_tcma(tcr
, mmu_idx
));
11290 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
11293 static CPUARMTBFlags
rebuild_hflags_internal(CPUARMState
*env
)
11295 int el
= arm_current_el(env
);
11296 int fp_el
= fp_exception_el(env
, el
);
11297 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11300 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11301 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
11302 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11304 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11308 void arm_rebuild_hflags(CPUARMState
*env
)
11310 env
->hflags
= rebuild_hflags_internal(env
);
11314 * If we have triggered a EL state change we can't rely on the
11315 * translator having passed it to us, we need to recompute.
11317 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
11319 int el
= arm_current_el(env
);
11320 int fp_el
= fp_exception_el(env
, el
);
11321 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11323 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11326 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
11328 int fp_el
= fp_exception_el(env
, el
);
11329 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11331 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
11335 * If we have triggered a EL state change we can't rely on the
11336 * translator having passed it to us, we need to recompute.
11338 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
11340 int el
= arm_current_el(env
);
11341 int fp_el
= fp_exception_el(env
, el
);
11342 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11343 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11346 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
11348 int fp_el
= fp_exception_el(env
, el
);
11349 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11351 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
11354 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
11356 int fp_el
= fp_exception_el(env
, el
);
11357 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
11359 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
11362 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
11364 #ifdef CONFIG_DEBUG_TCG
11365 CPUARMTBFlags c
= env
->hflags
;
11366 CPUARMTBFlags r
= rebuild_hflags_internal(env
);
11368 if (unlikely(c
.flags
!= r
.flags
|| c
.flags2
!= r
.flags2
)) {
11369 fprintf(stderr
, "TCG hflags mismatch "
11370 "(current:(0x%08x,0x" TARGET_FMT_lx
")"
11371 " rebuilt:(0x%08x,0x" TARGET_FMT_lx
")\n",
11372 c
.flags
, c
.flags2
, r
.flags
, r
.flags2
);
11378 static bool mve_no_pred(CPUARMState
*env
)
11381 * Return true if there is definitely no predication of MVE
11382 * instructions by VPR or LTPSIZE. (Returning false even if there
11383 * isn't any predication is OK; generated code will just be
11385 * If the CPU does not implement MVE then this TB flag is always 0.
11387 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
11388 * logic in gen_update_fp_context() needs to be updated to match.
11390 * We do not include the effect of the ECI bits here -- they are
11391 * tracked in other TB flags. This simplifies the logic for
11392 * "when did we emit code that changes the MVE_NO_PRED TB flag
11393 * and thus need to end the TB?".
11395 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
11398 if (env
->v7m
.vpr
) {
11401 if (env
->v7m
.ltpsize
< 4) {
11407 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
11408 target_ulong
*cs_base
, uint32_t *pflags
)
11410 CPUARMTBFlags flags
;
11412 assert_hflags_rebuild_correctly(env
);
11413 flags
= env
->hflags
;
11415 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
11417 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
11418 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
11421 *pc
= env
->regs
[15];
11423 if (arm_feature(env
, ARM_FEATURE_M
)) {
11424 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11425 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
11426 != env
->v7m
.secure
) {
11427 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
11430 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
11431 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
11432 (env
->v7m
.secure
&&
11433 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
11435 * ASPEN is set, but FPCA/SFPA indicate that there is no
11436 * active FP context; we must create a new FP context before
11437 * executing any FP insn.
11439 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
11442 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
11443 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
11444 DP_TBFLAG_M32(flags
, LSPACT
, 1);
11447 if (mve_no_pred(env
)) {
11448 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
11452 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
11453 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
11455 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11456 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
11458 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
11459 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
11461 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
11462 DP_TBFLAG_A32(flags
, VFPEN
, 1);
11466 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
11467 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
11471 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
11472 * states defined in the ARM ARM for software singlestep:
11473 * SS_ACTIVE PSTATE.SS State
11474 * 0 x Inactive (the TB flag for SS is always 0)
11475 * 1 0 Active-pending
11476 * 1 1 Active-not-pending
11477 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
11479 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
11480 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
11483 *pflags
= flags
.flags
;
11484 *cs_base
= flags
.flags2
;
11487 #ifdef TARGET_AARCH64
11489 * The manual says that when SVE is enabled and VQ is widened the
11490 * implementation is allowed to zero the previously inaccessible
11491 * portion of the registers. The corollary to that is that when
11492 * SVE is enabled and VQ is narrowed we are also allowed to zero
11493 * the now inaccessible portion of the registers.
11495 * The intent of this is that no predicate bit beyond VQ is ever set.
11496 * Which means that some operations on predicate registers themselves
11497 * may operate on full uint64_t or even unrolled across the maximum
11498 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
11499 * may well be cheaper than conditionals to restrict the operation
11500 * to the relevant portion of a uint16_t[16].
11502 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
11507 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
11508 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
11510 /* Zap the high bits of the zregs. */
11511 for (i
= 0; i
< 32; i
++) {
11512 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
11515 /* Zap the high bits of the pregs and ffr. */
11518 pmask
= ~(-1ULL << (16 * (vq
& 3)));
11520 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
11521 for (i
= 0; i
< 17; ++i
) {
11522 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
11529 * Notice a change in SVE vector size when changing EL.
11531 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
11532 int new_el
, bool el0_a64
)
11534 ARMCPU
*cpu
= env_archcpu(env
);
11535 int old_len
, new_len
;
11536 bool old_a64
, new_a64
;
11538 /* Nothing to do if no SVE. */
11539 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
11543 /* Nothing to do if FP is disabled in either EL. */
11544 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
11549 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
11550 * at ELx, or not available because the EL is in AArch32 state, then
11551 * for all purposes other than a direct read, the ZCR_ELx.LEN field
11552 * has an effective value of 0".
11554 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
11555 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
11556 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
11557 * we already have the correct register contents when encountering the
11558 * vq0->vq0 transition between EL0->EL1.
11560 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
11561 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
11562 ? sve_vqm1_for_el(env
, old_el
) : 0);
11563 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
11564 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
11565 ? sve_vqm1_for_el(env
, new_el
) : 0);
11567 /* When changing vector length, clear inaccessible state. */
11568 if (new_len
< old_len
) {
11569 aarch64_sve_narrow_vq(env
, new_len
+ 1);