2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
32 #include "trace-tcg.h"
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 # define LOG_DISAS(...) do { } while (0)
49 /*****************************************************************************/
50 /* Code translation helpers */
52 /* global register indexes */
53 static TCGv_env cpu_env
;
54 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
60 static TCGv cpu_gpr
[32];
61 static TCGv cpu_gprh
[32];
62 static TCGv_i64 cpu_fpr
[32];
63 static TCGv_i64 cpu_avrh
[32], cpu_avrl
[32];
64 static TCGv_i64 cpu_vsr
[32];
65 static TCGv_i32 cpu_crf
[8];
70 #if defined(TARGET_PPC64)
73 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
;
74 static TCGv cpu_reserve
;
75 static TCGv cpu_fpscr
;
76 static TCGv_i32 cpu_access_type
;
78 #include "exec/gen-icount.h"
80 void ppc_translate_init(void)
84 size_t cpu_reg_names_size
;
85 static int done_init
= 0;
90 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
91 tcg_ctx
.tcg_env
= cpu_env
;
94 cpu_reg_names_size
= sizeof(cpu_reg_names
);
96 for (i
= 0; i
< 8; i
++) {
97 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
98 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
99 offsetof(CPUPPCState
, crf
[i
]), p
);
101 cpu_reg_names_size
-= 5;
104 for (i
= 0; i
< 32; i
++) {
105 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
106 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
107 offsetof(CPUPPCState
, gpr
[i
]), p
);
108 p
+= (i
< 10) ? 3 : 4;
109 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
110 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
111 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
112 offsetof(CPUPPCState
, gprh
[i
]), p
);
113 p
+= (i
< 10) ? 4 : 5;
114 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
116 snprintf(p
, cpu_reg_names_size
, "fp%d", i
);
117 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
118 offsetof(CPUPPCState
, fpr
[i
]), p
);
119 p
+= (i
< 10) ? 4 : 5;
120 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
122 snprintf(p
, cpu_reg_names_size
, "avr%dH", i
);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
125 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
127 cpu_avrh
[i
] = tcg_global_mem_new_i64(cpu_env
,
128 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
130 p
+= (i
< 10) ? 6 : 7;
131 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
133 snprintf(p
, cpu_reg_names_size
, "avr%dL", i
);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
136 offsetof(CPUPPCState
, avr
[i
].u64
[1]), p
);
138 cpu_avrl
[i
] = tcg_global_mem_new_i64(cpu_env
,
139 offsetof(CPUPPCState
, avr
[i
].u64
[0]), p
);
141 p
+= (i
< 10) ? 6 : 7;
142 cpu_reg_names_size
-= (i
< 10) ? 6 : 7;
143 snprintf(p
, cpu_reg_names_size
, "vsr%d", i
);
144 cpu_vsr
[i
] = tcg_global_mem_new_i64(cpu_env
,
145 offsetof(CPUPPCState
, vsr
[i
]), p
);
146 p
+= (i
< 10) ? 5 : 6;
147 cpu_reg_names_size
-= (i
< 10) ? 5 : 6;
150 cpu_nip
= tcg_global_mem_new(cpu_env
,
151 offsetof(CPUPPCState
, nip
), "nip");
153 cpu_msr
= tcg_global_mem_new(cpu_env
,
154 offsetof(CPUPPCState
, msr
), "msr");
156 cpu_ctr
= tcg_global_mem_new(cpu_env
,
157 offsetof(CPUPPCState
, ctr
), "ctr");
159 cpu_lr
= tcg_global_mem_new(cpu_env
,
160 offsetof(CPUPPCState
, lr
), "lr");
162 #if defined(TARGET_PPC64)
163 cpu_cfar
= tcg_global_mem_new(cpu_env
,
164 offsetof(CPUPPCState
, cfar
), "cfar");
167 cpu_xer
= tcg_global_mem_new(cpu_env
,
168 offsetof(CPUPPCState
, xer
), "xer");
169 cpu_so
= tcg_global_mem_new(cpu_env
,
170 offsetof(CPUPPCState
, so
), "SO");
171 cpu_ov
= tcg_global_mem_new(cpu_env
,
172 offsetof(CPUPPCState
, ov
), "OV");
173 cpu_ca
= tcg_global_mem_new(cpu_env
,
174 offsetof(CPUPPCState
, ca
), "CA");
176 cpu_reserve
= tcg_global_mem_new(cpu_env
,
177 offsetof(CPUPPCState
, reserve_addr
),
180 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
181 offsetof(CPUPPCState
, fpscr
), "fpscr");
183 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
184 offsetof(CPUPPCState
, access_type
), "access_type");
189 /* internal defines */
190 struct DisasContext
{
191 struct TranslationBlock
*tb
;
195 /* Routine used to access memory */
200 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask
;
203 #if defined(TARGET_PPC64)
212 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled
;
214 uint64_t insns_flags
;
215 uint64_t insns_flags2
;
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext
*ctx
)
221 #if defined(TARGET_WORDS_BIGENDIAN)
224 return !ctx
->le_mode
;
228 /* True when active word size < size of target_long. */
230 # define NARROW_MODE(C) (!(C)->sf_mode)
232 # define NARROW_MODE(C) 0
235 struct opc_handler_t
{
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
240 /* instruction type */
242 /* extended instruction type */
245 void (*handler
)(DisasContext
*ctx
);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
249 #if defined(DO_PPC_STATISTICS)
254 static inline void gen_reset_fpstatus(void)
256 gen_helper_reset_fpstatus(cpu_env
);
259 static inline void gen_compute_fprf(TCGv_i64 arg
)
261 gen_helper_compute_fprf(cpu_env
, arg
);
262 gen_helper_float_check_status(cpu_env
);
265 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
267 if (ctx
->access_type
!= access_type
) {
268 tcg_gen_movi_i32(cpu_access_type
, access_type
);
269 ctx
->access_type
= access_type
;
273 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
275 if (NARROW_MODE(ctx
)) {
278 tcg_gen_movi_tl(cpu_nip
, nip
);
281 void gen_update_current_nip(void *opaque
)
283 DisasContext
*ctx
= opaque
;
285 tcg_gen_movi_tl(cpu_nip
, ctx
->nip
);
288 static inline void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
291 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
292 gen_update_nip(ctx
, ctx
->nip
);
294 t0
= tcg_const_i32(excp
);
295 t1
= tcg_const_i32(error
);
296 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
297 tcg_temp_free_i32(t0
);
298 tcg_temp_free_i32(t1
);
299 ctx
->exception
= (excp
);
302 static inline void gen_exception(DisasContext
*ctx
, uint32_t excp
)
305 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
306 gen_update_nip(ctx
, ctx
->nip
);
308 t0
= tcg_const_i32(excp
);
309 gen_helper_raise_exception(cpu_env
, t0
);
310 tcg_temp_free_i32(t0
);
311 ctx
->exception
= (excp
);
314 static inline void gen_debug_exception(DisasContext
*ctx
)
318 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
319 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
320 gen_update_nip(ctx
, ctx
->nip
);
322 t0
= tcg_const_i32(EXCP_DEBUG
);
323 gen_helper_raise_exception(cpu_env
, t0
);
324 tcg_temp_free_i32(t0
);
327 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
329 /* Will be converted to program check if needed */
330 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
333 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
335 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
338 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
340 /* Will be converted to program check if needed */
341 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
344 /* Stop translation */
345 static inline void gen_stop_exception(DisasContext
*ctx
)
347 gen_update_nip(ctx
, ctx
->nip
);
348 ctx
->exception
= POWERPC_EXCP_STOP
;
351 #ifndef CONFIG_USER_ONLY
352 /* No need to update nip here, as execution flow will change */
353 static inline void gen_sync_exception(DisasContext
*ctx
)
355 ctx
->exception
= POWERPC_EXCP_SYNC
;
359 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
360 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
362 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
363 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
365 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
366 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
368 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
369 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
371 typedef struct opcode_t
{
372 unsigned char opc1
, opc2
, opc3
;
373 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
374 unsigned char pad
[5];
376 unsigned char pad
[1];
378 opc_handler_t handler
;
382 /* Helpers for priv. check */
385 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
388 #if defined(CONFIG_USER_ONLY)
389 #define CHK_HV GEN_PRIV
390 #define CHK_SV GEN_PRIV
394 if (unlikely(ctx->pr || !ctx->hv)) { \
400 if (unlikely(ctx->pr)) { \
409 /*****************************************************************************/
410 /*** Instruction decoding ***/
411 #define EXTRACT_HELPER(name, shift, nb) \
412 static inline uint32_t name(uint32_t opcode) \
414 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
417 #define EXTRACT_SHELPER(name, shift, nb) \
418 static inline int32_t name(uint32_t opcode) \
420 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
423 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
424 static inline uint32_t name(uint32_t opcode) \
426 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
427 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
430 EXTRACT_HELPER(opc1
, 26, 6);
432 EXTRACT_HELPER(opc2
, 1, 5);
434 EXTRACT_HELPER(opc3
, 6, 5);
435 /* Update Cr0 flags */
436 EXTRACT_HELPER(Rc
, 0, 1);
437 /* Update Cr6 flags (Altivec) */
438 EXTRACT_HELPER(Rc21
, 10, 1);
440 EXTRACT_HELPER(rD
, 21, 5);
442 EXTRACT_HELPER(rS
, 21, 5);
444 EXTRACT_HELPER(rA
, 16, 5);
446 EXTRACT_HELPER(rB
, 11, 5);
448 EXTRACT_HELPER(rC
, 6, 5);
450 EXTRACT_HELPER(crfD
, 23, 3);
451 EXTRACT_HELPER(crfS
, 18, 3);
452 EXTRACT_HELPER(crbD
, 21, 5);
453 EXTRACT_HELPER(crbA
, 16, 5);
454 EXTRACT_HELPER(crbB
, 11, 5);
456 EXTRACT_HELPER(_SPR
, 11, 10);
457 static inline uint32_t SPR(uint32_t opcode
)
459 uint32_t sprn
= _SPR(opcode
);
461 return ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
463 /*** Get constants ***/
464 /* 16 bits signed immediate value */
465 EXTRACT_SHELPER(SIMM
, 0, 16);
466 /* 16 bits unsigned immediate value */
467 EXTRACT_HELPER(UIMM
, 0, 16);
468 /* 5 bits signed immediate value */
469 EXTRACT_HELPER(SIMM5
, 16, 5);
470 /* 5 bits signed immediate value */
471 EXTRACT_HELPER(UIMM5
, 16, 5);
473 EXTRACT_HELPER(NB
, 11, 5);
475 EXTRACT_HELPER(SH
, 11, 5);
476 /* Vector shift count */
477 EXTRACT_HELPER(VSH
, 6, 4);
479 EXTRACT_HELPER(MB
, 6, 5);
481 EXTRACT_HELPER(ME
, 1, 5);
483 EXTRACT_HELPER(TO
, 21, 5);
485 EXTRACT_HELPER(CRM
, 12, 8);
487 #ifndef CONFIG_USER_ONLY
488 EXTRACT_HELPER(SR
, 16, 4);
492 EXTRACT_HELPER(FPBF
, 23, 3);
493 EXTRACT_HELPER(FPIMM
, 12, 4);
494 EXTRACT_HELPER(FPL
, 25, 1);
495 EXTRACT_HELPER(FPFLM
, 17, 8);
496 EXTRACT_HELPER(FPW
, 16, 1);
498 /*** Jump target decoding ***/
499 /* Immediate address */
500 static inline target_ulong
LI(uint32_t opcode
)
502 return (opcode
>> 0) & 0x03FFFFFC;
505 static inline uint32_t BD(uint32_t opcode
)
507 return (opcode
>> 0) & 0xFFFC;
510 EXTRACT_HELPER(BO
, 21, 5);
511 EXTRACT_HELPER(BI
, 16, 5);
512 /* Absolute/relative address */
513 EXTRACT_HELPER(AA
, 1, 1);
515 EXTRACT_HELPER(LK
, 0, 1);
518 EXTRACT_HELPER(DCM
, 10, 6)
521 EXTRACT_HELPER(RMC
, 9, 2)
523 /* Create a mask between <start> and <end> bits */
524 static inline target_ulong
MASK(uint32_t start
, uint32_t end
)
528 #if defined(TARGET_PPC64)
529 if (likely(start
== 0)) {
530 ret
= UINT64_MAX
<< (63 - end
);
531 } else if (likely(end
== 63)) {
532 ret
= UINT64_MAX
>> start
;
535 if (likely(start
== 0)) {
536 ret
= UINT32_MAX
<< (31 - end
);
537 } else if (likely(end
== 31)) {
538 ret
= UINT32_MAX
>> start
;
542 ret
= (((target_ulong
)(-1ULL)) >> (start
)) ^
543 (((target_ulong
)(-1ULL) >> (end
)) >> 1);
544 if (unlikely(start
> end
))
551 EXTRACT_HELPER_SPLIT(xT
, 0, 1, 21, 5);
552 EXTRACT_HELPER_SPLIT(xS
, 0, 1, 21, 5);
553 EXTRACT_HELPER_SPLIT(xA
, 2, 1, 16, 5);
554 EXTRACT_HELPER_SPLIT(xB
, 1, 1, 11, 5);
555 EXTRACT_HELPER_SPLIT(xC
, 3, 1, 6, 5);
556 EXTRACT_HELPER(DM
, 8, 2);
557 EXTRACT_HELPER(UIM
, 16, 2);
558 EXTRACT_HELPER(SHW
, 8, 2);
559 EXTRACT_HELPER(SP
, 19, 2);
560 /*****************************************************************************/
561 /* PowerPC instructions table */
563 #if defined(DO_PPC_STATISTICS)
564 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
574 .handler = &gen_##name, \
575 .oname = stringify(name), \
577 .oname = stringify(name), \
579 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
590 .handler = &gen_##name, \
591 .oname = stringify(name), \
593 .oname = stringify(name), \
595 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
605 .handler = &gen_##name, \
611 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
621 .handler = &gen_##name, \
623 .oname = stringify(name), \
625 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
636 .handler = &gen_##name, \
638 .oname = stringify(name), \
640 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
650 .handler = &gen_##name, \
656 /* SPR load/store helpers */
657 static inline void gen_load_spr(TCGv t
, int reg
)
659 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
662 static inline void gen_store_spr(int reg
, TCGv t
)
664 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
667 /* Invalid instruction */
668 static void gen_invalid(DisasContext
*ctx
)
670 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
673 static opc_handler_t invalid_handler
= {
674 .inval1
= 0xFFFFFFFF,
675 .inval2
= 0xFFFFFFFF,
678 .handler
= gen_invalid
,
681 /*** Integer comparison ***/
683 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
685 TCGv t0
= tcg_temp_new();
686 TCGv_i32 t1
= tcg_temp_new_i32();
688 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
690 tcg_gen_setcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
);
691 tcg_gen_trunc_tl_i32(t1
, t0
);
692 tcg_gen_shli_i32(t1
, t1
, CRF_LT
);
693 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
695 tcg_gen_setcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
);
696 tcg_gen_trunc_tl_i32(t1
, t0
);
697 tcg_gen_shli_i32(t1
, t1
, CRF_GT
);
698 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
700 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, arg0
, arg1
);
701 tcg_gen_trunc_tl_i32(t1
, t0
);
702 tcg_gen_shli_i32(t1
, t1
, CRF_EQ
);
703 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t1
);
706 tcg_temp_free_i32(t1
);
709 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
711 TCGv t0
= tcg_const_tl(arg1
);
712 gen_op_cmp(arg0
, t0
, s
, crf
);
716 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
722 tcg_gen_ext32s_tl(t0
, arg0
);
723 tcg_gen_ext32s_tl(t1
, arg1
);
725 tcg_gen_ext32u_tl(t0
, arg0
);
726 tcg_gen_ext32u_tl(t1
, arg1
);
728 gen_op_cmp(t0
, t1
, s
, crf
);
733 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
735 TCGv t0
= tcg_const_tl(arg1
);
736 gen_op_cmp32(arg0
, t0
, s
, crf
);
740 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
742 if (NARROW_MODE(ctx
)) {
743 gen_op_cmpi32(reg
, 0, 1, 0);
745 gen_op_cmpi(reg
, 0, 1, 0);
750 static void gen_cmp(DisasContext
*ctx
)
752 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
753 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
754 1, crfD(ctx
->opcode
));
756 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
757 1, crfD(ctx
->opcode
));
762 static void gen_cmpi(DisasContext
*ctx
)
764 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
765 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
766 1, crfD(ctx
->opcode
));
768 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
769 1, crfD(ctx
->opcode
));
774 static void gen_cmpl(DisasContext
*ctx
)
776 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
777 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
778 0, crfD(ctx
->opcode
));
780 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
781 0, crfD(ctx
->opcode
));
786 static void gen_cmpli(DisasContext
*ctx
)
788 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
789 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
790 0, crfD(ctx
->opcode
));
792 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
793 0, crfD(ctx
->opcode
));
797 /* isel (PowerPC 2.03 specification) */
798 static void gen_isel(DisasContext
*ctx
)
800 uint32_t bi
= rC(ctx
->opcode
);
801 uint32_t mask
= 0x08 >> (bi
& 0x03);
802 TCGv t0
= tcg_temp_new();
805 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
806 tcg_gen_andi_tl(t0
, t0
, mask
);
808 zr
= tcg_const_tl(0);
809 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
810 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
811 cpu_gpr
[rB(ctx
->opcode
)]);
816 /* cmpb: PowerPC 2.05 specification */
817 static void gen_cmpb(DisasContext
*ctx
)
819 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
820 cpu_gpr
[rB(ctx
->opcode
)]);
823 /*** Integer arithmetic ***/
825 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
826 TCGv arg1
, TCGv arg2
, int sub
)
828 TCGv t0
= tcg_temp_new();
830 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
831 tcg_gen_xor_tl(t0
, arg1
, arg2
);
833 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
835 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
838 if (NARROW_MODE(ctx
)) {
839 tcg_gen_ext32s_tl(cpu_ov
, cpu_ov
);
841 tcg_gen_shri_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1);
842 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
845 /* Common add function */
846 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
847 TCGv arg2
, bool add_ca
, bool compute_ca
,
848 bool compute_ov
, bool compute_rc0
)
852 if (compute_ca
|| compute_ov
) {
857 if (NARROW_MODE(ctx
)) {
858 /* Caution: a non-obvious corner case of the spec is that we
859 must produce the *entire* 64-bit addition, but produce the
860 carry into bit 32. */
861 TCGv t1
= tcg_temp_new();
862 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
863 tcg_gen_add_tl(t0
, arg1
, arg2
);
865 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
867 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changed w/ carry */
869 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
870 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
872 TCGv zero
= tcg_const_tl(0);
874 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, cpu_ca
, zero
);
875 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, arg2
, zero
);
877 tcg_gen_add2_tl(t0
, cpu_ca
, arg1
, zero
, arg2
, zero
);
882 tcg_gen_add_tl(t0
, arg1
, arg2
);
884 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
889 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
891 if (unlikely(compute_rc0
)) {
892 gen_set_Rc0(ctx
, t0
);
895 if (!TCGV_EQUAL(t0
, ret
)) {
896 tcg_gen_mov_tl(ret
, t0
);
900 /* Add functions with two operands */
901 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
902 static void glue(gen_, name)(DisasContext *ctx) \
904 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
905 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
906 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
908 /* Add functions with one operand and one immediate */
909 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
910 add_ca, compute_ca, compute_ov) \
911 static void glue(gen_, name)(DisasContext *ctx) \
913 TCGv t0 = tcg_const_tl(const_val); \
914 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
915 cpu_gpr[rA(ctx->opcode)], t0, \
916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
920 /* add add. addo addo. */
921 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
922 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
923 /* addc addc. addco addco. */
924 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
925 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
926 /* adde adde. addeo addeo. */
927 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
928 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
929 /* addme addme. addmeo addmeo. */
930 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
931 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
932 /* addze addze. addzeo addzeo.*/
933 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
934 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
936 static void gen_addi(DisasContext
*ctx
)
938 target_long simm
= SIMM(ctx
->opcode
);
940 if (rA(ctx
->opcode
) == 0) {
942 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
944 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
945 cpu_gpr
[rA(ctx
->opcode
)], simm
);
949 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
951 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
952 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
953 c
, 0, 1, 0, compute_rc0
);
957 static void gen_addic(DisasContext
*ctx
)
959 gen_op_addic(ctx
, 0);
962 static void gen_addic_(DisasContext
*ctx
)
964 gen_op_addic(ctx
, 1);
968 static void gen_addis(DisasContext
*ctx
)
970 target_long simm
= SIMM(ctx
->opcode
);
972 if (rA(ctx
->opcode
) == 0) {
974 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
976 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
977 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
981 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
982 TCGv arg2
, int sign
, int compute_ov
)
984 TCGLabel
*l1
= gen_new_label();
985 TCGLabel
*l2
= gen_new_label();
986 TCGv_i32 t0
= tcg_temp_local_new_i32();
987 TCGv_i32 t1
= tcg_temp_local_new_i32();
989 tcg_gen_trunc_tl_i32(t0
, arg1
);
990 tcg_gen_trunc_tl_i32(t1
, arg2
);
991 tcg_gen_brcondi_i32(TCG_COND_EQ
, t1
, 0, l1
);
993 TCGLabel
*l3
= gen_new_label();
994 tcg_gen_brcondi_i32(TCG_COND_NE
, t1
, -1, l3
);
995 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, INT32_MIN
, l1
);
997 tcg_gen_div_i32(t0
, t0
, t1
);
999 tcg_gen_divu_i32(t0
, t0
, t1
);
1002 tcg_gen_movi_tl(cpu_ov
, 0);
1007 tcg_gen_sari_i32(t0
, t0
, 31);
1009 tcg_gen_movi_i32(t0
, 0);
1012 tcg_gen_movi_tl(cpu_ov
, 1);
1013 tcg_gen_movi_tl(cpu_so
, 1);
1016 tcg_gen_extu_i32_tl(ret
, t0
);
1017 tcg_temp_free_i32(t0
);
1018 tcg_temp_free_i32(t1
);
1019 if (unlikely(Rc(ctx
->opcode
) != 0))
1020 gen_set_Rc0(ctx
, ret
);
1023 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1024 static void glue(gen_, name)(DisasContext *ctx) \
1026 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1027 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1028 sign, compute_ov); \
1030 /* divwu divwu. divwuo divwuo. */
1031 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1032 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1033 /* divw divw. divwo divwo. */
1034 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1035 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1037 /* div[wd]eu[o][.] */
1038 #define GEN_DIVE(name, hlpr, compute_ov) \
1039 static void gen_##name(DisasContext *ctx) \
1041 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1042 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1043 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1044 tcg_temp_free_i32(t0); \
1045 if (unlikely(Rc(ctx->opcode) != 0)) { \
1046 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1050 GEN_DIVE(divweu
, divweu
, 0);
1051 GEN_DIVE(divweuo
, divweu
, 1);
1052 GEN_DIVE(divwe
, divwe
, 0);
1053 GEN_DIVE(divweo
, divwe
, 1);
1055 #if defined(TARGET_PPC64)
1056 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1057 TCGv arg2
, int sign
, int compute_ov
)
1059 TCGLabel
*l1
= gen_new_label();
1060 TCGLabel
*l2
= gen_new_label();
1062 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg2
, 0, l1
);
1064 TCGLabel
*l3
= gen_new_label();
1065 tcg_gen_brcondi_i64(TCG_COND_NE
, arg2
, -1, l3
);
1066 tcg_gen_brcondi_i64(TCG_COND_EQ
, arg1
, INT64_MIN
, l1
);
1068 tcg_gen_div_i64(ret
, arg1
, arg2
);
1070 tcg_gen_divu_i64(ret
, arg1
, arg2
);
1073 tcg_gen_movi_tl(cpu_ov
, 0);
1078 tcg_gen_sari_i64(ret
, arg1
, 63);
1080 tcg_gen_movi_i64(ret
, 0);
1083 tcg_gen_movi_tl(cpu_ov
, 1);
1084 tcg_gen_movi_tl(cpu_so
, 1);
1087 if (unlikely(Rc(ctx
->opcode
) != 0))
1088 gen_set_Rc0(ctx
, ret
);
1090 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1091 static void glue(gen_, name)(DisasContext *ctx) \
1093 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1094 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1095 sign, compute_ov); \
1097 /* divwu divwu. divwuo divwuo. */
1098 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1099 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1100 /* divw divw. divwo divwo. */
1101 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1102 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1104 GEN_DIVE(divdeu
, divdeu
, 0);
1105 GEN_DIVE(divdeuo
, divdeu
, 1);
1106 GEN_DIVE(divde
, divde
, 0);
1107 GEN_DIVE(divdeo
, divde
, 1);
1111 static void gen_mulhw(DisasContext
*ctx
)
1113 TCGv_i32 t0
= tcg_temp_new_i32();
1114 TCGv_i32 t1
= tcg_temp_new_i32();
1116 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1117 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1118 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1119 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1120 tcg_temp_free_i32(t0
);
1121 tcg_temp_free_i32(t1
);
1122 if (unlikely(Rc(ctx
->opcode
) != 0))
1123 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1126 /* mulhwu mulhwu. */
1127 static void gen_mulhwu(DisasContext
*ctx
)
1129 TCGv_i32 t0
= tcg_temp_new_i32();
1130 TCGv_i32 t1
= tcg_temp_new_i32();
1132 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1133 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1134 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1135 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1136 tcg_temp_free_i32(t0
);
1137 tcg_temp_free_i32(t1
);
1138 if (unlikely(Rc(ctx
->opcode
) != 0))
1139 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1143 static void gen_mullw(DisasContext
*ctx
)
1145 #if defined(TARGET_PPC64)
1147 t0
= tcg_temp_new_i64();
1148 t1
= tcg_temp_new_i64();
1149 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1150 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1151 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1155 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1156 cpu_gpr
[rB(ctx
->opcode
)]);
1158 if (unlikely(Rc(ctx
->opcode
) != 0))
1159 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1162 /* mullwo mullwo. */
1163 static void gen_mullwo(DisasContext
*ctx
)
1165 TCGv_i32 t0
= tcg_temp_new_i32();
1166 TCGv_i32 t1
= tcg_temp_new_i32();
1168 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1169 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1170 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1171 #if defined(TARGET_PPC64)
1172 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1174 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1177 tcg_gen_sari_i32(t0
, t0
, 31);
1178 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1179 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1180 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1182 tcg_temp_free_i32(t0
);
1183 tcg_temp_free_i32(t1
);
1184 if (unlikely(Rc(ctx
->opcode
) != 0))
1185 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1189 static void gen_mulli(DisasContext
*ctx
)
1191 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1195 #if defined(TARGET_PPC64)
1197 static void gen_mulhd(DisasContext
*ctx
)
1199 TCGv lo
= tcg_temp_new();
1200 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1201 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1203 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1204 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1208 /* mulhdu mulhdu. */
1209 static void gen_mulhdu(DisasContext
*ctx
)
1211 TCGv lo
= tcg_temp_new();
1212 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1213 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1215 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1216 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1221 static void gen_mulld(DisasContext
*ctx
)
1223 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1224 cpu_gpr
[rB(ctx
->opcode
)]);
1225 if (unlikely(Rc(ctx
->opcode
) != 0))
1226 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1229 /* mulldo mulldo. */
1230 static void gen_mulldo(DisasContext
*ctx
)
1232 TCGv_i64 t0
= tcg_temp_new_i64();
1233 TCGv_i64 t1
= tcg_temp_new_i64();
1235 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1236 cpu_gpr
[rB(ctx
->opcode
)]);
1237 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1239 tcg_gen_sari_i64(t0
, t0
, 63);
1240 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1241 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1243 tcg_temp_free_i64(t0
);
1244 tcg_temp_free_i64(t1
);
1246 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1247 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1252 /* Common subf function */
1253 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1254 TCGv arg2
, bool add_ca
, bool compute_ca
,
1255 bool compute_ov
, bool compute_rc0
)
1259 if (compute_ca
|| compute_ov
) {
1260 t0
= tcg_temp_new();
1264 /* dest = ~arg1 + arg2 [+ ca]. */
1265 if (NARROW_MODE(ctx
)) {
1266 /* Caution: a non-obvious corner case of the spec is that we
1267 must produce the *entire* 64-bit addition, but produce the
1268 carry into bit 32. */
1269 TCGv inv1
= tcg_temp_new();
1270 TCGv t1
= tcg_temp_new();
1271 tcg_gen_not_tl(inv1
, arg1
);
1273 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1275 tcg_gen_addi_tl(t0
, arg2
, 1);
1277 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1278 tcg_gen_add_tl(t0
, t0
, inv1
);
1279 tcg_temp_free(inv1
);
1280 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1282 tcg_gen_shri_tl(cpu_ca
, cpu_ca
, 32); /* extract bit 32 */
1283 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
1284 } else if (add_ca
) {
1285 TCGv zero
, inv1
= tcg_temp_new();
1286 tcg_gen_not_tl(inv1
, arg1
);
1287 zero
= tcg_const_tl(0);
1288 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1289 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1290 tcg_temp_free(zero
);
1291 tcg_temp_free(inv1
);
1293 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1294 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1296 } else if (add_ca
) {
1297 /* Since we're ignoring carry-out, we can simplify the
1298 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1299 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1300 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1301 tcg_gen_subi_tl(t0
, t0
, 1);
1303 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1307 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1309 if (unlikely(compute_rc0
)) {
1310 gen_set_Rc0(ctx
, t0
);
1313 if (!TCGV_EQUAL(t0
, ret
)) {
1314 tcg_gen_mov_tl(ret
, t0
);
1318 /* Sub functions with Two operands functions */
1319 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1320 static void glue(gen_, name)(DisasContext *ctx) \
1322 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1323 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1324 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1326 /* Sub functions with one operand and one immediate */
1327 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1328 add_ca, compute_ca, compute_ov) \
1329 static void glue(gen_, name)(DisasContext *ctx) \
1331 TCGv t0 = tcg_const_tl(const_val); \
1332 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1333 cpu_gpr[rA(ctx->opcode)], t0, \
1334 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1335 tcg_temp_free(t0); \
1337 /* subf subf. subfo subfo. */
1338 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1339 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1340 /* subfc subfc. subfco subfco. */
1341 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1342 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1343 /* subfe subfe. subfeo subfo. */
1344 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1345 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1346 /* subfme subfme. subfmeo subfmeo. */
1347 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1348 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1349 /* subfze subfze. subfzeo subfzeo.*/
1350 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1351 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1354 static void gen_subfic(DisasContext
*ctx
)
1356 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1357 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1362 /* neg neg. nego nego. */
1363 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1365 TCGv zero
= tcg_const_tl(0);
1366 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1367 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1368 tcg_temp_free(zero
);
1371 static void gen_neg(DisasContext
*ctx
)
1373 gen_op_arith_neg(ctx
, 0);
1376 static void gen_nego(DisasContext
*ctx
)
1378 gen_op_arith_neg(ctx
, 1);
1381 /*** Integer logical ***/
1382 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1383 static void glue(gen_, name)(DisasContext *ctx) \
1385 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1386 cpu_gpr[rB(ctx->opcode)]); \
1387 if (unlikely(Rc(ctx->opcode) != 0)) \
1388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1391 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1392 static void glue(gen_, name)(DisasContext *ctx) \
1394 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1395 if (unlikely(Rc(ctx->opcode) != 0)) \
1396 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1400 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1402 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1405 static void gen_andi_(DisasContext
*ctx
)
1407 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1408 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1412 static void gen_andis_(DisasContext
*ctx
)
1414 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1415 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1419 static void gen_cntlzw(DisasContext
*ctx
)
1421 gen_helper_cntlzw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1422 if (unlikely(Rc(ctx
->opcode
) != 0))
1423 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1426 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1427 /* extsb & extsb. */
1428 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1429 /* extsh & extsh. */
1430 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1432 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1434 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1436 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1437 static void gen_pause(DisasContext
*ctx
)
1439 TCGv_i32 t0
= tcg_const_i32(0);
1440 tcg_gen_st_i32(t0
, cpu_env
,
1441 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1442 tcg_temp_free_i32(t0
);
1444 /* Stop translation, this gives other CPUs a chance to run */
1445 gen_exception_err(ctx
, EXCP_HLT
, 1);
1447 #endif /* defined(TARGET_PPC64) */
1450 static void gen_or(DisasContext
*ctx
)
1454 rs
= rS(ctx
->opcode
);
1455 ra
= rA(ctx
->opcode
);
1456 rb
= rB(ctx
->opcode
);
1457 /* Optimisation for mr. ri case */
1458 if (rs
!= ra
|| rs
!= rb
) {
1460 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1462 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1463 if (unlikely(Rc(ctx
->opcode
) != 0))
1464 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1465 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1466 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1467 #if defined(TARGET_PPC64)
1473 /* Set process priority to low */
1477 /* Set process priority to medium-low */
1481 /* Set process priority to normal */
1484 #if !defined(CONFIG_USER_ONLY)
1487 /* Set process priority to very low */
1493 /* Set process priority to medium-hight */
1499 /* Set process priority to high */
1504 if (ctx
->hv
&& !ctx
->pr
) {
1505 /* Set process priority to very high */
1515 TCGv t0
= tcg_temp_new();
1516 gen_load_spr(t0
, SPR_PPR
);
1517 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1518 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1519 gen_store_spr(SPR_PPR
, t0
);
1521 /* Pause us out of TCG otherwise spin loops with smt_low
1522 * eat too much CPU and the kernel hangs
1524 #if !defined(CONFIG_USER_ONLY)
1532 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1535 static void gen_xor(DisasContext
*ctx
)
1537 /* Optimisation for "set to zero" case */
1538 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1539 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1541 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1542 if (unlikely(Rc(ctx
->opcode
) != 0))
1543 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1547 static void gen_ori(DisasContext
*ctx
)
1549 target_ulong uimm
= UIMM(ctx
->opcode
);
1551 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1554 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1558 static void gen_oris(DisasContext
*ctx
)
1560 target_ulong uimm
= UIMM(ctx
->opcode
);
1562 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1566 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1570 static void gen_xori(DisasContext
*ctx
)
1572 target_ulong uimm
= UIMM(ctx
->opcode
);
1574 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1578 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1582 static void gen_xoris(DisasContext
*ctx
)
1584 target_ulong uimm
= UIMM(ctx
->opcode
);
1586 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1590 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1593 /* popcntb : PowerPC 2.03 specification */
1594 static void gen_popcntb(DisasContext
*ctx
)
1596 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1599 static void gen_popcntw(DisasContext
*ctx
)
1601 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1604 #if defined(TARGET_PPC64)
1605 /* popcntd: PowerPC 2.06 specification */
1606 static void gen_popcntd(DisasContext
*ctx
)
1608 gen_helper_popcntd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1612 /* prtyw: PowerPC 2.05 specification */
1613 static void gen_prtyw(DisasContext
*ctx
)
1615 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1616 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1617 TCGv t0
= tcg_temp_new();
1618 tcg_gen_shri_tl(t0
, rs
, 16);
1619 tcg_gen_xor_tl(ra
, rs
, t0
);
1620 tcg_gen_shri_tl(t0
, ra
, 8);
1621 tcg_gen_xor_tl(ra
, ra
, t0
);
1622 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1626 #if defined(TARGET_PPC64)
1627 /* prtyd: PowerPC 2.05 specification */
1628 static void gen_prtyd(DisasContext
*ctx
)
1630 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1631 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1632 TCGv t0
= tcg_temp_new();
1633 tcg_gen_shri_tl(t0
, rs
, 32);
1634 tcg_gen_xor_tl(ra
, rs
, t0
);
1635 tcg_gen_shri_tl(t0
, ra
, 16);
1636 tcg_gen_xor_tl(ra
, ra
, t0
);
1637 tcg_gen_shri_tl(t0
, ra
, 8);
1638 tcg_gen_xor_tl(ra
, ra
, t0
);
1639 tcg_gen_andi_tl(ra
, ra
, 1);
1644 #if defined(TARGET_PPC64)
1646 static void gen_bpermd(DisasContext
*ctx
)
1648 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1649 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1653 #if defined(TARGET_PPC64)
1654 /* extsw & extsw. */
1655 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1658 static void gen_cntlzd(DisasContext
*ctx
)
1660 gen_helper_cntlzd(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1661 if (unlikely(Rc(ctx
->opcode
) != 0))
1662 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1666 /*** Integer rotate ***/
1668 /* rlwimi & rlwimi. */
1669 static void gen_rlwimi(DisasContext
*ctx
)
1671 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1672 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1673 uint32_t sh
= SH(ctx
->opcode
);
1674 uint32_t mb
= MB(ctx
->opcode
);
1675 uint32_t me
= ME(ctx
->opcode
);
1677 if (sh
== (31-me
) && mb
<= me
) {
1678 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1683 #if defined(TARGET_PPC64)
1687 mask
= MASK(mb
, me
);
1689 t1
= tcg_temp_new();
1690 if (mask
<= 0xffffffffu
) {
1691 TCGv_i32 t0
= tcg_temp_new_i32();
1692 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1693 tcg_gen_rotli_i32(t0
, t0
, sh
);
1694 tcg_gen_extu_i32_tl(t1
, t0
);
1695 tcg_temp_free_i32(t0
);
1697 #if defined(TARGET_PPC64)
1698 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1699 tcg_gen_rotli_i64(t1
, t1
, sh
);
1701 g_assert_not_reached();
1705 tcg_gen_andi_tl(t1
, t1
, mask
);
1706 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1707 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1710 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1711 gen_set_Rc0(ctx
, t_ra
);
1715 /* rlwinm & rlwinm. */
1716 static void gen_rlwinm(DisasContext
*ctx
)
1718 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1719 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1720 uint32_t sh
= SH(ctx
->opcode
);
1721 uint32_t mb
= MB(ctx
->opcode
);
1722 uint32_t me
= ME(ctx
->opcode
);
1724 if (mb
== 0 && me
== (31 - sh
)) {
1725 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
1726 tcg_gen_ext32u_tl(t_ra
, t_ra
);
1727 } else if (sh
!= 0 && me
== 31 && sh
== (32 - mb
)) {
1728 tcg_gen_ext32u_tl(t_ra
, t_rs
);
1729 tcg_gen_shri_tl(t_ra
, t_ra
, mb
);
1732 #if defined(TARGET_PPC64)
1736 mask
= MASK(mb
, me
);
1738 if (mask
<= 0xffffffffu
) {
1739 TCGv_i32 t0
= tcg_temp_new_i32();
1740 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1741 tcg_gen_rotli_i32(t0
, t0
, sh
);
1742 tcg_gen_andi_i32(t0
, t0
, mask
);
1743 tcg_gen_extu_i32_tl(t_ra
, t0
);
1744 tcg_temp_free_i32(t0
);
1746 #if defined(TARGET_PPC64)
1747 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1748 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1749 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1751 g_assert_not_reached();
1755 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1756 gen_set_Rc0(ctx
, t_ra
);
1760 /* rlwnm & rlwnm. */
1761 static void gen_rlwnm(DisasContext
*ctx
)
1763 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1764 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1765 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1766 uint32_t mb
= MB(ctx
->opcode
);
1767 uint32_t me
= ME(ctx
->opcode
);
1770 #if defined(TARGET_PPC64)
1774 mask
= MASK(mb
, me
);
1776 if (mask
<= 0xffffffffu
) {
1777 TCGv_i32 t0
= tcg_temp_new_i32();
1778 TCGv_i32 t1
= tcg_temp_new_i32();
1779 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1780 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1781 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1782 tcg_gen_rotl_i32(t1
, t1
, t0
);
1783 tcg_gen_extu_i32_tl(t_ra
, t1
);
1784 tcg_temp_free_i32(t0
);
1785 tcg_temp_free_i32(t1
);
1787 #if defined(TARGET_PPC64)
1788 TCGv_i64 t0
= tcg_temp_new_i64();
1789 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
1790 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1791 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
1792 tcg_temp_free_i64(t0
);
1794 g_assert_not_reached();
1798 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
1800 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1801 gen_set_Rc0(ctx
, t_ra
);
1805 #if defined(TARGET_PPC64)
1806 #define GEN_PPC64_R2(name, opc1, opc2) \
1807 static void glue(gen_, name##0)(DisasContext *ctx) \
1809 gen_##name(ctx, 0); \
1812 static void glue(gen_, name##1)(DisasContext *ctx) \
1814 gen_##name(ctx, 1); \
1816 #define GEN_PPC64_R4(name, opc1, opc2) \
1817 static void glue(gen_, name##0)(DisasContext *ctx) \
1819 gen_##name(ctx, 0, 0); \
1822 static void glue(gen_, name##1)(DisasContext *ctx) \
1824 gen_##name(ctx, 0, 1); \
1827 static void glue(gen_, name##2)(DisasContext *ctx) \
1829 gen_##name(ctx, 1, 0); \
1832 static void glue(gen_, name##3)(DisasContext *ctx) \
1834 gen_##name(ctx, 1, 1); \
1837 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
1839 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1840 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1842 if (sh
!= 0 && mb
== 0 && me
== (63 - sh
)) {
1843 tcg_gen_shli_tl(t_ra
, t_rs
, sh
);
1844 } else if (sh
!= 0 && me
== 63 && sh
== (64 - mb
)) {
1845 tcg_gen_shri_tl(t_ra
, t_rs
, mb
);
1847 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
1848 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
1850 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1851 gen_set_Rc0(ctx
, t_ra
);
1855 /* rldicl - rldicl. */
1856 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
1860 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1861 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1862 gen_rldinm(ctx
, mb
, 63, sh
);
1864 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
1866 /* rldicr - rldicr. */
1867 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
1871 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1872 me
= MB(ctx
->opcode
) | (men
<< 5);
1873 gen_rldinm(ctx
, 0, me
, sh
);
1875 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
1877 /* rldic - rldic. */
1878 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
1882 sh
= SH(ctx
->opcode
) | (shn
<< 5);
1883 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1884 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
1886 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
1888 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
1890 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1891 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1892 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1895 t0
= tcg_temp_new();
1896 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
1897 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
1900 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
1901 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1902 gen_set_Rc0(ctx
, t_ra
);
1906 /* rldcl - rldcl. */
1907 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
1911 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1912 gen_rldnm(ctx
, mb
, 63);
1914 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
1916 /* rldcr - rldcr. */
1917 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
1921 me
= MB(ctx
->opcode
) | (men
<< 5);
1922 gen_rldnm(ctx
, 0, me
);
1924 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
1926 /* rldimi - rldimi. */
1927 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
1929 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1930 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1931 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
1932 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
1933 uint32_t me
= 63 - sh
;
1936 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1938 target_ulong mask
= MASK(mb
, me
);
1939 TCGv t1
= tcg_temp_new();
1941 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
1942 tcg_gen_andi_tl(t1
, t1
, mask
);
1943 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1944 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1947 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1948 gen_set_Rc0(ctx
, t_ra
);
1951 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
1954 /*** Integer shift ***/
1957 static void gen_slw(DisasContext
*ctx
)
1961 t0
= tcg_temp_new();
1962 /* AND rS with a mask that is 0 when rB >= 0x20 */
1963 #if defined(TARGET_PPC64)
1964 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
1965 tcg_gen_sari_tl(t0
, t0
, 0x3f);
1967 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
1968 tcg_gen_sari_tl(t0
, t0
, 0x1f);
1970 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
1971 t1
= tcg_temp_new();
1972 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
1973 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
1976 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1977 if (unlikely(Rc(ctx
->opcode
) != 0))
1978 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1982 static void gen_sraw(DisasContext
*ctx
)
1984 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
1985 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1986 if (unlikely(Rc(ctx
->opcode
) != 0))
1987 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1990 /* srawi & srawi. */
1991 static void gen_srawi(DisasContext
*ctx
)
1993 int sh
= SH(ctx
->opcode
);
1994 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
1995 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
1997 tcg_gen_ext32s_tl(dst
, src
);
1998 tcg_gen_movi_tl(cpu_ca
, 0);
2001 tcg_gen_ext32s_tl(dst
, src
);
2002 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2003 t0
= tcg_temp_new();
2004 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2005 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2007 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2008 tcg_gen_sari_tl(dst
, dst
, sh
);
2010 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2011 gen_set_Rc0(ctx
, dst
);
2016 static void gen_srw(DisasContext
*ctx
)
2020 t0
= tcg_temp_new();
2021 /* AND rS with a mask that is 0 when rB >= 0x20 */
2022 #if defined(TARGET_PPC64)
2023 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2024 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2026 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2027 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2029 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2030 tcg_gen_ext32u_tl(t0
, t0
);
2031 t1
= tcg_temp_new();
2032 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2033 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2036 if (unlikely(Rc(ctx
->opcode
) != 0))
2037 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2040 #if defined(TARGET_PPC64)
2042 static void gen_sld(DisasContext
*ctx
)
2046 t0
= tcg_temp_new();
2047 /* AND rS with a mask that is 0 when rB >= 0x40 */
2048 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2049 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2050 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2051 t1
= tcg_temp_new();
2052 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2053 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2056 if (unlikely(Rc(ctx
->opcode
) != 0))
2057 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2061 static void gen_srad(DisasContext
*ctx
)
2063 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2064 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2065 if (unlikely(Rc(ctx
->opcode
) != 0))
2066 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2068 /* sradi & sradi. */
2069 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2071 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2072 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2073 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2075 tcg_gen_mov_tl(dst
, src
);
2076 tcg_gen_movi_tl(cpu_ca
, 0);
2079 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2080 t0
= tcg_temp_new();
2081 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2082 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2084 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2085 tcg_gen_sari_tl(dst
, src
, sh
);
2087 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2088 gen_set_Rc0(ctx
, dst
);
2092 static void gen_sradi0(DisasContext
*ctx
)
2097 static void gen_sradi1(DisasContext
*ctx
)
2103 static void gen_srd(DisasContext
*ctx
)
2107 t0
= tcg_temp_new();
2108 /* AND rS with a mask that is 0 when rB >= 0x40 */
2109 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2110 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2111 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2112 t1
= tcg_temp_new();
2113 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2114 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2117 if (unlikely(Rc(ctx
->opcode
) != 0))
2118 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2122 #if defined(TARGET_PPC64)
2123 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2125 TCGv_i32 tmp
= tcg_temp_new_i32();
2126 tcg_gen_trunc_tl_i32(tmp
, cpu_fpscr
);
2127 tcg_gen_shri_i32(cpu_crf
[1], tmp
, 28);
2128 tcg_temp_free_i32(tmp
);
2131 static void gen_set_cr1_from_fpscr(DisasContext
*ctx
)
2133 tcg_gen_shri_tl(cpu_crf
[1], cpu_fpscr
, 28);
2137 /*** Floating-Point arithmetic ***/
2138 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2139 static void gen_f##name(DisasContext *ctx) \
2141 if (unlikely(!ctx->fpu_enabled)) { \
2142 gen_exception(ctx, POWERPC_EXCP_FPU); \
2145 /* NIP cannot be restored if the memory exception comes from an helper */ \
2146 gen_update_nip(ctx, ctx->nip - 4); \
2147 gen_reset_fpstatus(); \
2148 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2149 cpu_fpr[rA(ctx->opcode)], \
2150 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2152 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2153 cpu_fpr[rD(ctx->opcode)]); \
2156 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2158 if (unlikely(Rc(ctx->opcode) != 0)) { \
2159 gen_set_cr1_from_fpscr(ctx); \
2163 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2164 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2165 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2167 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2168 static void gen_f##name(DisasContext *ctx) \
2170 if (unlikely(!ctx->fpu_enabled)) { \
2171 gen_exception(ctx, POWERPC_EXCP_FPU); \
2174 /* NIP cannot be restored if the memory exception comes from an helper */ \
2175 gen_update_nip(ctx, ctx->nip - 4); \
2176 gen_reset_fpstatus(); \
2177 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2178 cpu_fpr[rA(ctx->opcode)], \
2179 cpu_fpr[rB(ctx->opcode)]); \
2181 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2182 cpu_fpr[rD(ctx->opcode)]); \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2191 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2192 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2193 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2195 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2196 static void gen_f##name(DisasContext *ctx) \
2198 if (unlikely(!ctx->fpu_enabled)) { \
2199 gen_exception(ctx, POWERPC_EXCP_FPU); \
2202 /* NIP cannot be restored if the memory exception comes from an helper */ \
2203 gen_update_nip(ctx, ctx->nip - 4); \
2204 gen_reset_fpstatus(); \
2205 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2206 cpu_fpr[rA(ctx->opcode)], \
2207 cpu_fpr[rC(ctx->opcode)]); \
2209 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2210 cpu_fpr[rD(ctx->opcode)]); \
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2215 if (unlikely(Rc(ctx->opcode) != 0)) { \
2216 gen_set_cr1_from_fpscr(ctx); \
2219 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2220 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2221 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2223 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2224 static void gen_f##name(DisasContext *ctx) \
2226 if (unlikely(!ctx->fpu_enabled)) { \
2227 gen_exception(ctx, POWERPC_EXCP_FPU); \
2230 /* NIP cannot be restored if the memory exception comes from an helper */ \
2231 gen_update_nip(ctx, ctx->nip - 4); \
2232 gen_reset_fpstatus(); \
2233 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2234 cpu_fpr[rB(ctx->opcode)]); \
2236 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2238 if (unlikely(Rc(ctx->opcode) != 0)) { \
2239 gen_set_cr1_from_fpscr(ctx); \
2243 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2244 static void gen_f##name(DisasContext *ctx) \
2246 if (unlikely(!ctx->fpu_enabled)) { \
2247 gen_exception(ctx, POWERPC_EXCP_FPU); \
2250 /* NIP cannot be restored if the memory exception comes from an helper */ \
2251 gen_update_nip(ctx, ctx->nip - 4); \
2252 gen_reset_fpstatus(); \
2253 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2254 cpu_fpr[rB(ctx->opcode)]); \
2256 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2258 if (unlikely(Rc(ctx->opcode) != 0)) { \
2259 gen_set_cr1_from_fpscr(ctx); \
2264 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
);
2266 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
);
2268 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
);
2271 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
);
2274 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
);
2277 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
);
2280 static void gen_frsqrtes(DisasContext
*ctx
)
2282 if (unlikely(!ctx
->fpu_enabled
)) {
2283 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2286 /* NIP cannot be restored if the memory exception comes from an helper */
2287 gen_update_nip(ctx
, ctx
->nip
- 4);
2288 gen_reset_fpstatus();
2289 gen_helper_frsqrte(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2290 cpu_fpr
[rB(ctx
->opcode
)]);
2291 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2292 cpu_fpr
[rD(ctx
->opcode
)]);
2293 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2294 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2295 gen_set_cr1_from_fpscr(ctx
);
2300 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
);
2302 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
);
2306 static void gen_fsqrt(DisasContext
*ctx
)
2308 if (unlikely(!ctx
->fpu_enabled
)) {
2309 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2312 /* NIP cannot be restored if the memory exception comes from an helper */
2313 gen_update_nip(ctx
, ctx
->nip
- 4);
2314 gen_reset_fpstatus();
2315 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2316 cpu_fpr
[rB(ctx
->opcode
)]);
2317 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2318 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2319 gen_set_cr1_from_fpscr(ctx
);
2323 static void gen_fsqrts(DisasContext
*ctx
)
2325 if (unlikely(!ctx
->fpu_enabled
)) {
2326 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2329 /* NIP cannot be restored if the memory exception comes from an helper */
2330 gen_update_nip(ctx
, ctx
->nip
- 4);
2331 gen_reset_fpstatus();
2332 gen_helper_fsqrt(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2333 cpu_fpr
[rB(ctx
->opcode
)]);
2334 gen_helper_frsp(cpu_fpr
[rD(ctx
->opcode
)], cpu_env
,
2335 cpu_fpr
[rD(ctx
->opcode
)]);
2336 gen_compute_fprf(cpu_fpr
[rD(ctx
->opcode
)]);
2337 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2338 gen_set_cr1_from_fpscr(ctx
);
2342 /*** Floating-Point multiply-and-add ***/
2343 /* fmadd - fmadds */
2344 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
);
2345 /* fmsub - fmsubs */
2346 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
);
2347 /* fnmadd - fnmadds */
2348 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
);
2349 /* fnmsub - fnmsubs */
2350 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
);
2352 /*** Floating-Point round & convert ***/
2354 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
);
2356 GEN_FLOAT_B(ctiwu
, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206
);
2358 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
);
2360 GEN_FLOAT_B(ctiwuz
, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206
);
2362 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
);
2364 GEN_FLOAT_B(cfid
, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64
);
2366 GEN_FLOAT_B(cfids
, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206
);
2368 GEN_FLOAT_B(cfidu
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2370 GEN_FLOAT_B(cfidus
, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206
);
2372 GEN_FLOAT_B(ctid
, 0x0E, 0x19, 0, PPC2_FP_CVT_S64
);
2374 GEN_FLOAT_B(ctidu
, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2376 GEN_FLOAT_B(ctidz
, 0x0F, 0x19, 0, PPC2_FP_CVT_S64
);
2378 GEN_FLOAT_B(ctiduz
, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206
);
2381 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
);
2383 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
);
2385 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
);
2387 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
);
2389 static void gen_ftdiv(DisasContext
*ctx
)
2391 if (unlikely(!ctx
->fpu_enabled
)) {
2392 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2395 gen_helper_ftdiv(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2396 cpu_fpr
[rB(ctx
->opcode
)]);
2399 static void gen_ftsqrt(DisasContext
*ctx
)
2401 if (unlikely(!ctx
->fpu_enabled
)) {
2402 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2405 gen_helper_ftsqrt(cpu_crf
[crfD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2410 /*** Floating-Point compare ***/
2413 static void gen_fcmpo(DisasContext
*ctx
)
2416 if (unlikely(!ctx
->fpu_enabled
)) {
2417 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2420 /* NIP cannot be restored if the memory exception comes from an helper */
2421 gen_update_nip(ctx
, ctx
->nip
- 4);
2422 gen_reset_fpstatus();
2423 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2424 gen_helper_fcmpo(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2425 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2426 tcg_temp_free_i32(crf
);
2427 gen_helper_float_check_status(cpu_env
);
2431 static void gen_fcmpu(DisasContext
*ctx
)
2434 if (unlikely(!ctx
->fpu_enabled
)) {
2435 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2438 /* NIP cannot be restored if the memory exception comes from an helper */
2439 gen_update_nip(ctx
, ctx
->nip
- 4);
2440 gen_reset_fpstatus();
2441 crf
= tcg_const_i32(crfD(ctx
->opcode
));
2442 gen_helper_fcmpu(cpu_env
, cpu_fpr
[rA(ctx
->opcode
)],
2443 cpu_fpr
[rB(ctx
->opcode
)], crf
);
2444 tcg_temp_free_i32(crf
);
2445 gen_helper_float_check_status(cpu_env
);
2448 /*** Floating-point move ***/
2450 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2451 static void gen_fabs(DisasContext
*ctx
)
2453 if (unlikely(!ctx
->fpu_enabled
)) {
2454 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2457 tcg_gen_andi_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2459 if (unlikely(Rc(ctx
->opcode
))) {
2460 gen_set_cr1_from_fpscr(ctx
);
2465 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2466 static void gen_fmr(DisasContext
*ctx
)
2468 if (unlikely(!ctx
->fpu_enabled
)) {
2469 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2472 tcg_gen_mov_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)]);
2473 if (unlikely(Rc(ctx
->opcode
))) {
2474 gen_set_cr1_from_fpscr(ctx
);
2479 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2480 static void gen_fnabs(DisasContext
*ctx
)
2482 if (unlikely(!ctx
->fpu_enabled
)) {
2483 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2486 tcg_gen_ori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2488 if (unlikely(Rc(ctx
->opcode
))) {
2489 gen_set_cr1_from_fpscr(ctx
);
2494 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2495 static void gen_fneg(DisasContext
*ctx
)
2497 if (unlikely(!ctx
->fpu_enabled
)) {
2498 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2501 tcg_gen_xori_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rB(ctx
->opcode
)],
2503 if (unlikely(Rc(ctx
->opcode
))) {
2504 gen_set_cr1_from_fpscr(ctx
);
2508 /* fcpsgn: PowerPC 2.05 specification */
2509 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2510 static void gen_fcpsgn(DisasContext
*ctx
)
2512 if (unlikely(!ctx
->fpu_enabled
)) {
2513 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2516 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2517 cpu_fpr
[rB(ctx
->opcode
)], 0, 63);
2518 if (unlikely(Rc(ctx
->opcode
))) {
2519 gen_set_cr1_from_fpscr(ctx
);
2523 static void gen_fmrgew(DisasContext
*ctx
)
2526 if (unlikely(!ctx
->fpu_enabled
)) {
2527 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2530 b0
= tcg_temp_new_i64();
2531 tcg_gen_shri_i64(b0
, cpu_fpr
[rB(ctx
->opcode
)], 32);
2532 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpr
[rA(ctx
->opcode
)],
2534 tcg_temp_free_i64(b0
);
2537 static void gen_fmrgow(DisasContext
*ctx
)
2539 if (unlikely(!ctx
->fpu_enabled
)) {
2540 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2543 tcg_gen_deposit_i64(cpu_fpr
[rD(ctx
->opcode
)],
2544 cpu_fpr
[rB(ctx
->opcode
)],
2545 cpu_fpr
[rA(ctx
->opcode
)],
2549 /*** Floating-Point status & ctrl register ***/
2552 static void gen_mcrfs(DisasContext
*ctx
)
2554 TCGv tmp
= tcg_temp_new();
2556 TCGv_i64 tnew_fpscr
= tcg_temp_new_i64();
2561 if (unlikely(!ctx
->fpu_enabled
)) {
2562 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2565 bfa
= crfS(ctx
->opcode
);
2568 tcg_gen_shri_tl(tmp
, cpu_fpscr
, shift
);
2569 tcg_gen_trunc_tl_i32(cpu_crf
[crfD(ctx
->opcode
)], tmp
);
2570 tcg_gen_andi_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfD(ctx
->opcode
)], 0xf);
2572 tcg_gen_extu_tl_i64(tnew_fpscr
, cpu_fpscr
);
2573 /* Only the exception bits (including FX) should be cleared if read */
2574 tcg_gen_andi_i64(tnew_fpscr
, tnew_fpscr
, ~((0xF << shift
) & FP_EX_CLEAR_BITS
));
2575 /* FEX and VX need to be updated, so don't set fpscr directly */
2576 tmask
= tcg_const_i32(1 << nibble
);
2577 gen_helper_store_fpscr(cpu_env
, tnew_fpscr
, tmask
);
2578 tcg_temp_free_i32(tmask
);
2579 tcg_temp_free_i64(tnew_fpscr
);
2583 static void gen_mffs(DisasContext
*ctx
)
2585 if (unlikely(!ctx
->fpu_enabled
)) {
2586 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2589 gen_reset_fpstatus();
2590 tcg_gen_extu_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], cpu_fpscr
);
2591 if (unlikely(Rc(ctx
->opcode
))) {
2592 gen_set_cr1_from_fpscr(ctx
);
2597 static void gen_mtfsb0(DisasContext
*ctx
)
2601 if (unlikely(!ctx
->fpu_enabled
)) {
2602 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2605 crb
= 31 - crbD(ctx
->opcode
);
2606 gen_reset_fpstatus();
2607 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
)) {
2609 /* NIP cannot be restored if the memory exception comes from an helper */
2610 gen_update_nip(ctx
, ctx
->nip
- 4);
2611 t0
= tcg_const_i32(crb
);
2612 gen_helper_fpscr_clrbit(cpu_env
, t0
);
2613 tcg_temp_free_i32(t0
);
2615 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2616 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2617 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2622 static void gen_mtfsb1(DisasContext
*ctx
)
2626 if (unlikely(!ctx
->fpu_enabled
)) {
2627 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2630 crb
= 31 - crbD(ctx
->opcode
);
2631 gen_reset_fpstatus();
2632 /* XXX: we pretend we can only do IEEE floating-point computations */
2633 if (likely(crb
!= FPSCR_FEX
&& crb
!= FPSCR_VX
&& crb
!= FPSCR_NI
)) {
2635 /* NIP cannot be restored if the memory exception comes from an helper */
2636 gen_update_nip(ctx
, ctx
->nip
- 4);
2637 t0
= tcg_const_i32(crb
);
2638 gen_helper_fpscr_setbit(cpu_env
, t0
);
2639 tcg_temp_free_i32(t0
);
2641 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2642 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2643 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2645 /* We can raise a differed exception */
2646 gen_helper_float_check_status(cpu_env
);
2650 static void gen_mtfsf(DisasContext
*ctx
)
2655 if (unlikely(!ctx
->fpu_enabled
)) {
2656 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2659 flm
= FPFLM(ctx
->opcode
);
2660 l
= FPL(ctx
->opcode
);
2661 w
= FPW(ctx
->opcode
);
2662 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2663 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2666 /* NIP cannot be restored if the memory exception comes from an helper */
2667 gen_update_nip(ctx
, ctx
->nip
- 4);
2668 gen_reset_fpstatus();
2670 t0
= tcg_const_i32((ctx
->insns_flags2
& PPC2_ISA205
) ? 0xffff : 0xff);
2672 t0
= tcg_const_i32(flm
<< (w
* 8));
2674 gen_helper_store_fpscr(cpu_env
, cpu_fpr
[rB(ctx
->opcode
)], t0
);
2675 tcg_temp_free_i32(t0
);
2676 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2677 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2678 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2680 /* We can raise a differed exception */
2681 gen_helper_float_check_status(cpu_env
);
2685 static void gen_mtfsfi(DisasContext
*ctx
)
2691 if (unlikely(!ctx
->fpu_enabled
)) {
2692 gen_exception(ctx
, POWERPC_EXCP_FPU
);
2695 w
= FPW(ctx
->opcode
);
2696 bf
= FPBF(ctx
->opcode
);
2697 if (unlikely(w
& !(ctx
->insns_flags2
& PPC2_ISA205
))) {
2698 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2701 sh
= (8 * w
) + 7 - bf
;
2702 /* NIP cannot be restored if the memory exception comes from an helper */
2703 gen_update_nip(ctx
, ctx
->nip
- 4);
2704 gen_reset_fpstatus();
2705 t0
= tcg_const_i64(((uint64_t)FPIMM(ctx
->opcode
)) << (4 * sh
));
2706 t1
= tcg_const_i32(1 << sh
);
2707 gen_helper_store_fpscr(cpu_env
, t0
, t1
);
2708 tcg_temp_free_i64(t0
);
2709 tcg_temp_free_i32(t1
);
2710 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2711 tcg_gen_trunc_tl_i32(cpu_crf
[1], cpu_fpscr
);
2712 tcg_gen_shri_i32(cpu_crf
[1], cpu_crf
[1], FPSCR_OX
);
2714 /* We can raise a differed exception */
2715 gen_helper_float_check_status(cpu_env
);
2718 /*** Addressing modes ***/
2719 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2720 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2723 target_long simm
= SIMM(ctx
->opcode
);
2726 if (rA(ctx
->opcode
) == 0) {
2727 if (NARROW_MODE(ctx
)) {
2728 simm
= (uint32_t)simm
;
2730 tcg_gen_movi_tl(EA
, simm
);
2731 } else if (likely(simm
!= 0)) {
2732 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2733 if (NARROW_MODE(ctx
)) {
2734 tcg_gen_ext32u_tl(EA
, EA
);
2737 if (NARROW_MODE(ctx
)) {
2738 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2740 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2745 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2747 if (rA(ctx
->opcode
) == 0) {
2748 if (NARROW_MODE(ctx
)) {
2749 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2751 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2754 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2755 if (NARROW_MODE(ctx
)) {
2756 tcg_gen_ext32u_tl(EA
, EA
);
2761 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2763 if (rA(ctx
->opcode
) == 0) {
2764 tcg_gen_movi_tl(EA
, 0);
2765 } else if (NARROW_MODE(ctx
)) {
2766 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2768 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2772 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2775 tcg_gen_addi_tl(ret
, arg1
, val
);
2776 if (NARROW_MODE(ctx
)) {
2777 tcg_gen_ext32u_tl(ret
, ret
);
2781 static inline void gen_check_align(DisasContext
*ctx
, TCGv EA
, int mask
)
2783 TCGLabel
*l1
= gen_new_label();
2784 TCGv t0
= tcg_temp_new();
2786 /* NIP cannot be restored if the memory exception comes from an helper */
2787 gen_update_nip(ctx
, ctx
->nip
- 4);
2788 tcg_gen_andi_tl(t0
, EA
, mask
);
2789 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
2790 t1
= tcg_const_i32(POWERPC_EXCP_ALIGN
);
2791 t2
= tcg_const_i32(0);
2792 gen_helper_raise_exception_err(cpu_env
, t1
, t2
);
2793 tcg_temp_free_i32(t1
);
2794 tcg_temp_free_i32(t2
);
2799 /*** Integer load ***/
2800 static inline void gen_qemu_ld8u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2802 tcg_gen_qemu_ld8u(arg1
, arg2
, ctx
->mem_idx
);
2805 static inline void gen_qemu_ld16u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2807 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2808 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2811 static inline void gen_qemu_ld16s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2813 TCGMemOp op
= MO_SW
| ctx
->default_tcg_memop_mask
;
2814 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2817 static inline void gen_qemu_ld32u(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2819 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2820 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2823 static void gen_qemu_ld32u_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2825 TCGv tmp
= tcg_temp_new();
2826 gen_qemu_ld32u(ctx
, tmp
, addr
);
2827 tcg_gen_extu_tl_i64(val
, tmp
);
2831 static inline void gen_qemu_ld32s(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2833 TCGMemOp op
= MO_SL
| ctx
->default_tcg_memop_mask
;
2834 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2837 static void gen_qemu_ld32s_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2839 TCGv tmp
= tcg_temp_new();
2840 gen_qemu_ld32s(ctx
, tmp
, addr
);
2841 tcg_gen_ext_tl_i64(val
, tmp
);
2845 static inline void gen_qemu_ld64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2847 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2848 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2851 static inline void gen_qemu_st8(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2853 tcg_gen_qemu_st8(arg1
, arg2
, ctx
->mem_idx
);
2856 static inline void gen_qemu_st16(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2858 TCGMemOp op
= MO_UW
| ctx
->default_tcg_memop_mask
;
2859 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2862 static inline void gen_qemu_st32(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
2864 TCGMemOp op
= MO_UL
| ctx
->default_tcg_memop_mask
;
2865 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
2868 static void gen_qemu_st32_i64(DisasContext
*ctx
, TCGv_i64 val
, TCGv addr
)
2870 TCGv tmp
= tcg_temp_new();
2871 tcg_gen_trunc_i64_tl(tmp
, val
);
2872 gen_qemu_st32(ctx
, tmp
, addr
);
2876 static inline void gen_qemu_st64(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
2878 TCGMemOp op
= MO_Q
| ctx
->default_tcg_memop_mask
;
2879 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
2882 #define GEN_LD(name, ldop, opc, type) \
2883 static void glue(gen_, name)(DisasContext *ctx) \
2886 gen_set_access_type(ctx, ACCESS_INT); \
2887 EA = tcg_temp_new(); \
2888 gen_addr_imm_index(ctx, EA, 0); \
2889 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2890 tcg_temp_free(EA); \
2893 #define GEN_LDU(name, ldop, opc, type) \
2894 static void glue(gen_, name##u)(DisasContext *ctx) \
2897 if (unlikely(rA(ctx->opcode) == 0 || \
2898 rA(ctx->opcode) == rD(ctx->opcode))) { \
2899 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2902 gen_set_access_type(ctx, ACCESS_INT); \
2903 EA = tcg_temp_new(); \
2904 if (type == PPC_64B) \
2905 gen_addr_imm_index(ctx, EA, 0x03); \
2907 gen_addr_imm_index(ctx, EA, 0); \
2908 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2909 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2910 tcg_temp_free(EA); \
2913 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2914 static void glue(gen_, name##ux)(DisasContext *ctx) \
2917 if (unlikely(rA(ctx->opcode) == 0 || \
2918 rA(ctx->opcode) == rD(ctx->opcode))) { \
2919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2922 gen_set_access_type(ctx, ACCESS_INT); \
2923 EA = tcg_temp_new(); \
2924 gen_addr_reg_index(ctx, EA); \
2925 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2926 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2927 tcg_temp_free(EA); \
2930 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2931 static void glue(gen_, name##x)(DisasContext *ctx) \
2934 gen_set_access_type(ctx, ACCESS_INT); \
2935 EA = tcg_temp_new(); \
2936 gen_addr_reg_index(ctx, EA); \
2937 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2938 tcg_temp_free(EA); \
2940 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2941 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2943 #define GEN_LDS(name, ldop, op, type) \
2944 GEN_LD(name, ldop, op | 0x20, type); \
2945 GEN_LDU(name, ldop, op | 0x21, type); \
2946 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2947 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2949 /* lbz lbzu lbzux lbzx */
2950 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2951 /* lha lhau lhaux lhax */
2952 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2953 /* lhz lhzu lhzux lhzx */
2954 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2955 /* lwz lwzu lwzux lwzx */
2956 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2957 #if defined(TARGET_PPC64)
2959 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2961 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2963 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
);
2965 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
);
2967 static void gen_ld(DisasContext
*ctx
)
2970 if (Rc(ctx
->opcode
)) {
2971 if (unlikely(rA(ctx
->opcode
) == 0 ||
2972 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2973 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2977 gen_set_access_type(ctx
, ACCESS_INT
);
2978 EA
= tcg_temp_new();
2979 gen_addr_imm_index(ctx
, EA
, 0x03);
2980 if (ctx
->opcode
& 0x02) {
2981 /* lwa (lwau is undefined) */
2982 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2985 gen_qemu_ld64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2987 if (Rc(ctx
->opcode
))
2988 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2993 static void gen_lq(DisasContext
*ctx
)
2998 /* lq is a legal user mode instruction starting in ISA 2.07 */
2999 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3000 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3002 if (!legal_in_user_mode
&& ctx
->pr
) {
3003 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3007 if (!le_is_supported
&& ctx
->le_mode
) {
3008 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
3012 ra
= rA(ctx
->opcode
);
3013 rd
= rD(ctx
->opcode
);
3014 if (unlikely((rd
& 1) || rd
== ra
)) {
3015 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3019 gen_set_access_type(ctx
, ACCESS_INT
);
3020 EA
= tcg_temp_new();
3021 gen_addr_imm_index(ctx
, EA
, 0x0F);
3023 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3024 64-bit byteswap already. */
3025 if (unlikely(ctx
->le_mode
)) {
3026 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
3027 gen_addr_add(ctx
, EA
, EA
, 8);
3028 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
3030 gen_qemu_ld64(ctx
, cpu_gpr
[rd
], EA
);
3031 gen_addr_add(ctx
, EA
, EA
, 8);
3032 gen_qemu_ld64(ctx
, cpu_gpr
[rd
+1], EA
);
3038 /*** Integer store ***/
3039 #define GEN_ST(name, stop, opc, type) \
3040 static void glue(gen_, name)(DisasContext *ctx) \
3043 gen_set_access_type(ctx, ACCESS_INT); \
3044 EA = tcg_temp_new(); \
3045 gen_addr_imm_index(ctx, EA, 0); \
3046 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3047 tcg_temp_free(EA); \
3050 #define GEN_STU(name, stop, opc, type) \
3051 static void glue(gen_, stop##u)(DisasContext *ctx) \
3054 if (unlikely(rA(ctx->opcode) == 0)) { \
3055 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3058 gen_set_access_type(ctx, ACCESS_INT); \
3059 EA = tcg_temp_new(); \
3060 if (type == PPC_64B) \
3061 gen_addr_imm_index(ctx, EA, 0x03); \
3063 gen_addr_imm_index(ctx, EA, 0); \
3064 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3065 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3066 tcg_temp_free(EA); \
3069 #define GEN_STUX(name, stop, opc2, opc3, type) \
3070 static void glue(gen_, name##ux)(DisasContext *ctx) \
3073 if (unlikely(rA(ctx->opcode) == 0)) { \
3074 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3077 gen_set_access_type(ctx, ACCESS_INT); \
3078 EA = tcg_temp_new(); \
3079 gen_addr_reg_index(ctx, EA); \
3080 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3081 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3082 tcg_temp_free(EA); \
3085 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3086 static void glue(gen_, name##x)(DisasContext *ctx) \
3089 gen_set_access_type(ctx, ACCESS_INT); \
3090 EA = tcg_temp_new(); \
3091 gen_addr_reg_index(ctx, EA); \
3092 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3093 tcg_temp_free(EA); \
3095 #define GEN_STX(name, stop, opc2, opc3, type) \
3096 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3098 #define GEN_STS(name, stop, op, type) \
3099 GEN_ST(name, stop, op | 0x20, type); \
3100 GEN_STU(name, stop, op | 0x21, type); \
3101 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3102 GEN_STX(name, stop, 0x17, op | 0x00, type)
3104 /* stb stbu stbux stbx */
3105 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
3106 /* sth sthu sthux sthx */
3107 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
3108 /* stw stwu stwux stwx */
3109 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
3110 #if defined(TARGET_PPC64)
3111 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
);
3112 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
);
3114 static void gen_std(DisasContext
*ctx
)
3119 rs
= rS(ctx
->opcode
);
3120 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
3121 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3122 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
3124 if (!(ctx
->insns_flags
& PPC_64BX
)) {
3125 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3128 if (!legal_in_user_mode
&& ctx
->pr
) {
3129 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
3133 if (!le_is_supported
&& ctx
->le_mode
) {
3134 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
, POWERPC_EXCP_ALIGN_LE
);
3138 if (unlikely(rs
& 1)) {
3139 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3142 gen_set_access_type(ctx
, ACCESS_INT
);
3143 EA
= tcg_temp_new();
3144 gen_addr_imm_index(ctx
, EA
, 0x03);
3146 /* We only need to swap high and low halves. gen_qemu_st64 does
3147 necessary 64-bit byteswap already. */
3148 if (unlikely(ctx
->le_mode
)) {
3149 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3150 gen_addr_add(ctx
, EA
, EA
, 8);
3151 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3153 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3154 gen_addr_add(ctx
, EA
, EA
, 8);
3155 gen_qemu_st64(ctx
, cpu_gpr
[rs
+1], EA
);
3160 if (Rc(ctx
->opcode
)) {
3161 if (unlikely(rA(ctx
->opcode
) == 0)) {
3162 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3166 gen_set_access_type(ctx
, ACCESS_INT
);
3167 EA
= tcg_temp_new();
3168 gen_addr_imm_index(ctx
, EA
, 0x03);
3169 gen_qemu_st64(ctx
, cpu_gpr
[rs
], EA
);
3170 if (Rc(ctx
->opcode
))
3171 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
3176 /*** Integer load and store with byte reverse ***/
3179 static inline void gen_qemu_ld16ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3181 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3182 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3184 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
3187 static inline void gen_qemu_ld32ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3189 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3190 tcg_gen_qemu_ld_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3192 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
3194 #if defined(TARGET_PPC64)
3196 static inline void gen_qemu_ld64ur(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3198 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3199 tcg_gen_qemu_ld_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3201 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
);
3202 #endif /* TARGET_PPC64 */
3205 static inline void gen_qemu_st16r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3207 TCGMemOp op
= MO_UW
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3208 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3210 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
3213 static inline void gen_qemu_st32r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3215 TCGMemOp op
= MO_UL
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3216 tcg_gen_qemu_st_tl(arg1
, arg2
, ctx
->mem_idx
, op
);
3218 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
3220 #if defined(TARGET_PPC64)
3222 static inline void gen_qemu_st64r(DisasContext
*ctx
, TCGv arg1
, TCGv arg2
)
3224 TCGMemOp op
= MO_Q
| (ctx
->default_tcg_memop_mask
^ MO_BSWAP
);
3225 tcg_gen_qemu_st_i64(arg1
, arg2
, ctx
->mem_idx
, op
);
3227 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
);
3228 #endif /* TARGET_PPC64 */
3230 /*** Integer load and store multiple ***/
3233 static void gen_lmw(DisasContext
*ctx
)
3237 gen_set_access_type(ctx
, ACCESS_INT
);
3238 /* NIP cannot be restored if the memory exception comes from an helper */
3239 gen_update_nip(ctx
, ctx
->nip
- 4);
3240 t0
= tcg_temp_new();
3241 t1
= tcg_const_i32(rD(ctx
->opcode
));
3242 gen_addr_imm_index(ctx
, t0
, 0);
3243 gen_helper_lmw(cpu_env
, t0
, t1
);
3245 tcg_temp_free_i32(t1
);
3249 static void gen_stmw(DisasContext
*ctx
)
3253 gen_set_access_type(ctx
, ACCESS_INT
);
3254 /* NIP cannot be restored if the memory exception comes from an helper */
3255 gen_update_nip(ctx
, ctx
->nip
- 4);
3256 t0
= tcg_temp_new();
3257 t1
= tcg_const_i32(rS(ctx
->opcode
));
3258 gen_addr_imm_index(ctx
, t0
, 0);
3259 gen_helper_stmw(cpu_env
, t0
, t1
);
3261 tcg_temp_free_i32(t1
);
3264 /*** Integer load and store strings ***/
3267 /* PowerPC32 specification says we must generate an exception if
3268 * rA is in the range of registers to be loaded.
3269 * In an other hand, IBM says this is valid, but rA won't be loaded.
3270 * For now, I'll follow the spec...
3272 static void gen_lswi(DisasContext
*ctx
)
3276 int nb
= NB(ctx
->opcode
);
3277 int start
= rD(ctx
->opcode
);
3278 int ra
= rA(ctx
->opcode
);
3284 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
3285 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
3288 gen_set_access_type(ctx
, ACCESS_INT
);
3289 /* NIP cannot be restored if the memory exception comes from an helper */
3290 gen_update_nip(ctx
, ctx
->nip
- 4);
3291 t0
= tcg_temp_new();
3292 gen_addr_register(ctx
, t0
);
3293 t1
= tcg_const_i32(nb
);
3294 t2
= tcg_const_i32(start
);
3295 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
3297 tcg_temp_free_i32(t1
);
3298 tcg_temp_free_i32(t2
);
3302 static void gen_lswx(DisasContext
*ctx
)
3305 TCGv_i32 t1
, t2
, t3
;
3306 gen_set_access_type(ctx
, ACCESS_INT
);
3307 /* NIP cannot be restored if the memory exception comes from an helper */
3308 gen_update_nip(ctx
, ctx
->nip
- 4);
3309 t0
= tcg_temp_new();
3310 gen_addr_reg_index(ctx
, t0
);
3311 t1
= tcg_const_i32(rD(ctx
->opcode
));
3312 t2
= tcg_const_i32(rA(ctx
->opcode
));
3313 t3
= tcg_const_i32(rB(ctx
->opcode
));
3314 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3316 tcg_temp_free_i32(t1
);
3317 tcg_temp_free_i32(t2
);
3318 tcg_temp_free_i32(t3
);
3322 static void gen_stswi(DisasContext
*ctx
)
3326 int nb
= NB(ctx
->opcode
);
3327 gen_set_access_type(ctx
, ACCESS_INT
);
3328 /* NIP cannot be restored if the memory exception comes from an helper */
3329 gen_update_nip(ctx
, ctx
->nip
- 4);
3330 t0
= tcg_temp_new();
3331 gen_addr_register(ctx
, t0
);
3334 t1
= tcg_const_i32(nb
);
3335 t2
= tcg_const_i32(rS(ctx
->opcode
));
3336 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3338 tcg_temp_free_i32(t1
);
3339 tcg_temp_free_i32(t2
);
3343 static void gen_stswx(DisasContext
*ctx
)
3347 gen_set_access_type(ctx
, ACCESS_INT
);
3348 /* NIP cannot be restored if the memory exception comes from an helper */
3349 gen_update_nip(ctx
, ctx
->nip
- 4);
3350 t0
= tcg_temp_new();
3351 gen_addr_reg_index(ctx
, t0
);
3352 t1
= tcg_temp_new_i32();
3353 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3354 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3355 t2
= tcg_const_i32(rS(ctx
->opcode
));
3356 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3358 tcg_temp_free_i32(t1
);
3359 tcg_temp_free_i32(t2
);
3362 /*** Memory synchronisation ***/
3364 static void gen_eieio(DisasContext
*ctx
)
3368 #if !defined(CONFIG_USER_ONLY)
3369 static inline void gen_check_tlb_flush(DisasContext
*ctx
)
3374 if (!ctx
->lazy_tlb_flush
) {
3377 l
= gen_new_label();
3378 t
= tcg_temp_new_i32();
3379 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3380 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3381 gen_helper_check_tlb_flush(cpu_env
);
3383 tcg_temp_free_i32(t
);
3386 static inline void gen_check_tlb_flush(DisasContext
*ctx
) { }
3390 static void gen_isync(DisasContext
*ctx
)
3393 * We need to check for a pending TLB flush. This can only happen in
3394 * kernel mode however so check MSR_PR
3397 gen_check_tlb_flush(ctx
);
3399 gen_stop_exception(ctx
);
3402 #define LARX(name, len, loadop) \
3403 static void gen_##name(DisasContext *ctx) \
3406 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3407 gen_set_access_type(ctx, ACCESS_RES); \
3408 t0 = tcg_temp_local_new(); \
3409 gen_addr_reg_index(ctx, t0); \
3411 gen_check_align(ctx, t0, (len)-1); \
3413 gen_qemu_##loadop(ctx, gpr, t0); \
3414 tcg_gen_mov_tl(cpu_reserve, t0); \
3415 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3416 tcg_temp_free(t0); \
3420 LARX(lbarx
, 1, ld8u
);
3421 LARX(lharx
, 2, ld16u
);
3422 LARX(lwarx
, 4, ld32u
);
3425 #if defined(CONFIG_USER_ONLY)
3426 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3429 TCGv t0
= tcg_temp_new();
3430 uint32_t save_exception
= ctx
->exception
;
3432 tcg_gen_st_tl(EA
, cpu_env
, offsetof(CPUPPCState
, reserve_ea
));
3433 tcg_gen_movi_tl(t0
, (size
<< 5) | reg
);
3434 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUPPCState
, reserve_info
));
3436 gen_update_nip(ctx
, ctx
->nip
-4);
3437 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3438 gen_exception(ctx
, POWERPC_EXCP_STCX
);
3439 ctx
->exception
= save_exception
;
3442 static void gen_conditional_store(DisasContext
*ctx
, TCGv EA
,
3447 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3448 l1
= gen_new_label();
3449 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, l1
);
3450 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
3451 #if defined(TARGET_PPC64)
3453 gen_qemu_st64(ctx
, cpu_gpr
[reg
], EA
);
3457 gen_qemu_st32(ctx
, cpu_gpr
[reg
], EA
);
3458 } else if (size
== 2) {
3459 gen_qemu_st16(ctx
, cpu_gpr
[reg
], EA
);
3460 #if defined(TARGET_PPC64)
3461 } else if (size
== 16) {
3462 TCGv gpr1
, gpr2
, EA8
;
3463 if (unlikely(ctx
->le_mode
)) {
3464 gpr1
= cpu_gpr
[reg
+1];
3465 gpr2
= cpu_gpr
[reg
];
3467 gpr1
= cpu_gpr
[reg
];
3468 gpr2
= cpu_gpr
[reg
+1];
3470 gen_qemu_st64(ctx
, gpr1
, EA
);
3471 EA8
= tcg_temp_local_new();
3472 gen_addr_add(ctx
, EA8
, EA
, 8);
3473 gen_qemu_st64(ctx
, gpr2
, EA8
);
3477 gen_qemu_st8(ctx
, cpu_gpr
[reg
], EA
);
3480 tcg_gen_movi_tl(cpu_reserve
, -1);
3484 #define STCX(name, len) \
3485 static void gen_##name(DisasContext *ctx) \
3488 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3489 gen_inval_exception(ctx, \
3490 POWERPC_EXCP_INVAL_INVAL); \
3493 gen_set_access_type(ctx, ACCESS_RES); \
3494 t0 = tcg_temp_local_new(); \
3495 gen_addr_reg_index(ctx, t0); \
3497 gen_check_align(ctx, t0, (len)-1); \
3499 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3500 tcg_temp_free(t0); \
3507 #if defined(TARGET_PPC64)
3509 LARX(ldarx
, 8, ld64
);
3512 static void gen_lqarx(DisasContext
*ctx
)
3515 int rd
= rD(ctx
->opcode
);
3518 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3519 (rd
== rB(ctx
->opcode
)))) {
3520 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3524 gen_set_access_type(ctx
, ACCESS_RES
);
3525 EA
= tcg_temp_local_new();
3526 gen_addr_reg_index(ctx
, EA
);
3527 gen_check_align(ctx
, EA
, 15);
3528 if (unlikely(ctx
->le_mode
)) {
3529 gpr1
= cpu_gpr
[rd
+1];
3533 gpr2
= cpu_gpr
[rd
+1];
3535 gen_qemu_ld64(ctx
, gpr1
, EA
);
3536 tcg_gen_mov_tl(cpu_reserve
, EA
);
3538 gen_addr_add(ctx
, EA
, EA
, 8);
3539 gen_qemu_ld64(ctx
, gpr2
, EA
);
3541 tcg_gen_st_tl(gpr1
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3542 tcg_gen_st_tl(gpr2
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3550 #endif /* defined(TARGET_PPC64) */
3553 static void gen_sync(DisasContext
*ctx
)
3555 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3558 * We may need to check for a pending TLB flush.
3560 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3562 * Additionally, this can only happen in kernel mode however so
3563 * check MSR_PR as well.
3565 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3566 gen_check_tlb_flush(ctx
);
3571 static void gen_wait(DisasContext
*ctx
)
3573 TCGv_i32 t0
= tcg_const_i32(1);
3574 tcg_gen_st_i32(t0
, cpu_env
,
3575 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3576 tcg_temp_free_i32(t0
);
3577 /* Stop translation, as the CPU is supposed to sleep from now */
3578 gen_exception_err(ctx
, EXCP_HLT
, 1);
3581 /*** Floating-point load ***/
3582 #define GEN_LDF(name, ldop, opc, type) \
3583 static void glue(gen_, name)(DisasContext *ctx) \
3586 if (unlikely(!ctx->fpu_enabled)) { \
3587 gen_exception(ctx, POWERPC_EXCP_FPU); \
3590 gen_set_access_type(ctx, ACCESS_FLOAT); \
3591 EA = tcg_temp_new(); \
3592 gen_addr_imm_index(ctx, EA, 0); \
3593 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3594 tcg_temp_free(EA); \
3597 #define GEN_LDUF(name, ldop, opc, type) \
3598 static void glue(gen_, name##u)(DisasContext *ctx) \
3601 if (unlikely(!ctx->fpu_enabled)) { \
3602 gen_exception(ctx, POWERPC_EXCP_FPU); \
3605 if (unlikely(rA(ctx->opcode) == 0)) { \
3606 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3609 gen_set_access_type(ctx, ACCESS_FLOAT); \
3610 EA = tcg_temp_new(); \
3611 gen_addr_imm_index(ctx, EA, 0); \
3612 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3613 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3614 tcg_temp_free(EA); \
3617 #define GEN_LDUXF(name, ldop, opc, type) \
3618 static void glue(gen_, name##ux)(DisasContext *ctx) \
3621 if (unlikely(!ctx->fpu_enabled)) { \
3622 gen_exception(ctx, POWERPC_EXCP_FPU); \
3625 if (unlikely(rA(ctx->opcode) == 0)) { \
3626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3629 gen_set_access_type(ctx, ACCESS_FLOAT); \
3630 EA = tcg_temp_new(); \
3631 gen_addr_reg_index(ctx, EA); \
3632 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3633 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3634 tcg_temp_free(EA); \
3637 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3638 static void glue(gen_, name##x)(DisasContext *ctx) \
3641 if (unlikely(!ctx->fpu_enabled)) { \
3642 gen_exception(ctx, POWERPC_EXCP_FPU); \
3645 gen_set_access_type(ctx, ACCESS_FLOAT); \
3646 EA = tcg_temp_new(); \
3647 gen_addr_reg_index(ctx, EA); \
3648 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3649 tcg_temp_free(EA); \
3652 #define GEN_LDFS(name, ldop, op, type) \
3653 GEN_LDF(name, ldop, op | 0x20, type); \
3654 GEN_LDUF(name, ldop, op | 0x21, type); \
3655 GEN_LDUXF(name, ldop, op | 0x01, type); \
3656 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3658 static inline void gen_qemu_ld32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3660 TCGv t0
= tcg_temp_new();
3661 TCGv_i32 t1
= tcg_temp_new_i32();
3662 gen_qemu_ld32u(ctx
, t0
, arg2
);
3663 tcg_gen_trunc_tl_i32(t1
, t0
);
3665 gen_helper_float32_to_float64(arg1
, cpu_env
, t1
);
3666 tcg_temp_free_i32(t1
);
3669 /* lfd lfdu lfdux lfdx */
3670 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
);
3671 /* lfs lfsu lfsux lfsx */
3672 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
);
3675 static void gen_lfdp(DisasContext
*ctx
)
3678 if (unlikely(!ctx
->fpu_enabled
)) {
3679 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3682 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3683 EA
= tcg_temp_new();
3684 gen_addr_imm_index(ctx
, EA
, 0);
3685 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3686 64-bit byteswap already. */
3687 if (unlikely(ctx
->le_mode
)) {
3688 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3689 tcg_gen_addi_tl(EA
, EA
, 8);
3690 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3692 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3693 tcg_gen_addi_tl(EA
, EA
, 8);
3694 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3700 static void gen_lfdpx(DisasContext
*ctx
)
3703 if (unlikely(!ctx
->fpu_enabled
)) {
3704 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3707 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3708 EA
= tcg_temp_new();
3709 gen_addr_reg_index(ctx
, EA
);
3710 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3711 64-bit byteswap already. */
3712 if (unlikely(ctx
->le_mode
)) {
3713 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3714 tcg_gen_addi_tl(EA
, EA
, 8);
3715 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3717 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3718 tcg_gen_addi_tl(EA
, EA
, 8);
3719 gen_qemu_ld64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3725 static void gen_lfiwax(DisasContext
*ctx
)
3729 if (unlikely(!ctx
->fpu_enabled
)) {
3730 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3733 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3734 EA
= tcg_temp_new();
3735 t0
= tcg_temp_new();
3736 gen_addr_reg_index(ctx
, EA
);
3737 gen_qemu_ld32s(ctx
, t0
, EA
);
3738 tcg_gen_ext_tl_i64(cpu_fpr
[rD(ctx
->opcode
)], t0
);
3744 static void gen_lfiwzx(DisasContext
*ctx
)
3747 if (unlikely(!ctx
->fpu_enabled
)) {
3748 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3751 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3752 EA
= tcg_temp_new();
3753 gen_addr_reg_index(ctx
, EA
);
3754 gen_qemu_ld32u_i64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3757 /*** Floating-point store ***/
3758 #define GEN_STF(name, stop, opc, type) \
3759 static void glue(gen_, name)(DisasContext *ctx) \
3762 if (unlikely(!ctx->fpu_enabled)) { \
3763 gen_exception(ctx, POWERPC_EXCP_FPU); \
3766 gen_set_access_type(ctx, ACCESS_FLOAT); \
3767 EA = tcg_temp_new(); \
3768 gen_addr_imm_index(ctx, EA, 0); \
3769 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3770 tcg_temp_free(EA); \
3773 #define GEN_STUF(name, stop, opc, type) \
3774 static void glue(gen_, name##u)(DisasContext *ctx) \
3777 if (unlikely(!ctx->fpu_enabled)) { \
3778 gen_exception(ctx, POWERPC_EXCP_FPU); \
3781 if (unlikely(rA(ctx->opcode) == 0)) { \
3782 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3785 gen_set_access_type(ctx, ACCESS_FLOAT); \
3786 EA = tcg_temp_new(); \
3787 gen_addr_imm_index(ctx, EA, 0); \
3788 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3790 tcg_temp_free(EA); \
3793 #define GEN_STUXF(name, stop, opc, type) \
3794 static void glue(gen_, name##ux)(DisasContext *ctx) \
3797 if (unlikely(!ctx->fpu_enabled)) { \
3798 gen_exception(ctx, POWERPC_EXCP_FPU); \
3801 if (unlikely(rA(ctx->opcode) == 0)) { \
3802 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3805 gen_set_access_type(ctx, ACCESS_FLOAT); \
3806 EA = tcg_temp_new(); \
3807 gen_addr_reg_index(ctx, EA); \
3808 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3809 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3810 tcg_temp_free(EA); \
3813 #define GEN_STXF(name, stop, opc2, opc3, type) \
3814 static void glue(gen_, name##x)(DisasContext *ctx) \
3817 if (unlikely(!ctx->fpu_enabled)) { \
3818 gen_exception(ctx, POWERPC_EXCP_FPU); \
3821 gen_set_access_type(ctx, ACCESS_FLOAT); \
3822 EA = tcg_temp_new(); \
3823 gen_addr_reg_index(ctx, EA); \
3824 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3825 tcg_temp_free(EA); \
3828 #define GEN_STFS(name, stop, op, type) \
3829 GEN_STF(name, stop, op | 0x20, type); \
3830 GEN_STUF(name, stop, op | 0x21, type); \
3831 GEN_STUXF(name, stop, op | 0x01, type); \
3832 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3834 static inline void gen_qemu_st32fs(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3836 TCGv_i32 t0
= tcg_temp_new_i32();
3837 TCGv t1
= tcg_temp_new();
3838 gen_helper_float64_to_float32(t0
, cpu_env
, arg1
);
3839 tcg_gen_extu_i32_tl(t1
, t0
);
3840 tcg_temp_free_i32(t0
);
3841 gen_qemu_st32(ctx
, t1
, arg2
);
3845 /* stfd stfdu stfdux stfdx */
3846 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
);
3847 /* stfs stfsu stfsux stfsx */
3848 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
);
3851 static void gen_stfdp(DisasContext
*ctx
)
3854 if (unlikely(!ctx
->fpu_enabled
)) {
3855 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3858 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3859 EA
= tcg_temp_new();
3860 gen_addr_imm_index(ctx
, EA
, 0);
3861 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3862 64-bit byteswap already. */
3863 if (unlikely(ctx
->le_mode
)) {
3864 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3865 tcg_gen_addi_tl(EA
, EA
, 8);
3866 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3868 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3869 tcg_gen_addi_tl(EA
, EA
, 8);
3870 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3876 static void gen_stfdpx(DisasContext
*ctx
)
3879 if (unlikely(!ctx
->fpu_enabled
)) {
3880 gen_exception(ctx
, POWERPC_EXCP_FPU
);
3883 gen_set_access_type(ctx
, ACCESS_FLOAT
);
3884 EA
= tcg_temp_new();
3885 gen_addr_reg_index(ctx
, EA
);
3886 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3887 64-bit byteswap already. */
3888 if (unlikely(ctx
->le_mode
)) {
3889 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3890 tcg_gen_addi_tl(EA
, EA
, 8);
3891 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3893 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
)], EA
);
3894 tcg_gen_addi_tl(EA
, EA
, 8);
3895 gen_qemu_st64(ctx
, cpu_fpr
[rD(ctx
->opcode
) + 1], EA
);
3901 static inline void gen_qemu_st32fiw(DisasContext
*ctx
, TCGv_i64 arg1
, TCGv arg2
)
3903 TCGv t0
= tcg_temp_new();
3904 tcg_gen_trunc_i64_tl(t0
, arg1
),
3905 gen_qemu_st32(ctx
, t0
, arg2
);
3909 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
);
3911 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3913 #if defined(TARGET_PPC64)
3915 tcg_gen_movi_tl(cpu_cfar
, nip
);
3919 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3921 if (unlikely(ctx
->singlestep_enabled
)) {
3925 #ifndef CONFIG_USER_ONLY
3926 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3933 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3935 if (NARROW_MODE(ctx
)) {
3936 dest
= (uint32_t) dest
;
3938 if (use_goto_tb(ctx
, dest
)) {
3940 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3941 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3943 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3944 if (unlikely(ctx
->singlestep_enabled
)) {
3945 if ((ctx
->singlestep_enabled
&
3946 (CPU_BRANCH_STEP
| CPU_SINGLE_STEP
)) &&
3947 (ctx
->exception
== POWERPC_EXCP_BRANCH
||
3948 ctx
->exception
== POWERPC_EXCP_TRACE
)) {
3949 target_ulong tmp
= ctx
->nip
;
3951 gen_exception(ctx
, POWERPC_EXCP_TRACE
);
3954 if (ctx
->singlestep_enabled
& GDBSTUB_SINGLE_STEP
) {
3955 gen_debug_exception(ctx
);
3962 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3964 if (NARROW_MODE(ctx
)) {
3965 nip
= (uint32_t)nip
;
3967 tcg_gen_movi_tl(cpu_lr
, nip
);
3971 static void gen_b(DisasContext
*ctx
)
3973 target_ulong li
, target
;
3975 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3976 /* sign extend LI */
3977 li
= LI(ctx
->opcode
);
3978 li
= (li
^ 0x02000000) - 0x02000000;
3979 if (likely(AA(ctx
->opcode
) == 0)) {
3980 target
= ctx
->nip
+ li
- 4;
3984 if (LK(ctx
->opcode
)) {
3985 gen_setlr(ctx
, ctx
->nip
);
3987 gen_update_cfar(ctx
, ctx
->nip
);
3988 gen_goto_tb(ctx
, 0, target
);
3996 static inline void gen_bcond(DisasContext
*ctx
, int type
)
3998 uint32_t bo
= BO(ctx
->opcode
);
4002 ctx
->exception
= POWERPC_EXCP_BRANCH
;
4003 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
4004 target
= tcg_temp_local_new();
4005 if (type
== BCOND_CTR
)
4006 tcg_gen_mov_tl(target
, cpu_ctr
);
4007 else if (type
== BCOND_TAR
)
4008 gen_load_spr(target
, SPR_TAR
);
4010 tcg_gen_mov_tl(target
, cpu_lr
);
4012 TCGV_UNUSED(target
);
4014 if (LK(ctx
->opcode
))
4015 gen_setlr(ctx
, ctx
->nip
);
4016 l1
= gen_new_label();
4017 if ((bo
& 0x4) == 0) {
4018 /* Decrement and test CTR */
4019 TCGv temp
= tcg_temp_new();
4020 if (unlikely(type
== BCOND_CTR
)) {
4021 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4024 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
4025 if (NARROW_MODE(ctx
)) {
4026 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
4028 tcg_gen_mov_tl(temp
, cpu_ctr
);
4031 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
4033 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
4035 tcg_temp_free(temp
);
4037 if ((bo
& 0x10) == 0) {
4039 uint32_t bi
= BI(ctx
->opcode
);
4040 uint32_t mask
= 0x08 >> (bi
& 0x03);
4041 TCGv_i32 temp
= tcg_temp_new_i32();
4044 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
4045 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
4047 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
4048 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
4050 tcg_temp_free_i32(temp
);
4052 gen_update_cfar(ctx
, ctx
->nip
);
4053 if (type
== BCOND_IM
) {
4054 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
4055 if (likely(AA(ctx
->opcode
) == 0)) {
4056 gen_goto_tb(ctx
, 0, ctx
->nip
+ li
- 4);
4058 gen_goto_tb(ctx
, 0, li
);
4061 gen_goto_tb(ctx
, 1, ctx
->nip
);
4063 if (NARROW_MODE(ctx
)) {
4064 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
4066 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
4070 gen_update_nip(ctx
, ctx
->nip
);
4073 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
4074 tcg_temp_free(target
);
4078 static void gen_bc(DisasContext
*ctx
)
4080 gen_bcond(ctx
, BCOND_IM
);
4083 static void gen_bcctr(DisasContext
*ctx
)
4085 gen_bcond(ctx
, BCOND_CTR
);
4088 static void gen_bclr(DisasContext
*ctx
)
4090 gen_bcond(ctx
, BCOND_LR
);
4093 static void gen_bctar(DisasContext
*ctx
)
4095 gen_bcond(ctx
, BCOND_TAR
);
4098 /*** Condition register logical ***/
4099 #define GEN_CRLOGIC(name, tcg_op, opc) \
4100 static void glue(gen_, name)(DisasContext *ctx) \
4105 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4106 t0 = tcg_temp_new_i32(); \
4108 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4110 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4112 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4113 t1 = tcg_temp_new_i32(); \
4114 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4116 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4118 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4120 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4121 tcg_op(t0, t0, t1); \
4122 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4123 tcg_gen_andi_i32(t0, t0, bitmask); \
4124 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4125 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4126 tcg_temp_free_i32(t0); \
4127 tcg_temp_free_i32(t1); \
4131 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
4133 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
4135 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
4137 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
4139 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
4141 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
4143 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
4145 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
4148 static void gen_mcrf(DisasContext
*ctx
)
4150 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
4153 /*** System linkage ***/
4155 /* rfi (supervisor only) */
4156 static void gen_rfi(DisasContext
*ctx
)
4158 #if defined(CONFIG_USER_ONLY)
4161 /* FIXME: This instruction doesn't exist anymore on 64-bit server
4162 * processors compliant with arch 2.x, we should remove it there,
4163 * but we need to fix OpenBIOS not to use it on 970 first
4165 /* Restore CPU state */
4167 gen_update_cfar(ctx
, ctx
->nip
);
4168 gen_helper_rfi(cpu_env
);
4169 gen_sync_exception(ctx
);
4173 #if defined(TARGET_PPC64)
4174 static void gen_rfid(DisasContext
*ctx
)
4176 #if defined(CONFIG_USER_ONLY)
4179 /* Restore CPU state */
4181 gen_update_cfar(ctx
, ctx
->nip
);
4182 gen_helper_rfid(cpu_env
);
4183 gen_sync_exception(ctx
);
4187 static void gen_hrfid(DisasContext
*ctx
)
4189 #if defined(CONFIG_USER_ONLY)
4192 /* Restore CPU state */
4194 gen_helper_hrfid(cpu_env
);
4195 gen_sync_exception(ctx
);
4201 #if defined(CONFIG_USER_ONLY)
4202 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4204 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4206 static void gen_sc(DisasContext
*ctx
)
4210 lev
= (ctx
->opcode
>> 5) & 0x7F;
4211 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
4217 static void gen_tw(DisasContext
*ctx
)
4219 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4220 /* Update the nip since this might generate a trap exception */
4221 gen_update_nip(ctx
, ctx
->nip
);
4222 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4224 tcg_temp_free_i32(t0
);
4228 static void gen_twi(DisasContext
*ctx
)
4230 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4231 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4232 /* Update the nip since this might generate a trap exception */
4233 gen_update_nip(ctx
, ctx
->nip
);
4234 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4236 tcg_temp_free_i32(t1
);
4239 #if defined(TARGET_PPC64)
4241 static void gen_td(DisasContext
*ctx
)
4243 TCGv_i32 t0
= tcg_const_i32(TO(ctx
->opcode
));
4244 /* Update the nip since this might generate a trap exception */
4245 gen_update_nip(ctx
, ctx
->nip
);
4246 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4248 tcg_temp_free_i32(t0
);
4252 static void gen_tdi(DisasContext
*ctx
)
4254 TCGv t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4255 TCGv_i32 t1
= tcg_const_i32(TO(ctx
->opcode
));
4256 /* Update the nip since this might generate a trap exception */
4257 gen_update_nip(ctx
, ctx
->nip
);
4258 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4260 tcg_temp_free_i32(t1
);
4264 /*** Processor control ***/
4266 static void gen_read_xer(TCGv dst
)
4268 TCGv t0
= tcg_temp_new();
4269 TCGv t1
= tcg_temp_new();
4270 TCGv t2
= tcg_temp_new();
4271 tcg_gen_mov_tl(dst
, cpu_xer
);
4272 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
4273 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
4274 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
4275 tcg_gen_or_tl(t0
, t0
, t1
);
4276 tcg_gen_or_tl(dst
, dst
, t2
);
4277 tcg_gen_or_tl(dst
, dst
, t0
);
4283 static void gen_write_xer(TCGv src
)
4285 tcg_gen_andi_tl(cpu_xer
, src
,
4286 ~((1u << XER_SO
) | (1u << XER_OV
) | (1u << XER_CA
)));
4287 tcg_gen_shri_tl(cpu_so
, src
, XER_SO
);
4288 tcg_gen_shri_tl(cpu_ov
, src
, XER_OV
);
4289 tcg_gen_shri_tl(cpu_ca
, src
, XER_CA
);
4290 tcg_gen_andi_tl(cpu_so
, cpu_so
, 1);
4291 tcg_gen_andi_tl(cpu_ov
, cpu_ov
, 1);
4292 tcg_gen_andi_tl(cpu_ca
, cpu_ca
, 1);
4296 static void gen_mcrxr(DisasContext
*ctx
)
4298 TCGv_i32 t0
= tcg_temp_new_i32();
4299 TCGv_i32 t1
= tcg_temp_new_i32();
4300 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4302 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4303 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4304 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4305 tcg_gen_shli_i32(t0
, t0
, 3);
4306 tcg_gen_shli_i32(t1
, t1
, 2);
4307 tcg_gen_shli_i32(dst
, dst
, 1);
4308 tcg_gen_or_i32(dst
, dst
, t0
);
4309 tcg_gen_or_i32(dst
, dst
, t1
);
4310 tcg_temp_free_i32(t0
);
4311 tcg_temp_free_i32(t1
);
4313 tcg_gen_movi_tl(cpu_so
, 0);
4314 tcg_gen_movi_tl(cpu_ov
, 0);
4315 tcg_gen_movi_tl(cpu_ca
, 0);
4319 static void gen_mfcr(DisasContext
*ctx
)
4323 if (likely(ctx
->opcode
& 0x00100000)) {
4324 crm
= CRM(ctx
->opcode
);
4325 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4327 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4328 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4329 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4332 TCGv_i32 t0
= tcg_temp_new_i32();
4333 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4334 tcg_gen_shli_i32(t0
, t0
, 4);
4335 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4336 tcg_gen_shli_i32(t0
, t0
, 4);
4337 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4338 tcg_gen_shli_i32(t0
, t0
, 4);
4339 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4340 tcg_gen_shli_i32(t0
, t0
, 4);
4341 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4342 tcg_gen_shli_i32(t0
, t0
, 4);
4343 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4344 tcg_gen_shli_i32(t0
, t0
, 4);
4345 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4346 tcg_gen_shli_i32(t0
, t0
, 4);
4347 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4348 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4349 tcg_temp_free_i32(t0
);
4354 static void gen_mfmsr(DisasContext
*ctx
)
4357 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4360 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
4363 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
4364 printf("ERROR: try to access SPR %d !\n", sprn
);
4367 #define SPR_NOACCESS (&spr_noaccess)
4370 static inline void gen_op_mfspr(DisasContext
*ctx
)
4372 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4373 uint32_t sprn
= SPR(ctx
->opcode
);
4375 #if defined(CONFIG_USER_ONLY)
4376 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4379 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4380 } else if (ctx
->hv
) {
4381 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4383 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4386 if (likely(read_cb
!= NULL
)) {
4387 if (likely(read_cb
!= SPR_NOACCESS
)) {
4388 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4390 /* Privilege exception */
4391 /* This is a hack to avoid warnings when running Linux:
4392 * this OS breaks the PowerPC virtualisation model,
4393 * allowing userland application to read the PVR
4395 if (sprn
!= SPR_PVR
) {
4396 fprintf(stderr
, "Trying to read privileged spr %d (0x%03x) at "
4397 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4398 if (qemu_log_separate()) {
4399 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4400 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4403 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4406 /* ISA 2.07 defines these as no-ops */
4407 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4408 (sprn
>= 808 && sprn
<= 811)) {
4413 fprintf(stderr
, "Trying to read invalid spr %d (0x%03x) at "
4414 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4415 if (qemu_log_separate()) {
4416 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4417 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4420 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4421 * it can generate a priv, a hv emu or a no-op
4425 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4428 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
4429 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4435 static void gen_mfspr(DisasContext
*ctx
)
4441 static void gen_mftb(DisasContext
*ctx
)
4447 static void gen_mtcrf(DisasContext
*ctx
)
4451 crm
= CRM(ctx
->opcode
);
4452 if (likely((ctx
->opcode
& 0x00100000))) {
4453 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4454 TCGv_i32 temp
= tcg_temp_new_i32();
4456 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4457 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4458 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4459 tcg_temp_free_i32(temp
);
4462 TCGv_i32 temp
= tcg_temp_new_i32();
4463 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4464 for (crn
= 0 ; crn
< 8 ; crn
++) {
4465 if (crm
& (1 << crn
)) {
4466 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4467 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4470 tcg_temp_free_i32(temp
);
4475 #if defined(TARGET_PPC64)
4476 static void gen_mtmsrd(DisasContext
*ctx
)
4480 #if !defined(CONFIG_USER_ONLY)
4481 if (ctx
->opcode
& 0x00010000) {
4482 /* Special form that does not need any synchronisation */
4483 TCGv t0
= tcg_temp_new();
4484 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4485 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4486 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4489 /* XXX: we need to update nip before the store
4490 * if we enter power saving mode, we will exit the loop
4491 * directly from ppc_store_msr
4493 gen_update_nip(ctx
, ctx
->nip
);
4494 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4495 /* Must stop the translation as machine state (may have) changed */
4496 /* Note that mtmsr is not always defined as context-synchronizing */
4497 gen_stop_exception(ctx
);
4499 #endif /* !defined(CONFIG_USER_ONLY) */
4501 #endif /* defined(TARGET_PPC64) */
4503 static void gen_mtmsr(DisasContext
*ctx
)
4507 #if !defined(CONFIG_USER_ONLY)
4508 if (ctx
->opcode
& 0x00010000) {
4509 /* Special form that does not need any synchronisation */
4510 TCGv t0
= tcg_temp_new();
4511 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4512 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4513 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4516 TCGv msr
= tcg_temp_new();
4518 /* XXX: we need to update nip before the store
4519 * if we enter power saving mode, we will exit the loop
4520 * directly from ppc_store_msr
4522 gen_update_nip(ctx
, ctx
->nip
);
4523 #if defined(TARGET_PPC64)
4524 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4526 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4528 gen_helper_store_msr(cpu_env
, msr
);
4530 /* Must stop the translation as machine state (may have) changed */
4531 /* Note that mtmsr is not always defined as context-synchronizing */
4532 gen_stop_exception(ctx
);
4538 static void gen_mtspr(DisasContext
*ctx
)
4540 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4541 uint32_t sprn
= SPR(ctx
->opcode
);
4543 #if defined(CONFIG_USER_ONLY)
4544 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4547 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4548 } else if (ctx
->hv
) {
4549 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4551 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4554 if (likely(write_cb
!= NULL
)) {
4555 if (likely(write_cb
!= SPR_NOACCESS
)) {
4556 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4558 /* Privilege exception */
4559 fprintf(stderr
, "Trying to write privileged spr %d (0x%03x) at "
4560 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4561 if (qemu_log_separate()) {
4562 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4563 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4565 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4568 /* ISA 2.07 defines these as no-ops */
4569 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4570 (sprn
>= 808 && sprn
<= 811)) {
4576 if (qemu_log_separate()) {
4577 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4578 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4580 fprintf(stderr
, "Trying to write invalid spr %d (0x%03x) at "
4581 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->nip
- 4);
4584 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4585 * it can generate a priv, a hv emu or a no-op
4589 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4592 if (ctx
->pr
|| sprn
== 0) {
4593 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4599 /*** Cache management ***/
4602 static void gen_dcbf(DisasContext
*ctx
)
4604 /* XXX: specification says this is treated as a load by the MMU */
4606 gen_set_access_type(ctx
, ACCESS_CACHE
);
4607 t0
= tcg_temp_new();
4608 gen_addr_reg_index(ctx
, t0
);
4609 gen_qemu_ld8u(ctx
, t0
, t0
);
4613 /* dcbi (Supervisor only) */
4614 static void gen_dcbi(DisasContext
*ctx
)
4616 #if defined(CONFIG_USER_ONLY)
4622 EA
= tcg_temp_new();
4623 gen_set_access_type(ctx
, ACCESS_CACHE
);
4624 gen_addr_reg_index(ctx
, EA
);
4625 val
= tcg_temp_new();
4626 /* XXX: specification says this should be treated as a store by the MMU */
4627 gen_qemu_ld8u(ctx
, val
, EA
);
4628 gen_qemu_st8(ctx
, val
, EA
);
4631 #endif /* defined(CONFIG_USER_ONLY) */
4635 static void gen_dcbst(DisasContext
*ctx
)
4637 /* XXX: specification say this is treated as a load by the MMU */
4639 gen_set_access_type(ctx
, ACCESS_CACHE
);
4640 t0
= tcg_temp_new();
4641 gen_addr_reg_index(ctx
, t0
);
4642 gen_qemu_ld8u(ctx
, t0
, t0
);
4647 static void gen_dcbt(DisasContext
*ctx
)
4649 /* interpreted as no-op */
4650 /* XXX: specification say this is treated as a load by the MMU
4651 * but does not generate any exception
4656 static void gen_dcbtst(DisasContext
*ctx
)
4658 /* interpreted as no-op */
4659 /* XXX: specification say this is treated as a load by the MMU
4660 * but does not generate any exception
4665 static void gen_dcbtls(DisasContext
*ctx
)
4667 /* Always fails locking the cache */
4668 TCGv t0
= tcg_temp_new();
4669 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4670 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4671 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4676 static void gen_dcbz(DisasContext
*ctx
)
4679 TCGv_i32 tcgv_is_dcbzl
;
4680 int is_dcbzl
= ctx
->opcode
& 0x00200000 ? 1 : 0;
4682 gen_set_access_type(ctx
, ACCESS_CACHE
);
4683 /* NIP cannot be restored if the memory exception comes from an helper */
4684 gen_update_nip(ctx
, ctx
->nip
- 4);
4685 tcgv_addr
= tcg_temp_new();
4686 tcgv_is_dcbzl
= tcg_const_i32(is_dcbzl
);
4688 gen_addr_reg_index(ctx
, tcgv_addr
);
4689 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_is_dcbzl
);
4691 tcg_temp_free(tcgv_addr
);
4692 tcg_temp_free_i32(tcgv_is_dcbzl
);
4696 static void gen_dst(DisasContext
*ctx
)
4698 if (rA(ctx
->opcode
) == 0) {
4699 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4701 /* interpreted as no-op */
4706 static void gen_dstst(DisasContext
*ctx
)
4708 if (rA(ctx
->opcode
) == 0) {
4709 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
4711 /* interpreted as no-op */
4717 static void gen_dss(DisasContext
*ctx
)
4719 /* interpreted as no-op */
4723 static void gen_icbi(DisasContext
*ctx
)
4726 gen_set_access_type(ctx
, ACCESS_CACHE
);
4727 /* NIP cannot be restored if the memory exception comes from an helper */
4728 gen_update_nip(ctx
, ctx
->nip
- 4);
4729 t0
= tcg_temp_new();
4730 gen_addr_reg_index(ctx
, t0
);
4731 gen_helper_icbi(cpu_env
, t0
);
4737 static void gen_dcba(DisasContext
*ctx
)
4739 /* interpreted as no-op */
4740 /* XXX: specification say this is treated as a store by the MMU
4741 * but does not generate any exception
4745 /*** Segment register manipulation ***/
4746 /* Supervisor only: */
4749 static void gen_mfsr(DisasContext
*ctx
)
4751 #if defined(CONFIG_USER_ONLY)
4757 t0
= tcg_const_tl(SR(ctx
->opcode
));
4758 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4760 #endif /* defined(CONFIG_USER_ONLY) */
4764 static void gen_mfsrin(DisasContext
*ctx
)
4766 #if defined(CONFIG_USER_ONLY)
4772 t0
= tcg_temp_new();
4773 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4774 tcg_gen_andi_tl(t0
, t0
, 0xF);
4775 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4777 #endif /* defined(CONFIG_USER_ONLY) */
4781 static void gen_mtsr(DisasContext
*ctx
)
4783 #if defined(CONFIG_USER_ONLY)
4789 t0
= tcg_const_tl(SR(ctx
->opcode
));
4790 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4792 #endif /* defined(CONFIG_USER_ONLY) */
4796 static void gen_mtsrin(DisasContext
*ctx
)
4798 #if defined(CONFIG_USER_ONLY)
4804 t0
= tcg_temp_new();
4805 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4806 tcg_gen_andi_tl(t0
, t0
, 0xF);
4807 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4809 #endif /* defined(CONFIG_USER_ONLY) */
4812 #if defined(TARGET_PPC64)
4813 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4816 static void gen_mfsr_64b(DisasContext
*ctx
)
4818 #if defined(CONFIG_USER_ONLY)
4824 t0
= tcg_const_tl(SR(ctx
->opcode
));
4825 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4827 #endif /* defined(CONFIG_USER_ONLY) */
4831 static void gen_mfsrin_64b(DisasContext
*ctx
)
4833 #if defined(CONFIG_USER_ONLY)
4839 t0
= tcg_temp_new();
4840 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4841 tcg_gen_andi_tl(t0
, t0
, 0xF);
4842 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4844 #endif /* defined(CONFIG_USER_ONLY) */
4848 static void gen_mtsr_64b(DisasContext
*ctx
)
4850 #if defined(CONFIG_USER_ONLY)
4856 t0
= tcg_const_tl(SR(ctx
->opcode
));
4857 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4859 #endif /* defined(CONFIG_USER_ONLY) */
4863 static void gen_mtsrin_64b(DisasContext
*ctx
)
4865 #if defined(CONFIG_USER_ONLY)
4871 t0
= tcg_temp_new();
4872 tcg_gen_shri_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28);
4873 tcg_gen_andi_tl(t0
, t0
, 0xF);
4874 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4876 #endif /* defined(CONFIG_USER_ONLY) */
4880 static void gen_slbmte(DisasContext
*ctx
)
4882 #if defined(CONFIG_USER_ONLY)
4887 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4888 cpu_gpr
[rS(ctx
->opcode
)]);
4889 #endif /* defined(CONFIG_USER_ONLY) */
4892 static void gen_slbmfee(DisasContext
*ctx
)
4894 #if defined(CONFIG_USER_ONLY)
4899 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4900 cpu_gpr
[rB(ctx
->opcode
)]);
4901 #endif /* defined(CONFIG_USER_ONLY) */
4904 static void gen_slbmfev(DisasContext
*ctx
)
4906 #if defined(CONFIG_USER_ONLY)
4911 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4912 cpu_gpr
[rB(ctx
->opcode
)]);
4913 #endif /* defined(CONFIG_USER_ONLY) */
4916 static void gen_slbfee_(DisasContext
*ctx
)
4918 #if defined(CONFIG_USER_ONLY)
4919 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4923 if (unlikely(ctx
->pr
)) {
4924 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4927 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4928 cpu_gpr
[rB(ctx
->opcode
)]);
4929 l1
= gen_new_label();
4930 l2
= gen_new_label();
4931 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4932 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4933 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 1 << CRF_EQ
);
4936 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4940 #endif /* defined(TARGET_PPC64) */
4942 /*** Lookaside buffer management ***/
4943 /* Optional & supervisor only: */
4946 static void gen_tlbia(DisasContext
*ctx
)
4948 #if defined(CONFIG_USER_ONLY)
4953 gen_helper_tlbia(cpu_env
);
4954 #endif /* defined(CONFIG_USER_ONLY) */
4958 static void gen_tlbiel(DisasContext
*ctx
)
4960 #if defined(CONFIG_USER_ONLY)
4965 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4966 #endif /* defined(CONFIG_USER_ONLY) */
4970 static void gen_tlbie(DisasContext
*ctx
)
4972 #if defined(CONFIG_USER_ONLY)
4977 if (NARROW_MODE(ctx
)) {
4978 TCGv t0
= tcg_temp_new();
4979 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4980 gen_helper_tlbie(cpu_env
, t0
);
4983 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4985 #endif /* defined(CONFIG_USER_ONLY) */
4989 static void gen_tlbsync(DisasContext
*ctx
)
4991 #if defined(CONFIG_USER_ONLY)
4996 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4997 * embedded however needs to deal with tlbsync. We don't try to be
4998 * fancy and swallow the overhead of checking for both.
5000 gen_check_tlb_flush(ctx
);
5001 #endif /* defined(CONFIG_USER_ONLY) */
5004 #if defined(TARGET_PPC64)
5006 static void gen_slbia(DisasContext
*ctx
)
5008 #if defined(CONFIG_USER_ONLY)
5013 gen_helper_slbia(cpu_env
);
5014 #endif /* defined(CONFIG_USER_ONLY) */
5018 static void gen_slbie(DisasContext
*ctx
)
5020 #if defined(CONFIG_USER_ONLY)
5025 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5026 #endif /* defined(CONFIG_USER_ONLY) */
5028 #endif /* defined(TARGET_PPC64) */
5030 /*** External control ***/
5034 static void gen_eciwx(DisasContext
*ctx
)
5037 /* Should check EAR[E] ! */
5038 gen_set_access_type(ctx
, ACCESS_EXT
);
5039 t0
= tcg_temp_new();
5040 gen_addr_reg_index(ctx
, t0
);
5041 gen_check_align(ctx
, t0
, 0x03);
5042 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
5047 static void gen_ecowx(DisasContext
*ctx
)
5050 /* Should check EAR[E] ! */
5051 gen_set_access_type(ctx
, ACCESS_EXT
);
5052 t0
= tcg_temp_new();
5053 gen_addr_reg_index(ctx
, t0
);
5054 gen_check_align(ctx
, t0
, 0x03);
5055 gen_qemu_st32(ctx
, cpu_gpr
[rD(ctx
->opcode
)], t0
);
5059 /* PowerPC 601 specific instructions */
5062 static void gen_abs(DisasContext
*ctx
)
5064 TCGLabel
*l1
= gen_new_label();
5065 TCGLabel
*l2
= gen_new_label();
5066 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5067 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5070 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5072 if (unlikely(Rc(ctx
->opcode
) != 0))
5073 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5077 static void gen_abso(DisasContext
*ctx
)
5079 TCGLabel
*l1
= gen_new_label();
5080 TCGLabel
*l2
= gen_new_label();
5081 TCGLabel
*l3
= gen_new_label();
5082 /* Start with XER OV disabled, the most likely case */
5083 tcg_gen_movi_tl(cpu_ov
, 0);
5084 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
5085 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
5086 tcg_gen_movi_tl(cpu_ov
, 1);
5087 tcg_gen_movi_tl(cpu_so
, 1);
5090 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5093 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5095 if (unlikely(Rc(ctx
->opcode
) != 0))
5096 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5100 static void gen_clcs(DisasContext
*ctx
)
5102 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
5103 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5104 tcg_temp_free_i32(t0
);
5105 /* Rc=1 sets CR0 to an undefined state */
5109 static void gen_div(DisasContext
*ctx
)
5111 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5112 cpu_gpr
[rB(ctx
->opcode
)]);
5113 if (unlikely(Rc(ctx
->opcode
) != 0))
5114 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5118 static void gen_divo(DisasContext
*ctx
)
5120 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5121 cpu_gpr
[rB(ctx
->opcode
)]);
5122 if (unlikely(Rc(ctx
->opcode
) != 0))
5123 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5127 static void gen_divs(DisasContext
*ctx
)
5129 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5130 cpu_gpr
[rB(ctx
->opcode
)]);
5131 if (unlikely(Rc(ctx
->opcode
) != 0))
5132 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5135 /* divso - divso. */
5136 static void gen_divso(DisasContext
*ctx
)
5138 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5139 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5140 if (unlikely(Rc(ctx
->opcode
) != 0))
5141 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5145 static void gen_doz(DisasContext
*ctx
)
5147 TCGLabel
*l1
= gen_new_label();
5148 TCGLabel
*l2
= gen_new_label();
5149 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5150 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5153 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5155 if (unlikely(Rc(ctx
->opcode
) != 0))
5156 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5160 static void gen_dozo(DisasContext
*ctx
)
5162 TCGLabel
*l1
= gen_new_label();
5163 TCGLabel
*l2
= gen_new_label();
5164 TCGv t0
= tcg_temp_new();
5165 TCGv t1
= tcg_temp_new();
5166 TCGv t2
= tcg_temp_new();
5167 /* Start with XER OV disabled, the most likely case */
5168 tcg_gen_movi_tl(cpu_ov
, 0);
5169 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5170 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5171 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5172 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5173 tcg_gen_andc_tl(t1
, t1
, t2
);
5174 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5175 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5176 tcg_gen_movi_tl(cpu_ov
, 1);
5177 tcg_gen_movi_tl(cpu_so
, 1);
5180 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5185 if (unlikely(Rc(ctx
->opcode
) != 0))
5186 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5190 static void gen_dozi(DisasContext
*ctx
)
5192 target_long simm
= SIMM(ctx
->opcode
);
5193 TCGLabel
*l1
= gen_new_label();
5194 TCGLabel
*l2
= gen_new_label();
5195 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5196 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5199 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5201 if (unlikely(Rc(ctx
->opcode
) != 0))
5202 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5205 /* lscbx - lscbx. */
5206 static void gen_lscbx(DisasContext
*ctx
)
5208 TCGv t0
= tcg_temp_new();
5209 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5210 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5211 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5213 gen_addr_reg_index(ctx
, t0
);
5214 /* NIP cannot be restored if the memory exception comes from an helper */
5215 gen_update_nip(ctx
, ctx
->nip
- 4);
5216 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5217 tcg_temp_free_i32(t1
);
5218 tcg_temp_free_i32(t2
);
5219 tcg_temp_free_i32(t3
);
5220 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5221 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5222 if (unlikely(Rc(ctx
->opcode
) != 0))
5223 gen_set_Rc0(ctx
, t0
);
5227 /* maskg - maskg. */
5228 static void gen_maskg(DisasContext
*ctx
)
5230 TCGLabel
*l1
= gen_new_label();
5231 TCGv t0
= tcg_temp_new();
5232 TCGv t1
= tcg_temp_new();
5233 TCGv t2
= tcg_temp_new();
5234 TCGv t3
= tcg_temp_new();
5235 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5236 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5237 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5238 tcg_gen_addi_tl(t2
, t0
, 1);
5239 tcg_gen_shr_tl(t2
, t3
, t2
);
5240 tcg_gen_shr_tl(t3
, t3
, t1
);
5241 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5242 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5243 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5249 if (unlikely(Rc(ctx
->opcode
) != 0))
5250 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5253 /* maskir - maskir. */
5254 static void gen_maskir(DisasContext
*ctx
)
5256 TCGv t0
= tcg_temp_new();
5257 TCGv t1
= tcg_temp_new();
5258 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5259 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5260 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5263 if (unlikely(Rc(ctx
->opcode
) != 0))
5264 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5268 static void gen_mul(DisasContext
*ctx
)
5270 TCGv_i64 t0
= tcg_temp_new_i64();
5271 TCGv_i64 t1
= tcg_temp_new_i64();
5272 TCGv t2
= tcg_temp_new();
5273 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5274 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5275 tcg_gen_mul_i64(t0
, t0
, t1
);
5276 tcg_gen_trunc_i64_tl(t2
, t0
);
5277 gen_store_spr(SPR_MQ
, t2
);
5278 tcg_gen_shri_i64(t1
, t0
, 32);
5279 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5280 tcg_temp_free_i64(t0
);
5281 tcg_temp_free_i64(t1
);
5283 if (unlikely(Rc(ctx
->opcode
) != 0))
5284 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5288 static void gen_mulo(DisasContext
*ctx
)
5290 TCGLabel
*l1
= gen_new_label();
5291 TCGv_i64 t0
= tcg_temp_new_i64();
5292 TCGv_i64 t1
= tcg_temp_new_i64();
5293 TCGv t2
= tcg_temp_new();
5294 /* Start with XER OV disabled, the most likely case */
5295 tcg_gen_movi_tl(cpu_ov
, 0);
5296 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5297 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5298 tcg_gen_mul_i64(t0
, t0
, t1
);
5299 tcg_gen_trunc_i64_tl(t2
, t0
);
5300 gen_store_spr(SPR_MQ
, t2
);
5301 tcg_gen_shri_i64(t1
, t0
, 32);
5302 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5303 tcg_gen_ext32s_i64(t1
, t0
);
5304 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5305 tcg_gen_movi_tl(cpu_ov
, 1);
5306 tcg_gen_movi_tl(cpu_so
, 1);
5308 tcg_temp_free_i64(t0
);
5309 tcg_temp_free_i64(t1
);
5311 if (unlikely(Rc(ctx
->opcode
) != 0))
5312 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5316 static void gen_nabs(DisasContext
*ctx
)
5318 TCGLabel
*l1
= gen_new_label();
5319 TCGLabel
*l2
= gen_new_label();
5320 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5321 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5324 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5326 if (unlikely(Rc(ctx
->opcode
) != 0))
5327 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5330 /* nabso - nabso. */
5331 static void gen_nabso(DisasContext
*ctx
)
5333 TCGLabel
*l1
= gen_new_label();
5334 TCGLabel
*l2
= gen_new_label();
5335 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5336 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5339 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5341 /* nabs never overflows */
5342 tcg_gen_movi_tl(cpu_ov
, 0);
5343 if (unlikely(Rc(ctx
->opcode
) != 0))
5344 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5348 static void gen_rlmi(DisasContext
*ctx
)
5350 uint32_t mb
= MB(ctx
->opcode
);
5351 uint32_t me
= ME(ctx
->opcode
);
5352 TCGv t0
= tcg_temp_new();
5353 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5354 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5355 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5356 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
5357 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5359 if (unlikely(Rc(ctx
->opcode
) != 0))
5360 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5364 static void gen_rrib(DisasContext
*ctx
)
5366 TCGv t0
= tcg_temp_new();
5367 TCGv t1
= tcg_temp_new();
5368 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5369 tcg_gen_movi_tl(t1
, 0x80000000);
5370 tcg_gen_shr_tl(t1
, t1
, t0
);
5371 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5372 tcg_gen_and_tl(t0
, t0
, t1
);
5373 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5374 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5377 if (unlikely(Rc(ctx
->opcode
) != 0))
5378 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5382 static void gen_sle(DisasContext
*ctx
)
5384 TCGv t0
= tcg_temp_new();
5385 TCGv t1
= tcg_temp_new();
5386 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5387 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5388 tcg_gen_subfi_tl(t1
, 32, t1
);
5389 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5390 tcg_gen_or_tl(t1
, t0
, t1
);
5391 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5392 gen_store_spr(SPR_MQ
, t1
);
5395 if (unlikely(Rc(ctx
->opcode
) != 0))
5396 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5400 static void gen_sleq(DisasContext
*ctx
)
5402 TCGv t0
= tcg_temp_new();
5403 TCGv t1
= tcg_temp_new();
5404 TCGv t2
= tcg_temp_new();
5405 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5406 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5407 tcg_gen_shl_tl(t2
, t2
, t0
);
5408 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5409 gen_load_spr(t1
, SPR_MQ
);
5410 gen_store_spr(SPR_MQ
, t0
);
5411 tcg_gen_and_tl(t0
, t0
, t2
);
5412 tcg_gen_andc_tl(t1
, t1
, t2
);
5413 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5417 if (unlikely(Rc(ctx
->opcode
) != 0))
5418 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5422 static void gen_sliq(DisasContext
*ctx
)
5424 int sh
= SH(ctx
->opcode
);
5425 TCGv t0
= tcg_temp_new();
5426 TCGv t1
= tcg_temp_new();
5427 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5428 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5429 tcg_gen_or_tl(t1
, t0
, t1
);
5430 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5431 gen_store_spr(SPR_MQ
, t1
);
5434 if (unlikely(Rc(ctx
->opcode
) != 0))
5435 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5438 /* slliq - slliq. */
5439 static void gen_slliq(DisasContext
*ctx
)
5441 int sh
= SH(ctx
->opcode
);
5442 TCGv t0
= tcg_temp_new();
5443 TCGv t1
= tcg_temp_new();
5444 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5445 gen_load_spr(t1
, SPR_MQ
);
5446 gen_store_spr(SPR_MQ
, t0
);
5447 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5448 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5449 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5452 if (unlikely(Rc(ctx
->opcode
) != 0))
5453 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5457 static void gen_sllq(DisasContext
*ctx
)
5459 TCGLabel
*l1
= gen_new_label();
5460 TCGLabel
*l2
= gen_new_label();
5461 TCGv t0
= tcg_temp_local_new();
5462 TCGv t1
= tcg_temp_local_new();
5463 TCGv t2
= tcg_temp_local_new();
5464 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5465 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5466 tcg_gen_shl_tl(t1
, t1
, t2
);
5467 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5468 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5469 gen_load_spr(t0
, SPR_MQ
);
5470 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5473 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5474 gen_load_spr(t2
, SPR_MQ
);
5475 tcg_gen_andc_tl(t1
, t2
, t1
);
5476 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5481 if (unlikely(Rc(ctx
->opcode
) != 0))
5482 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5486 static void gen_slq(DisasContext
*ctx
)
5488 TCGLabel
*l1
= gen_new_label();
5489 TCGv t0
= tcg_temp_new();
5490 TCGv t1
= tcg_temp_new();
5491 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5492 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5493 tcg_gen_subfi_tl(t1
, 32, t1
);
5494 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5495 tcg_gen_or_tl(t1
, t0
, t1
);
5496 gen_store_spr(SPR_MQ
, t1
);
5497 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5498 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5499 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5500 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5504 if (unlikely(Rc(ctx
->opcode
) != 0))
5505 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5508 /* sraiq - sraiq. */
5509 static void gen_sraiq(DisasContext
*ctx
)
5511 int sh
= SH(ctx
->opcode
);
5512 TCGLabel
*l1
= gen_new_label();
5513 TCGv t0
= tcg_temp_new();
5514 TCGv t1
= tcg_temp_new();
5515 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5516 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5517 tcg_gen_or_tl(t0
, t0
, t1
);
5518 gen_store_spr(SPR_MQ
, t0
);
5519 tcg_gen_movi_tl(cpu_ca
, 0);
5520 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5521 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5522 tcg_gen_movi_tl(cpu_ca
, 1);
5524 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5527 if (unlikely(Rc(ctx
->opcode
) != 0))
5528 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5532 static void gen_sraq(DisasContext
*ctx
)
5534 TCGLabel
*l1
= gen_new_label();
5535 TCGLabel
*l2
= gen_new_label();
5536 TCGv t0
= tcg_temp_new();
5537 TCGv t1
= tcg_temp_local_new();
5538 TCGv t2
= tcg_temp_local_new();
5539 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5540 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5541 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5542 tcg_gen_subfi_tl(t2
, 32, t2
);
5543 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5544 tcg_gen_or_tl(t0
, t0
, t2
);
5545 gen_store_spr(SPR_MQ
, t0
);
5546 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5547 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5548 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5549 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5552 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5553 tcg_gen_movi_tl(cpu_ca
, 0);
5554 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5555 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5556 tcg_gen_movi_tl(cpu_ca
, 1);
5560 if (unlikely(Rc(ctx
->opcode
) != 0))
5561 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5565 static void gen_sre(DisasContext
*ctx
)
5567 TCGv t0
= tcg_temp_new();
5568 TCGv t1
= tcg_temp_new();
5569 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5570 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5571 tcg_gen_subfi_tl(t1
, 32, t1
);
5572 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5573 tcg_gen_or_tl(t1
, t0
, t1
);
5574 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5575 gen_store_spr(SPR_MQ
, t1
);
5578 if (unlikely(Rc(ctx
->opcode
) != 0))
5579 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5583 static void gen_srea(DisasContext
*ctx
)
5585 TCGv t0
= tcg_temp_new();
5586 TCGv t1
= tcg_temp_new();
5587 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5588 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5589 gen_store_spr(SPR_MQ
, t0
);
5590 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5593 if (unlikely(Rc(ctx
->opcode
) != 0))
5594 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5598 static void gen_sreq(DisasContext
*ctx
)
5600 TCGv t0
= tcg_temp_new();
5601 TCGv t1
= tcg_temp_new();
5602 TCGv t2
= tcg_temp_new();
5603 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5604 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5605 tcg_gen_shr_tl(t1
, t1
, t0
);
5606 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5607 gen_load_spr(t2
, SPR_MQ
);
5608 gen_store_spr(SPR_MQ
, t0
);
5609 tcg_gen_and_tl(t0
, t0
, t1
);
5610 tcg_gen_andc_tl(t2
, t2
, t1
);
5611 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5615 if (unlikely(Rc(ctx
->opcode
) != 0))
5616 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5620 static void gen_sriq(DisasContext
*ctx
)
5622 int sh
= SH(ctx
->opcode
);
5623 TCGv t0
= tcg_temp_new();
5624 TCGv t1
= tcg_temp_new();
5625 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5626 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5627 tcg_gen_or_tl(t1
, t0
, t1
);
5628 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5629 gen_store_spr(SPR_MQ
, t1
);
5632 if (unlikely(Rc(ctx
->opcode
) != 0))
5633 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5637 static void gen_srliq(DisasContext
*ctx
)
5639 int sh
= SH(ctx
->opcode
);
5640 TCGv t0
= tcg_temp_new();
5641 TCGv t1
= tcg_temp_new();
5642 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5643 gen_load_spr(t1
, SPR_MQ
);
5644 gen_store_spr(SPR_MQ
, t0
);
5645 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5646 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5647 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5650 if (unlikely(Rc(ctx
->opcode
) != 0))
5651 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5655 static void gen_srlq(DisasContext
*ctx
)
5657 TCGLabel
*l1
= gen_new_label();
5658 TCGLabel
*l2
= gen_new_label();
5659 TCGv t0
= tcg_temp_local_new();
5660 TCGv t1
= tcg_temp_local_new();
5661 TCGv t2
= tcg_temp_local_new();
5662 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5663 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5664 tcg_gen_shr_tl(t2
, t1
, t2
);
5665 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5666 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5667 gen_load_spr(t0
, SPR_MQ
);
5668 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5671 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5672 tcg_gen_and_tl(t0
, t0
, t2
);
5673 gen_load_spr(t1
, SPR_MQ
);
5674 tcg_gen_andc_tl(t1
, t1
, t2
);
5675 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5680 if (unlikely(Rc(ctx
->opcode
) != 0))
5681 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5685 static void gen_srq(DisasContext
*ctx
)
5687 TCGLabel
*l1
= gen_new_label();
5688 TCGv t0
= tcg_temp_new();
5689 TCGv t1
= tcg_temp_new();
5690 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5691 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5692 tcg_gen_subfi_tl(t1
, 32, t1
);
5693 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5694 tcg_gen_or_tl(t1
, t0
, t1
);
5695 gen_store_spr(SPR_MQ
, t1
);
5696 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5697 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5698 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5699 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5703 if (unlikely(Rc(ctx
->opcode
) != 0))
5704 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5707 /* PowerPC 602 specific instructions */
5710 static void gen_dsa(DisasContext
*ctx
)
5713 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5717 static void gen_esa(DisasContext
*ctx
)
5720 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5724 static void gen_mfrom(DisasContext
*ctx
)
5726 #if defined(CONFIG_USER_ONLY)
5730 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5731 #endif /* defined(CONFIG_USER_ONLY) */
5734 /* 602 - 603 - G2 TLB management */
5737 static void gen_tlbld_6xx(DisasContext
*ctx
)
5739 #if defined(CONFIG_USER_ONLY)
5743 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5744 #endif /* defined(CONFIG_USER_ONLY) */
5748 static void gen_tlbli_6xx(DisasContext
*ctx
)
5750 #if defined(CONFIG_USER_ONLY)
5754 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5755 #endif /* defined(CONFIG_USER_ONLY) */
5758 /* 74xx TLB management */
5761 static void gen_tlbld_74xx(DisasContext
*ctx
)
5763 #if defined(CONFIG_USER_ONLY)
5767 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5768 #endif /* defined(CONFIG_USER_ONLY) */
5772 static void gen_tlbli_74xx(DisasContext
*ctx
)
5774 #if defined(CONFIG_USER_ONLY)
5778 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5779 #endif /* defined(CONFIG_USER_ONLY) */
5782 /* POWER instructions not in PowerPC 601 */
5785 static void gen_clf(DisasContext
*ctx
)
5787 /* Cache line flush: implemented as no-op */
5791 static void gen_cli(DisasContext
*ctx
)
5793 #if defined(CONFIG_USER_ONLY)
5796 /* Cache line invalidate: privileged and treated as no-op */
5798 #endif /* defined(CONFIG_USER_ONLY) */
5802 static void gen_dclst(DisasContext
*ctx
)
5804 /* Data cache line store: treated as no-op */
5807 static void gen_mfsri(DisasContext
*ctx
)
5809 #if defined(CONFIG_USER_ONLY)
5812 int ra
= rA(ctx
->opcode
);
5813 int rd
= rD(ctx
->opcode
);
5817 t0
= tcg_temp_new();
5818 gen_addr_reg_index(ctx
, t0
);
5819 tcg_gen_shri_tl(t0
, t0
, 28);
5820 tcg_gen_andi_tl(t0
, t0
, 0xF);
5821 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5823 if (ra
!= 0 && ra
!= rd
)
5824 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5825 #endif /* defined(CONFIG_USER_ONLY) */
5828 static void gen_rac(DisasContext
*ctx
)
5830 #if defined(CONFIG_USER_ONLY)
5836 t0
= tcg_temp_new();
5837 gen_addr_reg_index(ctx
, t0
);
5838 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5840 #endif /* defined(CONFIG_USER_ONLY) */
5843 static void gen_rfsvc(DisasContext
*ctx
)
5845 #if defined(CONFIG_USER_ONLY)
5850 gen_helper_rfsvc(cpu_env
);
5851 gen_sync_exception(ctx
);
5852 #endif /* defined(CONFIG_USER_ONLY) */
5855 /* svc is not implemented for now */
5857 /* POWER2 specific instructions */
5858 /* Quad manipulation (load/store two floats at a time) */
5861 static void gen_lfq(DisasContext
*ctx
)
5863 int rd
= rD(ctx
->opcode
);
5865 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5866 t0
= tcg_temp_new();
5867 gen_addr_imm_index(ctx
, t0
, 0);
5868 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5869 gen_addr_add(ctx
, t0
, t0
, 8);
5870 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5875 static void gen_lfqu(DisasContext
*ctx
)
5877 int ra
= rA(ctx
->opcode
);
5878 int rd
= rD(ctx
->opcode
);
5880 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5881 t0
= tcg_temp_new();
5882 t1
= tcg_temp_new();
5883 gen_addr_imm_index(ctx
, t0
, 0);
5884 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5885 gen_addr_add(ctx
, t1
, t0
, 8);
5886 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5888 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5894 static void gen_lfqux(DisasContext
*ctx
)
5896 int ra
= rA(ctx
->opcode
);
5897 int rd
= rD(ctx
->opcode
);
5898 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5900 t0
= tcg_temp_new();
5901 gen_addr_reg_index(ctx
, t0
);
5902 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5903 t1
= tcg_temp_new();
5904 gen_addr_add(ctx
, t1
, t0
, 8);
5905 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5908 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5913 static void gen_lfqx(DisasContext
*ctx
)
5915 int rd
= rD(ctx
->opcode
);
5917 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5918 t0
= tcg_temp_new();
5919 gen_addr_reg_index(ctx
, t0
);
5920 gen_qemu_ld64(ctx
, cpu_fpr
[rd
], t0
);
5921 gen_addr_add(ctx
, t0
, t0
, 8);
5922 gen_qemu_ld64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5927 static void gen_stfq(DisasContext
*ctx
)
5929 int rd
= rD(ctx
->opcode
);
5931 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5932 t0
= tcg_temp_new();
5933 gen_addr_imm_index(ctx
, t0
, 0);
5934 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5935 gen_addr_add(ctx
, t0
, t0
, 8);
5936 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5941 static void gen_stfqu(DisasContext
*ctx
)
5943 int ra
= rA(ctx
->opcode
);
5944 int rd
= rD(ctx
->opcode
);
5946 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5947 t0
= tcg_temp_new();
5948 gen_addr_imm_index(ctx
, t0
, 0);
5949 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5950 t1
= tcg_temp_new();
5951 gen_addr_add(ctx
, t1
, t0
, 8);
5952 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5955 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5960 static void gen_stfqux(DisasContext
*ctx
)
5962 int ra
= rA(ctx
->opcode
);
5963 int rd
= rD(ctx
->opcode
);
5965 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5966 t0
= tcg_temp_new();
5967 gen_addr_reg_index(ctx
, t0
);
5968 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5969 t1
= tcg_temp_new();
5970 gen_addr_add(ctx
, t1
, t0
, 8);
5971 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t1
);
5974 tcg_gen_mov_tl(cpu_gpr
[ra
], t0
);
5979 static void gen_stfqx(DisasContext
*ctx
)
5981 int rd
= rD(ctx
->opcode
);
5983 gen_set_access_type(ctx
, ACCESS_FLOAT
);
5984 t0
= tcg_temp_new();
5985 gen_addr_reg_index(ctx
, t0
);
5986 gen_qemu_st64(ctx
, cpu_fpr
[rd
], t0
);
5987 gen_addr_add(ctx
, t0
, t0
, 8);
5988 gen_qemu_st64(ctx
, cpu_fpr
[(rd
+ 1) % 32], t0
);
5992 /* BookE specific instructions */
5994 /* XXX: not implemented on 440 ? */
5995 static void gen_mfapidi(DisasContext
*ctx
)
5998 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6001 /* XXX: not implemented on 440 ? */
6002 static void gen_tlbiva(DisasContext
*ctx
)
6004 #if defined(CONFIG_USER_ONLY)
6010 t0
= tcg_temp_new();
6011 gen_addr_reg_index(ctx
, t0
);
6012 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6014 #endif /* defined(CONFIG_USER_ONLY) */
6017 /* All 405 MAC instructions are translated here */
6018 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
6019 int ra
, int rb
, int rt
, int Rc
)
6023 t0
= tcg_temp_local_new();
6024 t1
= tcg_temp_local_new();
6026 switch (opc3
& 0x0D) {
6028 /* macchw - macchw. - macchwo - macchwo. */
6029 /* macchws - macchws. - macchwso - macchwso. */
6030 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6031 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6032 /* mulchw - mulchw. */
6033 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
6034 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
6035 tcg_gen_ext16s_tl(t1
, t1
);
6038 /* macchwu - macchwu. - macchwuo - macchwuo. */
6039 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6040 /* mulchwu - mulchwu. */
6041 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6042 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6043 tcg_gen_ext16u_tl(t1
, t1
);
6046 /* machhw - machhw. - machhwo - machhwo. */
6047 /* machhws - machhws. - machhwso - machhwso. */
6048 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6049 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6050 /* mulhhw - mulhhw. */
6051 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
6052 tcg_gen_ext16s_tl(t0
, t0
);
6053 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
6054 tcg_gen_ext16s_tl(t1
, t1
);
6057 /* machhwu - machhwu. - machhwuo - machhwuo. */
6058 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6059 /* mulhhwu - mulhhwu. */
6060 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
6061 tcg_gen_ext16u_tl(t0
, t0
);
6062 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
6063 tcg_gen_ext16u_tl(t1
, t1
);
6066 /* maclhw - maclhw. - maclhwo - maclhwo. */
6067 /* maclhws - maclhws. - maclhwso - maclhwso. */
6068 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6069 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6070 /* mullhw - mullhw. */
6071 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
6072 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
6075 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6076 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6077 /* mullhwu - mullhwu. */
6078 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
6079 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
6083 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6084 tcg_gen_mul_tl(t1
, t0
, t1
);
6086 /* nmultiply-and-accumulate (0x0E) */
6087 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
6089 /* multiply-and-accumulate (0x0C) */
6090 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
6094 /* Check overflow and/or saturate */
6095 TCGLabel
*l1
= gen_new_label();
6098 /* Start with XER OV disabled, the most likely case */
6099 tcg_gen_movi_tl(cpu_ov
, 0);
6103 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
6104 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
6105 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
6106 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
6109 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
6110 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
6114 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
6117 tcg_gen_movi_tl(t0
, UINT32_MAX
);
6121 /* Check overflow */
6122 tcg_gen_movi_tl(cpu_ov
, 1);
6123 tcg_gen_movi_tl(cpu_so
, 1);
6126 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
6129 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
6133 if (unlikely(Rc
) != 0) {
6135 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
6139 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6140 static void glue(gen_, name)(DisasContext *ctx) \
6142 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6143 rD(ctx->opcode), Rc(ctx->opcode)); \
6146 /* macchw - macchw. */
6147 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
6148 /* macchwo - macchwo. */
6149 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
6150 /* macchws - macchws. */
6151 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
6152 /* macchwso - macchwso. */
6153 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
6154 /* macchwsu - macchwsu. */
6155 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
6156 /* macchwsuo - macchwsuo. */
6157 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
6158 /* macchwu - macchwu. */
6159 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
6160 /* macchwuo - macchwuo. */
6161 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
6162 /* machhw - machhw. */
6163 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
6164 /* machhwo - machhwo. */
6165 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
6166 /* machhws - machhws. */
6167 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
6168 /* machhwso - machhwso. */
6169 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
6170 /* machhwsu - machhwsu. */
6171 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
6172 /* machhwsuo - machhwsuo. */
6173 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
6174 /* machhwu - machhwu. */
6175 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
6176 /* machhwuo - machhwuo. */
6177 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
6178 /* maclhw - maclhw. */
6179 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
6180 /* maclhwo - maclhwo. */
6181 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
6182 /* maclhws - maclhws. */
6183 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
6184 /* maclhwso - maclhwso. */
6185 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
6186 /* maclhwu - maclhwu. */
6187 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
6188 /* maclhwuo - maclhwuo. */
6189 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
6190 /* maclhwsu - maclhwsu. */
6191 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
6192 /* maclhwsuo - maclhwsuo. */
6193 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6194 /* nmacchw - nmacchw. */
6195 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6196 /* nmacchwo - nmacchwo. */
6197 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6198 /* nmacchws - nmacchws. */
6199 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6200 /* nmacchwso - nmacchwso. */
6201 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6202 /* nmachhw - nmachhw. */
6203 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6204 /* nmachhwo - nmachhwo. */
6205 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6206 /* nmachhws - nmachhws. */
6207 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6208 /* nmachhwso - nmachhwso. */
6209 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6210 /* nmaclhw - nmaclhw. */
6211 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6212 /* nmaclhwo - nmaclhwo. */
6213 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6214 /* nmaclhws - nmaclhws. */
6215 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6216 /* nmaclhwso - nmaclhwso. */
6217 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6219 /* mulchw - mulchw. */
6220 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6221 /* mulchwu - mulchwu. */
6222 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6223 /* mulhhw - mulhhw. */
6224 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6225 /* mulhhwu - mulhhwu. */
6226 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6227 /* mullhw - mullhw. */
6228 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6229 /* mullhwu - mullhwu. */
6230 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6233 static void gen_mfdcr(DisasContext
*ctx
)
6235 #if defined(CONFIG_USER_ONLY)
6241 /* NIP cannot be restored if the memory exception comes from an helper */
6242 gen_update_nip(ctx
, ctx
->nip
- 4);
6243 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6244 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6245 tcg_temp_free(dcrn
);
6246 #endif /* defined(CONFIG_USER_ONLY) */
6250 static void gen_mtdcr(DisasContext
*ctx
)
6252 #if defined(CONFIG_USER_ONLY)
6258 /* NIP cannot be restored if the memory exception comes from an helper */
6259 gen_update_nip(ctx
, ctx
->nip
- 4);
6260 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6261 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6262 tcg_temp_free(dcrn
);
6263 #endif /* defined(CONFIG_USER_ONLY) */
6267 /* XXX: not implemented on 440 ? */
6268 static void gen_mfdcrx(DisasContext
*ctx
)
6270 #if defined(CONFIG_USER_ONLY)
6274 /* NIP cannot be restored if the memory exception comes from an helper */
6275 gen_update_nip(ctx
, ctx
->nip
- 4);
6276 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6277 cpu_gpr
[rA(ctx
->opcode
)]);
6278 /* Note: Rc update flag set leads to undefined state of Rc0 */
6279 #endif /* defined(CONFIG_USER_ONLY) */
6283 /* XXX: not implemented on 440 ? */
6284 static void gen_mtdcrx(DisasContext
*ctx
)
6286 #if defined(CONFIG_USER_ONLY)
6290 /* NIP cannot be restored if the memory exception comes from an helper */
6291 gen_update_nip(ctx
, ctx
->nip
- 4);
6292 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6293 cpu_gpr
[rS(ctx
->opcode
)]);
6294 /* Note: Rc update flag set leads to undefined state of Rc0 */
6295 #endif /* defined(CONFIG_USER_ONLY) */
6298 /* mfdcrux (PPC 460) : user-mode access to DCR */
6299 static void gen_mfdcrux(DisasContext
*ctx
)
6301 /* NIP cannot be restored if the memory exception comes from an helper */
6302 gen_update_nip(ctx
, ctx
->nip
- 4);
6303 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6304 cpu_gpr
[rA(ctx
->opcode
)]);
6305 /* Note: Rc update flag set leads to undefined state of Rc0 */
6308 /* mtdcrux (PPC 460) : user-mode access to DCR */
6309 static void gen_mtdcrux(DisasContext
*ctx
)
6311 /* NIP cannot be restored if the memory exception comes from an helper */
6312 gen_update_nip(ctx
, ctx
->nip
- 4);
6313 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6314 cpu_gpr
[rS(ctx
->opcode
)]);
6315 /* Note: Rc update flag set leads to undefined state of Rc0 */
6319 static void gen_dccci(DisasContext
*ctx
)
6322 /* interpreted as no-op */
6326 static void gen_dcread(DisasContext
*ctx
)
6328 #if defined(CONFIG_USER_ONLY)
6334 gen_set_access_type(ctx
, ACCESS_CACHE
);
6335 EA
= tcg_temp_new();
6336 gen_addr_reg_index(ctx
, EA
);
6337 val
= tcg_temp_new();
6338 gen_qemu_ld32u(ctx
, val
, EA
);
6340 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6342 #endif /* defined(CONFIG_USER_ONLY) */
6346 static void gen_icbt_40x(DisasContext
*ctx
)
6348 /* interpreted as no-op */
6349 /* XXX: specification say this is treated as a load by the MMU
6350 * but does not generate any exception
6355 static void gen_iccci(DisasContext
*ctx
)
6358 /* interpreted as no-op */
6362 static void gen_icread(DisasContext
*ctx
)
6365 /* interpreted as no-op */
6368 /* rfci (supervisor only) */
6369 static void gen_rfci_40x(DisasContext
*ctx
)
6371 #if defined(CONFIG_USER_ONLY)
6375 /* Restore CPU state */
6376 gen_helper_40x_rfci(cpu_env
);
6377 gen_sync_exception(ctx
);
6378 #endif /* defined(CONFIG_USER_ONLY) */
6381 static void gen_rfci(DisasContext
*ctx
)
6383 #if defined(CONFIG_USER_ONLY)
6387 /* Restore CPU state */
6388 gen_helper_rfci(cpu_env
);
6389 gen_sync_exception(ctx
);
6390 #endif /* defined(CONFIG_USER_ONLY) */
6393 /* BookE specific */
6395 /* XXX: not implemented on 440 ? */
6396 static void gen_rfdi(DisasContext
*ctx
)
6398 #if defined(CONFIG_USER_ONLY)
6402 /* Restore CPU state */
6403 gen_helper_rfdi(cpu_env
);
6404 gen_sync_exception(ctx
);
6405 #endif /* defined(CONFIG_USER_ONLY) */
6408 /* XXX: not implemented on 440 ? */
6409 static void gen_rfmci(DisasContext
*ctx
)
6411 #if defined(CONFIG_USER_ONLY)
6415 /* Restore CPU state */
6416 gen_helper_rfmci(cpu_env
);
6417 gen_sync_exception(ctx
);
6418 #endif /* defined(CONFIG_USER_ONLY) */
6421 /* TLB management - PowerPC 405 implementation */
6424 static void gen_tlbre_40x(DisasContext
*ctx
)
6426 #if defined(CONFIG_USER_ONLY)
6430 switch (rB(ctx
->opcode
)) {
6432 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6433 cpu_gpr
[rA(ctx
->opcode
)]);
6436 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6437 cpu_gpr
[rA(ctx
->opcode
)]);
6440 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6443 #endif /* defined(CONFIG_USER_ONLY) */
6446 /* tlbsx - tlbsx. */
6447 static void gen_tlbsx_40x(DisasContext
*ctx
)
6449 #if defined(CONFIG_USER_ONLY)
6455 t0
= tcg_temp_new();
6456 gen_addr_reg_index(ctx
, t0
);
6457 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6459 if (Rc(ctx
->opcode
)) {
6460 TCGLabel
*l1
= gen_new_label();
6461 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6462 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6463 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6466 #endif /* defined(CONFIG_USER_ONLY) */
6470 static void gen_tlbwe_40x(DisasContext
*ctx
)
6472 #if defined(CONFIG_USER_ONLY)
6477 switch (rB(ctx
->opcode
)) {
6479 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6480 cpu_gpr
[rS(ctx
->opcode
)]);
6483 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6484 cpu_gpr
[rS(ctx
->opcode
)]);
6487 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6490 #endif /* defined(CONFIG_USER_ONLY) */
6493 /* TLB management - PowerPC 440 implementation */
6496 static void gen_tlbre_440(DisasContext
*ctx
)
6498 #if defined(CONFIG_USER_ONLY)
6503 switch (rB(ctx
->opcode
)) {
6508 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6509 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6510 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6511 tcg_temp_free_i32(t0
);
6515 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6518 #endif /* defined(CONFIG_USER_ONLY) */
6521 /* tlbsx - tlbsx. */
6522 static void gen_tlbsx_440(DisasContext
*ctx
)
6524 #if defined(CONFIG_USER_ONLY)
6530 t0
= tcg_temp_new();
6531 gen_addr_reg_index(ctx
, t0
);
6532 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6534 if (Rc(ctx
->opcode
)) {
6535 TCGLabel
*l1
= gen_new_label();
6536 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6537 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6538 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6541 #endif /* defined(CONFIG_USER_ONLY) */
6545 static void gen_tlbwe_440(DisasContext
*ctx
)
6547 #if defined(CONFIG_USER_ONLY)
6551 switch (rB(ctx
->opcode
)) {
6556 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6557 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6558 cpu_gpr
[rS(ctx
->opcode
)]);
6559 tcg_temp_free_i32(t0
);
6563 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6566 #endif /* defined(CONFIG_USER_ONLY) */
6569 /* TLB management - PowerPC BookE 2.06 implementation */
6572 static void gen_tlbre_booke206(DisasContext
*ctx
)
6574 #if defined(CONFIG_USER_ONLY)
6578 gen_helper_booke206_tlbre(cpu_env
);
6579 #endif /* defined(CONFIG_USER_ONLY) */
6582 /* tlbsx - tlbsx. */
6583 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6585 #if defined(CONFIG_USER_ONLY)
6591 if (rA(ctx
->opcode
)) {
6592 t0
= tcg_temp_new();
6593 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6595 t0
= tcg_const_tl(0);
6598 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6599 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6601 #endif /* defined(CONFIG_USER_ONLY) */
6605 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6607 #if defined(CONFIG_USER_ONLY)
6611 gen_update_nip(ctx
, ctx
->nip
- 4);
6612 gen_helper_booke206_tlbwe(cpu_env
);
6613 #endif /* defined(CONFIG_USER_ONLY) */
6616 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6618 #if defined(CONFIG_USER_ONLY)
6624 t0
= tcg_temp_new();
6625 gen_addr_reg_index(ctx
, t0
);
6626 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6628 #endif /* defined(CONFIG_USER_ONLY) */
6631 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6633 #if defined(CONFIG_USER_ONLY)
6639 t0
= tcg_temp_new();
6640 gen_addr_reg_index(ctx
, t0
);
6642 switch((ctx
->opcode
>> 21) & 0x3) {
6644 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6647 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6650 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6653 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6658 #endif /* defined(CONFIG_USER_ONLY) */
6663 static void gen_wrtee(DisasContext
*ctx
)
6665 #if defined(CONFIG_USER_ONLY)
6671 t0
= tcg_temp_new();
6672 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6673 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6674 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6676 /* Stop translation to have a chance to raise an exception
6677 * if we just set msr_ee to 1
6679 gen_stop_exception(ctx
);
6680 #endif /* defined(CONFIG_USER_ONLY) */
6684 static void gen_wrteei(DisasContext
*ctx
)
6686 #if defined(CONFIG_USER_ONLY)
6690 if (ctx
->opcode
& 0x00008000) {
6691 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6692 /* Stop translation to have a chance to raise an exception */
6693 gen_stop_exception(ctx
);
6695 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6697 #endif /* defined(CONFIG_USER_ONLY) */
6700 /* PowerPC 440 specific instructions */
6703 static void gen_dlmzb(DisasContext
*ctx
)
6705 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6706 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6707 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6708 tcg_temp_free_i32(t0
);
6711 /* mbar replaces eieio on 440 */
6712 static void gen_mbar(DisasContext
*ctx
)
6714 /* interpreted as no-op */
6717 /* msync replaces sync on 440 */
6718 static void gen_msync_4xx(DisasContext
*ctx
)
6720 /* interpreted as no-op */
6724 static void gen_icbt_440(DisasContext
*ctx
)
6726 /* interpreted as no-op */
6727 /* XXX: specification say this is treated as a load by the MMU
6728 * but does not generate any exception
6732 /* Embedded.Processor Control */
6734 static void gen_msgclr(DisasContext
*ctx
)
6736 #if defined(CONFIG_USER_ONLY)
6740 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6741 #endif /* defined(CONFIG_USER_ONLY) */
6744 static void gen_msgsnd(DisasContext
*ctx
)
6746 #if defined(CONFIG_USER_ONLY)
6750 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6751 #endif /* defined(CONFIG_USER_ONLY) */
6754 /*** Altivec vector extension ***/
6755 /* Altivec registers moves */
6757 static inline TCGv_ptr
gen_avr_ptr(int reg
)
6759 TCGv_ptr r
= tcg_temp_new_ptr();
6760 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, avr
[reg
]));
6764 #define GEN_VR_LDX(name, opc2, opc3) \
6765 static void glue(gen_, name)(DisasContext *ctx) \
6768 if (unlikely(!ctx->altivec_enabled)) { \
6769 gen_exception(ctx, POWERPC_EXCP_VPU); \
6772 gen_set_access_type(ctx, ACCESS_INT); \
6773 EA = tcg_temp_new(); \
6774 gen_addr_reg_index(ctx, EA); \
6775 tcg_gen_andi_tl(EA, EA, ~0xf); \
6776 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6777 64-bit byteswap already. */ \
6778 if (ctx->le_mode) { \
6779 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6780 tcg_gen_addi_tl(EA, EA, 8); \
6781 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6783 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6784 tcg_gen_addi_tl(EA, EA, 8); \
6785 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6787 tcg_temp_free(EA); \
6790 #define GEN_VR_STX(name, opc2, opc3) \
6791 static void gen_st##name(DisasContext *ctx) \
6794 if (unlikely(!ctx->altivec_enabled)) { \
6795 gen_exception(ctx, POWERPC_EXCP_VPU); \
6798 gen_set_access_type(ctx, ACCESS_INT); \
6799 EA = tcg_temp_new(); \
6800 gen_addr_reg_index(ctx, EA); \
6801 tcg_gen_andi_tl(EA, EA, ~0xf); \
6802 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6803 64-bit byteswap already. */ \
6804 if (ctx->le_mode) { \
6805 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6806 tcg_gen_addi_tl(EA, EA, 8); \
6807 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6809 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6810 tcg_gen_addi_tl(EA, EA, 8); \
6811 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6813 tcg_temp_free(EA); \
6816 #define GEN_VR_LVE(name, opc2, opc3, size) \
6817 static void gen_lve##name(DisasContext *ctx) \
6821 if (unlikely(!ctx->altivec_enabled)) { \
6822 gen_exception(ctx, POWERPC_EXCP_VPU); \
6825 gen_set_access_type(ctx, ACCESS_INT); \
6826 EA = tcg_temp_new(); \
6827 gen_addr_reg_index(ctx, EA); \
6829 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6831 rs = gen_avr_ptr(rS(ctx->opcode)); \
6832 gen_helper_lve##name(cpu_env, rs, EA); \
6833 tcg_temp_free(EA); \
6834 tcg_temp_free_ptr(rs); \
6837 #define GEN_VR_STVE(name, opc2, opc3, size) \
6838 static void gen_stve##name(DisasContext *ctx) \
6842 if (unlikely(!ctx->altivec_enabled)) { \
6843 gen_exception(ctx, POWERPC_EXCP_VPU); \
6846 gen_set_access_type(ctx, ACCESS_INT); \
6847 EA = tcg_temp_new(); \
6848 gen_addr_reg_index(ctx, EA); \
6850 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6852 rs = gen_avr_ptr(rS(ctx->opcode)); \
6853 gen_helper_stve##name(cpu_env, rs, EA); \
6854 tcg_temp_free(EA); \
6855 tcg_temp_free_ptr(rs); \
6858 GEN_VR_LDX(lvx
, 0x07, 0x03);
6859 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6860 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
6862 GEN_VR_LVE(bx
, 0x07, 0x00, 1);
6863 GEN_VR_LVE(hx
, 0x07, 0x01, 2);
6864 GEN_VR_LVE(wx
, 0x07, 0x02, 4);
6866 GEN_VR_STX(svx
, 0x07, 0x07);
6867 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6868 GEN_VR_STX(svxl
, 0x07, 0x0F);
6870 GEN_VR_STVE(bx
, 0x07, 0x04, 1);
6871 GEN_VR_STVE(hx
, 0x07, 0x05, 2);
6872 GEN_VR_STVE(wx
, 0x07, 0x06, 4);
6874 static void gen_lvsl(DisasContext
*ctx
)
6878 if (unlikely(!ctx
->altivec_enabled
)) {
6879 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6882 EA
= tcg_temp_new();
6883 gen_addr_reg_index(ctx
, EA
);
6884 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6885 gen_helper_lvsl(rd
, EA
);
6887 tcg_temp_free_ptr(rd
);
6890 static void gen_lvsr(DisasContext
*ctx
)
6894 if (unlikely(!ctx
->altivec_enabled
)) {
6895 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6898 EA
= tcg_temp_new();
6899 gen_addr_reg_index(ctx
, EA
);
6900 rd
= gen_avr_ptr(rD(ctx
->opcode
));
6901 gen_helper_lvsr(rd
, EA
);
6903 tcg_temp_free_ptr(rd
);
6906 static void gen_mfvscr(DisasContext
*ctx
)
6909 if (unlikely(!ctx
->altivec_enabled
)) {
6910 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6913 tcg_gen_movi_i64(cpu_avrh
[rD(ctx
->opcode
)], 0);
6914 t
= tcg_temp_new_i32();
6915 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, vscr
));
6916 tcg_gen_extu_i32_i64(cpu_avrl
[rD(ctx
->opcode
)], t
);
6917 tcg_temp_free_i32(t
);
6920 static void gen_mtvscr(DisasContext
*ctx
)
6923 if (unlikely(!ctx
->altivec_enabled
)) {
6924 gen_exception(ctx
, POWERPC_EXCP_VPU
);
6927 p
= gen_avr_ptr(rB(ctx
->opcode
));
6928 gen_helper_mtvscr(cpu_env
, p
);
6929 tcg_temp_free_ptr(p
);
6932 /* Logical operations */
6933 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6934 static void glue(gen_, name)(DisasContext *ctx) \
6936 if (unlikely(!ctx->altivec_enabled)) { \
6937 gen_exception(ctx, POWERPC_EXCP_VPU); \
6940 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6941 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6944 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16);
6945 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17);
6946 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18);
6947 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19);
6948 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20);
6949 GEN_VX_LOGICAL(veqv
, tcg_gen_eqv_i64
, 2, 26);
6950 GEN_VX_LOGICAL(vnand
, tcg_gen_nand_i64
, 2, 22);
6951 GEN_VX_LOGICAL(vorc
, tcg_gen_orc_i64
, 2, 21);
6953 #define GEN_VXFORM(name, opc2, opc3) \
6954 static void glue(gen_, name)(DisasContext *ctx) \
6956 TCGv_ptr ra, rb, rd; \
6957 if (unlikely(!ctx->altivec_enabled)) { \
6958 gen_exception(ctx, POWERPC_EXCP_VPU); \
6961 ra = gen_avr_ptr(rA(ctx->opcode)); \
6962 rb = gen_avr_ptr(rB(ctx->opcode)); \
6963 rd = gen_avr_ptr(rD(ctx->opcode)); \
6964 gen_helper_##name (rd, ra, rb); \
6965 tcg_temp_free_ptr(ra); \
6966 tcg_temp_free_ptr(rb); \
6967 tcg_temp_free_ptr(rd); \
6970 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6971 static void glue(gen_, name)(DisasContext *ctx) \
6973 TCGv_ptr ra, rb, rd; \
6974 if (unlikely(!ctx->altivec_enabled)) { \
6975 gen_exception(ctx, POWERPC_EXCP_VPU); \
6978 ra = gen_avr_ptr(rA(ctx->opcode)); \
6979 rb = gen_avr_ptr(rB(ctx->opcode)); \
6980 rd = gen_avr_ptr(rD(ctx->opcode)); \
6981 gen_helper_##name(cpu_env, rd, ra, rb); \
6982 tcg_temp_free_ptr(ra); \
6983 tcg_temp_free_ptr(rb); \
6984 tcg_temp_free_ptr(rd); \
6987 #define GEN_VXFORM3(name, opc2, opc3) \
6988 static void glue(gen_, name)(DisasContext *ctx) \
6990 TCGv_ptr ra, rb, rc, rd; \
6991 if (unlikely(!ctx->altivec_enabled)) { \
6992 gen_exception(ctx, POWERPC_EXCP_VPU); \
6995 ra = gen_avr_ptr(rA(ctx->opcode)); \
6996 rb = gen_avr_ptr(rB(ctx->opcode)); \
6997 rc = gen_avr_ptr(rC(ctx->opcode)); \
6998 rd = gen_avr_ptr(rD(ctx->opcode)); \
6999 gen_helper_##name(rd, ra, rb, rc); \
7000 tcg_temp_free_ptr(ra); \
7001 tcg_temp_free_ptr(rb); \
7002 tcg_temp_free_ptr(rc); \
7003 tcg_temp_free_ptr(rd); \
7007 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7008 * an opcode bit. In general, these pairs come from different
7009 * versions of the ISA, so we must also support a pair of flags for
7012 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7013 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7015 if ((Rc(ctx->opcode) == 0) && \
7016 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7018 } else if ((Rc(ctx->opcode) == 1) && \
7019 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7022 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7026 GEN_VXFORM(vaddubm
, 0, 0);
7027 GEN_VXFORM(vadduhm
, 0, 1);
7028 GEN_VXFORM(vadduwm
, 0, 2);
7029 GEN_VXFORM(vaddudm
, 0, 3);
7030 GEN_VXFORM(vsububm
, 0, 16);
7031 GEN_VXFORM(vsubuhm
, 0, 17);
7032 GEN_VXFORM(vsubuwm
, 0, 18);
7033 GEN_VXFORM(vsubudm
, 0, 19);
7034 GEN_VXFORM(vmaxub
, 1, 0);
7035 GEN_VXFORM(vmaxuh
, 1, 1);
7036 GEN_VXFORM(vmaxuw
, 1, 2);
7037 GEN_VXFORM(vmaxud
, 1, 3);
7038 GEN_VXFORM(vmaxsb
, 1, 4);
7039 GEN_VXFORM(vmaxsh
, 1, 5);
7040 GEN_VXFORM(vmaxsw
, 1, 6);
7041 GEN_VXFORM(vmaxsd
, 1, 7);
7042 GEN_VXFORM(vminub
, 1, 8);
7043 GEN_VXFORM(vminuh
, 1, 9);
7044 GEN_VXFORM(vminuw
, 1, 10);
7045 GEN_VXFORM(vminud
, 1, 11);
7046 GEN_VXFORM(vminsb
, 1, 12);
7047 GEN_VXFORM(vminsh
, 1, 13);
7048 GEN_VXFORM(vminsw
, 1, 14);
7049 GEN_VXFORM(vminsd
, 1, 15);
7050 GEN_VXFORM(vavgub
, 1, 16);
7051 GEN_VXFORM(vavguh
, 1, 17);
7052 GEN_VXFORM(vavguw
, 1, 18);
7053 GEN_VXFORM(vavgsb
, 1, 20);
7054 GEN_VXFORM(vavgsh
, 1, 21);
7055 GEN_VXFORM(vavgsw
, 1, 22);
7056 GEN_VXFORM(vmrghb
, 6, 0);
7057 GEN_VXFORM(vmrghh
, 6, 1);
7058 GEN_VXFORM(vmrghw
, 6, 2);
7059 GEN_VXFORM(vmrglb
, 6, 4);
7060 GEN_VXFORM(vmrglh
, 6, 5);
7061 GEN_VXFORM(vmrglw
, 6, 6);
7063 static void gen_vmrgew(DisasContext
*ctx
)
7067 if (unlikely(!ctx
->altivec_enabled
)) {
7068 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7071 VT
= rD(ctx
->opcode
);
7072 VA
= rA(ctx
->opcode
);
7073 VB
= rB(ctx
->opcode
);
7074 tmp
= tcg_temp_new_i64();
7075 tcg_gen_shri_i64(tmp
, cpu_avrh
[VB
], 32);
7076 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VA
], tmp
, 0, 32);
7077 tcg_gen_shri_i64(tmp
, cpu_avrl
[VB
], 32);
7078 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VA
], tmp
, 0, 32);
7079 tcg_temp_free_i64(tmp
);
7082 static void gen_vmrgow(DisasContext
*ctx
)
7085 if (unlikely(!ctx
->altivec_enabled
)) {
7086 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7089 VT
= rD(ctx
->opcode
);
7090 VA
= rA(ctx
->opcode
);
7091 VB
= rB(ctx
->opcode
);
7093 tcg_gen_deposit_i64(cpu_avrh
[VT
], cpu_avrh
[VB
], cpu_avrh
[VA
], 32, 32);
7094 tcg_gen_deposit_i64(cpu_avrl
[VT
], cpu_avrl
[VB
], cpu_avrl
[VA
], 32, 32);
7097 GEN_VXFORM(vmuloub
, 4, 0);
7098 GEN_VXFORM(vmulouh
, 4, 1);
7099 GEN_VXFORM(vmulouw
, 4, 2);
7100 GEN_VXFORM(vmuluwm
, 4, 2);
7101 GEN_VXFORM_DUAL(vmulouw
, PPC_ALTIVEC
, PPC_NONE
,
7102 vmuluwm
, PPC_NONE
, PPC2_ALTIVEC_207
)
7103 GEN_VXFORM(vmulosb
, 4, 4);
7104 GEN_VXFORM(vmulosh
, 4, 5);
7105 GEN_VXFORM(vmulosw
, 4, 6);
7106 GEN_VXFORM(vmuleub
, 4, 8);
7107 GEN_VXFORM(vmuleuh
, 4, 9);
7108 GEN_VXFORM(vmuleuw
, 4, 10);
7109 GEN_VXFORM(vmulesb
, 4, 12);
7110 GEN_VXFORM(vmulesh
, 4, 13);
7111 GEN_VXFORM(vmulesw
, 4, 14);
7112 GEN_VXFORM(vslb
, 2, 4);
7113 GEN_VXFORM(vslh
, 2, 5);
7114 GEN_VXFORM(vslw
, 2, 6);
7115 GEN_VXFORM(vsld
, 2, 23);
7116 GEN_VXFORM(vsrb
, 2, 8);
7117 GEN_VXFORM(vsrh
, 2, 9);
7118 GEN_VXFORM(vsrw
, 2, 10);
7119 GEN_VXFORM(vsrd
, 2, 27);
7120 GEN_VXFORM(vsrab
, 2, 12);
7121 GEN_VXFORM(vsrah
, 2, 13);
7122 GEN_VXFORM(vsraw
, 2, 14);
7123 GEN_VXFORM(vsrad
, 2, 15);
7124 GEN_VXFORM(vslo
, 6, 16);
7125 GEN_VXFORM(vsro
, 6, 17);
7126 GEN_VXFORM(vaddcuw
, 0, 6);
7127 GEN_VXFORM(vsubcuw
, 0, 22);
7128 GEN_VXFORM_ENV(vaddubs
, 0, 8);
7129 GEN_VXFORM_ENV(vadduhs
, 0, 9);
7130 GEN_VXFORM_ENV(vadduws
, 0, 10);
7131 GEN_VXFORM_ENV(vaddsbs
, 0, 12);
7132 GEN_VXFORM_ENV(vaddshs
, 0, 13);
7133 GEN_VXFORM_ENV(vaddsws
, 0, 14);
7134 GEN_VXFORM_ENV(vsububs
, 0, 24);
7135 GEN_VXFORM_ENV(vsubuhs
, 0, 25);
7136 GEN_VXFORM_ENV(vsubuws
, 0, 26);
7137 GEN_VXFORM_ENV(vsubsbs
, 0, 28);
7138 GEN_VXFORM_ENV(vsubshs
, 0, 29);
7139 GEN_VXFORM_ENV(vsubsws
, 0, 30);
7140 GEN_VXFORM(vadduqm
, 0, 4);
7141 GEN_VXFORM(vaddcuq
, 0, 5);
7142 GEN_VXFORM3(vaddeuqm
, 30, 0);
7143 GEN_VXFORM3(vaddecuq
, 30, 0);
7144 GEN_VXFORM_DUAL(vaddeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7145 vaddecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7146 GEN_VXFORM(vsubuqm
, 0, 20);
7147 GEN_VXFORM(vsubcuq
, 0, 21);
7148 GEN_VXFORM3(vsubeuqm
, 31, 0);
7149 GEN_VXFORM3(vsubecuq
, 31, 0);
7150 GEN_VXFORM_DUAL(vsubeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7151 vsubecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
7152 GEN_VXFORM(vrlb
, 2, 0);
7153 GEN_VXFORM(vrlh
, 2, 1);
7154 GEN_VXFORM(vrlw
, 2, 2);
7155 GEN_VXFORM(vrld
, 2, 3);
7156 GEN_VXFORM(vsl
, 2, 7);
7157 GEN_VXFORM(vsr
, 2, 11);
7158 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
7159 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
7160 GEN_VXFORM_ENV(vpkudum
, 7, 17);
7161 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
7162 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
7163 GEN_VXFORM_ENV(vpkudus
, 7, 19);
7164 GEN_VXFORM_ENV(vpkshus
, 7, 4);
7165 GEN_VXFORM_ENV(vpkswus
, 7, 5);
7166 GEN_VXFORM_ENV(vpksdus
, 7, 21);
7167 GEN_VXFORM_ENV(vpkshss
, 7, 6);
7168 GEN_VXFORM_ENV(vpkswss
, 7, 7);
7169 GEN_VXFORM_ENV(vpksdss
, 7, 23);
7170 GEN_VXFORM(vpkpx
, 7, 12);
7171 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
7172 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
7173 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
7174 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
7175 GEN_VXFORM_ENV(vsumsws
, 4, 30);
7176 GEN_VXFORM_ENV(vaddfp
, 5, 0);
7177 GEN_VXFORM_ENV(vsubfp
, 5, 1);
7178 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
7179 GEN_VXFORM_ENV(vminfp
, 5, 17);
7181 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7182 static void glue(gen_, name)(DisasContext *ctx) \
7184 TCGv_ptr ra, rb, rd; \
7185 if (unlikely(!ctx->altivec_enabled)) { \
7186 gen_exception(ctx, POWERPC_EXCP_VPU); \
7189 ra = gen_avr_ptr(rA(ctx->opcode)); \
7190 rb = gen_avr_ptr(rB(ctx->opcode)); \
7191 rd = gen_avr_ptr(rD(ctx->opcode)); \
7192 gen_helper_##opname(cpu_env, rd, ra, rb); \
7193 tcg_temp_free_ptr(ra); \
7194 tcg_temp_free_ptr(rb); \
7195 tcg_temp_free_ptr(rd); \
7198 #define GEN_VXRFORM(name, opc2, opc3) \
7199 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7200 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7203 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7204 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7205 * come from different versions of the ISA, so we must also support a
7206 * pair of flags for each instruction.
7208 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7209 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7211 if ((Rc(ctx->opcode) == 0) && \
7212 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7213 if (Rc21(ctx->opcode) == 0) { \
7216 gen_##name0##_(ctx); \
7218 } else if ((Rc(ctx->opcode) == 1) && \
7219 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7220 if (Rc21(ctx->opcode) == 0) { \
7223 gen_##name1##_(ctx); \
7226 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7230 GEN_VXRFORM(vcmpequb
, 3, 0)
7231 GEN_VXRFORM(vcmpequh
, 3, 1)
7232 GEN_VXRFORM(vcmpequw
, 3, 2)
7233 GEN_VXRFORM(vcmpequd
, 3, 3)
7234 GEN_VXRFORM(vcmpgtsb
, 3, 12)
7235 GEN_VXRFORM(vcmpgtsh
, 3, 13)
7236 GEN_VXRFORM(vcmpgtsw
, 3, 14)
7237 GEN_VXRFORM(vcmpgtsd
, 3, 15)
7238 GEN_VXRFORM(vcmpgtub
, 3, 8)
7239 GEN_VXRFORM(vcmpgtuh
, 3, 9)
7240 GEN_VXRFORM(vcmpgtuw
, 3, 10)
7241 GEN_VXRFORM(vcmpgtud
, 3, 11)
7242 GEN_VXRFORM(vcmpeqfp
, 3, 3)
7243 GEN_VXRFORM(vcmpgefp
, 3, 7)
7244 GEN_VXRFORM(vcmpgtfp
, 3, 11)
7245 GEN_VXRFORM(vcmpbfp
, 3, 15)
7247 GEN_VXRFORM_DUAL(vcmpeqfp
, PPC_ALTIVEC
, PPC_NONE
, \
7248 vcmpequd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7249 GEN_VXRFORM_DUAL(vcmpbfp
, PPC_ALTIVEC
, PPC_NONE
, \
7250 vcmpgtsd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7251 GEN_VXRFORM_DUAL(vcmpgtfp
, PPC_ALTIVEC
, PPC_NONE
, \
7252 vcmpgtud
, PPC_NONE
, PPC2_ALTIVEC_207
)
7254 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7255 static void glue(gen_, name)(DisasContext *ctx) \
7259 if (unlikely(!ctx->altivec_enabled)) { \
7260 gen_exception(ctx, POWERPC_EXCP_VPU); \
7263 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7264 rd = gen_avr_ptr(rD(ctx->opcode)); \
7265 gen_helper_##name (rd, simm); \
7266 tcg_temp_free_i32(simm); \
7267 tcg_temp_free_ptr(rd); \
7270 GEN_VXFORM_SIMM(vspltisb
, 6, 12);
7271 GEN_VXFORM_SIMM(vspltish
, 6, 13);
7272 GEN_VXFORM_SIMM(vspltisw
, 6, 14);
7274 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7275 static void glue(gen_, name)(DisasContext *ctx) \
7278 if (unlikely(!ctx->altivec_enabled)) { \
7279 gen_exception(ctx, POWERPC_EXCP_VPU); \
7282 rb = gen_avr_ptr(rB(ctx->opcode)); \
7283 rd = gen_avr_ptr(rD(ctx->opcode)); \
7284 gen_helper_##name (rd, rb); \
7285 tcg_temp_free_ptr(rb); \
7286 tcg_temp_free_ptr(rd); \
7289 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7290 static void glue(gen_, name)(DisasContext *ctx) \
7294 if (unlikely(!ctx->altivec_enabled)) { \
7295 gen_exception(ctx, POWERPC_EXCP_VPU); \
7298 rb = gen_avr_ptr(rB(ctx->opcode)); \
7299 rd = gen_avr_ptr(rD(ctx->opcode)); \
7300 gen_helper_##name(cpu_env, rd, rb); \
7301 tcg_temp_free_ptr(rb); \
7302 tcg_temp_free_ptr(rd); \
7305 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
7306 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
7307 GEN_VXFORM_NOA(vupkhsw
, 7, 25);
7308 GEN_VXFORM_NOA(vupklsb
, 7, 10);
7309 GEN_VXFORM_NOA(vupklsh
, 7, 11);
7310 GEN_VXFORM_NOA(vupklsw
, 7, 27);
7311 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
7312 GEN_VXFORM_NOA(vupklpx
, 7, 15);
7313 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
7314 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
7315 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
7316 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
7317 GEN_VXFORM_NOA_ENV(vrfim
, 5, 11);
7318 GEN_VXFORM_NOA_ENV(vrfin
, 5, 8);
7319 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
7320 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 9);
7322 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7323 static void glue(gen_, name)(DisasContext *ctx) \
7327 if (unlikely(!ctx->altivec_enabled)) { \
7328 gen_exception(ctx, POWERPC_EXCP_VPU); \
7331 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7332 rd = gen_avr_ptr(rD(ctx->opcode)); \
7333 gen_helper_##name (rd, simm); \
7334 tcg_temp_free_i32(simm); \
7335 tcg_temp_free_ptr(rd); \
7338 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7339 static void glue(gen_, name)(DisasContext *ctx) \
7343 if (unlikely(!ctx->altivec_enabled)) { \
7344 gen_exception(ctx, POWERPC_EXCP_VPU); \
7347 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7348 rb = gen_avr_ptr(rB(ctx->opcode)); \
7349 rd = gen_avr_ptr(rD(ctx->opcode)); \
7350 gen_helper_##name (rd, rb, uimm); \
7351 tcg_temp_free_i32(uimm); \
7352 tcg_temp_free_ptr(rb); \
7353 tcg_temp_free_ptr(rd); \
7356 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7357 static void glue(gen_, name)(DisasContext *ctx) \
7362 if (unlikely(!ctx->altivec_enabled)) { \
7363 gen_exception(ctx, POWERPC_EXCP_VPU); \
7366 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7367 rb = gen_avr_ptr(rB(ctx->opcode)); \
7368 rd = gen_avr_ptr(rD(ctx->opcode)); \
7369 gen_helper_##name(cpu_env, rd, rb, uimm); \
7370 tcg_temp_free_i32(uimm); \
7371 tcg_temp_free_ptr(rb); \
7372 tcg_temp_free_ptr(rd); \
7375 GEN_VXFORM_UIMM(vspltb
, 6, 8);
7376 GEN_VXFORM_UIMM(vsplth
, 6, 9);
7377 GEN_VXFORM_UIMM(vspltw
, 6, 10);
7378 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
7379 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
7380 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
7381 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
7383 static void gen_vsldoi(DisasContext
*ctx
)
7385 TCGv_ptr ra
, rb
, rd
;
7387 if (unlikely(!ctx
->altivec_enabled
)) {
7388 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7391 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7392 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7393 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7394 sh
= tcg_const_i32(VSH(ctx
->opcode
));
7395 gen_helper_vsldoi (rd
, ra
, rb
, sh
);
7396 tcg_temp_free_ptr(ra
);
7397 tcg_temp_free_ptr(rb
);
7398 tcg_temp_free_ptr(rd
);
7399 tcg_temp_free_i32(sh
);
7402 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7403 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7405 TCGv_ptr ra, rb, rc, rd; \
7406 if (unlikely(!ctx->altivec_enabled)) { \
7407 gen_exception(ctx, POWERPC_EXCP_VPU); \
7410 ra = gen_avr_ptr(rA(ctx->opcode)); \
7411 rb = gen_avr_ptr(rB(ctx->opcode)); \
7412 rc = gen_avr_ptr(rC(ctx->opcode)); \
7413 rd = gen_avr_ptr(rD(ctx->opcode)); \
7414 if (Rc(ctx->opcode)) { \
7415 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7417 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7419 tcg_temp_free_ptr(ra); \
7420 tcg_temp_free_ptr(rb); \
7421 tcg_temp_free_ptr(rc); \
7422 tcg_temp_free_ptr(rd); \
7425 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
7427 static void gen_vmladduhm(DisasContext
*ctx
)
7429 TCGv_ptr ra
, rb
, rc
, rd
;
7430 if (unlikely(!ctx
->altivec_enabled
)) {
7431 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7434 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7435 rb
= gen_avr_ptr(rB(ctx
->opcode
));
7436 rc
= gen_avr_ptr(rC(ctx
->opcode
));
7437 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7438 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
7439 tcg_temp_free_ptr(ra
);
7440 tcg_temp_free_ptr(rb
);
7441 tcg_temp_free_ptr(rc
);
7442 tcg_temp_free_ptr(rd
);
7445 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
7446 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
7447 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
7448 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
7449 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
7451 GEN_VXFORM_NOA(vclzb
, 1, 28)
7452 GEN_VXFORM_NOA(vclzh
, 1, 29)
7453 GEN_VXFORM_NOA(vclzw
, 1, 30)
7454 GEN_VXFORM_NOA(vclzd
, 1, 31)
7455 GEN_VXFORM_NOA(vpopcntb
, 1, 28)
7456 GEN_VXFORM_NOA(vpopcnth
, 1, 29)
7457 GEN_VXFORM_NOA(vpopcntw
, 1, 30)
7458 GEN_VXFORM_NOA(vpopcntd
, 1, 31)
7459 GEN_VXFORM_DUAL(vclzb
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7460 vpopcntb
, PPC_NONE
, PPC2_ALTIVEC_207
)
7461 GEN_VXFORM_DUAL(vclzh
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7462 vpopcnth
, PPC_NONE
, PPC2_ALTIVEC_207
)
7463 GEN_VXFORM_DUAL(vclzw
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7464 vpopcntw
, PPC_NONE
, PPC2_ALTIVEC_207
)
7465 GEN_VXFORM_DUAL(vclzd
, PPC_NONE
, PPC2_ALTIVEC_207
, \
7466 vpopcntd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7467 GEN_VXFORM(vbpermq
, 6, 21);
7468 GEN_VXFORM_NOA(vgbbd
, 6, 20);
7469 GEN_VXFORM(vpmsumb
, 4, 16)
7470 GEN_VXFORM(vpmsumh
, 4, 17)
7471 GEN_VXFORM(vpmsumw
, 4, 18)
7472 GEN_VXFORM(vpmsumd
, 4, 19)
7474 #define GEN_BCD(op) \
7475 static void gen_##op(DisasContext *ctx) \
7477 TCGv_ptr ra, rb, rd; \
7480 if (unlikely(!ctx->altivec_enabled)) { \
7481 gen_exception(ctx, POWERPC_EXCP_VPU); \
7485 ra = gen_avr_ptr(rA(ctx->opcode)); \
7486 rb = gen_avr_ptr(rB(ctx->opcode)); \
7487 rd = gen_avr_ptr(rD(ctx->opcode)); \
7489 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7491 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7493 tcg_temp_free_ptr(ra); \
7494 tcg_temp_free_ptr(rb); \
7495 tcg_temp_free_ptr(rd); \
7496 tcg_temp_free_i32(ps); \
7502 GEN_VXFORM_DUAL(vsububm
, PPC_ALTIVEC
, PPC_NONE
, \
7503 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7504 GEN_VXFORM_DUAL(vsububs
, PPC_ALTIVEC
, PPC_NONE
, \
7505 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
7506 GEN_VXFORM_DUAL(vsubuhm
, PPC_ALTIVEC
, PPC_NONE
, \
7507 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7508 GEN_VXFORM_DUAL(vsubuhs
, PPC_ALTIVEC
, PPC_NONE
, \
7509 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
7511 static void gen_vsbox(DisasContext
*ctx
)
7514 if (unlikely(!ctx
->altivec_enabled
)) {
7515 gen_exception(ctx
, POWERPC_EXCP_VPU
);
7518 ra
= gen_avr_ptr(rA(ctx
->opcode
));
7519 rd
= gen_avr_ptr(rD(ctx
->opcode
));
7520 gen_helper_vsbox(rd
, ra
);
7521 tcg_temp_free_ptr(ra
);
7522 tcg_temp_free_ptr(rd
);
7525 GEN_VXFORM(vcipher
, 4, 20)
7526 GEN_VXFORM(vcipherlast
, 4, 20)
7527 GEN_VXFORM(vncipher
, 4, 21)
7528 GEN_VXFORM(vncipherlast
, 4, 21)
7530 GEN_VXFORM_DUAL(vcipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7531 vcipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7532 GEN_VXFORM_DUAL(vncipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
7533 vncipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
7535 #define VSHASIGMA(op) \
7536 static void gen_##op(DisasContext *ctx) \
7540 if (unlikely(!ctx->altivec_enabled)) { \
7541 gen_exception(ctx, POWERPC_EXCP_VPU); \
7544 ra = gen_avr_ptr(rA(ctx->opcode)); \
7545 rd = gen_avr_ptr(rD(ctx->opcode)); \
7546 st_six = tcg_const_i32(rB(ctx->opcode)); \
7547 gen_helper_##op(rd, ra, st_six); \
7548 tcg_temp_free_ptr(ra); \
7549 tcg_temp_free_ptr(rd); \
7550 tcg_temp_free_i32(st_six); \
7553 VSHASIGMA(vshasigmaw
)
7554 VSHASIGMA(vshasigmad
)
7556 GEN_VXFORM3(vpermxor
, 22, 0xFF)
7557 GEN_VXFORM_DUAL(vsldoi
, PPC_ALTIVEC
, PPC_NONE
,
7558 vpermxor
, PPC_NONE
, PPC2_ALTIVEC_207
)
7560 /*** VSX extension ***/
7562 static inline TCGv_i64
cpu_vsrh(int n
)
7567 return cpu_avrh
[n
-32];
7571 static inline TCGv_i64
cpu_vsrl(int n
)
7576 return cpu_avrl
[n
-32];
7580 #define VSX_LOAD_SCALAR(name, operation) \
7581 static void gen_##name(DisasContext *ctx) \
7584 if (unlikely(!ctx->vsx_enabled)) { \
7585 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7588 gen_set_access_type(ctx, ACCESS_INT); \
7589 EA = tcg_temp_new(); \
7590 gen_addr_reg_index(ctx, EA); \
7591 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7592 /* NOTE: cpu_vsrl is undefined */ \
7593 tcg_temp_free(EA); \
7596 VSX_LOAD_SCALAR(lxsdx
, ld64
)
7597 VSX_LOAD_SCALAR(lxsiwax
, ld32s_i64
)
7598 VSX_LOAD_SCALAR(lxsiwzx
, ld32u_i64
)
7599 VSX_LOAD_SCALAR(lxsspx
, ld32fs
)
7601 static void gen_lxvd2x(DisasContext
*ctx
)
7604 if (unlikely(!ctx
->vsx_enabled
)) {
7605 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7608 gen_set_access_type(ctx
, ACCESS_INT
);
7609 EA
= tcg_temp_new();
7610 gen_addr_reg_index(ctx
, EA
);
7611 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7612 tcg_gen_addi_tl(EA
, EA
, 8);
7613 gen_qemu_ld64(ctx
, cpu_vsrl(xT(ctx
->opcode
)), EA
);
7617 static void gen_lxvdsx(DisasContext
*ctx
)
7620 if (unlikely(!ctx
->vsx_enabled
)) {
7621 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7624 gen_set_access_type(ctx
, ACCESS_INT
);
7625 EA
= tcg_temp_new();
7626 gen_addr_reg_index(ctx
, EA
);
7627 gen_qemu_ld64(ctx
, cpu_vsrh(xT(ctx
->opcode
)), EA
);
7628 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
7632 static void gen_lxvw4x(DisasContext
*ctx
)
7636 TCGv_i64 xth
= cpu_vsrh(xT(ctx
->opcode
));
7637 TCGv_i64 xtl
= cpu_vsrl(xT(ctx
->opcode
));
7638 if (unlikely(!ctx
->vsx_enabled
)) {
7639 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7642 gen_set_access_type(ctx
, ACCESS_INT
);
7643 EA
= tcg_temp_new();
7644 tmp
= tcg_temp_new_i64();
7646 gen_addr_reg_index(ctx
, EA
);
7647 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7648 tcg_gen_addi_tl(EA
, EA
, 4);
7649 gen_qemu_ld32u_i64(ctx
, xth
, EA
);
7650 tcg_gen_deposit_i64(xth
, xth
, tmp
, 32, 32);
7652 tcg_gen_addi_tl(EA
, EA
, 4);
7653 gen_qemu_ld32u_i64(ctx
, tmp
, EA
);
7654 tcg_gen_addi_tl(EA
, EA
, 4);
7655 gen_qemu_ld32u_i64(ctx
, xtl
, EA
);
7656 tcg_gen_deposit_i64(xtl
, xtl
, tmp
, 32, 32);
7659 tcg_temp_free_i64(tmp
);
7662 #define VSX_STORE_SCALAR(name, operation) \
7663 static void gen_##name(DisasContext *ctx) \
7666 if (unlikely(!ctx->vsx_enabled)) { \
7667 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7670 gen_set_access_type(ctx, ACCESS_INT); \
7671 EA = tcg_temp_new(); \
7672 gen_addr_reg_index(ctx, EA); \
7673 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7674 tcg_temp_free(EA); \
7677 VSX_STORE_SCALAR(stxsdx
, st64
)
7678 VSX_STORE_SCALAR(stxsiwx
, st32_i64
)
7679 VSX_STORE_SCALAR(stxsspx
, st32fs
)
7681 static void gen_stxvd2x(DisasContext
*ctx
)
7684 if (unlikely(!ctx
->vsx_enabled
)) {
7685 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7688 gen_set_access_type(ctx
, ACCESS_INT
);
7689 EA
= tcg_temp_new();
7690 gen_addr_reg_index(ctx
, EA
);
7691 gen_qemu_st64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7692 tcg_gen_addi_tl(EA
, EA
, 8);
7693 gen_qemu_st64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7697 static void gen_stxvw4x(DisasContext
*ctx
)
7701 if (unlikely(!ctx
->vsx_enabled
)) {
7702 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7705 gen_set_access_type(ctx
, ACCESS_INT
);
7706 EA
= tcg_temp_new();
7707 gen_addr_reg_index(ctx
, EA
);
7708 tmp
= tcg_temp_new_i64();
7710 tcg_gen_shri_i64(tmp
, cpu_vsrh(xS(ctx
->opcode
)), 32);
7711 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7712 tcg_gen_addi_tl(EA
, EA
, 4);
7713 gen_qemu_st32_i64(ctx
, cpu_vsrh(xS(ctx
->opcode
)), EA
);
7715 tcg_gen_shri_i64(tmp
, cpu_vsrl(xS(ctx
->opcode
)), 32);
7716 tcg_gen_addi_tl(EA
, EA
, 4);
7717 gen_qemu_st32_i64(ctx
, tmp
, EA
);
7718 tcg_gen_addi_tl(EA
, EA
, 4);
7719 gen_qemu_st32_i64(ctx
, cpu_vsrl(xS(ctx
->opcode
)), EA
);
7722 tcg_temp_free_i64(tmp
);
7725 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7726 static void gen_##name(DisasContext *ctx) \
7728 if (xS(ctx->opcode) < 32) { \
7729 if (unlikely(!ctx->fpu_enabled)) { \
7730 gen_exception(ctx, POWERPC_EXCP_FPU); \
7734 if (unlikely(!ctx->altivec_enabled)) { \
7735 gen_exception(ctx, POWERPC_EXCP_VPU); \
7739 TCGv_i64 tmp = tcg_temp_new_i64(); \
7740 tcg_gen_##tcgop1(tmp, source); \
7741 tcg_gen_##tcgop2(target, tmp); \
7742 tcg_temp_free_i64(tmp); \
7746 MV_VSRW(mfvsrwz
, ext32u_i64
, trunc_i64_tl
, cpu_gpr
[rA(ctx
->opcode
)], \
7747 cpu_vsrh(xS(ctx
->opcode
)))
7748 MV_VSRW(mtvsrwa
, extu_tl_i64
, ext32s_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7749 cpu_gpr
[rA(ctx
->opcode
)])
7750 MV_VSRW(mtvsrwz
, extu_tl_i64
, ext32u_i64
, cpu_vsrh(xT(ctx
->opcode
)), \
7751 cpu_gpr
[rA(ctx
->opcode
)])
7753 #if defined(TARGET_PPC64)
7754 #define MV_VSRD(name, target, source) \
7755 static void gen_##name(DisasContext *ctx) \
7757 if (xS(ctx->opcode) < 32) { \
7758 if (unlikely(!ctx->fpu_enabled)) { \
7759 gen_exception(ctx, POWERPC_EXCP_FPU); \
7763 if (unlikely(!ctx->altivec_enabled)) { \
7764 gen_exception(ctx, POWERPC_EXCP_VPU); \
7768 tcg_gen_mov_i64(target, source); \
7771 MV_VSRD(mfvsrd
, cpu_gpr
[rA(ctx
->opcode
)], cpu_vsrh(xS(ctx
->opcode
)))
7772 MV_VSRD(mtvsrd
, cpu_vsrh(xT(ctx
->opcode
)), cpu_gpr
[rA(ctx
->opcode
)])
7776 static void gen_xxpermdi(DisasContext
*ctx
)
7778 if (unlikely(!ctx
->vsx_enabled
)) {
7779 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
7783 if (unlikely((xT(ctx
->opcode
) == xA(ctx
->opcode
)) ||
7784 (xT(ctx
->opcode
) == xB(ctx
->opcode
)))) {
7787 xh
= tcg_temp_new_i64();
7788 xl
= tcg_temp_new_i64();
7790 if ((DM(ctx
->opcode
) & 2) == 0) {
7791 tcg_gen_mov_i64(xh
, cpu_vsrh(xA(ctx
->opcode
)));
7793 tcg_gen_mov_i64(xh
, cpu_vsrl(xA(ctx
->opcode
)));
7795 if ((DM(ctx
->opcode
) & 1) == 0) {
7796 tcg_gen_mov_i64(xl
, cpu_vsrh(xB(ctx
->opcode
)));
7798 tcg_gen_mov_i64(xl
, cpu_vsrl(xB(ctx
->opcode
)));
7801 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xh
);
7802 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xl
);
7804 tcg_temp_free_i64(xh
);
7805 tcg_temp_free_i64(xl
);
7807 if ((DM(ctx
->opcode
) & 2) == 0) {
7808 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrh(xA(ctx
->opcode
)));
7810 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), cpu_vsrl(xA(ctx
->opcode
)));
7812 if ((DM(ctx
->opcode
) & 1) == 0) {
7813 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xB(ctx
->opcode
)));
7815 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrl(xB(ctx
->opcode
)));
7824 #define SGN_MASK_DP 0x8000000000000000ull
7825 #define SGN_MASK_SP 0x8000000080000000ull
7827 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7828 static void glue(gen_, name)(DisasContext * ctx) \
7831 if (unlikely(!ctx->vsx_enabled)) { \
7832 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7835 xb = tcg_temp_new_i64(); \
7836 sgm = tcg_temp_new_i64(); \
7837 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7838 tcg_gen_movi_i64(sgm, sgn_mask); \
7841 tcg_gen_andc_i64(xb, xb, sgm); \
7845 tcg_gen_or_i64(xb, xb, sgm); \
7849 tcg_gen_xor_i64(xb, xb, sgm); \
7853 TCGv_i64 xa = tcg_temp_new_i64(); \
7854 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7855 tcg_gen_and_i64(xa, xa, sgm); \
7856 tcg_gen_andc_i64(xb, xb, sgm); \
7857 tcg_gen_or_i64(xb, xb, xa); \
7858 tcg_temp_free_i64(xa); \
7862 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7863 tcg_temp_free_i64(xb); \
7864 tcg_temp_free_i64(sgm); \
7867 VSX_SCALAR_MOVE(xsabsdp
, OP_ABS
, SGN_MASK_DP
)
7868 VSX_SCALAR_MOVE(xsnabsdp
, OP_NABS
, SGN_MASK_DP
)
7869 VSX_SCALAR_MOVE(xsnegdp
, OP_NEG
, SGN_MASK_DP
)
7870 VSX_SCALAR_MOVE(xscpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7872 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7873 static void glue(gen_, name)(DisasContext * ctx) \
7875 TCGv_i64 xbh, xbl, sgm; \
7876 if (unlikely(!ctx->vsx_enabled)) { \
7877 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7880 xbh = tcg_temp_new_i64(); \
7881 xbl = tcg_temp_new_i64(); \
7882 sgm = tcg_temp_new_i64(); \
7883 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7884 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7885 tcg_gen_movi_i64(sgm, sgn_mask); \
7888 tcg_gen_andc_i64(xbh, xbh, sgm); \
7889 tcg_gen_andc_i64(xbl, xbl, sgm); \
7893 tcg_gen_or_i64(xbh, xbh, sgm); \
7894 tcg_gen_or_i64(xbl, xbl, sgm); \
7898 tcg_gen_xor_i64(xbh, xbh, sgm); \
7899 tcg_gen_xor_i64(xbl, xbl, sgm); \
7903 TCGv_i64 xah = tcg_temp_new_i64(); \
7904 TCGv_i64 xal = tcg_temp_new_i64(); \
7905 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7906 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7907 tcg_gen_and_i64(xah, xah, sgm); \
7908 tcg_gen_and_i64(xal, xal, sgm); \
7909 tcg_gen_andc_i64(xbh, xbh, sgm); \
7910 tcg_gen_andc_i64(xbl, xbl, sgm); \
7911 tcg_gen_or_i64(xbh, xbh, xah); \
7912 tcg_gen_or_i64(xbl, xbl, xal); \
7913 tcg_temp_free_i64(xah); \
7914 tcg_temp_free_i64(xal); \
7918 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7919 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7920 tcg_temp_free_i64(xbh); \
7921 tcg_temp_free_i64(xbl); \
7922 tcg_temp_free_i64(sgm); \
7925 VSX_VECTOR_MOVE(xvabsdp
, OP_ABS
, SGN_MASK_DP
)
7926 VSX_VECTOR_MOVE(xvnabsdp
, OP_NABS
, SGN_MASK_DP
)
7927 VSX_VECTOR_MOVE(xvnegdp
, OP_NEG
, SGN_MASK_DP
)
7928 VSX_VECTOR_MOVE(xvcpsgndp
, OP_CPSGN
, SGN_MASK_DP
)
7929 VSX_VECTOR_MOVE(xvabssp
, OP_ABS
, SGN_MASK_SP
)
7930 VSX_VECTOR_MOVE(xvnabssp
, OP_NABS
, SGN_MASK_SP
)
7931 VSX_VECTOR_MOVE(xvnegsp
, OP_NEG
, SGN_MASK_SP
)
7932 VSX_VECTOR_MOVE(xvcpsgnsp
, OP_CPSGN
, SGN_MASK_SP
)
7934 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7935 static void gen_##name(DisasContext * ctx) \
7938 if (unlikely(!ctx->vsx_enabled)) { \
7939 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7942 /* NIP cannot be restored if the memory exception comes from an helper */ \
7943 gen_update_nip(ctx, ctx->nip - 4); \
7944 opc = tcg_const_i32(ctx->opcode); \
7945 gen_helper_##name(cpu_env, opc); \
7946 tcg_temp_free_i32(opc); \
7949 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7950 static void gen_##name(DisasContext * ctx) \
7952 if (unlikely(!ctx->vsx_enabled)) { \
7953 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7956 /* NIP cannot be restored if the exception comes */ \
7957 /* from a helper. */ \
7958 gen_update_nip(ctx, ctx->nip - 4); \
7960 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7961 cpu_vsrh(xB(ctx->opcode))); \
7964 GEN_VSX_HELPER_2(xsadddp
, 0x00, 0x04, 0, PPC2_VSX
)
7965 GEN_VSX_HELPER_2(xssubdp
, 0x00, 0x05, 0, PPC2_VSX
)
7966 GEN_VSX_HELPER_2(xsmuldp
, 0x00, 0x06, 0, PPC2_VSX
)
7967 GEN_VSX_HELPER_2(xsdivdp
, 0x00, 0x07, 0, PPC2_VSX
)
7968 GEN_VSX_HELPER_2(xsredp
, 0x14, 0x05, 0, PPC2_VSX
)
7969 GEN_VSX_HELPER_2(xssqrtdp
, 0x16, 0x04, 0, PPC2_VSX
)
7970 GEN_VSX_HELPER_2(xsrsqrtedp
, 0x14, 0x04, 0, PPC2_VSX
)
7971 GEN_VSX_HELPER_2(xstdivdp
, 0x14, 0x07, 0, PPC2_VSX
)
7972 GEN_VSX_HELPER_2(xstsqrtdp
, 0x14, 0x06, 0, PPC2_VSX
)
7973 GEN_VSX_HELPER_2(xsmaddadp
, 0x04, 0x04, 0, PPC2_VSX
)
7974 GEN_VSX_HELPER_2(xsmaddmdp
, 0x04, 0x05, 0, PPC2_VSX
)
7975 GEN_VSX_HELPER_2(xsmsubadp
, 0x04, 0x06, 0, PPC2_VSX
)
7976 GEN_VSX_HELPER_2(xsmsubmdp
, 0x04, 0x07, 0, PPC2_VSX
)
7977 GEN_VSX_HELPER_2(xsnmaddadp
, 0x04, 0x14, 0, PPC2_VSX
)
7978 GEN_VSX_HELPER_2(xsnmaddmdp
, 0x04, 0x15, 0, PPC2_VSX
)
7979 GEN_VSX_HELPER_2(xsnmsubadp
, 0x04, 0x16, 0, PPC2_VSX
)
7980 GEN_VSX_HELPER_2(xsnmsubmdp
, 0x04, 0x17, 0, PPC2_VSX
)
7981 GEN_VSX_HELPER_2(xscmpodp
, 0x0C, 0x05, 0, PPC2_VSX
)
7982 GEN_VSX_HELPER_2(xscmpudp
, 0x0C, 0x04, 0, PPC2_VSX
)
7983 GEN_VSX_HELPER_2(xsmaxdp
, 0x00, 0x14, 0, PPC2_VSX
)
7984 GEN_VSX_HELPER_2(xsmindp
, 0x00, 0x15, 0, PPC2_VSX
)
7985 GEN_VSX_HELPER_2(xscvdpsp
, 0x12, 0x10, 0, PPC2_VSX
)
7986 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn
, 0x16, 0x10, 0, PPC2_VSX207
)
7987 GEN_VSX_HELPER_2(xscvspdp
, 0x12, 0x14, 0, PPC2_VSX
)
7988 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn
, 0x16, 0x14, 0, PPC2_VSX207
)
7989 GEN_VSX_HELPER_2(xscvdpsxds
, 0x10, 0x15, 0, PPC2_VSX
)
7990 GEN_VSX_HELPER_2(xscvdpsxws
, 0x10, 0x05, 0, PPC2_VSX
)
7991 GEN_VSX_HELPER_2(xscvdpuxds
, 0x10, 0x14, 0, PPC2_VSX
)
7992 GEN_VSX_HELPER_2(xscvdpuxws
, 0x10, 0x04, 0, PPC2_VSX
)
7993 GEN_VSX_HELPER_2(xscvsxddp
, 0x10, 0x17, 0, PPC2_VSX
)
7994 GEN_VSX_HELPER_2(xscvuxddp
, 0x10, 0x16, 0, PPC2_VSX
)
7995 GEN_VSX_HELPER_2(xsrdpi
, 0x12, 0x04, 0, PPC2_VSX
)
7996 GEN_VSX_HELPER_2(xsrdpic
, 0x16, 0x06, 0, PPC2_VSX
)
7997 GEN_VSX_HELPER_2(xsrdpim
, 0x12, 0x07, 0, PPC2_VSX
)
7998 GEN_VSX_HELPER_2(xsrdpip
, 0x12, 0x06, 0, PPC2_VSX
)
7999 GEN_VSX_HELPER_2(xsrdpiz
, 0x12, 0x05, 0, PPC2_VSX
)
8000 GEN_VSX_HELPER_XT_XB_ENV(xsrsp
, 0x12, 0x11, 0, PPC2_VSX207
)
8002 GEN_VSX_HELPER_2(xsaddsp
, 0x00, 0x00, 0, PPC2_VSX207
)
8003 GEN_VSX_HELPER_2(xssubsp
, 0x00, 0x01, 0, PPC2_VSX207
)
8004 GEN_VSX_HELPER_2(xsmulsp
, 0x00, 0x02, 0, PPC2_VSX207
)
8005 GEN_VSX_HELPER_2(xsdivsp
, 0x00, 0x03, 0, PPC2_VSX207
)
8006 GEN_VSX_HELPER_2(xsresp
, 0x14, 0x01, 0, PPC2_VSX207
)
8007 GEN_VSX_HELPER_2(xssqrtsp
, 0x16, 0x00, 0, PPC2_VSX207
)
8008 GEN_VSX_HELPER_2(xsrsqrtesp
, 0x14, 0x00, 0, PPC2_VSX207
)
8009 GEN_VSX_HELPER_2(xsmaddasp
, 0x04, 0x00, 0, PPC2_VSX207
)
8010 GEN_VSX_HELPER_2(xsmaddmsp
, 0x04, 0x01, 0, PPC2_VSX207
)
8011 GEN_VSX_HELPER_2(xsmsubasp
, 0x04, 0x02, 0, PPC2_VSX207
)
8012 GEN_VSX_HELPER_2(xsmsubmsp
, 0x04, 0x03, 0, PPC2_VSX207
)
8013 GEN_VSX_HELPER_2(xsnmaddasp
, 0x04, 0x10, 0, PPC2_VSX207
)
8014 GEN_VSX_HELPER_2(xsnmaddmsp
, 0x04, 0x11, 0, PPC2_VSX207
)
8015 GEN_VSX_HELPER_2(xsnmsubasp
, 0x04, 0x12, 0, PPC2_VSX207
)
8016 GEN_VSX_HELPER_2(xsnmsubmsp
, 0x04, 0x13, 0, PPC2_VSX207
)
8017 GEN_VSX_HELPER_2(xscvsxdsp
, 0x10, 0x13, 0, PPC2_VSX207
)
8018 GEN_VSX_HELPER_2(xscvuxdsp
, 0x10, 0x12, 0, PPC2_VSX207
)
8020 GEN_VSX_HELPER_2(xvadddp
, 0x00, 0x0C, 0, PPC2_VSX
)
8021 GEN_VSX_HELPER_2(xvsubdp
, 0x00, 0x0D, 0, PPC2_VSX
)
8022 GEN_VSX_HELPER_2(xvmuldp
, 0x00, 0x0E, 0, PPC2_VSX
)
8023 GEN_VSX_HELPER_2(xvdivdp
, 0x00, 0x0F, 0, PPC2_VSX
)
8024 GEN_VSX_HELPER_2(xvredp
, 0x14, 0x0D, 0, PPC2_VSX
)
8025 GEN_VSX_HELPER_2(xvsqrtdp
, 0x16, 0x0C, 0, PPC2_VSX
)
8026 GEN_VSX_HELPER_2(xvrsqrtedp
, 0x14, 0x0C, 0, PPC2_VSX
)
8027 GEN_VSX_HELPER_2(xvtdivdp
, 0x14, 0x0F, 0, PPC2_VSX
)
8028 GEN_VSX_HELPER_2(xvtsqrtdp
, 0x14, 0x0E, 0, PPC2_VSX
)
8029 GEN_VSX_HELPER_2(xvmaddadp
, 0x04, 0x0C, 0, PPC2_VSX
)
8030 GEN_VSX_HELPER_2(xvmaddmdp
, 0x04, 0x0D, 0, PPC2_VSX
)
8031 GEN_VSX_HELPER_2(xvmsubadp
, 0x04, 0x0E, 0, PPC2_VSX
)
8032 GEN_VSX_HELPER_2(xvmsubmdp
, 0x04, 0x0F, 0, PPC2_VSX
)
8033 GEN_VSX_HELPER_2(xvnmaddadp
, 0x04, 0x1C, 0, PPC2_VSX
)
8034 GEN_VSX_HELPER_2(xvnmaddmdp
, 0x04, 0x1D, 0, PPC2_VSX
)
8035 GEN_VSX_HELPER_2(xvnmsubadp
, 0x04, 0x1E, 0, PPC2_VSX
)
8036 GEN_VSX_HELPER_2(xvnmsubmdp
, 0x04, 0x1F, 0, PPC2_VSX
)
8037 GEN_VSX_HELPER_2(xvmaxdp
, 0x00, 0x1C, 0, PPC2_VSX
)
8038 GEN_VSX_HELPER_2(xvmindp
, 0x00, 0x1D, 0, PPC2_VSX
)
8039 GEN_VSX_HELPER_2(xvcmpeqdp
, 0x0C, 0x0C, 0, PPC2_VSX
)
8040 GEN_VSX_HELPER_2(xvcmpgtdp
, 0x0C, 0x0D, 0, PPC2_VSX
)
8041 GEN_VSX_HELPER_2(xvcmpgedp
, 0x0C, 0x0E, 0, PPC2_VSX
)
8042 GEN_VSX_HELPER_2(xvcvdpsp
, 0x12, 0x18, 0, PPC2_VSX
)
8043 GEN_VSX_HELPER_2(xvcvdpsxds
, 0x10, 0x1D, 0, PPC2_VSX
)
8044 GEN_VSX_HELPER_2(xvcvdpsxws
, 0x10, 0x0D, 0, PPC2_VSX
)
8045 GEN_VSX_HELPER_2(xvcvdpuxds
, 0x10, 0x1C, 0, PPC2_VSX
)
8046 GEN_VSX_HELPER_2(xvcvdpuxws
, 0x10, 0x0C, 0, PPC2_VSX
)
8047 GEN_VSX_HELPER_2(xvcvsxddp
, 0x10, 0x1F, 0, PPC2_VSX
)
8048 GEN_VSX_HELPER_2(xvcvuxddp
, 0x10, 0x1E, 0, PPC2_VSX
)
8049 GEN_VSX_HELPER_2(xvcvsxwdp
, 0x10, 0x0F, 0, PPC2_VSX
)
8050 GEN_VSX_HELPER_2(xvcvuxwdp
, 0x10, 0x0E, 0, PPC2_VSX
)
8051 GEN_VSX_HELPER_2(xvrdpi
, 0x12, 0x0C, 0, PPC2_VSX
)
8052 GEN_VSX_HELPER_2(xvrdpic
, 0x16, 0x0E, 0, PPC2_VSX
)
8053 GEN_VSX_HELPER_2(xvrdpim
, 0x12, 0x0F, 0, PPC2_VSX
)
8054 GEN_VSX_HELPER_2(xvrdpip
, 0x12, 0x0E, 0, PPC2_VSX
)
8055 GEN_VSX_HELPER_2(xvrdpiz
, 0x12, 0x0D, 0, PPC2_VSX
)
8057 GEN_VSX_HELPER_2(xvaddsp
, 0x00, 0x08, 0, PPC2_VSX
)
8058 GEN_VSX_HELPER_2(xvsubsp
, 0x00, 0x09, 0, PPC2_VSX
)
8059 GEN_VSX_HELPER_2(xvmulsp
, 0x00, 0x0A, 0, PPC2_VSX
)
8060 GEN_VSX_HELPER_2(xvdivsp
, 0x00, 0x0B, 0, PPC2_VSX
)
8061 GEN_VSX_HELPER_2(xvresp
, 0x14, 0x09, 0, PPC2_VSX
)
8062 GEN_VSX_HELPER_2(xvsqrtsp
, 0x16, 0x08, 0, PPC2_VSX
)
8063 GEN_VSX_HELPER_2(xvrsqrtesp
, 0x14, 0x08, 0, PPC2_VSX
)
8064 GEN_VSX_HELPER_2(xvtdivsp
, 0x14, 0x0B, 0, PPC2_VSX
)
8065 GEN_VSX_HELPER_2(xvtsqrtsp
, 0x14, 0x0A, 0, PPC2_VSX
)
8066 GEN_VSX_HELPER_2(xvmaddasp
, 0x04, 0x08, 0, PPC2_VSX
)
8067 GEN_VSX_HELPER_2(xvmaddmsp
, 0x04, 0x09, 0, PPC2_VSX
)
8068 GEN_VSX_HELPER_2(xvmsubasp
, 0x04, 0x0A, 0, PPC2_VSX
)
8069 GEN_VSX_HELPER_2(xvmsubmsp
, 0x04, 0x0B, 0, PPC2_VSX
)
8070 GEN_VSX_HELPER_2(xvnmaddasp
, 0x04, 0x18, 0, PPC2_VSX
)
8071 GEN_VSX_HELPER_2(xvnmaddmsp
, 0x04, 0x19, 0, PPC2_VSX
)
8072 GEN_VSX_HELPER_2(xvnmsubasp
, 0x04, 0x1A, 0, PPC2_VSX
)
8073 GEN_VSX_HELPER_2(xvnmsubmsp
, 0x04, 0x1B, 0, PPC2_VSX
)
8074 GEN_VSX_HELPER_2(xvmaxsp
, 0x00, 0x18, 0, PPC2_VSX
)
8075 GEN_VSX_HELPER_2(xvminsp
, 0x00, 0x19, 0, PPC2_VSX
)
8076 GEN_VSX_HELPER_2(xvcmpeqsp
, 0x0C, 0x08, 0, PPC2_VSX
)
8077 GEN_VSX_HELPER_2(xvcmpgtsp
, 0x0C, 0x09, 0, PPC2_VSX
)
8078 GEN_VSX_HELPER_2(xvcmpgesp
, 0x0C, 0x0A, 0, PPC2_VSX
)
8079 GEN_VSX_HELPER_2(xvcvspdp
, 0x12, 0x1C, 0, PPC2_VSX
)
8080 GEN_VSX_HELPER_2(xvcvspsxds
, 0x10, 0x19, 0, PPC2_VSX
)
8081 GEN_VSX_HELPER_2(xvcvspsxws
, 0x10, 0x09, 0, PPC2_VSX
)
8082 GEN_VSX_HELPER_2(xvcvspuxds
, 0x10, 0x18, 0, PPC2_VSX
)
8083 GEN_VSX_HELPER_2(xvcvspuxws
, 0x10, 0x08, 0, PPC2_VSX
)
8084 GEN_VSX_HELPER_2(xvcvsxdsp
, 0x10, 0x1B, 0, PPC2_VSX
)
8085 GEN_VSX_HELPER_2(xvcvuxdsp
, 0x10, 0x1A, 0, PPC2_VSX
)
8086 GEN_VSX_HELPER_2(xvcvsxwsp
, 0x10, 0x0B, 0, PPC2_VSX
)
8087 GEN_VSX_HELPER_2(xvcvuxwsp
, 0x10, 0x0A, 0, PPC2_VSX
)
8088 GEN_VSX_HELPER_2(xvrspi
, 0x12, 0x08, 0, PPC2_VSX
)
8089 GEN_VSX_HELPER_2(xvrspic
, 0x16, 0x0A, 0, PPC2_VSX
)
8090 GEN_VSX_HELPER_2(xvrspim
, 0x12, 0x0B, 0, PPC2_VSX
)
8091 GEN_VSX_HELPER_2(xvrspip
, 0x12, 0x0A, 0, PPC2_VSX
)
8092 GEN_VSX_HELPER_2(xvrspiz
, 0x12, 0x09, 0, PPC2_VSX
)
8094 #define VSX_LOGICAL(name, tcg_op) \
8095 static void glue(gen_, name)(DisasContext * ctx) \
8097 if (unlikely(!ctx->vsx_enabled)) { \
8098 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8101 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8102 cpu_vsrh(xB(ctx->opcode))); \
8103 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8104 cpu_vsrl(xB(ctx->opcode))); \
8107 VSX_LOGICAL(xxland
, tcg_gen_and_i64
)
8108 VSX_LOGICAL(xxlandc
, tcg_gen_andc_i64
)
8109 VSX_LOGICAL(xxlor
, tcg_gen_or_i64
)
8110 VSX_LOGICAL(xxlxor
, tcg_gen_xor_i64
)
8111 VSX_LOGICAL(xxlnor
, tcg_gen_nor_i64
)
8112 VSX_LOGICAL(xxleqv
, tcg_gen_eqv_i64
)
8113 VSX_LOGICAL(xxlnand
, tcg_gen_nand_i64
)
8114 VSX_LOGICAL(xxlorc
, tcg_gen_orc_i64
)
8116 #define VSX_XXMRG(name, high) \
8117 static void glue(gen_, name)(DisasContext * ctx) \
8119 TCGv_i64 a0, a1, b0, b1; \
8120 if (unlikely(!ctx->vsx_enabled)) { \
8121 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8124 a0 = tcg_temp_new_i64(); \
8125 a1 = tcg_temp_new_i64(); \
8126 b0 = tcg_temp_new_i64(); \
8127 b1 = tcg_temp_new_i64(); \
8129 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8130 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8131 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8132 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8134 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8135 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8136 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8137 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8139 tcg_gen_shri_i64(a0, a0, 32); \
8140 tcg_gen_shri_i64(b0, b0, 32); \
8141 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8143 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8145 tcg_temp_free_i64(a0); \
8146 tcg_temp_free_i64(a1); \
8147 tcg_temp_free_i64(b0); \
8148 tcg_temp_free_i64(b1); \
8151 VSX_XXMRG(xxmrghw
, 1)
8152 VSX_XXMRG(xxmrglw
, 0)
8154 static void gen_xxsel(DisasContext
* ctx
)
8157 if (unlikely(!ctx
->vsx_enabled
)) {
8158 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8161 a
= tcg_temp_new_i64();
8162 b
= tcg_temp_new_i64();
8163 c
= tcg_temp_new_i64();
8165 tcg_gen_mov_i64(a
, cpu_vsrh(xA(ctx
->opcode
)));
8166 tcg_gen_mov_i64(b
, cpu_vsrh(xB(ctx
->opcode
)));
8167 tcg_gen_mov_i64(c
, cpu_vsrh(xC(ctx
->opcode
)));
8169 tcg_gen_and_i64(b
, b
, c
);
8170 tcg_gen_andc_i64(a
, a
, c
);
8171 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), a
, b
);
8173 tcg_gen_mov_i64(a
, cpu_vsrl(xA(ctx
->opcode
)));
8174 tcg_gen_mov_i64(b
, cpu_vsrl(xB(ctx
->opcode
)));
8175 tcg_gen_mov_i64(c
, cpu_vsrl(xC(ctx
->opcode
)));
8177 tcg_gen_and_i64(b
, b
, c
);
8178 tcg_gen_andc_i64(a
, a
, c
);
8179 tcg_gen_or_i64(cpu_vsrl(xT(ctx
->opcode
)), a
, b
);
8181 tcg_temp_free_i64(a
);
8182 tcg_temp_free_i64(b
);
8183 tcg_temp_free_i64(c
);
8186 static void gen_xxspltw(DisasContext
*ctx
)
8189 TCGv_i64 vsr
= (UIM(ctx
->opcode
) & 2) ?
8190 cpu_vsrl(xB(ctx
->opcode
)) :
8191 cpu_vsrh(xB(ctx
->opcode
));
8193 if (unlikely(!ctx
->vsx_enabled
)) {
8194 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8198 b
= tcg_temp_new_i64();
8199 b2
= tcg_temp_new_i64();
8201 if (UIM(ctx
->opcode
) & 1) {
8202 tcg_gen_ext32u_i64(b
, vsr
);
8204 tcg_gen_shri_i64(b
, vsr
, 32);
8207 tcg_gen_shli_i64(b2
, b
, 32);
8208 tcg_gen_or_i64(cpu_vsrh(xT(ctx
->opcode
)), b
, b2
);
8209 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), cpu_vsrh(xT(ctx
->opcode
)));
8211 tcg_temp_free_i64(b
);
8212 tcg_temp_free_i64(b2
);
8215 static void gen_xxsldwi(DisasContext
*ctx
)
8218 if (unlikely(!ctx
->vsx_enabled
)) {
8219 gen_exception(ctx
, POWERPC_EXCP_VSXU
);
8222 xth
= tcg_temp_new_i64();
8223 xtl
= tcg_temp_new_i64();
8225 switch (SHW(ctx
->opcode
)) {
8227 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8228 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8232 TCGv_i64 t0
= tcg_temp_new_i64();
8233 tcg_gen_mov_i64(xth
, cpu_vsrh(xA(ctx
->opcode
)));
8234 tcg_gen_shli_i64(xth
, xth
, 32);
8235 tcg_gen_mov_i64(t0
, cpu_vsrl(xA(ctx
->opcode
)));
8236 tcg_gen_shri_i64(t0
, t0
, 32);
8237 tcg_gen_or_i64(xth
, xth
, t0
);
8238 tcg_gen_mov_i64(xtl
, cpu_vsrl(xA(ctx
->opcode
)));
8239 tcg_gen_shli_i64(xtl
, xtl
, 32);
8240 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8241 tcg_gen_shri_i64(t0
, t0
, 32);
8242 tcg_gen_or_i64(xtl
, xtl
, t0
);
8243 tcg_temp_free_i64(t0
);
8247 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8248 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8252 TCGv_i64 t0
= tcg_temp_new_i64();
8253 tcg_gen_mov_i64(xth
, cpu_vsrl(xA(ctx
->opcode
)));
8254 tcg_gen_shli_i64(xth
, xth
, 32);
8255 tcg_gen_mov_i64(t0
, cpu_vsrh(xB(ctx
->opcode
)));
8256 tcg_gen_shri_i64(t0
, t0
, 32);
8257 tcg_gen_or_i64(xth
, xth
, t0
);
8258 tcg_gen_mov_i64(xtl
, cpu_vsrh(xB(ctx
->opcode
)));
8259 tcg_gen_shli_i64(xtl
, xtl
, 32);
8260 tcg_gen_mov_i64(t0
, cpu_vsrl(xB(ctx
->opcode
)));
8261 tcg_gen_shri_i64(t0
, t0
, 32);
8262 tcg_gen_or_i64(xtl
, xtl
, t0
);
8263 tcg_temp_free_i64(t0
);
8268 tcg_gen_mov_i64(cpu_vsrh(xT(ctx
->opcode
)), xth
);
8269 tcg_gen_mov_i64(cpu_vsrl(xT(ctx
->opcode
)), xtl
);
8271 tcg_temp_free_i64(xth
);
8272 tcg_temp_free_i64(xtl
);
8275 /*** Decimal Floating Point ***/
8277 static inline TCGv_ptr
gen_fprp_ptr(int reg
)
8279 TCGv_ptr r
= tcg_temp_new_ptr();
8280 tcg_gen_addi_ptr(r
, cpu_env
, offsetof(CPUPPCState
, fpr
[reg
]));
8284 #define GEN_DFP_T_A_B_Rc(name) \
8285 static void gen_##name(DisasContext *ctx) \
8287 TCGv_ptr rd, ra, rb; \
8288 if (unlikely(!ctx->fpu_enabled)) { \
8289 gen_exception(ctx, POWERPC_EXCP_FPU); \
8292 gen_update_nip(ctx, ctx->nip - 4); \
8293 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8294 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8295 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8296 gen_helper_##name(cpu_env, rd, ra, rb); \
8297 if (unlikely(Rc(ctx->opcode) != 0)) { \
8298 gen_set_cr1_from_fpscr(ctx); \
8300 tcg_temp_free_ptr(rd); \
8301 tcg_temp_free_ptr(ra); \
8302 tcg_temp_free_ptr(rb); \
8305 #define GEN_DFP_BF_A_B(name) \
8306 static void gen_##name(DisasContext *ctx) \
8309 if (unlikely(!ctx->fpu_enabled)) { \
8310 gen_exception(ctx, POWERPC_EXCP_FPU); \
8313 gen_update_nip(ctx, ctx->nip - 4); \
8314 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8315 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8316 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8318 tcg_temp_free_ptr(ra); \
8319 tcg_temp_free_ptr(rb); \
8322 #define GEN_DFP_BF_A_DCM(name) \
8323 static void gen_##name(DisasContext *ctx) \
8327 if (unlikely(!ctx->fpu_enabled)) { \
8328 gen_exception(ctx, POWERPC_EXCP_FPU); \
8331 gen_update_nip(ctx, ctx->nip - 4); \
8332 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8333 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8334 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8335 cpu_env, ra, dcm); \
8336 tcg_temp_free_ptr(ra); \
8337 tcg_temp_free_i32(dcm); \
8340 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8341 static void gen_##name(DisasContext *ctx) \
8344 TCGv_i32 u32_1, u32_2; \
8345 if (unlikely(!ctx->fpu_enabled)) { \
8346 gen_exception(ctx, POWERPC_EXCP_FPU); \
8349 gen_update_nip(ctx, ctx->nip - 4); \
8350 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8351 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8352 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8353 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8354 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8355 if (unlikely(Rc(ctx->opcode) != 0)) { \
8356 gen_set_cr1_from_fpscr(ctx); \
8358 tcg_temp_free_ptr(rt); \
8359 tcg_temp_free_ptr(rb); \
8360 tcg_temp_free_i32(u32_1); \
8361 tcg_temp_free_i32(u32_2); \
8364 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8365 static void gen_##name(DisasContext *ctx) \
8367 TCGv_ptr rt, ra, rb; \
8369 if (unlikely(!ctx->fpu_enabled)) { \
8370 gen_exception(ctx, POWERPC_EXCP_FPU); \
8373 gen_update_nip(ctx, ctx->nip - 4); \
8374 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8375 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8376 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8377 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8378 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8379 if (unlikely(Rc(ctx->opcode) != 0)) { \
8380 gen_set_cr1_from_fpscr(ctx); \
8382 tcg_temp_free_ptr(rt); \
8383 tcg_temp_free_ptr(rb); \
8384 tcg_temp_free_ptr(ra); \
8385 tcg_temp_free_i32(i32); \
8388 #define GEN_DFP_T_B_Rc(name) \
8389 static void gen_##name(DisasContext *ctx) \
8392 if (unlikely(!ctx->fpu_enabled)) { \
8393 gen_exception(ctx, POWERPC_EXCP_FPU); \
8396 gen_update_nip(ctx, ctx->nip - 4); \
8397 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8398 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8399 gen_helper_##name(cpu_env, rt, rb); \
8400 if (unlikely(Rc(ctx->opcode) != 0)) { \
8401 gen_set_cr1_from_fpscr(ctx); \
8403 tcg_temp_free_ptr(rt); \
8404 tcg_temp_free_ptr(rb); \
8407 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8408 static void gen_##name(DisasContext *ctx) \
8412 if (unlikely(!ctx->fpu_enabled)) { \
8413 gen_exception(ctx, POWERPC_EXCP_FPU); \
8416 gen_update_nip(ctx, ctx->nip - 4); \
8417 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8418 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8419 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8420 gen_helper_##name(cpu_env, rt, rs, i32); \
8421 if (unlikely(Rc(ctx->opcode) != 0)) { \
8422 gen_set_cr1_from_fpscr(ctx); \
8424 tcg_temp_free_ptr(rt); \
8425 tcg_temp_free_ptr(rs); \
8426 tcg_temp_free_i32(i32); \
8429 GEN_DFP_T_A_B_Rc(dadd
)
8430 GEN_DFP_T_A_B_Rc(daddq
)
8431 GEN_DFP_T_A_B_Rc(dsub
)
8432 GEN_DFP_T_A_B_Rc(dsubq
)
8433 GEN_DFP_T_A_B_Rc(dmul
)
8434 GEN_DFP_T_A_B_Rc(dmulq
)
8435 GEN_DFP_T_A_B_Rc(ddiv
)
8436 GEN_DFP_T_A_B_Rc(ddivq
)
8437 GEN_DFP_BF_A_B(dcmpu
)
8438 GEN_DFP_BF_A_B(dcmpuq
)
8439 GEN_DFP_BF_A_B(dcmpo
)
8440 GEN_DFP_BF_A_B(dcmpoq
)
8441 GEN_DFP_BF_A_DCM(dtstdc
)
8442 GEN_DFP_BF_A_DCM(dtstdcq
)
8443 GEN_DFP_BF_A_DCM(dtstdg
)
8444 GEN_DFP_BF_A_DCM(dtstdgq
)
8445 GEN_DFP_BF_A_B(dtstex
)
8446 GEN_DFP_BF_A_B(dtstexq
)
8447 GEN_DFP_BF_A_B(dtstsf
)
8448 GEN_DFP_BF_A_B(dtstsfq
)
8449 GEN_DFP_T_B_U32_U32_Rc(dquai
, SIMM5
, RMC
)
8450 GEN_DFP_T_B_U32_U32_Rc(dquaiq
, SIMM5
, RMC
)
8451 GEN_DFP_T_A_B_I32_Rc(dqua
, RMC
)
8452 GEN_DFP_T_A_B_I32_Rc(dquaq
, RMC
)
8453 GEN_DFP_T_A_B_I32_Rc(drrnd
, RMC
)
8454 GEN_DFP_T_A_B_I32_Rc(drrndq
, RMC
)
8455 GEN_DFP_T_B_U32_U32_Rc(drintx
, FPW
, RMC
)
8456 GEN_DFP_T_B_U32_U32_Rc(drintxq
, FPW
, RMC
)
8457 GEN_DFP_T_B_U32_U32_Rc(drintn
, FPW
, RMC
)
8458 GEN_DFP_T_B_U32_U32_Rc(drintnq
, FPW
, RMC
)
8459 GEN_DFP_T_B_Rc(dctdp
)
8460 GEN_DFP_T_B_Rc(dctqpq
)
8461 GEN_DFP_T_B_Rc(drsp
)
8462 GEN_DFP_T_B_Rc(drdpq
)
8463 GEN_DFP_T_B_Rc(dcffix
)
8464 GEN_DFP_T_B_Rc(dcffixq
)
8465 GEN_DFP_T_B_Rc(dctfix
)
8466 GEN_DFP_T_B_Rc(dctfixq
)
8467 GEN_DFP_T_FPR_I32_Rc(ddedpd
, rB
, SP
)
8468 GEN_DFP_T_FPR_I32_Rc(ddedpdq
, rB
, SP
)
8469 GEN_DFP_T_FPR_I32_Rc(denbcd
, rB
, SP
)
8470 GEN_DFP_T_FPR_I32_Rc(denbcdq
, rB
, SP
)
8471 GEN_DFP_T_B_Rc(dxex
)
8472 GEN_DFP_T_B_Rc(dxexq
)
8473 GEN_DFP_T_A_B_Rc(diex
)
8474 GEN_DFP_T_A_B_Rc(diexq
)
8475 GEN_DFP_T_FPR_I32_Rc(dscli
, rA
, DCM
)
8476 GEN_DFP_T_FPR_I32_Rc(dscliq
, rA
, DCM
)
8477 GEN_DFP_T_FPR_I32_Rc(dscri
, rA
, DCM
)
8478 GEN_DFP_T_FPR_I32_Rc(dscriq
, rA
, DCM
)
8480 /*** SPE extension ***/
8481 /* Register moves */
8483 static inline void gen_evmra(DisasContext
*ctx
)
8486 if (unlikely(!ctx
->spe_enabled
)) {
8487 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8491 TCGv_i64 tmp
= tcg_temp_new_i64();
8493 /* tmp := rA_lo + rA_hi << 32 */
8494 tcg_gen_concat_tl_i64(tmp
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8496 /* spe_acc := tmp */
8497 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8498 tcg_temp_free_i64(tmp
);
8501 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8502 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8505 static inline void gen_load_gpr64(TCGv_i64 t
, int reg
)
8507 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg
], cpu_gprh
[reg
]);
8510 static inline void gen_store_gpr64(int reg
, TCGv_i64 t
)
8512 tcg_gen_extr_i64_tl(cpu_gpr
[reg
], cpu_gprh
[reg
], t
);
8515 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8516 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8518 if (Rc(ctx->opcode)) \
8524 /* Handler for undefined SPE opcodes */
8525 static inline void gen_speundef(DisasContext
*ctx
)
8527 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
8531 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8532 static inline void gen_##name(DisasContext *ctx) \
8534 if (unlikely(!ctx->spe_enabled)) { \
8535 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8538 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8539 cpu_gpr[rB(ctx->opcode)]); \
8540 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8541 cpu_gprh[rB(ctx->opcode)]); \
8544 GEN_SPEOP_LOGIC2(evand
, tcg_gen_and_tl
);
8545 GEN_SPEOP_LOGIC2(evandc
, tcg_gen_andc_tl
);
8546 GEN_SPEOP_LOGIC2(evxor
, tcg_gen_xor_tl
);
8547 GEN_SPEOP_LOGIC2(evor
, tcg_gen_or_tl
);
8548 GEN_SPEOP_LOGIC2(evnor
, tcg_gen_nor_tl
);
8549 GEN_SPEOP_LOGIC2(eveqv
, tcg_gen_eqv_tl
);
8550 GEN_SPEOP_LOGIC2(evorc
, tcg_gen_orc_tl
);
8551 GEN_SPEOP_LOGIC2(evnand
, tcg_gen_nand_tl
);
8553 /* SPE logic immediate */
8554 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8555 static inline void gen_##name(DisasContext *ctx) \
8558 if (unlikely(!ctx->spe_enabled)) { \
8559 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8562 t0 = tcg_temp_new_i32(); \
8564 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8565 tcg_opi(t0, t0, rB(ctx->opcode)); \
8566 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8568 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8569 tcg_opi(t0, t0, rB(ctx->opcode)); \
8570 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8572 tcg_temp_free_i32(t0); \
8574 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi
, tcg_gen_shli_i32
);
8575 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu
, tcg_gen_shri_i32
);
8576 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis
, tcg_gen_sari_i32
);
8577 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi
, tcg_gen_rotli_i32
);
8579 /* SPE arithmetic */
8580 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8581 static inline void gen_##name(DisasContext *ctx) \
8584 if (unlikely(!ctx->spe_enabled)) { \
8585 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8588 t0 = tcg_temp_new_i32(); \
8590 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8592 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8594 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8596 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8598 tcg_temp_free_i32(t0); \
8601 static inline void gen_op_evabs(TCGv_i32 ret
, TCGv_i32 arg1
)
8603 TCGLabel
*l1
= gen_new_label();
8604 TCGLabel
*l2
= gen_new_label();
8606 tcg_gen_brcondi_i32(TCG_COND_GE
, arg1
, 0, l1
);
8607 tcg_gen_neg_i32(ret
, arg1
);
8610 tcg_gen_mov_i32(ret
, arg1
);
8613 GEN_SPEOP_ARITH1(evabs
, gen_op_evabs
);
8614 GEN_SPEOP_ARITH1(evneg
, tcg_gen_neg_i32
);
8615 GEN_SPEOP_ARITH1(evextsb
, tcg_gen_ext8s_i32
);
8616 GEN_SPEOP_ARITH1(evextsh
, tcg_gen_ext16s_i32
);
8617 static inline void gen_op_evrndw(TCGv_i32 ret
, TCGv_i32 arg1
)
8619 tcg_gen_addi_i32(ret
, arg1
, 0x8000);
8620 tcg_gen_ext16u_i32(ret
, ret
);
8622 GEN_SPEOP_ARITH1(evrndw
, gen_op_evrndw
);
8623 GEN_SPEOP_ARITH1(evcntlsw
, gen_helper_cntlsw32
);
8624 GEN_SPEOP_ARITH1(evcntlzw
, gen_helper_cntlzw32
);
8626 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8627 static inline void gen_##name(DisasContext *ctx) \
8630 if (unlikely(!ctx->spe_enabled)) { \
8631 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8634 t0 = tcg_temp_new_i32(); \
8635 t1 = tcg_temp_new_i32(); \
8637 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8638 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8639 tcg_op(t0, t0, t1); \
8640 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8642 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8643 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8644 tcg_op(t0, t0, t1); \
8645 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8647 tcg_temp_free_i32(t0); \
8648 tcg_temp_free_i32(t1); \
8651 static inline void gen_op_evsrwu(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8653 TCGLabel
*l1
= gen_new_label();
8654 TCGLabel
*l2
= gen_new_label();
8655 TCGv_i32 t0
= tcg_temp_local_new_i32();
8657 /* No error here: 6 bits are used */
8658 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8659 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8660 tcg_gen_shr_i32(ret
, arg1
, t0
);
8663 tcg_gen_movi_i32(ret
, 0);
8665 tcg_temp_free_i32(t0
);
8667 GEN_SPEOP_ARITH2(evsrwu
, gen_op_evsrwu
);
8668 static inline void gen_op_evsrws(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8670 TCGLabel
*l1
= gen_new_label();
8671 TCGLabel
*l2
= gen_new_label();
8672 TCGv_i32 t0
= tcg_temp_local_new_i32();
8674 /* No error here: 6 bits are used */
8675 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8676 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8677 tcg_gen_sar_i32(ret
, arg1
, t0
);
8680 tcg_gen_movi_i32(ret
, 0);
8682 tcg_temp_free_i32(t0
);
8684 GEN_SPEOP_ARITH2(evsrws
, gen_op_evsrws
);
8685 static inline void gen_op_evslw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8687 TCGLabel
*l1
= gen_new_label();
8688 TCGLabel
*l2
= gen_new_label();
8689 TCGv_i32 t0
= tcg_temp_local_new_i32();
8691 /* No error here: 6 bits are used */
8692 tcg_gen_andi_i32(t0
, arg2
, 0x3F);
8693 tcg_gen_brcondi_i32(TCG_COND_GE
, t0
, 32, l1
);
8694 tcg_gen_shl_i32(ret
, arg1
, t0
);
8697 tcg_gen_movi_i32(ret
, 0);
8699 tcg_temp_free_i32(t0
);
8701 GEN_SPEOP_ARITH2(evslw
, gen_op_evslw
);
8702 static inline void gen_op_evrlw(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8704 TCGv_i32 t0
= tcg_temp_new_i32();
8705 tcg_gen_andi_i32(t0
, arg2
, 0x1F);
8706 tcg_gen_rotl_i32(ret
, arg1
, t0
);
8707 tcg_temp_free_i32(t0
);
8709 GEN_SPEOP_ARITH2(evrlw
, gen_op_evrlw
);
8710 static inline void gen_evmergehi(DisasContext
*ctx
)
8712 if (unlikely(!ctx
->spe_enabled
)) {
8713 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8716 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8717 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8719 GEN_SPEOP_ARITH2(evaddw
, tcg_gen_add_i32
);
8720 static inline void gen_op_evsubf(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
8722 tcg_gen_sub_i32(ret
, arg2
, arg1
);
8724 GEN_SPEOP_ARITH2(evsubfw
, gen_op_evsubf
);
8726 /* SPE arithmetic immediate */
8727 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8728 static inline void gen_##name(DisasContext *ctx) \
8731 if (unlikely(!ctx->spe_enabled)) { \
8732 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8735 t0 = tcg_temp_new_i32(); \
8737 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8738 tcg_op(t0, t0, rA(ctx->opcode)); \
8739 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8741 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8742 tcg_op(t0, t0, rA(ctx->opcode)); \
8743 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8745 tcg_temp_free_i32(t0); \
8747 GEN_SPEOP_ARITH_IMM2(evaddiw
, tcg_gen_addi_i32
);
8748 GEN_SPEOP_ARITH_IMM2(evsubifw
, tcg_gen_subi_i32
);
8750 /* SPE comparison */
8751 #define GEN_SPEOP_COMP(name, tcg_cond) \
8752 static inline void gen_##name(DisasContext *ctx) \
8754 if (unlikely(!ctx->spe_enabled)) { \
8755 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8758 TCGLabel *l1 = gen_new_label(); \
8759 TCGLabel *l2 = gen_new_label(); \
8760 TCGLabel *l3 = gen_new_label(); \
8761 TCGLabel *l4 = gen_new_label(); \
8763 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8764 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8765 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8766 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8768 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8769 cpu_gpr[rB(ctx->opcode)], l1); \
8770 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8772 gen_set_label(l1); \
8773 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8774 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8775 gen_set_label(l2); \
8776 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8777 cpu_gprh[rB(ctx->opcode)], l3); \
8778 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8779 ~(CRF_CH | CRF_CH_AND_CL)); \
8781 gen_set_label(l3); \
8782 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8783 CRF_CH | CRF_CH_OR_CL); \
8784 gen_set_label(l4); \
8786 GEN_SPEOP_COMP(evcmpgtu
, TCG_COND_GTU
);
8787 GEN_SPEOP_COMP(evcmpgts
, TCG_COND_GT
);
8788 GEN_SPEOP_COMP(evcmpltu
, TCG_COND_LTU
);
8789 GEN_SPEOP_COMP(evcmplts
, TCG_COND_LT
);
8790 GEN_SPEOP_COMP(evcmpeq
, TCG_COND_EQ
);
8793 static inline void gen_brinc(DisasContext
*ctx
)
8795 /* Note: brinc is usable even if SPE is disabled */
8796 gen_helper_brinc(cpu_gpr
[rD(ctx
->opcode
)],
8797 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8799 static inline void gen_evmergelo(DisasContext
*ctx
)
8801 if (unlikely(!ctx
->spe_enabled
)) {
8802 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8805 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8806 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8808 static inline void gen_evmergehilo(DisasContext
*ctx
)
8810 if (unlikely(!ctx
->spe_enabled
)) {
8811 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8814 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8815 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8817 static inline void gen_evmergelohi(DisasContext
*ctx
)
8819 if (unlikely(!ctx
->spe_enabled
)) {
8820 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8823 if (rD(ctx
->opcode
) == rA(ctx
->opcode
)) {
8824 TCGv tmp
= tcg_temp_new();
8825 tcg_gen_mov_tl(tmp
, cpu_gpr
[rA(ctx
->opcode
)]);
8826 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8827 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], tmp
);
8830 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8831 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8834 static inline void gen_evsplati(DisasContext
*ctx
)
8836 uint64_t imm
= ((int32_t)(rA(ctx
->opcode
) << 27)) >> 27;
8838 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8839 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8841 static inline void gen_evsplatfi(DisasContext
*ctx
)
8843 uint64_t imm
= rA(ctx
->opcode
) << 27;
8845 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], imm
);
8846 tcg_gen_movi_tl(cpu_gprh
[rD(ctx
->opcode
)], imm
);
8849 static inline void gen_evsel(DisasContext
*ctx
)
8851 TCGLabel
*l1
= gen_new_label();
8852 TCGLabel
*l2
= gen_new_label();
8853 TCGLabel
*l3
= gen_new_label();
8854 TCGLabel
*l4
= gen_new_label();
8855 TCGv_i32 t0
= tcg_temp_local_new_i32();
8857 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 3);
8858 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l1
);
8859 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)]);
8862 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rB(ctx
->opcode
)]);
8864 tcg_gen_andi_i32(t0
, cpu_crf
[ctx
->opcode
& 0x07], 1 << 2);
8865 tcg_gen_brcondi_i32(TCG_COND_EQ
, t0
, 0, l3
);
8866 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
8869 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
8871 tcg_temp_free_i32(t0
);
8874 static void gen_evsel0(DisasContext
*ctx
)
8879 static void gen_evsel1(DisasContext
*ctx
)
8884 static void gen_evsel2(DisasContext
*ctx
)
8889 static void gen_evsel3(DisasContext
*ctx
)
8896 static inline void gen_evmwumi(DisasContext
*ctx
)
8900 if (unlikely(!ctx
->spe_enabled
)) {
8901 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8905 t0
= tcg_temp_new_i64();
8906 t1
= tcg_temp_new_i64();
8908 /* t0 := rA; t1 := rB */
8909 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8910 tcg_gen_ext32u_i64(t0
, t0
);
8911 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8912 tcg_gen_ext32u_i64(t1
, t1
);
8914 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8916 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8918 tcg_temp_free_i64(t0
);
8919 tcg_temp_free_i64(t1
);
8922 static inline void gen_evmwumia(DisasContext
*ctx
)
8926 if (unlikely(!ctx
->spe_enabled
)) {
8927 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8931 gen_evmwumi(ctx
); /* rD := rA * rB */
8933 tmp
= tcg_temp_new_i64();
8936 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8937 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8938 tcg_temp_free_i64(tmp
);
8941 static inline void gen_evmwumiaa(DisasContext
*ctx
)
8946 if (unlikely(!ctx
->spe_enabled
)) {
8947 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8951 gen_evmwumi(ctx
); /* rD := rA * rB */
8953 acc
= tcg_temp_new_i64();
8954 tmp
= tcg_temp_new_i64();
8957 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
8960 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8962 /* acc := tmp + acc */
8963 tcg_gen_add_i64(acc
, acc
, tmp
);
8966 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
8969 gen_store_gpr64(rD(ctx
->opcode
), acc
);
8971 tcg_temp_free_i64(acc
);
8972 tcg_temp_free_i64(tmp
);
8975 static inline void gen_evmwsmi(DisasContext
*ctx
)
8979 if (unlikely(!ctx
->spe_enabled
)) {
8980 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
8984 t0
= tcg_temp_new_i64();
8985 t1
= tcg_temp_new_i64();
8987 /* t0 := rA; t1 := rB */
8988 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
8989 tcg_gen_ext32s_i64(t0
, t0
);
8990 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
8991 tcg_gen_ext32s_i64(t1
, t1
);
8993 tcg_gen_mul_i64(t0
, t0
, t1
); /* t0 := rA * rB */
8995 gen_store_gpr64(rD(ctx
->opcode
), t0
); /* rD := t0 */
8997 tcg_temp_free_i64(t0
);
8998 tcg_temp_free_i64(t1
);
9001 static inline void gen_evmwsmia(DisasContext
*ctx
)
9005 gen_evmwsmi(ctx
); /* rD := rA * rB */
9007 tmp
= tcg_temp_new_i64();
9010 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9011 tcg_gen_st_i64(tmp
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9013 tcg_temp_free_i64(tmp
);
9016 static inline void gen_evmwsmiaa(DisasContext
*ctx
)
9018 TCGv_i64 acc
= tcg_temp_new_i64();
9019 TCGv_i64 tmp
= tcg_temp_new_i64();
9021 gen_evmwsmi(ctx
); /* rD := rA * rB */
9023 acc
= tcg_temp_new_i64();
9024 tmp
= tcg_temp_new_i64();
9027 gen_load_gpr64(tmp
, rD(ctx
->opcode
));
9030 tcg_gen_ld_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9032 /* acc := tmp + acc */
9033 tcg_gen_add_i64(acc
, acc
, tmp
);
9036 tcg_gen_st_i64(acc
, cpu_env
, offsetof(CPUPPCState
, spe_acc
));
9039 gen_store_gpr64(rD(ctx
->opcode
), acc
);
9041 tcg_temp_free_i64(acc
);
9042 tcg_temp_free_i64(tmp
);
9045 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9046 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9047 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9048 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9049 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9050 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9051 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
); ////
9052 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
); //
9053 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
);
9054 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9055 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9056 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9057 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9058 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9059 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9060 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9061 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
); ////
9062 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9063 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9064 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
);
9065 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
); ////
9066 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9067 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
); //
9068 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
);
9069 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9070 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
); ////
9071 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9072 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
); ////
9073 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
); ////
9075 /* SPE load and stores */
9076 static inline void gen_addr_spe_imm_index(DisasContext
*ctx
, TCGv EA
, int sh
)
9078 target_ulong uimm
= rB(ctx
->opcode
);
9080 if (rA(ctx
->opcode
) == 0) {
9081 tcg_gen_movi_tl(EA
, uimm
<< sh
);
9083 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], uimm
<< sh
);
9084 if (NARROW_MODE(ctx
)) {
9085 tcg_gen_ext32u_tl(EA
, EA
);
9090 static inline void gen_op_evldd(DisasContext
*ctx
, TCGv addr
)
9092 TCGv_i64 t0
= tcg_temp_new_i64();
9093 gen_qemu_ld64(ctx
, t0
, addr
);
9094 gen_store_gpr64(rD(ctx
->opcode
), t0
);
9095 tcg_temp_free_i64(t0
);
9098 static inline void gen_op_evldw(DisasContext
*ctx
, TCGv addr
)
9100 gen_qemu_ld32u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9101 gen_addr_add(ctx
, addr
, addr
, 4);
9102 gen_qemu_ld32u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9105 static inline void gen_op_evldh(DisasContext
*ctx
, TCGv addr
)
9107 TCGv t0
= tcg_temp_new();
9108 gen_qemu_ld16u(ctx
, t0
, addr
);
9109 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9110 gen_addr_add(ctx
, addr
, addr
, 2);
9111 gen_qemu_ld16u(ctx
, t0
, addr
);
9112 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9113 gen_addr_add(ctx
, addr
, addr
, 2);
9114 gen_qemu_ld16u(ctx
, t0
, addr
);
9115 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9116 gen_addr_add(ctx
, addr
, addr
, 2);
9117 gen_qemu_ld16u(ctx
, t0
, addr
);
9118 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rD(ctx
->opcode
)], t0
);
9122 static inline void gen_op_evlhhesplat(DisasContext
*ctx
, TCGv addr
)
9124 TCGv t0
= tcg_temp_new();
9125 gen_qemu_ld16u(ctx
, t0
, addr
);
9126 tcg_gen_shli_tl(t0
, t0
, 16);
9127 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9128 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9132 static inline void gen_op_evlhhousplat(DisasContext
*ctx
, TCGv addr
)
9134 TCGv t0
= tcg_temp_new();
9135 gen_qemu_ld16u(ctx
, t0
, addr
);
9136 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9137 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9141 static inline void gen_op_evlhhossplat(DisasContext
*ctx
, TCGv addr
)
9143 TCGv t0
= tcg_temp_new();
9144 gen_qemu_ld16s(ctx
, t0
, addr
);
9145 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9146 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9150 static inline void gen_op_evlwhe(DisasContext
*ctx
, TCGv addr
)
9152 TCGv t0
= tcg_temp_new();
9153 gen_qemu_ld16u(ctx
, t0
, addr
);
9154 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9155 gen_addr_add(ctx
, addr
, addr
, 2);
9156 gen_qemu_ld16u(ctx
, t0
, addr
);
9157 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9161 static inline void gen_op_evlwhou(DisasContext
*ctx
, TCGv addr
)
9163 gen_qemu_ld16u(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9164 gen_addr_add(ctx
, addr
, addr
, 2);
9165 gen_qemu_ld16u(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9168 static inline void gen_op_evlwhos(DisasContext
*ctx
, TCGv addr
)
9170 gen_qemu_ld16s(ctx
, cpu_gprh
[rD(ctx
->opcode
)], addr
);
9171 gen_addr_add(ctx
, addr
, addr
, 2);
9172 gen_qemu_ld16s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], addr
);
9175 static inline void gen_op_evlwwsplat(DisasContext
*ctx
, TCGv addr
)
9177 TCGv t0
= tcg_temp_new();
9178 gen_qemu_ld32u(ctx
, t0
, addr
);
9179 tcg_gen_mov_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
);
9180 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
9184 static inline void gen_op_evlwhsplat(DisasContext
*ctx
, TCGv addr
)
9186 TCGv t0
= tcg_temp_new();
9187 gen_qemu_ld16u(ctx
, t0
, addr
);
9188 tcg_gen_shli_tl(cpu_gprh
[rD(ctx
->opcode
)], t0
, 16);
9189 tcg_gen_or_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9190 gen_addr_add(ctx
, addr
, addr
, 2);
9191 gen_qemu_ld16u(ctx
, t0
, addr
);
9192 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, 16);
9193 tcg_gen_or_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gprh
[rD(ctx
->opcode
)], t0
);
9197 static inline void gen_op_evstdd(DisasContext
*ctx
, TCGv addr
)
9199 TCGv_i64 t0
= tcg_temp_new_i64();
9200 gen_load_gpr64(t0
, rS(ctx
->opcode
));
9201 gen_qemu_st64(ctx
, t0
, addr
);
9202 tcg_temp_free_i64(t0
);
9205 static inline void gen_op_evstdw(DisasContext
*ctx
, TCGv addr
)
9207 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9208 gen_addr_add(ctx
, addr
, addr
, 4);
9209 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9212 static inline void gen_op_evstdh(DisasContext
*ctx
, TCGv addr
)
9214 TCGv t0
= tcg_temp_new();
9215 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9216 gen_qemu_st16(ctx
, t0
, addr
);
9217 gen_addr_add(ctx
, addr
, addr
, 2);
9218 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9219 gen_addr_add(ctx
, addr
, addr
, 2);
9220 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9221 gen_qemu_st16(ctx
, t0
, addr
);
9223 gen_addr_add(ctx
, addr
, addr
, 2);
9224 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9227 static inline void gen_op_evstwhe(DisasContext
*ctx
, TCGv addr
)
9229 TCGv t0
= tcg_temp_new();
9230 tcg_gen_shri_tl(t0
, cpu_gprh
[rS(ctx
->opcode
)], 16);
9231 gen_qemu_st16(ctx
, t0
, addr
);
9232 gen_addr_add(ctx
, addr
, addr
, 2);
9233 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], 16);
9234 gen_qemu_st16(ctx
, t0
, addr
);
9238 static inline void gen_op_evstwho(DisasContext
*ctx
, TCGv addr
)
9240 gen_qemu_st16(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9241 gen_addr_add(ctx
, addr
, addr
, 2);
9242 gen_qemu_st16(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9245 static inline void gen_op_evstwwe(DisasContext
*ctx
, TCGv addr
)
9247 gen_qemu_st32(ctx
, cpu_gprh
[rS(ctx
->opcode
)], addr
);
9250 static inline void gen_op_evstwwo(DisasContext
*ctx
, TCGv addr
)
9252 gen_qemu_st32(ctx
, cpu_gpr
[rS(ctx
->opcode
)], addr
);
9255 #define GEN_SPEOP_LDST(name, opc2, sh) \
9256 static void glue(gen_, name)(DisasContext *ctx) \
9259 if (unlikely(!ctx->spe_enabled)) { \
9260 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9263 gen_set_access_type(ctx, ACCESS_INT); \
9264 t0 = tcg_temp_new(); \
9265 if (Rc(ctx->opcode)) { \
9266 gen_addr_spe_imm_index(ctx, t0, sh); \
9268 gen_addr_reg_index(ctx, t0); \
9270 gen_op_##name(ctx, t0); \
9271 tcg_temp_free(t0); \
9274 GEN_SPEOP_LDST(evldd
, 0x00, 3);
9275 GEN_SPEOP_LDST(evldw
, 0x01, 3);
9276 GEN_SPEOP_LDST(evldh
, 0x02, 3);
9277 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1);
9278 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1);
9279 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1);
9280 GEN_SPEOP_LDST(evlwhe
, 0x08, 2);
9281 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2);
9282 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2);
9283 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2);
9284 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2);
9286 GEN_SPEOP_LDST(evstdd
, 0x10, 3);
9287 GEN_SPEOP_LDST(evstdw
, 0x11, 3);
9288 GEN_SPEOP_LDST(evstdh
, 0x12, 3);
9289 GEN_SPEOP_LDST(evstwhe
, 0x18, 2);
9290 GEN_SPEOP_LDST(evstwho
, 0x1A, 2);
9291 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2);
9292 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2);
9294 /* Multiply and add - TODO */
9296 GEN_SPE(speundef
, evmhessf
, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);//
9297 GEN_SPE(speundef
, evmhossf
, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9298 GEN_SPE(evmheumi
, evmhesmi
, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9299 GEN_SPE(speundef
, evmhesmf
, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9300 GEN_SPE(evmhoumi
, evmhosmi
, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9301 GEN_SPE(speundef
, evmhosmf
, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9302 GEN_SPE(speundef
, evmhessfa
, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9303 GEN_SPE(speundef
, evmhossfa
, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9304 GEN_SPE(evmheumia
, evmhesmia
, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9305 GEN_SPE(speundef
, evmhesmfa
, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9306 GEN_SPE(evmhoumia
, evmhosmia
, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE
);
9307 GEN_SPE(speundef
, evmhosmfa
, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9309 GEN_SPE(speundef
, evmwhssf
, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9310 GEN_SPE(evmwlumi
, speundef
, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9311 GEN_SPE(evmwhumi
, evmwhsmi
, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9312 GEN_SPE(speundef
, evmwhsmf
, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9313 GEN_SPE(speundef
, evmwssf
, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9314 GEN_SPE(speundef
, evmwsmf
, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9315 GEN_SPE(speundef
, evmwhssfa
, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9316 GEN_SPE(evmwlumia
, speundef
, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE
);
9317 GEN_SPE(evmwhumia
, evmwhsmia
, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE
);
9318 GEN_SPE(speundef
, evmwhsmfa
, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9319 GEN_SPE(speundef
, evmwssfa
, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9320 GEN_SPE(speundef
, evmwsmfa
, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9322 GEN_SPE(evadduiaaw
, evaddsiaaw
, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9323 GEN_SPE(evsubfusiaaw
, evsubfssiaaw
, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9324 GEN_SPE(evaddumiaaw
, evaddsmiaaw
, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9325 GEN_SPE(evsubfumiaaw
, evsubfsmiaaw
, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE
);
9326 GEN_SPE(evdivws
, evdivwu
, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE
);
9328 GEN_SPE(evmheusiaaw
, evmhessiaaw
, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9329 GEN_SPE(speundef
, evmhessfaaw
, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9330 GEN_SPE(evmhousiaaw
, evmhossiaaw
, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9331 GEN_SPE(speundef
, evmhossfaaw
, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9332 GEN_SPE(evmheumiaaw
, evmhesmiaaw
, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9333 GEN_SPE(speundef
, evmhesmfaaw
, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9334 GEN_SPE(evmhoumiaaw
, evmhosmiaaw
, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9335 GEN_SPE(speundef
, evmhosmfaaw
, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9336 GEN_SPE(evmhegumiaa
, evmhegsmiaa
, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9337 GEN_SPE(speundef
, evmhegsmfaa
, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9338 GEN_SPE(evmhogumiaa
, evmhogsmiaa
, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE
);
9339 GEN_SPE(speundef
, evmhogsmfaa
, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9341 GEN_SPE(evmwlusiaaw
, evmwlssiaaw
, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9342 GEN_SPE(evmwlumiaaw
, evmwlsmiaaw
, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE
);
9343 GEN_SPE(speundef
, evmwssfaa
, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9344 GEN_SPE(speundef
, evmwsmfaa
, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9346 GEN_SPE(evmheusianw
, evmhessianw
, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9347 GEN_SPE(speundef
, evmhessfanw
, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9348 GEN_SPE(evmhousianw
, evmhossianw
, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9349 GEN_SPE(speundef
, evmhossfanw
, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9350 GEN_SPE(evmheumianw
, evmhesmianw
, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9351 GEN_SPE(speundef
, evmhesmfanw
, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9352 GEN_SPE(evmhoumianw
, evmhosmianw
, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9353 GEN_SPE(speundef
, evmhosmfanw
, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9354 GEN_SPE(evmhegumian
, evmhegsmian
, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9355 GEN_SPE(speundef
, evmhegsmfan
, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9356 GEN_SPE(evmhigumian
, evmhigsmian
, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE
);
9357 GEN_SPE(speundef
, evmhogsmfan
, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9359 GEN_SPE(evmwlusianw
, evmwlssianw
, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9360 GEN_SPE(evmwlumianw
, evmwlsmianw
, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9361 GEN_SPE(speundef
, evmwssfan
, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9362 GEN_SPE(evmwumian
, evmwsmian
, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE
);
9363 GEN_SPE(speundef
, evmwsmfan
, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE
);
9366 /*** SPE floating-point extension ***/
9367 #define GEN_SPEFPUOP_CONV_32_32(name) \
9368 static inline void gen_##name(DisasContext *ctx) \
9370 TCGv_i32 t0 = tcg_temp_new_i32(); \
9371 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9372 gen_helper_##name(t0, cpu_env, t0); \
9373 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9374 tcg_temp_free_i32(t0); \
9376 #define GEN_SPEFPUOP_CONV_32_64(name) \
9377 static inline void gen_##name(DisasContext *ctx) \
9379 TCGv_i64 t0 = tcg_temp_new_i64(); \
9380 TCGv_i32 t1 = tcg_temp_new_i32(); \
9381 gen_load_gpr64(t0, rB(ctx->opcode)); \
9382 gen_helper_##name(t1, cpu_env, t0); \
9383 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9384 tcg_temp_free_i64(t0); \
9385 tcg_temp_free_i32(t1); \
9387 #define GEN_SPEFPUOP_CONV_64_32(name) \
9388 static inline void gen_##name(DisasContext *ctx) \
9390 TCGv_i64 t0 = tcg_temp_new_i64(); \
9391 TCGv_i32 t1 = tcg_temp_new_i32(); \
9392 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9393 gen_helper_##name(t0, cpu_env, t1); \
9394 gen_store_gpr64(rD(ctx->opcode), t0); \
9395 tcg_temp_free_i64(t0); \
9396 tcg_temp_free_i32(t1); \
9398 #define GEN_SPEFPUOP_CONV_64_64(name) \
9399 static inline void gen_##name(DisasContext *ctx) \
9401 TCGv_i64 t0 = tcg_temp_new_i64(); \
9402 gen_load_gpr64(t0, rB(ctx->opcode)); \
9403 gen_helper_##name(t0, cpu_env, t0); \
9404 gen_store_gpr64(rD(ctx->opcode), t0); \
9405 tcg_temp_free_i64(t0); \
9407 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9408 static inline void gen_##name(DisasContext *ctx) \
9411 if (unlikely(!ctx->spe_enabled)) { \
9412 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9415 t0 = tcg_temp_new_i32(); \
9416 t1 = tcg_temp_new_i32(); \
9417 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9418 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9419 gen_helper_##name(t0, cpu_env, t0, t1); \
9420 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9422 tcg_temp_free_i32(t0); \
9423 tcg_temp_free_i32(t1); \
9425 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9426 static inline void gen_##name(DisasContext *ctx) \
9429 if (unlikely(!ctx->spe_enabled)) { \
9430 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9433 t0 = tcg_temp_new_i64(); \
9434 t1 = tcg_temp_new_i64(); \
9435 gen_load_gpr64(t0, rA(ctx->opcode)); \
9436 gen_load_gpr64(t1, rB(ctx->opcode)); \
9437 gen_helper_##name(t0, cpu_env, t0, t1); \
9438 gen_store_gpr64(rD(ctx->opcode), t0); \
9439 tcg_temp_free_i64(t0); \
9440 tcg_temp_free_i64(t1); \
9442 #define GEN_SPEFPUOP_COMP_32(name) \
9443 static inline void gen_##name(DisasContext *ctx) \
9446 if (unlikely(!ctx->spe_enabled)) { \
9447 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9450 t0 = tcg_temp_new_i32(); \
9451 t1 = tcg_temp_new_i32(); \
9453 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9454 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9455 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9457 tcg_temp_free_i32(t0); \
9458 tcg_temp_free_i32(t1); \
9460 #define GEN_SPEFPUOP_COMP_64(name) \
9461 static inline void gen_##name(DisasContext *ctx) \
9464 if (unlikely(!ctx->spe_enabled)) { \
9465 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9468 t0 = tcg_temp_new_i64(); \
9469 t1 = tcg_temp_new_i64(); \
9470 gen_load_gpr64(t0, rA(ctx->opcode)); \
9471 gen_load_gpr64(t1, rB(ctx->opcode)); \
9472 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9473 tcg_temp_free_i64(t0); \
9474 tcg_temp_free_i64(t1); \
9477 /* Single precision floating-point vectors operations */
9479 GEN_SPEFPUOP_ARITH2_64_64(evfsadd
);
9480 GEN_SPEFPUOP_ARITH2_64_64(evfssub
);
9481 GEN_SPEFPUOP_ARITH2_64_64(evfsmul
);
9482 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv
);
9483 static inline void gen_evfsabs(DisasContext
*ctx
)
9485 if (unlikely(!ctx
->spe_enabled
)) {
9486 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9489 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9491 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9494 static inline void gen_evfsnabs(DisasContext
*ctx
)
9496 if (unlikely(!ctx
->spe_enabled
)) {
9497 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9500 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9502 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9505 static inline void gen_evfsneg(DisasContext
*ctx
)
9507 if (unlikely(!ctx
->spe_enabled
)) {
9508 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9511 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
9513 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9518 GEN_SPEFPUOP_CONV_64_64(evfscfui
);
9519 GEN_SPEFPUOP_CONV_64_64(evfscfsi
);
9520 GEN_SPEFPUOP_CONV_64_64(evfscfuf
);
9521 GEN_SPEFPUOP_CONV_64_64(evfscfsf
);
9522 GEN_SPEFPUOP_CONV_64_64(evfsctui
);
9523 GEN_SPEFPUOP_CONV_64_64(evfsctsi
);
9524 GEN_SPEFPUOP_CONV_64_64(evfsctuf
);
9525 GEN_SPEFPUOP_CONV_64_64(evfsctsf
);
9526 GEN_SPEFPUOP_CONV_64_64(evfsctuiz
);
9527 GEN_SPEFPUOP_CONV_64_64(evfsctsiz
);
9530 GEN_SPEFPUOP_COMP_64(evfscmpgt
);
9531 GEN_SPEFPUOP_COMP_64(evfscmplt
);
9532 GEN_SPEFPUOP_COMP_64(evfscmpeq
);
9533 GEN_SPEFPUOP_COMP_64(evfststgt
);
9534 GEN_SPEFPUOP_COMP_64(evfststlt
);
9535 GEN_SPEFPUOP_COMP_64(evfststeq
);
9537 /* Opcodes definitions */
9538 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9539 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9540 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9541 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9542 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9543 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9544 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9545 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9546 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9547 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9548 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9549 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9550 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9551 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9553 /* Single precision floating-point operations */
9555 GEN_SPEFPUOP_ARITH2_32_32(efsadd
);
9556 GEN_SPEFPUOP_ARITH2_32_32(efssub
);
9557 GEN_SPEFPUOP_ARITH2_32_32(efsmul
);
9558 GEN_SPEFPUOP_ARITH2_32_32(efsdiv
);
9559 static inline void gen_efsabs(DisasContext
*ctx
)
9561 if (unlikely(!ctx
->spe_enabled
)) {
9562 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9565 tcg_gen_andi_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], (target_long
)~0x80000000LL
);
9567 static inline void gen_efsnabs(DisasContext
*ctx
)
9569 if (unlikely(!ctx
->spe_enabled
)) {
9570 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9573 tcg_gen_ori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9575 static inline void gen_efsneg(DisasContext
*ctx
)
9577 if (unlikely(!ctx
->spe_enabled
)) {
9578 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9581 tcg_gen_xori_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], 0x80000000);
9585 GEN_SPEFPUOP_CONV_32_32(efscfui
);
9586 GEN_SPEFPUOP_CONV_32_32(efscfsi
);
9587 GEN_SPEFPUOP_CONV_32_32(efscfuf
);
9588 GEN_SPEFPUOP_CONV_32_32(efscfsf
);
9589 GEN_SPEFPUOP_CONV_32_32(efsctui
);
9590 GEN_SPEFPUOP_CONV_32_32(efsctsi
);
9591 GEN_SPEFPUOP_CONV_32_32(efsctuf
);
9592 GEN_SPEFPUOP_CONV_32_32(efsctsf
);
9593 GEN_SPEFPUOP_CONV_32_32(efsctuiz
);
9594 GEN_SPEFPUOP_CONV_32_32(efsctsiz
);
9595 GEN_SPEFPUOP_CONV_32_64(efscfd
);
9598 GEN_SPEFPUOP_COMP_32(efscmpgt
);
9599 GEN_SPEFPUOP_COMP_32(efscmplt
);
9600 GEN_SPEFPUOP_COMP_32(efscmpeq
);
9601 GEN_SPEFPUOP_COMP_32(efststgt
);
9602 GEN_SPEFPUOP_COMP_32(efststlt
);
9603 GEN_SPEFPUOP_COMP_32(efststeq
);
9605 /* Opcodes definitions */
9606 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9607 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
); //
9608 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9609 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
); //
9610 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9611 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
); //
9612 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9613 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9614 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9615 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
); //
9616 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9617 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9618 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
); //
9619 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
); //
9621 /* Double precision floating-point operations */
9623 GEN_SPEFPUOP_ARITH2_64_64(efdadd
);
9624 GEN_SPEFPUOP_ARITH2_64_64(efdsub
);
9625 GEN_SPEFPUOP_ARITH2_64_64(efdmul
);
9626 GEN_SPEFPUOP_ARITH2_64_64(efddiv
);
9627 static inline void gen_efdabs(DisasContext
*ctx
)
9629 if (unlikely(!ctx
->spe_enabled
)) {
9630 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9633 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9634 tcg_gen_andi_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9637 static inline void gen_efdnabs(DisasContext
*ctx
)
9639 if (unlikely(!ctx
->spe_enabled
)) {
9640 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9643 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9644 tcg_gen_ori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9647 static inline void gen_efdneg(DisasContext
*ctx
)
9649 if (unlikely(!ctx
->spe_enabled
)) {
9650 gen_exception(ctx
, POWERPC_EXCP_SPEU
);
9653 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
9654 tcg_gen_xori_tl(cpu_gprh
[rD(ctx
->opcode
)], cpu_gprh
[rA(ctx
->opcode
)],
9659 GEN_SPEFPUOP_CONV_64_32(efdcfui
);
9660 GEN_SPEFPUOP_CONV_64_32(efdcfsi
);
9661 GEN_SPEFPUOP_CONV_64_32(efdcfuf
);
9662 GEN_SPEFPUOP_CONV_64_32(efdcfsf
);
9663 GEN_SPEFPUOP_CONV_32_64(efdctui
);
9664 GEN_SPEFPUOP_CONV_32_64(efdctsi
);
9665 GEN_SPEFPUOP_CONV_32_64(efdctuf
);
9666 GEN_SPEFPUOP_CONV_32_64(efdctsf
);
9667 GEN_SPEFPUOP_CONV_32_64(efdctuiz
);
9668 GEN_SPEFPUOP_CONV_32_64(efdctsiz
);
9669 GEN_SPEFPUOP_CONV_64_32(efdcfs
);
9670 GEN_SPEFPUOP_CONV_64_64(efdcfuid
);
9671 GEN_SPEFPUOP_CONV_64_64(efdcfsid
);
9672 GEN_SPEFPUOP_CONV_64_64(efdctuidz
);
9673 GEN_SPEFPUOP_CONV_64_64(efdctsidz
);
9676 GEN_SPEFPUOP_COMP_64(efdcmpgt
);
9677 GEN_SPEFPUOP_COMP_64(efdcmplt
);
9678 GEN_SPEFPUOP_COMP_64(efdcmpeq
);
9679 GEN_SPEFPUOP_COMP_64(efdtstgt
);
9680 GEN_SPEFPUOP_COMP_64(efdtstlt
);
9681 GEN_SPEFPUOP_COMP_64(efdtsteq
);
9683 /* Opcodes definitions */
9684 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9685 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9686 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
); //
9687 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9688 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
); //
9689 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9690 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9691 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
); //
9692 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9693 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9694 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9695 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
); //
9696 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9697 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9698 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
); //
9699 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
); //
9701 static void gen_tbegin(DisasContext
*ctx
)
9703 if (unlikely(!ctx
->tm_enabled
)) {
9704 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9707 gen_helper_tbegin(cpu_env
);
9710 #define GEN_TM_NOOP(name) \
9711 static inline void gen_##name(DisasContext *ctx) \
9713 if (unlikely(!ctx->tm_enabled)) { \
9714 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9717 /* Because tbegin always fails in QEMU, these user \
9718 * space instructions all have a simple implementation: \
9720 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9721 * = 0b0 || 0b00 || 0b0 \
9723 tcg_gen_movi_i32(cpu_crf[0], 0); \
9727 GEN_TM_NOOP(tabort
);
9728 GEN_TM_NOOP(tabortwc
);
9729 GEN_TM_NOOP(tabortwci
);
9730 GEN_TM_NOOP(tabortdc
);
9731 GEN_TM_NOOP(tabortdci
);
9734 static void gen_tcheck(DisasContext
*ctx
)
9736 if (unlikely(!ctx
->tm_enabled
)) {
9737 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
9740 /* Because tbegin always fails, the tcheck implementation
9743 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9744 * = 0b1 || 0b00 || 0b0
9746 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
9749 #if defined(CONFIG_USER_ONLY)
9750 #define GEN_TM_PRIV_NOOP(name) \
9751 static inline void gen_##name(DisasContext *ctx) \
9753 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9758 #define GEN_TM_PRIV_NOOP(name) \
9759 static inline void gen_##name(DisasContext *ctx) \
9762 if (unlikely(!ctx->tm_enabled)) { \
9763 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9766 /* Because tbegin always fails, the implementation is \
9769 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9770 * = 0b0 || 0b00 | 0b0 \
9772 tcg_gen_movi_i32(cpu_crf[0], 0); \
9777 GEN_TM_PRIV_NOOP(treclaim
);
9778 GEN_TM_PRIV_NOOP(trechkpt
);
9780 static opcode_t opcodes
[] = {
9781 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
9782 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
9783 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9784 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER
),
9785 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
9786 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
9787 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
9788 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9789 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9790 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9791 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9792 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
9793 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
9794 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
9795 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
9796 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9797 #if defined(TARGET_PPC64)
9798 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
9800 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
9801 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
9802 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9803 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9804 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9805 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
9806 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
9807 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
9808 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9809 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9810 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9811 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9812 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
9813 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
9814 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9815 #if defined(TARGET_PPC64)
9816 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
9817 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
9818 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
9819 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
9821 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9822 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9823 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9824 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
9825 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
9826 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
9827 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
9828 #if defined(TARGET_PPC64)
9829 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
9830 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
9831 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
9832 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
9833 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
9835 GEN_HANDLER(frsqrtes
, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES
),
9836 GEN_HANDLER(fsqrt
, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9837 GEN_HANDLER(fsqrts
, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT
),
9838 GEN_HANDLER(fcmpo
, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT
),
9839 GEN_HANDLER(fcmpu
, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT
),
9840 GEN_HANDLER(fabs
, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT
),
9841 GEN_HANDLER(fmr
, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT
),
9842 GEN_HANDLER(fnabs
, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT
),
9843 GEN_HANDLER(fneg
, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT
),
9844 GEN_HANDLER_E(fcpsgn
, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE
, PPC2_ISA205
),
9845 GEN_HANDLER_E(fmrgew
, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9846 GEN_HANDLER_E(fmrgow
, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE
, PPC2_VSX207
),
9847 GEN_HANDLER(mcrfs
, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT
),
9848 GEN_HANDLER(mffs
, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT
),
9849 GEN_HANDLER(mtfsb0
, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT
),
9850 GEN_HANDLER(mtfsb1
, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT
),
9851 GEN_HANDLER(mtfsf
, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT
),
9852 GEN_HANDLER(mtfsfi
, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT
),
9853 #if defined(TARGET_PPC64)
9854 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9855 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
9856 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9858 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9859 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
9860 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
9861 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
9862 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
9863 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
9864 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO
),
9865 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
9866 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9867 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9868 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
9869 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9870 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
9871 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
9872 #if defined(TARGET_PPC64)
9873 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
9874 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9875 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
9876 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
9878 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
9879 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
9880 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9881 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9882 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
9883 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
9884 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0, PPC_NONE
, PPC2_BCTAR_ISA207
),
9885 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
9886 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
9887 #if defined(TARGET_PPC64)
9888 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
9889 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
9891 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
9892 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
9893 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
9894 #if defined(TARGET_PPC64)
9895 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
9896 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
9898 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
9899 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
9900 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
9901 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
9902 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
9903 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
9904 #if defined(TARGET_PPC64)
9905 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
9907 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
9908 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
9909 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
9910 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
9911 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
9912 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
9913 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
9914 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
9915 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
9916 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
9917 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC
),
9918 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
9919 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
9920 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
9921 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
9922 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
9923 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
9924 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
9925 #if defined(TARGET_PPC64)
9926 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
9927 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9929 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
9930 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9932 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
9933 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
9934 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
9935 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
9937 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
9938 /* XXX Those instructions will need to be handled differently for
9939 * different ISA versions */
9940 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
9941 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
9942 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
9943 #if defined(TARGET_PPC64)
9944 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
9945 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
9947 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
9948 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
9949 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
9950 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
9951 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
9952 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
9953 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
9954 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
9955 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
9956 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
9957 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
9958 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9959 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
9960 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
9961 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
9962 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
9963 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
9964 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
9965 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
9966 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
9967 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
9968 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
9969 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
9970 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
9971 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
9972 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
9973 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
9974 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
9975 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
9976 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
9977 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
9978 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
9979 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
9980 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
9981 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
9982 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
9983 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
9984 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
9985 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
9986 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
9987 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
9988 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
9989 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
9990 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
9991 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
9992 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
9993 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
9994 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
9995 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
9996 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9997 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
9998 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
9999 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
10000 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
10001 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
10002 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
10003 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
10004 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
10005 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
10006 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
10007 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
10008 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
10009 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
10010 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
10011 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
10012 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
10013 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
10014 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
10015 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
10016 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
10017 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
10018 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
10019 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
10020 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
10021 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
10022 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
10023 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
10024 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
10025 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
10026 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
10027 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10028 PPC_NONE
, PPC2_BOOKE206
),
10029 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10030 PPC_NONE
, PPC2_BOOKE206
),
10031 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10032 PPC_NONE
, PPC2_BOOKE206
),
10033 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10034 PPC_NONE
, PPC2_BOOKE206
),
10035 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10036 PPC_NONE
, PPC2_BOOKE206
),
10037 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10038 PPC_NONE
, PPC2_PRCNTL
),
10039 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10040 PPC_NONE
, PPC2_PRCNTL
),
10041 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
10042 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
10043 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
10044 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
10045 PPC_BOOKE
, PPC2_BOOKE206
),
10046 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE
),
10047 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10048 PPC_BOOKE
, PPC2_BOOKE206
),
10049 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
10050 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
10051 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
10052 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
10053 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
10054 GEN_HANDLER2(evsel0
, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE
),
10055 GEN_HANDLER2(evsel1
, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE
),
10056 GEN_HANDLER2(evsel2
, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE
),
10057 GEN_HANDLER2(evsel3
, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE
),
10059 #undef GEN_INT_ARITH_ADD
10060 #undef GEN_INT_ARITH_ADD_CONST
10061 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10062 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10063 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10064 add_ca, compute_ca, compute_ov) \
10065 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10066 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
10067 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
10068 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
10069 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
10070 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
10071 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
10072 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
10073 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
10074 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
10075 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
10077 #undef GEN_INT_ARITH_DIVW
10078 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10079 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10080 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
10081 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
10082 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
10083 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
10084 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10085 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10086 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10087 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10089 #if defined(TARGET_PPC64)
10090 #undef GEN_INT_ARITH_DIVD
10091 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10092 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10093 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
10094 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
10095 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
10096 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
10098 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10099 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10100 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10101 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
10103 #undef GEN_INT_ARITH_MUL_HELPER
10104 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10105 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10106 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
10107 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
10108 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
10111 #undef GEN_INT_ARITH_SUBF
10112 #undef GEN_INT_ARITH_SUBF_CONST
10113 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10114 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10115 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10116 add_ca, compute_ca, compute_ov) \
10117 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10118 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
10119 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
10120 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
10121 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
10122 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
10123 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
10124 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
10125 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
10126 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
10127 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
10129 #undef GEN_LOGICAL1
10130 #undef GEN_LOGICAL2
10131 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10132 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10133 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10134 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10135 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
10136 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
10137 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
10138 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
10139 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
10140 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
10141 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
10142 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
10143 #if defined(TARGET_PPC64)
10144 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
10147 #if defined(TARGET_PPC64)
10148 #undef GEN_PPC64_R2
10149 #undef GEN_PPC64_R4
10150 #define GEN_PPC64_R2(name, opc1, opc2) \
10151 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10152 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10154 #define GEN_PPC64_R4(name, opc1, opc2) \
10155 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10156 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10158 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10160 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10162 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
10163 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
10164 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
10165 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
10166 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
10167 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
10170 #undef _GEN_FLOAT_ACB
10171 #undef GEN_FLOAT_ACB
10172 #undef _GEN_FLOAT_AB
10173 #undef GEN_FLOAT_AB
10174 #undef _GEN_FLOAT_AC
10175 #undef GEN_FLOAT_AC
10177 #undef GEN_FLOAT_BS
10178 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10179 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10180 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10181 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10182 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10183 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10184 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10185 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10186 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10187 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10188 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10189 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10190 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10191 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10192 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10193 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10194 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10195 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10196 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10198 GEN_FLOAT_AB(add
, 0x15, 0x000007C0, 1, PPC_FLOAT
),
10199 GEN_FLOAT_AB(div
, 0x12, 0x000007C0, 1, PPC_FLOAT
),
10200 GEN_FLOAT_AC(mul
, 0x19, 0x0000F800, 1, PPC_FLOAT
),
10201 GEN_FLOAT_BS(re
, 0x3F, 0x18, 1, PPC_FLOAT_EXT
),
10202 GEN_FLOAT_BS(res
, 0x3B, 0x18, 1, PPC_FLOAT_FRES
),
10203 GEN_FLOAT_BS(rsqrte
, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE
),
10204 _GEN_FLOAT_ACB(sel
, sel
, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL
),
10205 GEN_FLOAT_AB(sub
, 0x14, 0x000007C0, 1, PPC_FLOAT
),
10206 GEN_FLOAT_ACB(madd
, 0x1D, 1, PPC_FLOAT
),
10207 GEN_FLOAT_ACB(msub
, 0x1C, 1, PPC_FLOAT
),
10208 GEN_FLOAT_ACB(nmadd
, 0x1F, 1, PPC_FLOAT
),
10209 GEN_FLOAT_ACB(nmsub
, 0x1E, 1, PPC_FLOAT
),
10210 GEN_HANDLER_E(ftdiv
, 0x3F, 0x00, 0x04, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10211 GEN_HANDLER_E(ftsqrt
, 0x3F, 0x00, 0x05, 1, PPC_NONE
, PPC2_FP_TST_ISA206
),
10212 GEN_FLOAT_B(ctiw
, 0x0E, 0x00, 0, PPC_FLOAT
),
10213 GEN_HANDLER_E(fctiwu
, 0x3F, 0x0E, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10214 GEN_FLOAT_B(ctiwz
, 0x0F, 0x00, 0, PPC_FLOAT
),
10215 GEN_HANDLER_E(fctiwuz
, 0x3F, 0x0F, 0x04, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10216 GEN_FLOAT_B(rsp
, 0x0C, 0x00, 1, PPC_FLOAT
),
10217 GEN_HANDLER_E(fcfid
, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10218 GEN_HANDLER_E(fcfids
, 0x3B, 0x0E, 0x1A, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10219 GEN_HANDLER_E(fcfidu
, 0x3F, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10220 GEN_HANDLER_E(fcfidus
, 0x3B, 0x0E, 0x1E, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10221 GEN_HANDLER_E(fctid
, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10222 GEN_HANDLER_E(fctidu
, 0x3F, 0x0E, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10223 GEN_HANDLER_E(fctidz
, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE
, PPC2_FP_CVT_S64
),
10224 GEN_HANDLER_E(fctiduz
, 0x3F, 0x0F, 0x1D, 0, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10225 GEN_FLOAT_B(rin
, 0x08, 0x0C, 1, PPC_FLOAT_EXT
),
10226 GEN_FLOAT_B(riz
, 0x08, 0x0D, 1, PPC_FLOAT_EXT
),
10227 GEN_FLOAT_B(rip
, 0x08, 0x0E, 1, PPC_FLOAT_EXT
),
10228 GEN_FLOAT_B(rim
, 0x08, 0x0F, 1, PPC_FLOAT_EXT
),
10235 #define GEN_LD(name, ldop, opc, type) \
10236 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10237 #define GEN_LDU(name, ldop, opc, type) \
10238 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10239 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10240 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10241 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10242 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10243 #define GEN_LDS(name, ldop, op, type) \
10244 GEN_LD(name, ldop, op | 0x20, type) \
10245 GEN_LDU(name, ldop, op | 0x21, type) \
10246 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10247 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10249 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
10250 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
10251 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
10252 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
10253 #if defined(TARGET_PPC64)
10254 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
10255 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
10256 GEN_LDUX(ld
, ld64
, 0x15, 0x01, PPC_64B
)
10257 GEN_LDX(ld
, ld64
, 0x15, 0x00, PPC_64B
)
10258 GEN_LDX_E(ldbr
, ld64ur
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
)
10260 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
10261 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
10268 #define GEN_ST(name, stop, opc, type) \
10269 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10270 #define GEN_STU(name, stop, opc, type) \
10271 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10272 #define GEN_STUX(name, stop, opc2, opc3, type) \
10273 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10274 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10275 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10276 #define GEN_STS(name, stop, op, type) \
10277 GEN_ST(name, stop, op | 0x20, type) \
10278 GEN_STU(name, stop, op | 0x21, type) \
10279 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10280 GEN_STX(name, stop, 0x17, op | 0x00, type)
10282 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
10283 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
10284 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
10285 #if defined(TARGET_PPC64)
10286 GEN_STUX(std
, st64
, 0x15, 0x05, PPC_64B
)
10287 GEN_STX(std
, st64
, 0x15, 0x04, PPC_64B
)
10288 GEN_STX_E(stdbr
, st64r
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
)
10290 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
10291 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
10298 #define GEN_LDF(name, ldop, opc, type) \
10299 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10300 #define GEN_LDUF(name, ldop, opc, type) \
10301 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10302 #define GEN_LDUXF(name, ldop, opc, type) \
10303 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10304 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10305 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10306 #define GEN_LDFS(name, ldop, op, type) \
10307 GEN_LDF(name, ldop, op | 0x20, type) \
10308 GEN_LDUF(name, ldop, op | 0x21, type) \
10309 GEN_LDUXF(name, ldop, op | 0x01, type) \
10310 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10312 GEN_LDFS(lfd
, ld64
, 0x12, PPC_FLOAT
)
10313 GEN_LDFS(lfs
, ld32fs
, 0x10, PPC_FLOAT
)
10314 GEN_HANDLER_E(lfiwax
, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE
, PPC2_ISA205
),
10315 GEN_HANDLER_E(lfiwzx
, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE
, PPC2_FP_CVT_ISA206
),
10316 GEN_HANDLER_E(lfdp
, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10317 GEN_HANDLER_E(lfdpx
, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10324 #define GEN_STF(name, stop, opc, type) \
10325 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10326 #define GEN_STUF(name, stop, opc, type) \
10327 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10328 #define GEN_STUXF(name, stop, opc, type) \
10329 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10330 #define GEN_STXF(name, stop, opc2, opc3, type) \
10331 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10332 #define GEN_STFS(name, stop, op, type) \
10333 GEN_STF(name, stop, op | 0x20, type) \
10334 GEN_STUF(name, stop, op | 0x21, type) \
10335 GEN_STUXF(name, stop, op | 0x01, type) \
10336 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10338 GEN_STFS(stfd
, st64
, 0x16, PPC_FLOAT
)
10339 GEN_STFS(stfs
, st32fs
, 0x14, PPC_FLOAT
)
10340 GEN_STXF(stfiw
, st32fiw
, 0x17, 0x1E, PPC_FLOAT_STFIWX
)
10341 GEN_HANDLER_E(stfdp
, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE
, PPC2_ISA205
),
10342 GEN_HANDLER_E(stfdpx
, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE
, PPC2_ISA205
),
10345 #define GEN_CRLOGIC(name, tcg_op, opc) \
10346 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10347 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
10348 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
10349 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
10350 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
10351 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
10352 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
10353 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
10354 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
10356 #undef GEN_MAC_HANDLER
10357 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10358 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10359 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
10360 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
10361 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
10362 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
10363 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
10364 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
10365 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
10366 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
10367 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
10368 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
10369 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
10370 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
10371 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
10372 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
10373 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
10374 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
10375 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
10376 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
10377 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
10378 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
10379 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
10380 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
10381 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
10382 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
10383 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
10384 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
10385 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
10386 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
10387 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
10388 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
10389 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
10390 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
10391 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
10392 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
10393 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
10394 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
10395 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
10396 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
10397 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
10398 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
10399 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
10400 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
10406 #define GEN_VR_LDX(name, opc2, opc3) \
10407 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10408 #define GEN_VR_STX(name, opc2, opc3) \
10409 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10410 #define GEN_VR_LVE(name, opc2, opc3) \
10411 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10412 #define GEN_VR_STVE(name, opc2, opc3) \
10413 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10414 GEN_VR_LDX(lvx
, 0x07, 0x03),
10415 GEN_VR_LDX(lvxl
, 0x07, 0x0B),
10416 GEN_VR_LVE(bx
, 0x07, 0x00),
10417 GEN_VR_LVE(hx
, 0x07, 0x01),
10418 GEN_VR_LVE(wx
, 0x07, 0x02),
10419 GEN_VR_STX(svx
, 0x07, 0x07),
10420 GEN_VR_STX(svxl
, 0x07, 0x0F),
10421 GEN_VR_STVE(bx
, 0x07, 0x04),
10422 GEN_VR_STVE(hx
, 0x07, 0x05),
10423 GEN_VR_STVE(wx
, 0x07, 0x06),
10425 #undef GEN_VX_LOGICAL
10426 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10427 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10429 #undef GEN_VX_LOGICAL_207
10430 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10431 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10433 GEN_VX_LOGICAL(vand
, tcg_gen_and_i64
, 2, 16),
10434 GEN_VX_LOGICAL(vandc
, tcg_gen_andc_i64
, 2, 17),
10435 GEN_VX_LOGICAL(vor
, tcg_gen_or_i64
, 2, 18),
10436 GEN_VX_LOGICAL(vxor
, tcg_gen_xor_i64
, 2, 19),
10437 GEN_VX_LOGICAL(vnor
, tcg_gen_nor_i64
, 2, 20),
10438 GEN_VX_LOGICAL_207(veqv
, tcg_gen_eqv_i64
, 2, 26),
10439 GEN_VX_LOGICAL_207(vnand
, tcg_gen_nand_i64
, 2, 22),
10440 GEN_VX_LOGICAL_207(vorc
, tcg_gen_orc_i64
, 2, 21),
10443 #define GEN_VXFORM(name, opc2, opc3) \
10444 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10446 #undef GEN_VXFORM_207
10447 #define GEN_VXFORM_207(name, opc2, opc3) \
10448 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10450 #undef GEN_VXFORM_DUAL
10451 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10452 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10454 #undef GEN_VXRFORM_DUAL
10455 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10456 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10457 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10459 GEN_VXFORM(vaddubm
, 0, 0),
10460 GEN_VXFORM(vadduhm
, 0, 1),
10461 GEN_VXFORM(vadduwm
, 0, 2),
10462 GEN_VXFORM_207(vaddudm
, 0, 3),
10463 GEN_VXFORM_DUAL(vsububm
, bcdadd
, 0, 16, PPC_ALTIVEC
, PPC_NONE
),
10464 GEN_VXFORM_DUAL(vsubuhm
, bcdsub
, 0, 17, PPC_ALTIVEC
, PPC_NONE
),
10465 GEN_VXFORM(vsubuwm
, 0, 18),
10466 GEN_VXFORM_207(vsubudm
, 0, 19),
10467 GEN_VXFORM(vmaxub
, 1, 0),
10468 GEN_VXFORM(vmaxuh
, 1, 1),
10469 GEN_VXFORM(vmaxuw
, 1, 2),
10470 GEN_VXFORM_207(vmaxud
, 1, 3),
10471 GEN_VXFORM(vmaxsb
, 1, 4),
10472 GEN_VXFORM(vmaxsh
, 1, 5),
10473 GEN_VXFORM(vmaxsw
, 1, 6),
10474 GEN_VXFORM_207(vmaxsd
, 1, 7),
10475 GEN_VXFORM(vminub
, 1, 8),
10476 GEN_VXFORM(vminuh
, 1, 9),
10477 GEN_VXFORM(vminuw
, 1, 10),
10478 GEN_VXFORM_207(vminud
, 1, 11),
10479 GEN_VXFORM(vminsb
, 1, 12),
10480 GEN_VXFORM(vminsh
, 1, 13),
10481 GEN_VXFORM(vminsw
, 1, 14),
10482 GEN_VXFORM_207(vminsd
, 1, 15),
10483 GEN_VXFORM(vavgub
, 1, 16),
10484 GEN_VXFORM(vavguh
, 1, 17),
10485 GEN_VXFORM(vavguw
, 1, 18),
10486 GEN_VXFORM(vavgsb
, 1, 20),
10487 GEN_VXFORM(vavgsh
, 1, 21),
10488 GEN_VXFORM(vavgsw
, 1, 22),
10489 GEN_VXFORM(vmrghb
, 6, 0),
10490 GEN_VXFORM(vmrghh
, 6, 1),
10491 GEN_VXFORM(vmrghw
, 6, 2),
10492 GEN_VXFORM(vmrglb
, 6, 4),
10493 GEN_VXFORM(vmrglh
, 6, 5),
10494 GEN_VXFORM(vmrglw
, 6, 6),
10495 GEN_VXFORM_207(vmrgew
, 6, 30),
10496 GEN_VXFORM_207(vmrgow
, 6, 26),
10497 GEN_VXFORM(vmuloub
, 4, 0),
10498 GEN_VXFORM(vmulouh
, 4, 1),
10499 GEN_VXFORM_DUAL(vmulouw
, vmuluwm
, 4, 2, PPC_ALTIVEC
, PPC_NONE
),
10500 GEN_VXFORM(vmulosb
, 4, 4),
10501 GEN_VXFORM(vmulosh
, 4, 5),
10502 GEN_VXFORM_207(vmulosw
, 4, 6),
10503 GEN_VXFORM(vmuleub
, 4, 8),
10504 GEN_VXFORM(vmuleuh
, 4, 9),
10505 GEN_VXFORM_207(vmuleuw
, 4, 10),
10506 GEN_VXFORM(vmulesb
, 4, 12),
10507 GEN_VXFORM(vmulesh
, 4, 13),
10508 GEN_VXFORM_207(vmulesw
, 4, 14),
10509 GEN_VXFORM(vslb
, 2, 4),
10510 GEN_VXFORM(vslh
, 2, 5),
10511 GEN_VXFORM(vslw
, 2, 6),
10512 GEN_VXFORM_207(vsld
, 2, 23),
10513 GEN_VXFORM(vsrb
, 2, 8),
10514 GEN_VXFORM(vsrh
, 2, 9),
10515 GEN_VXFORM(vsrw
, 2, 10),
10516 GEN_VXFORM_207(vsrd
, 2, 27),
10517 GEN_VXFORM(vsrab
, 2, 12),
10518 GEN_VXFORM(vsrah
, 2, 13),
10519 GEN_VXFORM(vsraw
, 2, 14),
10520 GEN_VXFORM_207(vsrad
, 2, 15),
10521 GEN_VXFORM(vslo
, 6, 16),
10522 GEN_VXFORM(vsro
, 6, 17),
10523 GEN_VXFORM(vaddcuw
, 0, 6),
10524 GEN_VXFORM(vsubcuw
, 0, 22),
10525 GEN_VXFORM(vaddubs
, 0, 8),
10526 GEN_VXFORM(vadduhs
, 0, 9),
10527 GEN_VXFORM(vadduws
, 0, 10),
10528 GEN_VXFORM(vaddsbs
, 0, 12),
10529 GEN_VXFORM(vaddshs
, 0, 13),
10530 GEN_VXFORM(vaddsws
, 0, 14),
10531 GEN_VXFORM_DUAL(vsububs
, bcdadd
, 0, 24, PPC_ALTIVEC
, PPC_NONE
),
10532 GEN_VXFORM_DUAL(vsubuhs
, bcdsub
, 0, 25, PPC_ALTIVEC
, PPC_NONE
),
10533 GEN_VXFORM(vsubuws
, 0, 26),
10534 GEN_VXFORM(vsubsbs
, 0, 28),
10535 GEN_VXFORM(vsubshs
, 0, 29),
10536 GEN_VXFORM(vsubsws
, 0, 30),
10537 GEN_VXFORM_207(vadduqm
, 0, 4),
10538 GEN_VXFORM_207(vaddcuq
, 0, 5),
10539 GEN_VXFORM_DUAL(vaddeuqm
, vaddecuq
, 30, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10540 GEN_VXFORM_207(vsubuqm
, 0, 20),
10541 GEN_VXFORM_207(vsubcuq
, 0, 21),
10542 GEN_VXFORM_DUAL(vsubeuqm
, vsubecuq
, 31, 0xFF, PPC_NONE
, PPC2_ALTIVEC_207
),
10543 GEN_VXFORM(vrlb
, 2, 0),
10544 GEN_VXFORM(vrlh
, 2, 1),
10545 GEN_VXFORM(vrlw
, 2, 2),
10546 GEN_VXFORM_207(vrld
, 2, 3),
10547 GEN_VXFORM(vsl
, 2, 7),
10548 GEN_VXFORM(vsr
, 2, 11),
10549 GEN_VXFORM(vpkuhum
, 7, 0),
10550 GEN_VXFORM(vpkuwum
, 7, 1),
10551 GEN_VXFORM_207(vpkudum
, 7, 17),
10552 GEN_VXFORM(vpkuhus
, 7, 2),
10553 GEN_VXFORM(vpkuwus
, 7, 3),
10554 GEN_VXFORM_207(vpkudus
, 7, 19),
10555 GEN_VXFORM(vpkshus
, 7, 4),
10556 GEN_VXFORM(vpkswus
, 7, 5),
10557 GEN_VXFORM_207(vpksdus
, 7, 21),
10558 GEN_VXFORM(vpkshss
, 7, 6),
10559 GEN_VXFORM(vpkswss
, 7, 7),
10560 GEN_VXFORM_207(vpksdss
, 7, 23),
10561 GEN_VXFORM(vpkpx
, 7, 12),
10562 GEN_VXFORM(vsum4ubs
, 4, 24),
10563 GEN_VXFORM(vsum4sbs
, 4, 28),
10564 GEN_VXFORM(vsum4shs
, 4, 25),
10565 GEN_VXFORM(vsum2sws
, 4, 26),
10566 GEN_VXFORM(vsumsws
, 4, 30),
10567 GEN_VXFORM(vaddfp
, 5, 0),
10568 GEN_VXFORM(vsubfp
, 5, 1),
10569 GEN_VXFORM(vmaxfp
, 5, 16),
10570 GEN_VXFORM(vminfp
, 5, 17),
10572 #undef GEN_VXRFORM1
10574 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10575 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10576 #define GEN_VXRFORM(name, opc2, opc3) \
10577 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10578 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10579 GEN_VXRFORM(vcmpequb
, 3, 0)
10580 GEN_VXRFORM(vcmpequh
, 3, 1)
10581 GEN_VXRFORM(vcmpequw
, 3, 2)
10582 GEN_VXRFORM(vcmpgtsb
, 3, 12)
10583 GEN_VXRFORM(vcmpgtsh
, 3, 13)
10584 GEN_VXRFORM(vcmpgtsw
, 3, 14)
10585 GEN_VXRFORM(vcmpgtub
, 3, 8)
10586 GEN_VXRFORM(vcmpgtuh
, 3, 9)
10587 GEN_VXRFORM(vcmpgtuw
, 3, 10)
10588 GEN_VXRFORM_DUAL(vcmpeqfp
, vcmpequd
, 3, 3, PPC_ALTIVEC
, PPC_NONE
)
10589 GEN_VXRFORM(vcmpgefp
, 3, 7)
10590 GEN_VXRFORM_DUAL(vcmpgtfp
, vcmpgtud
, 3, 11, PPC_ALTIVEC
, PPC_NONE
)
10591 GEN_VXRFORM_DUAL(vcmpbfp
, vcmpgtsd
, 3, 15, PPC_ALTIVEC
, PPC_NONE
)
10593 #undef GEN_VXFORM_SIMM
10594 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10595 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10596 GEN_VXFORM_SIMM(vspltisb
, 6, 12),
10597 GEN_VXFORM_SIMM(vspltish
, 6, 13),
10598 GEN_VXFORM_SIMM(vspltisw
, 6, 14),
10600 #undef GEN_VXFORM_NOA
10601 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10602 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10603 GEN_VXFORM_NOA(vupkhsb
, 7, 8),
10604 GEN_VXFORM_NOA(vupkhsh
, 7, 9),
10605 GEN_VXFORM_207(vupkhsw
, 7, 25),
10606 GEN_VXFORM_NOA(vupklsb
, 7, 10),
10607 GEN_VXFORM_NOA(vupklsh
, 7, 11),
10608 GEN_VXFORM_207(vupklsw
, 7, 27),
10609 GEN_VXFORM_NOA(vupkhpx
, 7, 13),
10610 GEN_VXFORM_NOA(vupklpx
, 7, 15),
10611 GEN_VXFORM_NOA(vrefp
, 5, 4),
10612 GEN_VXFORM_NOA(vrsqrtefp
, 5, 5),
10613 GEN_VXFORM_NOA(vexptefp
, 5, 6),
10614 GEN_VXFORM_NOA(vlogefp
, 5, 7),
10615 GEN_VXFORM_NOA(vrfim
, 5, 11),
10616 GEN_VXFORM_NOA(vrfin
, 5, 8),
10617 GEN_VXFORM_NOA(vrfip
, 5, 10),
10618 GEN_VXFORM_NOA(vrfiz
, 5, 9),
10620 #undef GEN_VXFORM_UIMM
10621 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10622 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10623 GEN_VXFORM_UIMM(vspltb
, 6, 8),
10624 GEN_VXFORM_UIMM(vsplth
, 6, 9),
10625 GEN_VXFORM_UIMM(vspltw
, 6, 10),
10626 GEN_VXFORM_UIMM(vcfux
, 5, 12),
10627 GEN_VXFORM_UIMM(vcfsx
, 5, 13),
10628 GEN_VXFORM_UIMM(vctuxs
, 5, 14),
10629 GEN_VXFORM_UIMM(vctsxs
, 5, 15),
10631 #undef GEN_VAFORM_PAIRED
10632 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10633 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10634 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16),
10635 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18),
10636 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19),
10637 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20),
10638 GEN_VAFORM_PAIRED(vsel
, vperm
, 21),
10639 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23),
10641 GEN_VXFORM_DUAL(vclzb
, vpopcntb
, 1, 28, PPC_NONE
, PPC2_ALTIVEC_207
),
10642 GEN_VXFORM_DUAL(vclzh
, vpopcnth
, 1, 29, PPC_NONE
, PPC2_ALTIVEC_207
),
10643 GEN_VXFORM_DUAL(vclzw
, vpopcntw
, 1, 30, PPC_NONE
, PPC2_ALTIVEC_207
),
10644 GEN_VXFORM_DUAL(vclzd
, vpopcntd
, 1, 31, PPC_NONE
, PPC2_ALTIVEC_207
),
10646 GEN_VXFORM_207(vbpermq
, 6, 21),
10647 GEN_VXFORM_207(vgbbd
, 6, 20),
10648 GEN_VXFORM_207(vpmsumb
, 4, 16),
10649 GEN_VXFORM_207(vpmsumh
, 4, 17),
10650 GEN_VXFORM_207(vpmsumw
, 4, 18),
10651 GEN_VXFORM_207(vpmsumd
, 4, 19),
10653 GEN_VXFORM_207(vsbox
, 4, 23),
10655 GEN_VXFORM_DUAL(vcipher
, vcipherlast
, 4, 20, PPC_NONE
, PPC2_ALTIVEC_207
),
10656 GEN_VXFORM_DUAL(vncipher
, vncipherlast
, 4, 21, PPC_NONE
, PPC2_ALTIVEC_207
),
10658 GEN_VXFORM_207(vshasigmaw
, 1, 26),
10659 GEN_VXFORM_207(vshasigmad
, 1, 27),
10661 GEN_VXFORM_DUAL(vsldoi
, vpermxor
, 22, 0xFF, PPC_ALTIVEC
, PPC_NONE
),
10663 GEN_HANDLER_E(lxsdx
, 0x1F, 0x0C, 0x12, 0, PPC_NONE
, PPC2_VSX
),
10664 GEN_HANDLER_E(lxsiwax
, 0x1F, 0x0C, 0x02, 0, PPC_NONE
, PPC2_VSX207
),
10665 GEN_HANDLER_E(lxsiwzx
, 0x1F, 0x0C, 0x00, 0, PPC_NONE
, PPC2_VSX207
),
10666 GEN_HANDLER_E(lxsspx
, 0x1F, 0x0C, 0x10, 0, PPC_NONE
, PPC2_VSX207
),
10667 GEN_HANDLER_E(lxvd2x
, 0x1F, 0x0C, 0x1A, 0, PPC_NONE
, PPC2_VSX
),
10668 GEN_HANDLER_E(lxvdsx
, 0x1F, 0x0C, 0x0A, 0, PPC_NONE
, PPC2_VSX
),
10669 GEN_HANDLER_E(lxvw4x
, 0x1F, 0x0C, 0x18, 0, PPC_NONE
, PPC2_VSX
),
10671 GEN_HANDLER_E(stxsdx
, 0x1F, 0xC, 0x16, 0, PPC_NONE
, PPC2_VSX
),
10672 GEN_HANDLER_E(stxsiwx
, 0x1F, 0xC, 0x04, 0, PPC_NONE
, PPC2_VSX207
),
10673 GEN_HANDLER_E(stxsspx
, 0x1F, 0xC, 0x14, 0, PPC_NONE
, PPC2_VSX207
),
10674 GEN_HANDLER_E(stxvd2x
, 0x1F, 0xC, 0x1E, 0, PPC_NONE
, PPC2_VSX
),
10675 GEN_HANDLER_E(stxvw4x
, 0x1F, 0xC, 0x1C, 0, PPC_NONE
, PPC2_VSX
),
10677 GEN_HANDLER_E(mfvsrwz
, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10678 GEN_HANDLER_E(mtvsrwa
, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10679 GEN_HANDLER_E(mtvsrwz
, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10680 #if defined(TARGET_PPC64)
10681 GEN_HANDLER_E(mfvsrd
, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10682 GEN_HANDLER_E(mtvsrd
, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE
, PPC2_VSX207
),
10686 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10687 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10688 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10691 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10692 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10694 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10695 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10697 #undef GEN_XX2IFORM
10698 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10699 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10701 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10702 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10704 #undef GEN_XX3_RC_FORM
10705 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10708 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10709 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10710 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10711 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10712 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10713 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10715 #undef GEN_XX3FORM_DM
10716 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10717 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10718 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10719 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10720 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10721 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10722 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10723 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10724 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10725 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10726 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10727 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10728 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10729 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10730 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10731 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10732 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10734 GEN_XX2FORM(xsabsdp
, 0x12, 0x15, PPC2_VSX
),
10735 GEN_XX2FORM(xsnabsdp
, 0x12, 0x16, PPC2_VSX
),
10736 GEN_XX2FORM(xsnegdp
, 0x12, 0x17, PPC2_VSX
),
10737 GEN_XX3FORM(xscpsgndp
, 0x00, 0x16, PPC2_VSX
),
10739 GEN_XX2FORM(xvabsdp
, 0x12, 0x1D, PPC2_VSX
),
10740 GEN_XX2FORM(xvnabsdp
, 0x12, 0x1E, PPC2_VSX
),
10741 GEN_XX2FORM(xvnegdp
, 0x12, 0x1F, PPC2_VSX
),
10742 GEN_XX3FORM(xvcpsgndp
, 0x00, 0x1E, PPC2_VSX
),
10743 GEN_XX2FORM(xvabssp
, 0x12, 0x19, PPC2_VSX
),
10744 GEN_XX2FORM(xvnabssp
, 0x12, 0x1A, PPC2_VSX
),
10745 GEN_XX2FORM(xvnegsp
, 0x12, 0x1B, PPC2_VSX
),
10746 GEN_XX3FORM(xvcpsgnsp
, 0x00, 0x1A, PPC2_VSX
),
10748 GEN_XX3FORM(xsadddp
, 0x00, 0x04, PPC2_VSX
),
10749 GEN_XX3FORM(xssubdp
, 0x00, 0x05, PPC2_VSX
),
10750 GEN_XX3FORM(xsmuldp
, 0x00, 0x06, PPC2_VSX
),
10751 GEN_XX3FORM(xsdivdp
, 0x00, 0x07, PPC2_VSX
),
10752 GEN_XX2FORM(xsredp
, 0x14, 0x05, PPC2_VSX
),
10753 GEN_XX2FORM(xssqrtdp
, 0x16, 0x04, PPC2_VSX
),
10754 GEN_XX2FORM(xsrsqrtedp
, 0x14, 0x04, PPC2_VSX
),
10755 GEN_XX3FORM(xstdivdp
, 0x14, 0x07, PPC2_VSX
),
10756 GEN_XX2FORM(xstsqrtdp
, 0x14, 0x06, PPC2_VSX
),
10757 GEN_XX3FORM(xsmaddadp
, 0x04, 0x04, PPC2_VSX
),
10758 GEN_XX3FORM(xsmaddmdp
, 0x04, 0x05, PPC2_VSX
),
10759 GEN_XX3FORM(xsmsubadp
, 0x04, 0x06, PPC2_VSX
),
10760 GEN_XX3FORM(xsmsubmdp
, 0x04, 0x07, PPC2_VSX
),
10761 GEN_XX3FORM(xsnmaddadp
, 0x04, 0x14, PPC2_VSX
),
10762 GEN_XX3FORM(xsnmaddmdp
, 0x04, 0x15, PPC2_VSX
),
10763 GEN_XX3FORM(xsnmsubadp
, 0x04, 0x16, PPC2_VSX
),
10764 GEN_XX3FORM(xsnmsubmdp
, 0x04, 0x17, PPC2_VSX
),
10765 GEN_XX2IFORM(xscmpodp
, 0x0C, 0x05, PPC2_VSX
),
10766 GEN_XX2IFORM(xscmpudp
, 0x0C, 0x04, PPC2_VSX
),
10767 GEN_XX3FORM(xsmaxdp
, 0x00, 0x14, PPC2_VSX
),
10768 GEN_XX3FORM(xsmindp
, 0x00, 0x15, PPC2_VSX
),
10769 GEN_XX2FORM(xscvdpsp
, 0x12, 0x10, PPC2_VSX
),
10770 GEN_XX2FORM(xscvdpspn
, 0x16, 0x10, PPC2_VSX207
),
10771 GEN_XX2FORM(xscvspdp
, 0x12, 0x14, PPC2_VSX
),
10772 GEN_XX2FORM(xscvspdpn
, 0x16, 0x14, PPC2_VSX207
),
10773 GEN_XX2FORM(xscvdpsxds
, 0x10, 0x15, PPC2_VSX
),
10774 GEN_XX2FORM(xscvdpsxws
, 0x10, 0x05, PPC2_VSX
),
10775 GEN_XX2FORM(xscvdpuxds
, 0x10, 0x14, PPC2_VSX
),
10776 GEN_XX2FORM(xscvdpuxws
, 0x10, 0x04, PPC2_VSX
),
10777 GEN_XX2FORM(xscvsxddp
, 0x10, 0x17, PPC2_VSX
),
10778 GEN_XX2FORM(xscvuxddp
, 0x10, 0x16, PPC2_VSX
),
10779 GEN_XX2FORM(xsrdpi
, 0x12, 0x04, PPC2_VSX
),
10780 GEN_XX2FORM(xsrdpic
, 0x16, 0x06, PPC2_VSX
),
10781 GEN_XX2FORM(xsrdpim
, 0x12, 0x07, PPC2_VSX
),
10782 GEN_XX2FORM(xsrdpip
, 0x12, 0x06, PPC2_VSX
),
10783 GEN_XX2FORM(xsrdpiz
, 0x12, 0x05, PPC2_VSX
),
10785 GEN_XX3FORM(xsaddsp
, 0x00, 0x00, PPC2_VSX207
),
10786 GEN_XX3FORM(xssubsp
, 0x00, 0x01, PPC2_VSX207
),
10787 GEN_XX3FORM(xsmulsp
, 0x00, 0x02, PPC2_VSX207
),
10788 GEN_XX3FORM(xsdivsp
, 0x00, 0x03, PPC2_VSX207
),
10789 GEN_XX2FORM(xsresp
, 0x14, 0x01, PPC2_VSX207
),
10790 GEN_XX2FORM(xsrsp
, 0x12, 0x11, PPC2_VSX207
),
10791 GEN_XX2FORM(xssqrtsp
, 0x16, 0x00, PPC2_VSX207
),
10792 GEN_XX2FORM(xsrsqrtesp
, 0x14, 0x00, PPC2_VSX207
),
10793 GEN_XX3FORM(xsmaddasp
, 0x04, 0x00, PPC2_VSX207
),
10794 GEN_XX3FORM(xsmaddmsp
, 0x04, 0x01, PPC2_VSX207
),
10795 GEN_XX3FORM(xsmsubasp
, 0x04, 0x02, PPC2_VSX207
),
10796 GEN_XX3FORM(xsmsubmsp
, 0x04, 0x03, PPC2_VSX207
),
10797 GEN_XX3FORM(xsnmaddasp
, 0x04, 0x10, PPC2_VSX207
),
10798 GEN_XX3FORM(xsnmaddmsp
, 0x04, 0x11, PPC2_VSX207
),
10799 GEN_XX3FORM(xsnmsubasp
, 0x04, 0x12, PPC2_VSX207
),
10800 GEN_XX3FORM(xsnmsubmsp
, 0x04, 0x13, PPC2_VSX207
),
10801 GEN_XX2FORM(xscvsxdsp
, 0x10, 0x13, PPC2_VSX207
),
10802 GEN_XX2FORM(xscvuxdsp
, 0x10, 0x12, PPC2_VSX207
),
10804 GEN_XX3FORM(xvadddp
, 0x00, 0x0C, PPC2_VSX
),
10805 GEN_XX3FORM(xvsubdp
, 0x00, 0x0D, PPC2_VSX
),
10806 GEN_XX3FORM(xvmuldp
, 0x00, 0x0E, PPC2_VSX
),
10807 GEN_XX3FORM(xvdivdp
, 0x00, 0x0F, PPC2_VSX
),
10808 GEN_XX2FORM(xvredp
, 0x14, 0x0D, PPC2_VSX
),
10809 GEN_XX2FORM(xvsqrtdp
, 0x16, 0x0C, PPC2_VSX
),
10810 GEN_XX2FORM(xvrsqrtedp
, 0x14, 0x0C, PPC2_VSX
),
10811 GEN_XX3FORM(xvtdivdp
, 0x14, 0x0F, PPC2_VSX
),
10812 GEN_XX2FORM(xvtsqrtdp
, 0x14, 0x0E, PPC2_VSX
),
10813 GEN_XX3FORM(xvmaddadp
, 0x04, 0x0C, PPC2_VSX
),
10814 GEN_XX3FORM(xvmaddmdp
, 0x04, 0x0D, PPC2_VSX
),
10815 GEN_XX3FORM(xvmsubadp
, 0x04, 0x0E, PPC2_VSX
),
10816 GEN_XX3FORM(xvmsubmdp
, 0x04, 0x0F, PPC2_VSX
),
10817 GEN_XX3FORM(xvnmaddadp
, 0x04, 0x1C, PPC2_VSX
),
10818 GEN_XX3FORM(xvnmaddmdp
, 0x04, 0x1D, PPC2_VSX
),
10819 GEN_XX3FORM(xvnmsubadp
, 0x04, 0x1E, PPC2_VSX
),
10820 GEN_XX3FORM(xvnmsubmdp
, 0x04, 0x1F, PPC2_VSX
),
10821 GEN_XX3FORM(xvmaxdp
, 0x00, 0x1C, PPC2_VSX
),
10822 GEN_XX3FORM(xvmindp
, 0x00, 0x1D, PPC2_VSX
),
10823 GEN_XX3_RC_FORM(xvcmpeqdp
, 0x0C, 0x0C, PPC2_VSX
),
10824 GEN_XX3_RC_FORM(xvcmpgtdp
, 0x0C, 0x0D, PPC2_VSX
),
10825 GEN_XX3_RC_FORM(xvcmpgedp
, 0x0C, 0x0E, PPC2_VSX
),
10826 GEN_XX2FORM(xvcvdpsp
, 0x12, 0x18, PPC2_VSX
),
10827 GEN_XX2FORM(xvcvdpsxds
, 0x10, 0x1D, PPC2_VSX
),
10828 GEN_XX2FORM(xvcvdpsxws
, 0x10, 0x0D, PPC2_VSX
),
10829 GEN_XX2FORM(xvcvdpuxds
, 0x10, 0x1C, PPC2_VSX
),
10830 GEN_XX2FORM(xvcvdpuxws
, 0x10, 0x0C, PPC2_VSX
),
10831 GEN_XX2FORM(xvcvsxddp
, 0x10, 0x1F, PPC2_VSX
),
10832 GEN_XX2FORM(xvcvuxddp
, 0x10, 0x1E, PPC2_VSX
),
10833 GEN_XX2FORM(xvcvsxwdp
, 0x10, 0x0F, PPC2_VSX
),
10834 GEN_XX2FORM(xvcvuxwdp
, 0x10, 0x0E, PPC2_VSX
),
10835 GEN_XX2FORM(xvrdpi
, 0x12, 0x0C, PPC2_VSX
),
10836 GEN_XX2FORM(xvrdpic
, 0x16, 0x0E, PPC2_VSX
),
10837 GEN_XX2FORM(xvrdpim
, 0x12, 0x0F, PPC2_VSX
),
10838 GEN_XX2FORM(xvrdpip
, 0x12, 0x0E, PPC2_VSX
),
10839 GEN_XX2FORM(xvrdpiz
, 0x12, 0x0D, PPC2_VSX
),
10841 GEN_XX3FORM(xvaddsp
, 0x00, 0x08, PPC2_VSX
),
10842 GEN_XX3FORM(xvsubsp
, 0x00, 0x09, PPC2_VSX
),
10843 GEN_XX3FORM(xvmulsp
, 0x00, 0x0A, PPC2_VSX
),
10844 GEN_XX3FORM(xvdivsp
, 0x00, 0x0B, PPC2_VSX
),
10845 GEN_XX2FORM(xvresp
, 0x14, 0x09, PPC2_VSX
),
10846 GEN_XX2FORM(xvsqrtsp
, 0x16, 0x08, PPC2_VSX
),
10847 GEN_XX2FORM(xvrsqrtesp
, 0x14, 0x08, PPC2_VSX
),
10848 GEN_XX3FORM(xvtdivsp
, 0x14, 0x0B, PPC2_VSX
),
10849 GEN_XX2FORM(xvtsqrtsp
, 0x14, 0x0A, PPC2_VSX
),
10850 GEN_XX3FORM(xvmaddasp
, 0x04, 0x08, PPC2_VSX
),
10851 GEN_XX3FORM(xvmaddmsp
, 0x04, 0x09, PPC2_VSX
),
10852 GEN_XX3FORM(xvmsubasp
, 0x04, 0x0A, PPC2_VSX
),
10853 GEN_XX3FORM(xvmsubmsp
, 0x04, 0x0B, PPC2_VSX
),
10854 GEN_XX3FORM(xvnmaddasp
, 0x04, 0x18, PPC2_VSX
),
10855 GEN_XX3FORM(xvnmaddmsp
, 0x04, 0x19, PPC2_VSX
),
10856 GEN_XX3FORM(xvnmsubasp
, 0x04, 0x1A, PPC2_VSX
),
10857 GEN_XX3FORM(xvnmsubmsp
, 0x04, 0x1B, PPC2_VSX
),
10858 GEN_XX3FORM(xvmaxsp
, 0x00, 0x18, PPC2_VSX
),
10859 GEN_XX3FORM(xvminsp
, 0x00, 0x19, PPC2_VSX
),
10860 GEN_XX3_RC_FORM(xvcmpeqsp
, 0x0C, 0x08, PPC2_VSX
),
10861 GEN_XX3_RC_FORM(xvcmpgtsp
, 0x0C, 0x09, PPC2_VSX
),
10862 GEN_XX3_RC_FORM(xvcmpgesp
, 0x0C, 0x0A, PPC2_VSX
),
10863 GEN_XX2FORM(xvcvspdp
, 0x12, 0x1C, PPC2_VSX
),
10864 GEN_XX2FORM(xvcvspsxds
, 0x10, 0x19, PPC2_VSX
),
10865 GEN_XX2FORM(xvcvspsxws
, 0x10, 0x09, PPC2_VSX
),
10866 GEN_XX2FORM(xvcvspuxds
, 0x10, 0x18, PPC2_VSX
),
10867 GEN_XX2FORM(xvcvspuxws
, 0x10, 0x08, PPC2_VSX
),
10868 GEN_XX2FORM(xvcvsxdsp
, 0x10, 0x1B, PPC2_VSX
),
10869 GEN_XX2FORM(xvcvuxdsp
, 0x10, 0x1A, PPC2_VSX
),
10870 GEN_XX2FORM(xvcvsxwsp
, 0x10, 0x0B, PPC2_VSX
),
10871 GEN_XX2FORM(xvcvuxwsp
, 0x10, 0x0A, PPC2_VSX
),
10872 GEN_XX2FORM(xvrspi
, 0x12, 0x08, PPC2_VSX
),
10873 GEN_XX2FORM(xvrspic
, 0x16, 0x0A, PPC2_VSX
),
10874 GEN_XX2FORM(xvrspim
, 0x12, 0x0B, PPC2_VSX
),
10875 GEN_XX2FORM(xvrspip
, 0x12, 0x0A, PPC2_VSX
),
10876 GEN_XX2FORM(xvrspiz
, 0x12, 0x09, PPC2_VSX
),
10879 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10880 GEN_XX3FORM(name, opc2, opc3, fl2)
10882 VSX_LOGICAL(xxland
, 0x8, 0x10, PPC2_VSX
),
10883 VSX_LOGICAL(xxlandc
, 0x8, 0x11, PPC2_VSX
),
10884 VSX_LOGICAL(xxlor
, 0x8, 0x12, PPC2_VSX
),
10885 VSX_LOGICAL(xxlxor
, 0x8, 0x13, PPC2_VSX
),
10886 VSX_LOGICAL(xxlnor
, 0x8, 0x14, PPC2_VSX
),
10887 VSX_LOGICAL(xxleqv
, 0x8, 0x17, PPC2_VSX207
),
10888 VSX_LOGICAL(xxlnand
, 0x8, 0x16, PPC2_VSX207
),
10889 VSX_LOGICAL(xxlorc
, 0x8, 0x15, PPC2_VSX207
),
10890 GEN_XX3FORM(xxmrghw
, 0x08, 0x02, PPC2_VSX
),
10891 GEN_XX3FORM(xxmrglw
, 0x08, 0x06, PPC2_VSX
),
10892 GEN_XX2FORM(xxspltw
, 0x08, 0x0A, PPC2_VSX
),
10893 GEN_XX3FORM_DM(xxsldwi
, 0x08, 0x00),
10895 #define GEN_XXSEL_ROW(opc3) \
10896 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10897 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10898 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10899 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10900 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10901 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10902 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10903 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10905 GEN_XXSEL_ROW(0x00)
10906 GEN_XXSEL_ROW(0x01)
10907 GEN_XXSEL_ROW(0x02)
10908 GEN_XXSEL_ROW(0x03)
10909 GEN_XXSEL_ROW(0x04)
10910 GEN_XXSEL_ROW(0x05)
10911 GEN_XXSEL_ROW(0x06)
10912 GEN_XXSEL_ROW(0x07)
10913 GEN_XXSEL_ROW(0x08)
10914 GEN_XXSEL_ROW(0x09)
10915 GEN_XXSEL_ROW(0x0A)
10916 GEN_XXSEL_ROW(0x0B)
10917 GEN_XXSEL_ROW(0x0C)
10918 GEN_XXSEL_ROW(0x0D)
10919 GEN_XXSEL_ROW(0x0E)
10920 GEN_XXSEL_ROW(0x0F)
10921 GEN_XXSEL_ROW(0x10)
10922 GEN_XXSEL_ROW(0x11)
10923 GEN_XXSEL_ROW(0x12)
10924 GEN_XXSEL_ROW(0x13)
10925 GEN_XXSEL_ROW(0x14)
10926 GEN_XXSEL_ROW(0x15)
10927 GEN_XXSEL_ROW(0x16)
10928 GEN_XXSEL_ROW(0x17)
10929 GEN_XXSEL_ROW(0x18)
10930 GEN_XXSEL_ROW(0x19)
10931 GEN_XXSEL_ROW(0x1A)
10932 GEN_XXSEL_ROW(0x1B)
10933 GEN_XXSEL_ROW(0x1C)
10934 GEN_XXSEL_ROW(0x1D)
10935 GEN_XXSEL_ROW(0x1E)
10936 GEN_XXSEL_ROW(0x1F)
10938 GEN_XX3FORM_DM(xxpermdi
, 0x08, 0x01),
10940 #undef GEN_DFP_T_A_B_Rc
10941 #undef GEN_DFP_BF_A_B
10942 #undef GEN_DFP_BF_A_DCM
10943 #undef GEN_DFP_T_B_U32_U32_Rc
10944 #undef GEN_DFP_T_A_B_I32_Rc
10945 #undef GEN_DFP_T_B_Rc
10946 #undef GEN_DFP_T_FPR_I32_Rc
10948 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10949 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10951 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10952 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10953 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10955 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10956 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10957 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10958 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10959 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10961 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10962 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10964 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10965 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10966 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10968 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10969 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10970 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10971 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10972 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10974 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10975 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10977 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10978 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10980 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10981 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10983 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10984 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10986 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10987 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10989 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10990 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10992 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10993 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10995 #define GEN_DFP_BF_A_B(name, op1, op2) \
10996 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10998 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10999 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11001 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11002 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11004 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11005 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11007 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11008 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11010 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11011 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11013 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11014 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11016 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11017 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11019 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11020 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11022 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11023 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11025 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11026 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11028 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11029 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11031 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11032 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11034 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11035 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11037 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11038 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11040 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11041 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11043 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11044 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11046 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11047 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11049 GEN_DFP_T_A_B_Rc(dadd
, 0x02, 0x00),
11050 GEN_DFP_Tp_Ap_Bp_Rc(daddq
, 0x02, 0x00),
11051 GEN_DFP_T_A_B_Rc(dsub
, 0x02, 0x10),
11052 GEN_DFP_Tp_Ap_Bp_Rc(dsubq
, 0x02, 0x10),
11053 GEN_DFP_T_A_B_Rc(dmul
, 0x02, 0x01),
11054 GEN_DFP_Tp_Ap_Bp_Rc(dmulq
, 0x02, 0x01),
11055 GEN_DFP_T_A_B_Rc(ddiv
, 0x02, 0x11),
11056 GEN_DFP_Tp_Ap_Bp_Rc(ddivq
, 0x02, 0x11),
11057 GEN_DFP_BF_A_B(dcmpu
, 0x02, 0x14),
11058 GEN_DFP_BF_Ap_Bp(dcmpuq
, 0x02, 0x14),
11059 GEN_DFP_BF_A_B(dcmpo
, 0x02, 0x04),
11060 GEN_DFP_BF_Ap_Bp(dcmpoq
, 0x02, 0x04),
11061 GEN_DFP_BF_A_DCM(dtstdc
, 0x02, 0x06),
11062 GEN_DFP_BF_Ap_DCM(dtstdcq
, 0x02, 0x06),
11063 GEN_DFP_BF_A_DCM(dtstdg
, 0x02, 0x07),
11064 GEN_DFP_BF_Ap_DCM(dtstdgq
, 0x02, 0x07),
11065 GEN_DFP_BF_A_B(dtstex
, 0x02, 0x05),
11066 GEN_DFP_BF_Ap_Bp(dtstexq
, 0x02, 0x05),
11067 GEN_DFP_BF_A_B(dtstsf
, 0x02, 0x15),
11068 GEN_DFP_BF_A_Bp(dtstsfq
, 0x02, 0x15),
11069 GEN_DFP_TE_T_B_RMC_Rc(dquai
, 0x03, 0x02),
11070 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq
, 0x03, 0x02),
11071 GEN_DFP_T_A_B_RMC_Rc(dqua
, 0x03, 0x00),
11072 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq
, 0x03, 0x00),
11073 GEN_DFP_T_A_B_RMC_Rc(drrnd
, 0x03, 0x01),
11074 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq
, 0x03, 0x01),
11075 GEN_DFP_R_T_B_RMC_Rc(drintx
, 0x03, 0x03),
11076 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq
, 0x03, 0x03),
11077 GEN_DFP_R_T_B_RMC_Rc(drintn
, 0x03, 0x07),
11078 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq
, 0x03, 0x07),
11079 GEN_DFP_T_B_Rc(dctdp
, 0x02, 0x08),
11080 GEN_DFP_Tp_B_Rc(dctqpq
, 0x02, 0x08),
11081 GEN_DFP_T_B_Rc(drsp
, 0x02, 0x18),
11082 GEN_DFP_Tp_Bp_Rc(drdpq
, 0x02, 0x18),
11083 GEN_DFP_T_B_Rc(dcffix
, 0x02, 0x19),
11084 GEN_DFP_Tp_B_Rc(dcffixq
, 0x02, 0x19),
11085 GEN_DFP_T_B_Rc(dctfix
, 0x02, 0x09),
11086 GEN_DFP_T_Bp_Rc(dctfixq
, 0x02, 0x09),
11087 GEN_DFP_SP_T_B_Rc(ddedpd
, 0x02, 0x0a),
11088 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq
, 0x02, 0x0a),
11089 GEN_DFP_S_T_B_Rc(denbcd
, 0x02, 0x1a),
11090 GEN_DFP_S_Tp_Bp_Rc(denbcdq
, 0x02, 0x1a),
11091 GEN_DFP_T_B_Rc(dxex
, 0x02, 0x0b),
11092 GEN_DFP_T_Bp_Rc(dxexq
, 0x02, 0x0b),
11093 GEN_DFP_T_A_B_Rc(diex
, 0x02, 0x1b),
11094 GEN_DFP_Tp_A_Bp_Rc(diexq
, 0x02, 0x1b),
11095 GEN_DFP_T_A_SH_Rc(dscli
, 0x02, 0x02),
11096 GEN_DFP_Tp_Ap_SH_Rc(dscliq
, 0x02, 0x02),
11097 GEN_DFP_T_A_SH_Rc(dscri
, 0x02, 0x03),
11098 GEN_DFP_Tp_Ap_SH_Rc(dscriq
, 0x02, 0x03),
11101 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11102 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11103 GEN_SPE(evaddw
, speundef
, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11104 GEN_SPE(evaddiw
, speundef
, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11105 GEN_SPE(evsubfw
, speundef
, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11106 GEN_SPE(evsubifw
, speundef
, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11107 GEN_SPE(evabs
, evneg
, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11108 GEN_SPE(evextsb
, evextsh
, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11109 GEN_SPE(evrndw
, evcntlzw
, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE
),
11110 GEN_SPE(evcntlsw
, brinc
, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE
),
11111 GEN_SPE(evmra
, speundef
, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE
),
11112 GEN_SPE(speundef
, evand
, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11113 GEN_SPE(evandc
, speundef
, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11114 GEN_SPE(evxor
, evor
, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11115 GEN_SPE(evnor
, eveqv
, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11116 GEN_SPE(evmwumi
, evmwsmi
, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11117 GEN_SPE(evmwumia
, evmwsmia
, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE
),
11118 GEN_SPE(evmwumiaa
, evmwsmiaa
, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE
),
11119 GEN_SPE(speundef
, evorc
, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE
),
11120 GEN_SPE(evnand
, speundef
, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11121 GEN_SPE(evsrwu
, evsrws
, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11122 GEN_SPE(evsrwiu
, evsrwis
, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11123 GEN_SPE(evslw
, speundef
, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11124 GEN_SPE(evslwi
, speundef
, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE
),
11125 GEN_SPE(evrlw
, evsplati
, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11126 GEN_SPE(evrlwi
, evsplatfi
, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE
),
11127 GEN_SPE(evmergehi
, evmergelo
, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11128 GEN_SPE(evmergehilo
, evmergelohi
, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE
),
11129 GEN_SPE(evcmpgtu
, evcmpgts
, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11130 GEN_SPE(evcmpltu
, evcmplts
, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE
),
11131 GEN_SPE(evcmpeq
, speundef
, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE
),
11133 GEN_SPE(evfsadd
, evfssub
, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11134 GEN_SPE(evfsabs
, evfsnabs
, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11135 GEN_SPE(evfsneg
, speundef
, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11136 GEN_SPE(evfsmul
, evfsdiv
, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11137 GEN_SPE(evfscmpgt
, evfscmplt
, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11138 GEN_SPE(evfscmpeq
, speundef
, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11139 GEN_SPE(evfscfui
, evfscfsi
, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11140 GEN_SPE(evfscfuf
, evfscfsf
, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11141 GEN_SPE(evfsctui
, evfsctsi
, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11142 GEN_SPE(evfsctuf
, evfsctsf
, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11143 GEN_SPE(evfsctuiz
, speundef
, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11144 GEN_SPE(evfsctsiz
, speundef
, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11145 GEN_SPE(evfststgt
, evfststlt
, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11146 GEN_SPE(evfststeq
, speundef
, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11148 GEN_SPE(efsadd
, efssub
, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11149 GEN_SPE(efsabs
, efsnabs
, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE
),
11150 GEN_SPE(efsneg
, speundef
, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11151 GEN_SPE(efsmul
, efsdiv
, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE
),
11152 GEN_SPE(efscmpgt
, efscmplt
, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11153 GEN_SPE(efscmpeq
, efscfd
, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE
),
11154 GEN_SPE(efscfui
, efscfsi
, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11155 GEN_SPE(efscfuf
, efscfsf
, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11156 GEN_SPE(efsctui
, efsctsi
, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11157 GEN_SPE(efsctuf
, efsctsf
, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE
),
11158 GEN_SPE(efsctuiz
, speundef
, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11159 GEN_SPE(efsctsiz
, speundef
, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11160 GEN_SPE(efststgt
, efststlt
, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE
),
11161 GEN_SPE(efststeq
, speundef
, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE
),
11163 GEN_SPE(efdadd
, efdsub
, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11164 GEN_SPE(efdcfuid
, efdcfsid
, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11165 GEN_SPE(efdabs
, efdnabs
, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE
),
11166 GEN_SPE(efdneg
, speundef
, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11167 GEN_SPE(efdmul
, efddiv
, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE
),
11168 GEN_SPE(efdctuidz
, efdctsidz
, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11169 GEN_SPE(efdcmpgt
, efdcmplt
, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11170 GEN_SPE(efdcmpeq
, efdcfs
, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE
),
11171 GEN_SPE(efdcfui
, efdcfsi
, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11172 GEN_SPE(efdcfuf
, efdcfsf
, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11173 GEN_SPE(efdctui
, efdctsi
, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11174 GEN_SPE(efdctuf
, efdctsf
, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE
),
11175 GEN_SPE(efdctuiz
, speundef
, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11176 GEN_SPE(efdctsiz
, speundef
, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11177 GEN_SPE(efdtstgt
, efdtstlt
, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE
),
11178 GEN_SPE(efdtsteq
, speundef
, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE
),
11180 #undef GEN_SPEOP_LDST
11181 #define GEN_SPEOP_LDST(name, opc2, sh) \
11182 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11183 GEN_SPEOP_LDST(evldd
, 0x00, 3),
11184 GEN_SPEOP_LDST(evldw
, 0x01, 3),
11185 GEN_SPEOP_LDST(evldh
, 0x02, 3),
11186 GEN_SPEOP_LDST(evlhhesplat
, 0x04, 1),
11187 GEN_SPEOP_LDST(evlhhousplat
, 0x06, 1),
11188 GEN_SPEOP_LDST(evlhhossplat
, 0x07, 1),
11189 GEN_SPEOP_LDST(evlwhe
, 0x08, 2),
11190 GEN_SPEOP_LDST(evlwhou
, 0x0A, 2),
11191 GEN_SPEOP_LDST(evlwhos
, 0x0B, 2),
11192 GEN_SPEOP_LDST(evlwwsplat
, 0x0C, 2),
11193 GEN_SPEOP_LDST(evlwhsplat
, 0x0E, 2),
11195 GEN_SPEOP_LDST(evstdd
, 0x10, 3),
11196 GEN_SPEOP_LDST(evstdw
, 0x11, 3),
11197 GEN_SPEOP_LDST(evstdh
, 0x12, 3),
11198 GEN_SPEOP_LDST(evstwhe
, 0x18, 2),
11199 GEN_SPEOP_LDST(evstwho
, 0x1A, 2),
11200 GEN_SPEOP_LDST(evstwwe
, 0x1C, 2),
11201 GEN_SPEOP_LDST(evstwwo
, 0x1E, 2),
11203 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11204 PPC_NONE
, PPC2_TM
),
11205 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11206 PPC_NONE
, PPC2_TM
),
11207 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11208 PPC_NONE
, PPC2_TM
),
11209 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11210 PPC_NONE
, PPC2_TM
),
11211 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11212 PPC_NONE
, PPC2_TM
),
11213 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11214 PPC_NONE
, PPC2_TM
),
11215 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11216 PPC_NONE
, PPC2_TM
),
11217 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11218 PPC_NONE
, PPC2_TM
),
11219 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11220 PPC_NONE
, PPC2_TM
),
11221 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11222 PPC_NONE
, PPC2_TM
),
11223 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11224 PPC_NONE
, PPC2_TM
),
11227 #include "helper_regs.h"
11228 #include "translate_init.c"
11230 /*****************************************************************************/
11231 /* Misc PowerPC helpers */
11232 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
11238 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11239 CPUPPCState
*env
= &cpu
->env
;
11242 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
11243 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
11244 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
11246 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
11247 TARGET_FMT_lx
" iidx %d didx %d\n",
11248 env
->msr
, env
->spr
[SPR_HID0
],
11249 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
11250 #if !defined(NO_TIMER_DUMP)
11251 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
11252 #if !defined(CONFIG_USER_ONLY)
11256 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
11257 #if !defined(CONFIG_USER_ONLY)
11258 , cpu_ppc_load_decr(env
)
11262 for (i
= 0; i
< 32; i
++) {
11263 if ((i
& (RGPL
- 1)) == 0)
11264 cpu_fprintf(f
, "GPR%02d", i
);
11265 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
11266 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
11267 cpu_fprintf(f
, "\n");
11269 cpu_fprintf(f
, "CR ");
11270 for (i
= 0; i
< 8; i
++)
11271 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
11272 cpu_fprintf(f
, " [");
11273 for (i
= 0; i
< 8; i
++) {
11275 if (env
->crf
[i
] & 0x08)
11277 else if (env
->crf
[i
] & 0x04)
11279 else if (env
->crf
[i
] & 0x02)
11281 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
11283 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
11284 env
->reserve_addr
);
11285 for (i
= 0; i
< 32; i
++) {
11286 if ((i
& (RFPL
- 1)) == 0)
11287 cpu_fprintf(f
, "FPR%02d", i
);
11288 cpu_fprintf(f
, " %016" PRIx64
, *((uint64_t *)&env
->fpr
[i
]));
11289 if ((i
& (RFPL
- 1)) == (RFPL
- 1))
11290 cpu_fprintf(f
, "\n");
11292 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
11293 #if !defined(CONFIG_USER_ONLY)
11294 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
11295 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
11296 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
11297 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
11299 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
11300 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
11301 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
11302 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
11304 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
11305 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
11306 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
11307 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
11309 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
11310 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
11311 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
11312 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
11313 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
11315 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
11316 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
11317 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
11318 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
11320 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
11321 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
11322 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
11323 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
11325 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
11326 " EPR " TARGET_FMT_lx
"\n",
11327 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
11328 env
->spr
[SPR_BOOKE_EPR
]);
11331 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
11332 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
11333 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
11334 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
11337 * IVORs are left out as they are large and do not change often --
11338 * they can be read with "p $ivor0", "p $ivor1", etc.
11342 #if defined(TARGET_PPC64)
11343 if (env
->flags
& POWERPC_FLAG_CFAR
) {
11344 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
11348 switch (env
->mmu_model
) {
11349 case POWERPC_MMU_32B
:
11350 case POWERPC_MMU_601
:
11351 case POWERPC_MMU_SOFT_6xx
:
11352 case POWERPC_MMU_SOFT_74xx
:
11353 #if defined(TARGET_PPC64)
11354 case POWERPC_MMU_64B
:
11355 case POWERPC_MMU_2_03
:
11356 case POWERPC_MMU_2_06
:
11357 case POWERPC_MMU_2_06a
:
11358 case POWERPC_MMU_2_07
:
11359 case POWERPC_MMU_2_07a
:
11361 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" DAR " TARGET_FMT_lx
11362 " DSISR " TARGET_FMT_lx
"\n", env
->spr
[SPR_SDR1
],
11363 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
11365 case POWERPC_MMU_BOOKE206
:
11366 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
11367 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
11368 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
11369 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
11371 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
11372 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
11373 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
11374 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
11376 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
11377 " TLB1CFG " TARGET_FMT_lx
"\n",
11378 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
11379 env
->spr
[SPR_BOOKE_TLB1CFG
]);
11390 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
11391 fprintf_function cpu_fprintf
, int flags
)
11393 #if defined(DO_PPC_STATISTICS)
11394 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
11395 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
11398 t1
= cpu
->env
.opcodes
;
11399 for (op1
= 0; op1
< 64; op1
++) {
11401 if (is_indirect_opcode(handler
)) {
11402 t2
= ind_table(handler
);
11403 for (op2
= 0; op2
< 32; op2
++) {
11405 if (is_indirect_opcode(handler
)) {
11406 t3
= ind_table(handler
);
11407 for (op3
= 0; op3
< 32; op3
++) {
11409 if (handler
->count
== 0)
11411 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
11412 "%016" PRIx64
" %" PRId64
"\n",
11413 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
11415 handler
->count
, handler
->count
);
11418 if (handler
->count
== 0)
11420 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
11421 "%016" PRIx64
" %" PRId64
"\n",
11422 op1
, op2
, op1
, op2
, handler
->oname
,
11423 handler
->count
, handler
->count
);
11427 if (handler
->count
== 0)
11429 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
11431 op1
, op1
, handler
->oname
,
11432 handler
->count
, handler
->count
);
11438 /*****************************************************************************/
11439 void gen_intermediate_code(CPUPPCState
*env
, struct TranslationBlock
*tb
)
11441 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
11442 CPUState
*cs
= CPU(cpu
);
11443 DisasContext ctx
, *ctxp
= &ctx
;
11444 opc_handler_t
**table
, *handler
;
11445 target_ulong pc_start
;
11450 ctx
.nip
= pc_start
;
11452 ctx
.exception
= POWERPC_EXCP_NONE
;
11453 ctx
.spr_cb
= env
->spr_cb
;
11455 ctx
.mem_idx
= env
->dmmu_idx
;
11456 #if !defined(CONFIG_USER_ONLY)
11457 ctx
.hv
= msr_hv
|| !env
->has_hv_mode
;
11459 ctx
.insns_flags
= env
->insns_flags
;
11460 ctx
.insns_flags2
= env
->insns_flags2
;
11461 ctx
.access_type
= -1;
11462 ctx
.le_mode
= env
->hflags
& (1 << MSR_LE
) ? 1 : 0;
11463 ctx
.default_tcg_memop_mask
= ctx
.le_mode
? MO_LE
: MO_BE
;
11464 #if defined(TARGET_PPC64)
11465 ctx
.sf_mode
= msr_is_64bit(env
, env
->msr
);
11466 ctx
.has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
11468 if (env
->mmu_model
== POWERPC_MMU_32B
||
11469 env
->mmu_model
== POWERPC_MMU_601
||
11470 (env
->mmu_model
& POWERPC_MMU_64B
))
11471 ctx
.lazy_tlb_flush
= true;
11473 ctx
.fpu_enabled
= msr_fp
;
11474 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
11475 ctx
.spe_enabled
= msr_spe
;
11477 ctx
.spe_enabled
= 0;
11478 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
11479 ctx
.altivec_enabled
= msr_vr
;
11481 ctx
.altivec_enabled
= 0;
11482 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
11483 ctx
.vsx_enabled
= msr_vsx
;
11485 ctx
.vsx_enabled
= 0;
11487 #if defined(TARGET_PPC64)
11488 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
11489 ctx
.tm_enabled
= msr_tm
;
11491 ctx
.tm_enabled
= 0;
11494 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
11495 ctx
.singlestep_enabled
= CPU_SINGLE_STEP
;
11497 ctx
.singlestep_enabled
= 0;
11498 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
11499 ctx
.singlestep_enabled
|= CPU_BRANCH_STEP
;
11500 if (unlikely(cs
->singlestep_enabled
)) {
11501 ctx
.singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
11503 #if defined (DO_SINGLE_STEP) && 0
11504 /* Single step trace mode */
11508 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11509 if (max_insns
== 0) {
11510 max_insns
= CF_COUNT_MASK
;
11512 if (max_insns
> TCG_MAX_INSNS
) {
11513 max_insns
= TCG_MAX_INSNS
;
11517 tcg_clear_temp_count();
11518 /* Set env in case of segfault during code fetch */
11519 while (ctx
.exception
== POWERPC_EXCP_NONE
&& !tcg_op_buf_full()) {
11520 tcg_gen_insn_start(ctx
.nip
);
11523 if (unlikely(cpu_breakpoint_test(cs
, ctx
.nip
, BP_ANY
))) {
11524 gen_debug_exception(ctxp
);
11525 /* The address covered by the breakpoint must be included in
11526 [tb->pc, tb->pc + tb->size) in order to for it to be
11527 properly cleared -- thus we increment the PC here so that
11528 the logic setting tb->size below does the right thing. */
11533 LOG_DISAS("----------------\n");
11534 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
11535 ctx
.nip
, ctx
.mem_idx
, (int)msr_ir
);
11536 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
))
11538 if (unlikely(need_byteswap(&ctx
))) {
11539 ctx
.opcode
= bswap32(cpu_ldl_code(env
, ctx
.nip
));
11541 ctx
.opcode
= cpu_ldl_code(env
, ctx
.nip
);
11543 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11544 ctx
.opcode
, opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11545 opc3(ctx
.opcode
), ctx
.le_mode
? "little" : "big");
11547 table
= env
->opcodes
;
11548 handler
= table
[opc1(ctx
.opcode
)];
11549 if (is_indirect_opcode(handler
)) {
11550 table
= ind_table(handler
);
11551 handler
= table
[opc2(ctx
.opcode
)];
11552 if (is_indirect_opcode(handler
)) {
11553 table
= ind_table(handler
);
11554 handler
= table
[opc3(ctx
.opcode
)];
11557 /* Is opcode *REALLY* valid ? */
11558 if (unlikely(handler
->handler
== &gen_invalid
)) {
11559 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
11560 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
" %d\n",
11561 opc1(ctx
.opcode
), opc2(ctx
.opcode
),
11562 opc3(ctx
.opcode
), ctx
.opcode
, ctx
.nip
- 4, (int)msr_ir
);
11566 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
) && Rc(ctx
.opcode
))) {
11567 inval
= handler
->inval2
;
11569 inval
= handler
->inval1
;
11572 if (unlikely((ctx
.opcode
& inval
) != 0)) {
11573 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
11574 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx
"\n",
11575 ctx
.opcode
& inval
, opc1(ctx
.opcode
),
11576 opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11577 ctx
.opcode
, ctx
.nip
- 4);
11578 gen_inval_exception(ctxp
, POWERPC_EXCP_INVAL_INVAL
);
11582 (*(handler
->handler
))(&ctx
);
11583 #if defined(DO_PPC_STATISTICS)
11586 /* Check trace mode exceptions */
11587 if (unlikely(ctx
.singlestep_enabled
& CPU_SINGLE_STEP
&&
11588 (ctx
.nip
<= 0x100 || ctx
.nip
> 0xF00) &&
11589 ctx
.exception
!= POWERPC_SYSCALL
&&
11590 ctx
.exception
!= POWERPC_EXCP_TRAP
&&
11591 ctx
.exception
!= POWERPC_EXCP_BRANCH
)) {
11592 gen_exception(ctxp
, POWERPC_EXCP_TRACE
);
11593 } else if (unlikely(((ctx
.nip
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
11594 (cs
->singlestep_enabled
) ||
11596 num_insns
>= max_insns
)) {
11597 /* if we reach a page boundary or are single stepping, stop
11602 if (tcg_check_temp_count()) {
11603 fprintf(stderr
, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11604 opc1(ctx
.opcode
), opc2(ctx
.opcode
), opc3(ctx
.opcode
),
11609 if (tb
->cflags
& CF_LAST_IO
)
11611 if (ctx
.exception
== POWERPC_EXCP_NONE
) {
11612 gen_goto_tb(&ctx
, 0, ctx
.nip
);
11613 } else if (ctx
.exception
!= POWERPC_EXCP_BRANCH
) {
11614 if (unlikely(cs
->singlestep_enabled
)) {
11615 gen_debug_exception(ctxp
);
11617 /* Generate the return instruction */
11618 tcg_gen_exit_tb(0);
11620 gen_tb_end(tb
, num_insns
);
11622 tb
->size
= ctx
.nip
- pc_start
;
11623 tb
->icount
= num_insns
;
11625 #if defined(DEBUG_DISAS)
11626 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
11627 && qemu_log_in_addr_range(pc_start
)) {
11629 flags
= env
->bfd_mach
;
11630 flags
|= ctx
.le_mode
<< 16;
11631 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11632 log_target_disas(cs
, pc_start
, ctx
.nip
- pc_start
, flags
);
11638 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,
11639 target_ulong
*data
)
11641 env
->nip
= data
[0];