hw/xio3130_downstream.c

   1 /*
   2  * x3130_downstream.c
   3  * TI X3130 pci express downstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "hw/pci/pci_ids.h"
  23 #include "hw/pci/msi.h"
  24 #include "hw/pci/pcie.h"
  25 #include "hw/xio3130_downstream.h"
  26
  27 #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
  28 #define XIO3130_REVISION                0x1
  29 #define XIO3130_MSI_OFFSET              0x70
  30 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  31 #define XIO3130_MSI_NR_VECTOR           1
  32 #define XIO3130_SSVID_OFFSET            0x80
  33 #define XIO3130_SSVID_SVID              0
  34 #define XIO3130_SSVID_SSID              0
  35 #define XIO3130_EXP_OFFSET              0x90
  36 #define XIO3130_AER_OFFSET              0x100
  37
  38 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
  39                                          uint32_t val, int len)
  40 {
  41     pci_bridge_write_config(d, address, val, len);
  42     pcie_cap_flr_write_config(d, address, val, len);
  43     pcie_cap_slot_write_config(d, address, val, len);
  44     pcie_aer_write_config(d, address, val, len);
  45 }
  46
  47 static void xio3130_downstream_reset(DeviceState *qdev)
  48 {
  49     PCIDevice *d = PCI_DEVICE(qdev);
  50
  51     pcie_cap_deverr_reset(d);
  52     pcie_cap_slot_reset(d);
  53     pcie_cap_ari_reset(d);
  54     pci_bridge_reset(qdev);
  55 }
  56
  57 static int xio3130_downstream_initfn(PCIDevice *d)
  58 {
  59     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  60     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  61     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
  62     int rc;
  63
  64     rc = pci_bridge_initfn(d);
  65     if (rc < 0) {
  66         return rc;
  67     }
  68
  69     pcie_port_init_reg(d);
  70
  71     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  72                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  73                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  74     if (rc < 0) {
  75         goto err_bridge;
  76     }
  77     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  78                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  79     if (rc < 0) {
  80         goto err_bridge;
  81     }
  82     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
  83                        p->port);
  84     if (rc < 0) {
  85         goto err_msi;
  86     }
  87     pcie_cap_flr_init(d);
  88     pcie_cap_deverr_init(d);
  89     pcie_cap_slot_init(d, s->slot);
  90     pcie_chassis_create(s->chassis);
  91     rc = pcie_chassis_add_slot(s);
  92     if (rc < 0) {
  93         goto err_pcie_cap;
  94     }
  95     pcie_cap_ari_init(d);
  96     rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
  97     if (rc < 0) {
  98         goto err;
  99     }
 100
 101     return 0;
 102
 103 err:
 104     pcie_chassis_del_slot(s);
 105 err_pcie_cap:
 106     pcie_cap_exit(d);
 107 err_msi:
 108     msi_uninit(d);
 109 err_bridge:
 110     pci_bridge_exitfn(d);
 111     return rc;
 112 }
 113
 114 static void xio3130_downstream_exitfn(PCIDevice *d)
 115 {
 116     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
 117     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
 118     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
 119
 120     pcie_aer_exit(d);
 121     pcie_chassis_del_slot(s);
 122     pcie_cap_exit(d);
 123     msi_uninit(d);
 124     pci_bridge_exitfn(d);
 125 }
 126
 127 PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
 128                                   const char *bus_name, pci_map_irq_fn map_irq,
 129                                   uint8_t port, uint8_t chassis,
 130                                   uint16_t slot)
 131 {
 132     PCIDevice *d;
 133     PCIBridge *br;
 134     DeviceState *qdev;
 135
 136     d = pci_create_multifunction(bus, devfn, multifunction,
 137                                  "xio3130-downstream");
 138     if (!d) {
 139         return NULL;
 140     }
 141     br = DO_UPCAST(PCIBridge, dev, d);
 142
 143     qdev = &br->dev.qdev;
 144     pci_bridge_map_irq(br, bus_name, map_irq);
 145     qdev_prop_set_uint8(qdev, "port", port);
 146     qdev_prop_set_uint8(qdev, "chassis", chassis);
 147     qdev_prop_set_uint16(qdev, "slot", slot);
 148     qdev_init_nofail(qdev);
 149
 150     return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
 151 }
 152
 153 static const VMStateDescription vmstate_xio3130_downstream = {
 154     .name = "xio3130-express-downstream-port",
 155     .version_id = 1,
 156     .minimum_version_id = 1,
 157     .minimum_version_id_old = 1,
 158     .post_load = pcie_cap_slot_post_load,
 159     .fields = (VMStateField[]) {
 160         VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
 161         VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
 162                        vmstate_pcie_aer_log, PCIEAERLog),
 163         VMSTATE_END_OF_LIST()
 164     }
 165 };
 166
 167 static Property xio3130_downstream_properties[] = {
 168     DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
 169     DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 170     DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 171     DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
 172     port.br.dev.exp.aer_log.log_max,
 173     PCIE_AER_LOG_MAX_DEFAULT),
 174     DEFINE_PROP_END_OF_LIST(),
 175 };
 176
 177 static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
 178 {
 179     DeviceClass *dc = DEVICE_CLASS(klass);
 180     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 181
 182     k->is_express = 1;
 183     k->is_bridge = 1;
 184     k->config_write = xio3130_downstream_write_config;
 185     k->init = xio3130_downstream_initfn;
 186     k->exit = xio3130_downstream_exitfn;
 187     k->vendor_id = PCI_VENDOR_ID_TI;
 188     k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
 189     k->revision = XIO3130_REVISION;
 190     dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
 191     dc->reset = xio3130_downstream_reset;
 192     dc->vmsd = &vmstate_xio3130_downstream;
 193     dc->props = xio3130_downstream_properties;
 194 }
 195
 196 static const TypeInfo xio3130_downstream_info = {
 197     .name          = "xio3130-downstream",
 198     .parent        = TYPE_PCI_DEVICE,
 199     .instance_size = sizeof(PCIESlot),
 200     .class_init    = xio3130_downstream_class_init,
 201 };
 202
 203 static void xio3130_downstream_register_types(void)
 204 {
 205     type_register_static(&xio3130_downstream_info);
 206 }
 207
 208 type_init(xio3130_downstream_register_types)
 209
 210 /*
 211  * Local variables:
 212  *  c-indent-level: 4
 213  *  c-basic-offset: 4
 214  *  tab-width: 8
 215  *  indent-tab-mode: nil
 216  * End:
 217  */