hw/ppc/pnv.c

   1 /*
   2  * QEMU PowerPC PowerNV machine model
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "sysemu/sysemu.h"
  23 #include "sysemu/numa.h"
  24 #include "hw/hw.h"
  25 #include "target-ppc/cpu.h"
  26 #include "qemu/log.h"
  27 #include "hw/ppc/fdt.h"
  28 #include "hw/ppc/ppc.h"
  29 #include "hw/ppc/pnv.h"
  30 #include "hw/ppc/pnv_core.h"
  31 #include "hw/loader.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/cutils.h"
  34 #include "qapi/visitor.h"
  35
  36 #include "hw/ppc/pnv_xscom.h"
  37
  38 #include <libfdt.h>
  39
  40 #define FDT_MAX_SIZE            0x00100000
  41
  42 #define FW_FILE_NAME            "skiboot.lid"
  43 #define FW_LOAD_ADDR            0x0
  44 #define FW_MAX_SIZE             0x00400000
  45
  46 #define KERNEL_LOAD_ADDR        0x20000000
  47 #define INITRD_LOAD_ADDR        0x40000000
  48
  49 /*
  50  * On Power Systems E880 (POWER8), the max cpus (threads) should be :
  51  *     4 * 4 sockets * 12 cores * 8 threads = 1536
  52  * Let's make it 2^11
  53  */
  54 #define MAX_CPUS                2048
  55
  56 /*
  57  * Memory nodes are created by hostboot, one for each range of memory
  58  * that has a different "affinity". In practice, it means one range
  59  * per chip.
  60  */
  61 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
  62                                          hwaddr size)
  63 {
  64     char *mem_name;
  65     uint64_t mem_reg_property[2];
  66     int off;
  67
  68     mem_reg_property[0] = cpu_to_be64(start);
  69     mem_reg_property[1] = cpu_to_be64(size);
  70
  71     mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
  72     off = fdt_add_subnode(fdt, 0, mem_name);
  73     g_free(mem_name);
  74
  75     _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
  76     _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
  77                        sizeof(mem_reg_property))));
  78     _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
  79 }
  80
  81 static int get_cpus_node(void *fdt)
  82 {
  83     int cpus_offset = fdt_path_offset(fdt, "/cpus");
  84
  85     if (cpus_offset < 0) {
  86         cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
  87                                       "cpus");
  88         if (cpus_offset) {
  89             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
  90             _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
  91         }
  92     }
  93     _FDT(cpus_offset);
  94     return cpus_offset;
  95 }
  96
  97 /*
  98  * The PowerNV cores (and threads) need to use real HW ids and not an
  99  * incremental index like it has been done on other platforms. This HW
 100  * id is stored in the CPU PIR, it is used to create cpu nodes in the
 101  * device tree, used in XSCOM to address cores and in interrupt
 102  * servers.
 103  */
 104 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
 105 {
 106     CPUState *cs = CPU(DEVICE(pc->threads));
 107     DeviceClass *dc = DEVICE_GET_CLASS(cs);
 108     PowerPCCPU *cpu = POWERPC_CPU(cs);
 109     int smt_threads = ppc_get_compat_smt_threads(cpu);
 110     CPUPPCState *env = &cpu->env;
 111     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
 112     uint32_t servers_prop[smt_threads];
 113     int i;
 114     uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
 115                        0xffffffff, 0xffffffff};
 116     uint32_t tbfreq = PNV_TIMEBASE_FREQ;
 117     uint32_t cpufreq = 1000000000;
 118     uint32_t page_sizes_prop[64];
 119     size_t page_sizes_prop_size;
 120     const uint8_t pa_features[] = { 24, 0,
 121                                     0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
 122                                     0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
 123                                     0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
 124                                     0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
 125     int offset;
 126     char *nodename;
 127     int cpus_offset = get_cpus_node(fdt);
 128
 129     nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
 130     offset = fdt_add_subnode(fdt, cpus_offset, nodename);
 131     _FDT(offset);
 132     g_free(nodename);
 133
 134     _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
 135
 136     _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
 137     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
 138     _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
 139
 140     _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
 141     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
 142                             env->dcache_line_size)));
 143     _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
 144                             env->dcache_line_size)));
 145     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
 146                             env->icache_line_size)));
 147     _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
 148                             env->icache_line_size)));
 149
 150     if (pcc->l1_dcache_size) {
 151         _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
 152                                pcc->l1_dcache_size)));
 153     } else {
 154         error_report("Warning: Unknown L1 dcache size for cpu");
 155     }
 156     if (pcc->l1_icache_size) {
 157         _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
 158                                pcc->l1_icache_size)));
 159     } else {
 160         error_report("Warning: Unknown L1 icache size for cpu");
 161     }
 162
 163     _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
 164     _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
 165     _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
 166     _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
 167     _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
 168
 169     if (env->spr_cb[SPR_PURR].oea_read) {
 170         _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
 171     }
 172
 173     if (env->mmu_model & POWERPC_MMU_1TSEG) {
 174         _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
 175                            segs, sizeof(segs))));
 176     }
 177
 178     /* Advertise VMX/VSX (vector extensions) if available
 179      *   0 / no property == no vector extensions
 180      *   1               == VMX / Altivec available
 181      *   2               == VSX available */
 182     if (env->insns_flags & PPC_ALTIVEC) {
 183         uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
 184
 185         _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
 186     }
 187
 188     /* Advertise DFP (Decimal Floating Point) if available
 189      *   0 / no property == no DFP
 190      *   1               == DFP available */
 191     if (env->insns_flags2 & PPC2_DFP) {
 192         _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
 193     }
 194
 195     page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
 196                                                   sizeof(page_sizes_prop));
 197     if (page_sizes_prop_size) {
 198         _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
 199                            page_sizes_prop, page_sizes_prop_size)));
 200     }
 201
 202     _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
 203                        pa_features, sizeof(pa_features))));
 204
 205     if (cpu->cpu_version) {
 206         _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version)));
 207     }
 208
 209     /* Build interrupt servers properties */
 210     for (i = 0; i < smt_threads; i++) {
 211         servers_prop[i] = cpu_to_be32(pc->pir + i);
 212     }
 213     _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
 214                        servers_prop, sizeof(servers_prop))));
 215 }
 216
 217 static void powernv_populate_chip(PnvChip *chip, void *fdt)
 218 {
 219     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 220     char *typename = pnv_core_typename(pcc->cpu_model);
 221     size_t typesize = object_type_get_instance_size(typename);
 222     int i;
 223
 224     pnv_xscom_populate(chip, fdt, 0);
 225
 226     for (i = 0; i < chip->nr_cores; i++) {
 227         PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
 228
 229         powernv_create_core_node(chip, pnv_core, fdt);
 230     }
 231
 232     if (chip->ram_size) {
 233         powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
 234                                      chip->ram_size);
 235     }
 236     g_free(typename);
 237 }
 238
 239 static void *powernv_create_fdt(MachineState *machine)
 240 {
 241     const char plat_compat[] = "qemu,powernv\0ibm,powernv";
 242     PnvMachineState *pnv = POWERNV_MACHINE(machine);
 243     void *fdt;
 244     char *buf;
 245     int off;
 246     int i;
 247
 248     fdt = g_malloc0(FDT_MAX_SIZE);
 249     _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
 250
 251     /* Root node */
 252     _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
 253     _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
 254     _FDT((fdt_setprop_string(fdt, 0, "model",
 255                              "IBM PowerNV (emulated by qemu)")));
 256     _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
 257                       sizeof(plat_compat))));
 258
 259     buf =  qemu_uuid_unparse_strdup(&qemu_uuid);
 260     _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
 261     if (qemu_uuid_set) {
 262         _FDT((fdt_property_string(fdt, "system-id", buf)));
 263     }
 264     g_free(buf);
 265
 266     off = fdt_add_subnode(fdt, 0, "chosen");
 267     if (machine->kernel_cmdline) {
 268         _FDT((fdt_setprop_string(fdt, off, "bootargs",
 269                                  machine->kernel_cmdline)));
 270     }
 271
 272     if (pnv->initrd_size) {
 273         uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
 274         uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
 275
 276         _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
 277                                &start_prop, sizeof(start_prop))));
 278         _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
 279                                &end_prop, sizeof(end_prop))));
 280     }
 281
 282     /* Populate device tree for each chip */
 283     for (i = 0; i < pnv->num_chips; i++) {
 284         powernv_populate_chip(pnv->chips[i], fdt);
 285     }
 286     return fdt;
 287 }
 288
 289 static void ppc_powernv_reset(void)
 290 {
 291     MachineState *machine = MACHINE(qdev_get_machine());
 292     void *fdt;
 293
 294     qemu_devices_reset();
 295
 296     fdt = powernv_create_fdt(machine);
 297
 298     /* Pack resulting tree */
 299     _FDT((fdt_pack(fdt)));
 300
 301     cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
 302 }
 303
 304 static void ppc_powernv_init(MachineState *machine)
 305 {
 306     PnvMachineState *pnv = POWERNV_MACHINE(machine);
 307     MemoryRegion *ram;
 308     char *fw_filename;
 309     long fw_size;
 310     int i;
 311     char *chip_typename;
 312
 313     /* allocate RAM */
 314     if (machine->ram_size < (1 * G_BYTE)) {
 315         error_report("Warning: skiboot may not work with < 1GB of RAM");
 316     }
 317
 318     ram = g_new(MemoryRegion, 1);
 319     memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
 320                                          machine->ram_size);
 321     memory_region_add_subregion(get_system_memory(), 0, ram);
 322
 323     /* load skiboot firmware  */
 324     if (bios_name == NULL) {
 325         bios_name = FW_FILE_NAME;
 326     }
 327
 328     fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 329
 330     fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
 331     if (fw_size < 0) {
 332         hw_error("qemu: could not load OPAL '%s'\n", fw_filename);
 333         exit(1);
 334     }
 335     g_free(fw_filename);
 336
 337     /* load kernel */
 338     if (machine->kernel_filename) {
 339         long kernel_size;
 340
 341         kernel_size = load_image_targphys(machine->kernel_filename,
 342                                           KERNEL_LOAD_ADDR, 0x2000000);
 343         if (kernel_size < 0) {
 344             hw_error("qemu: could not load kernel'%s'\n",
 345                      machine->kernel_filename);
 346             exit(1);
 347         }
 348     }
 349
 350     /* load initrd */
 351     if (machine->initrd_filename) {
 352         pnv->initrd_base = INITRD_LOAD_ADDR;
 353         pnv->initrd_size = load_image_targphys(machine->initrd_filename,
 354                                   pnv->initrd_base, 0x10000000); /* 128MB max */
 355         if (pnv->initrd_size < 0) {
 356             error_report("qemu: could not load initial ram disk '%s'",
 357                          machine->initrd_filename);
 358             exit(1);
 359         }
 360     }
 361
 362     /* We need some cpu model to instantiate the PnvChip class */
 363     if (machine->cpu_model == NULL) {
 364         machine->cpu_model = "POWER8";
 365     }
 366
 367     /* Create the processor chips */
 368     chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
 369     if (!object_class_by_name(chip_typename)) {
 370         error_report("qemu: invalid CPU model '%s' for %s machine",
 371                      machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
 372         exit(1);
 373     }
 374
 375     pnv->chips = g_new0(PnvChip *, pnv->num_chips);
 376     for (i = 0; i < pnv->num_chips; i++) {
 377         char chip_name[32];
 378         Object *chip = object_new(chip_typename);
 379
 380         pnv->chips[i] = PNV_CHIP(chip);
 381
 382         /* TODO: put all the memory in one node on chip 0 until we find a
 383          * way to specify different ranges for each chip
 384          */
 385         if (i == 0) {
 386             object_property_set_int(chip, machine->ram_size, "ram-size",
 387                                     &error_fatal);
 388         }
 389
 390         snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
 391         object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
 392         object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
 393                                 &error_fatal);
 394         object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
 395         object_property_set_bool(chip, true, "realized", &error_fatal);
 396     }
 397     g_free(chip_typename);
 398 }
 399
 400 /*
 401  *    0:21  Reserved - Read as zeros
 402  *   22:24  Chip ID
 403  *   25:28  Core number
 404  *   29:31  Thread ID
 405  */
 406 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
 407 {
 408     return (chip->chip_id << 7) | (core_id << 3);
 409 }
 410
 411 /*
 412  *    0:48  Reserved - Read as zeroes
 413  *   49:52  Node ID
 414  *   53:55  Chip ID
 415  *   56     Reserved - Read as zero
 416  *   57:61  Core number
 417  *   62:63  Thread ID
 418  *
 419  * We only care about the lower bits. uint32_t is fine for the moment.
 420  */
 421 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
 422 {
 423     return (chip->chip_id << 8) | (core_id << 2);
 424 }
 425
 426 /* Allowed core identifiers on a POWER8 Processor Chip :
 427  *
 428  * <EX0 reserved>
 429  *  EX1  - Venice only
 430  *  EX2  - Venice only
 431  *  EX3  - Venice only
 432  *  EX4
 433  *  EX5
 434  *  EX6
 435  * <EX7,8 reserved> <reserved>
 436  *  EX9  - Venice only
 437  *  EX10 - Venice only
 438  *  EX11 - Venice only
 439  *  EX12
 440  *  EX13
 441  *  EX14
 442  * <EX15 reserved>
 443  */
 444 #define POWER8E_CORE_MASK  (0x7070ull)
 445 #define POWER8_CORE_MASK   (0x7e7eull)
 446
 447 /*
 448  * POWER9 has 24 cores, ids starting at 0x20
 449  */
 450 #define POWER9_CORE_MASK   (0xffffff00000000ull)
 451
 452 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
 453 {
 454     DeviceClass *dc = DEVICE_CLASS(klass);
 455     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 456
 457     k->cpu_model = "POWER8E";
 458     k->chip_type = PNV_CHIP_POWER8E;
 459     k->chip_cfam_id = 0x221ef04980000000ull;  /* P8 Murano DD2.1 */
 460     k->cores_mask = POWER8E_CORE_MASK;
 461     k->core_pir = pnv_chip_core_pir_p8;
 462     k->xscom_base = 0x003fc0000000000ull;
 463     dc->desc = "PowerNV Chip POWER8E";
 464 }
 465
 466 static const TypeInfo pnv_chip_power8e_info = {
 467     .name          = TYPE_PNV_CHIP_POWER8E,
 468     .parent        = TYPE_PNV_CHIP,
 469     .instance_size = sizeof(PnvChip),
 470     .class_init    = pnv_chip_power8e_class_init,
 471 };
 472
 473 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
 474 {
 475     DeviceClass *dc = DEVICE_CLASS(klass);
 476     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 477
 478     k->cpu_model = "POWER8";
 479     k->chip_type = PNV_CHIP_POWER8;
 480     k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
 481     k->cores_mask = POWER8_CORE_MASK;
 482     k->core_pir = pnv_chip_core_pir_p8;
 483     k->xscom_base = 0x003fc0000000000ull;
 484     dc->desc = "PowerNV Chip POWER8";
 485 }
 486
 487 static const TypeInfo pnv_chip_power8_info = {
 488     .name          = TYPE_PNV_CHIP_POWER8,
 489     .parent        = TYPE_PNV_CHIP,
 490     .instance_size = sizeof(PnvChip),
 491     .class_init    = pnv_chip_power8_class_init,
 492 };
 493
 494 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
 495 {
 496     DeviceClass *dc = DEVICE_CLASS(klass);
 497     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 498
 499     k->cpu_model = "POWER8NVL";
 500     k->chip_type = PNV_CHIP_POWER8NVL;
 501     k->chip_cfam_id = 0x120d304980000000ull;  /* P8 Naples DD1.0 */
 502     k->cores_mask = POWER8_CORE_MASK;
 503     k->core_pir = pnv_chip_core_pir_p8;
 504     k->xscom_base = 0x003fc0000000000ull;
 505     dc->desc = "PowerNV Chip POWER8NVL";
 506 }
 507
 508 static const TypeInfo pnv_chip_power8nvl_info = {
 509     .name          = TYPE_PNV_CHIP_POWER8NVL,
 510     .parent        = TYPE_PNV_CHIP,
 511     .instance_size = sizeof(PnvChip),
 512     .class_init    = pnv_chip_power8nvl_class_init,
 513 };
 514
 515 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
 516 {
 517     DeviceClass *dc = DEVICE_CLASS(klass);
 518     PnvChipClass *k = PNV_CHIP_CLASS(klass);
 519
 520     k->cpu_model = "POWER9";
 521     k->chip_type = PNV_CHIP_POWER9;
 522     k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
 523     k->cores_mask = POWER9_CORE_MASK;
 524     k->core_pir = pnv_chip_core_pir_p9;
 525     k->xscom_base = 0x00603fc00000000ull;
 526     dc->desc = "PowerNV Chip POWER9";
 527 }
 528
 529 static const TypeInfo pnv_chip_power9_info = {
 530     .name          = TYPE_PNV_CHIP_POWER9,
 531     .parent        = TYPE_PNV_CHIP,
 532     .instance_size = sizeof(PnvChip),
 533     .class_init    = pnv_chip_power9_class_init,
 534 };
 535
 536 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
 537 {
 538     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 539     int cores_max;
 540
 541     /*
 542      * No custom mask for this chip, let's use the default one from *
 543      * the chip class
 544      */
 545     if (!chip->cores_mask) {
 546         chip->cores_mask = pcc->cores_mask;
 547     }
 548
 549     /* filter alien core ids ! some are reserved */
 550     if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
 551         error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
 552                    chip->cores_mask);
 553         return;
 554     }
 555     chip->cores_mask &= pcc->cores_mask;
 556
 557     /* now that we have a sane layout, let check the number of cores */
 558     cores_max = hweight_long(chip->cores_mask);
 559     if (chip->nr_cores > cores_max) {
 560         error_setg(errp, "warning: too many cores for chip ! Limit is %d",
 561                    cores_max);
 562         return;
 563     }
 564 }
 565
 566 static void pnv_chip_init(Object *obj)
 567 {
 568     PnvChip *chip = PNV_CHIP(obj);
 569     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 570
 571     chip->xscom_base = pcc->xscom_base;
 572 }
 573
 574 static void pnv_chip_realize(DeviceState *dev, Error **errp)
 575 {
 576     PnvChip *chip = PNV_CHIP(dev);
 577     Error *error = NULL;
 578     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 579     char *typename = pnv_core_typename(pcc->cpu_model);
 580     size_t typesize = object_type_get_instance_size(typename);
 581     int i, core_hwid;
 582
 583     if (!object_class_by_name(typename)) {
 584         error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
 585         return;
 586     }
 587
 588     /* XSCOM bridge */
 589     pnv_xscom_realize(chip, &error);
 590     if (error) {
 591         error_propagate(errp, error);
 592         return;
 593     }
 594     sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
 595
 596     /* Cores */
 597     pnv_chip_core_sanitize(chip, &error);
 598     if (error) {
 599         error_propagate(errp, error);
 600         return;
 601     }
 602
 603     chip->cores = g_malloc0(typesize * chip->nr_cores);
 604
 605     for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
 606              && (i < chip->nr_cores); core_hwid++) {
 607         char core_name[32];
 608         void *pnv_core = chip->cores + i * typesize;
 609
 610         if (!(chip->cores_mask & (1ull << core_hwid))) {
 611             continue;
 612         }
 613
 614         object_initialize(pnv_core, typesize, typename);
 615         snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
 616         object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
 617                                   &error_fatal);
 618         object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
 619                                 &error_fatal);
 620         object_property_set_int(OBJECT(pnv_core), core_hwid,
 621                                 CPU_CORE_PROP_CORE_ID, &error_fatal);
 622         object_property_set_int(OBJECT(pnv_core),
 623                                 pcc->core_pir(chip, core_hwid),
 624                                 "pir", &error_fatal);
 625         object_property_set_bool(OBJECT(pnv_core), true, "realized",
 626                                  &error_fatal);
 627         object_unref(OBJECT(pnv_core));
 628         i++;
 629     }
 630     g_free(typename);
 631 }
 632
 633 static Property pnv_chip_properties[] = {
 634     DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
 635     DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
 636     DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
 637     DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
 638     DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
 639     DEFINE_PROP_END_OF_LIST(),
 640 };
 641
 642 static void pnv_chip_class_init(ObjectClass *klass, void *data)
 643 {
 644     DeviceClass *dc = DEVICE_CLASS(klass);
 645
 646     dc->realize = pnv_chip_realize;
 647     dc->props = pnv_chip_properties;
 648     dc->desc = "PowerNV Chip";
 649 }
 650
 651 static const TypeInfo pnv_chip_info = {
 652     .name          = TYPE_PNV_CHIP,
 653     .parent        = TYPE_SYS_BUS_DEVICE,
 654     .class_init    = pnv_chip_class_init,
 655     .instance_init = pnv_chip_init,
 656     .class_size    = sizeof(PnvChipClass),
 657     .abstract      = true,
 658 };
 659
 660 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
 661                               void *opaque, Error **errp)
 662 {
 663     visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
 664 }
 665
 666 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
 667                               void *opaque, Error **errp)
 668 {
 669     PnvMachineState *pnv = POWERNV_MACHINE(obj);
 670     uint32_t num_chips;
 671     Error *local_err = NULL;
 672
 673     visit_type_uint32(v, name, &num_chips, &local_err);
 674     if (local_err) {
 675         error_propagate(errp, local_err);
 676         return;
 677     }
 678
 679     /*
 680      * TODO: should we decide on how many chips we can create based
 681      * on #cores and Venice vs. Murano vs. Naples chip type etc...,
 682      */
 683     if (!is_power_of_2(num_chips) || num_chips > 4) {
 684         error_setg(errp, "invalid number of chips: '%d'", num_chips);
 685         return;
 686     }
 687
 688     pnv->num_chips = num_chips;
 689 }
 690
 691 static void powernv_machine_initfn(Object *obj)
 692 {
 693     PnvMachineState *pnv = POWERNV_MACHINE(obj);
 694     pnv->num_chips = 1;
 695 }
 696
 697 static void powernv_machine_class_props_init(ObjectClass *oc)
 698 {
 699     object_class_property_add(oc, "num-chips", "uint32_t",
 700                               pnv_get_num_chips, pnv_set_num_chips,
 701                               NULL, NULL, NULL);
 702     object_class_property_set_description(oc, "num-chips",
 703                               "Specifies the number of processor chips",
 704                               NULL);
 705 }
 706
 707 static void powernv_machine_class_init(ObjectClass *oc, void *data)
 708 {
 709     MachineClass *mc = MACHINE_CLASS(oc);
 710
 711     mc->desc = "IBM PowerNV (Non-Virtualized)";
 712     mc->init = ppc_powernv_init;
 713     mc->reset = ppc_powernv_reset;
 714     mc->max_cpus = MAX_CPUS;
 715     mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
 716                                       * storage */
 717     mc->no_parallel = 1;
 718     mc->default_boot_order = NULL;
 719     mc->default_ram_size = 1 * G_BYTE;
 720
 721     powernv_machine_class_props_init(oc);
 722 }
 723
 724 static const TypeInfo powernv_machine_info = {
 725     .name          = TYPE_POWERNV_MACHINE,
 726     .parent        = TYPE_MACHINE,
 727     .instance_size = sizeof(PnvMachineState),
 728     .instance_init = powernv_machine_initfn,
 729     .class_init    = powernv_machine_class_init,
 730 };
 731
 732 static void powernv_machine_register_types(void)
 733 {
 734     type_register_static(&powernv_machine_info);
 735     type_register_static(&pnv_chip_info);
 736     type_register_static(&pnv_chip_power8e_info);
 737     type_register_static(&pnv_chip_power8_info);
 738     type_register_static(&pnv_chip_power8nvl_info);
 739     type_register_static(&pnv_chip_power9_info);
 740 }
 741
 742 type_init(powernv_machine_register_types)