1 #include "qemu/osdep.h"
3 #include "exec/exec-all.h"
4 #include "sysemu/kvm.h"
5 #include "helper_regs.h"
6 #include "mmu-hash64.h"
7 #include "migration/cpu.h"
8 #include "qapi/error.h"
9 #include "qemu/main-loop.h"
11 #include "power8-pmu.h"
13 static void post_load_update_msr(CPUPPCState
*env
)
15 target_ulong msr
= env
->msr
;
18 * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
19 * before restoring. Note that this recomputes hflags.
21 env
->msr
^= env
->msr_mask
& ~((1ULL << MSR_TGPR
) | MSR_HVB
);
22 ppc_store_msr(env
, msr
);
23 pmu_update_summaries(env
);
26 static int get_avr(QEMUFile
*f
, void *pv
, size_t size
,
27 const VMStateField
*field
)
31 v
->u64
[0] = qemu_get_be64(f
);
32 v
->u64
[1] = qemu_get_be64(f
);
37 static int put_avr(QEMUFile
*f
, void *pv
, size_t size
,
38 const VMStateField
*field
, JSONWriter
*vmdesc
)
42 qemu_put_be64(f
, v
->u64
[0]);
43 qemu_put_be64(f
, v
->u64
[1]);
47 static const VMStateInfo vmstate_info_avr
= {
53 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
54 VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t)
56 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \
57 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
59 static int get_fpr(QEMUFile
*f
, void *pv
, size_t size
,
60 const VMStateField
*field
)
64 v
->VsrD(0) = qemu_get_be64(f
);
69 static int put_fpr(QEMUFile
*f
, void *pv
, size_t size
,
70 const VMStateField
*field
, JSONWriter
*vmdesc
)
74 qemu_put_be64(f
, v
->VsrD(0));
78 static const VMStateInfo vmstate_info_fpr
= {
84 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
85 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t)
87 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \
88 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
90 static int get_vsr(QEMUFile
*f
, void *pv
, size_t size
,
91 const VMStateField
*field
)
95 v
->VsrD(1) = qemu_get_be64(f
);
100 static int put_vsr(QEMUFile
*f
, void *pv
, size_t size
,
101 const VMStateField
*field
, JSONWriter
*vmdesc
)
105 qemu_put_be64(f
, v
->VsrD(1));
109 static const VMStateInfo vmstate_info_vsr
= {
115 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \
116 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t)
118 #define VMSTATE_VSR_ARRAY(_f, _s, _n) \
119 VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
121 static bool cpu_pre_2_8_migration(void *opaque
, int version_id
)
123 PowerPCCPU
*cpu
= opaque
;
125 return cpu
->pre_2_8_migration
;
128 #if defined(TARGET_PPC64)
129 static bool cpu_pre_3_0_migration(void *opaque
, int version_id
)
131 PowerPCCPU
*cpu
= opaque
;
133 return cpu
->pre_3_0_migration
;
137 static int cpu_pre_save(void *opaque
)
139 PowerPCCPU
*cpu
= opaque
;
140 CPUPPCState
*env
= &cpu
->env
;
142 uint64_t insns_compat_mask
=
143 PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
144 | PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
145 | PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FRSQRTES
146 | PPC_FLOAT_STFIWX
| PPC_FLOAT_EXT
147 | PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
148 | PPC_MEM_SYNC
| PPC_MEM_EIEIO
| PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
149 | PPC_64B
| PPC_64BX
| PPC_ALTIVEC
150 | PPC_SEGMENT_64B
| PPC_SLBI
| PPC_POPCNTB
| PPC_POPCNTWD
;
151 uint64_t insns_compat_mask2
= PPC2_VSX
| PPC2_VSX207
| PPC2_DFP
| PPC2_DBRX
152 | PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
153 | PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
154 | PPC2_FP_TST_ISA206
| PPC2_BCTAR_ISA207
155 | PPC2_LSQ_ISA207
| PPC2_ALTIVEC_207
156 | PPC2_ISA205
| PPC2_ISA207S
| PPC2_FP_CVT_S64
| PPC2_TM
;
158 env
->spr
[SPR_LR
] = env
->lr
;
159 env
->spr
[SPR_CTR
] = env
->ctr
;
160 env
->spr
[SPR_XER
] = cpu_read_xer(env
);
161 #if defined(TARGET_PPC64)
162 env
->spr
[SPR_CFAR
] = env
->cfar
;
164 env
->spr
[SPR_BOOKE_SPEFSCR
] = env
->spe_fscr
;
166 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
167 env
->spr
[SPR_DBAT0U
+ 2 * i
] = env
->DBAT
[0][i
];
168 env
->spr
[SPR_DBAT0U
+ 2 * i
+ 1] = env
->DBAT
[1][i
];
169 env
->spr
[SPR_IBAT0U
+ 2 * i
] = env
->IBAT
[0][i
];
170 env
->spr
[SPR_IBAT0U
+ 2 * i
+ 1] = env
->IBAT
[1][i
];
172 for (i
= 0; (i
< 4) && ((i
+ 4) < env
->nb_BATs
); i
++) {
173 env
->spr
[SPR_DBAT4U
+ 2 * i
] = env
->DBAT
[0][i
+ 4];
174 env
->spr
[SPR_DBAT4U
+ 2 * i
+ 1] = env
->DBAT
[1][i
+ 4];
175 env
->spr
[SPR_IBAT4U
+ 2 * i
] = env
->IBAT
[0][i
+ 4];
176 env
->spr
[SPR_IBAT4U
+ 2 * i
+ 1] = env
->IBAT
[1][i
+ 4];
179 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
180 if (cpu
->pre_2_8_migration
) {
182 * Mask out bits that got added to msr_mask since the versions
183 * which stupidly included it in the migration stream.
185 target_ulong metamask
= 0
186 #if defined(TARGET_PPC64)
191 cpu
->mig_msr_mask
= env
->msr_mask
& ~metamask
;
192 cpu
->mig_insns_flags
= env
->insns_flags
& insns_compat_mask
;
194 * CPU models supported by old machines all have
195 * PPC_MEM_TLBIE, so we set it unconditionally to allow
196 * backward migration from a POWER9 host to a POWER8 host.
198 cpu
->mig_insns_flags
|= PPC_MEM_TLBIE
;
199 cpu
->mig_insns_flags2
= env
->insns_flags2
& insns_compat_mask2
;
200 cpu
->mig_nb_BATs
= env
->nb_BATs
;
202 if (cpu
->pre_3_0_migration
) {
203 if (cpu
->hash64_opts
) {
204 cpu
->mig_slb_nr
= cpu
->hash64_opts
->slb_size
;
208 /* Retain migration compatibility for pre 6.0 for 601 machines. */
209 env
->hflags_compat_nmsr
= (env
->flags
& POWERPC_FLAG_HID0_LE
210 ? env
->hflags
& MSR_LE
: 0);
216 * Determine if a given PVR is a "close enough" match to the CPU
217 * object. For TCG and KVM PR it would probably be sufficient to
218 * require an exact PVR match. However for KVM HV the user is
219 * restricted to a PVR exactly matching the host CPU. The correct way
220 * to handle this is to put the guest into an architected
221 * compatibility mode. However, to allow a more forgiving transition
222 * and migration from before this was widely done, we allow migration
223 * between sufficiently similar PVRs, as determined by the CPU class's
226 static bool pvr_match(PowerPCCPU
*cpu
, uint32_t pvr
)
228 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
230 if (pvr
== pcc
->pvr
) {
233 return pcc
->pvr_match(pcc
, pvr
);
236 static int cpu_post_load(void *opaque
, int version_id
)
238 PowerPCCPU
*cpu
= opaque
;
239 CPUPPCState
*env
= &cpu
->env
;
243 * If we're operating in compat mode, we should be ok as long as
244 * the destination supports the same compatibility mode.
246 * Otherwise, however, we require that the destination has exactly
247 * the same CPU model as the source.
250 #if defined(TARGET_PPC64)
251 if (cpu
->compat_pvr
) {
252 uint32_t compat_pvr
= cpu
->compat_pvr
;
253 Error
*local_err
= NULL
;
257 ret
= ppc_set_compat(cpu
, compat_pvr
, &local_err
);
259 error_report_err(local_err
);
265 if (!pvr_match(cpu
, env
->spr
[SPR_PVR
])) {
271 * If we're running with KVM HV, there is a chance that the guest
272 * is running with KVM HV and its kernel does not have the
273 * capability of dealing with a different PVR other than this
274 * exact host PVR in KVM_SET_SREGS. If that happens, the
275 * guest freezes after migration.
277 * The function kvmppc_pvr_workaround_required does this verification
278 * by first checking if the kernel has the cap, returning true immediately
279 * if that is the case. Otherwise, it checks if we're running in KVM PR.
280 * If the guest kernel does not have the cap and we're not running KVM-PR
281 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
282 * receive the PVR it expects as a workaround.
285 if (kvmppc_pvr_workaround_required(cpu
)) {
286 env
->spr
[SPR_PVR
] = env
->spr_cb
[SPR_PVR
].default_value
;
289 env
->lr
= env
->spr
[SPR_LR
];
290 env
->ctr
= env
->spr
[SPR_CTR
];
291 cpu_write_xer(env
, env
->spr
[SPR_XER
]);
292 #if defined(TARGET_PPC64)
293 env
->cfar
= env
->spr
[SPR_CFAR
];
295 env
->spe_fscr
= env
->spr
[SPR_BOOKE_SPEFSCR
];
297 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
298 env
->DBAT
[0][i
] = env
->spr
[SPR_DBAT0U
+ 2 * i
];
299 env
->DBAT
[1][i
] = env
->spr
[SPR_DBAT0U
+ 2 * i
+ 1];
300 env
->IBAT
[0][i
] = env
->spr
[SPR_IBAT0U
+ 2 * i
];
301 env
->IBAT
[1][i
] = env
->spr
[SPR_IBAT0U
+ 2 * i
+ 1];
303 for (i
= 0; (i
< 4) && ((i
+ 4) < env
->nb_BATs
); i
++) {
304 env
->DBAT
[0][i
+ 4] = env
->spr
[SPR_DBAT4U
+ 2 * i
];
305 env
->DBAT
[1][i
+ 4] = env
->spr
[SPR_DBAT4U
+ 2 * i
+ 1];
306 env
->IBAT
[0][i
+ 4] = env
->spr
[SPR_IBAT4U
+ 2 * i
];
307 env
->IBAT
[1][i
+ 4] = env
->spr
[SPR_IBAT4U
+ 2 * i
+ 1];
311 ppc_store_sdr1(env
, env
->spr
[SPR_SDR1
]);
314 post_load_update_msr(env
);
319 static bool fpu_needed(void *opaque
)
321 PowerPCCPU
*cpu
= opaque
;
323 return cpu
->env
.insns_flags
& PPC_FLOAT
;
326 static const VMStateDescription vmstate_fpu
= {
329 .minimum_version_id
= 1,
330 .needed
= fpu_needed
,
331 .fields
= (VMStateField
[]) {
332 VMSTATE_FPR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
333 VMSTATE_UINTTL(env
.fpscr
, PowerPCCPU
),
334 VMSTATE_END_OF_LIST()
338 static bool altivec_needed(void *opaque
)
340 PowerPCCPU
*cpu
= opaque
;
342 return cpu
->env
.insns_flags
& PPC_ALTIVEC
;
345 static int get_vscr(QEMUFile
*f
, void *opaque
, size_t size
,
346 const VMStateField
*field
)
348 PowerPCCPU
*cpu
= opaque
;
349 ppc_store_vscr(&cpu
->env
, qemu_get_be32(f
));
353 static int put_vscr(QEMUFile
*f
, void *opaque
, size_t size
,
354 const VMStateField
*field
, JSONWriter
*vmdesc
)
356 PowerPCCPU
*cpu
= opaque
;
357 qemu_put_be32(f
, ppc_get_vscr(&cpu
->env
));
361 static const VMStateInfo vmstate_vscr
= {
362 .name
= "cpu/altivec/vscr",
367 static const VMStateDescription vmstate_altivec
= {
368 .name
= "cpu/altivec",
370 .minimum_version_id
= 1,
371 .needed
= altivec_needed
,
372 .fields
= (VMStateField
[]) {
373 VMSTATE_AVR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
375 * Save the architecture value of the vscr, not the internally
376 * expanded version. Since this architecture value does not
377 * exist in memory to be stored, this requires a but of hoop
378 * jumping. We want OFFSET=0 so that we effectively pass CPU
379 * to the helper functions.
384 .size
= sizeof(uint32_t),
385 .info
= &vmstate_vscr
,
389 VMSTATE_END_OF_LIST()
393 static bool vsx_needed(void *opaque
)
395 PowerPCCPU
*cpu
= opaque
;
397 return cpu
->env
.insns_flags2
& PPC2_VSX
;
400 static const VMStateDescription vmstate_vsx
= {
403 .minimum_version_id
= 1,
404 .needed
= vsx_needed
,
405 .fields
= (VMStateField
[]) {
406 VMSTATE_VSR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
407 VMSTATE_END_OF_LIST()
412 /* Transactional memory state */
413 static bool tm_needed(void *opaque
)
415 PowerPCCPU
*cpu
= opaque
;
416 CPUPPCState
*env
= &cpu
->env
;
420 static const VMStateDescription vmstate_tm
= {
423 .minimum_version_id
= 1,
424 .minimum_version_id_old
= 1,
426 .fields
= (VMStateField
[]) {
427 VMSTATE_UINTTL_ARRAY(env
.tm_gpr
, PowerPCCPU
, 32),
428 VMSTATE_AVR_ARRAY(env
.tm_vsr
, PowerPCCPU
, 64),
429 VMSTATE_UINT64(env
.tm_cr
, PowerPCCPU
),
430 VMSTATE_UINT64(env
.tm_lr
, PowerPCCPU
),
431 VMSTATE_UINT64(env
.tm_ctr
, PowerPCCPU
),
432 VMSTATE_UINT64(env
.tm_fpscr
, PowerPCCPU
),
433 VMSTATE_UINT64(env
.tm_amr
, PowerPCCPU
),
434 VMSTATE_UINT64(env
.tm_ppr
, PowerPCCPU
),
435 VMSTATE_UINT64(env
.tm_vrsave
, PowerPCCPU
),
436 VMSTATE_UINT32(env
.tm_vscr
, PowerPCCPU
),
437 VMSTATE_UINT64(env
.tm_dscr
, PowerPCCPU
),
438 VMSTATE_UINT64(env
.tm_tar
, PowerPCCPU
),
439 VMSTATE_END_OF_LIST()
444 static bool sr_needed(void *opaque
)
447 PowerPCCPU
*cpu
= opaque
;
449 return !mmu_is_64bit(cpu
->env
.mmu_model
);
455 static const VMStateDescription vmstate_sr
= {
458 .minimum_version_id
= 1,
460 .fields
= (VMStateField
[]) {
461 VMSTATE_UINTTL_ARRAY(env
.sr
, PowerPCCPU
, 32),
462 VMSTATE_END_OF_LIST()
467 static int get_slbe(QEMUFile
*f
, void *pv
, size_t size
,
468 const VMStateField
*field
)
472 v
->esid
= qemu_get_be64(f
);
473 v
->vsid
= qemu_get_be64(f
);
478 static int put_slbe(QEMUFile
*f
, void *pv
, size_t size
,
479 const VMStateField
*field
, JSONWriter
*vmdesc
)
483 qemu_put_be64(f
, v
->esid
);
484 qemu_put_be64(f
, v
->vsid
);
488 static const VMStateInfo vmstate_info_slbe
= {
494 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
495 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
497 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \
498 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
500 static bool slb_needed(void *opaque
)
502 PowerPCCPU
*cpu
= opaque
;
504 /* We don't support any of the old segment table based 64-bit CPUs */
505 return mmu_is_64bit(cpu
->env
.mmu_model
);
508 static int slb_post_load(void *opaque
, int version_id
)
510 PowerPCCPU
*cpu
= opaque
;
511 CPUPPCState
*env
= &cpu
->env
;
515 * We've pulled in the raw esid and vsid values from the migration
516 * stream, but we need to recompute the page size pointers
518 for (i
= 0; i
< cpu
->hash64_opts
->slb_size
; i
++) {
519 if (ppc_store_slb(cpu
, i
, env
->slb
[i
].esid
, env
->slb
[i
].vsid
) < 0) {
520 /* Migration source had bad values in its SLB */
528 static const VMStateDescription vmstate_slb
= {
531 .minimum_version_id
= 1,
532 .needed
= slb_needed
,
533 .post_load
= slb_post_load
,
534 .fields
= (VMStateField
[]) {
535 VMSTATE_INT32_TEST(mig_slb_nr
, PowerPCCPU
, cpu_pre_3_0_migration
),
536 VMSTATE_SLB_ARRAY(env
.slb
, PowerPCCPU
, MAX_SLB_ENTRIES
),
537 VMSTATE_END_OF_LIST()
540 #endif /* TARGET_PPC64 */
542 static const VMStateDescription vmstate_tlb6xx_entry
= {
543 .name
= "cpu/tlb6xx_entry",
545 .minimum_version_id
= 1,
546 .fields
= (VMStateField
[]) {
547 VMSTATE_UINTTL(pte0
, ppc6xx_tlb_t
),
548 VMSTATE_UINTTL(pte1
, ppc6xx_tlb_t
),
549 VMSTATE_UINTTL(EPN
, ppc6xx_tlb_t
),
550 VMSTATE_END_OF_LIST()
554 static bool tlb6xx_needed(void *opaque
)
556 PowerPCCPU
*cpu
= opaque
;
557 CPUPPCState
*env
= &cpu
->env
;
559 return env
->nb_tlb
&& (env
->tlb_type
== TLB_6XX
);
562 static const VMStateDescription vmstate_tlb6xx
= {
563 .name
= "cpu/tlb6xx",
565 .minimum_version_id
= 1,
566 .needed
= tlb6xx_needed
,
567 .fields
= (VMStateField
[]) {
568 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
569 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlb6
, PowerPCCPU
,
571 vmstate_tlb6xx_entry
,
573 VMSTATE_UINTTL_ARRAY(env
.tgpr
, PowerPCCPU
, 4),
574 VMSTATE_END_OF_LIST()
578 static const VMStateDescription vmstate_tlbemb_entry
= {
579 .name
= "cpu/tlbemb_entry",
581 .minimum_version_id
= 1,
582 .fields
= (VMStateField
[]) {
583 VMSTATE_UINT64(RPN
, ppcemb_tlb_t
),
584 VMSTATE_UINTTL(EPN
, ppcemb_tlb_t
),
585 VMSTATE_UINTTL(PID
, ppcemb_tlb_t
),
586 VMSTATE_UINTTL(size
, ppcemb_tlb_t
),
587 VMSTATE_UINT32(prot
, ppcemb_tlb_t
),
588 VMSTATE_UINT32(attr
, ppcemb_tlb_t
),
589 VMSTATE_END_OF_LIST()
593 static bool tlbemb_needed(void *opaque
)
595 PowerPCCPU
*cpu
= opaque
;
596 CPUPPCState
*env
= &cpu
->env
;
598 return env
->nb_tlb
&& (env
->tlb_type
== TLB_EMB
);
601 static bool pbr403_needed(void *opaque
)
603 PowerPCCPU
*cpu
= opaque
;
604 uint32_t pvr
= cpu
->env
.spr
[SPR_PVR
];
606 return (pvr
& 0xffff0000) == 0x00200000;
609 static const VMStateDescription vmstate_pbr403
= {
610 .name
= "cpu/pbr403",
612 .minimum_version_id
= 1,
613 .needed
= pbr403_needed
,
614 .fields
= (VMStateField
[]) {
615 VMSTATE_UINTTL_ARRAY(env
.pb
, PowerPCCPU
, 4),
616 VMSTATE_END_OF_LIST()
620 static const VMStateDescription vmstate_tlbemb
= {
621 .name
= "cpu/tlb6xx",
623 .minimum_version_id
= 1,
624 .needed
= tlbemb_needed
,
625 .fields
= (VMStateField
[]) {
626 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
627 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbe
, PowerPCCPU
,
629 vmstate_tlbemb_entry
,
631 /* 403 protection registers */
632 VMSTATE_END_OF_LIST()
634 .subsections
= (const VMStateDescription
*[]) {
640 static const VMStateDescription vmstate_tlbmas_entry
= {
641 .name
= "cpu/tlbmas_entry",
643 .minimum_version_id
= 1,
644 .fields
= (VMStateField
[]) {
645 VMSTATE_UINT32(mas8
, ppcmas_tlb_t
),
646 VMSTATE_UINT32(mas1
, ppcmas_tlb_t
),
647 VMSTATE_UINT64(mas2
, ppcmas_tlb_t
),
648 VMSTATE_UINT64(mas7_3
, ppcmas_tlb_t
),
649 VMSTATE_END_OF_LIST()
653 static bool tlbmas_needed(void *opaque
)
655 PowerPCCPU
*cpu
= opaque
;
656 CPUPPCState
*env
= &cpu
->env
;
658 return env
->nb_tlb
&& (env
->tlb_type
== TLB_MAS
);
661 static const VMStateDescription vmstate_tlbmas
= {
662 .name
= "cpu/tlbmas",
664 .minimum_version_id
= 1,
665 .needed
= tlbmas_needed
,
666 .fields
= (VMStateField
[]) {
667 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
668 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbm
, PowerPCCPU
,
670 vmstate_tlbmas_entry
,
672 VMSTATE_END_OF_LIST()
676 static bool compat_needed(void *opaque
)
678 PowerPCCPU
*cpu
= opaque
;
680 assert(!(cpu
->compat_pvr
&& !cpu
->vhyp
));
681 return !cpu
->pre_2_10_migration
&& cpu
->compat_pvr
!= 0;
684 static const VMStateDescription vmstate_compat
= {
685 .name
= "cpu/compat",
687 .minimum_version_id
= 1,
688 .needed
= compat_needed
,
689 .fields
= (VMStateField
[]) {
690 VMSTATE_UINT32(compat_pvr
, PowerPCCPU
),
691 VMSTATE_END_OF_LIST()
695 const VMStateDescription vmstate_ppc_cpu
= {
698 .minimum_version_id
= 5,
699 .minimum_version_id_old
= 4,
700 .pre_save
= cpu_pre_save
,
701 .post_load
= cpu_post_load
,
702 .fields
= (VMStateField
[]) {
703 VMSTATE_UNUSED(sizeof(target_ulong
)), /* was _EQUAL(env.spr[SPR_PVR]) */
705 /* User mode architected state */
706 VMSTATE_UINTTL_ARRAY(env
.gpr
, PowerPCCPU
, 32),
707 #if !defined(TARGET_PPC64)
708 VMSTATE_UINTTL_ARRAY(env
.gprh
, PowerPCCPU
, 32),
710 VMSTATE_UINT32_ARRAY(env
.crf
, PowerPCCPU
, 8),
711 VMSTATE_UINTTL(env
.nip
, PowerPCCPU
),
714 VMSTATE_UINTTL_ARRAY(env
.spr
, PowerPCCPU
, 1024),
715 VMSTATE_UINT64(env
.spe_acc
, PowerPCCPU
),
718 VMSTATE_UINTTL(env
.reserve_addr
, PowerPCCPU
),
720 /* Supervisor mode architected state */
721 VMSTATE_UINTTL(env
.msr
, PowerPCCPU
),
723 /* Backward compatible internal state */
724 VMSTATE_UINTTL(env
.hflags_compat_nmsr
, PowerPCCPU
),
726 /* Sanity checking */
727 VMSTATE_UINTTL_TEST(mig_msr_mask
, PowerPCCPU
, cpu_pre_2_8_migration
),
728 VMSTATE_UINT64_TEST(mig_insns_flags
, PowerPCCPU
, cpu_pre_2_8_migration
),
729 VMSTATE_UINT64_TEST(mig_insns_flags2
, PowerPCCPU
,
730 cpu_pre_2_8_migration
),
731 VMSTATE_UINT32_TEST(mig_nb_BATs
, PowerPCCPU
, cpu_pre_2_8_migration
),
732 VMSTATE_END_OF_LIST()
734 .subsections
= (const VMStateDescription
*[]) {
742 #endif /* TARGET_PPC64 */