?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'pull-ppc-20220706' of https://gitlab.com/danielhb/qemu into staging
[qemu/rayw.git] / hw / block / m25p80.c
blob3045dda53b81b415131e0eef4a1ff2d84f7661c5
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
29 #include "hw/ssi/ssi.h"
30 #include "migration/vmstate.h"
31 #include "qemu/bitops.h"
32 #include "qemu/log.h"
33 #include "qemu/module.h"
34 #include "qemu/error-report.h"
35 #include "qapi/error.h"
36 #include "trace.h"
37 #include "qom/object.h"
38
39 /* Fields for FlashPartInfo->flags */
40
41 /* erase capabilities */
42 #define ER_4K 1
43 #define ER_32K 2
44 /* set to allow the page program command to write 0s back to 1. Useful for
45 * modelling EEPROM with SPI flash command set
46 */
47 #define EEPROM 0x100
48
49 /* 16 MiB max in 3 byte address mode */
50 #define MAX_3BYTES_SIZE 0x1000000
51
52 #define SPI_NOR_MAX_ID_LEN 6
53
54 typedef struct FlashPartInfo {
55 const char *part_name;
56 /*
57 * This array stores the ID bytes.
58 * The first three bytes are the JEDIC ID.
59 * JEDEC ID zero means "no ID" (mostly older chips).
60 */
61 uint8_t id[SPI_NOR_MAX_ID_LEN];
62 uint8_t id_len;
63 /* there is confusion between manufacturers as to what a sector is. In this
64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
65 * command (opcode 0xd8).
66 */
67 uint32_t sector_size;
68 uint32_t n_sectors;
69 uint32_t page_size;
70 uint16_t flags;
71 /*
72 * Big sized spi nor are often stacked devices, thus sometime
73 * replace chip erase with die erase.
74 * This field inform how many die is in the chip.
75 */
76 uint8_t die_cnt;
77 } FlashPartInfo;
78
79 /* adapted from linux */
80 /* Used when the "_ext_id" is two bytes at most */
81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
82 .part_name = _part_name,\
83 .id = {\
84 ((_jedec_id) >> 16) & 0xff,\
85 ((_jedec_id) >> 8) & 0xff,\
86 (_jedec_id) & 0xff,\
87 ((_ext_id) >> 8) & 0xff,\
88 (_ext_id) & 0xff,\
89 },\
90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
91 .sector_size = (_sector_size),\
92 .n_sectors = (_n_sectors),\
93 .page_size = 256,\
94 .flags = (_flags),\
95 .die_cnt = 0
96
97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
98 .part_name = _part_name,\
99 .id = {\
100 ((_jedec_id) >> 16) & 0xff,\
101 ((_jedec_id) >> 8) & 0xff,\
102 (_jedec_id) & 0xff,\
103 ((_ext_id) >> 16) & 0xff,\
104 ((_ext_id) >> 8) & 0xff,\
105 (_ext_id) & 0xff,\
106 },\
107 .id_len = 6,\
108 .sector_size = (_sector_size),\
109 .n_sectors = (_n_sectors),\
110 .page_size = 256,\
111 .flags = (_flags),\
112 .die_cnt = 0
113
114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
115 _flags, _die_cnt)\
116 .part_name = _part_name,\
117 .id = {\
118 ((_jedec_id) >> 16) & 0xff,\
119 ((_jedec_id) >> 8) & 0xff,\
120 (_jedec_id) & 0xff,\
121 ((_ext_id) >> 8) & 0xff,\
122 (_ext_id) & 0xff,\
123 },\
124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
125 .sector_size = (_sector_size),\
126 .n_sectors = (_n_sectors),\
127 .page_size = 256,\
128 .flags = (_flags),\
129 .die_cnt = _die_cnt
130
131 #define JEDEC_NUMONYX 0x20
132 #define JEDEC_WINBOND 0xEF
133 #define JEDEC_SPANSION 0x01
134
135 /* Numonyx (Micron) Configuration register macros */
136 #define VCFG_DUMMY 0x1
137 #define VCFG_WRAP_SEQUENTIAL 0x2
138 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
139 #define NVCFG_XIP_MODE_MASK (7 << 9)
140 #define VCFG_XIP_MODE_DISABLED (1 << 3)
141 #define CFG_DUMMY_CLK_LEN 4
142 #define NVCFG_DUMMY_CLK_POS 12
143 #define VCFG_DUMMY_CLK_POS 4
144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
145 #define EVCFG_VPP_ACCELERATOR (1 << 3)
146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
147 #define NVCFG_DUAL_IO_MASK (1 << 2)
148 #define EVCFG_DUAL_IO_DISABLED (1 << 6)
149 #define NVCFG_QUAD_IO_MASK (1 << 3)
150 #define EVCFG_QUAD_IO_DISABLED (1 << 7)
151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
153
154 /* Numonyx (Micron) Flag Status Register macros */
155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
156 #define FSR_FLASH_READY (1 << 7)
157
158 /* Spansion configuration registers macros. */
159 #define SPANSION_QUAD_CFG_POS 0
160 #define SPANSION_QUAD_CFG_LEN 1
161 #define SPANSION_DUMMY_CLK_POS 0
162 #define SPANSION_DUMMY_CLK_LEN 4
163 #define SPANSION_ADDR_LEN_POS 7
164 #define SPANSION_ADDR_LEN_LEN 1
165
166 /*
167 * Spansion read mode command length in bytes,
168 * the mode is currently not supported.
169 */
170
171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
173
174 static const FlashPartInfo known_devices[] = {
175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
178
179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
182
183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
187
188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
189
190 /* Atmel EEPROMS - it is assumed, that don't care bit in command
191 * is set to 0. Block protection is not supported.
192 */
193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
195
196 /* EON -- en25xxx */
197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
202
203 /* GigaDevice */
204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
206
207 /* Intel/Numonyx -- xxxs33b */
208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
212
213 /* ISSI */
214 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
215 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
216 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
217 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
218 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
219 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
220 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) },
221 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
222 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
223 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
224 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
225
226 /* Macronix */
227 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
228 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
229 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
230 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
231 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
232 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
233 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
234 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
235 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },
236 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
237 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
238 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
239 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
240 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
241
242 /* Micron */
243 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
244 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
245 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
246 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
247 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
248 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
249 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
250 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
251 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
252 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
253 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
254 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
255 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
256 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
257 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
258 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
259 ER_4K | ER_32K, 2) },
260 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
261 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
262 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
263 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
264 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) },
265 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) },
266
267 /* Spansion -- single (large) sector size only, at least
268 * for the chips listed here (without boot sectors).
269 */
270 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
271 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
272 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
273 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
274 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
275 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
276 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
277 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
278 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
279 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
280 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
281 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
282 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
283 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
284 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
285 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
286 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
287
288 /* Spansion -- boot sectors support */
289 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
290 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
291
292 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
293 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
294 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
295 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
296 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
297 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
298 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
299 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
300 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
301 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
302
303 /* ST Microelectronics -- newer production may have feature updates */
304 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
305 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
306 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
307 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
308 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
309 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
310 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
311 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
312 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
313 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
314
315 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
316 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
317 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
318
319 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
320 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
321 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
322
323 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
324 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
325 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
326 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
327
328 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
329 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
330 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
331 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
332 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
333 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
334 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
335 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
336 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
337 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
338 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
339 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
340 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
341 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
342 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) },
343 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K) },
344 };
345
346 typedef enum {
347 NOP = 0,
348 WRSR = 0x1,
349 WRDI = 0x4,
350 RDSR = 0x5,
351 WREN = 0x6,
352 BRRD = 0x16,
353 BRWR = 0x17,
354 JEDEC_READ = 0x9f,
355 BULK_ERASE_60 = 0x60,
356 BULK_ERASE = 0xc7,
357 READ_FSR = 0x70,
358 RDCR = 0x15,
359
360 READ = 0x03,
361 READ4 = 0x13,
362 FAST_READ = 0x0b,
363 FAST_READ4 = 0x0c,
364 DOR = 0x3b,
365 DOR4 = 0x3c,
366 QOR = 0x6b,
367 QOR4 = 0x6c,
368 DIOR = 0xbb,
369 DIOR4 = 0xbc,
370 QIOR = 0xeb,
371 QIOR4 = 0xec,
372
373 PP = 0x02,
374 PP4 = 0x12,
375 PP4_4 = 0x3e,
376 DPP = 0xa2,
377 QPP = 0x32,
378 QPP_4 = 0x34,
379 RDID_90 = 0x90,
380 RDID_AB = 0xab,
381 AAI_WP = 0xad,
382
383 ERASE_4K = 0x20,
384 ERASE4_4K = 0x21,
385 ERASE_32K = 0x52,
386 ERASE4_32K = 0x5c,
387 ERASE_SECTOR = 0xd8,
388 ERASE4_SECTOR = 0xdc,
389
390 EN_4BYTE_ADDR = 0xB7,
391 EX_4BYTE_ADDR = 0xE9,
392
393 EXTEND_ADDR_READ = 0xC8,
394 EXTEND_ADDR_WRITE = 0xC5,
395
396 RESET_ENABLE = 0x66,
397 RESET_MEMORY = 0x99,
398
399 /*
400 * Micron: 0x35 - enable QPI
401 * Spansion: 0x35 - read control register
402 */
403 RDCR_EQIO = 0x35,
404 RSTQIO = 0xf5,
405
406 RNVCR = 0xB5,
407 WNVCR = 0xB1,
408
409 RVCR = 0x85,
410 WVCR = 0x81,
411
412 REVCR = 0x65,
413 WEVCR = 0x61,
414
415 DIE_ERASE = 0xC4,
416 } FlashCMD;
417
418 typedef enum {
419 STATE_IDLE,
420 STATE_PAGE_PROGRAM,
421 STATE_READ,
422 STATE_COLLECTING_DATA,
423 STATE_COLLECTING_VAR_LEN_DATA,
424 STATE_READING_DATA,
425 } CMDState;
426
427 typedef enum {
428 MAN_SPANSION,
429 MAN_MACRONIX,
430 MAN_NUMONYX,
431 MAN_WINBOND,
432 MAN_SST,
433 MAN_ISSI,
434 MAN_GENERIC,
435 } Manufacturer;
436
437 typedef enum {
438 MODE_STD = 0,
439 MODE_DIO = 1,
440 MODE_QIO = 2
441 } SPIMode;
442
443 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
444
445 struct Flash {
446 SSIPeripheral parent_obj;
447
448 BlockBackend *blk;
449
450 uint8_t *storage;
451 uint32_t size;
452 int page_size;
453
454 uint8_t state;
455 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
456 uint32_t len;
457 uint32_t pos;
458 bool data_read_loop;
459 uint8_t needed_bytes;
460 uint8_t cmd_in_progress;
461 uint32_t cur_addr;
462 uint32_t nonvolatile_cfg;
463 /* Configuration register for Macronix */
464 uint32_t volatile_cfg;
465 uint32_t enh_volatile_cfg;
466 /* Spansion cfg registers. */
467 uint8_t spansion_cr1nv;
468 uint8_t spansion_cr2nv;
469 uint8_t spansion_cr3nv;
470 uint8_t spansion_cr4nv;
471 uint8_t spansion_cr1v;
472 uint8_t spansion_cr2v;
473 uint8_t spansion_cr3v;
474 uint8_t spansion_cr4v;
475 bool wp_level;
476 bool write_enable;
477 bool four_bytes_address_mode;
478 bool reset_enable;
479 bool quad_enable;
480 bool aai_enable;
481 bool status_register_write_disabled;
482 uint8_t ear;
483
484 int64_t dirty_page;
485
486 const FlashPartInfo *pi;
487
488 };
489
490 struct M25P80Class {
491 SSIPeripheralClass parent_class;
492 FlashPartInfo *pi;
493 };
494
495 #define TYPE_M25P80 "m25p80-generic"
496 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
497
498 static inline Manufacturer get_man(Flash *s)
499 {
500 switch (s->pi->id[0]) {
501 case 0x20:
502 return MAN_NUMONYX;
503 case 0xEF:
504 return MAN_WINBOND;
505 case 0x01:
506 return MAN_SPANSION;
507 case 0xC2:
508 return MAN_MACRONIX;
509 case 0xBF:
510 return MAN_SST;
511 case 0x9D:
512 return MAN_ISSI;
513 default:
514 return MAN_GENERIC;
515 }
516 }
517
518 static void blk_sync_complete(void *opaque, int ret)
519 {
520 QEMUIOVector *iov = opaque;
521
522 qemu_iovec_destroy(iov);
523 g_free(iov);
524
525 /* do nothing. Masters do not directly interact with the backing store,
526 * only the working copy so no mutexing required.
527 */
528 }
529
530 static void flash_sync_page(Flash *s, int page)
531 {
532 QEMUIOVector *iov;
533
534 if (!s->blk || !blk_is_writable(s->blk)) {
535 return;
536 }
537
538 iov = g_new(QEMUIOVector, 1);
539 qemu_iovec_init(iov, 1);
540 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
541 s->pi->page_size);
542 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
543 blk_sync_complete, iov);
544 }
545
546 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
547 {
548 QEMUIOVector *iov;
549
550 if (!s->blk || !blk_is_writable(s->blk)) {
551 return;
552 }
553
554 assert(!(len % BDRV_SECTOR_SIZE));
555 iov = g_new(QEMUIOVector, 1);
556 qemu_iovec_init(iov, 1);
557 qemu_iovec_add(iov, s->storage + off, len);
558 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
559 }
560
561 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
562 {
563 uint32_t len;
564 uint8_t capa_to_assert = 0;
565
566 switch (cmd) {
567 case ERASE_4K:
568 case ERASE4_4K:
569 len = 4 * KiB;
570 capa_to_assert = ER_4K;
571 break;
572 case ERASE_32K:
573 case ERASE4_32K:
574 len = 32 * KiB;
575 capa_to_assert = ER_32K;
576 break;
577 case ERASE_SECTOR:
578 case ERASE4_SECTOR:
579 len = s->pi->sector_size;
580 break;
581 case BULK_ERASE:
582 len = s->size;
583 break;
584 case DIE_ERASE:
585 if (s->pi->die_cnt) {
586 len = s->size / s->pi->die_cnt;
587 offset = offset & (~(len - 1));
588 } else {
589 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
590 " by device\n");
591 return;
592 }
593 break;
594 default:
595 abort();
596 }
597
598 trace_m25p80_flash_erase(s, offset, len);
599
600 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
601 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
602 " device\n", len);
603 }
604
605 if (!s->write_enable) {
606 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
607 return;
608 }
609 memset(s->storage + offset, 0xff, len);
610 flash_sync_area(s, offset, len);
611 }
612
613 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
614 {
615 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
616 flash_sync_page(s, s->dirty_page);
617 s->dirty_page = newpage;
618 }
619 }
620
621 static inline
622 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
623 {
624 uint32_t page = addr / s->pi->page_size;
625 uint8_t prev = s->storage[s->cur_addr];
626
627 if (!s->write_enable) {
628 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
629 return;
630 }
631
632 if ((prev ^ data) & data) {
633 trace_m25p80_programming_zero_to_one(s, addr, prev, data);
634 }
635
636 if (s->pi->flags & EEPROM) {
637 s->storage[s->cur_addr] = data;
638 } else {
639 s->storage[s->cur_addr] &= data;
640 }
641
642 flash_sync_dirty(s, page);
643 s->dirty_page = page;
644 }
645
646 static inline int get_addr_length(Flash *s)
647 {
648 /* check if eeprom is in use */
649 if (s->pi->flags == EEPROM) {
650 return 2;
651 }
652
653 switch (s->cmd_in_progress) {
654 case PP4:
655 case PP4_4:
656 case QPP_4:
657 case READ4:
658 case QIOR4:
659 case ERASE4_4K:
660 case ERASE4_32K:
661 case ERASE4_SECTOR:
662 case FAST_READ4:
663 case DOR4:
664 case QOR4:
665 case DIOR4:
666 return 4;
667 default:
668 return s->four_bytes_address_mode ? 4 : 3;
669 }
670 }
671
672 static void complete_collecting_data(Flash *s)
673 {
674 int i, n;
675
676 n = get_addr_length(s);
677 s->cur_addr = (n == 3 ? s->ear : 0);
678 for (i = 0; i < n; ++i) {
679 s->cur_addr <<= 8;
680 s->cur_addr |= s->data[i];
681 }
682
683 s->cur_addr &= s->size - 1;
684
685 s->state = STATE_IDLE;
686
687 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
688 s->cur_addr);
689
690 switch (s->cmd_in_progress) {
691 case DPP:
692 case QPP:
693 case QPP_4:
694 case PP:
695 case PP4:
696 case PP4_4:
697 s->state = STATE_PAGE_PROGRAM;
698 break;
699 case AAI_WP:
700 /* AAI programming starts from the even address */
701 s->cur_addr &= ~BIT(0);
702 s->state = STATE_PAGE_PROGRAM;
703 break;
704 case READ:
705 case READ4:
706 case FAST_READ:
707 case FAST_READ4:
708 case DOR:
709 case DOR4:
710 case QOR:
711 case QOR4:
712 case DIOR:
713 case DIOR4:
714 case QIOR:
715 case QIOR4:
716 s->state = STATE_READ;
717 break;
718 case ERASE_4K:
719 case ERASE4_4K:
720 case ERASE_32K:
721 case ERASE4_32K:
722 case ERASE_SECTOR:
723 case ERASE4_SECTOR:
724 case DIE_ERASE:
725 flash_erase(s, s->cur_addr, s->cmd_in_progress);
726 break;
727 case WRSR:
728 s->status_register_write_disabled = extract32(s->data[0], 7, 1);
729
730 switch (get_man(s)) {
731 case MAN_SPANSION:
732 s->quad_enable = !!(s->data[1] & 0x02);
733 break;
734 case MAN_ISSI:
735 s->quad_enable = extract32(s->data[0], 6, 1);
736 break;
737 case MAN_MACRONIX:
738 s->quad_enable = extract32(s->data[0], 6, 1);
739 if (s->len > 1) {
740 s->volatile_cfg = s->data[1];
741 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
742 }
743 break;
744 default:
745 break;
746 }
747 if (s->write_enable) {
748 s->write_enable = false;
749 }
750 break;
751 case BRWR:
752 case EXTEND_ADDR_WRITE:
753 s->ear = s->data[0];
754 break;
755 case WNVCR:
756 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
757 break;
758 case WVCR:
759 s->volatile_cfg = s->data[0];
760 break;
761 case WEVCR:
762 s->enh_volatile_cfg = s->data[0];
763 break;
764 case RDID_90:
765 case RDID_AB:
766 if (get_man(s) == MAN_SST) {
767 if (s->cur_addr <= 1) {
768 if (s->cur_addr) {
769 s->data[0] = s->pi->id[2];
770 s->data[1] = s->pi->id[0];
771 } else {
772 s->data[0] = s->pi->id[0];
773 s->data[1] = s->pi->id[2];
774 }
775 s->pos = 0;
776 s->len = 2;
777 s->data_read_loop = true;
778 s->state = STATE_READING_DATA;
779 } else {
780 qemu_log_mask(LOG_GUEST_ERROR,
781 "M25P80: Invalid read id address\n");
782 }
783 } else {
784 qemu_log_mask(LOG_GUEST_ERROR,
785 "M25P80: Read id (command 0x90/0xAB) is not supported"
786 " by device\n");
787 }
788 break;
789 default:
790 break;
791 }
792 }
793
794 static void reset_memory(Flash *s)
795 {
796 s->cmd_in_progress = NOP;
797 s->cur_addr = 0;
798 s->ear = 0;
799 s->four_bytes_address_mode = false;
800 s->len = 0;
801 s->needed_bytes = 0;
802 s->pos = 0;
803 s->state = STATE_IDLE;
804 s->write_enable = false;
805 s->reset_enable = false;
806 s->quad_enable = false;
807 s->aai_enable = false;
808
809 switch (get_man(s)) {
810 case MAN_NUMONYX:
811 s->volatile_cfg = 0;
812 s->volatile_cfg |= VCFG_DUMMY;
813 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
814 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
815 == NVCFG_XIP_MODE_DISABLED) {
816 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
817 }
818 s->volatile_cfg |= deposit32(s->volatile_cfg,
819 VCFG_DUMMY_CLK_POS,
820 CFG_DUMMY_CLK_LEN,
821 extract32(s->nonvolatile_cfg,
822 NVCFG_DUMMY_CLK_POS,
823 CFG_DUMMY_CLK_LEN)
824 );
825
826 s->enh_volatile_cfg = 0;
827 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
828 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
829 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
830 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
831 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
832 }
833 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
834 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
835 }
836 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
837 s->four_bytes_address_mode = true;
838 }
839 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
840 s->ear = s->size / MAX_3BYTES_SIZE - 1;
841 }
842 break;
843 case MAN_MACRONIX:
844 s->volatile_cfg = 0x7;
845 break;
846 case MAN_SPANSION:
847 s->spansion_cr1v = s->spansion_cr1nv;
848 s->spansion_cr2v = s->spansion_cr2nv;
849 s->spansion_cr3v = s->spansion_cr3nv;
850 s->spansion_cr4v = s->spansion_cr4nv;
851 s->quad_enable = extract32(s->spansion_cr1v,
852 SPANSION_QUAD_CFG_POS,
853 SPANSION_QUAD_CFG_LEN
854 );
855 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
856 SPANSION_ADDR_LEN_POS,
857 SPANSION_ADDR_LEN_LEN
858 );
859 break;
860 default:
861 break;
862 }
863
864 trace_m25p80_reset_done(s);
865 }
866
867 static uint8_t numonyx_mode(Flash *s)
868 {
869 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
870 return MODE_QIO;
871 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
872 return MODE_DIO;
873 } else {
874 return MODE_STD;
875 }
876 }
877
878 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
879 {
880 uint8_t num_dummies;
881 uint8_t mode;
882 assert(get_man(s) == MAN_NUMONYX);
883
884 mode = numonyx_mode(s);
885 num_dummies = extract32(s->volatile_cfg, 4, 4);
886
887 if (num_dummies == 0x0 || num_dummies == 0xf) {
888 switch (s->cmd_in_progress) {
889 case QIOR:
890 case QIOR4:
891 num_dummies = 10;
892 break;
893 default:
894 num_dummies = (mode == MODE_QIO) ? 10 : 8;
895 break;
896 }
897 }
898
899 return num_dummies;
900 }
901
902 static void decode_fast_read_cmd(Flash *s)
903 {
904 s->needed_bytes = get_addr_length(s);
905 switch (get_man(s)) {
906 /* Dummy cycles - modeled with bytes writes instead of bits */
907 case MAN_SST:
908 s->needed_bytes += 1;
909 break;
910 case MAN_WINBOND:
911 s->needed_bytes += 8;
912 break;
913 case MAN_NUMONYX:
914 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
915 break;
916 case MAN_MACRONIX:
917 if (extract32(s->volatile_cfg, 6, 2) == 1) {
918 s->needed_bytes += 6;
919 } else {
920 s->needed_bytes += 8;
921 }
922 break;
923 case MAN_SPANSION:
924 s->needed_bytes += extract32(s->spansion_cr2v,
925 SPANSION_DUMMY_CLK_POS,
926 SPANSION_DUMMY_CLK_LEN
927 );
928 break;
929 case MAN_ISSI:
930 /*
931 * The Fast Read instruction code is followed by address bytes and
932 * dummy cycles, transmitted via the SI line.
933 *
934 * The number of dummy cycles is configurable but this is currently
935 * unmodeled, hence the default value 8 is used.
936 *
937 * QPI (Quad Peripheral Interface) mode has different default value
938 * of dummy cycles, but this is unsupported at the time being.
939 */
940 s->needed_bytes += 1;
941 break;
942 default:
943 break;
944 }
945 s->pos = 0;
946 s->len = 0;
947 s->state = STATE_COLLECTING_DATA;
948 }
949
950 static void decode_dio_read_cmd(Flash *s)
951 {
952 s->needed_bytes = get_addr_length(s);
953 /* Dummy cycles modeled with bytes writes instead of bits */
954 switch (get_man(s)) {
955 case MAN_WINBOND:
956 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
957 break;
958 case MAN_SPANSION:
959 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
960 s->needed_bytes += extract32(s->spansion_cr2v,
961 SPANSION_DUMMY_CLK_POS,
962 SPANSION_DUMMY_CLK_LEN
963 );
964 break;
965 case MAN_NUMONYX:
966 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
967 break;
968 case MAN_MACRONIX:
969 switch (extract32(s->volatile_cfg, 6, 2)) {
970 case 1:
971 s->needed_bytes += 6;
972 break;
973 case 2:
974 s->needed_bytes += 8;
975 break;
976 default:
977 s->needed_bytes += 4;
978 break;
979 }
980 break;
981 case MAN_ISSI:
982 /*
983 * The Fast Read Dual I/O instruction code is followed by address bytes
984 * and dummy cycles, transmitted via the IO1 and IO0 line.
985 *
986 * The number of dummy cycles is configurable but this is currently
987 * unmodeled, hence the default value 4 is used.
988 */
989 s->needed_bytes += 1;
990 break;
991 default:
992 break;
993 }
994 s->pos = 0;
995 s->len = 0;
996 s->state = STATE_COLLECTING_DATA;
997 }
998
999 static void decode_qio_read_cmd(Flash *s)
1000 {
1001 s->needed_bytes = get_addr_length(s);
1002 /* Dummy cycles modeled with bytes writes instead of bits */
1003 switch (get_man(s)) {
1004 case MAN_WINBOND:
1005 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
1006 s->needed_bytes += 4;
1007 break;
1008 case MAN_SPANSION:
1009 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
1010 s->needed_bytes += extract32(s->spansion_cr2v,
1011 SPANSION_DUMMY_CLK_POS,
1012 SPANSION_DUMMY_CLK_LEN
1013 );
1014 break;
1015 case MAN_NUMONYX:
1016 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1017 break;
1018 case MAN_MACRONIX:
1019 switch (extract32(s->volatile_cfg, 6, 2)) {
1020 case 1:
1021 s->needed_bytes += 4;
1022 break;
1023 case 2:
1024 s->needed_bytes += 8;
1025 break;
1026 default:
1027 s->needed_bytes += 6;
1028 break;
1029 }
1030 break;
1031 case MAN_ISSI:
1032 /*
1033 * The Fast Read Quad I/O instruction code is followed by address bytes
1034 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.
1035 *
1036 * The number of dummy cycles is configurable but this is currently
1037 * unmodeled, hence the default value 6 is used.
1038 *
1039 * QPI (Quad Peripheral Interface) mode has different default value
1040 * of dummy cycles, but this is unsupported at the time being.
1041 */
1042 s->needed_bytes += 3;
1043 break;
1044 default:
1045 break;
1046 }
1047 s->pos = 0;
1048 s->len = 0;
1049 s->state = STATE_COLLECTING_DATA;
1050 }
1051
1052 static bool is_valid_aai_cmd(uint32_t cmd)
1053 {
1054 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
1055 }
1056
1057 static void decode_new_cmd(Flash *s, uint32_t value)
1058 {
1059 int i;
1060
1061 s->cmd_in_progress = value;
1062 trace_m25p80_command_decoded(s, value);
1063
1064 if (value != RESET_MEMORY) {
1065 s->reset_enable = false;
1066 }
1067
1068 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
1069 qemu_log_mask(LOG_GUEST_ERROR,
1070 "M25P80: Invalid cmd within AAI programming sequence");
1071 }
1072
1073 switch (value) {
1074
1075 case ERASE_4K:
1076 case ERASE4_4K:
1077 case ERASE_32K:
1078 case ERASE4_32K:
1079 case ERASE_SECTOR:
1080 case ERASE4_SECTOR:
1081 case PP:
1082 case PP4:
1083 case DIE_ERASE:
1084 case RDID_90:
1085 case RDID_AB:
1086 s->needed_bytes = get_addr_length(s);
1087 s->pos = 0;
1088 s->len = 0;
1089 s->state = STATE_COLLECTING_DATA;
1090 break;
1091 case READ:
1092 case READ4:
1093 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1094 s->needed_bytes = get_addr_length(s);
1095 s->pos = 0;
1096 s->len = 0;
1097 s->state = STATE_COLLECTING_DATA;
1098 } else {
1099 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1100 "DIO or QIO mode\n", s->cmd_in_progress);
1101 }
1102 break;
1103 case DPP:
1104 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1105 s->needed_bytes = get_addr_length(s);
1106 s->pos = 0;
1107 s->len = 0;
1108 s->state = STATE_COLLECTING_DATA;
1109 } else {
1110 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1111 "QIO mode\n", s->cmd_in_progress);
1112 }
1113 break;
1114 case QPP:
1115 case QPP_4:
1116 case PP4_4:
1117 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1118 s->needed_bytes = get_addr_length(s);
1119 s->pos = 0;
1120 s->len = 0;
1121 s->state = STATE_COLLECTING_DATA;
1122 } else {
1123 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1124 "DIO mode\n", s->cmd_in_progress);
1125 }
1126 break;
1127
1128 case FAST_READ:
1129 case FAST_READ4:
1130 decode_fast_read_cmd(s);
1131 break;
1132 case DOR:
1133 case DOR4:
1134 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1135 decode_fast_read_cmd(s);
1136 } else {
1137 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1138 "QIO mode\n", s->cmd_in_progress);
1139 }
1140 break;
1141 case QOR:
1142 case QOR4:
1143 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1144 decode_fast_read_cmd(s);
1145 } else {
1146 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1147 "DIO mode\n", s->cmd_in_progress);
1148 }
1149 break;
1150
1151 case DIOR:
1152 case DIOR4:
1153 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1154 decode_dio_read_cmd(s);
1155 } else {
1156 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1157 "QIO mode\n", s->cmd_in_progress);
1158 }
1159 break;
1160
1161 case QIOR:
1162 case QIOR4:
1163 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1164 decode_qio_read_cmd(s);
1165 } else {
1166 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1167 "DIO mode\n", s->cmd_in_progress);
1168 }
1169 break;
1170
1171 case WRSR:
1172 /*
1173 * If WP# is low and status_register_write_disabled is high,
1174 * status register writes are disabled.
1175 * This is also called "hardware protected mode" (HPM). All other
1176 * combinations of the two states are called "software protected mode"
1177 * (SPM), and status register writes are permitted.
1178 */
1179 if ((s->wp_level == 0 && s->status_register_write_disabled)
1180 || !s->write_enable) {
1181 qemu_log_mask(LOG_GUEST_ERROR,
1182 "M25P80: Status register write is disabled!\n");
1183 break;
1184 }
1185
1186 switch (get_man(s)) {
1187 case MAN_SPANSION:
1188 s->needed_bytes = 2;
1189 s->state = STATE_COLLECTING_DATA;
1190 break;
1191 case MAN_MACRONIX:
1192 s->needed_bytes = 2;
1193 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1194 break;
1195 default:
1196 s->needed_bytes = 1;
1197 s->state = STATE_COLLECTING_DATA;
1198 }
1199 s->pos = 0;
1200 break;
1201
1202 case WRDI:
1203 s->write_enable = false;
1204 if (get_man(s) == MAN_SST) {
1205 s->aai_enable = false;
1206 }
1207 break;
1208 case WREN:
1209 s->write_enable = true;
1210 break;
1211
1212 case RDSR:
1213 s->data[0] = (!!s->write_enable) << 1;
1214 s->data[0] |= (!!s->status_register_write_disabled) << 7;
1215
1216 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
1217 s->data[0] |= (!!s->quad_enable) << 6;
1218 }
1219 if (get_man(s) == MAN_SST) {
1220 s->data[0] |= (!!s->aai_enable) << 6;
1221 }
1222
1223 s->pos = 0;
1224 s->len = 1;
1225 s->data_read_loop = true;
1226 s->state = STATE_READING_DATA;
1227 break;
1228
1229 case READ_FSR:
1230 s->data[0] = FSR_FLASH_READY;
1231 if (s->four_bytes_address_mode) {
1232 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1233 }
1234 s->pos = 0;
1235 s->len = 1;
1236 s->data_read_loop = true;
1237 s->state = STATE_READING_DATA;
1238 break;
1239
1240 case JEDEC_READ:
1241 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1242 trace_m25p80_populated_jedec(s);
1243 for (i = 0; i < s->pi->id_len; i++) {
1244 s->data[i] = s->pi->id[i];
1245 }
1246 for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1247 s->data[i] = 0;
1248 }
1249
1250 s->len = SPI_NOR_MAX_ID_LEN;
1251 s->pos = 0;
1252 s->state = STATE_READING_DATA;
1253 } else {
1254 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
1255 "in DIO or QIO mode\n");
1256 }
1257 break;
1258
1259 case RDCR:
1260 s->data[0] = s->volatile_cfg & 0xFF;
1261 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1262 s->pos = 0;
1263 s->len = 1;
1264 s->state = STATE_READING_DATA;
1265 break;
1266
1267 case BULK_ERASE_60:
1268 case BULK_ERASE:
1269 if (s->write_enable) {
1270 trace_m25p80_chip_erase(s);
1271 flash_erase(s, 0, BULK_ERASE);
1272 } else {
1273 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1274 "protect!\n");
1275 }
1276 break;
1277 case NOP:
1278 break;
1279 case EN_4BYTE_ADDR:
1280 s->four_bytes_address_mode = true;
1281 break;
1282 case EX_4BYTE_ADDR:
1283 s->four_bytes_address_mode = false;
1284 break;
1285 case BRRD:
1286 case EXTEND_ADDR_READ:
1287 s->data[0] = s->ear;
1288 s->pos = 0;
1289 s->len = 1;
1290 s->state = STATE_READING_DATA;
1291 break;
1292 case BRWR:
1293 case EXTEND_ADDR_WRITE:
1294 if (s->write_enable) {
1295 s->needed_bytes = 1;
1296 s->pos = 0;
1297 s->len = 0;
1298 s->state = STATE_COLLECTING_DATA;
1299 }
1300 break;
1301 case RNVCR:
1302 s->data[0] = s->nonvolatile_cfg & 0xFF;
1303 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1304 s->pos = 0;
1305 s->len = 2;
1306 s->state = STATE_READING_DATA;
1307 break;
1308 case WNVCR:
1309 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1310 s->needed_bytes = 2;
1311 s->pos = 0;
1312 s->len = 0;
1313 s->state = STATE_COLLECTING_DATA;
1314 }
1315 break;
1316 case RVCR:
1317 s->data[0] = s->volatile_cfg & 0xFF;
1318 s->pos = 0;
1319 s->len = 1;
1320 s->state = STATE_READING_DATA;
1321 break;
1322 case WVCR:
1323 if (s->write_enable) {
1324 s->needed_bytes = 1;
1325 s->pos = 0;
1326 s->len = 0;
1327 s->state = STATE_COLLECTING_DATA;
1328 }
1329 break;
1330 case REVCR:
1331 s->data[0] = s->enh_volatile_cfg & 0xFF;
1332 s->pos = 0;
1333 s->len = 1;
1334 s->state = STATE_READING_DATA;
1335 break;
1336 case WEVCR:
1337 if (s->write_enable) {
1338 s->needed_bytes = 1;
1339 s->pos = 0;
1340 s->len = 0;
1341 s->state = STATE_COLLECTING_DATA;
1342 }
1343 break;
1344 case RESET_ENABLE:
1345 s->reset_enable = true;
1346 break;
1347 case RESET_MEMORY:
1348 if (s->reset_enable) {
1349 reset_memory(s);
1350 }
1351 break;
1352 case RDCR_EQIO:
1353 switch (get_man(s)) {
1354 case MAN_SPANSION:
1355 s->data[0] = (!!s->quad_enable) << 1;
1356 s->pos = 0;
1357 s->len = 1;
1358 s->state = STATE_READING_DATA;
1359 break;
1360 case MAN_MACRONIX:
1361 s->quad_enable = true;
1362 break;
1363 default:
1364 break;
1365 }
1366 break;
1367 case RSTQIO:
1368 s->quad_enable = false;
1369 break;
1370 case AAI_WP:
1371 if (get_man(s) == MAN_SST) {
1372 if (s->write_enable) {
1373 if (s->aai_enable) {
1374 s->state = STATE_PAGE_PROGRAM;
1375 } else {
1376 s->aai_enable = true;
1377 s->needed_bytes = get_addr_length(s);
1378 s->state = STATE_COLLECTING_DATA;
1379 }
1380 } else {
1381 qemu_log_mask(LOG_GUEST_ERROR,
1382 "M25P80: AAI_WP with write protect\n");
1383 }
1384 } else {
1385 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1386 }
1387 break;
1388 default:
1389 s->pos = 0;
1390 s->len = 1;
1391 s->state = STATE_READING_DATA;
1392 s->data_read_loop = true;
1393 s->data[0] = 0;
1394 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1395 break;
1396 }
1397 }
1398
1399 static int m25p80_cs(SSIPeripheral *ss, bool select)
1400 {
1401 Flash *s = M25P80(ss);
1402
1403 if (select) {
1404 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1405 complete_collecting_data(s);
1406 }
1407 s->len = 0;
1408 s->pos = 0;
1409 s->state = STATE_IDLE;
1410 flash_sync_dirty(s, -1);
1411 s->data_read_loop = false;
1412 }
1413
1414 trace_m25p80_select(s, select ? "de" : "");
1415
1416 return 0;
1417 }
1418
1419 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
1420 {
1421 Flash *s = M25P80(ss);
1422 uint32_t r = 0;
1423
1424 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1425 s->cur_addr, (uint8_t)tx);
1426
1427 switch (s->state) {
1428
1429 case STATE_PAGE_PROGRAM:
1430 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1431 flash_write8(s, s->cur_addr, (uint8_t)tx);
1432 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1433
1434 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
1435 /*
1436 * There is no wrap mode during AAI programming once the highest
1437 * unprotected memory address is reached. The Write-Enable-Latch
1438 * bit is automatically reset, and AAI programming mode aborts.
1439 */
1440 s->write_enable = false;
1441 s->aai_enable = false;
1442 }
1443
1444 break;
1445
1446 case STATE_READ:
1447 r = s->storage[s->cur_addr];
1448 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1449 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1450 break;
1451
1452 case STATE_COLLECTING_DATA:
1453 case STATE_COLLECTING_VAR_LEN_DATA:
1454
1455 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1456 qemu_log_mask(LOG_GUEST_ERROR,
1457 "M25P80: Write overrun internal data buffer. "
1458 "SPI controller (QEMU emulator or guest driver) "
1459 "is misbehaving\n");
1460 s->len = s->pos = 0;
1461 s->state = STATE_IDLE;
1462 break;
1463 }
1464
1465 s->data[s->len] = (uint8_t)tx;
1466 s->len++;
1467
1468 if (s->len == s->needed_bytes) {
1469 complete_collecting_data(s);
1470 }
1471 break;
1472
1473 case STATE_READING_DATA:
1474
1475 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1476 qemu_log_mask(LOG_GUEST_ERROR,
1477 "M25P80: Read overrun internal data buffer. "
1478 "SPI controller (QEMU emulator or guest driver) "
1479 "is misbehaving\n");
1480 s->len = s->pos = 0;
1481 s->state = STATE_IDLE;
1482 break;
1483 }
1484
1485 r = s->data[s->pos];
1486 trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1487 s->pos++;
1488 if (s->pos == s->len) {
1489 s->pos = 0;
1490 if (!s->data_read_loop) {
1491 s->state = STATE_IDLE;
1492 }
1493 }
1494 break;
1495
1496 default:
1497 case STATE_IDLE:
1498 decode_new_cmd(s, (uint8_t)tx);
1499 break;
1500 }
1501
1502 return r;
1503 }
1504
1505 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level)
1506 {
1507 Flash *s = M25P80(opaque);
1508 /* WP# is just a single pin. */
1509 assert(n == 0);
1510 s->wp_level = !!level;
1511 }
1512
1513 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
1514 {
1515 Flash *s = M25P80(ss);
1516 M25P80Class *mc = M25P80_GET_CLASS(s);
1517 int ret;
1518
1519 s->pi = mc->pi;
1520
1521 s->size = s->pi->sector_size * s->pi->n_sectors;
1522 s->dirty_page = -1;
1523
1524 if (s->blk) {
1525 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1526 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
1527 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1528 if (ret < 0) {
1529 return;
1530 }
1531
1532 trace_m25p80_binding(s);
1533 s->storage = blk_blockalign(s->blk, s->size);
1534
1535 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1536 error_setg(errp, "failed to read the initial flash content");
1537 return;
1538 }
1539 } else {
1540 trace_m25p80_binding_no_bdrv(s);
1541 s->storage = blk_blockalign(NULL, s->size);
1542 memset(s->storage, 0xFF, s->size);
1543 }
1544
1545 qdev_init_gpio_in_named(DEVICE(s),
1546 m25p80_write_protect_pin_irq_handler, "WP#", 1);
1547 }
1548
1549 static void m25p80_reset(DeviceState *d)
1550 {
1551 Flash *s = M25P80(d);
1552
1553 s->wp_level = true;
1554 s->status_register_write_disabled = false;
1555
1556 reset_memory(s);
1557 }
1558
1559 static int m25p80_pre_save(void *opaque)
1560 {
1561 flash_sync_dirty((Flash *)opaque, -1);
1562
1563 return 0;
1564 }
1565
1566 static Property m25p80_properties[] = {
1567 /* This is default value for Micron flash */
1568 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false),
1569 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1570 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1571 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1572 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1573 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1574 DEFINE_PROP_DRIVE("drive", Flash, blk),
1575 DEFINE_PROP_END_OF_LIST(),
1576 };
1577
1578 static int m25p80_pre_load(void *opaque)
1579 {
1580 Flash *s = (Flash *)opaque;
1581
1582 s->data_read_loop = false;
1583 return 0;
1584 }
1585
1586 static bool m25p80_data_read_loop_needed(void *opaque)
1587 {
1588 Flash *s = (Flash *)opaque;
1589
1590 return s->data_read_loop;
1591 }
1592
1593 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1594 .name = "m25p80/data_read_loop",
1595 .version_id = 1,
1596 .minimum_version_id = 1,
1597 .needed = m25p80_data_read_loop_needed,
1598 .fields = (VMStateField[]) {
1599 VMSTATE_BOOL(data_read_loop, Flash),
1600 VMSTATE_END_OF_LIST()
1601 }
1602 };
1603
1604 static bool m25p80_aai_enable_needed(void *opaque)
1605 {
1606 Flash *s = (Flash *)opaque;
1607
1608 return s->aai_enable;
1609 }
1610
1611 static const VMStateDescription vmstate_m25p80_aai_enable = {
1612 .name = "m25p80/aai_enable",
1613 .version_id = 1,
1614 .minimum_version_id = 1,
1615 .needed = m25p80_aai_enable_needed,
1616 .fields = (VMStateField[]) {
1617 VMSTATE_BOOL(aai_enable, Flash),
1618 VMSTATE_END_OF_LIST()
1619 }
1620 };
1621
1622 static bool m25p80_wp_level_srwd_needed(void *opaque)
1623 {
1624 Flash *s = (Flash *)opaque;
1625
1626 return !s->wp_level || s->status_register_write_disabled;
1627 }
1628
1629 static const VMStateDescription vmstate_m25p80_write_protect = {
1630 .name = "m25p80/write_protect",
1631 .version_id = 1,
1632 .minimum_version_id = 1,
1633 .needed = m25p80_wp_level_srwd_needed,
1634 .fields = (VMStateField[]) {
1635 VMSTATE_BOOL(wp_level, Flash),
1636 VMSTATE_BOOL(status_register_write_disabled, Flash),
1637 VMSTATE_END_OF_LIST()
1638 }
1639 };
1640
1641 static const VMStateDescription vmstate_m25p80 = {
1642 .name = "m25p80",
1643 .version_id = 0,
1644 .minimum_version_id = 0,
1645 .pre_save = m25p80_pre_save,
1646 .pre_load = m25p80_pre_load,
1647 .fields = (VMStateField[]) {
1648 VMSTATE_UINT8(state, Flash),
1649 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1650 VMSTATE_UINT32(len, Flash),
1651 VMSTATE_UINT32(pos, Flash),
1652 VMSTATE_UINT8(needed_bytes, Flash),
1653 VMSTATE_UINT8(cmd_in_progress, Flash),
1654 VMSTATE_UINT32(cur_addr, Flash),
1655 VMSTATE_BOOL(write_enable, Flash),
1656 VMSTATE_BOOL(reset_enable, Flash),
1657 VMSTATE_UINT8(ear, Flash),
1658 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1659 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1660 VMSTATE_UINT32(volatile_cfg, Flash),
1661 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1662 VMSTATE_BOOL(quad_enable, Flash),
1663 VMSTATE_UINT8(spansion_cr1nv, Flash),
1664 VMSTATE_UINT8(spansion_cr2nv, Flash),
1665 VMSTATE_UINT8(spansion_cr3nv, Flash),
1666 VMSTATE_UINT8(spansion_cr4nv, Flash),
1667 VMSTATE_END_OF_LIST()
1668 },
1669 .subsections = (const VMStateDescription * []) {
1670 &vmstate_m25p80_data_read_loop,
1671 &vmstate_m25p80_aai_enable,
1672 &vmstate_m25p80_write_protect,
1673 NULL
1674 }
1675 };
1676
1677 static void m25p80_class_init(ObjectClass *klass, void *data)
1678 {
1679 DeviceClass *dc = DEVICE_CLASS(klass);
1680 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
1681 M25P80Class *mc = M25P80_CLASS(klass);
1682
1683 k->realize = m25p80_realize;
1684 k->transfer = m25p80_transfer8;
1685 k->set_cs = m25p80_cs;
1686 k->cs_polarity = SSI_CS_LOW;
1687 dc->vmsd = &vmstate_m25p80;
1688 device_class_set_props(dc, m25p80_properties);
1689 dc->reset = m25p80_reset;
1690 mc->pi = data;
1691 }
1692
1693 static const TypeInfo m25p80_info = {
1694 .name = TYPE_M25P80,
1695 .parent = TYPE_SSI_PERIPHERAL,
1696 .instance_size = sizeof(Flash),
1697 .class_size = sizeof(M25P80Class),
1698 .abstract = true,
1699 };
1700
1701 static void m25p80_register_types(void)
1702 {
1703 int i;
1704
1705 type_register_static(&m25p80_info);
1706 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1707 TypeInfo ti = {
1708 .name = known_devices[i].part_name,
1709 .parent = TYPE_M25P80,
1710 .class_init = m25p80_class_init,
1711 .class_data = (void *)&known_devices[i],
1712 };
1713 type_register(&ti);
1714 }
1715 }
1716
1717 type_init(m25p80_register_types)
Ray Wang's QEMU Repository