2 * QEMU NVM Express Controller
4 * Copyright (c) 2012, Intel Corporation
6 * Written by Keith Busch <keith.busch@intel.com>
8 * This code is licensed under the GNU GPL v2 or later.
12 * Reference Specs: http://www.nvmexpress.org, 1.4, 1.3, 1.2, 1.1, 1.0e
14 * https://nvmexpress.org/developers/nvme-specification/
19 * -drive file=<file>,if=none,id=<drive_id>
20 * -device nvme-subsys,id=<subsys_id>,nqn=<nqn_id>
21 * -device nvme,serial=<serial>,id=<bus_name>, \
22 * cmb_size_mb=<cmb_size_mb[optional]>, \
23 * [pmrdev=<mem_backend_file_id>,] \
24 * max_ioqpairs=<N[optional]>, \
25 * aerl=<N[optional]>,aer_max_queued=<N[optional]>, \
26 * mdts=<N[optional]>,vsl=<N[optional]>, \
27 * zoned.zasl=<N[optional]>, \
29 * -device nvme-ns,drive=<drive_id>,bus=<bus_name>,nsid=<nsid>,\
30 * zoned=<true|false[optional]>, \
31 * subsys=<subsys_id>,detached=<true|false[optional]>
33 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
34 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. By default, the
35 * device will use the "v1.4 CMB scheme" - use the `legacy-cmb` parameter to
36 * always enable the CMBLOC and CMBSZ registers (v1.3 behavior).
38 * Enabling pmr emulation can be achieved by pointing to memory-backend-file.
40 * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
41 * size=<size> .... -device nvme,...,pmrdev=<mem_id>
43 * The PMR will use BAR 4/5 exclusively.
45 * To place controller(s) and namespace(s) to a subsystem, then provide
46 * nvme-subsys device as above.
48 * nvme subsystem device parameters
49 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
51 * This parameter provides the `<nqn_id>` part of the string
52 * `nqn.2019-08.org.qemu:<nqn_id>` which will be reported in the SUBNQN field
53 * of subsystem controllers. Note that `<nqn_id>` should be unique per
54 * subsystem, but this is not enforced by QEMU. If not specified, it will
55 * default to the value of the `id` parameter (`<subsys_id>`).
57 * nvme device parameters
58 * ~~~~~~~~~~~~~~~~~~~~~~
60 * Specifying this parameter attaches the controller to the subsystem and
61 * the SUBNQN field in the controller will report the NQN of the subsystem
62 * device. This also enables multi controller capability represented in
63 * Identify Controller data structure in CMIC (Controller Multi-path I/O and
64 * Namesapce Sharing Capabilities).
67 * The Asynchronous Event Request Limit (AERL). Indicates the maximum number
68 * of concurrently outstanding Asynchronous Event Request commands support
69 * by the controller. This is a 0's based value.
72 * This is the maximum number of events that the device will enqueue for
73 * completion when there are no outstanding AERs. When the maximum number of
74 * enqueued events are reached, subsequent events will be dropped.
77 * Indicates the maximum data transfer size for a command that transfers data
78 * between host-accessible memory and the controller. The value is specified
79 * as a power of two (2^n) and is in units of the minimum memory page size
80 * (CAP.MPSMIN). The default value is 7 (i.e. 512 KiB).
83 * Indicates the maximum data size limit for the Verify command. Like `mdts`,
84 * this value is specified as a power of two (2^n) and is in units of the
85 * minimum memory page size (CAP.MPSMIN). The default value is 7 (i.e. 512
89 * Indicates the maximum data transfer size for the Zone Append command. Like
90 * `mdts`, the value is specified as a power of two (2^n) and is in units of
91 * the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.e.
92 * defaulting to the value of `mdts`).
94 * nvme namespace device parameters
95 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
97 * When the parent nvme device (as defined explicitly by the 'bus' parameter
98 * or implicitly by the most recently defined NvmeBus) is linked to an
99 * nvme-subsys device, the namespace will be attached to all controllers in
100 * the subsystem. If set to 'off' (the default), the namespace will remain a
101 * private namespace and may only be attached to a single controller at a
105 * This parameter is only valid together with the `subsys` parameter. If left
106 * at the default value (`false/off`), the namespace will be attached to all
107 * controllers in the NVMe subsystem at boot-up. If set to `true/on`, the
108 * namespace will be be available in the subsystem not not attached to any
111 * Setting `zoned` to true selects Zoned Command Set at the namespace.
112 * In this case, the following namespace properties are available to configure
114 * zoned.zone_size=<zone size in bytes, default: 128MiB>
115 * The number may be followed by K, M, G as in kilo-, mega- or giga-.
117 * zoned.zone_capacity=<zone capacity in bytes, default: zone size>
118 * The value 0 (default) forces zone capacity to be the same as zone
119 * size. The value of this property may not exceed zone size.
121 * zoned.descr_ext_size=<zone descriptor extension size, default 0>
122 * This value needs to be specified in 64B units. If it is zero,
123 * namespace(s) will not support zone descriptor extensions.
125 * zoned.max_active=<Maximum Active Resources (zones), default: 0>
126 * The default value means there is no limit to the number of
127 * concurrently active zones.
129 * zoned.max_open=<Maximum Open Resources (zones), default: 0>
130 * The default value means there is no limit to the number of
131 * concurrently open zones.
133 * zoned.cross_read=<enable RAZB, default: false>
134 * Setting this property to true enables Read Across Zone Boundaries.
137 #include "qemu/osdep.h"
138 #include "qemu/units.h"
139 #include "qemu/error-report.h"
140 #include "hw/block/block.h"
141 #include "hw/pci/msix.h"
142 #include "hw/pci/pci.h"
143 #include "hw/qdev-properties.h"
144 #include "migration/vmstate.h"
145 #include "sysemu/sysemu.h"
146 #include "qapi/error.h"
147 #include "qapi/visitor.h"
148 #include "sysemu/hostmem.h"
149 #include "sysemu/block-backend.h"
150 #include "exec/memory.h"
151 #include "qemu/log.h"
152 #include "qemu/module.h"
153 #include "qemu/cutils.h"
157 #include "nvme-dif.h"
159 #define NVME_MAX_IOQPAIRS 0xffff
160 #define NVME_DB_SIZE 4
161 #define NVME_SPEC_VER 0x00010400
162 #define NVME_CMB_BIR 2
163 #define NVME_PMR_BIR 4
164 #define NVME_TEMPERATURE 0x143
165 #define NVME_TEMPERATURE_WARNING 0x157
166 #define NVME_TEMPERATURE_CRITICAL 0x175
167 #define NVME_NUM_FW_SLOTS 1
169 #define NVME_GUEST_ERR(trace, fmt, ...) \
171 (trace_##trace)(__VA_ARGS__); \
172 qemu_log_mask(LOG_GUEST_ERROR, #trace \
173 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
176 static const bool nvme_feature_support
[NVME_FID_MAX
] = {
177 [NVME_ARBITRATION
] = true,
178 [NVME_POWER_MANAGEMENT
] = true,
179 [NVME_TEMPERATURE_THRESHOLD
] = true,
180 [NVME_ERROR_RECOVERY
] = true,
181 [NVME_VOLATILE_WRITE_CACHE
] = true,
182 [NVME_NUMBER_OF_QUEUES
] = true,
183 [NVME_INTERRUPT_COALESCING
] = true,
184 [NVME_INTERRUPT_VECTOR_CONF
] = true,
185 [NVME_WRITE_ATOMICITY
] = true,
186 [NVME_ASYNCHRONOUS_EVENT_CONF
] = true,
187 [NVME_TIMESTAMP
] = true,
188 [NVME_COMMAND_SET_PROFILE
] = true,
191 static const uint32_t nvme_feature_cap
[NVME_FID_MAX
] = {
192 [NVME_TEMPERATURE_THRESHOLD
] = NVME_FEAT_CAP_CHANGE
,
193 [NVME_ERROR_RECOVERY
] = NVME_FEAT_CAP_CHANGE
| NVME_FEAT_CAP_NS
,
194 [NVME_VOLATILE_WRITE_CACHE
] = NVME_FEAT_CAP_CHANGE
,
195 [NVME_NUMBER_OF_QUEUES
] = NVME_FEAT_CAP_CHANGE
,
196 [NVME_ASYNCHRONOUS_EVENT_CONF
] = NVME_FEAT_CAP_CHANGE
,
197 [NVME_TIMESTAMP
] = NVME_FEAT_CAP_CHANGE
,
198 [NVME_COMMAND_SET_PROFILE
] = NVME_FEAT_CAP_CHANGE
,
201 static const uint32_t nvme_cse_acs
[256] = {
202 [NVME_ADM_CMD_DELETE_SQ
] = NVME_CMD_EFF_CSUPP
,
203 [NVME_ADM_CMD_CREATE_SQ
] = NVME_CMD_EFF_CSUPP
,
204 [NVME_ADM_CMD_GET_LOG_PAGE
] = NVME_CMD_EFF_CSUPP
,
205 [NVME_ADM_CMD_DELETE_CQ
] = NVME_CMD_EFF_CSUPP
,
206 [NVME_ADM_CMD_CREATE_CQ
] = NVME_CMD_EFF_CSUPP
,
207 [NVME_ADM_CMD_IDENTIFY
] = NVME_CMD_EFF_CSUPP
,
208 [NVME_ADM_CMD_ABORT
] = NVME_CMD_EFF_CSUPP
,
209 [NVME_ADM_CMD_SET_FEATURES
] = NVME_CMD_EFF_CSUPP
,
210 [NVME_ADM_CMD_GET_FEATURES
] = NVME_CMD_EFF_CSUPP
,
211 [NVME_ADM_CMD_ASYNC_EV_REQ
] = NVME_CMD_EFF_CSUPP
,
212 [NVME_ADM_CMD_NS_ATTACHMENT
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_NIC
,
213 [NVME_ADM_CMD_FORMAT_NVM
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
216 static const uint32_t nvme_cse_iocs_none
[256];
218 static const uint32_t nvme_cse_iocs_nvm
[256] = {
219 [NVME_CMD_FLUSH
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
220 [NVME_CMD_WRITE_ZEROES
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
221 [NVME_CMD_WRITE
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
222 [NVME_CMD_READ
] = NVME_CMD_EFF_CSUPP
,
223 [NVME_CMD_DSM
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
224 [NVME_CMD_VERIFY
] = NVME_CMD_EFF_CSUPP
,
225 [NVME_CMD_COPY
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
226 [NVME_CMD_COMPARE
] = NVME_CMD_EFF_CSUPP
,
229 static const uint32_t nvme_cse_iocs_zoned
[256] = {
230 [NVME_CMD_FLUSH
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
231 [NVME_CMD_WRITE_ZEROES
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
232 [NVME_CMD_WRITE
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
233 [NVME_CMD_READ
] = NVME_CMD_EFF_CSUPP
,
234 [NVME_CMD_DSM
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
235 [NVME_CMD_VERIFY
] = NVME_CMD_EFF_CSUPP
,
236 [NVME_CMD_COPY
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
237 [NVME_CMD_COMPARE
] = NVME_CMD_EFF_CSUPP
,
238 [NVME_CMD_ZONE_APPEND
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
239 [NVME_CMD_ZONE_MGMT_SEND
] = NVME_CMD_EFF_CSUPP
| NVME_CMD_EFF_LBCC
,
240 [NVME_CMD_ZONE_MGMT_RECV
] = NVME_CMD_EFF_CSUPP
,
243 static void nvme_process_sq(void *opaque
);
245 static uint16_t nvme_sqid(NvmeRequest
*req
)
247 return le16_to_cpu(req
->sq
->sqid
);
250 static void nvme_assign_zone_state(NvmeNamespace
*ns
, NvmeZone
*zone
,
253 if (QTAILQ_IN_USE(zone
, entry
)) {
254 switch (nvme_get_zone_state(zone
)) {
255 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
256 QTAILQ_REMOVE(&ns
->exp_open_zones
, zone
, entry
);
258 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
259 QTAILQ_REMOVE(&ns
->imp_open_zones
, zone
, entry
);
261 case NVME_ZONE_STATE_CLOSED
:
262 QTAILQ_REMOVE(&ns
->closed_zones
, zone
, entry
);
264 case NVME_ZONE_STATE_FULL
:
265 QTAILQ_REMOVE(&ns
->full_zones
, zone
, entry
);
271 nvme_set_zone_state(zone
, state
);
274 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
275 QTAILQ_INSERT_TAIL(&ns
->exp_open_zones
, zone
, entry
);
277 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
278 QTAILQ_INSERT_TAIL(&ns
->imp_open_zones
, zone
, entry
);
280 case NVME_ZONE_STATE_CLOSED
:
281 QTAILQ_INSERT_TAIL(&ns
->closed_zones
, zone
, entry
);
283 case NVME_ZONE_STATE_FULL
:
284 QTAILQ_INSERT_TAIL(&ns
->full_zones
, zone
, entry
);
285 case NVME_ZONE_STATE_READ_ONLY
:
293 * Check if we can open a zone without exceeding open/active limits.
294 * AOR stands for "Active and Open Resources" (see TP 4053 section 2.5).
296 static int nvme_aor_check(NvmeNamespace
*ns
, uint32_t act
, uint32_t opn
)
298 if (ns
->params
.max_active_zones
!= 0 &&
299 ns
->nr_active_zones
+ act
> ns
->params
.max_active_zones
) {
300 trace_pci_nvme_err_insuff_active_res(ns
->params
.max_active_zones
);
301 return NVME_ZONE_TOO_MANY_ACTIVE
| NVME_DNR
;
303 if (ns
->params
.max_open_zones
!= 0 &&
304 ns
->nr_open_zones
+ opn
> ns
->params
.max_open_zones
) {
305 trace_pci_nvme_err_insuff_open_res(ns
->params
.max_open_zones
);
306 return NVME_ZONE_TOO_MANY_OPEN
| NVME_DNR
;
312 static bool nvme_addr_is_cmb(NvmeCtrl
*n
, hwaddr addr
)
320 lo
= n
->params
.legacy_cmb
? n
->cmb
.mem
.addr
: n
->cmb
.cba
;
321 hi
= lo
+ int128_get64(n
->cmb
.mem
.size
);
323 return addr
>= lo
&& addr
< hi
;
326 static inline void *nvme_addr_to_cmb(NvmeCtrl
*n
, hwaddr addr
)
328 hwaddr base
= n
->params
.legacy_cmb
? n
->cmb
.mem
.addr
: n
->cmb
.cba
;
329 return &n
->cmb
.buf
[addr
- base
];
332 static bool nvme_addr_is_pmr(NvmeCtrl
*n
, hwaddr addr
)
340 hi
= n
->pmr
.cba
+ int128_get64(n
->pmr
.dev
->mr
.size
);
342 return addr
>= n
->pmr
.cba
&& addr
< hi
;
345 static inline void *nvme_addr_to_pmr(NvmeCtrl
*n
, hwaddr addr
)
347 return memory_region_get_ram_ptr(&n
->pmr
.dev
->mr
) + (addr
- n
->pmr
.cba
);
350 static int nvme_addr_read(NvmeCtrl
*n
, hwaddr addr
, void *buf
, int size
)
352 hwaddr hi
= addr
+ size
- 1;
357 if (n
->bar
.cmbsz
&& nvme_addr_is_cmb(n
, addr
) && nvme_addr_is_cmb(n
, hi
)) {
358 memcpy(buf
, nvme_addr_to_cmb(n
, addr
), size
);
362 if (nvme_addr_is_pmr(n
, addr
) && nvme_addr_is_pmr(n
, hi
)) {
363 memcpy(buf
, nvme_addr_to_pmr(n
, addr
), size
);
367 return pci_dma_read(&n
->parent_obj
, addr
, buf
, size
);
370 static int nvme_addr_write(NvmeCtrl
*n
, hwaddr addr
, void *buf
, int size
)
372 hwaddr hi
= addr
+ size
- 1;
377 if (n
->bar
.cmbsz
&& nvme_addr_is_cmb(n
, addr
) && nvme_addr_is_cmb(n
, hi
)) {
378 memcpy(nvme_addr_to_cmb(n
, addr
), buf
, size
);
382 if (nvme_addr_is_pmr(n
, addr
) && nvme_addr_is_pmr(n
, hi
)) {
383 memcpy(nvme_addr_to_pmr(n
, addr
), buf
, size
);
387 return pci_dma_write(&n
->parent_obj
, addr
, buf
, size
);
390 static bool nvme_nsid_valid(NvmeCtrl
*n
, uint32_t nsid
)
392 return nsid
&& (nsid
== NVME_NSID_BROADCAST
|| nsid
<= n
->num_namespaces
);
395 static int nvme_check_sqid(NvmeCtrl
*n
, uint16_t sqid
)
397 return sqid
< n
->params
.max_ioqpairs
+ 1 && n
->sq
[sqid
] != NULL
? 0 : -1;
400 static int nvme_check_cqid(NvmeCtrl
*n
, uint16_t cqid
)
402 return cqid
< n
->params
.max_ioqpairs
+ 1 && n
->cq
[cqid
] != NULL
? 0 : -1;
405 static void nvme_inc_cq_tail(NvmeCQueue
*cq
)
408 if (cq
->tail
>= cq
->size
) {
410 cq
->phase
= !cq
->phase
;
414 static void nvme_inc_sq_head(NvmeSQueue
*sq
)
416 sq
->head
= (sq
->head
+ 1) % sq
->size
;
419 static uint8_t nvme_cq_full(NvmeCQueue
*cq
)
421 return (cq
->tail
+ 1) % cq
->size
== cq
->head
;
424 static uint8_t nvme_sq_empty(NvmeSQueue
*sq
)
426 return sq
->head
== sq
->tail
;
429 static void nvme_irq_check(NvmeCtrl
*n
)
431 if (msix_enabled(&(n
->parent_obj
))) {
434 if (~n
->bar
.intms
& n
->irq_status
) {
435 pci_irq_assert(&n
->parent_obj
);
437 pci_irq_deassert(&n
->parent_obj
);
441 static void nvme_irq_assert(NvmeCtrl
*n
, NvmeCQueue
*cq
)
443 if (cq
->irq_enabled
) {
444 if (msix_enabled(&(n
->parent_obj
))) {
445 trace_pci_nvme_irq_msix(cq
->vector
);
446 msix_notify(&(n
->parent_obj
), cq
->vector
);
448 trace_pci_nvme_irq_pin();
449 assert(cq
->vector
< 32);
450 n
->irq_status
|= 1 << cq
->vector
;
454 trace_pci_nvme_irq_masked();
458 static void nvme_irq_deassert(NvmeCtrl
*n
, NvmeCQueue
*cq
)
460 if (cq
->irq_enabled
) {
461 if (msix_enabled(&(n
->parent_obj
))) {
464 assert(cq
->vector
< 32);
465 n
->irq_status
&= ~(1 << cq
->vector
);
471 static void nvme_req_clear(NvmeRequest
*req
)
476 memset(&req
->cqe
, 0x0, sizeof(req
->cqe
));
477 req
->status
= NVME_SUCCESS
;
480 static inline void nvme_sg_init(NvmeCtrl
*n
, NvmeSg
*sg
, bool dma
)
483 pci_dma_sglist_init(&sg
->qsg
, &n
->parent_obj
, 0);
484 sg
->flags
= NVME_SG_DMA
;
486 qemu_iovec_init(&sg
->iov
, 0);
489 sg
->flags
|= NVME_SG_ALLOC
;
492 static inline void nvme_sg_unmap(NvmeSg
*sg
)
494 if (!(sg
->flags
& NVME_SG_ALLOC
)) {
498 if (sg
->flags
& NVME_SG_DMA
) {
499 qemu_sglist_destroy(&sg
->qsg
);
501 qemu_iovec_destroy(&sg
->iov
);
504 memset(sg
, 0x0, sizeof(*sg
));
508 * When metadata is transfered as extended LBAs, the DPTR mapped into `sg`
509 * holds both data and metadata. This function splits the data and metadata
510 * into two separate QSG/IOVs.
512 static void nvme_sg_split(NvmeSg
*sg
, NvmeNamespace
*ns
, NvmeSg
*data
,
516 size_t size
= nvme_lsize(ns
);
517 size_t msize
= nvme_msize(ns
);
518 uint32_t trans_len
, count
= size
;
520 bool dma
= sg
->flags
& NVME_SG_DMA
;
522 size_t sg_len
= dma
? sg
->qsg
.size
: sg
->iov
.size
;
525 assert(sg
->flags
& NVME_SG_ALLOC
);
528 sge_len
= dma
? sg
->qsg
.sg
[sg_idx
].len
: sg
->iov
.iov
[sg_idx
].iov_len
;
530 trans_len
= MIN(sg_len
, count
);
531 trans_len
= MIN(trans_len
, sge_len
- offset
);
535 qemu_sglist_add(&dst
->qsg
, sg
->qsg
.sg
[sg_idx
].base
+ offset
,
538 qemu_iovec_add(&dst
->iov
,
539 sg
->iov
.iov
[sg_idx
].iov_base
+ offset
,
549 dst
= (dst
== data
) ? mdata
: data
;
550 count
= (dst
== data
) ? size
: msize
;
553 if (sge_len
== offset
) {
560 static uint16_t nvme_map_addr_cmb(NvmeCtrl
*n
, QEMUIOVector
*iov
, hwaddr addr
,
567 trace_pci_nvme_map_addr_cmb(addr
, len
);
569 if (!nvme_addr_is_cmb(n
, addr
) || !nvme_addr_is_cmb(n
, addr
+ len
- 1)) {
570 return NVME_DATA_TRAS_ERROR
;
573 qemu_iovec_add(iov
, nvme_addr_to_cmb(n
, addr
), len
);
578 static uint16_t nvme_map_addr_pmr(NvmeCtrl
*n
, QEMUIOVector
*iov
, hwaddr addr
,
585 if (!nvme_addr_is_pmr(n
, addr
) || !nvme_addr_is_pmr(n
, addr
+ len
- 1)) {
586 return NVME_DATA_TRAS_ERROR
;
589 qemu_iovec_add(iov
, nvme_addr_to_pmr(n
, addr
), len
);
594 static uint16_t nvme_map_addr(NvmeCtrl
*n
, NvmeSg
*sg
, hwaddr addr
, size_t len
)
596 bool cmb
= false, pmr
= false;
602 trace_pci_nvme_map_addr(addr
, len
);
604 if (nvme_addr_is_cmb(n
, addr
)) {
606 } else if (nvme_addr_is_pmr(n
, addr
)) {
611 if (sg
->flags
& NVME_SG_DMA
) {
612 return NVME_INVALID_USE_OF_CMB
| NVME_DNR
;
616 return nvme_map_addr_cmb(n
, &sg
->iov
, addr
, len
);
618 return nvme_map_addr_pmr(n
, &sg
->iov
, addr
, len
);
622 if (!(sg
->flags
& NVME_SG_DMA
)) {
623 return NVME_INVALID_USE_OF_CMB
| NVME_DNR
;
626 qemu_sglist_add(&sg
->qsg
, addr
, len
);
631 static inline bool nvme_addr_is_dma(NvmeCtrl
*n
, hwaddr addr
)
633 return !(nvme_addr_is_cmb(n
, addr
) || nvme_addr_is_pmr(n
, addr
));
636 static uint16_t nvme_map_prp(NvmeCtrl
*n
, NvmeSg
*sg
, uint64_t prp1
,
637 uint64_t prp2
, uint32_t len
)
639 hwaddr trans_len
= n
->page_size
- (prp1
% n
->page_size
);
640 trans_len
= MIN(len
, trans_len
);
641 int num_prps
= (len
>> n
->page_bits
) + 1;
645 trace_pci_nvme_map_prp(trans_len
, len
, prp1
, prp2
, num_prps
);
647 nvme_sg_init(n
, sg
, nvme_addr_is_dma(n
, prp1
));
649 status
= nvme_map_addr(n
, sg
, prp1
, trans_len
);
656 if (len
> n
->page_size
) {
657 uint64_t prp_list
[n
->max_prp_ents
];
658 uint32_t nents
, prp_trans
;
662 * The first PRP list entry, pointed to by PRP2 may contain offset.
663 * Hence, we need to calculate the number of entries in based on
666 nents
= (n
->page_size
- (prp2
& (n
->page_size
- 1))) >> 3;
667 prp_trans
= MIN(n
->max_prp_ents
, nents
) * sizeof(uint64_t);
668 ret
= nvme_addr_read(n
, prp2
, (void *)prp_list
, prp_trans
);
670 trace_pci_nvme_err_addr_read(prp2
);
671 status
= NVME_DATA_TRAS_ERROR
;
675 uint64_t prp_ent
= le64_to_cpu(prp_list
[i
]);
677 if (i
== nents
- 1 && len
> n
->page_size
) {
678 if (unlikely(prp_ent
& (n
->page_size
- 1))) {
679 trace_pci_nvme_err_invalid_prplist_ent(prp_ent
);
680 status
= NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
685 nents
= (len
+ n
->page_size
- 1) >> n
->page_bits
;
686 nents
= MIN(nents
, n
->max_prp_ents
);
687 prp_trans
= nents
* sizeof(uint64_t);
688 ret
= nvme_addr_read(n
, prp_ent
, (void *)prp_list
,
691 trace_pci_nvme_err_addr_read(prp_ent
);
692 status
= NVME_DATA_TRAS_ERROR
;
695 prp_ent
= le64_to_cpu(prp_list
[i
]);
698 if (unlikely(prp_ent
& (n
->page_size
- 1))) {
699 trace_pci_nvme_err_invalid_prplist_ent(prp_ent
);
700 status
= NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
704 trans_len
= MIN(len
, n
->page_size
);
705 status
= nvme_map_addr(n
, sg
, prp_ent
, trans_len
);
714 if (unlikely(prp2
& (n
->page_size
- 1))) {
715 trace_pci_nvme_err_invalid_prp2_align(prp2
);
716 status
= NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
719 status
= nvme_map_addr(n
, sg
, prp2
, len
);
734 * Map 'nsgld' data descriptors from 'segment'. The function will subtract the
735 * number of bytes mapped in len.
737 static uint16_t nvme_map_sgl_data(NvmeCtrl
*n
, NvmeSg
*sg
,
738 NvmeSglDescriptor
*segment
, uint64_t nsgld
,
739 size_t *len
, NvmeCmd
*cmd
)
741 dma_addr_t addr
, trans_len
;
745 for (int i
= 0; i
< nsgld
; i
++) {
746 uint8_t type
= NVME_SGL_TYPE(segment
[i
].type
);
749 case NVME_SGL_DESCR_TYPE_BIT_BUCKET
:
750 if (cmd
->opcode
== NVME_CMD_WRITE
) {
753 case NVME_SGL_DESCR_TYPE_DATA_BLOCK
:
755 case NVME_SGL_DESCR_TYPE_SEGMENT
:
756 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT
:
757 return NVME_INVALID_NUM_SGL_DESCRS
| NVME_DNR
;
759 return NVME_SGL_DESCR_TYPE_INVALID
| NVME_DNR
;
762 dlen
= le32_to_cpu(segment
[i
].len
);
770 * All data has been mapped, but the SGL contains additional
771 * segments and/or descriptors. The controller might accept
772 * ignoring the rest of the SGL.
774 uint32_t sgls
= le32_to_cpu(n
->id_ctrl
.sgls
);
775 if (sgls
& NVME_CTRL_SGLS_EXCESS_LENGTH
) {
779 trace_pci_nvme_err_invalid_sgl_excess_length(dlen
);
780 return NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
783 trans_len
= MIN(*len
, dlen
);
785 if (type
== NVME_SGL_DESCR_TYPE_BIT_BUCKET
) {
789 addr
= le64_to_cpu(segment
[i
].addr
);
791 if (UINT64_MAX
- addr
< dlen
) {
792 return NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
795 status
= nvme_map_addr(n
, sg
, addr
, trans_len
);
807 static uint16_t nvme_map_sgl(NvmeCtrl
*n
, NvmeSg
*sg
, NvmeSglDescriptor sgl
,
808 size_t len
, NvmeCmd
*cmd
)
811 * Read the segment in chunks of 256 descriptors (one 4k page) to avoid
812 * dynamically allocating a potentially huge SGL. The spec allows the SGL
813 * to be larger (as in number of bytes required to describe the SGL
814 * descriptors and segment chain) than the command transfer size, so it is
815 * not bounded by MDTS.
817 const int SEG_CHUNK_SIZE
= 256;
819 NvmeSglDescriptor segment
[SEG_CHUNK_SIZE
], *sgld
, *last_sgld
;
827 addr
= le64_to_cpu(sgl
.addr
);
829 trace_pci_nvme_map_sgl(NVME_SGL_TYPE(sgl
.type
), len
);
831 nvme_sg_init(n
, sg
, nvme_addr_is_dma(n
, addr
));
834 * If the entire transfer can be described with a single data block it can
835 * be mapped directly.
837 if (NVME_SGL_TYPE(sgl
.type
) == NVME_SGL_DESCR_TYPE_DATA_BLOCK
) {
838 status
= nvme_map_sgl_data(n
, sg
, sgld
, 1, &len
, cmd
);
847 switch (NVME_SGL_TYPE(sgld
->type
)) {
848 case NVME_SGL_DESCR_TYPE_SEGMENT
:
849 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT
:
852 return NVME_INVALID_SGL_SEG_DESCR
| NVME_DNR
;
855 seg_len
= le32_to_cpu(sgld
->len
);
857 /* check the length of the (Last) Segment descriptor */
858 if ((!seg_len
|| seg_len
& 0xf) &&
859 (NVME_SGL_TYPE(sgld
->type
) != NVME_SGL_DESCR_TYPE_BIT_BUCKET
)) {
860 return NVME_INVALID_SGL_SEG_DESCR
| NVME_DNR
;
863 if (UINT64_MAX
- addr
< seg_len
) {
864 return NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
867 nsgld
= seg_len
/ sizeof(NvmeSglDescriptor
);
869 while (nsgld
> SEG_CHUNK_SIZE
) {
870 if (nvme_addr_read(n
, addr
, segment
, sizeof(segment
))) {
871 trace_pci_nvme_err_addr_read(addr
);
872 status
= NVME_DATA_TRAS_ERROR
;
876 status
= nvme_map_sgl_data(n
, sg
, segment
, SEG_CHUNK_SIZE
,
882 nsgld
-= SEG_CHUNK_SIZE
;
883 addr
+= SEG_CHUNK_SIZE
* sizeof(NvmeSglDescriptor
);
886 ret
= nvme_addr_read(n
, addr
, segment
, nsgld
*
887 sizeof(NvmeSglDescriptor
));
889 trace_pci_nvme_err_addr_read(addr
);
890 status
= NVME_DATA_TRAS_ERROR
;
894 last_sgld
= &segment
[nsgld
- 1];
897 * If the segment ends with a Data Block or Bit Bucket Descriptor Type,
900 switch (NVME_SGL_TYPE(last_sgld
->type
)) {
901 case NVME_SGL_DESCR_TYPE_DATA_BLOCK
:
902 case NVME_SGL_DESCR_TYPE_BIT_BUCKET
:
903 status
= nvme_map_sgl_data(n
, sg
, segment
, nsgld
, &len
, cmd
);
915 * If the last descriptor was not a Data Block or Bit Bucket, then the
916 * current segment must not be a Last Segment.
918 if (NVME_SGL_TYPE(sgld
->type
) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT
) {
919 status
= NVME_INVALID_SGL_SEG_DESCR
| NVME_DNR
;
924 addr
= le64_to_cpu(sgld
->addr
);
927 * Do not map the last descriptor; it will be a Segment or Last Segment
928 * descriptor and is handled by the next iteration.
930 status
= nvme_map_sgl_data(n
, sg
, segment
, nsgld
- 1, &len
, cmd
);
937 /* if there is any residual left in len, the SGL was too short */
939 status
= NVME_DATA_SGL_LEN_INVALID
| NVME_DNR
;
950 uint16_t nvme_map_dptr(NvmeCtrl
*n
, NvmeSg
*sg
, size_t len
,
955 switch (NVME_CMD_FLAGS_PSDT(cmd
->flags
)) {
957 prp1
= le64_to_cpu(cmd
->dptr
.prp1
);
958 prp2
= le64_to_cpu(cmd
->dptr
.prp2
);
960 return nvme_map_prp(n
, sg
, prp1
, prp2
, len
);
961 case NVME_PSDT_SGL_MPTR_CONTIGUOUS
:
962 case NVME_PSDT_SGL_MPTR_SGL
:
963 return nvme_map_sgl(n
, sg
, cmd
->dptr
.sgl
, len
, cmd
);
965 return NVME_INVALID_FIELD
;
969 static uint16_t nvme_map_mptr(NvmeCtrl
*n
, NvmeSg
*sg
, size_t len
,
972 int psdt
= NVME_CMD_FLAGS_PSDT(cmd
->flags
);
973 hwaddr mptr
= le64_to_cpu(cmd
->mptr
);
976 if (psdt
== NVME_PSDT_SGL_MPTR_SGL
) {
977 NvmeSglDescriptor sgl
;
979 if (nvme_addr_read(n
, mptr
, &sgl
, sizeof(sgl
))) {
980 return NVME_DATA_TRAS_ERROR
;
983 status
= nvme_map_sgl(n
, sg
, sgl
, len
, cmd
);
984 if (status
&& (status
& 0x7ff) == NVME_DATA_SGL_LEN_INVALID
) {
985 status
= NVME_MD_SGL_LEN_INVALID
| NVME_DNR
;
991 nvme_sg_init(n
, sg
, nvme_addr_is_dma(n
, mptr
));
992 status
= nvme_map_addr(n
, sg
, mptr
, len
);
1000 static uint16_t nvme_map_data(NvmeCtrl
*n
, uint32_t nlb
, NvmeRequest
*req
)
1002 NvmeNamespace
*ns
= req
->ns
;
1003 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1004 uint16_t ctrl
= le16_to_cpu(rw
->control
);
1005 size_t len
= nvme_l2b(ns
, nlb
);
1008 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
) &&
1009 (ctrl
& NVME_RW_PRINFO_PRACT
&& nvme_msize(ns
) == 8)) {
1013 if (nvme_ns_ext(ns
)) {
1016 len
+= nvme_m2b(ns
, nlb
);
1018 status
= nvme_map_dptr(n
, &sg
, len
, &req
->cmd
);
1023 nvme_sg_init(n
, &req
->sg
, sg
.flags
& NVME_SG_DMA
);
1024 nvme_sg_split(&sg
, ns
, &req
->sg
, NULL
);
1027 return NVME_SUCCESS
;
1031 return nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
1034 static uint16_t nvme_map_mdata(NvmeCtrl
*n
, uint32_t nlb
, NvmeRequest
*req
)
1036 NvmeNamespace
*ns
= req
->ns
;
1037 size_t len
= nvme_m2b(ns
, nlb
);
1040 if (nvme_ns_ext(ns
)) {
1043 len
+= nvme_l2b(ns
, nlb
);
1045 status
= nvme_map_dptr(n
, &sg
, len
, &req
->cmd
);
1050 nvme_sg_init(n
, &req
->sg
, sg
.flags
& NVME_SG_DMA
);
1051 nvme_sg_split(&sg
, ns
, NULL
, &req
->sg
);
1054 return NVME_SUCCESS
;
1057 return nvme_map_mptr(n
, &req
->sg
, len
, &req
->cmd
);
1060 static uint16_t nvme_tx_interleaved(NvmeCtrl
*n
, NvmeSg
*sg
, uint8_t *ptr
,
1061 uint32_t len
, uint32_t bytes
,
1062 int32_t skip_bytes
, int64_t offset
,
1063 NvmeTxDirection dir
)
1066 uint32_t trans_len
, count
= bytes
;
1067 bool dma
= sg
->flags
& NVME_SG_DMA
;
1072 assert(sg
->flags
& NVME_SG_ALLOC
);
1075 sge_len
= dma
? sg
->qsg
.sg
[sg_idx
].len
: sg
->iov
.iov
[sg_idx
].iov_len
;
1077 if (sge_len
- offset
< 0) {
1083 if (sge_len
== offset
) {
1089 trans_len
= MIN(len
, count
);
1090 trans_len
= MIN(trans_len
, sge_len
- offset
);
1093 addr
= sg
->qsg
.sg
[sg_idx
].base
+ offset
;
1095 addr
= (hwaddr
)(uintptr_t)sg
->iov
.iov
[sg_idx
].iov_base
+ offset
;
1098 if (dir
== NVME_TX_DIRECTION_TO_DEVICE
) {
1099 ret
= nvme_addr_read(n
, addr
, ptr
, trans_len
);
1101 ret
= nvme_addr_write(n
, addr
, ptr
, trans_len
);
1105 return NVME_DATA_TRAS_ERROR
;
1111 offset
+= trans_len
;
1115 offset
+= skip_bytes
;
1119 return NVME_SUCCESS
;
1122 static uint16_t nvme_tx(NvmeCtrl
*n
, NvmeSg
*sg
, uint8_t *ptr
, uint32_t len
,
1123 NvmeTxDirection dir
)
1125 assert(sg
->flags
& NVME_SG_ALLOC
);
1127 if (sg
->flags
& NVME_SG_DMA
) {
1130 if (dir
== NVME_TX_DIRECTION_TO_DEVICE
) {
1131 residual
= dma_buf_write(ptr
, len
, &sg
->qsg
);
1133 residual
= dma_buf_read(ptr
, len
, &sg
->qsg
);
1136 if (unlikely(residual
)) {
1137 trace_pci_nvme_err_invalid_dma();
1138 return NVME_INVALID_FIELD
| NVME_DNR
;
1143 if (dir
== NVME_TX_DIRECTION_TO_DEVICE
) {
1144 bytes
= qemu_iovec_to_buf(&sg
->iov
, 0, ptr
, len
);
1146 bytes
= qemu_iovec_from_buf(&sg
->iov
, 0, ptr
, len
);
1149 if (unlikely(bytes
!= len
)) {
1150 trace_pci_nvme_err_invalid_dma();
1151 return NVME_INVALID_FIELD
| NVME_DNR
;
1155 return NVME_SUCCESS
;
1158 static inline uint16_t nvme_c2h(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1163 status
= nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
1168 return nvme_tx(n
, &req
->sg
, ptr
, len
, NVME_TX_DIRECTION_FROM_DEVICE
);
1171 static inline uint16_t nvme_h2c(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1176 status
= nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
1181 return nvme_tx(n
, &req
->sg
, ptr
, len
, NVME_TX_DIRECTION_TO_DEVICE
);
1184 uint16_t nvme_bounce_data(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1185 NvmeTxDirection dir
, NvmeRequest
*req
)
1187 NvmeNamespace
*ns
= req
->ns
;
1188 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1189 uint16_t ctrl
= le16_to_cpu(rw
->control
);
1191 if (nvme_ns_ext(ns
) &&
1192 !(ctrl
& NVME_RW_PRINFO_PRACT
&& nvme_msize(ns
) == 8)) {
1193 size_t lsize
= nvme_lsize(ns
);
1194 size_t msize
= nvme_msize(ns
);
1196 return nvme_tx_interleaved(n
, &req
->sg
, ptr
, len
, lsize
, msize
, 0,
1200 return nvme_tx(n
, &req
->sg
, ptr
, len
, dir
);
1203 uint16_t nvme_bounce_mdata(NvmeCtrl
*n
, uint8_t *ptr
, uint32_t len
,
1204 NvmeTxDirection dir
, NvmeRequest
*req
)
1206 NvmeNamespace
*ns
= req
->ns
;
1209 if (nvme_ns_ext(ns
)) {
1210 size_t lsize
= nvme_lsize(ns
);
1211 size_t msize
= nvme_msize(ns
);
1213 return nvme_tx_interleaved(n
, &req
->sg
, ptr
, len
, msize
, lsize
, lsize
,
1217 nvme_sg_unmap(&req
->sg
);
1219 status
= nvme_map_mptr(n
, &req
->sg
, len
, &req
->cmd
);
1224 return nvme_tx(n
, &req
->sg
, ptr
, len
, dir
);
1227 static inline void nvme_blk_read(BlockBackend
*blk
, int64_t offset
,
1228 BlockCompletionFunc
*cb
, NvmeRequest
*req
)
1230 assert(req
->sg
.flags
& NVME_SG_ALLOC
);
1232 if (req
->sg
.flags
& NVME_SG_DMA
) {
1233 req
->aiocb
= dma_blk_read(blk
, &req
->sg
.qsg
, offset
, BDRV_SECTOR_SIZE
,
1236 req
->aiocb
= blk_aio_preadv(blk
, offset
, &req
->sg
.iov
, 0, cb
, req
);
1240 static inline void nvme_blk_write(BlockBackend
*blk
, int64_t offset
,
1241 BlockCompletionFunc
*cb
, NvmeRequest
*req
)
1243 assert(req
->sg
.flags
& NVME_SG_ALLOC
);
1245 if (req
->sg
.flags
& NVME_SG_DMA
) {
1246 req
->aiocb
= dma_blk_write(blk
, &req
->sg
.qsg
, offset
, BDRV_SECTOR_SIZE
,
1249 req
->aiocb
= blk_aio_pwritev(blk
, offset
, &req
->sg
.iov
, 0, cb
, req
);
1253 static void nvme_post_cqes(void *opaque
)
1255 NvmeCQueue
*cq
= opaque
;
1256 NvmeCtrl
*n
= cq
->ctrl
;
1257 NvmeRequest
*req
, *next
;
1260 QTAILQ_FOREACH_SAFE(req
, &cq
->req_list
, entry
, next
) {
1264 if (nvme_cq_full(cq
)) {
1269 req
->cqe
.status
= cpu_to_le16((req
->status
<< 1) | cq
->phase
);
1270 req
->cqe
.sq_id
= cpu_to_le16(sq
->sqid
);
1271 req
->cqe
.sq_head
= cpu_to_le16(sq
->head
);
1272 addr
= cq
->dma_addr
+ cq
->tail
* n
->cqe_size
;
1273 ret
= pci_dma_write(&n
->parent_obj
, addr
, (void *)&req
->cqe
,
1276 trace_pci_nvme_err_addr_write(addr
);
1277 trace_pci_nvme_err_cfs();
1278 n
->bar
.csts
= NVME_CSTS_FAILED
;
1281 QTAILQ_REMOVE(&cq
->req_list
, req
, entry
);
1282 nvme_inc_cq_tail(cq
);
1283 nvme_sg_unmap(&req
->sg
);
1284 QTAILQ_INSERT_TAIL(&sq
->req_list
, req
, entry
);
1286 if (cq
->tail
!= cq
->head
) {
1287 nvme_irq_assert(n
, cq
);
1291 static void nvme_enqueue_req_completion(NvmeCQueue
*cq
, NvmeRequest
*req
)
1293 assert(cq
->cqid
== req
->sq
->cqid
);
1294 trace_pci_nvme_enqueue_req_completion(nvme_cid(req
), cq
->cqid
,
1298 trace_pci_nvme_err_req_status(nvme_cid(req
), nvme_nsid(req
->ns
),
1299 req
->status
, req
->cmd
.opcode
);
1302 QTAILQ_REMOVE(&req
->sq
->out_req_list
, req
, entry
);
1303 QTAILQ_INSERT_TAIL(&cq
->req_list
, req
, entry
);
1304 timer_mod(cq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
1307 static void nvme_process_aers(void *opaque
)
1309 NvmeCtrl
*n
= opaque
;
1310 NvmeAsyncEvent
*event
, *next
;
1312 trace_pci_nvme_process_aers(n
->aer_queued
);
1314 QTAILQ_FOREACH_SAFE(event
, &n
->aer_queue
, entry
, next
) {
1316 NvmeAerResult
*result
;
1318 /* can't post cqe if there is nothing to complete */
1319 if (!n
->outstanding_aers
) {
1320 trace_pci_nvme_no_outstanding_aers();
1324 /* ignore if masked (cqe posted, but event not cleared) */
1325 if (n
->aer_mask
& (1 << event
->result
.event_type
)) {
1326 trace_pci_nvme_aer_masked(event
->result
.event_type
, n
->aer_mask
);
1330 QTAILQ_REMOVE(&n
->aer_queue
, event
, entry
);
1333 n
->aer_mask
|= 1 << event
->result
.event_type
;
1334 n
->outstanding_aers
--;
1336 req
= n
->aer_reqs
[n
->outstanding_aers
];
1338 result
= (NvmeAerResult
*) &req
->cqe
.result
;
1339 result
->event_type
= event
->result
.event_type
;
1340 result
->event_info
= event
->result
.event_info
;
1341 result
->log_page
= event
->result
.log_page
;
1344 trace_pci_nvme_aer_post_cqe(result
->event_type
, result
->event_info
,
1347 nvme_enqueue_req_completion(&n
->admin_cq
, req
);
1351 static void nvme_enqueue_event(NvmeCtrl
*n
, uint8_t event_type
,
1352 uint8_t event_info
, uint8_t log_page
)
1354 NvmeAsyncEvent
*event
;
1356 trace_pci_nvme_enqueue_event(event_type
, event_info
, log_page
);
1358 if (n
->aer_queued
== n
->params
.aer_max_queued
) {
1359 trace_pci_nvme_enqueue_event_noqueue(n
->aer_queued
);
1363 event
= g_new(NvmeAsyncEvent
, 1);
1364 event
->result
= (NvmeAerResult
) {
1365 .event_type
= event_type
,
1366 .event_info
= event_info
,
1367 .log_page
= log_page
,
1370 QTAILQ_INSERT_TAIL(&n
->aer_queue
, event
, entry
);
1373 nvme_process_aers(n
);
1376 static void nvme_smart_event(NvmeCtrl
*n
, uint8_t event
)
1380 /* Ref SPEC <Asynchronous Event Information 0x2013 SMART / Health Status> */
1381 if (!(NVME_AEC_SMART(n
->features
.async_config
) & event
)) {
1386 case NVME_SMART_SPARE
:
1387 aer_info
= NVME_AER_INFO_SMART_SPARE_THRESH
;
1389 case NVME_SMART_TEMPERATURE
:
1390 aer_info
= NVME_AER_INFO_SMART_TEMP_THRESH
;
1392 case NVME_SMART_RELIABILITY
:
1393 case NVME_SMART_MEDIA_READ_ONLY
:
1394 case NVME_SMART_FAILED_VOLATILE_MEDIA
:
1395 case NVME_SMART_PMR_UNRELIABLE
:
1396 aer_info
= NVME_AER_INFO_SMART_RELIABILITY
;
1402 nvme_enqueue_event(n
, NVME_AER_TYPE_SMART
, aer_info
, NVME_LOG_SMART_INFO
);
1405 static void nvme_clear_events(NvmeCtrl
*n
, uint8_t event_type
)
1407 n
->aer_mask
&= ~(1 << event_type
);
1408 if (!QTAILQ_EMPTY(&n
->aer_queue
)) {
1409 nvme_process_aers(n
);
1413 static inline uint16_t nvme_check_mdts(NvmeCtrl
*n
, size_t len
)
1415 uint8_t mdts
= n
->params
.mdts
;
1417 if (mdts
&& len
> n
->page_size
<< mdts
) {
1418 trace_pci_nvme_err_mdts(len
);
1419 return NVME_INVALID_FIELD
| NVME_DNR
;
1422 return NVME_SUCCESS
;
1425 static inline uint16_t nvme_check_bounds(NvmeNamespace
*ns
, uint64_t slba
,
1428 uint64_t nsze
= le64_to_cpu(ns
->id_ns
.nsze
);
1430 if (unlikely(UINT64_MAX
- slba
< nlb
|| slba
+ nlb
> nsze
)) {
1431 trace_pci_nvme_err_invalid_lba_range(slba
, nlb
, nsze
);
1432 return NVME_LBA_RANGE
| NVME_DNR
;
1435 return NVME_SUCCESS
;
1438 static uint16_t nvme_check_dulbe(NvmeNamespace
*ns
, uint64_t slba
,
1441 BlockDriverState
*bs
= blk_bs(ns
->blkconf
.blk
);
1443 int64_t pnum
= 0, bytes
= nvme_l2b(ns
, nlb
);
1444 int64_t offset
= nvme_l2b(ns
, slba
);
1448 Error
*local_err
= NULL
;
1451 * `pnum` holds the number of bytes after offset that shares the same
1452 * allocation status as the byte at offset. If `pnum` is different from
1453 * `bytes`, we should check the allocation status of the next range and
1454 * continue this until all bytes have been checked.
1459 ret
= bdrv_block_status(bs
, offset
, bytes
, &pnum
, NULL
, NULL
);
1461 error_setg_errno(&local_err
, -ret
, "unable to get block status");
1462 error_report_err(local_err
);
1464 return NVME_INTERNAL_DEV_ERROR
;
1467 zeroed
= !!(ret
& BDRV_BLOCK_ZERO
);
1469 trace_pci_nvme_block_status(offset
, bytes
, pnum
, ret
, zeroed
);
1476 } while (pnum
!= bytes
);
1478 return NVME_SUCCESS
;
1481 static void nvme_aio_err(NvmeRequest
*req
, int ret
)
1483 uint16_t status
= NVME_SUCCESS
;
1484 Error
*local_err
= NULL
;
1486 switch (req
->cmd
.opcode
) {
1488 status
= NVME_UNRECOVERED_READ
;
1490 case NVME_CMD_FLUSH
:
1491 case NVME_CMD_WRITE
:
1492 case NVME_CMD_WRITE_ZEROES
:
1493 case NVME_CMD_ZONE_APPEND
:
1494 status
= NVME_WRITE_FAULT
;
1497 status
= NVME_INTERNAL_DEV_ERROR
;
1501 trace_pci_nvme_err_aio(nvme_cid(req
), strerror(-ret
), status
);
1503 error_setg_errno(&local_err
, -ret
, "aio failed");
1504 error_report_err(local_err
);
1507 * Set the command status code to the first encountered error but allow a
1508 * subsequent Internal Device Error to trump it.
1510 if (req
->status
&& status
!= NVME_INTERNAL_DEV_ERROR
) {
1514 req
->status
= status
;
1517 static inline uint32_t nvme_zone_idx(NvmeNamespace
*ns
, uint64_t slba
)
1519 return ns
->zone_size_log2
> 0 ? slba
>> ns
->zone_size_log2
:
1520 slba
/ ns
->zone_size
;
1523 static inline NvmeZone
*nvme_get_zone_by_slba(NvmeNamespace
*ns
, uint64_t slba
)
1525 uint32_t zone_idx
= nvme_zone_idx(ns
, slba
);
1527 assert(zone_idx
< ns
->num_zones
);
1528 return &ns
->zone_array
[zone_idx
];
1531 static uint16_t nvme_check_zone_state_for_write(NvmeZone
*zone
)
1533 uint64_t zslba
= zone
->d
.zslba
;
1535 switch (nvme_get_zone_state(zone
)) {
1536 case NVME_ZONE_STATE_EMPTY
:
1537 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1538 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1539 case NVME_ZONE_STATE_CLOSED
:
1540 return NVME_SUCCESS
;
1541 case NVME_ZONE_STATE_FULL
:
1542 trace_pci_nvme_err_zone_is_full(zslba
);
1543 return NVME_ZONE_FULL
;
1544 case NVME_ZONE_STATE_OFFLINE
:
1545 trace_pci_nvme_err_zone_is_offline(zslba
);
1546 return NVME_ZONE_OFFLINE
;
1547 case NVME_ZONE_STATE_READ_ONLY
:
1548 trace_pci_nvme_err_zone_is_read_only(zslba
);
1549 return NVME_ZONE_READ_ONLY
;
1554 return NVME_INTERNAL_DEV_ERROR
;
1557 static uint16_t nvme_check_zone_write(NvmeNamespace
*ns
, NvmeZone
*zone
,
1558 uint64_t slba
, uint32_t nlb
)
1560 uint64_t zcap
= nvme_zone_wr_boundary(zone
);
1563 status
= nvme_check_zone_state_for_write(zone
);
1568 if (unlikely(slba
!= zone
->w_ptr
)) {
1569 trace_pci_nvme_err_write_not_at_wp(slba
, zone
->d
.zslba
, zone
->w_ptr
);
1570 return NVME_ZONE_INVALID_WRITE
;
1573 if (unlikely((slba
+ nlb
) > zcap
)) {
1574 trace_pci_nvme_err_zone_boundary(slba
, nlb
, zcap
);
1575 return NVME_ZONE_BOUNDARY_ERROR
;
1578 return NVME_SUCCESS
;
1581 static uint16_t nvme_check_zone_state_for_read(NvmeZone
*zone
)
1583 switch (nvme_get_zone_state(zone
)) {
1584 case NVME_ZONE_STATE_EMPTY
:
1585 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1586 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1587 case NVME_ZONE_STATE_FULL
:
1588 case NVME_ZONE_STATE_CLOSED
:
1589 case NVME_ZONE_STATE_READ_ONLY
:
1590 return NVME_SUCCESS
;
1591 case NVME_ZONE_STATE_OFFLINE
:
1592 trace_pci_nvme_err_zone_is_offline(zone
->d
.zslba
);
1593 return NVME_ZONE_OFFLINE
;
1598 return NVME_INTERNAL_DEV_ERROR
;
1601 static uint16_t nvme_check_zone_read(NvmeNamespace
*ns
, uint64_t slba
,
1604 NvmeZone
*zone
= nvme_get_zone_by_slba(ns
, slba
);
1605 uint64_t bndry
= nvme_zone_rd_boundary(ns
, zone
);
1606 uint64_t end
= slba
+ nlb
;
1609 status
= nvme_check_zone_state_for_read(zone
);
1612 } else if (unlikely(end
> bndry
)) {
1613 if (!ns
->params
.cross_zone_read
) {
1614 status
= NVME_ZONE_BOUNDARY_ERROR
;
1617 * Read across zone boundary - check that all subsequent
1618 * zones that are being read have an appropriate state.
1622 status
= nvme_check_zone_state_for_read(zone
);
1626 } while (end
> nvme_zone_rd_boundary(ns
, zone
));
1633 static uint16_t nvme_zrm_finish(NvmeNamespace
*ns
, NvmeZone
*zone
)
1635 switch (nvme_get_zone_state(zone
)) {
1636 case NVME_ZONE_STATE_FULL
:
1637 return NVME_SUCCESS
;
1639 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1640 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1641 nvme_aor_dec_open(ns
);
1643 case NVME_ZONE_STATE_CLOSED
:
1644 nvme_aor_dec_active(ns
);
1646 case NVME_ZONE_STATE_EMPTY
:
1647 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_FULL
);
1648 return NVME_SUCCESS
;
1651 return NVME_ZONE_INVAL_TRANSITION
;
1655 static uint16_t nvme_zrm_close(NvmeNamespace
*ns
, NvmeZone
*zone
)
1657 switch (nvme_get_zone_state(zone
)) {
1658 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1659 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1660 nvme_aor_dec_open(ns
);
1661 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_CLOSED
);
1663 case NVME_ZONE_STATE_CLOSED
:
1664 return NVME_SUCCESS
;
1667 return NVME_ZONE_INVAL_TRANSITION
;
1671 static void nvme_zrm_auto_transition_zone(NvmeNamespace
*ns
)
1675 if (ns
->params
.max_open_zones
&&
1676 ns
->nr_open_zones
== ns
->params
.max_open_zones
) {
1677 zone
= QTAILQ_FIRST(&ns
->imp_open_zones
);
1680 * Automatically close this implicitly open zone.
1682 QTAILQ_REMOVE(&ns
->imp_open_zones
, zone
, entry
);
1683 nvme_zrm_close(ns
, zone
);
1688 static uint16_t __nvme_zrm_open(NvmeNamespace
*ns
, NvmeZone
*zone
,
1694 switch (nvme_get_zone_state(zone
)) {
1695 case NVME_ZONE_STATE_EMPTY
:
1700 case NVME_ZONE_STATE_CLOSED
:
1701 nvme_zrm_auto_transition_zone(ns
);
1702 status
= nvme_aor_check(ns
, act
, 1);
1708 nvme_aor_inc_active(ns
);
1711 nvme_aor_inc_open(ns
);
1714 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_IMPLICITLY_OPEN
);
1715 return NVME_SUCCESS
;
1720 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
1722 return NVME_SUCCESS
;
1725 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_EXPLICITLY_OPEN
);
1729 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
1730 return NVME_SUCCESS
;
1733 return NVME_ZONE_INVAL_TRANSITION
;
1737 static inline uint16_t nvme_zrm_auto(NvmeNamespace
*ns
, NvmeZone
*zone
)
1739 return __nvme_zrm_open(ns
, zone
, true);
1742 static inline uint16_t nvme_zrm_open(NvmeNamespace
*ns
, NvmeZone
*zone
)
1744 return __nvme_zrm_open(ns
, zone
, false);
1747 static void __nvme_advance_zone_wp(NvmeNamespace
*ns
, NvmeZone
*zone
,
1752 if (zone
->d
.wp
== nvme_zone_wr_boundary(zone
)) {
1753 nvme_zrm_finish(ns
, zone
);
1757 static void nvme_finalize_zoned_write(NvmeNamespace
*ns
, NvmeRequest
*req
)
1759 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1764 slba
= le64_to_cpu(rw
->slba
);
1765 nlb
= le16_to_cpu(rw
->nlb
) + 1;
1766 zone
= nvme_get_zone_by_slba(ns
, slba
);
1768 __nvme_advance_zone_wp(ns
, zone
, nlb
);
1771 static inline bool nvme_is_write(NvmeRequest
*req
)
1773 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1775 return rw
->opcode
== NVME_CMD_WRITE
||
1776 rw
->opcode
== NVME_CMD_ZONE_APPEND
||
1777 rw
->opcode
== NVME_CMD_WRITE_ZEROES
;
1780 static void nvme_misc_cb(void *opaque
, int ret
)
1782 NvmeRequest
*req
= opaque
;
1783 NvmeNamespace
*ns
= req
->ns
;
1785 BlockBackend
*blk
= ns
->blkconf
.blk
;
1786 BlockAcctCookie
*acct
= &req
->acct
;
1787 BlockAcctStats
*stats
= blk_get_stats(blk
);
1789 trace_pci_nvme_misc_cb(nvme_cid(req
), blk_name(blk
));
1792 block_acct_failed(stats
, acct
);
1793 nvme_aio_err(req
, ret
);
1795 block_acct_done(stats
, acct
);
1798 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1801 void nvme_rw_complete_cb(void *opaque
, int ret
)
1803 NvmeRequest
*req
= opaque
;
1804 NvmeNamespace
*ns
= req
->ns
;
1805 BlockBackend
*blk
= ns
->blkconf
.blk
;
1806 BlockAcctCookie
*acct
= &req
->acct
;
1807 BlockAcctStats
*stats
= blk_get_stats(blk
);
1809 trace_pci_nvme_rw_complete_cb(nvme_cid(req
), blk_name(blk
));
1812 block_acct_failed(stats
, acct
);
1813 nvme_aio_err(req
, ret
);
1815 block_acct_done(stats
, acct
);
1818 if (ns
->params
.zoned
&& nvme_is_write(req
)) {
1819 nvme_finalize_zoned_write(ns
, req
);
1822 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1825 static void nvme_rw_cb(void *opaque
, int ret
)
1827 NvmeRequest
*req
= opaque
;
1828 NvmeNamespace
*ns
= req
->ns
;
1830 BlockBackend
*blk
= ns
->blkconf
.blk
;
1832 trace_pci_nvme_rw_cb(nvme_cid(req
), blk_name(blk
));
1838 if (nvme_msize(ns
)) {
1839 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1840 uint64_t slba
= le64_to_cpu(rw
->slba
);
1841 uint32_t nlb
= (uint32_t)le16_to_cpu(rw
->nlb
) + 1;
1842 uint64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
1844 if (req
->cmd
.opcode
== NVME_CMD_WRITE_ZEROES
) {
1845 size_t mlen
= nvme_m2b(ns
, nlb
);
1847 req
->aiocb
= blk_aio_pwrite_zeroes(blk
, offset
, mlen
,
1849 nvme_rw_complete_cb
, req
);
1853 if (nvme_ns_ext(ns
) || req
->cmd
.mptr
) {
1856 nvme_sg_unmap(&req
->sg
);
1857 status
= nvme_map_mdata(nvme_ctrl(req
), nlb
, req
);
1863 if (req
->cmd
.opcode
== NVME_CMD_READ
) {
1864 return nvme_blk_read(blk
, offset
, nvme_rw_complete_cb
, req
);
1867 return nvme_blk_write(blk
, offset
, nvme_rw_complete_cb
, req
);
1872 nvme_rw_complete_cb(req
, ret
);
1875 struct nvme_aio_format_ctx
{
1879 /* number of outstanding write zeroes for this namespace */
1883 static void nvme_aio_format_cb(void *opaque
, int ret
)
1885 struct nvme_aio_format_ctx
*ctx
= opaque
;
1886 NvmeRequest
*req
= ctx
->req
;
1887 NvmeNamespace
*ns
= ctx
->ns
;
1888 uintptr_t *num_formats
= (uintptr_t *)&req
->opaque
;
1889 int *count
= ctx
->count
;
1894 nvme_aio_err(req
, ret
);
1904 if (--(*num_formats
)) {
1908 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1911 struct nvme_aio_flush_ctx
{
1914 BlockAcctCookie acct
;
1917 static void nvme_aio_flush_cb(void *opaque
, int ret
)
1919 struct nvme_aio_flush_ctx
*ctx
= opaque
;
1920 NvmeRequest
*req
= ctx
->req
;
1921 uintptr_t *num_flushes
= (uintptr_t *)&req
->opaque
;
1923 BlockBackend
*blk
= ctx
->ns
->blkconf
.blk
;
1924 BlockAcctCookie
*acct
= &ctx
->acct
;
1925 BlockAcctStats
*stats
= blk_get_stats(blk
);
1927 trace_pci_nvme_aio_flush_cb(nvme_cid(req
), blk_name(blk
));
1930 block_acct_done(stats
, acct
);
1932 block_acct_failed(stats
, acct
);
1933 nvme_aio_err(req
, ret
);
1943 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1946 static void nvme_verify_cb(void *opaque
, int ret
)
1948 NvmeBounceContext
*ctx
= opaque
;
1949 NvmeRequest
*req
= ctx
->req
;
1950 NvmeNamespace
*ns
= req
->ns
;
1951 BlockBackend
*blk
= ns
->blkconf
.blk
;
1952 BlockAcctCookie
*acct
= &req
->acct
;
1953 BlockAcctStats
*stats
= blk_get_stats(blk
);
1954 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
1955 uint64_t slba
= le64_to_cpu(rw
->slba
);
1956 uint16_t ctrl
= le16_to_cpu(rw
->control
);
1957 uint16_t apptag
= le16_to_cpu(rw
->apptag
);
1958 uint16_t appmask
= le16_to_cpu(rw
->appmask
);
1959 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
1962 trace_pci_nvme_verify_cb(nvme_cid(req
), NVME_RW_PRINFO(ctrl
), apptag
,
1966 block_acct_failed(stats
, acct
);
1967 nvme_aio_err(req
, ret
);
1971 block_acct_done(stats
, acct
);
1973 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
1974 status
= nvme_dif_mangle_mdata(ns
, ctx
->mdata
.bounce
,
1975 ctx
->mdata
.iov
.size
, slba
);
1977 req
->status
= status
;
1981 req
->status
= nvme_dif_check(ns
, ctx
->data
.bounce
, ctx
->data
.iov
.size
,
1982 ctx
->mdata
.bounce
, ctx
->mdata
.iov
.size
,
1983 ctrl
, slba
, apptag
, appmask
, reftag
);
1987 qemu_iovec_destroy(&ctx
->data
.iov
);
1988 g_free(ctx
->data
.bounce
);
1990 qemu_iovec_destroy(&ctx
->mdata
.iov
);
1991 g_free(ctx
->mdata
.bounce
);
1995 nvme_enqueue_req_completion(nvme_cq(req
), req
);
1999 static void nvme_verify_mdata_in_cb(void *opaque
, int ret
)
2001 NvmeBounceContext
*ctx
= opaque
;
2002 NvmeRequest
*req
= ctx
->req
;
2003 NvmeNamespace
*ns
= req
->ns
;
2004 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2005 uint64_t slba
= le64_to_cpu(rw
->slba
);
2006 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2007 size_t mlen
= nvme_m2b(ns
, nlb
);
2008 uint64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
2009 BlockBackend
*blk
= ns
->blkconf
.blk
;
2011 trace_pci_nvme_verify_mdata_in_cb(nvme_cid(req
), blk_name(blk
));
2017 ctx
->mdata
.bounce
= g_malloc(mlen
);
2019 qemu_iovec_reset(&ctx
->mdata
.iov
);
2020 qemu_iovec_add(&ctx
->mdata
.iov
, ctx
->mdata
.bounce
, mlen
);
2022 req
->aiocb
= blk_aio_preadv(blk
, offset
, &ctx
->mdata
.iov
, 0,
2023 nvme_verify_cb
, ctx
);
2027 nvme_verify_cb(ctx
, ret
);
2030 static void nvme_aio_discard_cb(void *opaque
, int ret
)
2032 NvmeRequest
*req
= opaque
;
2033 uintptr_t *discards
= (uintptr_t *)&req
->opaque
;
2035 trace_pci_nvme_aio_discard_cb(nvme_cid(req
));
2038 nvme_aio_err(req
, ret
);
2047 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2050 struct nvme_zone_reset_ctx
{
2055 static void nvme_aio_zone_reset_complete_cb(void *opaque
, int ret
)
2057 struct nvme_zone_reset_ctx
*ctx
= opaque
;
2058 NvmeRequest
*req
= ctx
->req
;
2059 NvmeNamespace
*ns
= req
->ns
;
2060 NvmeZone
*zone
= ctx
->zone
;
2061 uintptr_t *resets
= (uintptr_t *)&req
->opaque
;
2064 nvme_aio_err(req
, ret
);
2068 switch (nvme_get_zone_state(zone
)) {
2069 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
2070 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
2071 nvme_aor_dec_open(ns
);
2073 case NVME_ZONE_STATE_CLOSED
:
2074 nvme_aor_dec_active(ns
);
2076 case NVME_ZONE_STATE_FULL
:
2077 zone
->w_ptr
= zone
->d
.zslba
;
2078 zone
->d
.wp
= zone
->w_ptr
;
2079 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_EMPTY
);
2094 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2097 static void nvme_aio_zone_reset_cb(void *opaque
, int ret
)
2099 struct nvme_zone_reset_ctx
*ctx
= opaque
;
2100 NvmeRequest
*req
= ctx
->req
;
2101 NvmeNamespace
*ns
= req
->ns
;
2102 NvmeZone
*zone
= ctx
->zone
;
2104 trace_pci_nvme_aio_zone_reset_cb(nvme_cid(req
), zone
->d
.zslba
);
2110 if (nvme_msize(ns
)) {
2111 int64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, zone
->d
.zslba
);
2113 blk_aio_pwrite_zeroes(ns
->blkconf
.blk
, offset
,
2114 nvme_m2b(ns
, ns
->zone_size
), BDRV_REQ_MAY_UNMAP
,
2115 nvme_aio_zone_reset_complete_cb
, ctx
);
2120 nvme_aio_zone_reset_complete_cb(opaque
, ret
);
2123 struct nvme_copy_ctx
{
2128 NvmeCopySourceRange
*ranges
;
2131 struct nvme_copy_in_ctx
{
2134 NvmeCopySourceRange
*range
;
2137 static void nvme_copy_complete_cb(void *opaque
, int ret
)
2139 NvmeRequest
*req
= opaque
;
2140 NvmeNamespace
*ns
= req
->ns
;
2141 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2144 block_acct_failed(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2145 nvme_aio_err(req
, ret
);
2149 block_acct_done(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2152 if (ns
->params
.zoned
) {
2153 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2154 uint64_t sdlba
= le64_to_cpu(copy
->sdlba
);
2155 NvmeZone
*zone
= nvme_get_zone_by_slba(ns
, sdlba
);
2157 __nvme_advance_zone_wp(ns
, zone
, ctx
->nlb
);
2160 g_free(ctx
->bounce
);
2161 g_free(ctx
->mbounce
);
2164 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2167 static void nvme_copy_cb(void *opaque
, int ret
)
2169 NvmeRequest
*req
= opaque
;
2170 NvmeNamespace
*ns
= req
->ns
;
2171 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2173 trace_pci_nvme_copy_cb(nvme_cid(req
));
2179 if (nvme_msize(ns
)) {
2180 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2181 uint64_t sdlba
= le64_to_cpu(copy
->sdlba
);
2182 int64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, sdlba
);
2184 qemu_iovec_reset(&req
->sg
.iov
);
2185 qemu_iovec_add(&req
->sg
.iov
, ctx
->mbounce
, nvme_m2b(ns
, ctx
->nlb
));
2187 req
->aiocb
= blk_aio_pwritev(ns
->blkconf
.blk
, offset
, &req
->sg
.iov
, 0,
2188 nvme_copy_complete_cb
, req
);
2193 nvme_copy_complete_cb(opaque
, ret
);
2196 static void nvme_copy_in_complete(NvmeRequest
*req
)
2198 NvmeNamespace
*ns
= req
->ns
;
2199 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2200 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2201 uint64_t sdlba
= le64_to_cpu(copy
->sdlba
);
2204 trace_pci_nvme_copy_in_complete(nvme_cid(req
));
2206 block_acct_done(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2208 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2209 uint16_t prinfor
= (copy
->control
[0] >> 4) & 0xf;
2210 uint16_t prinfow
= (copy
->control
[2] >> 2) & 0xf;
2211 uint16_t nr
= copy
->nr
+ 1;
2212 NvmeCopySourceRange
*range
;
2215 uint16_t apptag
, appmask
;
2217 uint8_t *buf
= ctx
->bounce
, *mbuf
= ctx
->mbounce
;
2222 * The dif helpers expects prinfo to be similar to the control field of
2223 * the NvmeRwCmd, so shift by 10 to fake it.
2225 prinfor
= prinfor
<< 10;
2226 prinfow
= prinfow
<< 10;
2228 for (i
= 0; i
< nr
; i
++) {
2229 range
= &ctx
->ranges
[i
];
2230 slba
= le64_to_cpu(range
->slba
);
2231 nlb
= le16_to_cpu(range
->nlb
) + 1;
2232 len
= nvme_l2b(ns
, nlb
);
2233 mlen
= nvme_m2b(ns
, nlb
);
2234 apptag
= le16_to_cpu(range
->apptag
);
2235 appmask
= le16_to_cpu(range
->appmask
);
2236 reftag
= le32_to_cpu(range
->reftag
);
2238 status
= nvme_dif_check(ns
, buf
, len
, mbuf
, mlen
, prinfor
, slba
,
2239 apptag
, appmask
, reftag
);
2248 apptag
= le16_to_cpu(copy
->apptag
);
2249 appmask
= le16_to_cpu(copy
->appmask
);
2250 reftag
= le32_to_cpu(copy
->reftag
);
2252 if (prinfow
& NVME_RW_PRINFO_PRACT
) {
2253 size_t len
= nvme_l2b(ns
, ctx
->nlb
);
2254 size_t mlen
= nvme_m2b(ns
, ctx
->nlb
);
2256 status
= nvme_check_prinfo(ns
, prinfow
, sdlba
, reftag
);
2261 nvme_dif_pract_generate_dif(ns
, ctx
->bounce
, len
, ctx
->mbounce
,
2262 mlen
, apptag
, reftag
);
2264 status
= nvme_dif_check(ns
, ctx
->bounce
, len
, ctx
->mbounce
, mlen
,
2265 prinfow
, sdlba
, apptag
, appmask
, reftag
);
2272 status
= nvme_check_bounds(ns
, sdlba
, ctx
->nlb
);
2277 if (ns
->params
.zoned
) {
2278 NvmeZone
*zone
= nvme_get_zone_by_slba(ns
, sdlba
);
2280 status
= nvme_check_zone_write(ns
, zone
, sdlba
, ctx
->nlb
);
2285 status
= nvme_zrm_auto(ns
, zone
);
2290 zone
->w_ptr
+= ctx
->nlb
;
2293 qemu_iovec_init(&req
->sg
.iov
, 1);
2294 qemu_iovec_add(&req
->sg
.iov
, ctx
->bounce
, nvme_l2b(ns
, ctx
->nlb
));
2296 block_acct_start(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
, 0,
2299 req
->aiocb
= blk_aio_pwritev(ns
->blkconf
.blk
, nvme_l2b(ns
, sdlba
),
2300 &req
->sg
.iov
, 0, nvme_copy_cb
, req
);
2305 req
->status
= status
;
2307 g_free(ctx
->bounce
);
2310 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2313 static void nvme_aio_copy_in_cb(void *opaque
, int ret
)
2315 struct nvme_copy_in_ctx
*in_ctx
= opaque
;
2316 NvmeRequest
*req
= in_ctx
->req
;
2317 NvmeNamespace
*ns
= req
->ns
;
2318 struct nvme_copy_ctx
*ctx
= req
->opaque
;
2320 qemu_iovec_destroy(&in_ctx
->iov
);
2323 trace_pci_nvme_aio_copy_in_cb(nvme_cid(req
));
2326 nvme_aio_err(req
, ret
);
2336 block_acct_failed(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
);
2338 g_free(ctx
->bounce
);
2339 g_free(ctx
->mbounce
);
2342 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2347 nvme_copy_in_complete(req
);
2350 struct nvme_compare_ctx
{
2362 static void nvme_compare_mdata_cb(void *opaque
, int ret
)
2364 NvmeRequest
*req
= opaque
;
2365 NvmeNamespace
*ns
= req
->ns
;
2366 NvmeCtrl
*n
= nvme_ctrl(req
);
2367 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2368 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2369 uint16_t apptag
= le16_to_cpu(rw
->apptag
);
2370 uint16_t appmask
= le16_to_cpu(rw
->appmask
);
2371 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
2372 struct nvme_compare_ctx
*ctx
= req
->opaque
;
2373 g_autofree
uint8_t *buf
= NULL
;
2374 BlockBackend
*blk
= ns
->blkconf
.blk
;
2375 BlockAcctCookie
*acct
= &req
->acct
;
2376 BlockAcctStats
*stats
= blk_get_stats(blk
);
2377 uint16_t status
= NVME_SUCCESS
;
2379 trace_pci_nvme_compare_mdata_cb(nvme_cid(req
));
2382 block_acct_failed(stats
, acct
);
2383 nvme_aio_err(req
, ret
);
2387 buf
= g_malloc(ctx
->mdata
.iov
.size
);
2389 status
= nvme_bounce_mdata(n
, buf
, ctx
->mdata
.iov
.size
,
2390 NVME_TX_DIRECTION_TO_DEVICE
, req
);
2392 req
->status
= status
;
2396 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2397 uint64_t slba
= le64_to_cpu(rw
->slba
);
2399 uint8_t *mbufp
= ctx
->mdata
.bounce
;
2400 uint8_t *end
= mbufp
+ ctx
->mdata
.iov
.size
;
2401 size_t msize
= nvme_msize(ns
);
2404 status
= nvme_dif_check(ns
, ctx
->data
.bounce
, ctx
->data
.iov
.size
,
2405 ctx
->mdata
.bounce
, ctx
->mdata
.iov
.size
, ctrl
,
2406 slba
, apptag
, appmask
, reftag
);
2408 req
->status
= status
;
2413 * When formatted with protection information, do not compare the DIF
2416 if (!(ns
->id_ns
.dps
& NVME_ID_NS_DPS_FIRST_EIGHT
)) {
2417 pil
= nvme_msize(ns
) - sizeof(NvmeDifTuple
);
2420 for (bufp
= buf
; mbufp
< end
; bufp
+= msize
, mbufp
+= msize
) {
2421 if (memcmp(bufp
+ pil
, mbufp
+ pil
, msize
- pil
)) {
2422 req
->status
= NVME_CMP_FAILURE
;
2430 if (memcmp(buf
, ctx
->mdata
.bounce
, ctx
->mdata
.iov
.size
)) {
2431 req
->status
= NVME_CMP_FAILURE
;
2435 block_acct_done(stats
, acct
);
2438 qemu_iovec_destroy(&ctx
->data
.iov
);
2439 g_free(ctx
->data
.bounce
);
2441 qemu_iovec_destroy(&ctx
->mdata
.iov
);
2442 g_free(ctx
->mdata
.bounce
);
2446 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2449 static void nvme_compare_data_cb(void *opaque
, int ret
)
2451 NvmeRequest
*req
= opaque
;
2452 NvmeCtrl
*n
= nvme_ctrl(req
);
2453 NvmeNamespace
*ns
= req
->ns
;
2454 BlockBackend
*blk
= ns
->blkconf
.blk
;
2455 BlockAcctCookie
*acct
= &req
->acct
;
2456 BlockAcctStats
*stats
= blk_get_stats(blk
);
2458 struct nvme_compare_ctx
*ctx
= req
->opaque
;
2459 g_autofree
uint8_t *buf
= NULL
;
2462 trace_pci_nvme_compare_data_cb(nvme_cid(req
));
2465 block_acct_failed(stats
, acct
);
2466 nvme_aio_err(req
, ret
);
2470 buf
= g_malloc(ctx
->data
.iov
.size
);
2472 status
= nvme_bounce_data(n
, buf
, ctx
->data
.iov
.size
,
2473 NVME_TX_DIRECTION_TO_DEVICE
, req
);
2475 req
->status
= status
;
2479 if (memcmp(buf
, ctx
->data
.bounce
, ctx
->data
.iov
.size
)) {
2480 req
->status
= NVME_CMP_FAILURE
;
2484 if (nvme_msize(ns
)) {
2485 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2486 uint64_t slba
= le64_to_cpu(rw
->slba
);
2487 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2488 size_t mlen
= nvme_m2b(ns
, nlb
);
2489 uint64_t offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
2491 ctx
->mdata
.bounce
= g_malloc(mlen
);
2493 qemu_iovec_init(&ctx
->mdata
.iov
, 1);
2494 qemu_iovec_add(&ctx
->mdata
.iov
, ctx
->mdata
.bounce
, mlen
);
2496 req
->aiocb
= blk_aio_preadv(blk
, offset
, &ctx
->mdata
.iov
, 0,
2497 nvme_compare_mdata_cb
, req
);
2501 block_acct_done(stats
, acct
);
2504 qemu_iovec_destroy(&ctx
->data
.iov
);
2505 g_free(ctx
->data
.bounce
);
2508 nvme_enqueue_req_completion(nvme_cq(req
), req
);
2511 static uint16_t nvme_dsm(NvmeCtrl
*n
, NvmeRequest
*req
)
2513 NvmeNamespace
*ns
= req
->ns
;
2514 NvmeDsmCmd
*dsm
= (NvmeDsmCmd
*) &req
->cmd
;
2516 uint32_t attr
= le32_to_cpu(dsm
->attributes
);
2517 uint32_t nr
= (le32_to_cpu(dsm
->nr
) & 0xff) + 1;
2519 uint16_t status
= NVME_SUCCESS
;
2521 trace_pci_nvme_dsm(nvme_cid(req
), nvme_nsid(ns
), nr
, attr
);
2523 if (attr
& NVME_DSMGMT_AD
) {
2526 NvmeDsmRange range
[nr
];
2527 uintptr_t *discards
= (uintptr_t *)&req
->opaque
;
2529 status
= nvme_h2c(n
, (uint8_t *)range
, sizeof(range
), req
);
2535 * AIO callbacks may be called immediately, so initialize discards to 1
2536 * to make sure the the callback does not complete the request before
2537 * all discards have been issued.
2541 for (int i
= 0; i
< nr
; i
++) {
2542 uint64_t slba
= le64_to_cpu(range
[i
].slba
);
2543 uint32_t nlb
= le32_to_cpu(range
[i
].nlb
);
2545 if (nvme_check_bounds(ns
, slba
, nlb
)) {
2549 trace_pci_nvme_dsm_deallocate(nvme_cid(req
), nvme_nsid(ns
), slba
,
2552 if (nlb
> n
->dmrsl
) {
2553 trace_pci_nvme_dsm_single_range_limit_exceeded(nlb
, n
->dmrsl
);
2556 offset
= nvme_l2b(ns
, slba
);
2557 len
= nvme_l2b(ns
, nlb
);
2560 size_t bytes
= MIN(BDRV_REQUEST_MAX_BYTES
, len
);
2564 blk_aio_pdiscard(ns
->blkconf
.blk
, offset
, bytes
,
2565 nvme_aio_discard_cb
, req
);
2572 /* account for the 1-initialization */
2576 status
= NVME_NO_COMPLETE
;
2578 status
= req
->status
;
2585 static uint16_t nvme_verify(NvmeCtrl
*n
, NvmeRequest
*req
)
2587 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2588 NvmeNamespace
*ns
= req
->ns
;
2589 BlockBackend
*blk
= ns
->blkconf
.blk
;
2590 uint64_t slba
= le64_to_cpu(rw
->slba
);
2591 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2592 size_t len
= nvme_l2b(ns
, nlb
);
2593 int64_t offset
= nvme_l2b(ns
, slba
);
2594 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2595 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
2596 NvmeBounceContext
*ctx
= NULL
;
2599 trace_pci_nvme_verify(nvme_cid(req
), nvme_nsid(ns
), slba
, nlb
);
2601 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2602 status
= nvme_check_prinfo(ns
, ctrl
, slba
, reftag
);
2607 if (ctrl
& NVME_RW_PRINFO_PRACT
) {
2608 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
2612 if (len
> n
->page_size
<< n
->params
.vsl
) {
2613 return NVME_INVALID_FIELD
| NVME_DNR
;
2616 status
= nvme_check_bounds(ns
, slba
, nlb
);
2621 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2622 status
= nvme_check_dulbe(ns
, slba
, nlb
);
2628 ctx
= g_new0(NvmeBounceContext
, 1);
2631 ctx
->data
.bounce
= g_malloc(len
);
2633 qemu_iovec_init(&ctx
->data
.iov
, 1);
2634 qemu_iovec_add(&ctx
->data
.iov
, ctx
->data
.bounce
, len
);
2636 block_acct_start(blk_get_stats(blk
), &req
->acct
, ctx
->data
.iov
.size
,
2639 req
->aiocb
= blk_aio_preadv(ns
->blkconf
.blk
, offset
, &ctx
->data
.iov
, 0,
2640 nvme_verify_mdata_in_cb
, ctx
);
2641 return NVME_NO_COMPLETE
;
2644 static uint16_t nvme_copy(NvmeCtrl
*n
, NvmeRequest
*req
)
2646 NvmeNamespace
*ns
= req
->ns
;
2647 NvmeCopyCmd
*copy
= (NvmeCopyCmd
*)&req
->cmd
;
2649 uint16_t nr
= copy
->nr
+ 1;
2650 uint8_t format
= copy
->control
[0] & 0xf;
2653 * Shift the PRINFOR/PRINFOW values by 10 to allow reusing the
2654 * NVME_RW_PRINFO constants.
2656 uint16_t prinfor
= ((copy
->control
[0] >> 4) & 0xf) << 10;
2657 uint16_t prinfow
= ((copy
->control
[2] >> 2) & 0xf) << 10;
2660 uint8_t *bounce
= NULL
, *bouncep
= NULL
;
2661 uint8_t *mbounce
= NULL
, *mbouncep
= NULL
;
2662 struct nvme_copy_ctx
*ctx
;
2666 trace_pci_nvme_copy(nvme_cid(req
), nvme_nsid(ns
), nr
, format
);
2668 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
) &&
2669 ((prinfor
& NVME_RW_PRINFO_PRACT
) != (prinfow
& NVME_RW_PRINFO_PRACT
))) {
2670 return NVME_INVALID_FIELD
| NVME_DNR
;
2673 if (!(n
->id_ctrl
.ocfs
& (1 << format
))) {
2674 trace_pci_nvme_err_copy_invalid_format(format
);
2675 return NVME_INVALID_FIELD
| NVME_DNR
;
2678 if (nr
> ns
->id_ns
.msrc
+ 1) {
2679 return NVME_CMD_SIZE_LIMIT
| NVME_DNR
;
2682 ctx
= g_new(struct nvme_copy_ctx
, 1);
2683 ctx
->ranges
= g_new(NvmeCopySourceRange
, nr
);
2685 status
= nvme_h2c(n
, (uint8_t *)ctx
->ranges
,
2686 nr
* sizeof(NvmeCopySourceRange
), req
);
2691 for (i
= 0; i
< nr
; i
++) {
2692 uint64_t slba
= le64_to_cpu(ctx
->ranges
[i
].slba
);
2693 uint32_t _nlb
= le16_to_cpu(ctx
->ranges
[i
].nlb
) + 1;
2695 if (_nlb
> le16_to_cpu(ns
->id_ns
.mssrl
)) {
2696 status
= NVME_CMD_SIZE_LIMIT
| NVME_DNR
;
2700 status
= nvme_check_bounds(ns
, slba
, _nlb
);
2705 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2706 status
= nvme_check_dulbe(ns
, slba
, _nlb
);
2712 if (ns
->params
.zoned
) {
2713 status
= nvme_check_zone_read(ns
, slba
, _nlb
);
2722 if (nlb
> le32_to_cpu(ns
->id_ns
.mcl
)) {
2723 status
= NVME_CMD_SIZE_LIMIT
| NVME_DNR
;
2727 bounce
= bouncep
= g_malloc(nvme_l2b(ns
, nlb
));
2728 if (nvme_msize(ns
)) {
2729 mbounce
= mbouncep
= g_malloc(nvme_m2b(ns
, nlb
));
2732 block_acct_start(blk_get_stats(ns
->blkconf
.blk
), &req
->acct
, 0,
2735 ctx
->bounce
= bounce
;
2736 ctx
->mbounce
= mbounce
;
2742 for (i
= 0; i
< nr
; i
++) {
2743 uint64_t slba
= le64_to_cpu(ctx
->ranges
[i
].slba
);
2744 uint32_t nlb
= le16_to_cpu(ctx
->ranges
[i
].nlb
) + 1;
2746 size_t len
= nvme_l2b(ns
, nlb
);
2747 int64_t offset
= nvme_l2b(ns
, slba
);
2749 trace_pci_nvme_copy_source_range(slba
, nlb
);
2751 struct nvme_copy_in_ctx
*in_ctx
= g_new(struct nvme_copy_in_ctx
, 1);
2754 qemu_iovec_init(&in_ctx
->iov
, 1);
2755 qemu_iovec_add(&in_ctx
->iov
, bouncep
, len
);
2759 blk_aio_preadv(ns
->blkconf
.blk
, offset
, &in_ctx
->iov
, 0,
2760 nvme_aio_copy_in_cb
, in_ctx
);
2764 if (nvme_msize(ns
)) {
2765 len
= nvme_m2b(ns
, nlb
);
2766 offset
= ns
->mdata_offset
+ nvme_m2b(ns
, slba
);
2768 in_ctx
= g_new(struct nvme_copy_in_ctx
, 1);
2771 qemu_iovec_init(&in_ctx
->iov
, 1);
2772 qemu_iovec_add(&in_ctx
->iov
, mbouncep
, len
);
2776 blk_aio_preadv(ns
->blkconf
.blk
, offset
, &in_ctx
->iov
, 0,
2777 nvme_aio_copy_in_cb
, in_ctx
);
2783 /* account for the 1-initialization */
2787 nvme_copy_in_complete(req
);
2790 return NVME_NO_COMPLETE
;
2793 g_free(ctx
->ranges
);
2799 static uint16_t nvme_compare(NvmeCtrl
*n
, NvmeRequest
*req
)
2801 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2802 NvmeNamespace
*ns
= req
->ns
;
2803 BlockBackend
*blk
= ns
->blkconf
.blk
;
2804 uint64_t slba
= le64_to_cpu(rw
->slba
);
2805 uint32_t nlb
= le16_to_cpu(rw
->nlb
) + 1;
2806 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2807 size_t data_len
= nvme_l2b(ns
, nlb
);
2808 size_t len
= data_len
;
2809 int64_t offset
= nvme_l2b(ns
, slba
);
2810 struct nvme_compare_ctx
*ctx
= NULL
;
2813 trace_pci_nvme_compare(nvme_cid(req
), nvme_nsid(ns
), slba
, nlb
);
2815 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
) && (ctrl
& NVME_RW_PRINFO_PRACT
)) {
2816 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
2819 if (nvme_ns_ext(ns
)) {
2820 len
+= nvme_m2b(ns
, nlb
);
2823 status
= nvme_check_mdts(n
, len
);
2828 status
= nvme_check_bounds(ns
, slba
, nlb
);
2833 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2834 status
= nvme_check_dulbe(ns
, slba
, nlb
);
2840 status
= nvme_map_dptr(n
, &req
->sg
, len
, &req
->cmd
);
2845 ctx
= g_new(struct nvme_compare_ctx
, 1);
2846 ctx
->data
.bounce
= g_malloc(data_len
);
2850 qemu_iovec_init(&ctx
->data
.iov
, 1);
2851 qemu_iovec_add(&ctx
->data
.iov
, ctx
->data
.bounce
, data_len
);
2853 block_acct_start(blk_get_stats(blk
), &req
->acct
, data_len
,
2855 req
->aiocb
= blk_aio_preadv(blk
, offset
, &ctx
->data
.iov
, 0,
2856 nvme_compare_data_cb
, req
);
2858 return NVME_NO_COMPLETE
;
2861 static uint16_t nvme_flush(NvmeCtrl
*n
, NvmeRequest
*req
)
2863 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
2864 uintptr_t *num_flushes
= (uintptr_t *)&req
->opaque
;
2866 struct nvme_aio_flush_ctx
*ctx
;
2869 trace_pci_nvme_flush(nvme_cid(req
), nsid
);
2871 if (nsid
!= NVME_NSID_BROADCAST
) {
2872 req
->ns
= nvme_ns(n
, nsid
);
2873 if (unlikely(!req
->ns
)) {
2874 return NVME_INVALID_FIELD
| NVME_DNR
;
2877 block_acct_start(blk_get_stats(req
->ns
->blkconf
.blk
), &req
->acct
, 0,
2879 req
->aiocb
= blk_aio_flush(req
->ns
->blkconf
.blk
, nvme_misc_cb
, req
);
2880 return NVME_NO_COMPLETE
;
2883 /* 1-initialize; see comment in nvme_dsm */
2886 for (int i
= 1; i
<= n
->num_namespaces
; i
++) {
2892 ctx
= g_new(struct nvme_aio_flush_ctx
, 1);
2898 block_acct_start(blk_get_stats(ns
->blkconf
.blk
), &ctx
->acct
, 0,
2900 blk_aio_flush(ns
->blkconf
.blk
, nvme_aio_flush_cb
, ctx
);
2903 /* account for the 1-initialization */
2907 status
= NVME_NO_COMPLETE
;
2909 status
= req
->status
;
2915 static uint16_t nvme_read(NvmeCtrl
*n
, NvmeRequest
*req
)
2917 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2918 NvmeNamespace
*ns
= req
->ns
;
2919 uint64_t slba
= le64_to_cpu(rw
->slba
);
2920 uint32_t nlb
= (uint32_t)le16_to_cpu(rw
->nlb
) + 1;
2921 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2922 uint64_t data_size
= nvme_l2b(ns
, nlb
);
2923 uint64_t mapped_size
= data_size
;
2924 uint64_t data_offset
;
2925 BlockBackend
*blk
= ns
->blkconf
.blk
;
2928 if (nvme_ns_ext(ns
)) {
2929 mapped_size
+= nvme_m2b(ns
, nlb
);
2931 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2932 bool pract
= ctrl
& NVME_RW_PRINFO_PRACT
;
2934 if (pract
&& nvme_msize(ns
) == 8) {
2935 mapped_size
= data_size
;
2940 trace_pci_nvme_read(nvme_cid(req
), nvme_nsid(ns
), nlb
, mapped_size
, slba
);
2942 status
= nvme_check_mdts(n
, mapped_size
);
2947 status
= nvme_check_bounds(ns
, slba
, nlb
);
2952 if (ns
->params
.zoned
) {
2953 status
= nvme_check_zone_read(ns
, slba
, nlb
);
2955 trace_pci_nvme_err_zone_read_not_ok(slba
, nlb
, status
);
2960 if (NVME_ERR_REC_DULBE(ns
->features
.err_rec
)) {
2961 status
= nvme_check_dulbe(ns
, slba
, nlb
);
2967 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
2968 return nvme_dif_rw(n
, req
);
2971 status
= nvme_map_data(n
, nlb
, req
);
2976 data_offset
= nvme_l2b(ns
, slba
);
2978 block_acct_start(blk_get_stats(blk
), &req
->acct
, data_size
,
2980 nvme_blk_read(blk
, data_offset
, nvme_rw_cb
, req
);
2981 return NVME_NO_COMPLETE
;
2984 block_acct_invalid(blk_get_stats(blk
), BLOCK_ACCT_READ
);
2985 return status
| NVME_DNR
;
2988 static uint16_t nvme_do_write(NvmeCtrl
*n
, NvmeRequest
*req
, bool append
,
2991 NvmeRwCmd
*rw
= (NvmeRwCmd
*)&req
->cmd
;
2992 NvmeNamespace
*ns
= req
->ns
;
2993 uint64_t slba
= le64_to_cpu(rw
->slba
);
2994 uint32_t nlb
= (uint32_t)le16_to_cpu(rw
->nlb
) + 1;
2995 uint16_t ctrl
= le16_to_cpu(rw
->control
);
2996 uint64_t data_size
= nvme_l2b(ns
, nlb
);
2997 uint64_t mapped_size
= data_size
;
2998 uint64_t data_offset
;
3000 NvmeZonedResult
*res
= (NvmeZonedResult
*)&req
->cqe
;
3001 BlockBackend
*blk
= ns
->blkconf
.blk
;
3004 if (nvme_ns_ext(ns
)) {
3005 mapped_size
+= nvme_m2b(ns
, nlb
);
3007 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
3008 bool pract
= ctrl
& NVME_RW_PRINFO_PRACT
;
3010 if (pract
&& nvme_msize(ns
) == 8) {
3011 mapped_size
-= nvme_m2b(ns
, nlb
);
3016 trace_pci_nvme_write(nvme_cid(req
), nvme_io_opc_str(rw
->opcode
),
3017 nvme_nsid(ns
), nlb
, mapped_size
, slba
);
3020 status
= nvme_check_mdts(n
, mapped_size
);
3026 status
= nvme_check_bounds(ns
, slba
, nlb
);
3031 if (ns
->params
.zoned
) {
3032 zone
= nvme_get_zone_by_slba(ns
, slba
);
3035 bool piremap
= !!(ctrl
& NVME_RW_PIREMAP
);
3037 if (unlikely(slba
!= zone
->d
.zslba
)) {
3038 trace_pci_nvme_err_append_not_at_start(slba
, zone
->d
.zslba
);
3039 status
= NVME_INVALID_FIELD
;
3043 if (n
->params
.zasl
&&
3044 data_size
> (uint64_t)n
->page_size
<< n
->params
.zasl
) {
3045 trace_pci_nvme_err_zasl(data_size
);
3046 return NVME_INVALID_FIELD
| NVME_DNR
;
3050 rw
->slba
= cpu_to_le64(slba
);
3051 res
->slba
= cpu_to_le64(slba
);
3053 switch (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
3054 case NVME_ID_NS_DPS_TYPE_1
:
3056 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
3061 case NVME_ID_NS_DPS_TYPE_2
:
3063 uint32_t reftag
= le32_to_cpu(rw
->reftag
);
3064 rw
->reftag
= cpu_to_le32(reftag
+ (slba
- zone
->d
.zslba
));
3069 case NVME_ID_NS_DPS_TYPE_3
:
3071 return NVME_INVALID_PROT_INFO
| NVME_DNR
;
3078 status
= nvme_check_zone_write(ns
, zone
, slba
, nlb
);
3083 status
= nvme_zrm_auto(ns
, zone
);
3091 data_offset
= nvme_l2b(ns
, slba
);
3093 if (NVME_ID_NS_DPS_TYPE(ns
->id_ns
.dps
)) {
3094 return nvme_dif_rw(n
, req
);
3098 status
= nvme_map_data(n
, nlb
, req
);
3103 block_acct_start(blk_get_stats(blk
), &req
->acct
, data_size
,
3105 nvme_blk_write(blk
, data_offset
, nvme_rw_cb
, req
);
3107 req
->aiocb
= blk_aio_pwrite_zeroes(blk
, data_offset
, data_size
,
3108 BDRV_REQ_MAY_UNMAP
, nvme_rw_cb
,
3112 return NVME_NO_COMPLETE
;
3115 block_acct_invalid(blk_get_stats(blk
), BLOCK_ACCT_WRITE
);
3116 return status
| NVME_DNR
;
3119 static inline uint16_t nvme_write(NvmeCtrl
*n
, NvmeRequest
*req
)
3121 return nvme_do_write(n
, req
, false, false);
3124 static inline uint16_t nvme_write_zeroes(NvmeCtrl
*n
, NvmeRequest
*req
)
3126 return nvme_do_write(n
, req
, false, true);
3129 static inline uint16_t nvme_zone_append(NvmeCtrl
*n
, NvmeRequest
*req
)
3131 return nvme_do_write(n
, req
, true, false);
3134 static uint16_t nvme_get_mgmt_zone_slba_idx(NvmeNamespace
*ns
, NvmeCmd
*c
,
3135 uint64_t *slba
, uint32_t *zone_idx
)
3137 uint32_t dw10
= le32_to_cpu(c
->cdw10
);
3138 uint32_t dw11
= le32_to_cpu(c
->cdw11
);
3140 if (!ns
->params
.zoned
) {
3141 trace_pci_nvme_err_invalid_opc(c
->opcode
);
3142 return NVME_INVALID_OPCODE
| NVME_DNR
;
3145 *slba
= ((uint64_t)dw11
) << 32 | dw10
;
3146 if (unlikely(*slba
>= ns
->id_ns
.nsze
)) {
3147 trace_pci_nvme_err_invalid_lba_range(*slba
, 0, ns
->id_ns
.nsze
);
3149 return NVME_LBA_RANGE
| NVME_DNR
;
3152 *zone_idx
= nvme_zone_idx(ns
, *slba
);
3153 assert(*zone_idx
< ns
->num_zones
);
3155 return NVME_SUCCESS
;
3158 typedef uint16_t (*op_handler_t
)(NvmeNamespace
*, NvmeZone
*, NvmeZoneState
,
3161 enum NvmeZoneProcessingMask
{
3162 NVME_PROC_CURRENT_ZONE
= 0,
3163 NVME_PROC_OPENED_ZONES
= 1 << 0,
3164 NVME_PROC_CLOSED_ZONES
= 1 << 1,
3165 NVME_PROC_READ_ONLY_ZONES
= 1 << 2,
3166 NVME_PROC_FULL_ZONES
= 1 << 3,
3169 static uint16_t nvme_open_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3170 NvmeZoneState state
, NvmeRequest
*req
)
3172 return nvme_zrm_open(ns
, zone
);
3175 static uint16_t nvme_close_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3176 NvmeZoneState state
, NvmeRequest
*req
)
3178 return nvme_zrm_close(ns
, zone
);
3181 static uint16_t nvme_finish_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3182 NvmeZoneState state
, NvmeRequest
*req
)
3184 return nvme_zrm_finish(ns
, zone
);
3187 static uint16_t nvme_reset_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3188 NvmeZoneState state
, NvmeRequest
*req
)
3190 uintptr_t *resets
= (uintptr_t *)&req
->opaque
;
3191 struct nvme_zone_reset_ctx
*ctx
;
3194 case NVME_ZONE_STATE_EMPTY
:
3195 return NVME_SUCCESS
;
3196 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
3197 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
3198 case NVME_ZONE_STATE_CLOSED
:
3199 case NVME_ZONE_STATE_FULL
:
3202 return NVME_ZONE_INVAL_TRANSITION
;
3206 * The zone reset aio callback needs to know the zone that is being reset
3207 * in order to transition the zone on completion.
3209 ctx
= g_new(struct nvme_zone_reset_ctx
, 1);
3215 blk_aio_pwrite_zeroes(ns
->blkconf
.blk
, nvme_l2b(ns
, zone
->d
.zslba
),
3216 nvme_l2b(ns
, ns
->zone_size
), BDRV_REQ_MAY_UNMAP
,
3217 nvme_aio_zone_reset_cb
, ctx
);
3219 return NVME_NO_COMPLETE
;
3222 static uint16_t nvme_offline_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3223 NvmeZoneState state
, NvmeRequest
*req
)
3226 case NVME_ZONE_STATE_READ_ONLY
:
3227 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_OFFLINE
);
3229 case NVME_ZONE_STATE_OFFLINE
:
3230 return NVME_SUCCESS
;
3232 return NVME_ZONE_INVAL_TRANSITION
;
3236 static uint16_t nvme_set_zd_ext(NvmeNamespace
*ns
, NvmeZone
*zone
)
3239 uint8_t state
= nvme_get_zone_state(zone
);
3241 if (state
== NVME_ZONE_STATE_EMPTY
) {
3242 status
= nvme_aor_check(ns
, 1, 0);
3246 nvme_aor_inc_active(ns
);
3247 zone
->d
.za
|= NVME_ZA_ZD_EXT_VALID
;
3248 nvme_assign_zone_state(ns
, zone
, NVME_ZONE_STATE_CLOSED
);
3249 return NVME_SUCCESS
;
3252 return NVME_ZONE_INVAL_TRANSITION
;
3255 static uint16_t nvme_bulk_proc_zone(NvmeNamespace
*ns
, NvmeZone
*zone
,
3256 enum NvmeZoneProcessingMask proc_mask
,
3257 op_handler_t op_hndlr
, NvmeRequest
*req
)
3259 uint16_t status
= NVME_SUCCESS
;
3260 NvmeZoneState zs
= nvme_get_zone_state(zone
);
3264 case NVME_ZONE_STATE_IMPLICITLY_OPEN
:
3265 case NVME_ZONE_STATE_EXPLICITLY_OPEN
:
3266 proc_zone
= proc_mask
& NVME_PROC_OPENED_ZONES
;
3268 case NVME_ZONE_STATE_CLOSED
:
3269 proc_zone
= proc_mask
& NVME_PROC_CLOSED_ZONES
;
3271 case NVME_ZONE_STATE_READ_ONLY
:
3272 proc_zone
= proc_mask
& NVME_PROC_READ_ONLY_ZONES
;
3274 case NVME_ZONE_STATE_FULL
:
3275 proc_zone
= proc_mask
& NVME_PROC_FULL_ZONES
;
3282 status
= op_hndlr(ns
, zone
, zs
, req
);
3288 static uint16_t nvme_do_zone_op(NvmeNamespace
*ns
, NvmeZone
*zone
,
3289 enum NvmeZoneProcessingMask proc_mask
,
3290 op_handler_t op_hndlr
, NvmeRequest
*req
)
3293 uint16_t status
= NVME_SUCCESS
;
3297 status
= op_hndlr(ns
, zone
, nvme_get_zone_state(zone
), req
);
3299 if (proc_mask
& NVME_PROC_CLOSED_ZONES
) {
3300 QTAILQ_FOREACH_SAFE(zone
, &ns
->closed_zones
, entry
, next
) {
3301 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3303 if (status
&& status
!= NVME_NO_COMPLETE
) {
3308 if (proc_mask
& NVME_PROC_OPENED_ZONES
) {
3309 QTAILQ_FOREACH_SAFE(zone
, &ns
->imp_open_zones
, entry
, next
) {
3310 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3312 if (status
&& status
!= NVME_NO_COMPLETE
) {
3317 QTAILQ_FOREACH_SAFE(zone
, &ns
->exp_open_zones
, entry
, next
) {
3318 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3320 if (status
&& status
!= NVME_NO_COMPLETE
) {
3325 if (proc_mask
& NVME_PROC_FULL_ZONES
) {
3326 QTAILQ_FOREACH_SAFE(zone
, &ns
->full_zones
, entry
, next
) {
3327 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3329 if (status
&& status
!= NVME_NO_COMPLETE
) {
3335 if (proc_mask
& NVME_PROC_READ_ONLY_ZONES
) {
3336 for (i
= 0; i
< ns
->num_zones
; i
++, zone
++) {
3337 status
= nvme_bulk_proc_zone(ns
, zone
, proc_mask
, op_hndlr
,
3339 if (status
&& status
!= NVME_NO_COMPLETE
) {
3350 static uint16_t nvme_zone_mgmt_send(NvmeCtrl
*n
, NvmeRequest
*req
)
3352 NvmeCmd
*cmd
= (NvmeCmd
*)&req
->cmd
;
3353 NvmeNamespace
*ns
= req
->ns
;
3357 uint32_t dw13
= le32_to_cpu(cmd
->cdw13
);
3359 uint32_t zone_idx
= 0;
3363 enum NvmeZoneProcessingMask proc_mask
= NVME_PROC_CURRENT_ZONE
;
3365 action
= dw13
& 0xff;
3368 req
->status
= NVME_SUCCESS
;
3371 status
= nvme_get_mgmt_zone_slba_idx(ns
, cmd
, &slba
, &zone_idx
);
3377 zone
= &ns
->zone_array
[zone_idx
];
3378 if (slba
!= zone
->d
.zslba
) {
3379 trace_pci_nvme_err_unaligned_zone_cmd(action
, slba
, zone
->d
.zslba
);
3380 return NVME_INVALID_FIELD
| NVME_DNR
;
3385 case NVME_ZONE_ACTION_OPEN
:
3387 proc_mask
= NVME_PROC_CLOSED_ZONES
;
3389 trace_pci_nvme_open_zone(slba
, zone_idx
, all
);
3390 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_open_zone
, req
);
3393 case NVME_ZONE_ACTION_CLOSE
:
3395 proc_mask
= NVME_PROC_OPENED_ZONES
;
3397 trace_pci_nvme_close_zone(slba
, zone_idx
, all
);
3398 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_close_zone
, req
);
3401 case NVME_ZONE_ACTION_FINISH
:
3403 proc_mask
= NVME_PROC_OPENED_ZONES
| NVME_PROC_CLOSED_ZONES
;
3405 trace_pci_nvme_finish_zone(slba
, zone_idx
, all
);
3406 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_finish_zone
, req
);
3409 case NVME_ZONE_ACTION_RESET
:
3410 resets
= (uintptr_t *)&req
->opaque
;
3413 proc_mask
= NVME_PROC_OPENED_ZONES
| NVME_PROC_CLOSED_ZONES
|
3414 NVME_PROC_FULL_ZONES
;
3416 trace_pci_nvme_reset_zone(slba
, zone_idx
, all
);
3420 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_reset_zone
, req
);
3424 return *resets
? NVME_NO_COMPLETE
: req
->status
;
3426 case NVME_ZONE_ACTION_OFFLINE
:
3428 proc_mask
= NVME_PROC_READ_ONLY_ZONES
;
3430 trace_pci_nvme_offline_zone(slba
, zone_idx
, all
);
3431 status
= nvme_do_zone_op(ns
, zone
, proc_mask
, nvme_offline_zone
, req
);
3434 case NVME_ZONE_ACTION_SET_ZD_EXT
:
3435 trace_pci_nvme_set_descriptor_extension(slba
, zone_idx
);
3436 if (all
|| !ns
->params
.zd_extension_size
) {
3437 return NVME_INVALID_FIELD
| NVME_DNR
;
3439 zd_ext
= nvme_get_zd_extension(ns
, zone_idx
);
3440 status
= nvme_h2c(n
, zd_ext
, ns
->params
.zd_extension_size
, req
);
3442 trace_pci_nvme_err_zd_extension_map_error(zone_idx
);
3446 status
= nvme_set_zd_ext(ns
, zone
);
3447 if (status
== NVME_SUCCESS
) {
3448 trace_pci_nvme_zd_extension_set(zone_idx
);
3454 trace_pci_nvme_err_invalid_mgmt_action(action
);
3455 status
= NVME_INVALID_FIELD
;
3458 if (status
== NVME_ZONE_INVAL_TRANSITION
) {
3459 trace_pci_nvme_err_invalid_zone_state_transition(action
, slba
,
3469 static bool nvme_zone_matches_filter(uint32_t zafs
, NvmeZone
*zl
)
3471 NvmeZoneState zs
= nvme_get_zone_state(zl
);
3474 case NVME_ZONE_REPORT_ALL
:
3476 case NVME_ZONE_REPORT_EMPTY
:
3477 return zs
== NVME_ZONE_STATE_EMPTY
;
3478 case NVME_ZONE_REPORT_IMPLICITLY_OPEN
:
3479 return zs
== NVME_ZONE_STATE_IMPLICITLY_OPEN
;
3480 case NVME_ZONE_REPORT_EXPLICITLY_OPEN
:
3481 return zs
== NVME_ZONE_STATE_EXPLICITLY_OPEN
;
3482 case NVME_ZONE_REPORT_CLOSED
:
3483 return zs
== NVME_ZONE_STATE_CLOSED
;
3484 case NVME_ZONE_REPORT_FULL
:
3485 return zs
== NVME_ZONE_STATE_FULL
;
3486 case NVME_ZONE_REPORT_READ_ONLY
:
3487 return zs
== NVME_ZONE_STATE_READ_ONLY
;
3488 case NVME_ZONE_REPORT_OFFLINE
:
3489 return zs
== NVME_ZONE_STATE_OFFLINE
;
3495 static uint16_t nvme_zone_mgmt_recv(NvmeCtrl
*n
, NvmeRequest
*req
)
3497 NvmeCmd
*cmd
= (NvmeCmd
*)&req
->cmd
;
3498 NvmeNamespace
*ns
= req
->ns
;
3499 /* cdw12 is zero-based number of dwords to return. Convert to bytes */
3500 uint32_t data_size
= (le32_to_cpu(cmd
->cdw12
) + 1) << 2;
3501 uint32_t dw13
= le32_to_cpu(cmd
->cdw13
);
3502 uint32_t zone_idx
, zra
, zrasf
, partial
;
3503 uint64_t max_zones
, nr_zones
= 0;
3508 NvmeZoneReportHeader
*header
;
3510 size_t zone_entry_sz
;
3513 req
->status
= NVME_SUCCESS
;
3515 status
= nvme_get_mgmt_zone_slba_idx(ns
, cmd
, &slba
, &zone_idx
);
3521 if (zra
!= NVME_ZONE_REPORT
&& zra
!= NVME_ZONE_REPORT_EXTENDED
) {
3522 return NVME_INVALID_FIELD
| NVME_DNR
;
3524 if (zra
== NVME_ZONE_REPORT_EXTENDED
&& !ns
->params
.zd_extension_size
) {
3525 return NVME_INVALID_FIELD
| NVME_DNR
;
3528 zrasf
= (dw13
>> 8) & 0xff;
3529 if (zrasf
> NVME_ZONE_REPORT_OFFLINE
) {
3530 return NVME_INVALID_FIELD
| NVME_DNR
;
3533 if (data_size
< sizeof(NvmeZoneReportHeader
)) {
3534 return NVME_INVALID_FIELD
| NVME_DNR
;
3537 status
= nvme_check_mdts(n
, data_size
);
3542 partial
= (dw13
>> 16) & 0x01;
3544 zone_entry_sz
= sizeof(NvmeZoneDescr
);
3545 if (zra
== NVME_ZONE_REPORT_EXTENDED
) {
3546 zone_entry_sz
+= ns
->params
.zd_extension_size
;
3549 max_zones
= (data_size
- sizeof(NvmeZoneReportHeader
)) / zone_entry_sz
;
3550 buf
= g_malloc0(data_size
);
3552 zone
= &ns
->zone_array
[zone_idx
];
3553 for (i
= zone_idx
; i
< ns
->num_zones
; i
++) {
3554 if (partial
&& nr_zones
>= max_zones
) {
3557 if (nvme_zone_matches_filter(zrasf
, zone
++)) {
3561 header
= (NvmeZoneReportHeader
*)buf
;
3562 header
->nr_zones
= cpu_to_le64(nr_zones
);
3564 buf_p
= buf
+ sizeof(NvmeZoneReportHeader
);
3565 for (; zone_idx
< ns
->num_zones
&& max_zones
> 0; zone_idx
++) {
3566 zone
= &ns
->zone_array
[zone_idx
];
3567 if (nvme_zone_matches_filter(zrasf
, zone
)) {
3568 z
= (NvmeZoneDescr
*)buf_p
;
3569 buf_p
+= sizeof(NvmeZoneDescr
);
3573 z
->zcap
= cpu_to_le64(zone
->d
.zcap
);
3574 z
->zslba
= cpu_to_le64(zone
->d
.zslba
);
3577 if (nvme_wp_is_valid(zone
)) {
3578 z
->wp
= cpu_to_le64(zone
->d
.wp
);
3580 z
->wp
= cpu_to_le64(~0ULL);
3583 if (zra
== NVME_ZONE_REPORT_EXTENDED
) {
3584 if (zone
->d
.za
& NVME_ZA_ZD_EXT_VALID
) {
3585 memcpy(buf_p
, nvme_get_zd_extension(ns
, zone_idx
),
3586 ns
->params
.zd_extension_size
);
3588 buf_p
+= ns
->params
.zd_extension_size
;
3595 status
= nvme_c2h(n
, (uint8_t *)buf
, data_size
, req
);
3602 static uint16_t nvme_io_cmd(NvmeCtrl
*n
, NvmeRequest
*req
)
3604 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
3607 trace_pci_nvme_io_cmd(nvme_cid(req
), nsid
, nvme_sqid(req
),
3608 req
->cmd
.opcode
, nvme_io_opc_str(req
->cmd
.opcode
));
3610 if (!nvme_nsid_valid(n
, nsid
)) {
3611 return NVME_INVALID_NSID
| NVME_DNR
;
3615 * In the base NVM command set, Flush may apply to all namespaces
3616 * (indicated by NSID being set to 0xFFFFFFFF). But if that feature is used
3617 * along with TP 4056 (Namespace Types), it may be pretty screwed up.
3619 * If NSID is indeed set to 0xFFFFFFFF, we simply cannot associate the
3620 * opcode with a specific command since we cannot determine a unique I/O
3621 * command set. Opcode 0x0 could have any other meaning than something
3622 * equivalent to flushing and say it DOES have completely different
3623 * semantics in some other command set - does an NSID of 0xFFFFFFFF then
3624 * mean "for all namespaces, apply whatever command set specific command
3625 * that uses the 0x0 opcode?" Or does it mean "for all namespaces, apply
3626 * whatever command that uses the 0x0 opcode if, and only if, it allows
3627 * NSID to be 0xFFFFFFFF"?
3629 * Anyway (and luckily), for now, we do not care about this since the
3630 * device only supports namespace types that includes the NVM Flush command
3631 * (NVM and Zoned), so always do an NVM Flush.
3633 if (req
->cmd
.opcode
== NVME_CMD_FLUSH
) {
3634 return nvme_flush(n
, req
);
3637 req
->ns
= nvme_ns(n
, nsid
);
3638 if (unlikely(!req
->ns
)) {
3639 return NVME_INVALID_FIELD
| NVME_DNR
;
3642 if (!(req
->ns
->iocs
[req
->cmd
.opcode
] & NVME_CMD_EFF_CSUPP
)) {
3643 trace_pci_nvme_err_invalid_opc(req
->cmd
.opcode
);
3644 return NVME_INVALID_OPCODE
| NVME_DNR
;
3647 status
= nvme_ns_status(req
->ns
);
3648 if (unlikely(status
)) {
3652 switch (req
->cmd
.opcode
) {
3653 case NVME_CMD_WRITE_ZEROES
:
3654 return nvme_write_zeroes(n
, req
);
3655 case NVME_CMD_ZONE_APPEND
:
3656 return nvme_zone_append(n
, req
);
3657 case NVME_CMD_WRITE
:
3658 return nvme_write(n
, req
);
3660 return nvme_read(n
, req
);
3661 case NVME_CMD_COMPARE
:
3662 return nvme_compare(n
, req
);
3664 return nvme_dsm(n
, req
);
3665 case NVME_CMD_VERIFY
:
3666 return nvme_verify(n
, req
);
3668 return nvme_copy(n
, req
);
3669 case NVME_CMD_ZONE_MGMT_SEND
:
3670 return nvme_zone_mgmt_send(n
, req
);
3671 case NVME_CMD_ZONE_MGMT_RECV
:
3672 return nvme_zone_mgmt_recv(n
, req
);
3677 return NVME_INVALID_OPCODE
| NVME_DNR
;
3680 static void nvme_free_sq(NvmeSQueue
*sq
, NvmeCtrl
*n
)
3682 n
->sq
[sq
->sqid
] = NULL
;
3683 timer_free(sq
->timer
);
3690 static uint16_t nvme_del_sq(NvmeCtrl
*n
, NvmeRequest
*req
)
3692 NvmeDeleteQ
*c
= (NvmeDeleteQ
*)&req
->cmd
;
3693 NvmeRequest
*r
, *next
;
3696 uint16_t qid
= le16_to_cpu(c
->qid
);
3699 if (unlikely(!qid
|| nvme_check_sqid(n
, qid
))) {
3700 trace_pci_nvme_err_invalid_del_sq(qid
);
3701 return NVME_INVALID_QID
| NVME_DNR
;
3704 trace_pci_nvme_del_sq(qid
);
3707 while (!QTAILQ_EMPTY(&sq
->out_req_list
)) {
3708 r
= QTAILQ_FIRST(&sq
->out_req_list
);
3710 blk_aio_cancel(r
->aiocb
);
3715 * Drain all namespaces if there are still outstanding requests that we
3716 * could not cancel explicitly.
3718 if (!QTAILQ_EMPTY(&sq
->out_req_list
)) {
3719 for (nsid
= 1; nsid
<= NVME_MAX_NAMESPACES
; nsid
++) {
3720 NvmeNamespace
*ns
= nvme_ns(n
, nsid
);
3727 assert(QTAILQ_EMPTY(&sq
->out_req_list
));
3729 if (!nvme_check_cqid(n
, sq
->cqid
)) {
3730 cq
= n
->cq
[sq
->cqid
];
3731 QTAILQ_REMOVE(&cq
->sq_list
, sq
, entry
);
3734 QTAILQ_FOREACH_SAFE(r
, &cq
->req_list
, entry
, next
) {
3736 QTAILQ_REMOVE(&cq
->req_list
, r
, entry
);
3737 QTAILQ_INSERT_TAIL(&sq
->req_list
, r
, entry
);
3742 nvme_free_sq(sq
, n
);
3743 return NVME_SUCCESS
;
3746 static void nvme_init_sq(NvmeSQueue
*sq
, NvmeCtrl
*n
, uint64_t dma_addr
,
3747 uint16_t sqid
, uint16_t cqid
, uint16_t size
)
3753 sq
->dma_addr
= dma_addr
;
3757 sq
->head
= sq
->tail
= 0;
3758 sq
->io_req
= g_new0(NvmeRequest
, sq
->size
);
3760 QTAILQ_INIT(&sq
->req_list
);
3761 QTAILQ_INIT(&sq
->out_req_list
);
3762 for (i
= 0; i
< sq
->size
; i
++) {
3763 sq
->io_req
[i
].sq
= sq
;
3764 QTAILQ_INSERT_TAIL(&(sq
->req_list
), &sq
->io_req
[i
], entry
);
3766 sq
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, nvme_process_sq
, sq
);
3768 assert(n
->cq
[cqid
]);
3770 QTAILQ_INSERT_TAIL(&(cq
->sq_list
), sq
, entry
);
3774 static uint16_t nvme_create_sq(NvmeCtrl
*n
, NvmeRequest
*req
)
3777 NvmeCreateSq
*c
= (NvmeCreateSq
*)&req
->cmd
;
3779 uint16_t cqid
= le16_to_cpu(c
->cqid
);
3780 uint16_t sqid
= le16_to_cpu(c
->sqid
);
3781 uint16_t qsize
= le16_to_cpu(c
->qsize
);
3782 uint16_t qflags
= le16_to_cpu(c
->sq_flags
);
3783 uint64_t prp1
= le64_to_cpu(c
->prp1
);
3785 trace_pci_nvme_create_sq(prp1
, sqid
, cqid
, qsize
, qflags
);
3787 if (unlikely(!cqid
|| nvme_check_cqid(n
, cqid
))) {
3788 trace_pci_nvme_err_invalid_create_sq_cqid(cqid
);
3789 return NVME_INVALID_CQID
| NVME_DNR
;
3791 if (unlikely(!sqid
|| sqid
> n
->params
.max_ioqpairs
||
3792 n
->sq
[sqid
] != NULL
)) {
3793 trace_pci_nvme_err_invalid_create_sq_sqid(sqid
);
3794 return NVME_INVALID_QID
| NVME_DNR
;
3796 if (unlikely(!qsize
|| qsize
> NVME_CAP_MQES(n
->bar
.cap
))) {
3797 trace_pci_nvme_err_invalid_create_sq_size(qsize
);
3798 return NVME_MAX_QSIZE_EXCEEDED
| NVME_DNR
;
3800 if (unlikely(prp1
& (n
->page_size
- 1))) {
3801 trace_pci_nvme_err_invalid_create_sq_addr(prp1
);
3802 return NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
3804 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags
)))) {
3805 trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags
));
3806 return NVME_INVALID_FIELD
| NVME_DNR
;
3808 sq
= g_malloc0(sizeof(*sq
));
3809 nvme_init_sq(sq
, n
, prp1
, sqid
, cqid
, qsize
+ 1);
3810 return NVME_SUCCESS
;
3814 uint64_t units_read
;
3815 uint64_t units_written
;
3816 uint64_t read_commands
;
3817 uint64_t write_commands
;
3820 static void nvme_set_blk_stats(NvmeNamespace
*ns
, struct nvme_stats
*stats
)
3822 BlockAcctStats
*s
= blk_get_stats(ns
->blkconf
.blk
);
3824 stats
->units_read
+= s
->nr_bytes
[BLOCK_ACCT_READ
] >> BDRV_SECTOR_BITS
;
3825 stats
->units_written
+= s
->nr_bytes
[BLOCK_ACCT_WRITE
] >> BDRV_SECTOR_BITS
;
3826 stats
->read_commands
+= s
->nr_ops
[BLOCK_ACCT_READ
];
3827 stats
->write_commands
+= s
->nr_ops
[BLOCK_ACCT_WRITE
];
3830 static uint16_t nvme_smart_info(NvmeCtrl
*n
, uint8_t rae
, uint32_t buf_len
,
3831 uint64_t off
, NvmeRequest
*req
)
3833 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
3834 struct nvme_stats stats
= { 0 };
3835 NvmeSmartLog smart
= { 0 };
3840 if (off
>= sizeof(smart
)) {
3841 return NVME_INVALID_FIELD
| NVME_DNR
;
3844 if (nsid
!= 0xffffffff) {
3845 ns
= nvme_ns(n
, nsid
);
3847 return NVME_INVALID_NSID
| NVME_DNR
;
3849 nvme_set_blk_stats(ns
, &stats
);
3853 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
3858 nvme_set_blk_stats(ns
, &stats
);
3862 trans_len
= MIN(sizeof(smart
) - off
, buf_len
);
3863 smart
.critical_warning
= n
->smart_critical_warning
;
3865 smart
.data_units_read
[0] = cpu_to_le64(DIV_ROUND_UP(stats
.units_read
,
3867 smart
.data_units_written
[0] = cpu_to_le64(DIV_ROUND_UP(stats
.units_written
,
3869 smart
.host_read_commands
[0] = cpu_to_le64(stats
.read_commands
);
3870 smart
.host_write_commands
[0] = cpu_to_le64(stats
.write_commands
);
3872 smart
.temperature
= cpu_to_le16(n
->temperature
);
3874 if ((n
->temperature
>= n
->features
.temp_thresh_hi
) ||
3875 (n
->temperature
<= n
->features
.temp_thresh_low
)) {
3876 smart
.critical_warning
|= NVME_SMART_TEMPERATURE
;
3879 current_ms
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
3880 smart
.power_on_hours
[0] =
3881 cpu_to_le64((((current_ms
- n
->starttime_ms
) / 1000) / 60) / 60);
3884 nvme_clear_events(n
, NVME_AER_TYPE_SMART
);
3887 return nvme_c2h(n
, (uint8_t *) &smart
+ off
, trans_len
, req
);
3890 static uint16_t nvme_fw_log_info(NvmeCtrl
*n
, uint32_t buf_len
, uint64_t off
,
3894 NvmeFwSlotInfoLog fw_log
= {
3898 if (off
>= sizeof(fw_log
)) {
3899 return NVME_INVALID_FIELD
| NVME_DNR
;
3902 strpadcpy((char *)&fw_log
.frs1
, sizeof(fw_log
.frs1
), "1.0", ' ');
3903 trans_len
= MIN(sizeof(fw_log
) - off
, buf_len
);
3905 return nvme_c2h(n
, (uint8_t *) &fw_log
+ off
, trans_len
, req
);
3908 static uint16_t nvme_error_info(NvmeCtrl
*n
, uint8_t rae
, uint32_t buf_len
,
3909 uint64_t off
, NvmeRequest
*req
)
3912 NvmeErrorLog errlog
;
3914 if (off
>= sizeof(errlog
)) {
3915 return NVME_INVALID_FIELD
| NVME_DNR
;
3919 nvme_clear_events(n
, NVME_AER_TYPE_ERROR
);
3922 memset(&errlog
, 0x0, sizeof(errlog
));
3923 trans_len
= MIN(sizeof(errlog
) - off
, buf_len
);
3925 return nvme_c2h(n
, (uint8_t *)&errlog
, trans_len
, req
);
3928 static uint16_t nvme_changed_nslist(NvmeCtrl
*n
, uint8_t rae
, uint32_t buf_len
,
3929 uint64_t off
, NvmeRequest
*req
)
3931 uint32_t nslist
[1024];
3936 memset(nslist
, 0x0, sizeof(nslist
));
3937 trans_len
= MIN(sizeof(nslist
) - off
, buf_len
);
3939 while ((nsid
= find_first_bit(n
->changed_nsids
, NVME_CHANGED_NSID_SIZE
)) !=
3940 NVME_CHANGED_NSID_SIZE
) {
3942 * If more than 1024 namespaces, the first entry in the log page should
3943 * be set to 0xffffffff and the others to 0 as spec.
3945 if (i
== ARRAY_SIZE(nslist
)) {
3946 memset(nslist
, 0x0, sizeof(nslist
));
3947 nslist
[0] = 0xffffffff;
3952 clear_bit(nsid
, n
->changed_nsids
);
3956 * Remove all the remaining list entries in case returns directly due to
3957 * more than 1024 namespaces.
3959 if (nslist
[0] == 0xffffffff) {
3960 bitmap_zero(n
->changed_nsids
, NVME_CHANGED_NSID_SIZE
);
3964 nvme_clear_events(n
, NVME_AER_TYPE_NOTICE
);
3967 return nvme_c2h(n
, ((uint8_t *)nslist
) + off
, trans_len
, req
);
3970 static uint16_t nvme_cmd_effects(NvmeCtrl
*n
, uint8_t csi
, uint32_t buf_len
,
3971 uint64_t off
, NvmeRequest
*req
)
3973 NvmeEffectsLog log
= {};
3974 const uint32_t *src_iocs
= NULL
;
3977 if (off
>= sizeof(log
)) {
3978 trace_pci_nvme_err_invalid_log_page_offset(off
, sizeof(log
));
3979 return NVME_INVALID_FIELD
| NVME_DNR
;
3982 switch (NVME_CC_CSS(n
->bar
.cc
)) {
3983 case NVME_CC_CSS_NVM
:
3984 src_iocs
= nvme_cse_iocs_nvm
;
3986 case NVME_CC_CSS_ADMIN_ONLY
:
3988 case NVME_CC_CSS_CSI
:
3991 src_iocs
= nvme_cse_iocs_nvm
;
3993 case NVME_CSI_ZONED
:
3994 src_iocs
= nvme_cse_iocs_zoned
;
3999 memcpy(log
.acs
, nvme_cse_acs
, sizeof(nvme_cse_acs
));
4002 memcpy(log
.iocs
, src_iocs
, sizeof(log
.iocs
));
4005 trans_len
= MIN(sizeof(log
) - off
, buf_len
);
4007 return nvme_c2h(n
, ((uint8_t *)&log
) + off
, trans_len
, req
);
4010 static uint16_t nvme_get_log(NvmeCtrl
*n
, NvmeRequest
*req
)
4012 NvmeCmd
*cmd
= &req
->cmd
;
4014 uint32_t dw10
= le32_to_cpu(cmd
->cdw10
);
4015 uint32_t dw11
= le32_to_cpu(cmd
->cdw11
);
4016 uint32_t dw12
= le32_to_cpu(cmd
->cdw12
);
4017 uint32_t dw13
= le32_to_cpu(cmd
->cdw13
);
4018 uint8_t lid
= dw10
& 0xff;
4019 uint8_t lsp
= (dw10
>> 8) & 0xf;
4020 uint8_t rae
= (dw10
>> 15) & 0x1;
4021 uint8_t csi
= le32_to_cpu(cmd
->cdw14
) >> 24;
4022 uint32_t numdl
, numdu
;
4023 uint64_t off
, lpol
, lpou
;
4027 numdl
= (dw10
>> 16);
4028 numdu
= (dw11
& 0xffff);
4032 len
= (((numdu
<< 16) | numdl
) + 1) << 2;
4033 off
= (lpou
<< 32ULL) | lpol
;
4036 return NVME_INVALID_FIELD
| NVME_DNR
;
4039 trace_pci_nvme_get_log(nvme_cid(req
), lid
, lsp
, rae
, len
, off
);
4041 status
= nvme_check_mdts(n
, len
);
4047 case NVME_LOG_ERROR_INFO
:
4048 return nvme_error_info(n
, rae
, len
, off
, req
);
4049 case NVME_LOG_SMART_INFO
:
4050 return nvme_smart_info(n
, rae
, len
, off
, req
);
4051 case NVME_LOG_FW_SLOT_INFO
:
4052 return nvme_fw_log_info(n
, len
, off
, req
);
4053 case NVME_LOG_CHANGED_NSLIST
:
4054 return nvme_changed_nslist(n
, rae
, len
, off
, req
);
4055 case NVME_LOG_CMD_EFFECTS
:
4056 return nvme_cmd_effects(n
, csi
, len
, off
, req
);
4058 trace_pci_nvme_err_invalid_log_page(nvme_cid(req
), lid
);
4059 return NVME_INVALID_FIELD
| NVME_DNR
;
4063 static void nvme_free_cq(NvmeCQueue
*cq
, NvmeCtrl
*n
)
4065 n
->cq
[cq
->cqid
] = NULL
;
4066 timer_free(cq
->timer
);
4067 if (msix_enabled(&n
->parent_obj
)) {
4068 msix_vector_unuse(&n
->parent_obj
, cq
->vector
);
4075 static uint16_t nvme_del_cq(NvmeCtrl
*n
, NvmeRequest
*req
)
4077 NvmeDeleteQ
*c
= (NvmeDeleteQ
*)&req
->cmd
;
4079 uint16_t qid
= le16_to_cpu(c
->qid
);
4081 if (unlikely(!qid
|| nvme_check_cqid(n
, qid
))) {
4082 trace_pci_nvme_err_invalid_del_cq_cqid(qid
);
4083 return NVME_INVALID_CQID
| NVME_DNR
;
4087 if (unlikely(!QTAILQ_EMPTY(&cq
->sq_list
))) {
4088 trace_pci_nvme_err_invalid_del_cq_notempty(qid
);
4089 return NVME_INVALID_QUEUE_DEL
;
4091 nvme_irq_deassert(n
, cq
);
4092 trace_pci_nvme_del_cq(qid
);
4093 nvme_free_cq(cq
, n
);
4094 return NVME_SUCCESS
;
4097 static void nvme_init_cq(NvmeCQueue
*cq
, NvmeCtrl
*n
, uint64_t dma_addr
,
4098 uint16_t cqid
, uint16_t vector
, uint16_t size
,
4099 uint16_t irq_enabled
)
4103 if (msix_enabled(&n
->parent_obj
)) {
4104 ret
= msix_vector_use(&n
->parent_obj
, vector
);
4110 cq
->dma_addr
= dma_addr
;
4112 cq
->irq_enabled
= irq_enabled
;
4113 cq
->vector
= vector
;
4114 cq
->head
= cq
->tail
= 0;
4115 QTAILQ_INIT(&cq
->req_list
);
4116 QTAILQ_INIT(&cq
->sq_list
);
4118 cq
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, nvme_post_cqes
, cq
);
4121 static uint16_t nvme_create_cq(NvmeCtrl
*n
, NvmeRequest
*req
)
4124 NvmeCreateCq
*c
= (NvmeCreateCq
*)&req
->cmd
;
4125 uint16_t cqid
= le16_to_cpu(c
->cqid
);
4126 uint16_t vector
= le16_to_cpu(c
->irq_vector
);
4127 uint16_t qsize
= le16_to_cpu(c
->qsize
);
4128 uint16_t qflags
= le16_to_cpu(c
->cq_flags
);
4129 uint64_t prp1
= le64_to_cpu(c
->prp1
);
4131 trace_pci_nvme_create_cq(prp1
, cqid
, vector
, qsize
, qflags
,
4132 NVME_CQ_FLAGS_IEN(qflags
) != 0);
4134 if (unlikely(!cqid
|| cqid
> n
->params
.max_ioqpairs
||
4135 n
->cq
[cqid
] != NULL
)) {
4136 trace_pci_nvme_err_invalid_create_cq_cqid(cqid
);
4137 return NVME_INVALID_QID
| NVME_DNR
;
4139 if (unlikely(!qsize
|| qsize
> NVME_CAP_MQES(n
->bar
.cap
))) {
4140 trace_pci_nvme_err_invalid_create_cq_size(qsize
);
4141 return NVME_MAX_QSIZE_EXCEEDED
| NVME_DNR
;
4143 if (unlikely(prp1
& (n
->page_size
- 1))) {
4144 trace_pci_nvme_err_invalid_create_cq_addr(prp1
);
4145 return NVME_INVALID_PRP_OFFSET
| NVME_DNR
;
4147 if (unlikely(!msix_enabled(&n
->parent_obj
) && vector
)) {
4148 trace_pci_nvme_err_invalid_create_cq_vector(vector
);
4149 return NVME_INVALID_IRQ_VECTOR
| NVME_DNR
;
4151 if (unlikely(vector
>= n
->params
.msix_qsize
)) {
4152 trace_pci_nvme_err_invalid_create_cq_vector(vector
);
4153 return NVME_INVALID_IRQ_VECTOR
| NVME_DNR
;
4155 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags
)))) {
4156 trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags
));
4157 return NVME_INVALID_FIELD
| NVME_DNR
;
4160 cq
= g_malloc0(sizeof(*cq
));
4161 nvme_init_cq(cq
, n
, prp1
, cqid
, vector
, qsize
+ 1,
4162 NVME_CQ_FLAGS_IEN(qflags
));
4165 * It is only required to set qs_created when creating a completion queue;
4166 * creating a submission queue without a matching completion queue will
4169 n
->qs_created
= true;
4170 return NVME_SUCCESS
;
4173 static uint16_t nvme_rpt_empty_id_struct(NvmeCtrl
*n
, NvmeRequest
*req
)
4175 uint8_t id
[NVME_IDENTIFY_DATA_SIZE
] = {};
4177 return nvme_c2h(n
, id
, sizeof(id
), req
);
4180 static inline bool nvme_csi_has_nvm_support(NvmeNamespace
*ns
)
4184 case NVME_CSI_ZONED
:
4190 static uint16_t nvme_identify_ctrl(NvmeCtrl
*n
, NvmeRequest
*req
)
4192 trace_pci_nvme_identify_ctrl();
4194 return nvme_c2h(n
, (uint8_t *)&n
->id_ctrl
, sizeof(n
->id_ctrl
), req
);
4197 static uint16_t nvme_identify_ctrl_csi(NvmeCtrl
*n
, NvmeRequest
*req
)
4199 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4200 uint8_t id
[NVME_IDENTIFY_DATA_SIZE
] = {};
4201 NvmeIdCtrlNvm
*id_nvm
= (NvmeIdCtrlNvm
*)&id
;
4203 trace_pci_nvme_identify_ctrl_csi(c
->csi
);
4207 id_nvm
->vsl
= n
->params
.vsl
;
4208 id_nvm
->dmrsl
= cpu_to_le32(n
->dmrsl
);
4211 case NVME_CSI_ZONED
:
4212 ((NvmeIdCtrlZoned
*)&id
)->zasl
= n
->params
.zasl
;
4216 return NVME_INVALID_FIELD
| NVME_DNR
;
4219 return nvme_c2h(n
, id
, sizeof(id
), req
);
4222 static uint16_t nvme_identify_ns(NvmeCtrl
*n
, NvmeRequest
*req
, bool active
)
4225 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4226 uint32_t nsid
= le32_to_cpu(c
->nsid
);
4228 trace_pci_nvme_identify_ns(nsid
);
4230 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4231 return NVME_INVALID_NSID
| NVME_DNR
;
4234 ns
= nvme_ns(n
, nsid
);
4235 if (unlikely(!ns
)) {
4237 ns
= nvme_subsys_ns(n
->subsys
, nsid
);
4239 return nvme_rpt_empty_id_struct(n
, req
);
4242 return nvme_rpt_empty_id_struct(n
, req
);
4246 if (c
->csi
== NVME_CSI_NVM
&& nvme_csi_has_nvm_support(ns
)) {
4247 return nvme_c2h(n
, (uint8_t *)&ns
->id_ns
, sizeof(NvmeIdNs
), req
);
4250 return NVME_INVALID_CMD_SET
| NVME_DNR
;
4253 static uint16_t nvme_identify_ns_attached_list(NvmeCtrl
*n
, NvmeRequest
*req
)
4255 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4256 uint16_t min_id
= le16_to_cpu(c
->ctrlid
);
4257 uint16_t list
[NVME_CONTROLLER_LIST_SIZE
] = {};
4258 uint16_t *ids
= &list
[1];
4261 int cntlid
, nr_ids
= 0;
4263 trace_pci_nvme_identify_ns_attached_list(min_id
);
4265 if (c
->nsid
== NVME_NSID_BROADCAST
) {
4266 return NVME_INVALID_FIELD
| NVME_DNR
;
4269 ns
= nvme_subsys_ns(n
->subsys
, c
->nsid
);
4271 return NVME_INVALID_FIELD
| NVME_DNR
;
4274 for (cntlid
= min_id
; cntlid
< ARRAY_SIZE(n
->subsys
->ctrls
); cntlid
++) {
4275 ctrl
= nvme_subsys_ctrl(n
->subsys
, cntlid
);
4280 if (!nvme_ns(ctrl
, c
->nsid
)) {
4284 ids
[nr_ids
++] = cntlid
;
4289 return nvme_c2h(n
, (uint8_t *)list
, sizeof(list
), req
);
4292 static uint16_t nvme_identify_ns_csi(NvmeCtrl
*n
, NvmeRequest
*req
,
4296 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4297 uint32_t nsid
= le32_to_cpu(c
->nsid
);
4299 trace_pci_nvme_identify_ns_csi(nsid
, c
->csi
);
4301 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4302 return NVME_INVALID_NSID
| NVME_DNR
;
4305 ns
= nvme_ns(n
, nsid
);
4306 if (unlikely(!ns
)) {
4308 ns
= nvme_subsys_ns(n
->subsys
, nsid
);
4310 return nvme_rpt_empty_id_struct(n
, req
);
4313 return nvme_rpt_empty_id_struct(n
, req
);
4317 if (c
->csi
== NVME_CSI_NVM
&& nvme_csi_has_nvm_support(ns
)) {
4318 return nvme_rpt_empty_id_struct(n
, req
);
4319 } else if (c
->csi
== NVME_CSI_ZONED
&& ns
->csi
== NVME_CSI_ZONED
) {
4320 return nvme_c2h(n
, (uint8_t *)ns
->id_ns_zoned
, sizeof(NvmeIdNsZoned
),
4324 return NVME_INVALID_FIELD
| NVME_DNR
;
4327 static uint16_t nvme_identify_nslist(NvmeCtrl
*n
, NvmeRequest
*req
,
4331 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4332 uint32_t min_nsid
= le32_to_cpu(c
->nsid
);
4333 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4334 static const int data_len
= sizeof(list
);
4335 uint32_t *list_ptr
= (uint32_t *)list
;
4338 trace_pci_nvme_identify_nslist(min_nsid
);
4341 * Both 0xffffffff (NVME_NSID_BROADCAST) and 0xfffffffe are invalid values
4342 * since the Active Namespace ID List should return namespaces with ids
4343 * *higher* than the NSID specified in the command. This is also specified
4344 * in the spec (NVM Express v1.3d, Section 5.15.4).
4346 if (min_nsid
>= NVME_NSID_BROADCAST
- 1) {
4347 return NVME_INVALID_NSID
| NVME_DNR
;
4350 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4354 ns
= nvme_subsys_ns(n
->subsys
, i
);
4362 if (ns
->params
.nsid
<= min_nsid
) {
4365 list_ptr
[j
++] = cpu_to_le32(ns
->params
.nsid
);
4366 if (j
== data_len
/ sizeof(uint32_t)) {
4371 return nvme_c2h(n
, list
, data_len
, req
);
4374 static uint16_t nvme_identify_nslist_csi(NvmeCtrl
*n
, NvmeRequest
*req
,
4378 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4379 uint32_t min_nsid
= le32_to_cpu(c
->nsid
);
4380 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4381 static const int data_len
= sizeof(list
);
4382 uint32_t *list_ptr
= (uint32_t *)list
;
4385 trace_pci_nvme_identify_nslist_csi(min_nsid
, c
->csi
);
4388 * Same as in nvme_identify_nslist(), 0xffffffff/0xfffffffe are invalid.
4390 if (min_nsid
>= NVME_NSID_BROADCAST
- 1) {
4391 return NVME_INVALID_NSID
| NVME_DNR
;
4394 if (c
->csi
!= NVME_CSI_NVM
&& c
->csi
!= NVME_CSI_ZONED
) {
4395 return NVME_INVALID_FIELD
| NVME_DNR
;
4398 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4402 ns
= nvme_subsys_ns(n
->subsys
, i
);
4410 if (ns
->params
.nsid
<= min_nsid
|| c
->csi
!= ns
->csi
) {
4413 list_ptr
[j
++] = cpu_to_le32(ns
->params
.nsid
);
4414 if (j
== data_len
/ sizeof(uint32_t)) {
4419 return nvme_c2h(n
, list
, data_len
, req
);
4422 static uint16_t nvme_identify_ns_descr_list(NvmeCtrl
*n
, NvmeRequest
*req
)
4425 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4426 uint32_t nsid
= le32_to_cpu(c
->nsid
);
4427 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4432 uint8_t v
[NVME_NIDL_UUID
];
4440 struct data
*ns_descrs
= (struct data
*)list
;
4442 trace_pci_nvme_identify_ns_descr_list(nsid
);
4444 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4445 return NVME_INVALID_NSID
| NVME_DNR
;
4448 ns
= nvme_ns(n
, nsid
);
4449 if (unlikely(!ns
)) {
4450 return NVME_INVALID_FIELD
| NVME_DNR
;
4454 * Because the NGUID and EUI64 fields are 0 in the Identify Namespace data
4455 * structure, a Namespace UUID (nidt = 0x3) must be reported in the
4456 * Namespace Identification Descriptor. Add the namespace UUID here.
4458 ns_descrs
->uuid
.hdr
.nidt
= NVME_NIDT_UUID
;
4459 ns_descrs
->uuid
.hdr
.nidl
= NVME_NIDL_UUID
;
4460 memcpy(&ns_descrs
->uuid
.v
, ns
->params
.uuid
.data
, NVME_NIDL_UUID
);
4462 ns_descrs
->csi
.hdr
.nidt
= NVME_NIDT_CSI
;
4463 ns_descrs
->csi
.hdr
.nidl
= NVME_NIDL_CSI
;
4464 ns_descrs
->csi
.v
= ns
->csi
;
4466 return nvme_c2h(n
, list
, sizeof(list
), req
);
4469 static uint16_t nvme_identify_cmd_set(NvmeCtrl
*n
, NvmeRequest
*req
)
4471 uint8_t list
[NVME_IDENTIFY_DATA_SIZE
] = {};
4472 static const int data_len
= sizeof(list
);
4474 trace_pci_nvme_identify_cmd_set();
4476 NVME_SET_CSI(*list
, NVME_CSI_NVM
);
4477 NVME_SET_CSI(*list
, NVME_CSI_ZONED
);
4479 return nvme_c2h(n
, list
, data_len
, req
);
4482 static uint16_t nvme_identify(NvmeCtrl
*n
, NvmeRequest
*req
)
4484 NvmeIdentify
*c
= (NvmeIdentify
*)&req
->cmd
;
4486 trace_pci_nvme_identify(nvme_cid(req
), c
->cns
, le16_to_cpu(c
->ctrlid
),
4490 case NVME_ID_CNS_NS
:
4491 return nvme_identify_ns(n
, req
, true);
4492 case NVME_ID_CNS_NS_PRESENT
:
4493 return nvme_identify_ns(n
, req
, false);
4494 case NVME_ID_CNS_NS_ATTACHED_CTRL_LIST
:
4495 return nvme_identify_ns_attached_list(n
, req
);
4496 case NVME_ID_CNS_CS_NS
:
4497 return nvme_identify_ns_csi(n
, req
, true);
4498 case NVME_ID_CNS_CS_NS_PRESENT
:
4499 return nvme_identify_ns_csi(n
, req
, false);
4500 case NVME_ID_CNS_CTRL
:
4501 return nvme_identify_ctrl(n
, req
);
4502 case NVME_ID_CNS_CS_CTRL
:
4503 return nvme_identify_ctrl_csi(n
, req
);
4504 case NVME_ID_CNS_NS_ACTIVE_LIST
:
4505 return nvme_identify_nslist(n
, req
, true);
4506 case NVME_ID_CNS_NS_PRESENT_LIST
:
4507 return nvme_identify_nslist(n
, req
, false);
4508 case NVME_ID_CNS_CS_NS_ACTIVE_LIST
:
4509 return nvme_identify_nslist_csi(n
, req
, true);
4510 case NVME_ID_CNS_CS_NS_PRESENT_LIST
:
4511 return nvme_identify_nslist_csi(n
, req
, false);
4512 case NVME_ID_CNS_NS_DESCR_LIST
:
4513 return nvme_identify_ns_descr_list(n
, req
);
4514 case NVME_ID_CNS_IO_COMMAND_SET
:
4515 return nvme_identify_cmd_set(n
, req
);
4517 trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c
->cns
));
4518 return NVME_INVALID_FIELD
| NVME_DNR
;
4522 static uint16_t nvme_abort(NvmeCtrl
*n
, NvmeRequest
*req
)
4524 uint16_t sqid
= le32_to_cpu(req
->cmd
.cdw10
) & 0xffff;
4526 req
->cqe
.result
= 1;
4527 if (nvme_check_sqid(n
, sqid
)) {
4528 return NVME_INVALID_FIELD
| NVME_DNR
;
4531 return NVME_SUCCESS
;
4534 static inline void nvme_set_timestamp(NvmeCtrl
*n
, uint64_t ts
)
4536 trace_pci_nvme_setfeat_timestamp(ts
);
4538 n
->host_timestamp
= le64_to_cpu(ts
);
4539 n
->timestamp_set_qemu_clock_ms
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
4542 static inline uint64_t nvme_get_timestamp(const NvmeCtrl
*n
)
4544 uint64_t current_time
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
4545 uint64_t elapsed_time
= current_time
- n
->timestamp_set_qemu_clock_ms
;
4547 union nvme_timestamp
{
4549 uint64_t timestamp
:48;
4557 union nvme_timestamp ts
;
4559 ts
.timestamp
= n
->host_timestamp
+ elapsed_time
;
4561 /* If the host timestamp is non-zero, set the timestamp origin */
4562 ts
.origin
= n
->host_timestamp
? 0x01 : 0x00;
4564 trace_pci_nvme_getfeat_timestamp(ts
.all
);
4566 return cpu_to_le64(ts
.all
);
4569 static uint16_t nvme_get_feature_timestamp(NvmeCtrl
*n
, NvmeRequest
*req
)
4571 uint64_t timestamp
= nvme_get_timestamp(n
);
4573 return nvme_c2h(n
, (uint8_t *)×tamp
, sizeof(timestamp
), req
);
4576 static uint16_t nvme_get_feature(NvmeCtrl
*n
, NvmeRequest
*req
)
4578 NvmeCmd
*cmd
= &req
->cmd
;
4579 uint32_t dw10
= le32_to_cpu(cmd
->cdw10
);
4580 uint32_t dw11
= le32_to_cpu(cmd
->cdw11
);
4581 uint32_t nsid
= le32_to_cpu(cmd
->nsid
);
4583 uint8_t fid
= NVME_GETSETFEAT_FID(dw10
);
4584 NvmeGetFeatureSelect sel
= NVME_GETFEAT_SELECT(dw10
);
4589 static const uint32_t nvme_feature_default
[NVME_FID_MAX
] = {
4590 [NVME_ARBITRATION
] = NVME_ARB_AB_NOLIMIT
,
4593 trace_pci_nvme_getfeat(nvme_cid(req
), nsid
, fid
, sel
, dw11
);
4595 if (!nvme_feature_support
[fid
]) {
4596 return NVME_INVALID_FIELD
| NVME_DNR
;
4599 if (nvme_feature_cap
[fid
] & NVME_FEAT_CAP_NS
) {
4600 if (!nvme_nsid_valid(n
, nsid
) || nsid
== NVME_NSID_BROADCAST
) {
4602 * The Reservation Notification Mask and Reservation Persistence
4603 * features require a status code of Invalid Field in Command when
4604 * NSID is 0xFFFFFFFF. Since the device does not support those
4605 * features we can always return Invalid Namespace or Format as we
4606 * should do for all other features.
4608 return NVME_INVALID_NSID
| NVME_DNR
;
4611 if (!nvme_ns(n
, nsid
)) {
4612 return NVME_INVALID_FIELD
| NVME_DNR
;
4617 case NVME_GETFEAT_SELECT_CURRENT
:
4619 case NVME_GETFEAT_SELECT_SAVED
:
4620 /* no features are saveable by the controller; fallthrough */
4621 case NVME_GETFEAT_SELECT_DEFAULT
:
4623 case NVME_GETFEAT_SELECT_CAP
:
4624 result
= nvme_feature_cap
[fid
];
4629 case NVME_TEMPERATURE_THRESHOLD
:
4633 * The controller only implements the Composite Temperature sensor, so
4634 * return 0 for all other sensors.
4636 if (NVME_TEMP_TMPSEL(dw11
) != NVME_TEMP_TMPSEL_COMPOSITE
) {
4640 switch (NVME_TEMP_THSEL(dw11
)) {
4641 case NVME_TEMP_THSEL_OVER
:
4642 result
= n
->features
.temp_thresh_hi
;
4644 case NVME_TEMP_THSEL_UNDER
:
4645 result
= n
->features
.temp_thresh_low
;
4649 return NVME_INVALID_FIELD
| NVME_DNR
;
4650 case NVME_ERROR_RECOVERY
:
4651 if (!nvme_nsid_valid(n
, nsid
)) {
4652 return NVME_INVALID_NSID
| NVME_DNR
;
4655 ns
= nvme_ns(n
, nsid
);
4656 if (unlikely(!ns
)) {
4657 return NVME_INVALID_FIELD
| NVME_DNR
;
4660 result
= ns
->features
.err_rec
;
4662 case NVME_VOLATILE_WRITE_CACHE
:
4664 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4670 result
= blk_enable_write_cache(ns
->blkconf
.blk
);
4675 trace_pci_nvme_getfeat_vwcache(result
? "enabled" : "disabled");
4677 case NVME_ASYNCHRONOUS_EVENT_CONF
:
4678 result
= n
->features
.async_config
;
4680 case NVME_TIMESTAMP
:
4681 return nvme_get_feature_timestamp(n
, req
);
4688 case NVME_TEMPERATURE_THRESHOLD
:
4691 if (NVME_TEMP_TMPSEL(dw11
) != NVME_TEMP_TMPSEL_COMPOSITE
) {
4695 if (NVME_TEMP_THSEL(dw11
) == NVME_TEMP_THSEL_OVER
) {
4696 result
= NVME_TEMPERATURE_WARNING
;
4700 case NVME_NUMBER_OF_QUEUES
:
4701 result
= (n
->params
.max_ioqpairs
- 1) |
4702 ((n
->params
.max_ioqpairs
- 1) << 16);
4703 trace_pci_nvme_getfeat_numq(result
);
4705 case NVME_INTERRUPT_VECTOR_CONF
:
4707 if (iv
>= n
->params
.max_ioqpairs
+ 1) {
4708 return NVME_INVALID_FIELD
| NVME_DNR
;
4712 if (iv
== n
->admin_cq
.vector
) {
4713 result
|= NVME_INTVC_NOCOALESCING
;
4717 result
= nvme_feature_default
[fid
];
4722 req
->cqe
.result
= cpu_to_le32(result
);
4723 return NVME_SUCCESS
;
4726 static uint16_t nvme_set_feature_timestamp(NvmeCtrl
*n
, NvmeRequest
*req
)
4731 ret
= nvme_h2c(n
, (uint8_t *)×tamp
, sizeof(timestamp
), req
);
4736 nvme_set_timestamp(n
, timestamp
);
4738 return NVME_SUCCESS
;
4741 static uint16_t nvme_set_feature(NvmeCtrl
*n
, NvmeRequest
*req
)
4743 NvmeNamespace
*ns
= NULL
;
4745 NvmeCmd
*cmd
= &req
->cmd
;
4746 uint32_t dw10
= le32_to_cpu(cmd
->cdw10
);
4747 uint32_t dw11
= le32_to_cpu(cmd
->cdw11
);
4748 uint32_t nsid
= le32_to_cpu(cmd
->nsid
);
4749 uint8_t fid
= NVME_GETSETFEAT_FID(dw10
);
4750 uint8_t save
= NVME_SETFEAT_SAVE(dw10
);
4753 trace_pci_nvme_setfeat(nvme_cid(req
), nsid
, fid
, save
, dw11
);
4755 if (save
&& !(nvme_feature_cap
[fid
] & NVME_FEAT_CAP_SAVE
)) {
4756 return NVME_FID_NOT_SAVEABLE
| NVME_DNR
;
4759 if (!nvme_feature_support
[fid
]) {
4760 return NVME_INVALID_FIELD
| NVME_DNR
;
4763 if (nvme_feature_cap
[fid
] & NVME_FEAT_CAP_NS
) {
4764 if (nsid
!= NVME_NSID_BROADCAST
) {
4765 if (!nvme_nsid_valid(n
, nsid
)) {
4766 return NVME_INVALID_NSID
| NVME_DNR
;
4769 ns
= nvme_ns(n
, nsid
);
4770 if (unlikely(!ns
)) {
4771 return NVME_INVALID_FIELD
| NVME_DNR
;
4774 } else if (nsid
&& nsid
!= NVME_NSID_BROADCAST
) {
4775 if (!nvme_nsid_valid(n
, nsid
)) {
4776 return NVME_INVALID_NSID
| NVME_DNR
;
4779 return NVME_FEAT_NOT_NS_SPEC
| NVME_DNR
;
4782 if (!(nvme_feature_cap
[fid
] & NVME_FEAT_CAP_CHANGE
)) {
4783 return NVME_FEAT_NOT_CHANGEABLE
| NVME_DNR
;
4787 case NVME_TEMPERATURE_THRESHOLD
:
4788 if (NVME_TEMP_TMPSEL(dw11
) != NVME_TEMP_TMPSEL_COMPOSITE
) {
4792 switch (NVME_TEMP_THSEL(dw11
)) {
4793 case NVME_TEMP_THSEL_OVER
:
4794 n
->features
.temp_thresh_hi
= NVME_TEMP_TMPTH(dw11
);
4796 case NVME_TEMP_THSEL_UNDER
:
4797 n
->features
.temp_thresh_low
= NVME_TEMP_TMPTH(dw11
);
4800 return NVME_INVALID_FIELD
| NVME_DNR
;
4803 if ((n
->temperature
>= n
->features
.temp_thresh_hi
) ||
4804 (n
->temperature
<= n
->features
.temp_thresh_low
)) {
4805 nvme_smart_event(n
, NVME_AER_INFO_SMART_TEMP_THRESH
);
4809 case NVME_ERROR_RECOVERY
:
4810 if (nsid
== NVME_NSID_BROADCAST
) {
4811 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4818 if (NVME_ID_NS_NSFEAT_DULBE(ns
->id_ns
.nsfeat
)) {
4819 ns
->features
.err_rec
= dw11
;
4827 if (NVME_ID_NS_NSFEAT_DULBE(ns
->id_ns
.nsfeat
)) {
4828 ns
->features
.err_rec
= dw11
;
4831 case NVME_VOLATILE_WRITE_CACHE
:
4832 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
4838 if (!(dw11
& 0x1) && blk_enable_write_cache(ns
->blkconf
.blk
)) {
4839 blk_flush(ns
->blkconf
.blk
);
4842 blk_set_enable_write_cache(ns
->blkconf
.blk
, dw11
& 1);
4847 case NVME_NUMBER_OF_QUEUES
:
4848 if (n
->qs_created
) {
4849 return NVME_CMD_SEQ_ERROR
| NVME_DNR
;
4853 * NVMe v1.3, Section 5.21.1.7: 0xffff is not an allowed value for NCQR
4856 if ((dw11
& 0xffff) == 0xffff || ((dw11
>> 16) & 0xffff) == 0xffff) {
4857 return NVME_INVALID_FIELD
| NVME_DNR
;
4860 trace_pci_nvme_setfeat_numq((dw11
& 0xFFFF) + 1,
4861 ((dw11
>> 16) & 0xFFFF) + 1,
4862 n
->params
.max_ioqpairs
,
4863 n
->params
.max_ioqpairs
);
4864 req
->cqe
.result
= cpu_to_le32((n
->params
.max_ioqpairs
- 1) |
4865 ((n
->params
.max_ioqpairs
- 1) << 16));
4867 case NVME_ASYNCHRONOUS_EVENT_CONF
:
4868 n
->features
.async_config
= dw11
;
4870 case NVME_TIMESTAMP
:
4871 return nvme_set_feature_timestamp(n
, req
);
4872 case NVME_COMMAND_SET_PROFILE
:
4874 trace_pci_nvme_err_invalid_iocsci(dw11
& 0x1ff);
4875 return NVME_CMD_SET_CMB_REJECTED
| NVME_DNR
;
4879 return NVME_FEAT_NOT_CHANGEABLE
| NVME_DNR
;
4881 return NVME_SUCCESS
;
4884 static uint16_t nvme_aer(NvmeCtrl
*n
, NvmeRequest
*req
)
4886 trace_pci_nvme_aer(nvme_cid(req
));
4888 if (n
->outstanding_aers
> n
->params
.aerl
) {
4889 trace_pci_nvme_aer_aerl_exceeded();
4890 return NVME_AER_LIMIT_EXCEEDED
;
4893 n
->aer_reqs
[n
->outstanding_aers
] = req
;
4894 n
->outstanding_aers
++;
4896 if (!QTAILQ_EMPTY(&n
->aer_queue
)) {
4897 nvme_process_aers(n
);
4900 return NVME_NO_COMPLETE
;
4903 static void nvme_update_dmrsl(NvmeCtrl
*n
)
4907 for (nsid
= 1; nsid
<= NVME_MAX_NAMESPACES
; nsid
++) {
4908 NvmeNamespace
*ns
= nvme_ns(n
, nsid
);
4913 n
->dmrsl
= MIN_NON_ZERO(n
->dmrsl
,
4914 BDRV_REQUEST_MAX_BYTES
/ nvme_l2b(ns
, 1));
4918 static void __nvme_select_ns_iocs(NvmeCtrl
*n
, NvmeNamespace
*ns
);
4919 static uint16_t nvme_ns_attachment(NvmeCtrl
*n
, NvmeRequest
*req
)
4923 uint16_t list
[NVME_CONTROLLER_LIST_SIZE
] = {};
4924 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
4925 uint32_t dw10
= le32_to_cpu(req
->cmd
.cdw10
);
4926 bool attach
= !(dw10
& 0xf);
4927 uint16_t *nr_ids
= &list
[0];
4928 uint16_t *ids
= &list
[1];
4932 trace_pci_nvme_ns_attachment(nvme_cid(req
), dw10
& 0xf);
4934 if (!nvme_nsid_valid(n
, nsid
)) {
4935 return NVME_INVALID_NSID
| NVME_DNR
;
4938 ns
= nvme_subsys_ns(n
->subsys
, nsid
);
4940 return NVME_INVALID_FIELD
| NVME_DNR
;
4943 ret
= nvme_h2c(n
, (uint8_t *)list
, 4096, req
);
4949 return NVME_NS_CTRL_LIST_INVALID
| NVME_DNR
;
4952 *nr_ids
= MIN(*nr_ids
, NVME_CONTROLLER_LIST_SIZE
- 1);
4953 for (i
= 0; i
< *nr_ids
; i
++) {
4954 ctrl
= nvme_subsys_ctrl(n
->subsys
, ids
[i
]);
4956 return NVME_NS_CTRL_LIST_INVALID
| NVME_DNR
;
4960 if (nvme_ns(ctrl
, nsid
)) {
4961 return NVME_NS_ALREADY_ATTACHED
| NVME_DNR
;
4964 if (ns
->attached
&& !ns
->params
.shared
) {
4965 return NVME_NS_PRIVATE
| NVME_DNR
;
4968 nvme_attach_ns(ctrl
, ns
);
4969 __nvme_select_ns_iocs(ctrl
, ns
);
4971 if (!nvme_ns(ctrl
, nsid
)) {
4972 return NVME_NS_NOT_ATTACHED
| NVME_DNR
;
4975 ctrl
->namespaces
[nsid
- 1] = NULL
;
4978 nvme_update_dmrsl(ctrl
);
4982 * Add namespace id to the changed namespace id list for event clearing
4983 * via Get Log Page command.
4985 if (!test_and_set_bit(nsid
, ctrl
->changed_nsids
)) {
4986 nvme_enqueue_event(ctrl
, NVME_AER_TYPE_NOTICE
,
4987 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED
,
4988 NVME_LOG_CHANGED_NSLIST
);
4992 return NVME_SUCCESS
;
4995 static uint16_t nvme_format_ns(NvmeCtrl
*n
, NvmeNamespace
*ns
, uint8_t lbaf
,
4996 uint8_t mset
, uint8_t pi
, uint8_t pil
,
4999 int64_t len
, offset
;
5000 struct nvme_aio_format_ctx
*ctx
;
5001 BlockBackend
*blk
= ns
->blkconf
.blk
;
5003 uintptr_t *num_formats
= (uintptr_t *)&req
->opaque
;
5006 if (ns
->params
.zoned
) {
5007 return NVME_INVALID_FORMAT
| NVME_DNR
;
5010 trace_pci_nvme_format_ns(nvme_cid(req
), nvme_nsid(ns
), lbaf
, mset
, pi
, pil
);
5012 if (lbaf
> ns
->id_ns
.nlbaf
) {
5013 return NVME_INVALID_FORMAT
| NVME_DNR
;
5016 ms
= ns
->id_ns
.lbaf
[lbaf
].ms
;
5018 if (pi
&& (ms
< sizeof(NvmeDifTuple
))) {
5019 return NVME_INVALID_FORMAT
| NVME_DNR
;
5022 if (pi
&& pi
> NVME_ID_NS_DPS_TYPE_3
) {
5023 return NVME_INVALID_FIELD
| NVME_DNR
;
5027 nvme_ns_shutdown(ns
);
5028 nvme_ns_cleanup(ns
);
5030 ns
->id_ns
.dps
= (pil
<< 3) | pi
;
5031 ns
->id_ns
.flbas
= lbaf
| (mset
<< 4);
5033 nvme_ns_init_format(ns
);
5035 ns
->status
= NVME_FORMAT_IN_PROGRESS
;
5040 count
= g_new(int, 1);
5046 ctx
= g_new(struct nvme_aio_format_ctx
, 1);
5051 size_t bytes
= MIN(BDRV_REQUEST_MAX_BYTES
, len
);
5055 blk_aio_pwrite_zeroes(blk
, offset
, bytes
, BDRV_REQ_MAY_UNMAP
,
5056 nvme_aio_format_cb
, ctx
);
5064 return NVME_NO_COMPLETE
;
5071 return NVME_SUCCESS
;
5074 static uint16_t nvme_format(NvmeCtrl
*n
, NvmeRequest
*req
)
5077 uint32_t dw10
= le32_to_cpu(req
->cmd
.cdw10
);
5078 uint32_t nsid
= le32_to_cpu(req
->cmd
.nsid
);
5079 uint8_t lbaf
= dw10
& 0xf;
5080 uint8_t mset
= (dw10
>> 4) & 0x1;
5081 uint8_t pi
= (dw10
>> 5) & 0x7;
5082 uint8_t pil
= (dw10
>> 8) & 0x1;
5083 uintptr_t *num_formats
= (uintptr_t *)&req
->opaque
;
5087 trace_pci_nvme_format(nvme_cid(req
), nsid
, lbaf
, mset
, pi
, pil
);
5089 /* 1-initialize; see the comment in nvme_dsm */
5092 if (nsid
!= NVME_NSID_BROADCAST
) {
5093 if (!nvme_nsid_valid(n
, nsid
)) {
5094 return NVME_INVALID_NSID
| NVME_DNR
;
5097 ns
= nvme_ns(n
, nsid
);
5099 return NVME_INVALID_FIELD
| NVME_DNR
;
5102 status
= nvme_format_ns(n
, ns
, lbaf
, mset
, pi
, pil
, req
);
5103 if (status
&& status
!= NVME_NO_COMPLETE
) {
5104 req
->status
= status
;
5107 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5113 status
= nvme_format_ns(n
, ns
, lbaf
, mset
, pi
, pil
, req
);
5114 if (status
&& status
!= NVME_NO_COMPLETE
) {
5115 req
->status
= status
;
5121 /* account for the 1-initialization */
5122 if (--(*num_formats
)) {
5123 return NVME_NO_COMPLETE
;
5129 static uint16_t nvme_admin_cmd(NvmeCtrl
*n
, NvmeRequest
*req
)
5131 trace_pci_nvme_admin_cmd(nvme_cid(req
), nvme_sqid(req
), req
->cmd
.opcode
,
5132 nvme_adm_opc_str(req
->cmd
.opcode
));
5134 if (!(nvme_cse_acs
[req
->cmd
.opcode
] & NVME_CMD_EFF_CSUPP
)) {
5135 trace_pci_nvme_err_invalid_admin_opc(req
->cmd
.opcode
);
5136 return NVME_INVALID_OPCODE
| NVME_DNR
;
5139 /* SGLs shall not be used for Admin commands in NVMe over PCIe */
5140 if (NVME_CMD_FLAGS_PSDT(req
->cmd
.flags
) != NVME_PSDT_PRP
) {
5141 return NVME_INVALID_FIELD
| NVME_DNR
;
5144 switch (req
->cmd
.opcode
) {
5145 case NVME_ADM_CMD_DELETE_SQ
:
5146 return nvme_del_sq(n
, req
);
5147 case NVME_ADM_CMD_CREATE_SQ
:
5148 return nvme_create_sq(n
, req
);
5149 case NVME_ADM_CMD_GET_LOG_PAGE
:
5150 return nvme_get_log(n
, req
);
5151 case NVME_ADM_CMD_DELETE_CQ
:
5152 return nvme_del_cq(n
, req
);
5153 case NVME_ADM_CMD_CREATE_CQ
:
5154 return nvme_create_cq(n
, req
);
5155 case NVME_ADM_CMD_IDENTIFY
:
5156 return nvme_identify(n
, req
);
5157 case NVME_ADM_CMD_ABORT
:
5158 return nvme_abort(n
, req
);
5159 case NVME_ADM_CMD_SET_FEATURES
:
5160 return nvme_set_feature(n
, req
);
5161 case NVME_ADM_CMD_GET_FEATURES
:
5162 return nvme_get_feature(n
, req
);
5163 case NVME_ADM_CMD_ASYNC_EV_REQ
:
5164 return nvme_aer(n
, req
);
5165 case NVME_ADM_CMD_NS_ATTACHMENT
:
5166 return nvme_ns_attachment(n
, req
);
5167 case NVME_ADM_CMD_FORMAT_NVM
:
5168 return nvme_format(n
, req
);
5173 return NVME_INVALID_OPCODE
| NVME_DNR
;
5176 static void nvme_process_sq(void *opaque
)
5178 NvmeSQueue
*sq
= opaque
;
5179 NvmeCtrl
*n
= sq
->ctrl
;
5180 NvmeCQueue
*cq
= n
->cq
[sq
->cqid
];
5187 while (!(nvme_sq_empty(sq
) || QTAILQ_EMPTY(&sq
->req_list
))) {
5188 addr
= sq
->dma_addr
+ sq
->head
* n
->sqe_size
;
5189 if (nvme_addr_read(n
, addr
, (void *)&cmd
, sizeof(cmd
))) {
5190 trace_pci_nvme_err_addr_read(addr
);
5191 trace_pci_nvme_err_cfs();
5192 n
->bar
.csts
= NVME_CSTS_FAILED
;
5195 nvme_inc_sq_head(sq
);
5197 req
= QTAILQ_FIRST(&sq
->req_list
);
5198 QTAILQ_REMOVE(&sq
->req_list
, req
, entry
);
5199 QTAILQ_INSERT_TAIL(&sq
->out_req_list
, req
, entry
);
5200 nvme_req_clear(req
);
5201 req
->cqe
.cid
= cmd
.cid
;
5202 memcpy(&req
->cmd
, &cmd
, sizeof(NvmeCmd
));
5204 status
= sq
->sqid
? nvme_io_cmd(n
, req
) :
5205 nvme_admin_cmd(n
, req
);
5206 if (status
!= NVME_NO_COMPLETE
) {
5207 req
->status
= status
;
5208 nvme_enqueue_req_completion(cq
, req
);
5213 static void nvme_ctrl_reset(NvmeCtrl
*n
)
5218 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5227 for (i
= 0; i
< n
->params
.max_ioqpairs
+ 1; i
++) {
5228 if (n
->sq
[i
] != NULL
) {
5229 nvme_free_sq(n
->sq
[i
], n
);
5232 for (i
= 0; i
< n
->params
.max_ioqpairs
+ 1; i
++) {
5233 if (n
->cq
[i
] != NULL
) {
5234 nvme_free_cq(n
->cq
[i
], n
);
5238 while (!QTAILQ_EMPTY(&n
->aer_queue
)) {
5239 NvmeAsyncEvent
*event
= QTAILQ_FIRST(&n
->aer_queue
);
5240 QTAILQ_REMOVE(&n
->aer_queue
, event
, entry
);
5245 n
->outstanding_aers
= 0;
5246 n
->qs_created
= false;
5251 static void nvme_ctrl_shutdown(NvmeCtrl
*n
)
5257 memory_region_msync(&n
->pmr
.dev
->mr
, 0, n
->pmr
.dev
->size
);
5260 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5266 nvme_ns_shutdown(ns
);
5270 static void __nvme_select_ns_iocs(NvmeCtrl
*n
, NvmeNamespace
*ns
)
5272 ns
->iocs
= nvme_cse_iocs_none
;
5275 if (NVME_CC_CSS(n
->bar
.cc
) != NVME_CC_CSS_ADMIN_ONLY
) {
5276 ns
->iocs
= nvme_cse_iocs_nvm
;
5279 case NVME_CSI_ZONED
:
5280 if (NVME_CC_CSS(n
->bar
.cc
) == NVME_CC_CSS_CSI
) {
5281 ns
->iocs
= nvme_cse_iocs_zoned
;
5282 } else if (NVME_CC_CSS(n
->bar
.cc
) == NVME_CC_CSS_NVM
) {
5283 ns
->iocs
= nvme_cse_iocs_nvm
;
5289 static void nvme_select_ns_iocs(NvmeCtrl
*n
)
5294 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
5300 __nvme_select_ns_iocs(n
, ns
);
5304 static int nvme_start_ctrl(NvmeCtrl
*n
)
5306 uint32_t page_bits
= NVME_CC_MPS(n
->bar
.cc
) + 12;
5307 uint32_t page_size
= 1 << page_bits
;
5309 if (unlikely(n
->cq
[0])) {
5310 trace_pci_nvme_err_startfail_cq();
5313 if (unlikely(n
->sq
[0])) {
5314 trace_pci_nvme_err_startfail_sq();
5317 if (unlikely(!n
->bar
.asq
)) {
5318 trace_pci_nvme_err_startfail_nbarasq();
5321 if (unlikely(!n
->bar
.acq
)) {
5322 trace_pci_nvme_err_startfail_nbaracq();
5325 if (unlikely(n
->bar
.asq
& (page_size
- 1))) {
5326 trace_pci_nvme_err_startfail_asq_misaligned(n
->bar
.asq
);
5329 if (unlikely(n
->bar
.acq
& (page_size
- 1))) {
5330 trace_pci_nvme_err_startfail_acq_misaligned(n
->bar
.acq
);
5333 if (unlikely(!(NVME_CAP_CSS(n
->bar
.cap
) & (1 << NVME_CC_CSS(n
->bar
.cc
))))) {
5334 trace_pci_nvme_err_startfail_css(NVME_CC_CSS(n
->bar
.cc
));
5337 if (unlikely(NVME_CC_MPS(n
->bar
.cc
) <
5338 NVME_CAP_MPSMIN(n
->bar
.cap
))) {
5339 trace_pci_nvme_err_startfail_page_too_small(
5340 NVME_CC_MPS(n
->bar
.cc
),
5341 NVME_CAP_MPSMIN(n
->bar
.cap
));
5344 if (unlikely(NVME_CC_MPS(n
->bar
.cc
) >
5345 NVME_CAP_MPSMAX(n
->bar
.cap
))) {
5346 trace_pci_nvme_err_startfail_page_too_large(
5347 NVME_CC_MPS(n
->bar
.cc
),
5348 NVME_CAP_MPSMAX(n
->bar
.cap
));
5351 if (unlikely(NVME_CC_IOCQES(n
->bar
.cc
) <
5352 NVME_CTRL_CQES_MIN(n
->id_ctrl
.cqes
))) {
5353 trace_pci_nvme_err_startfail_cqent_too_small(
5354 NVME_CC_IOCQES(n
->bar
.cc
),
5355 NVME_CTRL_CQES_MIN(n
->bar
.cap
));
5358 if (unlikely(NVME_CC_IOCQES(n
->bar
.cc
) >
5359 NVME_CTRL_CQES_MAX(n
->id_ctrl
.cqes
))) {
5360 trace_pci_nvme_err_startfail_cqent_too_large(
5361 NVME_CC_IOCQES(n
->bar
.cc
),
5362 NVME_CTRL_CQES_MAX(n
->bar
.cap
));
5365 if (unlikely(NVME_CC_IOSQES(n
->bar
.cc
) <
5366 NVME_CTRL_SQES_MIN(n
->id_ctrl
.sqes
))) {
5367 trace_pci_nvme_err_startfail_sqent_too_small(
5368 NVME_CC_IOSQES(n
->bar
.cc
),
5369 NVME_CTRL_SQES_MIN(n
->bar
.cap
));
5372 if (unlikely(NVME_CC_IOSQES(n
->bar
.cc
) >
5373 NVME_CTRL_SQES_MAX(n
->id_ctrl
.sqes
))) {
5374 trace_pci_nvme_err_startfail_sqent_too_large(
5375 NVME_CC_IOSQES(n
->bar
.cc
),
5376 NVME_CTRL_SQES_MAX(n
->bar
.cap
));
5379 if (unlikely(!NVME_AQA_ASQS(n
->bar
.aqa
))) {
5380 trace_pci_nvme_err_startfail_asqent_sz_zero();
5383 if (unlikely(!NVME_AQA_ACQS(n
->bar
.aqa
))) {
5384 trace_pci_nvme_err_startfail_acqent_sz_zero();
5388 n
->page_bits
= page_bits
;
5389 n
->page_size
= page_size
;
5390 n
->max_prp_ents
= n
->page_size
/ sizeof(uint64_t);
5391 n
->cqe_size
= 1 << NVME_CC_IOCQES(n
->bar
.cc
);
5392 n
->sqe_size
= 1 << NVME_CC_IOSQES(n
->bar
.cc
);
5393 nvme_init_cq(&n
->admin_cq
, n
, n
->bar
.acq
, 0, 0,
5394 NVME_AQA_ACQS(n
->bar
.aqa
) + 1, 1);
5395 nvme_init_sq(&n
->admin_sq
, n
, n
->bar
.asq
, 0, 0,
5396 NVME_AQA_ASQS(n
->bar
.aqa
) + 1);
5398 nvme_set_timestamp(n
, 0ULL);
5400 QTAILQ_INIT(&n
->aer_queue
);
5402 nvme_select_ns_iocs(n
);
5407 static void nvme_cmb_enable_regs(NvmeCtrl
*n
)
5409 NVME_CMBLOC_SET_CDPCILS(n
->bar
.cmbloc
, 1);
5410 NVME_CMBLOC_SET_CDPMLS(n
->bar
.cmbloc
, 1);
5411 NVME_CMBLOC_SET_BIR(n
->bar
.cmbloc
, NVME_CMB_BIR
);
5413 NVME_CMBSZ_SET_SQS(n
->bar
.cmbsz
, 1);
5414 NVME_CMBSZ_SET_CQS(n
->bar
.cmbsz
, 0);
5415 NVME_CMBSZ_SET_LISTS(n
->bar
.cmbsz
, 1);
5416 NVME_CMBSZ_SET_RDS(n
->bar
.cmbsz
, 1);
5417 NVME_CMBSZ_SET_WDS(n
->bar
.cmbsz
, 1);
5418 NVME_CMBSZ_SET_SZU(n
->bar
.cmbsz
, 2); /* MBs */
5419 NVME_CMBSZ_SET_SZ(n
->bar
.cmbsz
, n
->params
.cmb_size_mb
);
5422 static void nvme_write_bar(NvmeCtrl
*n
, hwaddr offset
, uint64_t data
,
5425 if (unlikely(offset
& (sizeof(uint32_t) - 1))) {
5426 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32
,
5427 "MMIO write not 32-bit aligned,"
5428 " offset=0x%"PRIx64
"", offset
);
5429 /* should be ignored, fall through for now */
5432 if (unlikely(size
< sizeof(uint32_t))) {
5433 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall
,
5434 "MMIO write smaller than 32-bits,"
5435 " offset=0x%"PRIx64
", size=%u",
5437 /* should be ignored, fall through for now */
5441 case 0xc: /* INTMS */
5442 if (unlikely(msix_enabled(&(n
->parent_obj
)))) {
5443 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix
,
5444 "undefined access to interrupt mask set"
5445 " when MSI-X is enabled");
5446 /* should be ignored, fall through for now */
5448 n
->bar
.intms
|= data
& 0xffffffff;
5449 n
->bar
.intmc
= n
->bar
.intms
;
5450 trace_pci_nvme_mmio_intm_set(data
& 0xffffffff, n
->bar
.intmc
);
5453 case 0x10: /* INTMC */
5454 if (unlikely(msix_enabled(&(n
->parent_obj
)))) {
5455 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix
,
5456 "undefined access to interrupt mask clr"
5457 " when MSI-X is enabled");
5458 /* should be ignored, fall through for now */
5460 n
->bar
.intms
&= ~(data
& 0xffffffff);
5461 n
->bar
.intmc
= n
->bar
.intms
;
5462 trace_pci_nvme_mmio_intm_clr(data
& 0xffffffff, n
->bar
.intmc
);
5466 trace_pci_nvme_mmio_cfg(data
& 0xffffffff);
5467 /* Windows first sends data, then sends enable bit */
5468 if (!NVME_CC_EN(data
) && !NVME_CC_EN(n
->bar
.cc
) &&
5469 !NVME_CC_SHN(data
) && !NVME_CC_SHN(n
->bar
.cc
))
5474 if (NVME_CC_EN(data
) && !NVME_CC_EN(n
->bar
.cc
)) {
5476 if (unlikely(nvme_start_ctrl(n
))) {
5477 trace_pci_nvme_err_startfail();
5478 n
->bar
.csts
= NVME_CSTS_FAILED
;
5480 trace_pci_nvme_mmio_start_success();
5481 n
->bar
.csts
= NVME_CSTS_READY
;
5483 } else if (!NVME_CC_EN(data
) && NVME_CC_EN(n
->bar
.cc
)) {
5484 trace_pci_nvme_mmio_stopped();
5486 n
->bar
.csts
&= ~NVME_CSTS_READY
;
5488 if (NVME_CC_SHN(data
) && !(NVME_CC_SHN(n
->bar
.cc
))) {
5489 trace_pci_nvme_mmio_shutdown_set();
5490 nvme_ctrl_shutdown(n
);
5492 n
->bar
.csts
|= NVME_CSTS_SHST_COMPLETE
;
5493 } else if (!NVME_CC_SHN(data
) && NVME_CC_SHN(n
->bar
.cc
)) {
5494 trace_pci_nvme_mmio_shutdown_cleared();
5495 n
->bar
.csts
&= ~NVME_CSTS_SHST_COMPLETE
;
5499 case 0x1C: /* CSTS */
5500 if (data
& (1 << 4)) {
5501 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported
,
5502 "attempted to W1C CSTS.NSSRO"
5503 " but CAP.NSSRS is zero (not supported)");
5504 } else if (data
!= 0) {
5505 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts
,
5506 "attempted to set a read only bit"
5507 " of controller status");
5510 case 0x20: /* NSSR */
5511 if (data
== 0x4E564D65) {
5512 trace_pci_nvme_ub_mmiowr_ssreset_unsupported();
5514 /* The spec says that writes of other values have no effect */
5518 case 0x24: /* AQA */
5519 n
->bar
.aqa
= data
& 0xffffffff;
5520 trace_pci_nvme_mmio_aqattr(data
& 0xffffffff);
5522 case 0x28: /* ASQ */
5523 n
->bar
.asq
= size
== 8 ? data
:
5524 (n
->bar
.asq
& ~0xffffffffULL
) | (data
& 0xffffffff);
5525 trace_pci_nvme_mmio_asqaddr(data
);
5527 case 0x2c: /* ASQ hi */
5528 n
->bar
.asq
= (n
->bar
.asq
& 0xffffffff) | (data
<< 32);
5529 trace_pci_nvme_mmio_asqaddr_hi(data
, n
->bar
.asq
);
5531 case 0x30: /* ACQ */
5532 trace_pci_nvme_mmio_acqaddr(data
);
5533 n
->bar
.acq
= size
== 8 ? data
:
5534 (n
->bar
.acq
& ~0xffffffffULL
) | (data
& 0xffffffff);
5536 case 0x34: /* ACQ hi */
5537 n
->bar
.acq
= (n
->bar
.acq
& 0xffffffff) | (data
<< 32);
5538 trace_pci_nvme_mmio_acqaddr_hi(data
, n
->bar
.acq
);
5540 case 0x38: /* CMBLOC */
5541 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved
,
5542 "invalid write to reserved CMBLOC"
5543 " when CMBSZ is zero, ignored");
5545 case 0x3C: /* CMBSZ */
5546 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly
,
5547 "invalid write to read only CMBSZ, ignored");
5549 case 0x50: /* CMBMSC */
5550 if (!NVME_CAP_CMBS(n
->bar
.cap
)) {
5554 n
->bar
.cmbmsc
= size
== 8 ? data
:
5555 (n
->bar
.cmbmsc
& ~0xffffffff) | (data
& 0xffffffff);
5556 n
->cmb
.cmse
= false;
5558 if (NVME_CMBMSC_CRE(data
)) {
5559 nvme_cmb_enable_regs(n
);
5561 if (NVME_CMBMSC_CMSE(data
)) {
5562 hwaddr cba
= NVME_CMBMSC_CBA(data
) << CMBMSC_CBA_SHIFT
;
5563 if (cba
+ int128_get64(n
->cmb
.mem
.size
) < cba
) {
5564 NVME_CMBSTS_SET_CBAI(n
->bar
.cmbsts
, 1);
5577 case 0x54: /* CMBMSC hi */
5578 n
->bar
.cmbmsc
= (n
->bar
.cmbmsc
& 0xffffffff) | (data
<< 32);
5581 case 0xE00: /* PMRCAP */
5582 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly
,
5583 "invalid write to PMRCAP register, ignored");
5585 case 0xE04: /* PMRCTL */
5586 n
->bar
.pmrctl
= data
;
5587 if (NVME_PMRCTL_EN(data
)) {
5588 memory_region_set_enabled(&n
->pmr
.dev
->mr
, true);
5591 memory_region_set_enabled(&n
->pmr
.dev
->mr
, false);
5592 NVME_PMRSTS_SET_NRDY(n
->bar
.pmrsts
, 1);
5593 n
->pmr
.cmse
= false;
5596 case 0xE08: /* PMRSTS */
5597 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly
,
5598 "invalid write to PMRSTS register, ignored");
5600 case 0xE0C: /* PMREBS */
5601 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly
,
5602 "invalid write to PMREBS register, ignored");
5604 case 0xE10: /* PMRSWTP */
5605 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly
,
5606 "invalid write to PMRSWTP register, ignored");
5608 case 0xE14: /* PMRMSCL */
5609 if (!NVME_CAP_PMRS(n
->bar
.cap
)) {
5613 n
->bar
.pmrmsc
= (n
->bar
.pmrmsc
& ~0xffffffff) | (data
& 0xffffffff);
5614 n
->pmr
.cmse
= false;
5616 if (NVME_PMRMSC_CMSE(n
->bar
.pmrmsc
)) {
5617 hwaddr cba
= NVME_PMRMSC_CBA(n
->bar
.pmrmsc
) << PMRMSC_CBA_SHIFT
;
5618 if (cba
+ int128_get64(n
->pmr
.dev
->mr
.size
) < cba
) {
5619 NVME_PMRSTS_SET_CBAI(n
->bar
.pmrsts
, 1);
5628 case 0xE18: /* PMRMSCU */
5629 if (!NVME_CAP_PMRS(n
->bar
.cap
)) {
5633 n
->bar
.pmrmsc
= (n
->bar
.pmrmsc
& 0xffffffff) | (data
<< 32);
5636 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid
,
5637 "invalid MMIO write,"
5638 " offset=0x%"PRIx64
", data=%"PRIx64
"",
5644 static uint64_t nvme_mmio_read(void *opaque
, hwaddr addr
, unsigned size
)
5646 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5647 uint8_t *ptr
= (uint8_t *)&n
->bar
;
5650 trace_pci_nvme_mmio_read(addr
, size
);
5652 if (unlikely(addr
& (sizeof(uint32_t) - 1))) {
5653 NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32
,
5654 "MMIO read not 32-bit aligned,"
5655 " offset=0x%"PRIx64
"", addr
);
5656 /* should RAZ, fall through for now */
5657 } else if (unlikely(size
< sizeof(uint32_t))) {
5658 NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall
,
5659 "MMIO read smaller than 32-bits,"
5660 " offset=0x%"PRIx64
"", addr
);
5661 /* should RAZ, fall through for now */
5664 if (addr
< sizeof(n
->bar
)) {
5666 * When PMRWBM bit 1 is set then read from
5667 * from PMRSTS should ensure prior writes
5668 * made it to persistent media
5670 if (addr
== 0xE08 &&
5671 (NVME_PMRCAP_PMRWBM(n
->bar
.pmrcap
) & 0x02)) {
5672 memory_region_msync(&n
->pmr
.dev
->mr
, 0, n
->pmr
.dev
->size
);
5674 memcpy(&val
, ptr
+ addr
, size
);
5676 NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs
,
5677 "MMIO read beyond last register,"
5678 " offset=0x%"PRIx64
", returning 0", addr
);
5684 static void nvme_process_db(NvmeCtrl
*n
, hwaddr addr
, int val
)
5688 if (unlikely(addr
& ((1 << 2) - 1))) {
5689 NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned
,
5690 "doorbell write not 32-bit aligned,"
5691 " offset=0x%"PRIx64
", ignoring", addr
);
5695 if (((addr
- 0x1000) >> 2) & 1) {
5696 /* Completion queue doorbell write */
5698 uint16_t new_head
= val
& 0xffff;
5702 qid
= (addr
- (0x1000 + (1 << 2))) >> 3;
5703 if (unlikely(nvme_check_cqid(n
, qid
))) {
5704 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq
,
5705 "completion queue doorbell write"
5706 " for nonexistent queue,"
5707 " sqid=%"PRIu32
", ignoring", qid
);
5710 * NVM Express v1.3d, Section 4.1 state: "If host software writes
5711 * an invalid value to the Submission Queue Tail Doorbell or
5712 * Completion Queue Head Doorbell regiter and an Asynchronous Event
5713 * Request command is outstanding, then an asynchronous event is
5714 * posted to the Admin Completion Queue with a status code of
5715 * Invalid Doorbell Write Value."
5717 * Also note that the spec includes the "Invalid Doorbell Register"
5718 * status code, but nowhere does it specify when to use it.
5719 * However, it seems reasonable to use it here in a similar
5722 if (n
->outstanding_aers
) {
5723 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5724 NVME_AER_INFO_ERR_INVALID_DB_REGISTER
,
5725 NVME_LOG_ERROR_INFO
);
5732 if (unlikely(new_head
>= cq
->size
)) {
5733 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead
,
5734 "completion queue doorbell write value"
5735 " beyond queue size, sqid=%"PRIu32
","
5736 " new_head=%"PRIu16
", ignoring",
5739 if (n
->outstanding_aers
) {
5740 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5741 NVME_AER_INFO_ERR_INVALID_DB_VALUE
,
5742 NVME_LOG_ERROR_INFO
);
5748 trace_pci_nvme_mmio_doorbell_cq(cq
->cqid
, new_head
);
5750 start_sqs
= nvme_cq_full(cq
) ? 1 : 0;
5751 cq
->head
= new_head
;
5754 QTAILQ_FOREACH(sq
, &cq
->sq_list
, entry
) {
5755 timer_mod(sq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
5757 timer_mod(cq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
5760 if (cq
->tail
== cq
->head
) {
5761 nvme_irq_deassert(n
, cq
);
5764 /* Submission queue doorbell write */
5766 uint16_t new_tail
= val
& 0xffff;
5769 qid
= (addr
- 0x1000) >> 3;
5770 if (unlikely(nvme_check_sqid(n
, qid
))) {
5771 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq
,
5772 "submission queue doorbell write"
5773 " for nonexistent queue,"
5774 " sqid=%"PRIu32
", ignoring", qid
);
5776 if (n
->outstanding_aers
) {
5777 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5778 NVME_AER_INFO_ERR_INVALID_DB_REGISTER
,
5779 NVME_LOG_ERROR_INFO
);
5786 if (unlikely(new_tail
>= sq
->size
)) {
5787 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail
,
5788 "submission queue doorbell write value"
5789 " beyond queue size, sqid=%"PRIu32
","
5790 " new_tail=%"PRIu16
", ignoring",
5793 if (n
->outstanding_aers
) {
5794 nvme_enqueue_event(n
, NVME_AER_TYPE_ERROR
,
5795 NVME_AER_INFO_ERR_INVALID_DB_VALUE
,
5796 NVME_LOG_ERROR_INFO
);
5802 trace_pci_nvme_mmio_doorbell_sq(sq
->sqid
, new_tail
);
5804 sq
->tail
= new_tail
;
5805 timer_mod(sq
->timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 500);
5809 static void nvme_mmio_write(void *opaque
, hwaddr addr
, uint64_t data
,
5812 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5814 trace_pci_nvme_mmio_write(addr
, data
, size
);
5816 if (addr
< sizeof(n
->bar
)) {
5817 nvme_write_bar(n
, addr
, data
, size
);
5819 nvme_process_db(n
, addr
, data
);
5823 static const MemoryRegionOps nvme_mmio_ops
= {
5824 .read
= nvme_mmio_read
,
5825 .write
= nvme_mmio_write
,
5826 .endianness
= DEVICE_LITTLE_ENDIAN
,
5828 .min_access_size
= 2,
5829 .max_access_size
= 8,
5833 static void nvme_cmb_write(void *opaque
, hwaddr addr
, uint64_t data
,
5836 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5837 stn_le_p(&n
->cmb
.buf
[addr
], size
, data
);
5840 static uint64_t nvme_cmb_read(void *opaque
, hwaddr addr
, unsigned size
)
5842 NvmeCtrl
*n
= (NvmeCtrl
*)opaque
;
5843 return ldn_le_p(&n
->cmb
.buf
[addr
], size
);
5846 static const MemoryRegionOps nvme_cmb_ops
= {
5847 .read
= nvme_cmb_read
,
5848 .write
= nvme_cmb_write
,
5849 .endianness
= DEVICE_LITTLE_ENDIAN
,
5851 .min_access_size
= 1,
5852 .max_access_size
= 8,
5856 static void nvme_check_constraints(NvmeCtrl
*n
, Error
**errp
)
5858 NvmeParams
*params
= &n
->params
;
5860 if (params
->num_queues
) {
5861 warn_report("num_queues is deprecated; please use max_ioqpairs "
5864 params
->max_ioqpairs
= params
->num_queues
- 1;
5867 if (n
->namespace.blkconf
.blk
&& n
->subsys
) {
5868 error_setg(errp
, "subsystem support is unavailable with legacy "
5869 "namespace ('drive' property)");
5873 if (params
->max_ioqpairs
< 1 ||
5874 params
->max_ioqpairs
> NVME_MAX_IOQPAIRS
) {
5875 error_setg(errp
, "max_ioqpairs must be between 1 and %d",
5880 if (params
->msix_qsize
< 1 ||
5881 params
->msix_qsize
> PCI_MSIX_FLAGS_QSIZE
+ 1) {
5882 error_setg(errp
, "msix_qsize must be between 1 and %d",
5883 PCI_MSIX_FLAGS_QSIZE
+ 1);
5887 if (!params
->serial
) {
5888 error_setg(errp
, "serial property not set");
5893 if (host_memory_backend_is_mapped(n
->pmr
.dev
)) {
5894 error_setg(errp
, "can't use already busy memdev: %s",
5895 object_get_canonical_path_component(OBJECT(n
->pmr
.dev
)));
5899 if (!is_power_of_2(n
->pmr
.dev
->size
)) {
5900 error_setg(errp
, "pmr backend size needs to be power of 2 in size");
5904 host_memory_backend_set_mapped(n
->pmr
.dev
, true);
5907 if (n
->params
.zasl
> n
->params
.mdts
) {
5908 error_setg(errp
, "zoned.zasl (Zone Append Size Limit) must be less "
5909 "than or equal to mdts (Maximum Data Transfer Size)");
5913 if (!n
->params
.vsl
) {
5914 error_setg(errp
, "vsl must be non-zero");
5919 static void nvme_init_state(NvmeCtrl
*n
)
5921 n
->num_namespaces
= NVME_MAX_NAMESPACES
;
5922 /* add one to max_ioqpairs to account for the admin queue pair */
5923 n
->reg_size
= pow2ceil(sizeof(NvmeBar
) +
5924 2 * (n
->params
.max_ioqpairs
+ 1) * NVME_DB_SIZE
);
5925 n
->sq
= g_new0(NvmeSQueue
*, n
->params
.max_ioqpairs
+ 1);
5926 n
->cq
= g_new0(NvmeCQueue
*, n
->params
.max_ioqpairs
+ 1);
5927 n
->temperature
= NVME_TEMPERATURE
;
5928 n
->features
.temp_thresh_hi
= NVME_TEMPERATURE_WARNING
;
5929 n
->starttime_ms
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
5930 n
->aer_reqs
= g_new0(NvmeRequest
*, n
->params
.aerl
+ 1);
5933 static void nvme_init_cmb(NvmeCtrl
*n
, PCIDevice
*pci_dev
)
5935 uint64_t cmb_size
= n
->params
.cmb_size_mb
* MiB
;
5937 n
->cmb
.buf
= g_malloc0(cmb_size
);
5938 memory_region_init_io(&n
->cmb
.mem
, OBJECT(n
), &nvme_cmb_ops
, n
,
5939 "nvme-cmb", cmb_size
);
5940 pci_register_bar(pci_dev
, NVME_CMB_BIR
,
5941 PCI_BASE_ADDRESS_SPACE_MEMORY
|
5942 PCI_BASE_ADDRESS_MEM_TYPE_64
|
5943 PCI_BASE_ADDRESS_MEM_PREFETCH
, &n
->cmb
.mem
);
5945 NVME_CAP_SET_CMBS(n
->bar
.cap
, 1);
5947 if (n
->params
.legacy_cmb
) {
5948 nvme_cmb_enable_regs(n
);
5953 static void nvme_init_pmr(NvmeCtrl
*n
, PCIDevice
*pci_dev
)
5955 NVME_PMRCAP_SET_RDS(n
->bar
.pmrcap
, 1);
5956 NVME_PMRCAP_SET_WDS(n
->bar
.pmrcap
, 1);
5957 NVME_PMRCAP_SET_BIR(n
->bar
.pmrcap
, NVME_PMR_BIR
);
5958 /* Turn on bit 1 support */
5959 NVME_PMRCAP_SET_PMRWBM(n
->bar
.pmrcap
, 0x02);
5960 NVME_PMRCAP_SET_CMSS(n
->bar
.pmrcap
, 1);
5962 pci_register_bar(pci_dev
, NVME_PMRCAP_BIR(n
->bar
.pmrcap
),
5963 PCI_BASE_ADDRESS_SPACE_MEMORY
|
5964 PCI_BASE_ADDRESS_MEM_TYPE_64
|
5965 PCI_BASE_ADDRESS_MEM_PREFETCH
, &n
->pmr
.dev
->mr
);
5967 memory_region_set_enabled(&n
->pmr
.dev
->mr
, false);
5970 static int nvme_init_pci(NvmeCtrl
*n
, PCIDevice
*pci_dev
, Error
**errp
)
5972 uint8_t *pci_conf
= pci_dev
->config
;
5973 uint64_t bar_size
, msix_table_size
, msix_pba_size
;
5974 unsigned msix_table_offset
, msix_pba_offset
;
5979 pci_conf
[PCI_INTERRUPT_PIN
] = 1;
5980 pci_config_set_prog_interface(pci_conf
, 0x2);
5982 if (n
->params
.use_intel_id
) {
5983 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
5984 pci_config_set_device_id(pci_conf
, 0x5845);
5986 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_REDHAT
);
5987 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_REDHAT_NVME
);
5990 pci_config_set_class(pci_conf
, PCI_CLASS_STORAGE_EXPRESS
);
5991 pcie_endpoint_cap_init(pci_dev
, 0x80);
5993 bar_size
= QEMU_ALIGN_UP(n
->reg_size
, 4 * KiB
);
5994 msix_table_offset
= bar_size
;
5995 msix_table_size
= PCI_MSIX_ENTRY_SIZE
* n
->params
.msix_qsize
;
5997 bar_size
+= msix_table_size
;
5998 bar_size
= QEMU_ALIGN_UP(bar_size
, 4 * KiB
);
5999 msix_pba_offset
= bar_size
;
6000 msix_pba_size
= QEMU_ALIGN_UP(n
->params
.msix_qsize
, 64) / 8;
6002 bar_size
+= msix_pba_size
;
6003 bar_size
= pow2ceil(bar_size
);
6005 memory_region_init(&n
->bar0
, OBJECT(n
), "nvme-bar0", bar_size
);
6006 memory_region_init_io(&n
->iomem
, OBJECT(n
), &nvme_mmio_ops
, n
, "nvme",
6008 memory_region_add_subregion(&n
->bar0
, 0, &n
->iomem
);
6010 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
|
6011 PCI_BASE_ADDRESS_MEM_TYPE_64
, &n
->bar0
);
6012 ret
= msix_init(pci_dev
, n
->params
.msix_qsize
,
6013 &n
->bar0
, 0, msix_table_offset
,
6014 &n
->bar0
, 0, msix_pba_offset
, 0, &err
);
6016 if (ret
== -ENOTSUP
) {
6017 warn_report_err(err
);
6019 error_propagate(errp
, err
);
6024 if (n
->params
.cmb_size_mb
) {
6025 nvme_init_cmb(n
, pci_dev
);
6029 nvme_init_pmr(n
, pci_dev
);
6035 static void nvme_init_subnqn(NvmeCtrl
*n
)
6037 NvmeSubsystem
*subsys
= n
->subsys
;
6038 NvmeIdCtrl
*id
= &n
->id_ctrl
;
6041 snprintf((char *)id
->subnqn
, sizeof(id
->subnqn
),
6042 "nqn.2019-08.org.qemu:%s", n
->params
.serial
);
6044 pstrcpy((char *)id
->subnqn
, sizeof(id
->subnqn
), (char*)subsys
->subnqn
);
6048 static void nvme_init_ctrl(NvmeCtrl
*n
, PCIDevice
*pci_dev
)
6050 NvmeIdCtrl
*id
= &n
->id_ctrl
;
6051 uint8_t *pci_conf
= pci_dev
->config
;
6053 id
->vid
= cpu_to_le16(pci_get_word(pci_conf
+ PCI_VENDOR_ID
));
6054 id
->ssvid
= cpu_to_le16(pci_get_word(pci_conf
+ PCI_SUBSYSTEM_VENDOR_ID
));
6055 strpadcpy((char *)id
->mn
, sizeof(id
->mn
), "QEMU NVMe Ctrl", ' ');
6056 strpadcpy((char *)id
->fr
, sizeof(id
->fr
), "1.0", ' ');
6057 strpadcpy((char *)id
->sn
, sizeof(id
->sn
), n
->params
.serial
, ' ');
6059 id
->cntlid
= cpu_to_le16(n
->cntlid
);
6061 id
->oaes
= cpu_to_le32(NVME_OAES_NS_ATTR
);
6065 if (n
->params
.use_intel_id
) {
6075 id
->mdts
= n
->params
.mdts
;
6076 id
->ver
= cpu_to_le32(NVME_SPEC_VER
);
6077 id
->oacs
= cpu_to_le16(NVME_OACS_NS_MGMT
| NVME_OACS_FORMAT
);
6078 id
->cntrltype
= 0x1;
6081 * Because the controller always completes the Abort command immediately,
6082 * there can never be more than one concurrently executing Abort command,
6083 * so this value is never used for anything. Note that there can easily be
6084 * many Abort commands in the queues, but they are not considered
6085 * "executing" until processed by nvme_abort.
6087 * The specification recommends a value of 3 for Abort Command Limit (four
6088 * concurrently outstanding Abort commands), so lets use that though it is
6092 id
->aerl
= n
->params
.aerl
;
6093 id
->frmw
= (NVME_NUM_FW_SLOTS
<< 1) | NVME_FRMW_SLOT1_RO
;
6094 id
->lpa
= NVME_LPA_NS_SMART
| NVME_LPA_CSE
| NVME_LPA_EXTENDED
;
6096 /* recommended default value (~70 C) */
6097 id
->wctemp
= cpu_to_le16(NVME_TEMPERATURE_WARNING
);
6098 id
->cctemp
= cpu_to_le16(NVME_TEMPERATURE_CRITICAL
);
6100 id
->sqes
= (0x6 << 4) | 0x6;
6101 id
->cqes
= (0x4 << 4) | 0x4;
6102 id
->nn
= cpu_to_le32(n
->num_namespaces
);
6103 id
->oncs
= cpu_to_le16(NVME_ONCS_WRITE_ZEROES
| NVME_ONCS_TIMESTAMP
|
6104 NVME_ONCS_FEATURES
| NVME_ONCS_DSM
|
6105 NVME_ONCS_COMPARE
| NVME_ONCS_COPY
);
6108 * NOTE: If this device ever supports a command set that does NOT use 0x0
6109 * as a Flush-equivalent operation, support for the broadcast NSID in Flush
6110 * should probably be removed.
6112 * See comment in nvme_io_cmd.
6114 id
->vwc
= NVME_VWC_NSID_BROADCAST_SUPPORT
| NVME_VWC_PRESENT
;
6116 id
->ocfs
= cpu_to_le16(NVME_OCFS_COPY_FORMAT_0
);
6117 id
->sgls
= cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN
|
6118 NVME_CTRL_SGLS_BITBUCKET
);
6120 nvme_init_subnqn(n
);
6122 id
->psd
[0].mp
= cpu_to_le16(0x9c4);
6123 id
->psd
[0].enlat
= cpu_to_le32(0x10);
6124 id
->psd
[0].exlat
= cpu_to_le32(0x4);
6127 id
->cmic
|= NVME_CMIC_MULTI_CTRL
;
6130 NVME_CAP_SET_MQES(n
->bar
.cap
, 0x7ff);
6131 NVME_CAP_SET_CQR(n
->bar
.cap
, 1);
6132 NVME_CAP_SET_TO(n
->bar
.cap
, 0xf);
6133 NVME_CAP_SET_CSS(n
->bar
.cap
, NVME_CAP_CSS_NVM
);
6134 NVME_CAP_SET_CSS(n
->bar
.cap
, NVME_CAP_CSS_CSI_SUPP
);
6135 NVME_CAP_SET_CSS(n
->bar
.cap
, NVME_CAP_CSS_ADMIN_ONLY
);
6136 NVME_CAP_SET_MPSMAX(n
->bar
.cap
, 4);
6137 NVME_CAP_SET_CMBS(n
->bar
.cap
, n
->params
.cmb_size_mb
? 1 : 0);
6138 NVME_CAP_SET_PMRS(n
->bar
.cap
, n
->pmr
.dev
? 1 : 0);
6140 n
->bar
.vs
= NVME_SPEC_VER
;
6141 n
->bar
.intmc
= n
->bar
.intms
= 0;
6144 static int nvme_init_subsys(NvmeCtrl
*n
, Error
**errp
)
6152 cntlid
= nvme_subsys_register_ctrl(n
, errp
);
6162 void nvme_attach_ns(NvmeCtrl
*n
, NvmeNamespace
*ns
)
6164 uint32_t nsid
= ns
->params
.nsid
;
6165 assert(nsid
&& nsid
<= NVME_MAX_NAMESPACES
);
6167 n
->namespaces
[nsid
- 1] = ns
;
6170 n
->dmrsl
= MIN_NON_ZERO(n
->dmrsl
,
6171 BDRV_REQUEST_MAX_BYTES
/ nvme_l2b(ns
, 1));
6174 static void nvme_realize(PCIDevice
*pci_dev
, Error
**errp
)
6176 NvmeCtrl
*n
= NVME(pci_dev
);
6178 Error
*local_err
= NULL
;
6180 nvme_check_constraints(n
, &local_err
);
6182 error_propagate(errp
, local_err
);
6186 qbus_create_inplace(&n
->bus
, sizeof(NvmeBus
), TYPE_NVME_BUS
,
6187 &pci_dev
->qdev
, n
->parent_obj
.qdev
.id
);
6190 if (nvme_init_pci(n
, pci_dev
, errp
)) {
6194 if (nvme_init_subsys(n
, errp
)) {
6195 error_propagate(errp
, local_err
);
6198 nvme_init_ctrl(n
, pci_dev
);
6200 /* setup a namespace if the controller drive property was given */
6201 if (n
->namespace.blkconf
.blk
) {
6203 ns
->params
.nsid
= 1;
6205 if (nvme_ns_setup(n
, ns
, errp
)) {
6209 nvme_attach_ns(n
, ns
);
6213 static void nvme_exit(PCIDevice
*pci_dev
)
6215 NvmeCtrl
*n
= NVME(pci_dev
);
6221 for (i
= 1; i
<= n
->num_namespaces
; i
++) {
6227 nvme_ns_cleanup(ns
);
6232 g_free(n
->aer_reqs
);
6234 if (n
->params
.cmb_size_mb
) {
6239 host_memory_backend_set_mapped(n
->pmr
.dev
, false);
6241 msix_uninit(pci_dev
, &n
->bar0
, &n
->bar0
);
6242 memory_region_del_subregion(&n
->bar0
, &n
->iomem
);
6245 static Property nvme_props
[] = {
6246 DEFINE_BLOCK_PROPERTIES(NvmeCtrl
, namespace.blkconf
),
6247 DEFINE_PROP_LINK("pmrdev", NvmeCtrl
, pmr
.dev
, TYPE_MEMORY_BACKEND
,
6248 HostMemoryBackend
*),
6249 DEFINE_PROP_LINK("subsys", NvmeCtrl
, subsys
, TYPE_NVME_SUBSYS
,
6251 DEFINE_PROP_STRING("serial", NvmeCtrl
, params
.serial
),
6252 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl
, params
.cmb_size_mb
, 0),
6253 DEFINE_PROP_UINT32("num_queues", NvmeCtrl
, params
.num_queues
, 0),
6254 DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl
, params
.max_ioqpairs
, 64),
6255 DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl
, params
.msix_qsize
, 65),
6256 DEFINE_PROP_UINT8("aerl", NvmeCtrl
, params
.aerl
, 3),
6257 DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl
, params
.aer_max_queued
, 64),
6258 DEFINE_PROP_UINT8("mdts", NvmeCtrl
, params
.mdts
, 7),
6259 DEFINE_PROP_UINT8("vsl", NvmeCtrl
, params
.vsl
, 7),
6260 DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl
, params
.use_intel_id
, false),
6261 DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl
, params
.legacy_cmb
, false),
6262 DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl
, params
.zasl
, 0),
6263 DEFINE_PROP_END_OF_LIST(),
6266 static void nvme_get_smart_warning(Object
*obj
, Visitor
*v
, const char *name
,
6267 void *opaque
, Error
**errp
)
6269 NvmeCtrl
*n
= NVME(obj
);
6270 uint8_t value
= n
->smart_critical_warning
;
6272 visit_type_uint8(v
, name
, &value
, errp
);
6275 static void nvme_set_smart_warning(Object
*obj
, Visitor
*v
, const char *name
,
6276 void *opaque
, Error
**errp
)
6278 NvmeCtrl
*n
= NVME(obj
);
6279 uint8_t value
, old_value
, cap
= 0, index
, event
;
6281 if (!visit_type_uint8(v
, name
, &value
, errp
)) {
6285 cap
= NVME_SMART_SPARE
| NVME_SMART_TEMPERATURE
| NVME_SMART_RELIABILITY
6286 | NVME_SMART_MEDIA_READ_ONLY
| NVME_SMART_FAILED_VOLATILE_MEDIA
;
6287 if (NVME_CAP_PMRS(n
->bar
.cap
)) {
6288 cap
|= NVME_SMART_PMR_UNRELIABLE
;
6291 if ((value
& cap
) != value
) {
6292 error_setg(errp
, "unsupported smart critical warning bits: 0x%x",
6297 old_value
= n
->smart_critical_warning
;
6298 n
->smart_critical_warning
= value
;
6300 /* only inject new bits of smart critical warning */
6301 for (index
= 0; index
< NVME_SMART_WARN_MAX
; index
++) {
6303 if (value
& ~old_value
& event
)
6304 nvme_smart_event(n
, event
);
6308 static const VMStateDescription nvme_vmstate
= {
6313 static void nvme_class_init(ObjectClass
*oc
, void *data
)
6315 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6316 PCIDeviceClass
*pc
= PCI_DEVICE_CLASS(oc
);
6318 pc
->realize
= nvme_realize
;
6319 pc
->exit
= nvme_exit
;
6320 pc
->class_id
= PCI_CLASS_STORAGE_EXPRESS
;
6323 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
6324 dc
->desc
= "Non-Volatile Memory Express";
6325 device_class_set_props(dc
, nvme_props
);
6326 dc
->vmsd
= &nvme_vmstate
;
6329 static void nvme_instance_init(Object
*obj
)
6331 NvmeCtrl
*n
= NVME(obj
);
6333 device_add_bootindex_property(obj
, &n
->namespace.blkconf
.bootindex
,
6334 "bootindex", "/namespace@1,0",
6337 object_property_add(obj
, "smart_critical_warning", "uint8",
6338 nvme_get_smart_warning
,
6339 nvme_set_smart_warning
, NULL
, NULL
);
6342 static const TypeInfo nvme_info
= {
6344 .parent
= TYPE_PCI_DEVICE
,
6345 .instance_size
= sizeof(NvmeCtrl
),
6346 .instance_init
= nvme_instance_init
,
6347 .class_init
= nvme_class_init
,
6348 .interfaces
= (InterfaceInfo
[]) {
6349 { INTERFACE_PCIE_DEVICE
},
6354 static const TypeInfo nvme_bus_info
= {
6355 .name
= TYPE_NVME_BUS
,
6357 .instance_size
= sizeof(NvmeBus
),
6360 static void nvme_register_types(void)
6362 type_register_static(&nvme_info
);
6363 type_register_static(&nvme_bus_info
);
6366 type_init(nvme_register_types
)