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memory: add early bail out from cpu_physical_memory_set_dirty_range
[qemu/rayw.git] / target-mips / translate_init.c
blobbb33c7cfebd7effdc584e86df9d9b3ebe37793f9
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t MSAIR;
88 int32_t SEGBITS;
89 int32_t PABITS;
90 int32_t CP0_SRSConf0_rw_bitmask;
91 int32_t CP0_SRSConf0;
92 int32_t CP0_SRSConf1_rw_bitmask;
93 int32_t CP0_SRSConf1;
94 int32_t CP0_SRSConf2_rw_bitmask;
95 int32_t CP0_SRSConf2;
96 int32_t CP0_SRSConf3_rw_bitmask;
97 int32_t CP0_SRSConf3;
98 int32_t CP0_SRSConf4_rw_bitmask;
99 int32_t CP0_SRSConf4;
100 int32_t CP0_PageGrain_rw_bitmask;
101 int32_t CP0_PageGrain;
102 int insn_flags;
103 enum mips_mmu_types mmu_type;
104 };
105
106 /*****************************************************************************/
107 /* MIPS CPU definitions */
108 static const mips_def_t mips_defs[] =
109 {
110 {
111 .name = "4Kc",
112 .CP0_PRid = 0x00018000,
113 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
114 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
115 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
116 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
117 (0 << CP0C1_CA),
118 .CP0_Config2 = MIPS_CONFIG2,
119 .CP0_Config3 = MIPS_CONFIG3,
120 .CP0_LLAddr_rw_bitmask = 0,
121 .CP0_LLAddr_shift = 4,
122 .SYNCI_Step = 32,
123 .CCRes = 2,
124 .CP0_Status_rw_bitmask = 0x1278FF17,
125 .SEGBITS = 32,
126 .PABITS = 32,
127 .insn_flags = CPU_MIPS32,
128 .mmu_type = MMU_TYPE_R4000,
129 },
130 {
131 .name = "4Km",
132 .CP0_PRid = 0x00018300,
133 /* Config1 implemented, fixed mapping MMU,
134 no virtual icache, uncached coherency. */
135 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
136 .CP0_Config1 = MIPS_CONFIG1 |
137 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
138 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
139 (1 << CP0C1_CA),
140 .CP0_Config2 = MIPS_CONFIG2,
141 .CP0_Config3 = MIPS_CONFIG3,
142 .CP0_LLAddr_rw_bitmask = 0,
143 .CP0_LLAddr_shift = 4,
144 .SYNCI_Step = 32,
145 .CCRes = 2,
146 .CP0_Status_rw_bitmask = 0x1258FF17,
147 .SEGBITS = 32,
148 .PABITS = 32,
149 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
150 .mmu_type = MMU_TYPE_FMT,
151 },
152 {
153 .name = "4KEcR1",
154 .CP0_PRid = 0x00018400,
155 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
156 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
157 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
158 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
159 (0 << CP0C1_CA),
160 .CP0_Config2 = MIPS_CONFIG2,
161 .CP0_Config3 = MIPS_CONFIG3,
162 .CP0_LLAddr_rw_bitmask = 0,
163 .CP0_LLAddr_shift = 4,
164 .SYNCI_Step = 32,
165 .CCRes = 2,
166 .CP0_Status_rw_bitmask = 0x1278FF17,
167 .SEGBITS = 32,
168 .PABITS = 32,
169 .insn_flags = CPU_MIPS32,
170 .mmu_type = MMU_TYPE_R4000,
171 },
172 {
173 .name = "4KEmR1",
174 .CP0_PRid = 0x00018500,
175 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
176 .CP0_Config1 = MIPS_CONFIG1 |
177 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
178 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
179 (1 << CP0C1_CA),
180 .CP0_Config2 = MIPS_CONFIG2,
181 .CP0_Config3 = MIPS_CONFIG3,
182 .CP0_LLAddr_rw_bitmask = 0,
183 .CP0_LLAddr_shift = 4,
184 .SYNCI_Step = 32,
185 .CCRes = 2,
186 .CP0_Status_rw_bitmask = 0x1258FF17,
187 .SEGBITS = 32,
188 .PABITS = 32,
189 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
190 .mmu_type = MMU_TYPE_FMT,
191 },
192 {
193 .name = "4KEc",
194 .CP0_PRid = 0x00019000,
195 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
196 (MMU_TYPE_R4000 << CP0C0_MT),
197 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
198 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
199 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
200 (0 << CP0C1_CA),
201 .CP0_Config2 = MIPS_CONFIG2,
202 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
203 .CP0_LLAddr_rw_bitmask = 0,
204 .CP0_LLAddr_shift = 4,
205 .SYNCI_Step = 32,
206 .CCRes = 2,
207 .CP0_Status_rw_bitmask = 0x1278FF17,
208 .SEGBITS = 32,
209 .PABITS = 32,
210 .insn_flags = CPU_MIPS32R2,
211 .mmu_type = MMU_TYPE_R4000,
212 },
213 {
214 .name = "4KEm",
215 .CP0_PRid = 0x00019100,
216 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
217 (MMU_TYPE_FMT << CP0C0_MT),
218 .CP0_Config1 = MIPS_CONFIG1 |
219 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
220 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
221 (1 << CP0C1_CA),
222 .CP0_Config2 = MIPS_CONFIG2,
223 .CP0_Config3 = MIPS_CONFIG3,
224 .CP0_LLAddr_rw_bitmask = 0,
225 .CP0_LLAddr_shift = 4,
226 .SYNCI_Step = 32,
227 .CCRes = 2,
228 .CP0_Status_rw_bitmask = 0x1258FF17,
229 .SEGBITS = 32,
230 .PABITS = 32,
231 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
232 .mmu_type = MMU_TYPE_FMT,
233 },
234 {
235 .name = "24Kc",
236 .CP0_PRid = 0x00019300,
237 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
238 (MMU_TYPE_R4000 << CP0C0_MT),
239 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
240 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
241 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
242 (1 << CP0C1_CA),
243 .CP0_Config2 = MIPS_CONFIG2,
244 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
245 .CP0_LLAddr_rw_bitmask = 0,
246 .CP0_LLAddr_shift = 4,
247 .SYNCI_Step = 32,
248 .CCRes = 2,
249 /* No DSP implemented. */
250 .CP0_Status_rw_bitmask = 0x1278FF1F,
251 .SEGBITS = 32,
252 .PABITS = 32,
253 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
254 .mmu_type = MMU_TYPE_R4000,
255 },
256 {
257 .name = "24Kf",
258 .CP0_PRid = 0x00019300,
259 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
260 (MMU_TYPE_R4000 << CP0C0_MT),
261 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
262 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
263 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
264 (1 << CP0C1_CA),
265 .CP0_Config2 = MIPS_CONFIG2,
266 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
267 .CP0_LLAddr_rw_bitmask = 0,
268 .CP0_LLAddr_shift = 4,
269 .SYNCI_Step = 32,
270 .CCRes = 2,
271 /* No DSP implemented. */
272 .CP0_Status_rw_bitmask = 0x3678FF1F,
273 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
274 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
275 .SEGBITS = 32,
276 .PABITS = 32,
277 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
278 .mmu_type = MMU_TYPE_R4000,
279 },
280 {
281 .name = "34Kf",
282 .CP0_PRid = 0x00019500,
283 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
284 (MMU_TYPE_R4000 << CP0C0_MT),
285 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
286 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
287 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
288 (1 << CP0C1_CA),
289 .CP0_Config2 = MIPS_CONFIG2,
290 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
291 (1 << CP0C3_DSPP),
292 .CP0_LLAddr_rw_bitmask = 0,
293 .CP0_LLAddr_shift = 0,
294 .SYNCI_Step = 32,
295 .CCRes = 2,
296 .CP0_Status_rw_bitmask = 0x3778FF1F,
297 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
298 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
299 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
300 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
301 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
302 (0xff << CP0TCSt_TASID),
303 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
304 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
305 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
306 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
307 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
308 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
309 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
310 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
311 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
312 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
313 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
314 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
315 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
316 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
317 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
318 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
319 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
320 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
321 .SEGBITS = 32,
322 .PABITS = 32,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
324 .mmu_type = MMU_TYPE_R4000,
325 },
326 {
327 .name = "74Kf",
328 .CP0_PRid = 0x00019700,
329 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
330 (MMU_TYPE_R4000 << CP0C0_MT),
331 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
332 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
333 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
334 (1 << CP0C1_CA),
335 .CP0_Config2 = MIPS_CONFIG2,
336 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
337 (1 << CP0C3_VInt),
338 .CP0_LLAddr_rw_bitmask = 0,
339 .CP0_LLAddr_shift = 4,
340 .SYNCI_Step = 32,
341 .CCRes = 2,
342 .CP0_Status_rw_bitmask = 0x3778FF1F,
343 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
344 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
345 .SEGBITS = 32,
346 .PABITS = 32,
347 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
348 .mmu_type = MMU_TYPE_R4000,
349 },
350 {
351 .name = "M14K",
352 .CP0_PRid = 0x00019b00,
353 /* Config1 implemented, fixed mapping MMU,
354 no virtual icache, uncached coherency. */
355 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
356 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
357 .CP0_Config1 = MIPS_CONFIG1,
358 .CP0_Config2 = MIPS_CONFIG2,
359 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
360 .CP0_LLAddr_rw_bitmask = 0,
361 .CP0_LLAddr_shift = 4,
362 .SYNCI_Step = 32,
363 .CCRes = 2,
364 .CP0_Status_rw_bitmask = 0x1258FF17,
365 .SEGBITS = 32,
366 .PABITS = 32,
367 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
368 .mmu_type = MMU_TYPE_FMT,
369 },
370 {
371 .name = "M14Kc",
372 /* This is the TLB-based MMU core. */
373 .CP0_PRid = 0x00019c00,
374 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
375 (MMU_TYPE_R4000 << CP0C0_MT),
376 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
377 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
378 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
379 .CP0_Config2 = MIPS_CONFIG2,
380 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
381 .CP0_LLAddr_rw_bitmask = 0,
382 .CP0_LLAddr_shift = 4,
383 .SYNCI_Step = 32,
384 .CCRes = 2,
385 .CP0_Status_rw_bitmask = 0x1278FF17,
386 .SEGBITS = 32,
387 .PABITS = 32,
388 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
389 .mmu_type = MMU_TYPE_R4000,
390 },
391 {
392 /* FIXME:
393 * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
394 * Config4: MMUExtDef
395 * Config5: EVA, MRP
396 * FIR(FCR0): Has2008
397 * */
398 .name = "P5600",
399 .CP0_PRid = 0x0001A800,
400 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
401 (MMU_TYPE_R4000 << CP0C0_MT),
402 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
403 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
404 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
405 (1 << CP0C1_PC) | (1 << CP0C1_FP),
406 .CP0_Config2 = MIPS_CONFIG2,
407 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
408 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
409 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
410 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
411 (0x1c << CP0C4_KScrExist),
412 .CP0_Config4_rw_bitmask = 0,
413 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
414 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
415 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
416 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
417 .CP0_LLAddr_rw_bitmask = 0,
418 .CP0_LLAddr_shift = 0,
419 .SYNCI_Step = 32,
420 .CCRes = 2,
421 .CP0_Status_rw_bitmask = 0x3C68FF1F,
422 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
423 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
424 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_F64) |
425 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
426 (1 << FCR0_S) | (0x03 << FCR0_PRID),
427 .SEGBITS = 32,
428 .PABITS = 40,
429 .insn_flags = CPU_MIPS32R5 | ASE_MSA,
430 .mmu_type = MMU_TYPE_R4000,
431 },
432 {
433 /* A generic CPU supporting MIPS32 Release 6 ISA.
434 FIXME: Support IEEE 754-2008 FP.
435 Eventually this should be replaced by a real CPU model. */
436 .name = "mips32r6-generic",
437 .CP0_PRid = 0x00010000,
438 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
439 (MMU_TYPE_R4000 << CP0C0_MT),
440 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
441 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
442 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
443 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
444 .CP0_Config2 = MIPS_CONFIG2,
445 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
446 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
447 (1 << CP0C3_RXI) | (1U << CP0C3_M),
448 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
449 (3 << CP0C4_IE) | (1U << CP0C4_M),
450 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
451 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
452 (1 << CP0C5_UFE),
453 .CP0_LLAddr_rw_bitmask = 0,
454 .CP0_LLAddr_shift = 0,
455 .SYNCI_Step = 32,
456 .CCRes = 2,
457 .CP0_Status_rw_bitmask = 0x3058FF1F,
458 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
459 (1U << CP0PG_RIE),
460 .CP0_PageGrain_rw_bitmask = 0,
461 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
462 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
463 (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
464 .SEGBITS = 32,
465 .PABITS = 32,
466 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
467 .mmu_type = MMU_TYPE_R4000,
468 },
469 #if defined(TARGET_MIPS64)
470 {
471 .name = "R4000",
472 .CP0_PRid = 0x00000400,
473 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
474 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
475 /* Note: Config1 is only used internally, the R4000 has only Config0. */
476 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
477 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
478 .CP0_LLAddr_shift = 4,
479 .SYNCI_Step = 16,
480 .CCRes = 2,
481 .CP0_Status_rw_bitmask = 0x3678FFFF,
482 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
483 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
484 .SEGBITS = 40,
485 .PABITS = 36,
486 .insn_flags = CPU_MIPS3,
487 .mmu_type = MMU_TYPE_R4000,
488 },
489 {
490 .name = "VR5432",
491 .CP0_PRid = 0x00005400,
492 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
493 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
494 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
495 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
496 .CP0_LLAddr_shift = 4,
497 .SYNCI_Step = 16,
498 .CCRes = 2,
499 .CP0_Status_rw_bitmask = 0x3678FFFF,
500 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
501 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
502 .SEGBITS = 40,
503 .PABITS = 32,
504 .insn_flags = CPU_VR54XX,
505 .mmu_type = MMU_TYPE_R4000,
506 },
507 {
508 .name = "5Kc",
509 .CP0_PRid = 0x00018100,
510 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
511 (MMU_TYPE_R4000 << CP0C0_MT),
512 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
513 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
514 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
515 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
516 .CP0_Config2 = MIPS_CONFIG2,
517 .CP0_Config3 = MIPS_CONFIG3,
518 .CP0_LLAddr_rw_bitmask = 0,
519 .CP0_LLAddr_shift = 4,
520 .SYNCI_Step = 32,
521 .CCRes = 2,
522 .CP0_Status_rw_bitmask = 0x12F8FFFF,
523 .SEGBITS = 42,
524 .PABITS = 36,
525 .insn_flags = CPU_MIPS64,
526 .mmu_type = MMU_TYPE_R4000,
527 },
528 {
529 .name = "5Kf",
530 .CP0_PRid = 0x00018100,
531 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
532 (MMU_TYPE_R4000 << CP0C0_MT),
533 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
534 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
535 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
536 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
537 .CP0_Config2 = MIPS_CONFIG2,
538 .CP0_Config3 = MIPS_CONFIG3,
539 .CP0_LLAddr_rw_bitmask = 0,
540 .CP0_LLAddr_shift = 4,
541 .SYNCI_Step = 32,
542 .CCRes = 2,
543 .CP0_Status_rw_bitmask = 0x36F8FFFF,
544 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
545 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
546 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
547 .SEGBITS = 42,
548 .PABITS = 36,
549 .insn_flags = CPU_MIPS64,
550 .mmu_type = MMU_TYPE_R4000,
551 },
552 {
553 .name = "20Kc",
554 /* We emulate a later version of the 20Kc, earlier ones had a broken
555 WAIT instruction. */
556 .CP0_PRid = 0x000182a0,
557 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
558 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
559 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
560 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
561 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
562 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
563 .CP0_Config2 = MIPS_CONFIG2,
564 .CP0_Config3 = MIPS_CONFIG3,
565 .CP0_LLAddr_rw_bitmask = 0,
566 .CP0_LLAddr_shift = 0,
567 .SYNCI_Step = 32,
568 .CCRes = 1,
569 .CP0_Status_rw_bitmask = 0x36FBFFFF,
570 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
571 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
572 (1 << FCR0_D) | (1 << FCR0_S) |
573 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
574 .SEGBITS = 40,
575 .PABITS = 36,
576 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
577 .mmu_type = MMU_TYPE_R4000,
578 },
579 {
580 /* A generic CPU providing MIPS64 Release 2 features.
581 FIXME: Eventually this should be replaced by a real CPU model. */
582 .name = "MIPS64R2-generic",
583 .CP0_PRid = 0x00010000,
584 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
585 (MMU_TYPE_R4000 << CP0C0_MT),
586 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
587 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
588 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
589 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
590 .CP0_Config2 = MIPS_CONFIG2,
591 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
592 .CP0_LLAddr_rw_bitmask = 0,
593 .CP0_LLAddr_shift = 0,
594 .SYNCI_Step = 32,
595 .CCRes = 2,
596 .CP0_Status_rw_bitmask = 0x36FBFFFF,
597 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
598 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
599 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
600 .SEGBITS = 42,
601 .PABITS = 36,
602 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
603 .mmu_type = MMU_TYPE_R4000,
604 },
605 {
606 .name = "5KEc",
607 .CP0_PRid = 0x00018900,
608 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
609 (MMU_TYPE_R4000 << CP0C0_MT),
610 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
611 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
612 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
613 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
614 .CP0_Config2 = MIPS_CONFIG2,
615 .CP0_Config3 = MIPS_CONFIG3,
616 .CP0_LLAddr_rw_bitmask = 0,
617 .CP0_LLAddr_shift = 4,
618 .SYNCI_Step = 32,
619 .CCRes = 2,
620 .CP0_Status_rw_bitmask = 0x12F8FFFF,
621 .SEGBITS = 42,
622 .PABITS = 36,
623 .insn_flags = CPU_MIPS64R2,
624 .mmu_type = MMU_TYPE_R4000,
625 },
626 {
627 .name = "5KEf",
628 .CP0_PRid = 0x00018900,
629 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
630 (MMU_TYPE_R4000 << CP0C0_MT),
631 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
632 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
633 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
634 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
635 .CP0_Config2 = MIPS_CONFIG2,
636 .CP0_Config3 = MIPS_CONFIG3,
637 .CP0_LLAddr_rw_bitmask = 0,
638 .CP0_LLAddr_shift = 4,
639 .SYNCI_Step = 32,
640 .CCRes = 2,
641 .CP0_Status_rw_bitmask = 0x36F8FFFF,
642 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
643 (1 << FCR0_D) | (1 << FCR0_S) |
644 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
645 .SEGBITS = 42,
646 .PABITS = 36,
647 .insn_flags = CPU_MIPS64R2,
648 .mmu_type = MMU_TYPE_R4000,
649 },
650 {
651 /* A generic CPU supporting MIPS64 Release 6 ISA.
652 FIXME: Support IEEE 754-2008 FP.
653 Eventually this should be replaced by a real CPU model. */
654 .name = "MIPS64R6-generic",
655 .CP0_PRid = 0x00010000,
656 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
657 (MMU_TYPE_R4000 << CP0C0_MT),
658 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
659 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
660 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
661 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
662 .CP0_Config2 = MIPS_CONFIG2,
663 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
664 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
665 (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
666 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
667 (0xfc << CP0C4_KScrExist),
668 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
669 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
670 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
671 .CP0_LLAddr_rw_bitmask = 0,
672 .CP0_LLAddr_shift = 0,
673 .SYNCI_Step = 32,
674 .CCRes = 2,
675 .CP0_Status_rw_bitmask = 0x30D8FFFF,
676 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
677 (1U << CP0PG_RIE),
678 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
679 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
680 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
681 (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
682 .SEGBITS = 48,
683 .PABITS = 48,
684 .insn_flags = CPU_MIPS64R6 | ASE_MSA,
685 .mmu_type = MMU_TYPE_R4000,
686 },
687 {
688 .name = "Loongson-2E",
689 .CP0_PRid = 0x6302,
690 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
691 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
692 (0x1<<5) | (0x1<<4) | (0x1<<1),
693 /* Note: Config1 is only used internally,
694 Loongson-2E has only Config0. */
695 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
696 .SYNCI_Step = 16,
697 .CCRes = 2,
698 .CP0_Status_rw_bitmask = 0x35D0FFFF,
699 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
700 .SEGBITS = 40,
701 .PABITS = 40,
702 .insn_flags = CPU_LOONGSON2E,
703 .mmu_type = MMU_TYPE_R4000,
704 },
705 {
706 .name = "Loongson-2F",
707 .CP0_PRid = 0x6303,
708 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
709 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
710 (0x1<<5) | (0x1<<4) | (0x1<<1),
711 /* Note: Config1 is only used internally,
712 Loongson-2F has only Config0. */
713 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
714 .SYNCI_Step = 16,
715 .CCRes = 2,
716 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
717 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
718 .SEGBITS = 40,
719 .PABITS = 40,
720 .insn_flags = CPU_LOONGSON2F,
721 .mmu_type = MMU_TYPE_R4000,
722 },
723 {
724 /* A generic CPU providing MIPS64 ASE DSP 2 features.
725 FIXME: Eventually this should be replaced by a real CPU model. */
726 .name = "mips64dspr2",
727 .CP0_PRid = 0x00010000,
728 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
729 (MMU_TYPE_R4000 << CP0C0_MT),
730 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
731 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
732 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
733 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
734 .CP0_Config2 = MIPS_CONFIG2,
735 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
736 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
737 .CP0_LLAddr_rw_bitmask = 0,
738 .CP0_LLAddr_shift = 0,
739 .SYNCI_Step = 32,
740 .CCRes = 2,
741 .CP0_Status_rw_bitmask = 0x37FBFFFF,
742 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
743 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
744 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
745 .SEGBITS = 42,
746 .PABITS = 36,
747 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
748 .mmu_type = MMU_TYPE_R4000,
749 },
750
751 #endif
752 };
753
754 static const mips_def_t *cpu_mips_find_by_name (const char *name)
755 {
756 int i;
757
758 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
759 if (strcasecmp(name, mips_defs[i].name) == 0) {
760 return &mips_defs[i];
761 }
762 }
763 return NULL;
764 }
765
766 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
767 {
768 int i;
769
770 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
771 (*cpu_fprintf)(f, "MIPS '%s'\n",
772 mips_defs[i].name);
773 }
774 }
775
776 #ifndef CONFIG_USER_ONLY
777 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
778 {
779 env->tlb->nb_tlb = 1;
780 env->tlb->map_address = &no_mmu_map_address;
781 }
782
783 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
784 {
785 env->tlb->nb_tlb = 1;
786 env->tlb->map_address = &fixed_mmu_map_address;
787 }
788
789 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
790 {
791 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
792 env->tlb->map_address = &r4k_map_address;
793 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
794 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
795 env->tlb->helper_tlbp = r4k_helper_tlbp;
796 env->tlb->helper_tlbr = r4k_helper_tlbr;
797 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
798 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
799 }
800
801 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
802 {
803 MIPSCPU *cpu = mips_env_get_cpu(env);
804
805 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
806
807 switch (def->mmu_type) {
808 case MMU_TYPE_NONE:
809 no_mmu_init(env, def);
810 break;
811 case MMU_TYPE_R4000:
812 r4k_mmu_init(env, def);
813 break;
814 case MMU_TYPE_FMT:
815 fixed_mmu_init(env, def);
816 break;
817 case MMU_TYPE_R3000:
818 case MMU_TYPE_R6000:
819 case MMU_TYPE_R8000:
820 default:
821 cpu_abort(CPU(cpu), "MMU type not supported\n");
822 }
823 }
824 #endif /* CONFIG_USER_ONLY */
825
826 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
827 {
828 int i;
829
830 for (i = 0; i < MIPS_FPU_MAX; i++)
831 env->fpus[i].fcr0 = def->CP1_fcr0;
832
833 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
834 }
835
836 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
837 {
838 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
839
840 /* MVPConf1 implemented, TLB sharable, no gating storage support,
841 programmable cache partitioning implemented, number of allocatable
842 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
843 implemented, 5 TCs implemented. */
844 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
845 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
846 // TODO: actually do 2 VPEs.
847 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
848 // (0x04 << CP0MVPC0_PTC);
849 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
850 (0x00 << CP0MVPC0_PTC);
851 #if !defined(CONFIG_USER_ONLY)
852 /* Usermode has no TLB support */
853 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
854 #endif
855
856 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
857 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
858 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
859 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
860 (0x1 << CP0MVPC1_PCP1);
861 }
862
863 static void msa_reset(CPUMIPSState *env)
864 {
865 #ifdef CONFIG_USER_ONLY
866 /* MSA access enabled */
867 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
868 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
869 #endif
870
871 /* MSA CSR:
872 - non-signaling floating point exception mode off (NX bit is 0)
873 - Cause, Enables, and Flags are all 0
874 - round to nearest / ties to even (RM bits are 0) */
875 env->active_tc.msacsr = 0;
876
877 restore_msa_fp_status(env);
878
879 /* tininess detected after rounding.*/
880 set_float_detect_tininess(float_tininess_after_rounding,
881 &env->active_tc.msa_fp_status);
882
883 /* clear float_status exception flags */
884 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
885
886 /* clear float_status nan mode */
887 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
888 }
Ray Wang's QEMU Repository