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configure: Remove unused CONFIG_ZERO_MALLOC setting
[qemu/rayw.git] / target-ppc / translate.c
blobb6894751e8df24018ba8e65f39099fd23a8684cd
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93 cpu_reg_names_size = sizeof(cpu_reg_names);
94
95 for (i = 0; i < 8; i++) {
96 snprintf(p, cpu_reg_names_size, "crf%d", i);
97 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
98 offsetof(CPUPPCState, crf[i]), p);
99 p += 5;
100 cpu_reg_names_size -= 5;
101 }
102
103 for (i = 0; i < 32; i++) {
104 snprintf(p, cpu_reg_names_size, "r%d", i);
105 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
106 offsetof(CPUPPCState, gpr[i]), p);
107 p += (i < 10) ? 3 : 4;
108 cpu_reg_names_size -= (i < 10) ? 3 : 4;
109 snprintf(p, cpu_reg_names_size, "r%dH", i);
110 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
111 offsetof(CPUPPCState, gprh[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv;
196 bool lazy_tlb_flush;
197 int mem_idx;
198 int access_type;
199 /* Translation flags */
200 int le_mode;
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 int sf_mode;
204 int has_cfar;
205 #endif
206 int fpu_enabled;
207 int altivec_enabled;
208 int vsx_enabled;
209 int spe_enabled;
210 int tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_reset_fpstatus(void)
254 {
255 gen_helper_reset_fpstatus(cpu_env);
256 }
257
258 static inline void gen_compute_fprf(TCGv_i64 arg)
259 {
260 gen_helper_compute_fprf(cpu_env, arg);
261 gen_helper_float_check_status(cpu_env);
262 }
263
264 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
265 {
266 if (ctx->access_type != access_type) {
267 tcg_gen_movi_i32(cpu_access_type, access_type);
268 ctx->access_type = access_type;
269 }
270 }
271
272 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
273 {
274 if (NARROW_MODE(ctx)) {
275 nip = (uint32_t)nip;
276 }
277 tcg_gen_movi_tl(cpu_nip, nip);
278 }
279
280 void gen_update_current_nip(void *opaque)
281 {
282 DisasContext *ctx = opaque;
283
284 tcg_gen_movi_tl(cpu_nip, ctx->nip);
285 }
286
287 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
288 {
289 TCGv_i32 t0, t1;
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->nip);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
295 gen_helper_raise_exception_err(cpu_env, t0, t1);
296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299 }
300
301 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303 TCGv_i32 t0;
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static inline void gen_debug_exception(DisasContext *ctx)
314 {
315 TCGv_i32 t0;
316
317 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
318 (ctx->exception != POWERPC_EXCP_SYNC)) {
319 gen_update_nip(ctx, ctx->nip);
320 }
321 t0 = tcg_const_i32(EXCP_DEBUG);
322 gen_helper_raise_exception(cpu_env, t0);
323 tcg_temp_free_i32(t0);
324 }
325
326 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
327 {
328 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
329 }
330
331 /* Stop translation */
332 static inline void gen_stop_exception(DisasContext *ctx)
333 {
334 gen_update_nip(ctx, ctx->nip);
335 ctx->exception = POWERPC_EXCP_STOP;
336 }
337
338 #ifndef CONFIG_USER_ONLY
339 /* No need to update nip here, as execution flow will change */
340 static inline void gen_sync_exception(DisasContext *ctx)
341 {
342 ctx->exception = POWERPC_EXCP_SYNC;
343 }
344 #endif
345
346 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
347 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
348
349 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
350 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
351
352 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
353 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
354
355 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
356 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
357
358 typedef struct opcode_t {
359 unsigned char opc1, opc2, opc3;
360 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
361 unsigned char pad[5];
362 #else
363 unsigned char pad[1];
364 #endif
365 opc_handler_t handler;
366 const char *oname;
367 } opcode_t;
368
369 /*****************************************************************************/
370 /*** Instruction decoding ***/
371 #define EXTRACT_HELPER(name, shift, nb) \
372 static inline uint32_t name(uint32_t opcode) \
373 { \
374 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
375 }
376
377 #define EXTRACT_SHELPER(name, shift, nb) \
378 static inline int32_t name(uint32_t opcode) \
379 { \
380 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
381 }
382
383 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
384 static inline uint32_t name(uint32_t opcode) \
385 { \
386 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
387 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
388 }
389 /* Opcode part 1 */
390 EXTRACT_HELPER(opc1, 26, 6);
391 /* Opcode part 2 */
392 EXTRACT_HELPER(opc2, 1, 5);
393 /* Opcode part 3 */
394 EXTRACT_HELPER(opc3, 6, 5);
395 /* Update Cr0 flags */
396 EXTRACT_HELPER(Rc, 0, 1);
397 /* Update Cr6 flags (Altivec) */
398 EXTRACT_HELPER(Rc21, 10, 1);
399 /* Destination */
400 EXTRACT_HELPER(rD, 21, 5);
401 /* Source */
402 EXTRACT_HELPER(rS, 21, 5);
403 /* First operand */
404 EXTRACT_HELPER(rA, 16, 5);
405 /* Second operand */
406 EXTRACT_HELPER(rB, 11, 5);
407 /* Third operand */
408 EXTRACT_HELPER(rC, 6, 5);
409 /*** Get CRn ***/
410 EXTRACT_HELPER(crfD, 23, 3);
411 EXTRACT_HELPER(crfS, 18, 3);
412 EXTRACT_HELPER(crbD, 21, 5);
413 EXTRACT_HELPER(crbA, 16, 5);
414 EXTRACT_HELPER(crbB, 11, 5);
415 /* SPR / TBL */
416 EXTRACT_HELPER(_SPR, 11, 10);
417 static inline uint32_t SPR(uint32_t opcode)
418 {
419 uint32_t sprn = _SPR(opcode);
420
421 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
422 }
423 /*** Get constants ***/
424 /* 16 bits signed immediate value */
425 EXTRACT_SHELPER(SIMM, 0, 16);
426 /* 16 bits unsigned immediate value */
427 EXTRACT_HELPER(UIMM, 0, 16);
428 /* 5 bits signed immediate value */
429 EXTRACT_HELPER(SIMM5, 16, 5);
430 /* 5 bits signed immediate value */
431 EXTRACT_HELPER(UIMM5, 16, 5);
432 /* Bit count */
433 EXTRACT_HELPER(NB, 11, 5);
434 /* Shift count */
435 EXTRACT_HELPER(SH, 11, 5);
436 /* Vector shift count */
437 EXTRACT_HELPER(VSH, 6, 4);
438 /* Mask start */
439 EXTRACT_HELPER(MB, 6, 5);
440 /* Mask end */
441 EXTRACT_HELPER(ME, 1, 5);
442 /* Trap operand */
443 EXTRACT_HELPER(TO, 21, 5);
444
445 EXTRACT_HELPER(CRM, 12, 8);
446
447 #ifndef CONFIG_USER_ONLY
448 EXTRACT_HELPER(SR, 16, 4);
449 #endif
450
451 /* mtfsf/mtfsfi */
452 EXTRACT_HELPER(FPBF, 23, 3);
453 EXTRACT_HELPER(FPIMM, 12, 4);
454 EXTRACT_HELPER(FPL, 25, 1);
455 EXTRACT_HELPER(FPFLM, 17, 8);
456 EXTRACT_HELPER(FPW, 16, 1);
457
458 /*** Jump target decoding ***/
459 /* Immediate address */
460 static inline target_ulong LI(uint32_t opcode)
461 {
462 return (opcode >> 0) & 0x03FFFFFC;
463 }
464
465 static inline uint32_t BD(uint32_t opcode)
466 {
467 return (opcode >> 0) & 0xFFFC;
468 }
469
470 EXTRACT_HELPER(BO, 21, 5);
471 EXTRACT_HELPER(BI, 16, 5);
472 /* Absolute/relative address */
473 EXTRACT_HELPER(AA, 1, 1);
474 /* Link */
475 EXTRACT_HELPER(LK, 0, 1);
476
477 /* DFP Z22-form */
478 EXTRACT_HELPER(DCM, 10, 6)
479
480 /* DFP Z23-form */
481 EXTRACT_HELPER(RMC, 9, 2)
482
483 /* Create a mask between <start> and <end> bits */
484 static inline target_ulong MASK(uint32_t start, uint32_t end)
485 {
486 target_ulong ret;
487
488 #if defined(TARGET_PPC64)
489 if (likely(start == 0)) {
490 ret = UINT64_MAX << (63 - end);
491 } else if (likely(end == 63)) {
492 ret = UINT64_MAX >> start;
493 }
494 #else
495 if (likely(start == 0)) {
496 ret = UINT32_MAX << (31 - end);
497 } else if (likely(end == 31)) {
498 ret = UINT32_MAX >> start;
499 }
500 #endif
501 else {
502 ret = (((target_ulong)(-1ULL)) >> (start)) ^
503 (((target_ulong)(-1ULL) >> (end)) >> 1);
504 if (unlikely(start > end))
505 return ~ret;
506 }
507
508 return ret;
509 }
510
511 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
512 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
513 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
514 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
515 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
516 EXTRACT_HELPER(DM, 8, 2);
517 EXTRACT_HELPER(UIM, 16, 2);
518 EXTRACT_HELPER(SHW, 8, 2);
519 EXTRACT_HELPER(SP, 19, 2);
520 /*****************************************************************************/
521 /* PowerPC instructions table */
522
523 #if defined(DO_PPC_STATISTICS)
524 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
525 { \
526 .opc1 = op1, \
527 .opc2 = op2, \
528 .opc3 = op3, \
529 .pad = { 0, }, \
530 .handler = { \
531 .inval1 = invl, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 .oname = stringify(name), \
552 }, \
553 .oname = stringify(name), \
554 }
555 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 .oname = onam, \
567 }, \
568 .oname = onam, \
569 }
570 #else
571 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
572 { \
573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .pad = { 0, }, \
577 .handler = { \
578 .inval1 = invl, \
579 .type = _typ, \
580 .type2 = _typ2, \
581 .handler = &gen_##name, \
582 }, \
583 .oname = stringify(name), \
584 }
585 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
586 { \
587 .opc1 = op1, \
588 .opc2 = op2, \
589 .opc3 = op3, \
590 .pad = { 0, }, \
591 .handler = { \
592 .inval1 = invl1, \
593 .inval2 = invl2, \
594 .type = _typ, \
595 .type2 = _typ2, \
596 .handler = &gen_##name, \
597 }, \
598 .oname = stringify(name), \
599 }
600 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
601 { \
602 .opc1 = op1, \
603 .opc2 = op2, \
604 .opc3 = op3, \
605 .pad = { 0, }, \
606 .handler = { \
607 .inval1 = invl, \
608 .type = _typ, \
609 .type2 = _typ2, \
610 .handler = &gen_##name, \
611 }, \
612 .oname = onam, \
613 }
614 #endif
615
616 /* SPR load/store helpers */
617 static inline void gen_load_spr(TCGv t, int reg)
618 {
619 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
620 }
621
622 static inline void gen_store_spr(int reg, TCGv t)
623 {
624 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
625 }
626
627 /* Invalid instruction */
628 static void gen_invalid(DisasContext *ctx)
629 {
630 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
631 }
632
633 static opc_handler_t invalid_handler = {
634 .inval1 = 0xFFFFFFFF,
635 .inval2 = 0xFFFFFFFF,
636 .type = PPC_NONE,
637 .type2 = PPC_NONE,
638 .handler = gen_invalid,
639 };
640
641 /*** Integer comparison ***/
642
643 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
644 {
645 TCGv t0 = tcg_temp_new();
646 TCGv_i32 t1 = tcg_temp_new_i32();
647
648 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
649
650 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
651 tcg_gen_trunc_tl_i32(t1, t0);
652 tcg_gen_shli_i32(t1, t1, CRF_LT);
653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
654
655 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
656 tcg_gen_trunc_tl_i32(t1, t0);
657 tcg_gen_shli_i32(t1, t1, CRF_GT);
658 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
659
660 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
661 tcg_gen_trunc_tl_i32(t1, t0);
662 tcg_gen_shli_i32(t1, t1, CRF_EQ);
663 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
664
665 tcg_temp_free(t0);
666 tcg_temp_free_i32(t1);
667 }
668
669 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
670 {
671 TCGv t0 = tcg_const_tl(arg1);
672 gen_op_cmp(arg0, t0, s, crf);
673 tcg_temp_free(t0);
674 }
675
676 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
677 {
678 TCGv t0, t1;
679 t0 = tcg_temp_new();
680 t1 = tcg_temp_new();
681 if (s) {
682 tcg_gen_ext32s_tl(t0, arg0);
683 tcg_gen_ext32s_tl(t1, arg1);
684 } else {
685 tcg_gen_ext32u_tl(t0, arg0);
686 tcg_gen_ext32u_tl(t1, arg1);
687 }
688 gen_op_cmp(t0, t1, s, crf);
689 tcg_temp_free(t1);
690 tcg_temp_free(t0);
691 }
692
693 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
694 {
695 TCGv t0 = tcg_const_tl(arg1);
696 gen_op_cmp32(arg0, t0, s, crf);
697 tcg_temp_free(t0);
698 }
699
700 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
701 {
702 if (NARROW_MODE(ctx)) {
703 gen_op_cmpi32(reg, 0, 1, 0);
704 } else {
705 gen_op_cmpi(reg, 0, 1, 0);
706 }
707 }
708
709 /* cmp */
710 static void gen_cmp(DisasContext *ctx)
711 {
712 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
713 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
714 1, crfD(ctx->opcode));
715 } else {
716 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
717 1, crfD(ctx->opcode));
718 }
719 }
720
721 /* cmpi */
722 static void gen_cmpi(DisasContext *ctx)
723 {
724 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
725 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
726 1, crfD(ctx->opcode));
727 } else {
728 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
729 1, crfD(ctx->opcode));
730 }
731 }
732
733 /* cmpl */
734 static void gen_cmpl(DisasContext *ctx)
735 {
736 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
737 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
738 0, crfD(ctx->opcode));
739 } else {
740 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
741 0, crfD(ctx->opcode));
742 }
743 }
744
745 /* cmpli */
746 static void gen_cmpli(DisasContext *ctx)
747 {
748 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
749 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
750 0, crfD(ctx->opcode));
751 } else {
752 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
753 0, crfD(ctx->opcode));
754 }
755 }
756
757 /* isel (PowerPC 2.03 specification) */
758 static void gen_isel(DisasContext *ctx)
759 {
760 uint32_t bi = rC(ctx->opcode);
761 uint32_t mask = 0x08 >> (bi & 0x03);
762 TCGv t0 = tcg_temp_new();
763 TCGv zr;
764
765 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
766 tcg_gen_andi_tl(t0, t0, mask);
767
768 zr = tcg_const_tl(0);
769 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
770 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
771 cpu_gpr[rB(ctx->opcode)]);
772 tcg_temp_free(zr);
773 tcg_temp_free(t0);
774 }
775
776 /* cmpb: PowerPC 2.05 specification */
777 static void gen_cmpb(DisasContext *ctx)
778 {
779 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
780 cpu_gpr[rB(ctx->opcode)]);
781 }
782
783 /*** Integer arithmetic ***/
784
785 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
786 TCGv arg1, TCGv arg2, int sub)
787 {
788 TCGv t0 = tcg_temp_new();
789
790 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
791 tcg_gen_xor_tl(t0, arg1, arg2);
792 if (sub) {
793 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
794 } else {
795 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
796 }
797 tcg_temp_free(t0);
798 if (NARROW_MODE(ctx)) {
799 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
800 }
801 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
802 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
803 }
804
805 /* Common add function */
806 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
807 TCGv arg2, bool add_ca, bool compute_ca,
808 bool compute_ov, bool compute_rc0)
809 {
810 TCGv t0 = ret;
811
812 if (compute_ca || compute_ov) {
813 t0 = tcg_temp_new();
814 }
815
816 if (compute_ca) {
817 if (NARROW_MODE(ctx)) {
818 /* Caution: a non-obvious corner case of the spec is that we
819 must produce the *entire* 64-bit addition, but produce the
820 carry into bit 32. */
821 TCGv t1 = tcg_temp_new();
822 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
823 tcg_gen_add_tl(t0, arg1, arg2);
824 if (add_ca) {
825 tcg_gen_add_tl(t0, t0, cpu_ca);
826 }
827 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
828 tcg_temp_free(t1);
829 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
830 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
831 } else {
832 TCGv zero = tcg_const_tl(0);
833 if (add_ca) {
834 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
835 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
836 } else {
837 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
838 }
839 tcg_temp_free(zero);
840 }
841 } else {
842 tcg_gen_add_tl(t0, arg1, arg2);
843 if (add_ca) {
844 tcg_gen_add_tl(t0, t0, cpu_ca);
845 }
846 }
847
848 if (compute_ov) {
849 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
850 }
851 if (unlikely(compute_rc0)) {
852 gen_set_Rc0(ctx, t0);
853 }
854
855 if (!TCGV_EQUAL(t0, ret)) {
856 tcg_gen_mov_tl(ret, t0);
857 tcg_temp_free(t0);
858 }
859 }
860 /* Add functions with two operands */
861 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
865 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
866 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
867 }
868 /* Add functions with one operand and one immediate */
869 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
870 add_ca, compute_ca, compute_ov) \
871 static void glue(gen_, name)(DisasContext *ctx) \
872 { \
873 TCGv t0 = tcg_const_tl(const_val); \
874 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
875 cpu_gpr[rA(ctx->opcode)], t0, \
876 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
877 tcg_temp_free(t0); \
878 }
879
880 /* add add. addo addo. */
881 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
882 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
883 /* addc addc. addco addco. */
884 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
885 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
886 /* adde adde. addeo addeo. */
887 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
888 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
889 /* addme addme. addmeo addmeo. */
890 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
891 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
892 /* addze addze. addzeo addzeo.*/
893 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
894 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
895 /* addi */
896 static void gen_addi(DisasContext *ctx)
897 {
898 target_long simm = SIMM(ctx->opcode);
899
900 if (rA(ctx->opcode) == 0) {
901 /* li case */
902 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
903 } else {
904 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
905 cpu_gpr[rA(ctx->opcode)], simm);
906 }
907 }
908 /* addic addic.*/
909 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
910 {
911 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
913 c, 0, 1, 0, compute_rc0);
914 tcg_temp_free(c);
915 }
916
917 static void gen_addic(DisasContext *ctx)
918 {
919 gen_op_addic(ctx, 0);
920 }
921
922 static void gen_addic_(DisasContext *ctx)
923 {
924 gen_op_addic(ctx, 1);
925 }
926
927 /* addis */
928 static void gen_addis(DisasContext *ctx)
929 {
930 target_long simm = SIMM(ctx->opcode);
931
932 if (rA(ctx->opcode) == 0) {
933 /* lis case */
934 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
935 } else {
936 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
937 cpu_gpr[rA(ctx->opcode)], simm << 16);
938 }
939 }
940
941 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
942 TCGv arg2, int sign, int compute_ov)
943 {
944 TCGLabel *l1 = gen_new_label();
945 TCGLabel *l2 = gen_new_label();
946 TCGv_i32 t0 = tcg_temp_local_new_i32();
947 TCGv_i32 t1 = tcg_temp_local_new_i32();
948
949 tcg_gen_trunc_tl_i32(t0, arg1);
950 tcg_gen_trunc_tl_i32(t1, arg2);
951 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
952 if (sign) {
953 TCGLabel *l3 = gen_new_label();
954 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
955 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i32(t0, t0, t1);
958 } else {
959 tcg_gen_divu_i32(t0, t0, t1);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i32(t0, t0, 31);
968 } else {
969 tcg_gen_movi_i32(t0, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 tcg_gen_extu_i32_tl(ret, t0);
977 tcg_temp_free_i32(t0);
978 tcg_temp_free_i32(t1);
979 if (unlikely(Rc(ctx->opcode) != 0))
980 gen_set_Rc0(ctx, ret);
981 }
982 /* Div functions */
983 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
984 static void glue(gen_, name)(DisasContext *ctx) \
985 { \
986 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
987 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
988 sign, compute_ov); \
989 }
990 /* divwu divwu. divwuo divwuo. */
991 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
992 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
993 /* divw divw. divwo divwo. */
994 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
995 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
996
997 /* div[wd]eu[o][.] */
998 #define GEN_DIVE(name, hlpr, compute_ov) \
999 static void gen_##name(DisasContext *ctx) \
1000 { \
1001 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1002 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1004 tcg_temp_free_i32(t0); \
1005 if (unlikely(Rc(ctx->opcode) != 0)) { \
1006 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1007 } \
1008 }
1009
1010 GEN_DIVE(divweu, divweu, 0);
1011 GEN_DIVE(divweuo, divweu, 1);
1012 GEN_DIVE(divwe, divwe, 0);
1013 GEN_DIVE(divweo, divwe, 1);
1014
1015 #if defined(TARGET_PPC64)
1016 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1017 TCGv arg2, int sign, int compute_ov)
1018 {
1019 TCGLabel *l1 = gen_new_label();
1020 TCGLabel *l2 = gen_new_label();
1021
1022 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1023 if (sign) {
1024 TCGLabel *l3 = gen_new_label();
1025 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1026 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1027 gen_set_label(l3);
1028 tcg_gen_div_i64(ret, arg1, arg2);
1029 } else {
1030 tcg_gen_divu_i64(ret, arg1, arg2);
1031 }
1032 if (compute_ov) {
1033 tcg_gen_movi_tl(cpu_ov, 0);
1034 }
1035 tcg_gen_br(l2);
1036 gen_set_label(l1);
1037 if (sign) {
1038 tcg_gen_sari_i64(ret, arg1, 63);
1039 } else {
1040 tcg_gen_movi_i64(ret, 0);
1041 }
1042 if (compute_ov) {
1043 tcg_gen_movi_tl(cpu_ov, 1);
1044 tcg_gen_movi_tl(cpu_so, 1);
1045 }
1046 gen_set_label(l2);
1047 if (unlikely(Rc(ctx->opcode) != 0))
1048 gen_set_Rc0(ctx, ret);
1049 }
1050 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1051 static void glue(gen_, name)(DisasContext *ctx) \
1052 { \
1053 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1055 sign, compute_ov); \
1056 }
1057 /* divwu divwu. divwuo divwuo. */
1058 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1059 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1060 /* divw divw. divwo divwo. */
1061 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1062 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1063
1064 GEN_DIVE(divdeu, divdeu, 0);
1065 GEN_DIVE(divdeuo, divdeu, 1);
1066 GEN_DIVE(divde, divde, 0);
1067 GEN_DIVE(divdeo, divde, 1);
1068 #endif
1069
1070 /* mulhw mulhw. */
1071 static void gen_mulhw(DisasContext *ctx)
1072 {
1073 TCGv_i32 t0 = tcg_temp_new_i32();
1074 TCGv_i32 t1 = tcg_temp_new_i32();
1075
1076 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1077 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1078 tcg_gen_muls2_i32(t0, t1, t0, t1);
1079 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1080 tcg_temp_free_i32(t0);
1081 tcg_temp_free_i32(t1);
1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1084 }
1085
1086 /* mulhwu mulhwu. */
1087 static void gen_mulhwu(DisasContext *ctx)
1088 {
1089 TCGv_i32 t0 = tcg_temp_new_i32();
1090 TCGv_i32 t1 = tcg_temp_new_i32();
1091
1092 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1093 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1094 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1095 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1096 tcg_temp_free_i32(t0);
1097 tcg_temp_free_i32(t1);
1098 if (unlikely(Rc(ctx->opcode) != 0))
1099 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1100 }
1101
1102 /* mullw mullw. */
1103 static void gen_mullw(DisasContext *ctx)
1104 {
1105 #if defined(TARGET_PPC64)
1106 TCGv_i64 t0, t1;
1107 t0 = tcg_temp_new_i64();
1108 t1 = tcg_temp_new_i64();
1109 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1110 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1111 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1112 tcg_temp_free(t0);
1113 tcg_temp_free(t1);
1114 #else
1115 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1116 cpu_gpr[rB(ctx->opcode)]);
1117 #endif
1118 if (unlikely(Rc(ctx->opcode) != 0))
1119 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1120 }
1121
1122 /* mullwo mullwo. */
1123 static void gen_mullwo(DisasContext *ctx)
1124 {
1125 TCGv_i32 t0 = tcg_temp_new_i32();
1126 TCGv_i32 t1 = tcg_temp_new_i32();
1127
1128 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1129 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1130 tcg_gen_muls2_i32(t0, t1, t0, t1);
1131 #if defined(TARGET_PPC64)
1132 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1133 #else
1134 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1135 #endif
1136
1137 tcg_gen_sari_i32(t0, t0, 31);
1138 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1139 tcg_gen_extu_i32_tl(cpu_ov, t0);
1140 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1141
1142 tcg_temp_free_i32(t0);
1143 tcg_temp_free_i32(t1);
1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1146 }
1147
1148 /* mulli */
1149 static void gen_mulli(DisasContext *ctx)
1150 {
1151 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1152 SIMM(ctx->opcode));
1153 }
1154
1155 #if defined(TARGET_PPC64)
1156 /* mulhd mulhd. */
1157 static void gen_mulhd(DisasContext *ctx)
1158 {
1159 TCGv lo = tcg_temp_new();
1160 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1162 tcg_temp_free(lo);
1163 if (unlikely(Rc(ctx->opcode) != 0)) {
1164 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1165 }
1166 }
1167
1168 /* mulhdu mulhdu. */
1169 static void gen_mulhdu(DisasContext *ctx)
1170 {
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178 }
1179
1180 /* mulld mulld. */
1181 static void gen_mulld(DisasContext *ctx)
1182 {
1183 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1184 cpu_gpr[rB(ctx->opcode)]);
1185 if (unlikely(Rc(ctx->opcode) != 0))
1186 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1187 }
1188
1189 /* mulldo mulldo. */
1190 static void gen_mulldo(DisasContext *ctx)
1191 {
1192 TCGv_i64 t0 = tcg_temp_new_i64();
1193 TCGv_i64 t1 = tcg_temp_new_i64();
1194
1195 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1196 cpu_gpr[rB(ctx->opcode)]);
1197 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1198
1199 tcg_gen_sari_i64(t0, t0, 63);
1200 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1201 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1202
1203 tcg_temp_free_i64(t0);
1204 tcg_temp_free_i64(t1);
1205
1206 if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1208 }
1209 }
1210 #endif
1211
1212 /* Common subf function */
1213 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1214 TCGv arg2, bool add_ca, bool compute_ca,
1215 bool compute_ov, bool compute_rc0)
1216 {
1217 TCGv t0 = ret;
1218
1219 if (compute_ca || compute_ov) {
1220 t0 = tcg_temp_new();
1221 }
1222
1223 if (compute_ca) {
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx)) {
1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
1229 TCGv inv1 = tcg_temp_new();
1230 TCGv t1 = tcg_temp_new();
1231 tcg_gen_not_tl(inv1, arg1);
1232 if (add_ca) {
1233 tcg_gen_add_tl(t0, arg2, cpu_ca);
1234 } else {
1235 tcg_gen_addi_tl(t0, arg2, 1);
1236 }
1237 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1238 tcg_gen_add_tl(t0, t0, inv1);
1239 tcg_temp_free(inv1);
1240 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1241 tcg_temp_free(t1);
1242 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1244 } else if (add_ca) {
1245 TCGv zero, inv1 = tcg_temp_new();
1246 tcg_gen_not_tl(inv1, arg1);
1247 zero = tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1249 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1250 tcg_temp_free(zero);
1251 tcg_temp_free(inv1);
1252 } else {
1253 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1254 tcg_gen_sub_tl(t0, arg2, arg1);
1255 }
1256 } else if (add_ca) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 tcg_gen_add_tl(t0, t0, cpu_ca);
1261 tcg_gen_subi_tl(t0, t0, 1);
1262 } else {
1263 tcg_gen_sub_tl(t0, arg2, arg1);
1264 }
1265
1266 if (compute_ov) {
1267 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1268 }
1269 if (unlikely(compute_rc0)) {
1270 gen_set_Rc0(ctx, t0);
1271 }
1272
1273 if (!TCGV_EQUAL(t0, ret)) {
1274 tcg_gen_mov_tl(ret, t0);
1275 tcg_temp_free(t0);
1276 }
1277 }
1278 /* Sub functions with Two operands functions */
1279 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1280 static void glue(gen_, name)(DisasContext *ctx) \
1281 { \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1285 }
1286 /* Sub functions with one operand and one immediate */
1287 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
1289 static void glue(gen_, name)(DisasContext *ctx) \
1290 { \
1291 TCGv t0 = tcg_const_tl(const_val); \
1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1295 tcg_temp_free(t0); \
1296 }
1297 /* subf subf. subfo subfo. */
1298 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1299 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1300 /* subfc subfc. subfco subfco. */
1301 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1302 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1303 /* subfe subfe. subfeo subfo. */
1304 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1305 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1306 /* subfme subfme. subfmeo subfmeo. */
1307 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1309 /* subfze subfze. subfzeo subfzeo.*/
1310 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1312
1313 /* subfic */
1314 static void gen_subfic(DisasContext *ctx)
1315 {
1316 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1317 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1318 c, 0, 1, 0, 0);
1319 tcg_temp_free(c);
1320 }
1321
1322 /* neg neg. nego nego. */
1323 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1324 {
1325 TCGv zero = tcg_const_tl(0);
1326 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1327 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1328 tcg_temp_free(zero);
1329 }
1330
1331 static void gen_neg(DisasContext *ctx)
1332 {
1333 gen_op_arith_neg(ctx, 0);
1334 }
1335
1336 static void gen_nego(DisasContext *ctx)
1337 {
1338 gen_op_arith_neg(ctx, 1);
1339 }
1340
1341 /*** Integer logical ***/
1342 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1343 static void glue(gen_, name)(DisasContext *ctx) \
1344 { \
1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
1347 if (unlikely(Rc(ctx->opcode) != 0)) \
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1349 }
1350
1351 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1352 static void glue(gen_, name)(DisasContext *ctx) \
1353 { \
1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1355 if (unlikely(Rc(ctx->opcode) != 0)) \
1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1357 }
1358
1359 /* and & and. */
1360 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1361 /* andc & andc. */
1362 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1363
1364 /* andi. */
1365 static void gen_andi_(DisasContext *ctx)
1366 {
1367 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1369 }
1370
1371 /* andis. */
1372 static void gen_andis_(DisasContext *ctx)
1373 {
1374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1376 }
1377
1378 /* cntlzw */
1379 static void gen_cntlzw(DisasContext *ctx)
1380 {
1381 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1384 }
1385 /* eqv & eqv. */
1386 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1387 /* extsb & extsb. */
1388 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1389 /* extsh & extsh. */
1390 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1391 /* nand & nand. */
1392 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1393 /* nor & nor. */
1394 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1395
1396 #if defined(TARGET_PPC64)
1397 static void gen_pause(DisasContext *ctx)
1398 {
1399 TCGv_i32 t0 = tcg_const_i32(0);
1400 tcg_gen_st_i32(t0, cpu_env,
1401 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1402 tcg_temp_free_i32(t0);
1403
1404 /* Stop translation, this gives other CPUs a chance to run */
1405 gen_exception_err(ctx, EXCP_HLT, 1);
1406 }
1407 #endif /* defined(TARGET_PPC64) */
1408
1409 /* or & or. */
1410 static void gen_or(DisasContext *ctx)
1411 {
1412 int rs, ra, rb;
1413
1414 rs = rS(ctx->opcode);
1415 ra = rA(ctx->opcode);
1416 rb = rB(ctx->opcode);
1417 /* Optimisation for mr. ri case */
1418 if (rs != ra || rs != rb) {
1419 if (rs != rb)
1420 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1421 else
1422 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1423 if (unlikely(Rc(ctx->opcode) != 0))
1424 gen_set_Rc0(ctx, cpu_gpr[ra]);
1425 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1426 gen_set_Rc0(ctx, cpu_gpr[rs]);
1427 #if defined(TARGET_PPC64)
1428 } else {
1429 int prio = 0;
1430
1431 switch (rs) {
1432 case 1:
1433 /* Set process priority to low */
1434 prio = 2;
1435 break;
1436 case 6:
1437 /* Set process priority to medium-low */
1438 prio = 3;
1439 break;
1440 case 2:
1441 /* Set process priority to normal */
1442 prio = 4;
1443 break;
1444 #if !defined(CONFIG_USER_ONLY)
1445 case 31:
1446 if (!ctx->pr) {
1447 /* Set process priority to very low */
1448 prio = 1;
1449 }
1450 break;
1451 case 5:
1452 if (!ctx->pr) {
1453 /* Set process priority to medium-hight */
1454 prio = 5;
1455 }
1456 break;
1457 case 3:
1458 if (!ctx->pr) {
1459 /* Set process priority to high */
1460 prio = 6;
1461 }
1462 break;
1463 case 7:
1464 if (ctx->hv && !ctx->pr) {
1465 /* Set process priority to very high */
1466 prio = 7;
1467 }
1468 break;
1469 #endif
1470 default:
1471 /* nop */
1472 break;
1473 }
1474 if (prio) {
1475 TCGv t0 = tcg_temp_new();
1476 gen_load_spr(t0, SPR_PPR);
1477 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1478 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1479 gen_store_spr(SPR_PPR, t0);
1480 tcg_temp_free(t0);
1481 /* Pause us out of TCG otherwise spin loops with smt_low
1482 * eat too much CPU and the kernel hangs
1483 */
1484 gen_pause(ctx);
1485 }
1486 #endif
1487 }
1488 }
1489 /* orc & orc. */
1490 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1491
1492 /* xor & xor. */
1493 static void gen_xor(DisasContext *ctx)
1494 {
1495 /* Optimisation for "set to zero" case */
1496 if (rS(ctx->opcode) != rB(ctx->opcode))
1497 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1498 else
1499 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1500 if (unlikely(Rc(ctx->opcode) != 0))
1501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1502 }
1503
1504 /* ori */
1505 static void gen_ori(DisasContext *ctx)
1506 {
1507 target_ulong uimm = UIMM(ctx->opcode);
1508
1509 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1510 return;
1511 }
1512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1513 }
1514
1515 /* oris */
1516 static void gen_oris(DisasContext *ctx)
1517 {
1518 target_ulong uimm = UIMM(ctx->opcode);
1519
1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
1523 }
1524 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1525 }
1526
1527 /* xori */
1528 static void gen_xori(DisasContext *ctx)
1529 {
1530 target_ulong uimm = UIMM(ctx->opcode);
1531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
1536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1537 }
1538
1539 /* xoris */
1540 static void gen_xoris(DisasContext *ctx)
1541 {
1542 target_ulong uimm = UIMM(ctx->opcode);
1543
1544 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1545 /* NOP */
1546 return;
1547 }
1548 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1549 }
1550
1551 /* popcntb : PowerPC 2.03 specification */
1552 static void gen_popcntb(DisasContext *ctx)
1553 {
1554 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555 }
1556
1557 static void gen_popcntw(DisasContext *ctx)
1558 {
1559 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1560 }
1561
1562 #if defined(TARGET_PPC64)
1563 /* popcntd: PowerPC 2.06 specification */
1564 static void gen_popcntd(DisasContext *ctx)
1565 {
1566 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1567 }
1568 #endif
1569
1570 /* prtyw: PowerPC 2.05 specification */
1571 static void gen_prtyw(DisasContext *ctx)
1572 {
1573 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1574 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1575 TCGv t0 = tcg_temp_new();
1576 tcg_gen_shri_tl(t0, rs, 16);
1577 tcg_gen_xor_tl(ra, rs, t0);
1578 tcg_gen_shri_tl(t0, ra, 8);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1581 tcg_temp_free(t0);
1582 }
1583
1584 #if defined(TARGET_PPC64)
1585 /* prtyd: PowerPC 2.05 specification */
1586 static void gen_prtyd(DisasContext *ctx)
1587 {
1588 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1589 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1590 TCGv t0 = tcg_temp_new();
1591 tcg_gen_shri_tl(t0, rs, 32);
1592 tcg_gen_xor_tl(ra, rs, t0);
1593 tcg_gen_shri_tl(t0, ra, 16);
1594 tcg_gen_xor_tl(ra, ra, t0);
1595 tcg_gen_shri_tl(t0, ra, 8);
1596 tcg_gen_xor_tl(ra, ra, t0);
1597 tcg_gen_andi_tl(ra, ra, 1);
1598 tcg_temp_free(t0);
1599 }
1600 #endif
1601
1602 #if defined(TARGET_PPC64)
1603 /* bpermd */
1604 static void gen_bpermd(DisasContext *ctx)
1605 {
1606 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1607 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1608 }
1609 #endif
1610
1611 #if defined(TARGET_PPC64)
1612 /* extsw & extsw. */
1613 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1614
1615 /* cntlzd */
1616 static void gen_cntlzd(DisasContext *ctx)
1617 {
1618 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1619 if (unlikely(Rc(ctx->opcode) != 0))
1620 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1621 }
1622 #endif
1623
1624 /*** Integer rotate ***/
1625
1626 /* rlwimi & rlwimi. */
1627 static void gen_rlwimi(DisasContext *ctx)
1628 {
1629 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1630 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1631 uint32_t sh = SH(ctx->opcode);
1632 uint32_t mb = MB(ctx->opcode);
1633 uint32_t me = ME(ctx->opcode);
1634
1635 if (sh == (31-me) && mb <= me) {
1636 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1637 } else {
1638 target_ulong mask;
1639 TCGv_i32 t0;
1640 TCGv t1;
1641
1642 #if defined(TARGET_PPC64)
1643 mb += 32;
1644 me += 32;
1645 #endif
1646 mask = MASK(mb, me);
1647
1648 t0 = tcg_temp_new_i32();
1649 t1 = tcg_temp_new();
1650 tcg_gen_trunc_tl_i32(t0, t_rs);
1651 tcg_gen_rotli_i32(t0, t0, sh);
1652 tcg_gen_extu_i32_tl(t1, t0);
1653 tcg_temp_free_i32(t0);
1654
1655 tcg_gen_andi_tl(t1, t1, mask);
1656 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1657 tcg_gen_or_tl(t_ra, t_ra, t1);
1658 tcg_temp_free(t1);
1659 }
1660 if (unlikely(Rc(ctx->opcode) != 0)) {
1661 gen_set_Rc0(ctx, t_ra);
1662 }
1663 }
1664
1665 /* rlwinm & rlwinm. */
1666 static void gen_rlwinm(DisasContext *ctx)
1667 {
1668 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1669 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1670 uint32_t sh = SH(ctx->opcode);
1671 uint32_t mb = MB(ctx->opcode);
1672 uint32_t me = ME(ctx->opcode);
1673
1674 if (mb == 0 && me == (31 - sh)) {
1675 tcg_gen_shli_tl(t_ra, t_rs, sh);
1676 tcg_gen_ext32u_tl(t_ra, t_ra);
1677 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1678 tcg_gen_ext32u_tl(t_ra, t_rs);
1679 tcg_gen_shri_tl(t_ra, t_ra, mb);
1680 } else {
1681 #if defined(TARGET_PPC64)
1682 mb += 32;
1683 me += 32;
1684 #endif
1685 if (sh == 0) {
1686 tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
1687 } else {
1688 TCGv_i32 t0 = tcg_temp_new_i32();
1689
1690 tcg_gen_trunc_tl_i32(t0, t_rs);
1691 tcg_gen_rotli_i32(t0, t0, sh);
1692 tcg_gen_andi_i32(t0, t0, MASK(mb, me));
1693 tcg_gen_extu_i32_tl(t_ra, t0);
1694 tcg_temp_free_i32(t0);
1695 }
1696 }
1697 if (unlikely(Rc(ctx->opcode) != 0)) {
1698 gen_set_Rc0(ctx, t_ra);
1699 }
1700 }
1701
1702 /* rlwnm & rlwnm. */
1703 static void gen_rlwnm(DisasContext *ctx)
1704 {
1705 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1706 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1707 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1708 uint32_t mb = MB(ctx->opcode);
1709 uint32_t me = ME(ctx->opcode);
1710 TCGv_i32 t0, t1;
1711
1712 #if defined(TARGET_PPC64)
1713 mb += 32;
1714 me += 32;
1715 #endif
1716
1717 t0 = tcg_temp_new_i32();
1718 t1 = tcg_temp_new_i32();
1719 tcg_gen_trunc_tl_i32(t0, t_rb);
1720 tcg_gen_trunc_tl_i32(t1, t_rs);
1721 tcg_gen_andi_i32(t0, t0, 0x1f);
1722 tcg_gen_rotl_i32(t1, t1, t0);
1723 tcg_temp_free_i32(t0);
1724
1725 tcg_gen_andi_i32(t1, t1, MASK(mb, me));
1726 tcg_gen_extu_i32_tl(t_ra, t1);
1727 tcg_temp_free_i32(t1);
1728
1729 if (unlikely(Rc(ctx->opcode) != 0)) {
1730 gen_set_Rc0(ctx, t_ra);
1731 }
1732 }
1733
1734 #if defined(TARGET_PPC64)
1735 #define GEN_PPC64_R2(name, opc1, opc2) \
1736 static void glue(gen_, name##0)(DisasContext *ctx) \
1737 { \
1738 gen_##name(ctx, 0); \
1739 } \
1740 \
1741 static void glue(gen_, name##1)(DisasContext *ctx) \
1742 { \
1743 gen_##name(ctx, 1); \
1744 }
1745 #define GEN_PPC64_R4(name, opc1, opc2) \
1746 static void glue(gen_, name##0)(DisasContext *ctx) \
1747 { \
1748 gen_##name(ctx, 0, 0); \
1749 } \
1750 \
1751 static void glue(gen_, name##1)(DisasContext *ctx) \
1752 { \
1753 gen_##name(ctx, 0, 1); \
1754 } \
1755 \
1756 static void glue(gen_, name##2)(DisasContext *ctx) \
1757 { \
1758 gen_##name(ctx, 1, 0); \
1759 } \
1760 \
1761 static void glue(gen_, name##3)(DisasContext *ctx) \
1762 { \
1763 gen_##name(ctx, 1, 1); \
1764 }
1765
1766 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1767 {
1768 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1769 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1770
1771 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1772 tcg_gen_shli_tl(t_ra, t_rs, sh);
1773 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1774 tcg_gen_shri_tl(t_ra, t_rs, mb);
1775 } else {
1776 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1777 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1778 }
1779 if (unlikely(Rc(ctx->opcode) != 0)) {
1780 gen_set_Rc0(ctx, t_ra);
1781 }
1782 }
1783
1784 /* rldicl - rldicl. */
1785 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1786 {
1787 uint32_t sh, mb;
1788
1789 sh = SH(ctx->opcode) | (shn << 5);
1790 mb = MB(ctx->opcode) | (mbn << 5);
1791 gen_rldinm(ctx, mb, 63, sh);
1792 }
1793 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1794
1795 /* rldicr - rldicr. */
1796 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1797 {
1798 uint32_t sh, me;
1799
1800 sh = SH(ctx->opcode) | (shn << 5);
1801 me = MB(ctx->opcode) | (men << 5);
1802 gen_rldinm(ctx, 0, me, sh);
1803 }
1804 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1805
1806 /* rldic - rldic. */
1807 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1808 {
1809 uint32_t sh, mb;
1810
1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
1813 gen_rldinm(ctx, mb, 63 - sh, sh);
1814 }
1815 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1816
1817 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1818 {
1819 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1820 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1821 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1822 TCGv t0;
1823
1824 t0 = tcg_temp_new();
1825 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1826 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1827 tcg_temp_free(t0);
1828
1829 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1830 if (unlikely(Rc(ctx->opcode) != 0)) {
1831 gen_set_Rc0(ctx, t_ra);
1832 }
1833 }
1834
1835 /* rldcl - rldcl. */
1836 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1837 {
1838 uint32_t mb;
1839
1840 mb = MB(ctx->opcode) | (mbn << 5);
1841 gen_rldnm(ctx, mb, 63);
1842 }
1843 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1844
1845 /* rldcr - rldcr. */
1846 static inline void gen_rldcr(DisasContext *ctx, int men)
1847 {
1848 uint32_t me;
1849
1850 me = MB(ctx->opcode) | (men << 5);
1851 gen_rldnm(ctx, 0, me);
1852 }
1853 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1854
1855 /* rldimi - rldimi. */
1856 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1857 {
1858 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1859 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1860 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1861 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1862 uint32_t me = 63 - sh;
1863
1864 if (mb <= me) {
1865 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1866 } else {
1867 target_ulong mask = MASK(mb, me);
1868 TCGv t1 = tcg_temp_new();
1869
1870 tcg_gen_rotli_tl(t1, t_rs, sh);
1871 tcg_gen_andi_tl(t1, t1, mask);
1872 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1873 tcg_gen_or_tl(t_ra, t_ra, t1);
1874 tcg_temp_free(t1);
1875 }
1876 if (unlikely(Rc(ctx->opcode) != 0)) {
1877 gen_set_Rc0(ctx, t_ra);
1878 }
1879 }
1880 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1881 #endif
1882
1883 /*** Integer shift ***/
1884
1885 /* slw & slw. */
1886 static void gen_slw(DisasContext *ctx)
1887 {
1888 TCGv t0, t1;
1889
1890 t0 = tcg_temp_new();
1891 /* AND rS with a mask that is 0 when rB >= 0x20 */
1892 #if defined(TARGET_PPC64)
1893 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1894 tcg_gen_sari_tl(t0, t0, 0x3f);
1895 #else
1896 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1897 tcg_gen_sari_tl(t0, t0, 0x1f);
1898 #endif
1899 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1900 t1 = tcg_temp_new();
1901 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1902 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1903 tcg_temp_free(t1);
1904 tcg_temp_free(t0);
1905 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1906 if (unlikely(Rc(ctx->opcode) != 0))
1907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1908 }
1909
1910 /* sraw & sraw. */
1911 static void gen_sraw(DisasContext *ctx)
1912 {
1913 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1914 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1915 if (unlikely(Rc(ctx->opcode) != 0))
1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1917 }
1918
1919 /* srawi & srawi. */
1920 static void gen_srawi(DisasContext *ctx)
1921 {
1922 int sh = SH(ctx->opcode);
1923 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1924 TCGv src = cpu_gpr[rS(ctx->opcode)];
1925 if (sh == 0) {
1926 tcg_gen_ext32s_tl(dst, src);
1927 tcg_gen_movi_tl(cpu_ca, 0);
1928 } else {
1929 TCGv t0;
1930 tcg_gen_ext32s_tl(dst, src);
1931 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1932 t0 = tcg_temp_new();
1933 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1934 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1935 tcg_temp_free(t0);
1936 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1937 tcg_gen_sari_tl(dst, dst, sh);
1938 }
1939 if (unlikely(Rc(ctx->opcode) != 0)) {
1940 gen_set_Rc0(ctx, dst);
1941 }
1942 }
1943
1944 /* srw & srw. */
1945 static void gen_srw(DisasContext *ctx)
1946 {
1947 TCGv t0, t1;
1948
1949 t0 = tcg_temp_new();
1950 /* AND rS with a mask that is 0 when rB >= 0x20 */
1951 #if defined(TARGET_PPC64)
1952 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1953 tcg_gen_sari_tl(t0, t0, 0x3f);
1954 #else
1955 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1956 tcg_gen_sari_tl(t0, t0, 0x1f);
1957 #endif
1958 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1959 tcg_gen_ext32u_tl(t0, t0);
1960 t1 = tcg_temp_new();
1961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1962 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1963 tcg_temp_free(t1);
1964 tcg_temp_free(t0);
1965 if (unlikely(Rc(ctx->opcode) != 0))
1966 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1967 }
1968
1969 #if defined(TARGET_PPC64)
1970 /* sld & sld. */
1971 static void gen_sld(DisasContext *ctx)
1972 {
1973 TCGv t0, t1;
1974
1975 t0 = tcg_temp_new();
1976 /* AND rS with a mask that is 0 when rB >= 0x40 */
1977 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1978 tcg_gen_sari_tl(t0, t0, 0x3f);
1979 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980 t1 = tcg_temp_new();
1981 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1982 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1983 tcg_temp_free(t1);
1984 tcg_temp_free(t0);
1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987 }
1988
1989 /* srad & srad. */
1990 static void gen_srad(DisasContext *ctx)
1991 {
1992 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1993 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1994 if (unlikely(Rc(ctx->opcode) != 0))
1995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1996 }
1997 /* sradi & sradi. */
1998 static inline void gen_sradi(DisasContext *ctx, int n)
1999 {
2000 int sh = SH(ctx->opcode) + (n << 5);
2001 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2002 TCGv src = cpu_gpr[rS(ctx->opcode)];
2003 if (sh == 0) {
2004 tcg_gen_mov_tl(dst, src);
2005 tcg_gen_movi_tl(cpu_ca, 0);
2006 } else {
2007 TCGv t0;
2008 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2009 t0 = tcg_temp_new();
2010 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2011 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2012 tcg_temp_free(t0);
2013 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2014 tcg_gen_sari_tl(dst, src, sh);
2015 }
2016 if (unlikely(Rc(ctx->opcode) != 0)) {
2017 gen_set_Rc0(ctx, dst);
2018 }
2019 }
2020
2021 static void gen_sradi0(DisasContext *ctx)
2022 {
2023 gen_sradi(ctx, 0);
2024 }
2025
2026 static void gen_sradi1(DisasContext *ctx)
2027 {
2028 gen_sradi(ctx, 1);
2029 }
2030
2031 /* srd & srd. */
2032 static void gen_srd(DisasContext *ctx)
2033 {
2034 TCGv t0, t1;
2035
2036 t0 = tcg_temp_new();
2037 /* AND rS with a mask that is 0 when rB >= 0x40 */
2038 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2039 tcg_gen_sari_tl(t0, t0, 0x3f);
2040 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2041 t1 = tcg_temp_new();
2042 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2043 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2044 tcg_temp_free(t1);
2045 tcg_temp_free(t0);
2046 if (unlikely(Rc(ctx->opcode) != 0))
2047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2048 }
2049 #endif
2050
2051 #if defined(TARGET_PPC64)
2052 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2053 {
2054 TCGv_i32 tmp = tcg_temp_new_i32();
2055 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2056 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2057 tcg_temp_free_i32(tmp);
2058 }
2059 #else
2060 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2061 {
2062 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2063 }
2064 #endif
2065
2066 /*** Floating-Point arithmetic ***/
2067 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2068 static void gen_f##name(DisasContext *ctx) \
2069 { \
2070 if (unlikely(!ctx->fpu_enabled)) { \
2071 gen_exception(ctx, POWERPC_EXCP_FPU); \
2072 return; \
2073 } \
2074 /* NIP cannot be restored if the memory exception comes from an helper */ \
2075 gen_update_nip(ctx, ctx->nip - 4); \
2076 gen_reset_fpstatus(); \
2077 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2078 cpu_fpr[rA(ctx->opcode)], \
2079 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2080 if (isfloat) { \
2081 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2082 cpu_fpr[rD(ctx->opcode)]); \
2083 } \
2084 if (set_fprf) { \
2085 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2086 } \
2087 if (unlikely(Rc(ctx->opcode) != 0)) { \
2088 gen_set_cr1_from_fpscr(ctx); \
2089 } \
2090 }
2091
2092 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2093 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2094 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2095
2096 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2097 static void gen_f##name(DisasContext *ctx) \
2098 { \
2099 if (unlikely(!ctx->fpu_enabled)) { \
2100 gen_exception(ctx, POWERPC_EXCP_FPU); \
2101 return; \
2102 } \
2103 /* NIP cannot be restored if the memory exception comes from an helper */ \
2104 gen_update_nip(ctx, ctx->nip - 4); \
2105 gen_reset_fpstatus(); \
2106 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2107 cpu_fpr[rA(ctx->opcode)], \
2108 cpu_fpr[rB(ctx->opcode)]); \
2109 if (isfloat) { \
2110 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2111 cpu_fpr[rD(ctx->opcode)]); \
2112 } \
2113 if (set_fprf) { \
2114 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2115 } \
2116 if (unlikely(Rc(ctx->opcode) != 0)) { \
2117 gen_set_cr1_from_fpscr(ctx); \
2118 } \
2119 }
2120 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2121 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2122 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2123
2124 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2125 static void gen_f##name(DisasContext *ctx) \
2126 { \
2127 if (unlikely(!ctx->fpu_enabled)) { \
2128 gen_exception(ctx, POWERPC_EXCP_FPU); \
2129 return; \
2130 } \
2131 /* NIP cannot be restored if the memory exception comes from an helper */ \
2132 gen_update_nip(ctx, ctx->nip - 4); \
2133 gen_reset_fpstatus(); \
2134 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2135 cpu_fpr[rA(ctx->opcode)], \
2136 cpu_fpr[rC(ctx->opcode)]); \
2137 if (isfloat) { \
2138 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2139 cpu_fpr[rD(ctx->opcode)]); \
2140 } \
2141 if (set_fprf) { \
2142 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2143 } \
2144 if (unlikely(Rc(ctx->opcode) != 0)) { \
2145 gen_set_cr1_from_fpscr(ctx); \
2146 } \
2147 }
2148 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2149 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2150 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2151
2152 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2153 static void gen_f##name(DisasContext *ctx) \
2154 { \
2155 if (unlikely(!ctx->fpu_enabled)) { \
2156 gen_exception(ctx, POWERPC_EXCP_FPU); \
2157 return; \
2158 } \
2159 /* NIP cannot be restored if the memory exception comes from an helper */ \
2160 gen_update_nip(ctx, ctx->nip - 4); \
2161 gen_reset_fpstatus(); \
2162 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2163 cpu_fpr[rB(ctx->opcode)]); \
2164 if (set_fprf) { \
2165 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2166 } \
2167 if (unlikely(Rc(ctx->opcode) != 0)) { \
2168 gen_set_cr1_from_fpscr(ctx); \
2169 } \
2170 }
2171
2172 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2173 static void gen_f##name(DisasContext *ctx) \
2174 { \
2175 if (unlikely(!ctx->fpu_enabled)) { \
2176 gen_exception(ctx, POWERPC_EXCP_FPU); \
2177 return; \
2178 } \
2179 /* NIP cannot be restored if the memory exception comes from an helper */ \
2180 gen_update_nip(ctx, ctx->nip - 4); \
2181 gen_reset_fpstatus(); \
2182 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2183 cpu_fpr[rB(ctx->opcode)]); \
2184 if (set_fprf) { \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2186 } \
2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2189 } \
2190 }
2191
2192 /* fadd - fadds */
2193 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2194 /* fdiv - fdivs */
2195 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2196 /* fmul - fmuls */
2197 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2198
2199 /* fre */
2200 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2201
2202 /* fres */
2203 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2204
2205 /* frsqrte */
2206 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2207
2208 /* frsqrtes */
2209 static void gen_frsqrtes(DisasContext *ctx)
2210 {
2211 if (unlikely(!ctx->fpu_enabled)) {
2212 gen_exception(ctx, POWERPC_EXCP_FPU);
2213 return;
2214 }
2215 /* NIP cannot be restored if the memory exception comes from an helper */
2216 gen_update_nip(ctx, ctx->nip - 4);
2217 gen_reset_fpstatus();
2218 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2219 cpu_fpr[rB(ctx->opcode)]);
2220 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2221 cpu_fpr[rD(ctx->opcode)]);
2222 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2223 if (unlikely(Rc(ctx->opcode) != 0)) {
2224 gen_set_cr1_from_fpscr(ctx);
2225 }
2226 }
2227
2228 /* fsel */
2229 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2230 /* fsub - fsubs */
2231 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2232 /* Optional: */
2233
2234 /* fsqrt */
2235 static void gen_fsqrt(DisasContext *ctx)
2236 {
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
2243 gen_reset_fpstatus();
2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2245 cpu_fpr[rB(ctx->opcode)]);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2247 if (unlikely(Rc(ctx->opcode) != 0)) {
2248 gen_set_cr1_from_fpscr(ctx);
2249 }
2250 }
2251
2252 static void gen_fsqrts(DisasContext *ctx)
2253 {
2254 if (unlikely(!ctx->fpu_enabled)) {
2255 gen_exception(ctx, POWERPC_EXCP_FPU);
2256 return;
2257 }
2258 /* NIP cannot be restored if the memory exception comes from an helper */
2259 gen_update_nip(ctx, ctx->nip - 4);
2260 gen_reset_fpstatus();
2261 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2262 cpu_fpr[rB(ctx->opcode)]);
2263 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2264 cpu_fpr[rD(ctx->opcode)]);
2265 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2266 if (unlikely(Rc(ctx->opcode) != 0)) {
2267 gen_set_cr1_from_fpscr(ctx);
2268 }
2269 }
2270
2271 /*** Floating-Point multiply-and-add ***/
2272 /* fmadd - fmadds */
2273 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2274 /* fmsub - fmsubs */
2275 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2276 /* fnmadd - fnmadds */
2277 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2278 /* fnmsub - fnmsubs */
2279 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2280
2281 /*** Floating-Point round & convert ***/
2282 /* fctiw */
2283 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2284 /* fctiwu */
2285 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2286 /* fctiwz */
2287 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2288 /* fctiwuz */
2289 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2290 /* frsp */
2291 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2292 /* fcfid */
2293 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2294 /* fcfids */
2295 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2296 /* fcfidu */
2297 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2298 /* fcfidus */
2299 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2300 /* fctid */
2301 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2302 /* fctidu */
2303 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2304 /* fctidz */
2305 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2306 /* fctidu */
2307 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2308
2309 /* frin */
2310 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2311 /* friz */
2312 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2313 /* frip */
2314 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2315 /* frim */
2316 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2317
2318 static void gen_ftdiv(DisasContext *ctx)
2319 {
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2325 cpu_fpr[rB(ctx->opcode)]);
2326 }
2327
2328 static void gen_ftsqrt(DisasContext *ctx)
2329 {
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2335 }
2336
2337
2338
2339 /*** Floating-Point compare ***/
2340
2341 /* fcmpo */
2342 static void gen_fcmpo(DisasContext *ctx)
2343 {
2344 TCGv_i32 crf;
2345 if (unlikely(!ctx->fpu_enabled)) {
2346 gen_exception(ctx, POWERPC_EXCP_FPU);
2347 return;
2348 }
2349 /* NIP cannot be restored if the memory exception comes from an helper */
2350 gen_update_nip(ctx, ctx->nip - 4);
2351 gen_reset_fpstatus();
2352 crf = tcg_const_i32(crfD(ctx->opcode));
2353 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2354 cpu_fpr[rB(ctx->opcode)], crf);
2355 tcg_temp_free_i32(crf);
2356 gen_helper_float_check_status(cpu_env);
2357 }
2358
2359 /* fcmpu */
2360 static void gen_fcmpu(DisasContext *ctx)
2361 {
2362 TCGv_i32 crf;
2363 if (unlikely(!ctx->fpu_enabled)) {
2364 gen_exception(ctx, POWERPC_EXCP_FPU);
2365 return;
2366 }
2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
2369 gen_reset_fpstatus();
2370 crf = tcg_const_i32(crfD(ctx->opcode));
2371 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2372 cpu_fpr[rB(ctx->opcode)], crf);
2373 tcg_temp_free_i32(crf);
2374 gen_helper_float_check_status(cpu_env);
2375 }
2376
2377 /*** Floating-point move ***/
2378 /* fabs */
2379 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2380 static void gen_fabs(DisasContext *ctx)
2381 {
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2387 ~(1ULL << 63));
2388 if (unlikely(Rc(ctx->opcode))) {
2389 gen_set_cr1_from_fpscr(ctx);
2390 }
2391 }
2392
2393 /* fmr - fmr. */
2394 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2395 static void gen_fmr(DisasContext *ctx)
2396 {
2397 if (unlikely(!ctx->fpu_enabled)) {
2398 gen_exception(ctx, POWERPC_EXCP_FPU);
2399 return;
2400 }
2401 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2402 if (unlikely(Rc(ctx->opcode))) {
2403 gen_set_cr1_from_fpscr(ctx);
2404 }
2405 }
2406
2407 /* fnabs */
2408 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2409 static void gen_fnabs(DisasContext *ctx)
2410 {
2411 if (unlikely(!ctx->fpu_enabled)) {
2412 gen_exception(ctx, POWERPC_EXCP_FPU);
2413 return;
2414 }
2415 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2416 1ULL << 63);
2417 if (unlikely(Rc(ctx->opcode))) {
2418 gen_set_cr1_from_fpscr(ctx);
2419 }
2420 }
2421
2422 /* fneg */
2423 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2424 static void gen_fneg(DisasContext *ctx)
2425 {
2426 if (unlikely(!ctx->fpu_enabled)) {
2427 gen_exception(ctx, POWERPC_EXCP_FPU);
2428 return;
2429 }
2430 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2431 1ULL << 63);
2432 if (unlikely(Rc(ctx->opcode))) {
2433 gen_set_cr1_from_fpscr(ctx);
2434 }
2435 }
2436
2437 /* fcpsgn: PowerPC 2.05 specification */
2438 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2439 static void gen_fcpsgn(DisasContext *ctx)
2440 {
2441 if (unlikely(!ctx->fpu_enabled)) {
2442 gen_exception(ctx, POWERPC_EXCP_FPU);
2443 return;
2444 }
2445 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2446 cpu_fpr[rB(ctx->opcode)], 0, 63);
2447 if (unlikely(Rc(ctx->opcode))) {
2448 gen_set_cr1_from_fpscr(ctx);
2449 }
2450 }
2451
2452 static void gen_fmrgew(DisasContext *ctx)
2453 {
2454 TCGv_i64 b0;
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 b0 = tcg_temp_new_i64();
2460 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2461 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2462 b0, 0, 32);
2463 tcg_temp_free_i64(b0);
2464 }
2465
2466 static void gen_fmrgow(DisasContext *ctx)
2467 {
2468 if (unlikely(!ctx->fpu_enabled)) {
2469 gen_exception(ctx, POWERPC_EXCP_FPU);
2470 return;
2471 }
2472 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2473 cpu_fpr[rB(ctx->opcode)],
2474 cpu_fpr[rA(ctx->opcode)],
2475 32, 32);
2476 }
2477
2478 /*** Floating-Point status & ctrl register ***/
2479
2480 /* mcrfs */
2481 static void gen_mcrfs(DisasContext *ctx)
2482 {
2483 TCGv tmp = tcg_temp_new();
2484 TCGv_i32 tmask;
2485 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2486 int bfa;
2487 int nibble;
2488 int shift;
2489
2490 if (unlikely(!ctx->fpu_enabled)) {
2491 gen_exception(ctx, POWERPC_EXCP_FPU);
2492 return;
2493 }
2494 bfa = crfS(ctx->opcode);
2495 nibble = 7 - bfa;
2496 shift = 4 * nibble;
2497 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2498 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2499 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2500 tcg_temp_free(tmp);
2501 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2502 /* Only the exception bits (including FX) should be cleared if read */
2503 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2504 /* FEX and VX need to be updated, so don't set fpscr directly */
2505 tmask = tcg_const_i32(1 << nibble);
2506 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2507 tcg_temp_free_i32(tmask);
2508 tcg_temp_free_i64(tnew_fpscr);
2509 }
2510
2511 /* mffs */
2512 static void gen_mffs(DisasContext *ctx)
2513 {
2514 if (unlikely(!ctx->fpu_enabled)) {
2515 gen_exception(ctx, POWERPC_EXCP_FPU);
2516 return;
2517 }
2518 gen_reset_fpstatus();
2519 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2520 if (unlikely(Rc(ctx->opcode))) {
2521 gen_set_cr1_from_fpscr(ctx);
2522 }
2523 }
2524
2525 /* mtfsb0 */
2526 static void gen_mtfsb0(DisasContext *ctx)
2527 {
2528 uint8_t crb;
2529
2530 if (unlikely(!ctx->fpu_enabled)) {
2531 gen_exception(ctx, POWERPC_EXCP_FPU);
2532 return;
2533 }
2534 crb = 31 - crbD(ctx->opcode);
2535 gen_reset_fpstatus();
2536 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2537 TCGv_i32 t0;
2538 /* NIP cannot be restored if the memory exception comes from an helper */
2539 gen_update_nip(ctx, ctx->nip - 4);
2540 t0 = tcg_const_i32(crb);
2541 gen_helper_fpscr_clrbit(cpu_env, t0);
2542 tcg_temp_free_i32(t0);
2543 }
2544 if (unlikely(Rc(ctx->opcode) != 0)) {
2545 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2546 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2547 }
2548 }
2549
2550 /* mtfsb1 */
2551 static void gen_mtfsb1(DisasContext *ctx)
2552 {
2553 uint8_t crb;
2554
2555 if (unlikely(!ctx->fpu_enabled)) {
2556 gen_exception(ctx, POWERPC_EXCP_FPU);
2557 return;
2558 }
2559 crb = 31 - crbD(ctx->opcode);
2560 gen_reset_fpstatus();
2561 /* XXX: we pretend we can only do IEEE floating-point computations */
2562 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2563 TCGv_i32 t0;
2564 /* NIP cannot be restored if the memory exception comes from an helper */
2565 gen_update_nip(ctx, ctx->nip - 4);
2566 t0 = tcg_const_i32(crb);
2567 gen_helper_fpscr_setbit(cpu_env, t0);
2568 tcg_temp_free_i32(t0);
2569 }
2570 if (unlikely(Rc(ctx->opcode) != 0)) {
2571 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2572 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2573 }
2574 /* We can raise a differed exception */
2575 gen_helper_float_check_status(cpu_env);
2576 }
2577
2578 /* mtfsf */
2579 static void gen_mtfsf(DisasContext *ctx)
2580 {
2581 TCGv_i32 t0;
2582 int flm, l, w;
2583
2584 if (unlikely(!ctx->fpu_enabled)) {
2585 gen_exception(ctx, POWERPC_EXCP_FPU);
2586 return;
2587 }
2588 flm = FPFLM(ctx->opcode);
2589 l = FPL(ctx->opcode);
2590 w = FPW(ctx->opcode);
2591 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2593 return;
2594 }
2595 /* NIP cannot be restored if the memory exception comes from an helper */
2596 gen_update_nip(ctx, ctx->nip - 4);
2597 gen_reset_fpstatus();
2598 if (l) {
2599 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2600 } else {
2601 t0 = tcg_const_i32(flm << (w * 8));
2602 }
2603 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2604 tcg_temp_free_i32(t0);
2605 if (unlikely(Rc(ctx->opcode) != 0)) {
2606 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2607 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2608 }
2609 /* We can raise a differed exception */
2610 gen_helper_float_check_status(cpu_env);
2611 }
2612
2613 /* mtfsfi */
2614 static void gen_mtfsfi(DisasContext *ctx)
2615 {
2616 int bf, sh, w;
2617 TCGv_i64 t0;
2618 TCGv_i32 t1;
2619
2620 if (unlikely(!ctx->fpu_enabled)) {
2621 gen_exception(ctx, POWERPC_EXCP_FPU);
2622 return;
2623 }
2624 w = FPW(ctx->opcode);
2625 bf = FPBF(ctx->opcode);
2626 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2627 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2628 return;
2629 }
2630 sh = (8 * w) + 7 - bf;
2631 /* NIP cannot be restored if the memory exception comes from an helper */
2632 gen_update_nip(ctx, ctx->nip - 4);
2633 gen_reset_fpstatus();
2634 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2635 t1 = tcg_const_i32(1 << sh);
2636 gen_helper_store_fpscr(cpu_env, t0, t1);
2637 tcg_temp_free_i64(t0);
2638 tcg_temp_free_i32(t1);
2639 if (unlikely(Rc(ctx->opcode) != 0)) {
2640 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2641 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2642 }
2643 /* We can raise a differed exception */
2644 gen_helper_float_check_status(cpu_env);
2645 }
2646
2647 /*** Addressing modes ***/
2648 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2649 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2650 target_long maskl)
2651 {
2652 target_long simm = SIMM(ctx->opcode);
2653
2654 simm &= ~maskl;
2655 if (rA(ctx->opcode) == 0) {
2656 if (NARROW_MODE(ctx)) {
2657 simm = (uint32_t)simm;
2658 }
2659 tcg_gen_movi_tl(EA, simm);
2660 } else if (likely(simm != 0)) {
2661 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2662 if (NARROW_MODE(ctx)) {
2663 tcg_gen_ext32u_tl(EA, EA);
2664 }
2665 } else {
2666 if (NARROW_MODE(ctx)) {
2667 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2668 } else {
2669 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2670 }
2671 }
2672 }
2673
2674 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2675 {
2676 if (rA(ctx->opcode) == 0) {
2677 if (NARROW_MODE(ctx)) {
2678 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2679 } else {
2680 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2681 }
2682 } else {
2683 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2684 if (NARROW_MODE(ctx)) {
2685 tcg_gen_ext32u_tl(EA, EA);
2686 }
2687 }
2688 }
2689
2690 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2691 {
2692 if (rA(ctx->opcode) == 0) {
2693 tcg_gen_movi_tl(EA, 0);
2694 } else if (NARROW_MODE(ctx)) {
2695 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2696 } else {
2697 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2698 }
2699 }
2700
2701 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2702 target_long val)
2703 {
2704 tcg_gen_addi_tl(ret, arg1, val);
2705 if (NARROW_MODE(ctx)) {
2706 tcg_gen_ext32u_tl(ret, ret);
2707 }
2708 }
2709
2710 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2711 {
2712 TCGLabel *l1 = gen_new_label();
2713 TCGv t0 = tcg_temp_new();
2714 TCGv_i32 t1, t2;
2715 /* NIP cannot be restored if the memory exception comes from an helper */
2716 gen_update_nip(ctx, ctx->nip - 4);
2717 tcg_gen_andi_tl(t0, EA, mask);
2718 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2719 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2720 t2 = tcg_const_i32(0);
2721 gen_helper_raise_exception_err(cpu_env, t1, t2);
2722 tcg_temp_free_i32(t1);
2723 tcg_temp_free_i32(t2);
2724 gen_set_label(l1);
2725 tcg_temp_free(t0);
2726 }
2727
2728 /*** Integer load ***/
2729 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2730 {
2731 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2732 }
2733
2734 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2735 {
2736 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2737 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2738 }
2739
2740 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2741 {
2742 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2743 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2744 }
2745
2746 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2747 {
2748 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2749 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2750 }
2751
2752 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2753 {
2754 TCGv tmp = tcg_temp_new();
2755 gen_qemu_ld32u(ctx, tmp, addr);
2756 tcg_gen_extu_tl_i64(val, tmp);
2757 tcg_temp_free(tmp);
2758 }
2759
2760 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2761 {
2762 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2763 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2764 }
2765
2766 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2767 {
2768 TCGv tmp = tcg_temp_new();
2769 gen_qemu_ld32s(ctx, tmp, addr);
2770 tcg_gen_ext_tl_i64(val, tmp);
2771 tcg_temp_free(tmp);
2772 }
2773
2774 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2775 {
2776 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2777 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2778 }
2779
2780 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2781 {
2782 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2783 }
2784
2785 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2786 {
2787 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2788 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2789 }
2790
2791 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2792 {
2793 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2794 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2795 }
2796
2797 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2798 {
2799 TCGv tmp = tcg_temp_new();
2800 tcg_gen_trunc_i64_tl(tmp, val);
2801 gen_qemu_st32(ctx, tmp, addr);
2802 tcg_temp_free(tmp);
2803 }
2804
2805 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2806 {
2807 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2808 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2809 }
2810
2811 #define GEN_LD(name, ldop, opc, type) \
2812 static void glue(gen_, name)(DisasContext *ctx) \
2813 { \
2814 TCGv EA; \
2815 gen_set_access_type(ctx, ACCESS_INT); \
2816 EA = tcg_temp_new(); \
2817 gen_addr_imm_index(ctx, EA, 0); \
2818 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2819 tcg_temp_free(EA); \
2820 }
2821
2822 #define GEN_LDU(name, ldop, opc, type) \
2823 static void glue(gen_, name##u)(DisasContext *ctx) \
2824 { \
2825 TCGv EA; \
2826 if (unlikely(rA(ctx->opcode) == 0 || \
2827 rA(ctx->opcode) == rD(ctx->opcode))) { \
2828 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2829 return; \
2830 } \
2831 gen_set_access_type(ctx, ACCESS_INT); \
2832 EA = tcg_temp_new(); \
2833 if (type == PPC_64B) \
2834 gen_addr_imm_index(ctx, EA, 0x03); \
2835 else \
2836 gen_addr_imm_index(ctx, EA, 0); \
2837 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2838 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2839 tcg_temp_free(EA); \
2840 }
2841
2842 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2843 static void glue(gen_, name##ux)(DisasContext *ctx) \
2844 { \
2845 TCGv EA; \
2846 if (unlikely(rA(ctx->opcode) == 0 || \
2847 rA(ctx->opcode) == rD(ctx->opcode))) { \
2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2849 return; \
2850 } \
2851 gen_set_access_type(ctx, ACCESS_INT); \
2852 EA = tcg_temp_new(); \
2853 gen_addr_reg_index(ctx, EA); \
2854 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2856 tcg_temp_free(EA); \
2857 }
2858
2859 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2860 static void glue(gen_, name##x)(DisasContext *ctx) \
2861 { \
2862 TCGv EA; \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 gen_addr_reg_index(ctx, EA); \
2866 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2867 tcg_temp_free(EA); \
2868 }
2869 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2870 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2871
2872 #define GEN_LDS(name, ldop, op, type) \
2873 GEN_LD(name, ldop, op | 0x20, type); \
2874 GEN_LDU(name, ldop, op | 0x21, type); \
2875 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2876 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2877
2878 /* lbz lbzu lbzux lbzx */
2879 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2880 /* lha lhau lhaux lhax */
2881 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2882 /* lhz lhzu lhzux lhzx */
2883 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2884 /* lwz lwzu lwzux lwzx */
2885 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2886 #if defined(TARGET_PPC64)
2887 /* lwaux */
2888 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2889 /* lwax */
2890 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2891 /* ldux */
2892 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2893 /* ldx */
2894 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2895
2896 static void gen_ld(DisasContext *ctx)
2897 {
2898 TCGv EA;
2899 if (Rc(ctx->opcode)) {
2900 if (unlikely(rA(ctx->opcode) == 0 ||
2901 rA(ctx->opcode) == rD(ctx->opcode))) {
2902 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2903 return;
2904 }
2905 }
2906 gen_set_access_type(ctx, ACCESS_INT);
2907 EA = tcg_temp_new();
2908 gen_addr_imm_index(ctx, EA, 0x03);
2909 if (ctx->opcode & 0x02) {
2910 /* lwa (lwau is undefined) */
2911 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2912 } else {
2913 /* ld - ldu */
2914 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2915 }
2916 if (Rc(ctx->opcode))
2917 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2918 tcg_temp_free(EA);
2919 }
2920
2921 /* lq */
2922 static void gen_lq(DisasContext *ctx)
2923 {
2924 int ra, rd;
2925 TCGv EA;
2926
2927 /* lq is a legal user mode instruction starting in ISA 2.07 */
2928 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2929 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2930
2931 if (!legal_in_user_mode && ctx->pr) {
2932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2933 return;
2934 }
2935
2936 if (!le_is_supported && ctx->le_mode) {
2937 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2938 return;
2939 }
2940
2941 ra = rA(ctx->opcode);
2942 rd = rD(ctx->opcode);
2943 if (unlikely((rd & 1) || rd == ra)) {
2944 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2945 return;
2946 }
2947
2948 gen_set_access_type(ctx, ACCESS_INT);
2949 EA = tcg_temp_new();
2950 gen_addr_imm_index(ctx, EA, 0x0F);
2951
2952 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2953 64-bit byteswap already. */
2954 if (unlikely(ctx->le_mode)) {
2955 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2956 gen_addr_add(ctx, EA, EA, 8);
2957 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2958 } else {
2959 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2960 gen_addr_add(ctx, EA, EA, 8);
2961 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2962 }
2963 tcg_temp_free(EA);
2964 }
2965 #endif
2966
2967 /*** Integer store ***/
2968 #define GEN_ST(name, stop, opc, type) \
2969 static void glue(gen_, name)(DisasContext *ctx) \
2970 { \
2971 TCGv EA; \
2972 gen_set_access_type(ctx, ACCESS_INT); \
2973 EA = tcg_temp_new(); \
2974 gen_addr_imm_index(ctx, EA, 0); \
2975 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2976 tcg_temp_free(EA); \
2977 }
2978
2979 #define GEN_STU(name, stop, opc, type) \
2980 static void glue(gen_, stop##u)(DisasContext *ctx) \
2981 { \
2982 TCGv EA; \
2983 if (unlikely(rA(ctx->opcode) == 0)) { \
2984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2985 return; \
2986 } \
2987 gen_set_access_type(ctx, ACCESS_INT); \
2988 EA = tcg_temp_new(); \
2989 if (type == PPC_64B) \
2990 gen_addr_imm_index(ctx, EA, 0x03); \
2991 else \
2992 gen_addr_imm_index(ctx, EA, 0); \
2993 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2994 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2995 tcg_temp_free(EA); \
2996 }
2997
2998 #define GEN_STUX(name, stop, opc2, opc3, type) \
2999 static void glue(gen_, name##ux)(DisasContext *ctx) \
3000 { \
3001 TCGv EA; \
3002 if (unlikely(rA(ctx->opcode) == 0)) { \
3003 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3004 return; \
3005 } \
3006 gen_set_access_type(ctx, ACCESS_INT); \
3007 EA = tcg_temp_new(); \
3008 gen_addr_reg_index(ctx, EA); \
3009 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3010 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3011 tcg_temp_free(EA); \
3012 }
3013
3014 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3015 static void glue(gen_, name##x)(DisasContext *ctx) \
3016 { \
3017 TCGv EA; \
3018 gen_set_access_type(ctx, ACCESS_INT); \
3019 EA = tcg_temp_new(); \
3020 gen_addr_reg_index(ctx, EA); \
3021 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3022 tcg_temp_free(EA); \
3023 }
3024 #define GEN_STX(name, stop, opc2, opc3, type) \
3025 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3026
3027 #define GEN_STS(name, stop, op, type) \
3028 GEN_ST(name, stop, op | 0x20, type); \
3029 GEN_STU(name, stop, op | 0x21, type); \
3030 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3031 GEN_STX(name, stop, 0x17, op | 0x00, type)
3032
3033 /* stb stbu stbux stbx */
3034 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3035 /* sth sthu sthux sthx */
3036 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3037 /* stw stwu stwux stwx */
3038 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3039 #if defined(TARGET_PPC64)
3040 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3041 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3042
3043 static void gen_std(DisasContext *ctx)
3044 {
3045 int rs;
3046 TCGv EA;
3047
3048 rs = rS(ctx->opcode);
3049 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3050 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3051 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3052
3053 if (!(ctx->insns_flags & PPC_64BX)) {
3054 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3055 }
3056
3057 if (!legal_in_user_mode && ctx->pr) {
3058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3059 return;
3060 }
3061
3062 if (!le_is_supported && ctx->le_mode) {
3063 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3064 return;
3065 }
3066
3067 if (unlikely(rs & 1)) {
3068 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3069 return;
3070 }
3071 gen_set_access_type(ctx, ACCESS_INT);
3072 EA = tcg_temp_new();
3073 gen_addr_imm_index(ctx, EA, 0x03);
3074
3075 /* We only need to swap high and low halves. gen_qemu_st64 does
3076 necessary 64-bit byteswap already. */
3077 if (unlikely(ctx->le_mode)) {
3078 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3079 gen_addr_add(ctx, EA, EA, 8);
3080 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3081 } else {
3082 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3083 gen_addr_add(ctx, EA, EA, 8);
3084 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3085 }
3086 tcg_temp_free(EA);
3087 } else {
3088 /* std / stdu*/
3089 if (Rc(ctx->opcode)) {
3090 if (unlikely(rA(ctx->opcode) == 0)) {
3091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3092 return;
3093 }
3094 }
3095 gen_set_access_type(ctx, ACCESS_INT);
3096 EA = tcg_temp_new();
3097 gen_addr_imm_index(ctx, EA, 0x03);
3098 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3099 if (Rc(ctx->opcode))
3100 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3101 tcg_temp_free(EA);
3102 }
3103 }
3104 #endif
3105 /*** Integer load and store with byte reverse ***/
3106
3107 /* lhbrx */
3108 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3109 {
3110 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3111 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3112 }
3113 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3114
3115 /* lwbrx */
3116 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3117 {
3118 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3119 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3120 }
3121 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3122
3123 #if defined(TARGET_PPC64)
3124 /* ldbrx */
3125 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3126 {
3127 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3128 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3129 }
3130 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3131 #endif /* TARGET_PPC64 */
3132
3133 /* sthbrx */
3134 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3135 {
3136 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3138 }
3139 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3140
3141 /* stwbrx */
3142 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3143 {
3144 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3145 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3146 }
3147 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3148
3149 #if defined(TARGET_PPC64)
3150 /* stdbrx */
3151 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3152 {
3153 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3154 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3155 }
3156 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3157 #endif /* TARGET_PPC64 */
3158
3159 /*** Integer load and store multiple ***/
3160
3161 /* lmw */
3162 static void gen_lmw(DisasContext *ctx)
3163 {
3164 TCGv t0;
3165 TCGv_i32 t1;
3166 gen_set_access_type(ctx, ACCESS_INT);
3167 /* NIP cannot be restored if the memory exception comes from an helper */
3168 gen_update_nip(ctx, ctx->nip - 4);
3169 t0 = tcg_temp_new();
3170 t1 = tcg_const_i32(rD(ctx->opcode));
3171 gen_addr_imm_index(ctx, t0, 0);
3172 gen_helper_lmw(cpu_env, t0, t1);
3173 tcg_temp_free(t0);
3174 tcg_temp_free_i32(t1);
3175 }
3176
3177 /* stmw */
3178 static void gen_stmw(DisasContext *ctx)
3179 {
3180 TCGv t0;
3181 TCGv_i32 t1;
3182 gen_set_access_type(ctx, ACCESS_INT);
3183 /* NIP cannot be restored if the memory exception comes from an helper */
3184 gen_update_nip(ctx, ctx->nip - 4);
3185 t0 = tcg_temp_new();
3186 t1 = tcg_const_i32(rS(ctx->opcode));
3187 gen_addr_imm_index(ctx, t0, 0);
3188 gen_helper_stmw(cpu_env, t0, t1);
3189 tcg_temp_free(t0);
3190 tcg_temp_free_i32(t1);
3191 }
3192
3193 /*** Integer load and store strings ***/
3194
3195 /* lswi */
3196 /* PowerPC32 specification says we must generate an exception if
3197 * rA is in the range of registers to be loaded.
3198 * In an other hand, IBM says this is valid, but rA won't be loaded.
3199 * For now, I'll follow the spec...
3200 */
3201 static void gen_lswi(DisasContext *ctx)
3202 {
3203 TCGv t0;
3204 TCGv_i32 t1, t2;
3205 int nb = NB(ctx->opcode);
3206 int start = rD(ctx->opcode);
3207 int ra = rA(ctx->opcode);
3208 int nr;
3209
3210 if (nb == 0)
3211 nb = 32;
3212 nr = (nb + 3) / 4;
3213 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3214 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3215 return;
3216 }
3217 gen_set_access_type(ctx, ACCESS_INT);
3218 /* NIP cannot be restored if the memory exception comes from an helper */
3219 gen_update_nip(ctx, ctx->nip - 4);
3220 t0 = tcg_temp_new();
3221 gen_addr_register(ctx, t0);
3222 t1 = tcg_const_i32(nb);
3223 t2 = tcg_const_i32(start);
3224 gen_helper_lsw(cpu_env, t0, t1, t2);
3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
3228 }
3229
3230 /* lswx */
3231 static void gen_lswx(DisasContext *ctx)
3232 {
3233 TCGv t0;
3234 TCGv_i32 t1, t2, t3;
3235 gen_set_access_type(ctx, ACCESS_INT);
3236 /* NIP cannot be restored if the memory exception comes from an helper */
3237 gen_update_nip(ctx, ctx->nip - 4);
3238 t0 = tcg_temp_new();
3239 gen_addr_reg_index(ctx, t0);
3240 t1 = tcg_const_i32(rD(ctx->opcode));
3241 t2 = tcg_const_i32(rA(ctx->opcode));
3242 t3 = tcg_const_i32(rB(ctx->opcode));
3243 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3244 tcg_temp_free(t0);
3245 tcg_temp_free_i32(t1);
3246 tcg_temp_free_i32(t2);
3247 tcg_temp_free_i32(t3);
3248 }
3249
3250 /* stswi */
3251 static void gen_stswi(DisasContext *ctx)
3252 {
3253 TCGv t0;
3254 TCGv_i32 t1, t2;
3255 int nb = NB(ctx->opcode);
3256 gen_set_access_type(ctx, ACCESS_INT);
3257 /* NIP cannot be restored if the memory exception comes from an helper */
3258 gen_update_nip(ctx, ctx->nip - 4);
3259 t0 = tcg_temp_new();
3260 gen_addr_register(ctx, t0);
3261 if (nb == 0)
3262 nb = 32;
3263 t1 = tcg_const_i32(nb);
3264 t2 = tcg_const_i32(rS(ctx->opcode));
3265 gen_helper_stsw(cpu_env, t0, t1, t2);
3266 tcg_temp_free(t0);
3267 tcg_temp_free_i32(t1);
3268 tcg_temp_free_i32(t2);
3269 }
3270
3271 /* stswx */
3272 static void gen_stswx(DisasContext *ctx)
3273 {
3274 TCGv t0;
3275 TCGv_i32 t1, t2;
3276 gen_set_access_type(ctx, ACCESS_INT);
3277 /* NIP cannot be restored if the memory exception comes from an helper */
3278 gen_update_nip(ctx, ctx->nip - 4);
3279 t0 = tcg_temp_new();
3280 gen_addr_reg_index(ctx, t0);
3281 t1 = tcg_temp_new_i32();
3282 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3283 tcg_gen_andi_i32(t1, t1, 0x7F);
3284 t2 = tcg_const_i32(rS(ctx->opcode));
3285 gen_helper_stsw(cpu_env, t0, t1, t2);
3286 tcg_temp_free(t0);
3287 tcg_temp_free_i32(t1);
3288 tcg_temp_free_i32(t2);
3289 }
3290
3291 /*** Memory synchronisation ***/
3292 /* eieio */
3293 static void gen_eieio(DisasContext *ctx)
3294 {
3295 }
3296
3297 #if !defined(CONFIG_USER_ONLY)
3298 static inline void gen_check_tlb_flush(DisasContext *ctx)
3299 {
3300 TCGv_i32 t;
3301 TCGLabel *l;
3302
3303 if (!ctx->lazy_tlb_flush) {
3304 return;
3305 }
3306 l = gen_new_label();
3307 t = tcg_temp_new_i32();
3308 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3309 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3310 gen_helper_check_tlb_flush(cpu_env);
3311 gen_set_label(l);
3312 tcg_temp_free_i32(t);
3313 }
3314 #else
3315 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3316 #endif
3317
3318 /* isync */
3319 static void gen_isync(DisasContext *ctx)
3320 {
3321 /*
3322 * We need to check for a pending TLB flush. This can only happen in
3323 * kernel mode however so check MSR_PR
3324 */
3325 if (!ctx->pr) {
3326 gen_check_tlb_flush(ctx);
3327 }
3328 gen_stop_exception(ctx);
3329 }
3330
3331 #define LARX(name, len, loadop) \
3332 static void gen_##name(DisasContext *ctx) \
3333 { \
3334 TCGv t0; \
3335 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3336 gen_set_access_type(ctx, ACCESS_RES); \
3337 t0 = tcg_temp_local_new(); \
3338 gen_addr_reg_index(ctx, t0); \
3339 if ((len) > 1) { \
3340 gen_check_align(ctx, t0, (len)-1); \
3341 } \
3342 gen_qemu_##loadop(ctx, gpr, t0); \
3343 tcg_gen_mov_tl(cpu_reserve, t0); \
3344 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3345 tcg_temp_free(t0); \
3346 }
3347
3348 /* lwarx */
3349 LARX(lbarx, 1, ld8u);
3350 LARX(lharx, 2, ld16u);
3351 LARX(lwarx, 4, ld32u);
3352
3353
3354 #if defined(CONFIG_USER_ONLY)
3355 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3356 int reg, int size)
3357 {
3358 TCGv t0 = tcg_temp_new();
3359 uint32_t save_exception = ctx->exception;
3360
3361 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3362 tcg_gen_movi_tl(t0, (size << 5) | reg);
3363 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3364 tcg_temp_free(t0);
3365 gen_update_nip(ctx, ctx->nip-4);
3366 ctx->exception = POWERPC_EXCP_BRANCH;
3367 gen_exception(ctx, POWERPC_EXCP_STCX);
3368 ctx->exception = save_exception;
3369 }
3370 #else
3371 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3372 int reg, int size)
3373 {
3374 TCGLabel *l1;
3375
3376 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3377 l1 = gen_new_label();
3378 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3379 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3380 #if defined(TARGET_PPC64)
3381 if (size == 8) {
3382 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3383 } else
3384 #endif
3385 if (size == 4) {
3386 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3387 } else if (size == 2) {
3388 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3389 #if defined(TARGET_PPC64)
3390 } else if (size == 16) {
3391 TCGv gpr1, gpr2 , EA8;
3392 if (unlikely(ctx->le_mode)) {
3393 gpr1 = cpu_gpr[reg+1];
3394 gpr2 = cpu_gpr[reg];
3395 } else {
3396 gpr1 = cpu_gpr[reg];
3397 gpr2 = cpu_gpr[reg+1];
3398 }
3399 gen_qemu_st64(ctx, gpr1, EA);
3400 EA8 = tcg_temp_local_new();
3401 gen_addr_add(ctx, EA8, EA, 8);
3402 gen_qemu_st64(ctx, gpr2, EA8);
3403 tcg_temp_free(EA8);
3404 #endif
3405 } else {
3406 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3407 }
3408 gen_set_label(l1);
3409 tcg_gen_movi_tl(cpu_reserve, -1);
3410 }
3411 #endif
3412
3413 #define STCX(name, len) \
3414 static void gen_##name(DisasContext *ctx) \
3415 { \
3416 TCGv t0; \
3417 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3418 gen_inval_exception(ctx, \
3419 POWERPC_EXCP_INVAL_INVAL); \
3420 return; \
3421 } \
3422 gen_set_access_type(ctx, ACCESS_RES); \
3423 t0 = tcg_temp_local_new(); \
3424 gen_addr_reg_index(ctx, t0); \
3425 if (len > 1) { \
3426 gen_check_align(ctx, t0, (len)-1); \
3427 } \
3428 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3429 tcg_temp_free(t0); \
3430 }
3431
3432 STCX(stbcx_, 1);
3433 STCX(sthcx_, 2);
3434 STCX(stwcx_, 4);
3435
3436 #if defined(TARGET_PPC64)
3437 /* ldarx */
3438 LARX(ldarx, 8, ld64);
3439
3440 /* lqarx */
3441 static void gen_lqarx(DisasContext *ctx)
3442 {
3443 TCGv EA;
3444 int rd = rD(ctx->opcode);
3445 TCGv gpr1, gpr2;
3446
3447 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3448 (rd == rB(ctx->opcode)))) {
3449 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3450 return;
3451 }
3452
3453 gen_set_access_type(ctx, ACCESS_RES);
3454 EA = tcg_temp_local_new();
3455 gen_addr_reg_index(ctx, EA);
3456 gen_check_align(ctx, EA, 15);
3457 if (unlikely(ctx->le_mode)) {
3458 gpr1 = cpu_gpr[rd+1];
3459 gpr2 = cpu_gpr[rd];
3460 } else {
3461 gpr1 = cpu_gpr[rd];
3462 gpr2 = cpu_gpr[rd+1];
3463 }
3464 gen_qemu_ld64(ctx, gpr1, EA);
3465 tcg_gen_mov_tl(cpu_reserve, EA);
3466
3467 gen_addr_add(ctx, EA, EA, 8);
3468 gen_qemu_ld64(ctx, gpr2, EA);
3469
3470 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3471 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3472
3473 tcg_temp_free(EA);
3474 }
3475
3476 /* stdcx. */
3477 STCX(stdcx_, 8);
3478 STCX(stqcx_, 16);
3479 #endif /* defined(TARGET_PPC64) */
3480
3481 /* sync */
3482 static void gen_sync(DisasContext *ctx)
3483 {
3484 uint32_t l = (ctx->opcode >> 21) & 3;
3485
3486 /*
3487 * We may need to check for a pending TLB flush.
3488 *
3489 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3490 *
3491 * Additionally, this can only happen in kernel mode however so
3492 * check MSR_PR as well.
3493 */
3494 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3495 gen_check_tlb_flush(ctx);
3496 }
3497 }
3498
3499 /* wait */
3500 static void gen_wait(DisasContext *ctx)
3501 {
3502 TCGv_i32 t0 = tcg_temp_new_i32();
3503 tcg_gen_st_i32(t0, cpu_env,
3504 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3505 tcg_temp_free_i32(t0);
3506 /* Stop translation, as the CPU is supposed to sleep from now */
3507 gen_exception_err(ctx, EXCP_HLT, 1);
3508 }
3509
3510 /*** Floating-point load ***/
3511 #define GEN_LDF(name, ldop, opc, type) \
3512 static void glue(gen_, name)(DisasContext *ctx) \
3513 { \
3514 TCGv EA; \
3515 if (unlikely(!ctx->fpu_enabled)) { \
3516 gen_exception(ctx, POWERPC_EXCP_FPU); \
3517 return; \
3518 } \
3519 gen_set_access_type(ctx, ACCESS_FLOAT); \
3520 EA = tcg_temp_new(); \
3521 gen_addr_imm_index(ctx, EA, 0); \
3522 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3523 tcg_temp_free(EA); \
3524 }
3525
3526 #define GEN_LDUF(name, ldop, opc, type) \
3527 static void glue(gen_, name##u)(DisasContext *ctx) \
3528 { \
3529 TCGv EA; \
3530 if (unlikely(!ctx->fpu_enabled)) { \
3531 gen_exception(ctx, POWERPC_EXCP_FPU); \
3532 return; \
3533 } \
3534 if (unlikely(rA(ctx->opcode) == 0)) { \
3535 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3536 return; \
3537 } \
3538 gen_set_access_type(ctx, ACCESS_FLOAT); \
3539 EA = tcg_temp_new(); \
3540 gen_addr_imm_index(ctx, EA, 0); \
3541 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3542 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3543 tcg_temp_free(EA); \
3544 }
3545
3546 #define GEN_LDUXF(name, ldop, opc, type) \
3547 static void glue(gen_, name##ux)(DisasContext *ctx) \
3548 { \
3549 TCGv EA; \
3550 if (unlikely(!ctx->fpu_enabled)) { \
3551 gen_exception(ctx, POWERPC_EXCP_FPU); \
3552 return; \
3553 } \
3554 if (unlikely(rA(ctx->opcode) == 0)) { \
3555 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3556 return; \
3557 } \
3558 gen_set_access_type(ctx, ACCESS_FLOAT); \
3559 EA = tcg_temp_new(); \
3560 gen_addr_reg_index(ctx, EA); \
3561 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3562 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3563 tcg_temp_free(EA); \
3564 }
3565
3566 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3567 static void glue(gen_, name##x)(DisasContext *ctx) \
3568 { \
3569 TCGv EA; \
3570 if (unlikely(!ctx->fpu_enabled)) { \
3571 gen_exception(ctx, POWERPC_EXCP_FPU); \
3572 return; \
3573 } \
3574 gen_set_access_type(ctx, ACCESS_FLOAT); \
3575 EA = tcg_temp_new(); \
3576 gen_addr_reg_index(ctx, EA); \
3577 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3578 tcg_temp_free(EA); \
3579 }
3580
3581 #define GEN_LDFS(name, ldop, op, type) \
3582 GEN_LDF(name, ldop, op | 0x20, type); \
3583 GEN_LDUF(name, ldop, op | 0x21, type); \
3584 GEN_LDUXF(name, ldop, op | 0x01, type); \
3585 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3586
3587 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3588 {
3589 TCGv t0 = tcg_temp_new();
3590 TCGv_i32 t1 = tcg_temp_new_i32();
3591 gen_qemu_ld32u(ctx, t0, arg2);
3592 tcg_gen_trunc_tl_i32(t1, t0);
3593 tcg_temp_free(t0);
3594 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3595 tcg_temp_free_i32(t1);
3596 }
3597
3598 /* lfd lfdu lfdux lfdx */
3599 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3600 /* lfs lfsu lfsux lfsx */
3601 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3602
3603 /* lfdp */
3604 static void gen_lfdp(DisasContext *ctx)
3605 {
3606 TCGv EA;
3607 if (unlikely(!ctx->fpu_enabled)) {
3608 gen_exception(ctx, POWERPC_EXCP_FPU);
3609 return;
3610 }
3611 gen_set_access_type(ctx, ACCESS_FLOAT);
3612 EA = tcg_temp_new();
3613 gen_addr_imm_index(ctx, EA, 0);
3614 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3615 64-bit byteswap already. */
3616 if (unlikely(ctx->le_mode)) {
3617 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3618 tcg_gen_addi_tl(EA, EA, 8);
3619 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3620 } else {
3621 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3622 tcg_gen_addi_tl(EA, EA, 8);
3623 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3624 }
3625 tcg_temp_free(EA);
3626 }
3627
3628 /* lfdpx */
3629 static void gen_lfdpx(DisasContext *ctx)
3630 {
3631 TCGv EA;
3632 if (unlikely(!ctx->fpu_enabled)) {
3633 gen_exception(ctx, POWERPC_EXCP_FPU);
3634 return;
3635 }
3636 gen_set_access_type(ctx, ACCESS_FLOAT);
3637 EA = tcg_temp_new();
3638 gen_addr_reg_index(ctx, EA);
3639 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3640 64-bit byteswap already. */
3641 if (unlikely(ctx->le_mode)) {
3642 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3643 tcg_gen_addi_tl(EA, EA, 8);
3644 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3645 } else {
3646 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3647 tcg_gen_addi_tl(EA, EA, 8);
3648 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3649 }
3650 tcg_temp_free(EA);
3651 }
3652
3653 /* lfiwax */
3654 static void gen_lfiwax(DisasContext *ctx)
3655 {
3656 TCGv EA;
3657 TCGv t0;
3658 if (unlikely(!ctx->fpu_enabled)) {
3659 gen_exception(ctx, POWERPC_EXCP_FPU);
3660 return;
3661 }
3662 gen_set_access_type(ctx, ACCESS_FLOAT);
3663 EA = tcg_temp_new();
3664 t0 = tcg_temp_new();
3665 gen_addr_reg_index(ctx, EA);
3666 gen_qemu_ld32s(ctx, t0, EA);
3667 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3668 tcg_temp_free(EA);
3669 tcg_temp_free(t0);
3670 }
3671
3672 /* lfiwzx */
3673 static void gen_lfiwzx(DisasContext *ctx)
3674 {
3675 TCGv EA;
3676 if (unlikely(!ctx->fpu_enabled)) {
3677 gen_exception(ctx, POWERPC_EXCP_FPU);
3678 return;
3679 }
3680 gen_set_access_type(ctx, ACCESS_FLOAT);
3681 EA = tcg_temp_new();
3682 gen_addr_reg_index(ctx, EA);
3683 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3684 tcg_temp_free(EA);
3685 }
3686 /*** Floating-point store ***/
3687 #define GEN_STF(name, stop, opc, type) \
3688 static void glue(gen_, name)(DisasContext *ctx) \
3689 { \
3690 TCGv EA; \
3691 if (unlikely(!ctx->fpu_enabled)) { \
3692 gen_exception(ctx, POWERPC_EXCP_FPU); \
3693 return; \
3694 } \
3695 gen_set_access_type(ctx, ACCESS_FLOAT); \
3696 EA = tcg_temp_new(); \
3697 gen_addr_imm_index(ctx, EA, 0); \
3698 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3699 tcg_temp_free(EA); \
3700 }
3701
3702 #define GEN_STUF(name, stop, opc, type) \
3703 static void glue(gen_, name##u)(DisasContext *ctx) \
3704 { \
3705 TCGv EA; \
3706 if (unlikely(!ctx->fpu_enabled)) { \
3707 gen_exception(ctx, POWERPC_EXCP_FPU); \
3708 return; \
3709 } \
3710 if (unlikely(rA(ctx->opcode) == 0)) { \
3711 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3712 return; \
3713 } \
3714 gen_set_access_type(ctx, ACCESS_FLOAT); \
3715 EA = tcg_temp_new(); \
3716 gen_addr_imm_index(ctx, EA, 0); \
3717 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3718 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3719 tcg_temp_free(EA); \
3720 }
3721
3722 #define GEN_STUXF(name, stop, opc, type) \
3723 static void glue(gen_, name##ux)(DisasContext *ctx) \
3724 { \
3725 TCGv EA; \
3726 if (unlikely(!ctx->fpu_enabled)) { \
3727 gen_exception(ctx, POWERPC_EXCP_FPU); \
3728 return; \
3729 } \
3730 if (unlikely(rA(ctx->opcode) == 0)) { \
3731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3732 return; \
3733 } \
3734 gen_set_access_type(ctx, ACCESS_FLOAT); \
3735 EA = tcg_temp_new(); \
3736 gen_addr_reg_index(ctx, EA); \
3737 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3738 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3739 tcg_temp_free(EA); \
3740 }
3741
3742 #define GEN_STXF(name, stop, opc2, opc3, type) \
3743 static void glue(gen_, name##x)(DisasContext *ctx) \
3744 { \
3745 TCGv EA; \
3746 if (unlikely(!ctx->fpu_enabled)) { \
3747 gen_exception(ctx, POWERPC_EXCP_FPU); \
3748 return; \
3749 } \
3750 gen_set_access_type(ctx, ACCESS_FLOAT); \
3751 EA = tcg_temp_new(); \
3752 gen_addr_reg_index(ctx, EA); \
3753 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3754 tcg_temp_free(EA); \
3755 }
3756
3757 #define GEN_STFS(name, stop, op, type) \
3758 GEN_STF(name, stop, op | 0x20, type); \
3759 GEN_STUF(name, stop, op | 0x21, type); \
3760 GEN_STUXF(name, stop, op | 0x01, type); \
3761 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3762
3763 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3764 {
3765 TCGv_i32 t0 = tcg_temp_new_i32();
3766 TCGv t1 = tcg_temp_new();
3767 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3768 tcg_gen_extu_i32_tl(t1, t0);
3769 tcg_temp_free_i32(t0);
3770 gen_qemu_st32(ctx, t1, arg2);
3771 tcg_temp_free(t1);
3772 }
3773
3774 /* stfd stfdu stfdux stfdx */
3775 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3776 /* stfs stfsu stfsux stfsx */
3777 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3778
3779 /* stfdp */
3780 static void gen_stfdp(DisasContext *ctx)
3781 {
3782 TCGv EA;
3783 if (unlikely(!ctx->fpu_enabled)) {
3784 gen_exception(ctx, POWERPC_EXCP_FPU);
3785 return;
3786 }
3787 gen_set_access_type(ctx, ACCESS_FLOAT);
3788 EA = tcg_temp_new();
3789 gen_addr_imm_index(ctx, EA, 0);
3790 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3791 64-bit byteswap already. */
3792 if (unlikely(ctx->le_mode)) {
3793 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3794 tcg_gen_addi_tl(EA, EA, 8);
3795 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3796 } else {
3797 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3798 tcg_gen_addi_tl(EA, EA, 8);
3799 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3800 }
3801 tcg_temp_free(EA);
3802 }
3803
3804 /* stfdpx */
3805 static void gen_stfdpx(DisasContext *ctx)
3806 {
3807 TCGv EA;
3808 if (unlikely(!ctx->fpu_enabled)) {
3809 gen_exception(ctx, POWERPC_EXCP_FPU);
3810 return;
3811 }
3812 gen_set_access_type(ctx, ACCESS_FLOAT);
3813 EA = tcg_temp_new();
3814 gen_addr_reg_index(ctx, EA);
3815 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3816 64-bit byteswap already. */
3817 if (unlikely(ctx->le_mode)) {
3818 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3819 tcg_gen_addi_tl(EA, EA, 8);
3820 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3821 } else {
3822 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3823 tcg_gen_addi_tl(EA, EA, 8);
3824 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3825 }
3826 tcg_temp_free(EA);
3827 }
3828
3829 /* Optional: */
3830 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3831 {
3832 TCGv t0 = tcg_temp_new();
3833 tcg_gen_trunc_i64_tl(t0, arg1),
3834 gen_qemu_st32(ctx, t0, arg2);
3835 tcg_temp_free(t0);
3836 }
3837 /* stfiwx */
3838 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3839
3840 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3841 {
3842 #if defined(TARGET_PPC64)
3843 if (ctx->has_cfar)
3844 tcg_gen_movi_tl(cpu_cfar, nip);
3845 #endif
3846 }
3847
3848 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3849 {
3850 if (unlikely(ctx->singlestep_enabled)) {
3851 return false;
3852 }
3853
3854 #ifndef CONFIG_USER_ONLY
3855 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3856 #else
3857 return true;
3858 #endif
3859 }
3860
3861 /*** Branch ***/
3862 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3863 {
3864 if (NARROW_MODE(ctx)) {
3865 dest = (uint32_t) dest;
3866 }
3867 if (use_goto_tb(ctx, dest)) {
3868 tcg_gen_goto_tb(n);
3869 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3870 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3871 } else {
3872 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3873 if (unlikely(ctx->singlestep_enabled)) {
3874 if ((ctx->singlestep_enabled &
3875 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3876 (ctx->exception == POWERPC_EXCP_BRANCH ||
3877 ctx->exception == POWERPC_EXCP_TRACE)) {
3878 target_ulong tmp = ctx->nip;
3879 ctx->nip = dest;
3880 gen_exception(ctx, POWERPC_EXCP_TRACE);
3881 ctx->nip = tmp;
3882 }
3883 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3884 gen_debug_exception(ctx);
3885 }
3886 }
3887 tcg_gen_exit_tb(0);
3888 }
3889 }
3890
3891 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3892 {
3893 if (NARROW_MODE(ctx)) {
3894 nip = (uint32_t)nip;
3895 }
3896 tcg_gen_movi_tl(cpu_lr, nip);
3897 }
3898
3899 /* b ba bl bla */
3900 static void gen_b(DisasContext *ctx)
3901 {
3902 target_ulong li, target;
3903
3904 ctx->exception = POWERPC_EXCP_BRANCH;
3905 /* sign extend LI */
3906 li = LI(ctx->opcode);
3907 li = (li ^ 0x02000000) - 0x02000000;
3908 if (likely(AA(ctx->opcode) == 0)) {
3909 target = ctx->nip + li - 4;
3910 } else {
3911 target = li;
3912 }
3913 if (LK(ctx->opcode)) {
3914 gen_setlr(ctx, ctx->nip);
3915 }
3916 gen_update_cfar(ctx, ctx->nip);
3917 gen_goto_tb(ctx, 0, target);
3918 }
3919
3920 #define BCOND_IM 0
3921 #define BCOND_LR 1
3922 #define BCOND_CTR 2
3923 #define BCOND_TAR 3
3924
3925 static inline void gen_bcond(DisasContext *ctx, int type)
3926 {
3927 uint32_t bo = BO(ctx->opcode);
3928 TCGLabel *l1;
3929 TCGv target;
3930
3931 ctx->exception = POWERPC_EXCP_BRANCH;
3932 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3933 target = tcg_temp_local_new();
3934 if (type == BCOND_CTR)
3935 tcg_gen_mov_tl(target, cpu_ctr);
3936 else if (type == BCOND_TAR)
3937 gen_load_spr(target, SPR_TAR);
3938 else
3939 tcg_gen_mov_tl(target, cpu_lr);
3940 } else {
3941 TCGV_UNUSED(target);
3942 }
3943 if (LK(ctx->opcode))
3944 gen_setlr(ctx, ctx->nip);
3945 l1 = gen_new_label();
3946 if ((bo & 0x4) == 0) {
3947 /* Decrement and test CTR */
3948 TCGv temp = tcg_temp_new();
3949 if (unlikely(type == BCOND_CTR)) {
3950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3951 return;
3952 }
3953 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3954 if (NARROW_MODE(ctx)) {
3955 tcg_gen_ext32u_tl(temp, cpu_ctr);
3956 } else {
3957 tcg_gen_mov_tl(temp, cpu_ctr);
3958 }
3959 if (bo & 0x2) {
3960 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3961 } else {
3962 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3963 }
3964 tcg_temp_free(temp);
3965 }
3966 if ((bo & 0x10) == 0) {
3967 /* Test CR */
3968 uint32_t bi = BI(ctx->opcode);
3969 uint32_t mask = 0x08 >> (bi & 0x03);
3970 TCGv_i32 temp = tcg_temp_new_i32();
3971
3972 if (bo & 0x8) {
3973 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3974 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3975 } else {
3976 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3977 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3978 }
3979 tcg_temp_free_i32(temp);
3980 }
3981 gen_update_cfar(ctx, ctx->nip);
3982 if (type == BCOND_IM) {
3983 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3984 if (likely(AA(ctx->opcode) == 0)) {
3985 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3986 } else {
3987 gen_goto_tb(ctx, 0, li);
3988 }
3989 gen_set_label(l1);
3990 gen_goto_tb(ctx, 1, ctx->nip);
3991 } else {
3992 if (NARROW_MODE(ctx)) {
3993 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3994 } else {
3995 tcg_gen_andi_tl(cpu_nip, target, ~3);
3996 }
3997 tcg_gen_exit_tb(0);
3998 gen_set_label(l1);
3999 gen_update_nip(ctx, ctx->nip);
4000 tcg_gen_exit_tb(0);
4001 }
4002 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4003 tcg_temp_free(target);
4004 }
4005 }
4006
4007 static void gen_bc(DisasContext *ctx)
4008 {
4009 gen_bcond(ctx, BCOND_IM);
4010 }
4011
4012 static void gen_bcctr(DisasContext *ctx)
4013 {
4014 gen_bcond(ctx, BCOND_CTR);
4015 }
4016
4017 static void gen_bclr(DisasContext *ctx)
4018 {
4019 gen_bcond(ctx, BCOND_LR);
4020 }
4021
4022 static void gen_bctar(DisasContext *ctx)
4023 {
4024 gen_bcond(ctx, BCOND_TAR);
4025 }
4026
4027 /*** Condition register logical ***/
4028 #define GEN_CRLOGIC(name, tcg_op, opc) \
4029 static void glue(gen_, name)(DisasContext *ctx) \
4030 { \
4031 uint8_t bitmask; \
4032 int sh; \
4033 TCGv_i32 t0, t1; \
4034 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4035 t0 = tcg_temp_new_i32(); \
4036 if (sh > 0) \
4037 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4038 else if (sh < 0) \
4039 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4040 else \
4041 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4042 t1 = tcg_temp_new_i32(); \
4043 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4044 if (sh > 0) \
4045 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4046 else if (sh < 0) \
4047 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4048 else \
4049 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4050 tcg_op(t0, t0, t1); \
4051 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4052 tcg_gen_andi_i32(t0, t0, bitmask); \
4053 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4054 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4055 tcg_temp_free_i32(t0); \
4056 tcg_temp_free_i32(t1); \
4057 }
4058
4059 /* crand */
4060 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4061 /* crandc */
4062 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4063 /* creqv */
4064 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4065 /* crnand */
4066 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4067 /* crnor */
4068 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4069 /* cror */
4070 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4071 /* crorc */
4072 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4073 /* crxor */
4074 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4075
4076 /* mcrf */
4077 static void gen_mcrf(DisasContext *ctx)
4078 {
4079 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4080 }
4081
4082 /*** System linkage ***/
4083
4084 /* rfi (supervisor only) */
4085 static void gen_rfi(DisasContext *ctx)
4086 {
4087 #if defined(CONFIG_USER_ONLY)
4088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4089 #else
4090 /* Restore CPU state */
4091 if (unlikely(ctx->pr)) {
4092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4093 return;
4094 }
4095 gen_update_cfar(ctx, ctx->nip);
4096 gen_helper_rfi(cpu_env);
4097 gen_sync_exception(ctx);
4098 #endif
4099 }
4100
4101 #if defined(TARGET_PPC64)
4102 static void gen_rfid(DisasContext *ctx)
4103 {
4104 #if defined(CONFIG_USER_ONLY)
4105 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4106 #else
4107 /* Restore CPU state */
4108 if (unlikely(ctx->pr)) {
4109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4110 return;
4111 }
4112 gen_update_cfar(ctx, ctx->nip);
4113 gen_helper_rfid(cpu_env);
4114 gen_sync_exception(ctx);
4115 #endif
4116 }
4117
4118 static void gen_hrfid(DisasContext *ctx)
4119 {
4120 #if defined(CONFIG_USER_ONLY)
4121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4122 #else
4123 /* Restore CPU state */
4124 if (unlikely(ctx->pr || !ctx->hv)) {
4125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4126 return;
4127 }
4128 gen_helper_hrfid(cpu_env);
4129 gen_sync_exception(ctx);
4130 #endif
4131 }
4132 #endif
4133
4134 /* sc */
4135 #if defined(CONFIG_USER_ONLY)
4136 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4137 #else
4138 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4139 #endif
4140 static void gen_sc(DisasContext *ctx)
4141 {
4142 uint32_t lev;
4143
4144 lev = (ctx->opcode >> 5) & 0x7F;
4145 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4146 }
4147
4148 /*** Trap ***/
4149
4150 /* tw */
4151 static void gen_tw(DisasContext *ctx)
4152 {
4153 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4154 /* Update the nip since this might generate a trap exception */
4155 gen_update_nip(ctx, ctx->nip);
4156 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4157 t0);
4158 tcg_temp_free_i32(t0);
4159 }
4160
4161 /* twi */
4162 static void gen_twi(DisasContext *ctx)
4163 {
4164 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4165 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4166 /* Update the nip since this might generate a trap exception */
4167 gen_update_nip(ctx, ctx->nip);
4168 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4169 tcg_temp_free(t0);
4170 tcg_temp_free_i32(t1);
4171 }
4172
4173 #if defined(TARGET_PPC64)
4174 /* td */
4175 static void gen_td(DisasContext *ctx)
4176 {
4177 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4178 /* Update the nip since this might generate a trap exception */
4179 gen_update_nip(ctx, ctx->nip);
4180 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4181 t0);
4182 tcg_temp_free_i32(t0);
4183 }
4184
4185 /* tdi */
4186 static void gen_tdi(DisasContext *ctx)
4187 {
4188 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4189 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4190 /* Update the nip since this might generate a trap exception */
4191 gen_update_nip(ctx, ctx->nip);
4192 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4193 tcg_temp_free(t0);
4194 tcg_temp_free_i32(t1);
4195 }
4196 #endif
4197
4198 /*** Processor control ***/
4199
4200 static void gen_read_xer(TCGv dst)
4201 {
4202 TCGv t0 = tcg_temp_new();
4203 TCGv t1 = tcg_temp_new();
4204 TCGv t2 = tcg_temp_new();
4205 tcg_gen_mov_tl(dst, cpu_xer);
4206 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4207 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4208 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4209 tcg_gen_or_tl(t0, t0, t1);
4210 tcg_gen_or_tl(dst, dst, t2);
4211 tcg_gen_or_tl(dst, dst, t0);
4212 tcg_temp_free(t0);
4213 tcg_temp_free(t1);
4214 tcg_temp_free(t2);
4215 }
4216
4217 static void gen_write_xer(TCGv src)
4218 {
4219 tcg_gen_andi_tl(cpu_xer, src,
4220 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4221 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4222 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4223 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4224 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4225 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4226 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4227 }
4228
4229 /* mcrxr */
4230 static void gen_mcrxr(DisasContext *ctx)
4231 {
4232 TCGv_i32 t0 = tcg_temp_new_i32();
4233 TCGv_i32 t1 = tcg_temp_new_i32();
4234 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4235
4236 tcg_gen_trunc_tl_i32(t0, cpu_so);
4237 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4238 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4239 tcg_gen_shli_i32(t0, t0, 3);
4240 tcg_gen_shli_i32(t1, t1, 2);
4241 tcg_gen_shli_i32(dst, dst, 1);
4242 tcg_gen_or_i32(dst, dst, t0);
4243 tcg_gen_or_i32(dst, dst, t1);
4244 tcg_temp_free_i32(t0);
4245 tcg_temp_free_i32(t1);
4246
4247 tcg_gen_movi_tl(cpu_so, 0);
4248 tcg_gen_movi_tl(cpu_ov, 0);
4249 tcg_gen_movi_tl(cpu_ca, 0);
4250 }
4251
4252 /* mfcr mfocrf */
4253 static void gen_mfcr(DisasContext *ctx)
4254 {
4255 uint32_t crm, crn;
4256
4257 if (likely(ctx->opcode & 0x00100000)) {
4258 crm = CRM(ctx->opcode);
4259 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4260 crn = ctz32 (crm);
4261 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4262 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4263 cpu_gpr[rD(ctx->opcode)], crn * 4);
4264 }
4265 } else {
4266 TCGv_i32 t0 = tcg_temp_new_i32();
4267 tcg_gen_mov_i32(t0, cpu_crf[0]);
4268 tcg_gen_shli_i32(t0, t0, 4);
4269 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4270 tcg_gen_shli_i32(t0, t0, 4);
4271 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4272 tcg_gen_shli_i32(t0, t0, 4);
4273 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4274 tcg_gen_shli_i32(t0, t0, 4);
4275 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4276 tcg_gen_shli_i32(t0, t0, 4);
4277 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4278 tcg_gen_shli_i32(t0, t0, 4);
4279 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4280 tcg_gen_shli_i32(t0, t0, 4);
4281 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4282 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4283 tcg_temp_free_i32(t0);
4284 }
4285 }
4286
4287 /* mfmsr */
4288 static void gen_mfmsr(DisasContext *ctx)
4289 {
4290 #if defined(CONFIG_USER_ONLY)
4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4292 #else
4293 if (unlikely(ctx->pr)) {
4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4295 return;
4296 }
4297 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4298 #endif
4299 }
4300
4301 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4302 {
4303 #if 0
4304 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4305 printf("ERROR: try to access SPR %d !\n", sprn);
4306 #endif
4307 }
4308 #define SPR_NOACCESS (&spr_noaccess)
4309
4310 /* mfspr */
4311 static inline void gen_op_mfspr(DisasContext *ctx)
4312 {
4313 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4314 uint32_t sprn = SPR(ctx->opcode);
4315
4316 #if defined(CONFIG_USER_ONLY)
4317 read_cb = ctx->spr_cb[sprn].uea_read;
4318 #else
4319 if (ctx->pr) {
4320 read_cb = ctx->spr_cb[sprn].uea_read;
4321 } else if (ctx->hv) {
4322 read_cb = ctx->spr_cb[sprn].hea_read;
4323 } else {
4324 read_cb = ctx->spr_cb[sprn].oea_read;
4325 }
4326 #endif
4327 if (likely(read_cb != NULL)) {
4328 if (likely(read_cb != SPR_NOACCESS)) {
4329 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4330 } else {
4331 /* Privilege exception */
4332 /* This is a hack to avoid warnings when running Linux:
4333 * this OS breaks the PowerPC virtualisation model,
4334 * allowing userland application to read the PVR
4335 */
4336 if (sprn != SPR_PVR) {
4337 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4338 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4339 if (qemu_log_separate()) {
4340 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4341 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4342 }
4343 }
4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4345 }
4346 } else {
4347 /* Not defined */
4348 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4349 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4350 if (qemu_log_separate()) {
4351 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4352 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4353 }
4354 /* Only generate an exception in user space, otherwise this is a nop */
4355 if (ctx->pr) {
4356 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4357 }
4358 }
4359 }
4360
4361 static void gen_mfspr(DisasContext *ctx)
4362 {
4363 gen_op_mfspr(ctx);
4364 }
4365
4366 /* mftb */
4367 static void gen_mftb(DisasContext *ctx)
4368 {
4369 gen_op_mfspr(ctx);
4370 }
4371
4372 /* mtcrf mtocrf*/
4373 static void gen_mtcrf(DisasContext *ctx)
4374 {
4375 uint32_t crm, crn;
4376
4377 crm = CRM(ctx->opcode);
4378 if (likely((ctx->opcode & 0x00100000))) {
4379 if (crm && ((crm & (crm - 1)) == 0)) {
4380 TCGv_i32 temp = tcg_temp_new_i32();
4381 crn = ctz32 (crm);
4382 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4383 tcg_gen_shri_i32(temp, temp, crn * 4);
4384 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4385 tcg_temp_free_i32(temp);
4386 }
4387 } else {
4388 TCGv_i32 temp = tcg_temp_new_i32();
4389 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4390 for (crn = 0 ; crn < 8 ; crn++) {
4391 if (crm & (1 << crn)) {
4392 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4393 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4394 }
4395 }
4396 tcg_temp_free_i32(temp);
4397 }
4398 }
4399
4400 /* mtmsr */
4401 #if defined(TARGET_PPC64)
4402 static void gen_mtmsrd(DisasContext *ctx)
4403 {
4404 #if defined(CONFIG_USER_ONLY)
4405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4406 #else
4407 if (unlikely(ctx->pr)) {
4408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4409 return;
4410 }
4411 if (ctx->opcode & 0x00010000) {
4412 /* Special form that does not need any synchronisation */
4413 TCGv t0 = tcg_temp_new();
4414 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4415 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4416 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4417 tcg_temp_free(t0);
4418 } else {
4419 /* XXX: we need to update nip before the store
4420 * if we enter power saving mode, we will exit the loop
4421 * directly from ppc_store_msr
4422 */
4423 gen_update_nip(ctx, ctx->nip);
4424 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4425 /* Must stop the translation as machine state (may have) changed */
4426 /* Note that mtmsr is not always defined as context-synchronizing */
4427 gen_stop_exception(ctx);
4428 }
4429 #endif
4430 }
4431 #endif
4432
4433 static void gen_mtmsr(DisasContext *ctx)
4434 {
4435 #if defined(CONFIG_USER_ONLY)
4436 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4437 #else
4438 if (unlikely(ctx->pr)) {
4439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4440 return;
4441 }
4442 if (ctx->opcode & 0x00010000) {
4443 /* Special form that does not need any synchronisation */
4444 TCGv t0 = tcg_temp_new();
4445 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4446 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4447 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4448 tcg_temp_free(t0);
4449 } else {
4450 TCGv msr = tcg_temp_new();
4451
4452 /* XXX: we need to update nip before the store
4453 * if we enter power saving mode, we will exit the loop
4454 * directly from ppc_store_msr
4455 */
4456 gen_update_nip(ctx, ctx->nip);
4457 #if defined(TARGET_PPC64)
4458 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4459 #else
4460 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4461 #endif
4462 gen_helper_store_msr(cpu_env, msr);
4463 tcg_temp_free(msr);
4464 /* Must stop the translation as machine state (may have) changed */
4465 /* Note that mtmsr is not always defined as context-synchronizing */
4466 gen_stop_exception(ctx);
4467 }
4468 #endif
4469 }
4470
4471 /* mtspr */
4472 static void gen_mtspr(DisasContext *ctx)
4473 {
4474 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4475 uint32_t sprn = SPR(ctx->opcode);
4476
4477 #if defined(CONFIG_USER_ONLY)
4478 write_cb = ctx->spr_cb[sprn].uea_write;
4479 #else
4480 if (ctx->pr) {
4481 write_cb = ctx->spr_cb[sprn].uea_write;
4482 } else if (ctx->hv) {
4483 write_cb = ctx->spr_cb[sprn].hea_write;
4484 } else {
4485 write_cb = ctx->spr_cb[sprn].oea_write;
4486 }
4487 #endif
4488 if (likely(write_cb != NULL)) {
4489 if (likely(write_cb != SPR_NOACCESS)) {
4490 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4491 } else {
4492 /* Privilege exception */
4493 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4494 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4495 if (qemu_log_separate()) {
4496 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4497 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4498 }
4499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4500 }
4501 } else {
4502 /* Not defined */
4503 if (qemu_log_separate()) {
4504 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4505 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4506 }
4507 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4508 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4509
4510 /* Only generate an exception in user space, otherwise this is a nop */
4511 if (ctx->pr) {
4512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4513 }
4514 }
4515 }
4516
4517 /*** Cache management ***/
4518
4519 /* dcbf */
4520 static void gen_dcbf(DisasContext *ctx)
4521 {
4522 /* XXX: specification says this is treated as a load by the MMU */
4523 TCGv t0;
4524 gen_set_access_type(ctx, ACCESS_CACHE);
4525 t0 = tcg_temp_new();
4526 gen_addr_reg_index(ctx, t0);
4527 gen_qemu_ld8u(ctx, t0, t0);
4528 tcg_temp_free(t0);
4529 }
4530
4531 /* dcbi (Supervisor only) */
4532 static void gen_dcbi(DisasContext *ctx)
4533 {
4534 #if defined(CONFIG_USER_ONLY)
4535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4536 #else
4537 TCGv EA, val;
4538 if (unlikely(ctx->pr)) {
4539 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4540 return;
4541 }
4542 EA = tcg_temp_new();
4543 gen_set_access_type(ctx, ACCESS_CACHE);
4544 gen_addr_reg_index(ctx, EA);
4545 val = tcg_temp_new();
4546 /* XXX: specification says this should be treated as a store by the MMU */
4547 gen_qemu_ld8u(ctx, val, EA);
4548 gen_qemu_st8(ctx, val, EA);
4549 tcg_temp_free(val);
4550 tcg_temp_free(EA);
4551 #endif
4552 }
4553
4554 /* dcdst */
4555 static void gen_dcbst(DisasContext *ctx)
4556 {
4557 /* XXX: specification say this is treated as a load by the MMU */
4558 TCGv t0;
4559 gen_set_access_type(ctx, ACCESS_CACHE);
4560 t0 = tcg_temp_new();
4561 gen_addr_reg_index(ctx, t0);
4562 gen_qemu_ld8u(ctx, t0, t0);
4563 tcg_temp_free(t0);
4564 }
4565
4566 /* dcbt */
4567 static void gen_dcbt(DisasContext *ctx)
4568 {
4569 /* interpreted as no-op */
4570 /* XXX: specification say this is treated as a load by the MMU
4571 * but does not generate any exception
4572 */
4573 }
4574
4575 /* dcbtst */
4576 static void gen_dcbtst(DisasContext *ctx)
4577 {
4578 /* interpreted as no-op */
4579 /* XXX: specification say this is treated as a load by the MMU
4580 * but does not generate any exception
4581 */
4582 }
4583
4584 /* dcbtls */
4585 static void gen_dcbtls(DisasContext *ctx)
4586 {
4587 /* Always fails locking the cache */
4588 TCGv t0 = tcg_temp_new();
4589 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4590 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4591 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4592 tcg_temp_free(t0);
4593 }
4594
4595 /* dcbz */
4596 static void gen_dcbz(DisasContext *ctx)
4597 {
4598 TCGv tcgv_addr;
4599 TCGv_i32 tcgv_is_dcbzl;
4600 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4601
4602 gen_set_access_type(ctx, ACCESS_CACHE);
4603 /* NIP cannot be restored if the memory exception comes from an helper */
4604 gen_update_nip(ctx, ctx->nip - 4);
4605 tcgv_addr = tcg_temp_new();
4606 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4607
4608 gen_addr_reg_index(ctx, tcgv_addr);
4609 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4610
4611 tcg_temp_free(tcgv_addr);
4612 tcg_temp_free_i32(tcgv_is_dcbzl);
4613 }
4614
4615 /* dst / dstt */
4616 static void gen_dst(DisasContext *ctx)
4617 {
4618 if (rA(ctx->opcode) == 0) {
4619 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4620 } else {
4621 /* interpreted as no-op */
4622 }
4623 }
4624
4625 /* dstst /dststt */
4626 static void gen_dstst(DisasContext *ctx)
4627 {
4628 if (rA(ctx->opcode) == 0) {
4629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4630 } else {
4631 /* interpreted as no-op */
4632 }
4633
4634 }
4635
4636 /* dss / dssall */
4637 static void gen_dss(DisasContext *ctx)
4638 {
4639 /* interpreted as no-op */
4640 }
4641
4642 /* icbi */
4643 static void gen_icbi(DisasContext *ctx)
4644 {
4645 TCGv t0;
4646 gen_set_access_type(ctx, ACCESS_CACHE);
4647 /* NIP cannot be restored if the memory exception comes from an helper */
4648 gen_update_nip(ctx, ctx->nip - 4);
4649 t0 = tcg_temp_new();
4650 gen_addr_reg_index(ctx, t0);
4651 gen_helper_icbi(cpu_env, t0);
4652 tcg_temp_free(t0);
4653 }
4654
4655 /* Optional: */
4656 /* dcba */
4657 static void gen_dcba(DisasContext *ctx)
4658 {
4659 /* interpreted as no-op */
4660 /* XXX: specification say this is treated as a store by the MMU
4661 * but does not generate any exception
4662 */
4663 }
4664
4665 /*** Segment register manipulation ***/
4666 /* Supervisor only: */
4667
4668 /* mfsr */
4669 static void gen_mfsr(DisasContext *ctx)
4670 {
4671 #if defined(CONFIG_USER_ONLY)
4672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4673 #else
4674 TCGv t0;
4675 if (unlikely(ctx->pr)) {
4676 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4677 return;
4678 }
4679 t0 = tcg_const_tl(SR(ctx->opcode));
4680 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4681 tcg_temp_free(t0);
4682 #endif
4683 }
4684
4685 /* mfsrin */
4686 static void gen_mfsrin(DisasContext *ctx)
4687 {
4688 #if defined(CONFIG_USER_ONLY)
4689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4690 #else
4691 TCGv t0;
4692 if (unlikely(ctx->pr)) {
4693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4694 return;
4695 }
4696 t0 = tcg_temp_new();
4697 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4698 tcg_gen_andi_tl(t0, t0, 0xF);
4699 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4700 tcg_temp_free(t0);
4701 #endif
4702 }
4703
4704 /* mtsr */
4705 static void gen_mtsr(DisasContext *ctx)
4706 {
4707 #if defined(CONFIG_USER_ONLY)
4708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4709 #else
4710 TCGv t0;
4711 if (unlikely(ctx->pr)) {
4712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4713 return;
4714 }
4715 t0 = tcg_const_tl(SR(ctx->opcode));
4716 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4717 tcg_temp_free(t0);
4718 #endif
4719 }
4720
4721 /* mtsrin */
4722 static void gen_mtsrin(DisasContext *ctx)
4723 {
4724 #if defined(CONFIG_USER_ONLY)
4725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4726 #else
4727 TCGv t0;
4728 if (unlikely(ctx->pr)) {
4729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4730 return;
4731 }
4732 t0 = tcg_temp_new();
4733 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4734 tcg_gen_andi_tl(t0, t0, 0xF);
4735 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4736 tcg_temp_free(t0);
4737 #endif
4738 }
4739
4740 #if defined(TARGET_PPC64)
4741 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4742
4743 /* mfsr */
4744 static void gen_mfsr_64b(DisasContext *ctx)
4745 {
4746 #if defined(CONFIG_USER_ONLY)
4747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4748 #else
4749 TCGv t0;
4750 if (unlikely(ctx->pr)) {
4751 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4752 return;
4753 }
4754 t0 = tcg_const_tl(SR(ctx->opcode));
4755 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4756 tcg_temp_free(t0);
4757 #endif
4758 }
4759
4760 /* mfsrin */
4761 static void gen_mfsrin_64b(DisasContext *ctx)
4762 {
4763 #if defined(CONFIG_USER_ONLY)
4764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4765 #else
4766 TCGv t0;
4767 if (unlikely(ctx->pr)) {
4768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4769 return;
4770 }
4771 t0 = tcg_temp_new();
4772 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4773 tcg_gen_andi_tl(t0, t0, 0xF);
4774 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4775 tcg_temp_free(t0);
4776 #endif
4777 }
4778
4779 /* mtsr */
4780 static void gen_mtsr_64b(DisasContext *ctx)
4781 {
4782 #if defined(CONFIG_USER_ONLY)
4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4784 #else
4785 TCGv t0;
4786 if (unlikely(ctx->pr)) {
4787 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4788 return;
4789 }
4790 t0 = tcg_const_tl(SR(ctx->opcode));
4791 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4792 tcg_temp_free(t0);
4793 #endif
4794 }
4795
4796 /* mtsrin */
4797 static void gen_mtsrin_64b(DisasContext *ctx)
4798 {
4799 #if defined(CONFIG_USER_ONLY)
4800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4801 #else
4802 TCGv t0;
4803 if (unlikely(ctx->pr)) {
4804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4805 return;
4806 }
4807 t0 = tcg_temp_new();
4808 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4809 tcg_gen_andi_tl(t0, t0, 0xF);
4810 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4811 tcg_temp_free(t0);
4812 #endif
4813 }
4814
4815 /* slbmte */
4816 static void gen_slbmte(DisasContext *ctx)
4817 {
4818 #if defined(CONFIG_USER_ONLY)
4819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4820 #else
4821 if (unlikely(ctx->pr)) {
4822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4823 return;
4824 }
4825 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4826 cpu_gpr[rS(ctx->opcode)]);
4827 #endif
4828 }
4829
4830 static void gen_slbmfee(DisasContext *ctx)
4831 {
4832 #if defined(CONFIG_USER_ONLY)
4833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4834 #else
4835 if (unlikely(ctx->pr)) {
4836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4837 return;
4838 }
4839 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4840 cpu_gpr[rB(ctx->opcode)]);
4841 #endif
4842 }
4843
4844 static void gen_slbmfev(DisasContext *ctx)
4845 {
4846 #if defined(CONFIG_USER_ONLY)
4847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4848 #else
4849 if (unlikely(ctx->pr)) {
4850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4851 return;
4852 }
4853 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4854 cpu_gpr[rB(ctx->opcode)]);
4855 #endif
4856 }
4857
4858 static void gen_slbfee_(DisasContext *ctx)
4859 {
4860 #if defined(CONFIG_USER_ONLY)
4861 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4862 #else
4863 TCGLabel *l1, *l2;
4864
4865 if (unlikely(ctx->pr)) {
4866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4867 return;
4868 }
4869 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4870 cpu_gpr[rB(ctx->opcode)]);
4871 l1 = gen_new_label();
4872 l2 = gen_new_label();
4873 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4874 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4875 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4876 tcg_gen_br(l2);
4877 gen_set_label(l1);
4878 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4879 gen_set_label(l2);
4880 #endif
4881 }
4882 #endif /* defined(TARGET_PPC64) */
4883
4884 /*** Lookaside buffer management ***/
4885 /* Optional & supervisor only: */
4886
4887 /* tlbia */
4888 static void gen_tlbia(DisasContext *ctx)
4889 {
4890 #if defined(CONFIG_USER_ONLY)
4891 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4892 #else
4893 if (unlikely(ctx->pr || !ctx->hv)) {
4894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4895 return;
4896 }
4897 gen_helper_tlbia(cpu_env);
4898 #endif
4899 }
4900
4901 /* tlbiel */
4902 static void gen_tlbiel(DisasContext *ctx)
4903 {
4904 #if defined(CONFIG_USER_ONLY)
4905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4906 #else
4907 if (unlikely(ctx->pr)) {
4908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4909 return;
4910 }
4911 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4912 #endif
4913 }
4914
4915 /* tlbie */
4916 static void gen_tlbie(DisasContext *ctx)
4917 {
4918 #if defined(CONFIG_USER_ONLY)
4919 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4920 #else
4921 if (unlikely(ctx->pr || !ctx->hv)) {
4922 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4923 return;
4924 }
4925 if (NARROW_MODE(ctx)) {
4926 TCGv t0 = tcg_temp_new();
4927 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4928 gen_helper_tlbie(cpu_env, t0);
4929 tcg_temp_free(t0);
4930 } else {
4931 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4932 }
4933 #endif
4934 }
4935
4936 /* tlbsync */
4937 static void gen_tlbsync(DisasContext *ctx)
4938 {
4939 #if defined(CONFIG_USER_ONLY)
4940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4941 #else
4942 if (unlikely(ctx->pr || !ctx->hv)) {
4943 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4944 return;
4945 }
4946 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4947 * embedded however needs to deal with tlbsync. We don't try to be
4948 * fancy and swallow the overhead of checking for both.
4949 */
4950 gen_check_tlb_flush(ctx);
4951 #endif
4952 }
4953
4954 #if defined(TARGET_PPC64)
4955 /* slbia */
4956 static void gen_slbia(DisasContext *ctx)
4957 {
4958 #if defined(CONFIG_USER_ONLY)
4959 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4960 #else
4961 if (unlikely(ctx->pr)) {
4962 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4963 return;
4964 }
4965 gen_helper_slbia(cpu_env);
4966 #endif
4967 }
4968
4969 /* slbie */
4970 static void gen_slbie(DisasContext *ctx)
4971 {
4972 #if defined(CONFIG_USER_ONLY)
4973 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4974 #else
4975 if (unlikely(ctx->pr)) {
4976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4977 return;
4978 }
4979 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4980 #endif
4981 }
4982 #endif
4983
4984 /*** External control ***/
4985 /* Optional: */
4986
4987 /* eciwx */
4988 static void gen_eciwx(DisasContext *ctx)
4989 {
4990 TCGv t0;
4991 /* Should check EAR[E] ! */
4992 gen_set_access_type(ctx, ACCESS_EXT);
4993 t0 = tcg_temp_new();
4994 gen_addr_reg_index(ctx, t0);
4995 gen_check_align(ctx, t0, 0x03);
4996 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4997 tcg_temp_free(t0);
4998 }
4999
5000 /* ecowx */
5001 static void gen_ecowx(DisasContext *ctx)
5002 {
5003 TCGv t0;
5004 /* Should check EAR[E] ! */
5005 gen_set_access_type(ctx, ACCESS_EXT);
5006 t0 = tcg_temp_new();
5007 gen_addr_reg_index(ctx, t0);
5008 gen_check_align(ctx, t0, 0x03);
5009 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5010 tcg_temp_free(t0);
5011 }
5012
5013 /* PowerPC 601 specific instructions */
5014
5015 /* abs - abs. */
5016 static void gen_abs(DisasContext *ctx)
5017 {
5018 TCGLabel *l1 = gen_new_label();
5019 TCGLabel *l2 = gen_new_label();
5020 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5021 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5022 tcg_gen_br(l2);
5023 gen_set_label(l1);
5024 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5025 gen_set_label(l2);
5026 if (unlikely(Rc(ctx->opcode) != 0))
5027 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5028 }
5029
5030 /* abso - abso. */
5031 static void gen_abso(DisasContext *ctx)
5032 {
5033 TCGLabel *l1 = gen_new_label();
5034 TCGLabel *l2 = gen_new_label();
5035 TCGLabel *l3 = gen_new_label();
5036 /* Start with XER OV disabled, the most likely case */
5037 tcg_gen_movi_tl(cpu_ov, 0);
5038 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5039 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5040 tcg_gen_movi_tl(cpu_ov, 1);
5041 tcg_gen_movi_tl(cpu_so, 1);
5042 tcg_gen_br(l2);
5043 gen_set_label(l1);
5044 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5045 tcg_gen_br(l3);
5046 gen_set_label(l2);
5047 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5048 gen_set_label(l3);
5049 if (unlikely(Rc(ctx->opcode) != 0))
5050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5051 }
5052
5053 /* clcs */
5054 static void gen_clcs(DisasContext *ctx)
5055 {
5056 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5057 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5058 tcg_temp_free_i32(t0);
5059 /* Rc=1 sets CR0 to an undefined state */
5060 }
5061
5062 /* div - div. */
5063 static void gen_div(DisasContext *ctx)
5064 {
5065 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5066 cpu_gpr[rB(ctx->opcode)]);
5067 if (unlikely(Rc(ctx->opcode) != 0))
5068 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5069 }
5070
5071 /* divo - divo. */
5072 static void gen_divo(DisasContext *ctx)
5073 {
5074 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5075 cpu_gpr[rB(ctx->opcode)]);
5076 if (unlikely(Rc(ctx->opcode) != 0))
5077 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5078 }
5079
5080 /* divs - divs. */
5081 static void gen_divs(DisasContext *ctx)
5082 {
5083 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5084 cpu_gpr[rB(ctx->opcode)]);
5085 if (unlikely(Rc(ctx->opcode) != 0))
5086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5087 }
5088
5089 /* divso - divso. */
5090 static void gen_divso(DisasContext *ctx)
5091 {
5092 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5093 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5094 if (unlikely(Rc(ctx->opcode) != 0))
5095 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5096 }
5097
5098 /* doz - doz. */
5099 static void gen_doz(DisasContext *ctx)
5100 {
5101 TCGLabel *l1 = gen_new_label();
5102 TCGLabel *l2 = gen_new_label();
5103 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5104 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5105 tcg_gen_br(l2);
5106 gen_set_label(l1);
5107 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5108 gen_set_label(l2);
5109 if (unlikely(Rc(ctx->opcode) != 0))
5110 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5111 }
5112
5113 /* dozo - dozo. */
5114 static void gen_dozo(DisasContext *ctx)
5115 {
5116 TCGLabel *l1 = gen_new_label();
5117 TCGLabel *l2 = gen_new_label();
5118 TCGv t0 = tcg_temp_new();
5119 TCGv t1 = tcg_temp_new();
5120 TCGv t2 = tcg_temp_new();
5121 /* Start with XER OV disabled, the most likely case */
5122 tcg_gen_movi_tl(cpu_ov, 0);
5123 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5124 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5125 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5126 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5127 tcg_gen_andc_tl(t1, t1, t2);
5128 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5129 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5130 tcg_gen_movi_tl(cpu_ov, 1);
5131 tcg_gen_movi_tl(cpu_so, 1);
5132 tcg_gen_br(l2);
5133 gen_set_label(l1);
5134 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5135 gen_set_label(l2);
5136 tcg_temp_free(t0);
5137 tcg_temp_free(t1);
5138 tcg_temp_free(t2);
5139 if (unlikely(Rc(ctx->opcode) != 0))
5140 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5141 }
5142
5143 /* dozi */
5144 static void gen_dozi(DisasContext *ctx)
5145 {
5146 target_long simm = SIMM(ctx->opcode);
5147 TCGLabel *l1 = gen_new_label();
5148 TCGLabel *l2 = gen_new_label();
5149 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5150 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5151 tcg_gen_br(l2);
5152 gen_set_label(l1);
5153 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5154 gen_set_label(l2);
5155 if (unlikely(Rc(ctx->opcode) != 0))
5156 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5157 }
5158
5159 /* lscbx - lscbx. */
5160 static void gen_lscbx(DisasContext *ctx)
5161 {
5162 TCGv t0 = tcg_temp_new();
5163 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5164 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5165 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5166
5167 gen_addr_reg_index(ctx, t0);
5168 /* NIP cannot be restored if the memory exception comes from an helper */
5169 gen_update_nip(ctx, ctx->nip - 4);
5170 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5171 tcg_temp_free_i32(t1);
5172 tcg_temp_free_i32(t2);
5173 tcg_temp_free_i32(t3);
5174 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5175 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5176 if (unlikely(Rc(ctx->opcode) != 0))
5177 gen_set_Rc0(ctx, t0);
5178 tcg_temp_free(t0);
5179 }
5180
5181 /* maskg - maskg. */
5182 static void gen_maskg(DisasContext *ctx)
5183 {
5184 TCGLabel *l1 = gen_new_label();
5185 TCGv t0 = tcg_temp_new();
5186 TCGv t1 = tcg_temp_new();
5187 TCGv t2 = tcg_temp_new();
5188 TCGv t3 = tcg_temp_new();
5189 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5190 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5191 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5192 tcg_gen_addi_tl(t2, t0, 1);
5193 tcg_gen_shr_tl(t2, t3, t2);
5194 tcg_gen_shr_tl(t3, t3, t1);
5195 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5196 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5197 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5198 gen_set_label(l1);
5199 tcg_temp_free(t0);
5200 tcg_temp_free(t1);
5201 tcg_temp_free(t2);
5202 tcg_temp_free(t3);
5203 if (unlikely(Rc(ctx->opcode) != 0))
5204 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5205 }
5206
5207 /* maskir - maskir. */
5208 static void gen_maskir(DisasContext *ctx)
5209 {
5210 TCGv t0 = tcg_temp_new();
5211 TCGv t1 = tcg_temp_new();
5212 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5213 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5214 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5215 tcg_temp_free(t0);
5216 tcg_temp_free(t1);
5217 if (unlikely(Rc(ctx->opcode) != 0))
5218 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5219 }
5220
5221 /* mul - mul. */
5222 static void gen_mul(DisasContext *ctx)
5223 {
5224 TCGv_i64 t0 = tcg_temp_new_i64();
5225 TCGv_i64 t1 = tcg_temp_new_i64();
5226 TCGv t2 = tcg_temp_new();
5227 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5228 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5229 tcg_gen_mul_i64(t0, t0, t1);
5230 tcg_gen_trunc_i64_tl(t2, t0);
5231 gen_store_spr(SPR_MQ, t2);
5232 tcg_gen_shri_i64(t1, t0, 32);
5233 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5234 tcg_temp_free_i64(t0);
5235 tcg_temp_free_i64(t1);
5236 tcg_temp_free(t2);
5237 if (unlikely(Rc(ctx->opcode) != 0))
5238 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5239 }
5240
5241 /* mulo - mulo. */
5242 static void gen_mulo(DisasContext *ctx)
5243 {
5244 TCGLabel *l1 = gen_new_label();
5245 TCGv_i64 t0 = tcg_temp_new_i64();
5246 TCGv_i64 t1 = tcg_temp_new_i64();
5247 TCGv t2 = tcg_temp_new();
5248 /* Start with XER OV disabled, the most likely case */
5249 tcg_gen_movi_tl(cpu_ov, 0);
5250 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5251 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5252 tcg_gen_mul_i64(t0, t0, t1);
5253 tcg_gen_trunc_i64_tl(t2, t0);
5254 gen_store_spr(SPR_MQ, t2);
5255 tcg_gen_shri_i64(t1, t0, 32);
5256 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5257 tcg_gen_ext32s_i64(t1, t0);
5258 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5259 tcg_gen_movi_tl(cpu_ov, 1);
5260 tcg_gen_movi_tl(cpu_so, 1);
5261 gen_set_label(l1);
5262 tcg_temp_free_i64(t0);
5263 tcg_temp_free_i64(t1);
5264 tcg_temp_free(t2);
5265 if (unlikely(Rc(ctx->opcode) != 0))
5266 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5267 }
5268
5269 /* nabs - nabs. */
5270 static void gen_nabs(DisasContext *ctx)
5271 {
5272 TCGLabel *l1 = gen_new_label();
5273 TCGLabel *l2 = gen_new_label();
5274 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5276 tcg_gen_br(l2);
5277 gen_set_label(l1);
5278 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5279 gen_set_label(l2);
5280 if (unlikely(Rc(ctx->opcode) != 0))
5281 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5282 }
5283
5284 /* nabso - nabso. */
5285 static void gen_nabso(DisasContext *ctx)
5286 {
5287 TCGLabel *l1 = gen_new_label();
5288 TCGLabel *l2 = gen_new_label();
5289 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5290 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5291 tcg_gen_br(l2);
5292 gen_set_label(l1);
5293 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5294 gen_set_label(l2);
5295 /* nabs never overflows */
5296 tcg_gen_movi_tl(cpu_ov, 0);
5297 if (unlikely(Rc(ctx->opcode) != 0))
5298 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5299 }
5300
5301 /* rlmi - rlmi. */
5302 static void gen_rlmi(DisasContext *ctx)
5303 {
5304 uint32_t mb = MB(ctx->opcode);
5305 uint32_t me = ME(ctx->opcode);
5306 TCGv t0 = tcg_temp_new();
5307 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5308 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5309 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5310 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5311 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5312 tcg_temp_free(t0);
5313 if (unlikely(Rc(ctx->opcode) != 0))
5314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5315 }
5316
5317 /* rrib - rrib. */
5318 static void gen_rrib(DisasContext *ctx)
5319 {
5320 TCGv t0 = tcg_temp_new();
5321 TCGv t1 = tcg_temp_new();
5322 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5323 tcg_gen_movi_tl(t1, 0x80000000);
5324 tcg_gen_shr_tl(t1, t1, t0);
5325 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5326 tcg_gen_and_tl(t0, t0, t1);
5327 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5328 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5329 tcg_temp_free(t0);
5330 tcg_temp_free(t1);
5331 if (unlikely(Rc(ctx->opcode) != 0))
5332 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5333 }
5334
5335 /* sle - sle. */
5336 static void gen_sle(DisasContext *ctx)
5337 {
5338 TCGv t0 = tcg_temp_new();
5339 TCGv t1 = tcg_temp_new();
5340 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5341 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5342 tcg_gen_subfi_tl(t1, 32, t1);
5343 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5344 tcg_gen_or_tl(t1, t0, t1);
5345 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5346 gen_store_spr(SPR_MQ, t1);
5347 tcg_temp_free(t0);
5348 tcg_temp_free(t1);
5349 if (unlikely(Rc(ctx->opcode) != 0))
5350 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5351 }
5352
5353 /* sleq - sleq. */
5354 static void gen_sleq(DisasContext *ctx)
5355 {
5356 TCGv t0 = tcg_temp_new();
5357 TCGv t1 = tcg_temp_new();
5358 TCGv t2 = tcg_temp_new();
5359 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5360 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5361 tcg_gen_shl_tl(t2, t2, t0);
5362 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5363 gen_load_spr(t1, SPR_MQ);
5364 gen_store_spr(SPR_MQ, t0);
5365 tcg_gen_and_tl(t0, t0, t2);
5366 tcg_gen_andc_tl(t1, t1, t2);
5367 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5368 tcg_temp_free(t0);
5369 tcg_temp_free(t1);
5370 tcg_temp_free(t2);
5371 if (unlikely(Rc(ctx->opcode) != 0))
5372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5373 }
5374
5375 /* sliq - sliq. */
5376 static void gen_sliq(DisasContext *ctx)
5377 {
5378 int sh = SH(ctx->opcode);
5379 TCGv t0 = tcg_temp_new();
5380 TCGv t1 = tcg_temp_new();
5381 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5382 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5383 tcg_gen_or_tl(t1, t0, t1);
5384 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5385 gen_store_spr(SPR_MQ, t1);
5386 tcg_temp_free(t0);
5387 tcg_temp_free(t1);
5388 if (unlikely(Rc(ctx->opcode) != 0))
5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5390 }
5391
5392 /* slliq - slliq. */
5393 static void gen_slliq(DisasContext *ctx)
5394 {
5395 int sh = SH(ctx->opcode);
5396 TCGv t0 = tcg_temp_new();
5397 TCGv t1 = tcg_temp_new();
5398 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5399 gen_load_spr(t1, SPR_MQ);
5400 gen_store_spr(SPR_MQ, t0);
5401 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5402 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5403 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5404 tcg_temp_free(t0);
5405 tcg_temp_free(t1);
5406 if (unlikely(Rc(ctx->opcode) != 0))
5407 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5408 }
5409
5410 /* sllq - sllq. */
5411 static void gen_sllq(DisasContext *ctx)
5412 {
5413 TCGLabel *l1 = gen_new_label();
5414 TCGLabel *l2 = gen_new_label();
5415 TCGv t0 = tcg_temp_local_new();
5416 TCGv t1 = tcg_temp_local_new();
5417 TCGv t2 = tcg_temp_local_new();
5418 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5419 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5420 tcg_gen_shl_tl(t1, t1, t2);
5421 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5422 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5423 gen_load_spr(t0, SPR_MQ);
5424 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5425 tcg_gen_br(l2);
5426 gen_set_label(l1);
5427 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5428 gen_load_spr(t2, SPR_MQ);
5429 tcg_gen_andc_tl(t1, t2, t1);
5430 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5431 gen_set_label(l2);
5432 tcg_temp_free(t0);
5433 tcg_temp_free(t1);
5434 tcg_temp_free(t2);
5435 if (unlikely(Rc(ctx->opcode) != 0))
5436 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5437 }
5438
5439 /* slq - slq. */
5440 static void gen_slq(DisasContext *ctx)
5441 {
5442 TCGLabel *l1 = gen_new_label();
5443 TCGv t0 = tcg_temp_new();
5444 TCGv t1 = tcg_temp_new();
5445 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5446 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5447 tcg_gen_subfi_tl(t1, 32, t1);
5448 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5449 tcg_gen_or_tl(t1, t0, t1);
5450 gen_store_spr(SPR_MQ, t1);
5451 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5452 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5453 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5454 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5455 gen_set_label(l1);
5456 tcg_temp_free(t0);
5457 tcg_temp_free(t1);
5458 if (unlikely(Rc(ctx->opcode) != 0))
5459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5460 }
5461
5462 /* sraiq - sraiq. */
5463 static void gen_sraiq(DisasContext *ctx)
5464 {
5465 int sh = SH(ctx->opcode);
5466 TCGLabel *l1 = gen_new_label();
5467 TCGv t0 = tcg_temp_new();
5468 TCGv t1 = tcg_temp_new();
5469 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5470 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5471 tcg_gen_or_tl(t0, t0, t1);
5472 gen_store_spr(SPR_MQ, t0);
5473 tcg_gen_movi_tl(cpu_ca, 0);
5474 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5475 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5476 tcg_gen_movi_tl(cpu_ca, 1);
5477 gen_set_label(l1);
5478 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5479 tcg_temp_free(t0);
5480 tcg_temp_free(t1);
5481 if (unlikely(Rc(ctx->opcode) != 0))
5482 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5483 }
5484
5485 /* sraq - sraq. */
5486 static void gen_sraq(DisasContext *ctx)
5487 {
5488 TCGLabel *l1 = gen_new_label();
5489 TCGLabel *l2 = gen_new_label();
5490 TCGv t0 = tcg_temp_new();
5491 TCGv t1 = tcg_temp_local_new();
5492 TCGv t2 = tcg_temp_local_new();
5493 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5494 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5495 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5496 tcg_gen_subfi_tl(t2, 32, t2);
5497 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5498 tcg_gen_or_tl(t0, t0, t2);
5499 gen_store_spr(SPR_MQ, t0);
5500 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5501 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5502 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5503 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5504 gen_set_label(l1);
5505 tcg_temp_free(t0);
5506 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5507 tcg_gen_movi_tl(cpu_ca, 0);
5508 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5509 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5510 tcg_gen_movi_tl(cpu_ca, 1);
5511 gen_set_label(l2);
5512 tcg_temp_free(t1);
5513 tcg_temp_free(t2);
5514 if (unlikely(Rc(ctx->opcode) != 0))
5515 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5516 }
5517
5518 /* sre - sre. */
5519 static void gen_sre(DisasContext *ctx)
5520 {
5521 TCGv t0 = tcg_temp_new();
5522 TCGv t1 = tcg_temp_new();
5523 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5524 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5525 tcg_gen_subfi_tl(t1, 32, t1);
5526 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5527 tcg_gen_or_tl(t1, t0, t1);
5528 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5529 gen_store_spr(SPR_MQ, t1);
5530 tcg_temp_free(t0);
5531 tcg_temp_free(t1);
5532 if (unlikely(Rc(ctx->opcode) != 0))
5533 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5534 }
5535
5536 /* srea - srea. */
5537 static void gen_srea(DisasContext *ctx)
5538 {
5539 TCGv t0 = tcg_temp_new();
5540 TCGv t1 = tcg_temp_new();
5541 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5542 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5543 gen_store_spr(SPR_MQ, t0);
5544 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5545 tcg_temp_free(t0);
5546 tcg_temp_free(t1);
5547 if (unlikely(Rc(ctx->opcode) != 0))
5548 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5549 }
5550
5551 /* sreq */
5552 static void gen_sreq(DisasContext *ctx)
5553 {
5554 TCGv t0 = tcg_temp_new();
5555 TCGv t1 = tcg_temp_new();
5556 TCGv t2 = tcg_temp_new();
5557 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5558 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5559 tcg_gen_shr_tl(t1, t1, t0);
5560 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5561 gen_load_spr(t2, SPR_MQ);
5562 gen_store_spr(SPR_MQ, t0);
5563 tcg_gen_and_tl(t0, t0, t1);
5564 tcg_gen_andc_tl(t2, t2, t1);
5565 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5566 tcg_temp_free(t0);
5567 tcg_temp_free(t1);
5568 tcg_temp_free(t2);
5569 if (unlikely(Rc(ctx->opcode) != 0))
5570 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5571 }
5572
5573 /* sriq */
5574 static void gen_sriq(DisasContext *ctx)
5575 {
5576 int sh = SH(ctx->opcode);
5577 TCGv t0 = tcg_temp_new();
5578 TCGv t1 = tcg_temp_new();
5579 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5580 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5581 tcg_gen_or_tl(t1, t0, t1);
5582 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5583 gen_store_spr(SPR_MQ, t1);
5584 tcg_temp_free(t0);
5585 tcg_temp_free(t1);
5586 if (unlikely(Rc(ctx->opcode) != 0))
5587 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5588 }
5589
5590 /* srliq */
5591 static void gen_srliq(DisasContext *ctx)
5592 {
5593 int sh = SH(ctx->opcode);
5594 TCGv t0 = tcg_temp_new();
5595 TCGv t1 = tcg_temp_new();
5596 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5597 gen_load_spr(t1, SPR_MQ);
5598 gen_store_spr(SPR_MQ, t0);
5599 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5600 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5601 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5602 tcg_temp_free(t0);
5603 tcg_temp_free(t1);
5604 if (unlikely(Rc(ctx->opcode) != 0))
5605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5606 }
5607
5608 /* srlq */
5609 static void gen_srlq(DisasContext *ctx)
5610 {
5611 TCGLabel *l1 = gen_new_label();
5612 TCGLabel *l2 = gen_new_label();
5613 TCGv t0 = tcg_temp_local_new();
5614 TCGv t1 = tcg_temp_local_new();
5615 TCGv t2 = tcg_temp_local_new();
5616 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5617 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5618 tcg_gen_shr_tl(t2, t1, t2);
5619 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5620 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5621 gen_load_spr(t0, SPR_MQ);
5622 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5623 tcg_gen_br(l2);
5624 gen_set_label(l1);
5625 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5626 tcg_gen_and_tl(t0, t0, t2);
5627 gen_load_spr(t1, SPR_MQ);
5628 tcg_gen_andc_tl(t1, t1, t2);
5629 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5630 gen_set_label(l2);
5631 tcg_temp_free(t0);
5632 tcg_temp_free(t1);
5633 tcg_temp_free(t2);
5634 if (unlikely(Rc(ctx->opcode) != 0))
5635 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5636 }
5637
5638 /* srq */
5639 static void gen_srq(DisasContext *ctx)
5640 {
5641 TCGLabel *l1 = gen_new_label();
5642 TCGv t0 = tcg_temp_new();
5643 TCGv t1 = tcg_temp_new();
5644 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5645 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5646 tcg_gen_subfi_tl(t1, 32, t1);
5647 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5648 tcg_gen_or_tl(t1, t0, t1);
5649 gen_store_spr(SPR_MQ, t1);
5650 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5651 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5652 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5653 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5654 gen_set_label(l1);
5655 tcg_temp_free(t0);
5656 tcg_temp_free(t1);
5657 if (unlikely(Rc(ctx->opcode) != 0))
5658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5659 }
5660
5661 /* PowerPC 602 specific instructions */
5662
5663 /* dsa */
5664 static void gen_dsa(DisasContext *ctx)
5665 {
5666 /* XXX: TODO */
5667 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5668 }
5669
5670 /* esa */
5671 static void gen_esa(DisasContext *ctx)
5672 {
5673 /* XXX: TODO */
5674 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5675 }
5676
5677 /* mfrom */
5678 static void gen_mfrom(DisasContext *ctx)
5679 {
5680 #if defined(CONFIG_USER_ONLY)
5681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5682 #else
5683 if (unlikely(ctx->pr)) {
5684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5685 return;
5686 }
5687 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5688 #endif
5689 }
5690
5691 /* 602 - 603 - G2 TLB management */
5692
5693 /* tlbld */
5694 static void gen_tlbld_6xx(DisasContext *ctx)
5695 {
5696 #if defined(CONFIG_USER_ONLY)
5697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5698 #else
5699 if (unlikely(ctx->pr)) {
5700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5701 return;
5702 }
5703 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5704 #endif
5705 }
5706
5707 /* tlbli */
5708 static void gen_tlbli_6xx(DisasContext *ctx)
5709 {
5710 #if defined(CONFIG_USER_ONLY)
5711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5712 #else
5713 if (unlikely(ctx->pr)) {
5714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5715 return;
5716 }
5717 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5718 #endif
5719 }
5720
5721 /* 74xx TLB management */
5722
5723 /* tlbld */
5724 static void gen_tlbld_74xx(DisasContext *ctx)
5725 {
5726 #if defined(CONFIG_USER_ONLY)
5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5728 #else
5729 if (unlikely(ctx->pr)) {
5730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5731 return;
5732 }
5733 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5734 #endif
5735 }
5736
5737 /* tlbli */
5738 static void gen_tlbli_74xx(DisasContext *ctx)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5742 #else
5743 if (unlikely(ctx->pr)) {
5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5745 return;
5746 }
5747 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5748 #endif
5749 }
5750
5751 /* POWER instructions not in PowerPC 601 */
5752
5753 /* clf */
5754 static void gen_clf(DisasContext *ctx)
5755 {
5756 /* Cache line flush: implemented as no-op */
5757 }
5758
5759 /* cli */
5760 static void gen_cli(DisasContext *ctx)
5761 {
5762 /* Cache line invalidate: privileged and treated as no-op */
5763 #if defined(CONFIG_USER_ONLY)
5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5765 #else
5766 if (unlikely(ctx->pr)) {
5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5768 return;
5769 }
5770 #endif
5771 }
5772
5773 /* dclst */
5774 static void gen_dclst(DisasContext *ctx)
5775 {
5776 /* Data cache line store: treated as no-op */
5777 }
5778
5779 static void gen_mfsri(DisasContext *ctx)
5780 {
5781 #if defined(CONFIG_USER_ONLY)
5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5783 #else
5784 int ra = rA(ctx->opcode);
5785 int rd = rD(ctx->opcode);
5786 TCGv t0;
5787 if (unlikely(ctx->pr)) {
5788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5789 return;
5790 }
5791 t0 = tcg_temp_new();
5792 gen_addr_reg_index(ctx, t0);
5793 tcg_gen_shri_tl(t0, t0, 28);
5794 tcg_gen_andi_tl(t0, t0, 0xF);
5795 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5796 tcg_temp_free(t0);
5797 if (ra != 0 && ra != rd)
5798 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5799 #endif
5800 }
5801
5802 static void gen_rac(DisasContext *ctx)
5803 {
5804 #if defined(CONFIG_USER_ONLY)
5805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5806 #else
5807 TCGv t0;
5808 if (unlikely(ctx->pr)) {
5809 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5810 return;
5811 }
5812 t0 = tcg_temp_new();
5813 gen_addr_reg_index(ctx, t0);
5814 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5815 tcg_temp_free(t0);
5816 #endif
5817 }
5818
5819 static void gen_rfsvc(DisasContext *ctx)
5820 {
5821 #if defined(CONFIG_USER_ONLY)
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 #else
5824 if (unlikely(ctx->pr)) {
5825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5826 return;
5827 }
5828 gen_helper_rfsvc(cpu_env);
5829 gen_sync_exception(ctx);
5830 #endif
5831 }
5832
5833 /* svc is not implemented for now */
5834
5835 /* POWER2 specific instructions */
5836 /* Quad manipulation (load/store two floats at a time) */
5837
5838 /* lfq */
5839 static void gen_lfq(DisasContext *ctx)
5840 {
5841 int rd = rD(ctx->opcode);
5842 TCGv t0;
5843 gen_set_access_type(ctx, ACCESS_FLOAT);
5844 t0 = tcg_temp_new();
5845 gen_addr_imm_index(ctx, t0, 0);
5846 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5847 gen_addr_add(ctx, t0, t0, 8);
5848 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5849 tcg_temp_free(t0);
5850 }
5851
5852 /* lfqu */
5853 static void gen_lfqu(DisasContext *ctx)
5854 {
5855 int ra = rA(ctx->opcode);
5856 int rd = rD(ctx->opcode);
5857 TCGv t0, t1;
5858 gen_set_access_type(ctx, ACCESS_FLOAT);
5859 t0 = tcg_temp_new();
5860 t1 = tcg_temp_new();
5861 gen_addr_imm_index(ctx, t0, 0);
5862 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5863 gen_addr_add(ctx, t1, t0, 8);
5864 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5865 if (ra != 0)
5866 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5867 tcg_temp_free(t0);
5868 tcg_temp_free(t1);
5869 }
5870
5871 /* lfqux */
5872 static void gen_lfqux(DisasContext *ctx)
5873 {
5874 int ra = rA(ctx->opcode);
5875 int rd = rD(ctx->opcode);
5876 gen_set_access_type(ctx, ACCESS_FLOAT);
5877 TCGv t0, t1;
5878 t0 = tcg_temp_new();
5879 gen_addr_reg_index(ctx, t0);
5880 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5881 t1 = tcg_temp_new();
5882 gen_addr_add(ctx, t1, t0, 8);
5883 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5884 tcg_temp_free(t1);
5885 if (ra != 0)
5886 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5887 tcg_temp_free(t0);
5888 }
5889
5890 /* lfqx */
5891 static void gen_lfqx(DisasContext *ctx)
5892 {
5893 int rd = rD(ctx->opcode);
5894 TCGv t0;
5895 gen_set_access_type(ctx, ACCESS_FLOAT);
5896 t0 = tcg_temp_new();
5897 gen_addr_reg_index(ctx, t0);
5898 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5899 gen_addr_add(ctx, t0, t0, 8);
5900 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5901 tcg_temp_free(t0);
5902 }
5903
5904 /* stfq */
5905 static void gen_stfq(DisasContext *ctx)
5906 {
5907 int rd = rD(ctx->opcode);
5908 TCGv t0;
5909 gen_set_access_type(ctx, ACCESS_FLOAT);
5910 t0 = tcg_temp_new();
5911 gen_addr_imm_index(ctx, t0, 0);
5912 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5913 gen_addr_add(ctx, t0, t0, 8);
5914 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5915 tcg_temp_free(t0);
5916 }
5917
5918 /* stfqu */
5919 static void gen_stfqu(DisasContext *ctx)
5920 {
5921 int ra = rA(ctx->opcode);
5922 int rd = rD(ctx->opcode);
5923 TCGv t0, t1;
5924 gen_set_access_type(ctx, ACCESS_FLOAT);
5925 t0 = tcg_temp_new();
5926 gen_addr_imm_index(ctx, t0, 0);
5927 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5928 t1 = tcg_temp_new();
5929 gen_addr_add(ctx, t1, t0, 8);
5930 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5931 tcg_temp_free(t1);
5932 if (ra != 0)
5933 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5934 tcg_temp_free(t0);
5935 }
5936
5937 /* stfqux */
5938 static void gen_stfqux(DisasContext *ctx)
5939 {
5940 int ra = rA(ctx->opcode);
5941 int rd = rD(ctx->opcode);
5942 TCGv t0, t1;
5943 gen_set_access_type(ctx, ACCESS_FLOAT);
5944 t0 = tcg_temp_new();
5945 gen_addr_reg_index(ctx, t0);
5946 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5947 t1 = tcg_temp_new();
5948 gen_addr_add(ctx, t1, t0, 8);
5949 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5950 tcg_temp_free(t1);
5951 if (ra != 0)
5952 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5953 tcg_temp_free(t0);
5954 }
5955
5956 /* stfqx */
5957 static void gen_stfqx(DisasContext *ctx)
5958 {
5959 int rd = rD(ctx->opcode);
5960 TCGv t0;
5961 gen_set_access_type(ctx, ACCESS_FLOAT);
5962 t0 = tcg_temp_new();
5963 gen_addr_reg_index(ctx, t0);
5964 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5965 gen_addr_add(ctx, t0, t0, 8);
5966 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5967 tcg_temp_free(t0);
5968 }
5969
5970 /* BookE specific instructions */
5971
5972 /* XXX: not implemented on 440 ? */
5973 static void gen_mfapidi(DisasContext *ctx)
5974 {
5975 /* XXX: TODO */
5976 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5977 }
5978
5979 /* XXX: not implemented on 440 ? */
5980 static void gen_tlbiva(DisasContext *ctx)
5981 {
5982 #if defined(CONFIG_USER_ONLY)
5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5984 #else
5985 TCGv t0;
5986 if (unlikely(ctx->pr)) {
5987 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5988 return;
5989 }
5990 t0 = tcg_temp_new();
5991 gen_addr_reg_index(ctx, t0);
5992 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5993 tcg_temp_free(t0);
5994 #endif
5995 }
5996
5997 /* All 405 MAC instructions are translated here */
5998 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5999 int ra, int rb, int rt, int Rc)
6000 {
6001 TCGv t0, t1;
6002
6003 t0 = tcg_temp_local_new();
6004 t1 = tcg_temp_local_new();
6005
6006 switch (opc3 & 0x0D) {
6007 case 0x05:
6008 /* macchw - macchw. - macchwo - macchwo. */
6009 /* macchws - macchws. - macchwso - macchwso. */
6010 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6011 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6012 /* mulchw - mulchw. */
6013 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6014 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6015 tcg_gen_ext16s_tl(t1, t1);
6016 break;
6017 case 0x04:
6018 /* macchwu - macchwu. - macchwuo - macchwuo. */
6019 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6020 /* mulchwu - mulchwu. */
6021 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6022 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6023 tcg_gen_ext16u_tl(t1, t1);
6024 break;
6025 case 0x01:
6026 /* machhw - machhw. - machhwo - machhwo. */
6027 /* machhws - machhws. - machhwso - machhwso. */
6028 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6029 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6030 /* mulhhw - mulhhw. */
6031 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6032 tcg_gen_ext16s_tl(t0, t0);
6033 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6034 tcg_gen_ext16s_tl(t1, t1);
6035 break;
6036 case 0x00:
6037 /* machhwu - machhwu. - machhwuo - machhwuo. */
6038 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6039 /* mulhhwu - mulhhwu. */
6040 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6041 tcg_gen_ext16u_tl(t0, t0);
6042 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6043 tcg_gen_ext16u_tl(t1, t1);
6044 break;
6045 case 0x0D:
6046 /* maclhw - maclhw. - maclhwo - maclhwo. */
6047 /* maclhws - maclhws. - maclhwso - maclhwso. */
6048 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6049 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6050 /* mullhw - mullhw. */
6051 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6052 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6053 break;
6054 case 0x0C:
6055 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6056 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6057 /* mullhwu - mullhwu. */
6058 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6059 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6060 break;
6061 }
6062 if (opc2 & 0x04) {
6063 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6064 tcg_gen_mul_tl(t1, t0, t1);
6065 if (opc2 & 0x02) {
6066 /* nmultiply-and-accumulate (0x0E) */
6067 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6068 } else {
6069 /* multiply-and-accumulate (0x0C) */
6070 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6071 }
6072
6073 if (opc3 & 0x12) {
6074 /* Check overflow and/or saturate */
6075 TCGLabel *l1 = gen_new_label();
6076
6077 if (opc3 & 0x10) {
6078 /* Start with XER OV disabled, the most likely case */
6079 tcg_gen_movi_tl(cpu_ov, 0);
6080 }
6081 if (opc3 & 0x01) {
6082 /* Signed */
6083 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6084 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6085 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6086 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6087 if (opc3 & 0x02) {
6088 /* Saturate */
6089 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6090 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6091 }
6092 } else {
6093 /* Unsigned */
6094 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6095 if (opc3 & 0x02) {
6096 /* Saturate */
6097 tcg_gen_movi_tl(t0, UINT32_MAX);
6098 }
6099 }
6100 if (opc3 & 0x10) {
6101 /* Check overflow */
6102 tcg_gen_movi_tl(cpu_ov, 1);
6103 tcg_gen_movi_tl(cpu_so, 1);
6104 }
6105 gen_set_label(l1);
6106 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6107 }
6108 } else {
6109 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6110 }
6111 tcg_temp_free(t0);
6112 tcg_temp_free(t1);
6113 if (unlikely(Rc) != 0) {
6114 /* Update Rc0 */
6115 gen_set_Rc0(ctx, cpu_gpr[rt]);
6116 }
6117 }
6118
6119 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6120 static void glue(gen_, name)(DisasContext *ctx) \
6121 { \
6122 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6123 rD(ctx->opcode), Rc(ctx->opcode)); \
6124 }
6125
6126 /* macchw - macchw. */
6127 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6128 /* macchwo - macchwo. */
6129 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6130 /* macchws - macchws. */
6131 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6132 /* macchwso - macchwso. */
6133 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6134 /* macchwsu - macchwsu. */
6135 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6136 /* macchwsuo - macchwsuo. */
6137 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6138 /* macchwu - macchwu. */
6139 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6140 /* macchwuo - macchwuo. */
6141 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6142 /* machhw - machhw. */
6143 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6144 /* machhwo - machhwo. */
6145 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6146 /* machhws - machhws. */
6147 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6148 /* machhwso - machhwso. */
6149 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6150 /* machhwsu - machhwsu. */
6151 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6152 /* machhwsuo - machhwsuo. */
6153 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6154 /* machhwu - machhwu. */
6155 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6156 /* machhwuo - machhwuo. */
6157 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6158 /* maclhw - maclhw. */
6159 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6160 /* maclhwo - maclhwo. */
6161 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6162 /* maclhws - maclhws. */
6163 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6164 /* maclhwso - maclhwso. */
6165 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6166 /* maclhwu - maclhwu. */
6167 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6168 /* maclhwuo - maclhwuo. */
6169 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6170 /* maclhwsu - maclhwsu. */
6171 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6172 /* maclhwsuo - maclhwsuo. */
6173 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6174 /* nmacchw - nmacchw. */
6175 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6176 /* nmacchwo - nmacchwo. */
6177 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6178 /* nmacchws - nmacchws. */
6179 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6180 /* nmacchwso - nmacchwso. */
6181 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6182 /* nmachhw - nmachhw. */
6183 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6184 /* nmachhwo - nmachhwo. */
6185 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6186 /* nmachhws - nmachhws. */
6187 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6188 /* nmachhwso - nmachhwso. */
6189 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6190 /* nmaclhw - nmaclhw. */
6191 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6192 /* nmaclhwo - nmaclhwo. */
6193 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6194 /* nmaclhws - nmaclhws. */
6195 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6196 /* nmaclhwso - nmaclhwso. */
6197 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6198
6199 /* mulchw - mulchw. */
6200 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6201 /* mulchwu - mulchwu. */
6202 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6203 /* mulhhw - mulhhw. */
6204 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6205 /* mulhhwu - mulhhwu. */
6206 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6207 /* mullhw - mullhw. */
6208 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6209 /* mullhwu - mullhwu. */
6210 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6211
6212 /* mfdcr */
6213 static void gen_mfdcr(DisasContext *ctx)
6214 {
6215 #if defined(CONFIG_USER_ONLY)
6216 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6217 #else
6218 TCGv dcrn;
6219 if (unlikely(ctx->pr)) {
6220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6221 return;
6222 }
6223 /* NIP cannot be restored if the memory exception comes from an helper */
6224 gen_update_nip(ctx, ctx->nip - 4);
6225 dcrn = tcg_const_tl(SPR(ctx->opcode));
6226 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6227 tcg_temp_free(dcrn);
6228 #endif
6229 }
6230
6231 /* mtdcr */
6232 static void gen_mtdcr(DisasContext *ctx)
6233 {
6234 #if defined(CONFIG_USER_ONLY)
6235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6236 #else
6237 TCGv dcrn;
6238 if (unlikely(ctx->pr)) {
6239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6240 return;
6241 }
6242 /* NIP cannot be restored if the memory exception comes from an helper */
6243 gen_update_nip(ctx, ctx->nip - 4);
6244 dcrn = tcg_const_tl(SPR(ctx->opcode));
6245 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6246 tcg_temp_free(dcrn);
6247 #endif
6248 }
6249
6250 /* mfdcrx */
6251 /* XXX: not implemented on 440 ? */
6252 static void gen_mfdcrx(DisasContext *ctx)
6253 {
6254 #if defined(CONFIG_USER_ONLY)
6255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6256 #else
6257 if (unlikely(ctx->pr)) {
6258 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6259 return;
6260 }
6261 /* NIP cannot be restored if the memory exception comes from an helper */
6262 gen_update_nip(ctx, ctx->nip - 4);
6263 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6264 cpu_gpr[rA(ctx->opcode)]);
6265 /* Note: Rc update flag set leads to undefined state of Rc0 */
6266 #endif
6267 }
6268
6269 /* mtdcrx */
6270 /* XXX: not implemented on 440 ? */
6271 static void gen_mtdcrx(DisasContext *ctx)
6272 {
6273 #if defined(CONFIG_USER_ONLY)
6274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6275 #else
6276 if (unlikely(ctx->pr)) {
6277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6278 return;
6279 }
6280 /* NIP cannot be restored if the memory exception comes from an helper */
6281 gen_update_nip(ctx, ctx->nip - 4);
6282 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6283 cpu_gpr[rS(ctx->opcode)]);
6284 /* Note: Rc update flag set leads to undefined state of Rc0 */
6285 #endif
6286 }
6287
6288 /* mfdcrux (PPC 460) : user-mode access to DCR */
6289 static void gen_mfdcrux(DisasContext *ctx)
6290 {
6291 /* NIP cannot be restored if the memory exception comes from an helper */
6292 gen_update_nip(ctx, ctx->nip - 4);
6293 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6294 cpu_gpr[rA(ctx->opcode)]);
6295 /* Note: Rc update flag set leads to undefined state of Rc0 */
6296 }
6297
6298 /* mtdcrux (PPC 460) : user-mode access to DCR */
6299 static void gen_mtdcrux(DisasContext *ctx)
6300 {
6301 /* NIP cannot be restored if the memory exception comes from an helper */
6302 gen_update_nip(ctx, ctx->nip - 4);
6303 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6304 cpu_gpr[rS(ctx->opcode)]);
6305 /* Note: Rc update flag set leads to undefined state of Rc0 */
6306 }
6307
6308 /* dccci */
6309 static void gen_dccci(DisasContext *ctx)
6310 {
6311 #if defined(CONFIG_USER_ONLY)
6312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6313 #else
6314 if (unlikely(ctx->pr)) {
6315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6316 return;
6317 }
6318 /* interpreted as no-op */
6319 #endif
6320 }
6321
6322 /* dcread */
6323 static void gen_dcread(DisasContext *ctx)
6324 {
6325 #if defined(CONFIG_USER_ONLY)
6326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6327 #else
6328 TCGv EA, val;
6329 if (unlikely(ctx->pr)) {
6330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6331 return;
6332 }
6333 gen_set_access_type(ctx, ACCESS_CACHE);
6334 EA = tcg_temp_new();
6335 gen_addr_reg_index(ctx, EA);
6336 val = tcg_temp_new();
6337 gen_qemu_ld32u(ctx, val, EA);
6338 tcg_temp_free(val);
6339 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6340 tcg_temp_free(EA);
6341 #endif
6342 }
6343
6344 /* icbt */
6345 static void gen_icbt_40x(DisasContext *ctx)
6346 {
6347 /* interpreted as no-op */
6348 /* XXX: specification say this is treated as a load by the MMU
6349 * but does not generate any exception
6350 */
6351 }
6352
6353 /* iccci */
6354 static void gen_iccci(DisasContext *ctx)
6355 {
6356 #if defined(CONFIG_USER_ONLY)
6357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6358 #else
6359 if (unlikely(ctx->pr)) {
6360 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6361 return;
6362 }
6363 /* interpreted as no-op */
6364 #endif
6365 }
6366
6367 /* icread */
6368 static void gen_icread(DisasContext *ctx)
6369 {
6370 #if defined(CONFIG_USER_ONLY)
6371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6372 #else
6373 if (unlikely(ctx->pr)) {
6374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6375 return;
6376 }
6377 /* interpreted as no-op */
6378 #endif
6379 }
6380
6381 /* rfci (supervisor only) */
6382 static void gen_rfci_40x(DisasContext *ctx)
6383 {
6384 #if defined(CONFIG_USER_ONLY)
6385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6386 #else
6387 if (unlikely(ctx->pr)) {
6388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6389 return;
6390 }
6391 /* Restore CPU state */
6392 gen_helper_40x_rfci(cpu_env);
6393 gen_sync_exception(ctx);
6394 #endif
6395 }
6396
6397 static void gen_rfci(DisasContext *ctx)
6398 {
6399 #if defined(CONFIG_USER_ONLY)
6400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6401 #else
6402 if (unlikely(ctx->pr)) {
6403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6404 return;
6405 }
6406 /* Restore CPU state */
6407 gen_helper_rfci(cpu_env);
6408 gen_sync_exception(ctx);
6409 #endif
6410 }
6411
6412 /* BookE specific */
6413
6414 /* XXX: not implemented on 440 ? */
6415 static void gen_rfdi(DisasContext *ctx)
6416 {
6417 #if defined(CONFIG_USER_ONLY)
6418 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6419 #else
6420 if (unlikely(ctx->pr)) {
6421 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6422 return;
6423 }
6424 /* Restore CPU state */
6425 gen_helper_rfdi(cpu_env);
6426 gen_sync_exception(ctx);
6427 #endif
6428 }
6429
6430 /* XXX: not implemented on 440 ? */
6431 static void gen_rfmci(DisasContext *ctx)
6432 {
6433 #if defined(CONFIG_USER_ONLY)
6434 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6435 #else
6436 if (unlikely(ctx->pr)) {
6437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6438 return;
6439 }
6440 /* Restore CPU state */
6441 gen_helper_rfmci(cpu_env);
6442 gen_sync_exception(ctx);
6443 #endif
6444 }
6445
6446 /* TLB management - PowerPC 405 implementation */
6447
6448 /* tlbre */
6449 static void gen_tlbre_40x(DisasContext *ctx)
6450 {
6451 #if defined(CONFIG_USER_ONLY)
6452 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6453 #else
6454 if (unlikely(ctx->pr)) {
6455 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6456 return;
6457 }
6458 switch (rB(ctx->opcode)) {
6459 case 0:
6460 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6461 cpu_gpr[rA(ctx->opcode)]);
6462 break;
6463 case 1:
6464 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6465 cpu_gpr[rA(ctx->opcode)]);
6466 break;
6467 default:
6468 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6469 break;
6470 }
6471 #endif
6472 }
6473
6474 /* tlbsx - tlbsx. */
6475 static void gen_tlbsx_40x(DisasContext *ctx)
6476 {
6477 #if defined(CONFIG_USER_ONLY)
6478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6479 #else
6480 TCGv t0;
6481 if (unlikely(ctx->pr)) {
6482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6483 return;
6484 }
6485 t0 = tcg_temp_new();
6486 gen_addr_reg_index(ctx, t0);
6487 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6488 tcg_temp_free(t0);
6489 if (Rc(ctx->opcode)) {
6490 TCGLabel *l1 = gen_new_label();
6491 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6492 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6493 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6494 gen_set_label(l1);
6495 }
6496 #endif
6497 }
6498
6499 /* tlbwe */
6500 static void gen_tlbwe_40x(DisasContext *ctx)
6501 {
6502 #if defined(CONFIG_USER_ONLY)
6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6504 #else
6505 if (unlikely(ctx->pr)) {
6506 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6507 return;
6508 }
6509 switch (rB(ctx->opcode)) {
6510 case 0:
6511 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6512 cpu_gpr[rS(ctx->opcode)]);
6513 break;
6514 case 1:
6515 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6516 cpu_gpr[rS(ctx->opcode)]);
6517 break;
6518 default:
6519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6520 break;
6521 }
6522 #endif
6523 }
6524
6525 /* TLB management - PowerPC 440 implementation */
6526
6527 /* tlbre */
6528 static void gen_tlbre_440(DisasContext *ctx)
6529 {
6530 #if defined(CONFIG_USER_ONLY)
6531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6532 #else
6533 if (unlikely(ctx->pr)) {
6534 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6535 return;
6536 }
6537 switch (rB(ctx->opcode)) {
6538 case 0:
6539 case 1:
6540 case 2:
6541 {
6542 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6543 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6544 t0, cpu_gpr[rA(ctx->opcode)]);
6545 tcg_temp_free_i32(t0);
6546 }
6547 break;
6548 default:
6549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6550 break;
6551 }
6552 #endif
6553 }
6554
6555 /* tlbsx - tlbsx. */
6556 static void gen_tlbsx_440(DisasContext *ctx)
6557 {
6558 #if defined(CONFIG_USER_ONLY)
6559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6560 #else
6561 TCGv t0;
6562 if (unlikely(ctx->pr)) {
6563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6564 return;
6565 }
6566 t0 = tcg_temp_new();
6567 gen_addr_reg_index(ctx, t0);
6568 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6569 tcg_temp_free(t0);
6570 if (Rc(ctx->opcode)) {
6571 TCGLabel *l1 = gen_new_label();
6572 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6573 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6574 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6575 gen_set_label(l1);
6576 }
6577 #endif
6578 }
6579
6580 /* tlbwe */
6581 static void gen_tlbwe_440(DisasContext *ctx)
6582 {
6583 #if defined(CONFIG_USER_ONLY)
6584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6585 #else
6586 if (unlikely(ctx->pr)) {
6587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6588 return;
6589 }
6590 switch (rB(ctx->opcode)) {
6591 case 0:
6592 case 1:
6593 case 2:
6594 {
6595 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6596 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6597 cpu_gpr[rS(ctx->opcode)]);
6598 tcg_temp_free_i32(t0);
6599 }
6600 break;
6601 default:
6602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6603 break;
6604 }
6605 #endif
6606 }
6607
6608 /* TLB management - PowerPC BookE 2.06 implementation */
6609
6610 /* tlbre */
6611 static void gen_tlbre_booke206(DisasContext *ctx)
6612 {
6613 #if defined(CONFIG_USER_ONLY)
6614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6615 #else
6616 if (unlikely(ctx->pr)) {
6617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6618 return;
6619 }
6620
6621 gen_helper_booke206_tlbre(cpu_env);
6622 #endif
6623 }
6624
6625 /* tlbsx - tlbsx. */
6626 static void gen_tlbsx_booke206(DisasContext *ctx)
6627 {
6628 #if defined(CONFIG_USER_ONLY)
6629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6630 #else
6631 TCGv t0;
6632 if (unlikely(ctx->pr)) {
6633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6634 return;
6635 }
6636
6637 if (rA(ctx->opcode)) {
6638 t0 = tcg_temp_new();
6639 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6640 } else {
6641 t0 = tcg_const_tl(0);
6642 }
6643
6644 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6645 gen_helper_booke206_tlbsx(cpu_env, t0);
6646 tcg_temp_free(t0);
6647 #endif
6648 }
6649
6650 /* tlbwe */
6651 static void gen_tlbwe_booke206(DisasContext *ctx)
6652 {
6653 #if defined(CONFIG_USER_ONLY)
6654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6655 #else
6656 if (unlikely(ctx->pr)) {
6657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6658 return;
6659 }
6660 gen_update_nip(ctx, ctx->nip - 4);
6661 gen_helper_booke206_tlbwe(cpu_env);
6662 #endif
6663 }
6664
6665 static void gen_tlbivax_booke206(DisasContext *ctx)
6666 {
6667 #if defined(CONFIG_USER_ONLY)
6668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6669 #else
6670 TCGv t0;
6671 if (unlikely(ctx->pr)) {
6672 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6673 return;
6674 }
6675
6676 t0 = tcg_temp_new();
6677 gen_addr_reg_index(ctx, t0);
6678
6679 gen_helper_booke206_tlbivax(cpu_env, t0);
6680 tcg_temp_free(t0);
6681 #endif
6682 }
6683
6684 static void gen_tlbilx_booke206(DisasContext *ctx)
6685 {
6686 #if defined(CONFIG_USER_ONLY)
6687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6688 #else
6689 TCGv t0;
6690 if (unlikely(ctx->pr)) {
6691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6692 return;
6693 }
6694
6695 t0 = tcg_temp_new();
6696 gen_addr_reg_index(ctx, t0);
6697
6698 switch((ctx->opcode >> 21) & 0x3) {
6699 case 0:
6700 gen_helper_booke206_tlbilx0(cpu_env, t0);
6701 break;
6702 case 1:
6703 gen_helper_booke206_tlbilx1(cpu_env, t0);
6704 break;
6705 case 3:
6706 gen_helper_booke206_tlbilx3(cpu_env, t0);
6707 break;
6708 default:
6709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6710 break;
6711 }
6712
6713 tcg_temp_free(t0);
6714 #endif
6715 }
6716
6717
6718 /* wrtee */
6719 static void gen_wrtee(DisasContext *ctx)
6720 {
6721 #if defined(CONFIG_USER_ONLY)
6722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6723 #else
6724 TCGv t0;
6725 if (unlikely(ctx->pr)) {
6726 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6727 return;
6728 }
6729 t0 = tcg_temp_new();
6730 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6731 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6732 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6733 tcg_temp_free(t0);
6734 /* Stop translation to have a chance to raise an exception
6735 * if we just set msr_ee to 1
6736 */
6737 gen_stop_exception(ctx);
6738 #endif
6739 }
6740
6741 /* wrteei */
6742 static void gen_wrteei(DisasContext *ctx)
6743 {
6744 #if defined(CONFIG_USER_ONLY)
6745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6746 #else
6747 if (unlikely(ctx->pr)) {
6748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6749 return;
6750 }
6751 if (ctx->opcode & 0x00008000) {
6752 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6753 /* Stop translation to have a chance to raise an exception */
6754 gen_stop_exception(ctx);
6755 } else {
6756 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6757 }
6758 #endif
6759 }
6760
6761 /* PowerPC 440 specific instructions */
6762
6763 /* dlmzb */
6764 static void gen_dlmzb(DisasContext *ctx)
6765 {
6766 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6767 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6768 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6769 tcg_temp_free_i32(t0);
6770 }
6771
6772 /* mbar replaces eieio on 440 */
6773 static void gen_mbar(DisasContext *ctx)
6774 {
6775 /* interpreted as no-op */
6776 }
6777
6778 /* msync replaces sync on 440 */
6779 static void gen_msync_4xx(DisasContext *ctx)
6780 {
6781 /* interpreted as no-op */
6782 }
6783
6784 /* icbt */
6785 static void gen_icbt_440(DisasContext *ctx)
6786 {
6787 /* interpreted as no-op */
6788 /* XXX: specification say this is treated as a load by the MMU
6789 * but does not generate any exception
6790 */
6791 }
6792
6793 /* Embedded.Processor Control */
6794
6795 static void gen_msgclr(DisasContext *ctx)
6796 {
6797 #if defined(CONFIG_USER_ONLY)
6798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6799 #else
6800 if (unlikely(ctx->pr)) {
6801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6802 return;
6803 }
6804
6805 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6806 #endif
6807 }
6808
6809 static void gen_msgsnd(DisasContext *ctx)
6810 {
6811 #if defined(CONFIG_USER_ONLY)
6812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6813 #else
6814 if (unlikely(ctx->pr)) {
6815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6816 return;
6817 }
6818
6819 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6820 #endif
6821 }
6822
6823 /*** Altivec vector extension ***/
6824 /* Altivec registers moves */
6825
6826 static inline TCGv_ptr gen_avr_ptr(int reg)
6827 {
6828 TCGv_ptr r = tcg_temp_new_ptr();
6829 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6830 return r;
6831 }
6832
6833 #define GEN_VR_LDX(name, opc2, opc3) \
6834 static void glue(gen_, name)(DisasContext *ctx) \
6835 { \
6836 TCGv EA; \
6837 if (unlikely(!ctx->altivec_enabled)) { \
6838 gen_exception(ctx, POWERPC_EXCP_VPU); \
6839 return; \
6840 } \
6841 gen_set_access_type(ctx, ACCESS_INT); \
6842 EA = tcg_temp_new(); \
6843 gen_addr_reg_index(ctx, EA); \
6844 tcg_gen_andi_tl(EA, EA, ~0xf); \
6845 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6846 64-bit byteswap already. */ \
6847 if (ctx->le_mode) { \
6848 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6849 tcg_gen_addi_tl(EA, EA, 8); \
6850 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6851 } else { \
6852 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6853 tcg_gen_addi_tl(EA, EA, 8); \
6854 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6855 } \
6856 tcg_temp_free(EA); \
6857 }
6858
6859 #define GEN_VR_STX(name, opc2, opc3) \
6860 static void gen_st##name(DisasContext *ctx) \
6861 { \
6862 TCGv EA; \
6863 if (unlikely(!ctx->altivec_enabled)) { \
6864 gen_exception(ctx, POWERPC_EXCP_VPU); \
6865 return; \
6866 } \
6867 gen_set_access_type(ctx, ACCESS_INT); \
6868 EA = tcg_temp_new(); \
6869 gen_addr_reg_index(ctx, EA); \
6870 tcg_gen_andi_tl(EA, EA, ~0xf); \
6871 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6872 64-bit byteswap already. */ \
6873 if (ctx->le_mode) { \
6874 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6875 tcg_gen_addi_tl(EA, EA, 8); \
6876 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6877 } else { \
6878 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6879 tcg_gen_addi_tl(EA, EA, 8); \
6880 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6881 } \
6882 tcg_temp_free(EA); \
6883 }
6884
6885 #define GEN_VR_LVE(name, opc2, opc3, size) \
6886 static void gen_lve##name(DisasContext *ctx) \
6887 { \
6888 TCGv EA; \
6889 TCGv_ptr rs; \
6890 if (unlikely(!ctx->altivec_enabled)) { \
6891 gen_exception(ctx, POWERPC_EXCP_VPU); \
6892 return; \
6893 } \
6894 gen_set_access_type(ctx, ACCESS_INT); \
6895 EA = tcg_temp_new(); \
6896 gen_addr_reg_index(ctx, EA); \
6897 if (size > 1) { \
6898 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6899 } \
6900 rs = gen_avr_ptr(rS(ctx->opcode)); \
6901 gen_helper_lve##name(cpu_env, rs, EA); \
6902 tcg_temp_free(EA); \
6903 tcg_temp_free_ptr(rs); \
6904 }
6905
6906 #define GEN_VR_STVE(name, opc2, opc3, size) \
6907 static void gen_stve##name(DisasContext *ctx) \
6908 { \
6909 TCGv EA; \
6910 TCGv_ptr rs; \
6911 if (unlikely(!ctx->altivec_enabled)) { \
6912 gen_exception(ctx, POWERPC_EXCP_VPU); \
6913 return; \
6914 } \
6915 gen_set_access_type(ctx, ACCESS_INT); \
6916 EA = tcg_temp_new(); \
6917 gen_addr_reg_index(ctx, EA); \
6918 if (size > 1) { \
6919 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6920 } \
6921 rs = gen_avr_ptr(rS(ctx->opcode)); \
6922 gen_helper_stve##name(cpu_env, rs, EA); \
6923 tcg_temp_free(EA); \
6924 tcg_temp_free_ptr(rs); \
6925 }
6926
6927 GEN_VR_LDX(lvx, 0x07, 0x03);
6928 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6929 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6930
6931 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6932 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6933 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6934
6935 GEN_VR_STX(svx, 0x07, 0x07);
6936 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6937 GEN_VR_STX(svxl, 0x07, 0x0F);
6938
6939 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6940 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6941 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6942
6943 static void gen_lvsl(DisasContext *ctx)
6944 {
6945 TCGv_ptr rd;
6946 TCGv EA;
6947 if (unlikely(!ctx->altivec_enabled)) {
6948 gen_exception(ctx, POWERPC_EXCP_VPU);
6949 return;
6950 }
6951 EA = tcg_temp_new();
6952 gen_addr_reg_index(ctx, EA);
6953 rd = gen_avr_ptr(rD(ctx->opcode));
6954 gen_helper_lvsl(rd, EA);
6955 tcg_temp_free(EA);
6956 tcg_temp_free_ptr(rd);
6957 }
6958
6959 static void gen_lvsr(DisasContext *ctx)
6960 {
6961 TCGv_ptr rd;
6962 TCGv EA;
6963 if (unlikely(!ctx->altivec_enabled)) {
6964 gen_exception(ctx, POWERPC_EXCP_VPU);
6965 return;
6966 }
6967 EA = tcg_temp_new();
6968 gen_addr_reg_index(ctx, EA);
6969 rd = gen_avr_ptr(rD(ctx->opcode));
6970 gen_helper_lvsr(rd, EA);
6971 tcg_temp_free(EA);
6972 tcg_temp_free_ptr(rd);
6973 }
6974
6975 static void gen_mfvscr(DisasContext *ctx)
6976 {
6977 TCGv_i32 t;
6978 if (unlikely(!ctx->altivec_enabled)) {
6979 gen_exception(ctx, POWERPC_EXCP_VPU);
6980 return;
6981 }
6982 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6983 t = tcg_temp_new_i32();
6984 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6985 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6986 tcg_temp_free_i32(t);
6987 }
6988
6989 static void gen_mtvscr(DisasContext *ctx)
6990 {
6991 TCGv_ptr p;
6992 if (unlikely(!ctx->altivec_enabled)) {
6993 gen_exception(ctx, POWERPC_EXCP_VPU);
6994 return;
6995 }
6996 p = gen_avr_ptr(rB(ctx->opcode));
6997 gen_helper_mtvscr(cpu_env, p);
6998 tcg_temp_free_ptr(p);
6999 }
7000
7001 /* Logical operations */
7002 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
7003 static void glue(gen_, name)(DisasContext *ctx) \
7004 { \
7005 if (unlikely(!ctx->altivec_enabled)) { \
7006 gen_exception(ctx, POWERPC_EXCP_VPU); \
7007 return; \
7008 } \
7009 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7010 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7011 }
7012
7013 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7014 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7015 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7016 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7017 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
7018 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7019 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7020 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7021
7022 #define GEN_VXFORM(name, opc2, opc3) \
7023 static void glue(gen_, name)(DisasContext *ctx) \
7024 { \
7025 TCGv_ptr ra, rb, rd; \
7026 if (unlikely(!ctx->altivec_enabled)) { \
7027 gen_exception(ctx, POWERPC_EXCP_VPU); \
7028 return; \
7029 } \
7030 ra = gen_avr_ptr(rA(ctx->opcode)); \
7031 rb = gen_avr_ptr(rB(ctx->opcode)); \
7032 rd = gen_avr_ptr(rD(ctx->opcode)); \
7033 gen_helper_##name (rd, ra, rb); \
7034 tcg_temp_free_ptr(ra); \
7035 tcg_temp_free_ptr(rb); \
7036 tcg_temp_free_ptr(rd); \
7037 }
7038
7039 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7040 static void glue(gen_, name)(DisasContext *ctx) \
7041 { \
7042 TCGv_ptr ra, rb, rd; \
7043 if (unlikely(!ctx->altivec_enabled)) { \
7044 gen_exception(ctx, POWERPC_EXCP_VPU); \
7045 return; \
7046 } \
7047 ra = gen_avr_ptr(rA(ctx->opcode)); \
7048 rb = gen_avr_ptr(rB(ctx->opcode)); \
7049 rd = gen_avr_ptr(rD(ctx->opcode)); \
7050 gen_helper_##name(cpu_env, rd, ra, rb); \
7051 tcg_temp_free_ptr(ra); \
7052 tcg_temp_free_ptr(rb); \
7053 tcg_temp_free_ptr(rd); \
7054 }
7055
7056 #define GEN_VXFORM3(name, opc2, opc3) \
7057 static void glue(gen_, name)(DisasContext *ctx) \
7058 { \
7059 TCGv_ptr ra, rb, rc, rd; \
7060 if (unlikely(!ctx->altivec_enabled)) { \
7061 gen_exception(ctx, POWERPC_EXCP_VPU); \
7062 return; \
7063 } \
7064 ra = gen_avr_ptr(rA(ctx->opcode)); \
7065 rb = gen_avr_ptr(rB(ctx->opcode)); \
7066 rc = gen_avr_ptr(rC(ctx->opcode)); \
7067 rd = gen_avr_ptr(rD(ctx->opcode)); \
7068 gen_helper_##name(rd, ra, rb, rc); \
7069 tcg_temp_free_ptr(ra); \
7070 tcg_temp_free_ptr(rb); \
7071 tcg_temp_free_ptr(rc); \
7072 tcg_temp_free_ptr(rd); \
7073 }
7074
7075 /*
7076 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7077 * an opcode bit. In general, these pairs come from different
7078 * versions of the ISA, so we must also support a pair of flags for
7079 * each instruction.
7080 */
7081 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7082 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7083 { \
7084 if ((Rc(ctx->opcode) == 0) && \
7085 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7086 gen_##name0(ctx); \
7087 } else if ((Rc(ctx->opcode) == 1) && \
7088 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7089 gen_##name1(ctx); \
7090 } else { \
7091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7092 } \
7093 }
7094
7095 GEN_VXFORM(vaddubm, 0, 0);
7096 GEN_VXFORM(vadduhm, 0, 1);
7097 GEN_VXFORM(vadduwm, 0, 2);
7098 GEN_VXFORM(vaddudm, 0, 3);
7099 GEN_VXFORM(vsububm, 0, 16);
7100 GEN_VXFORM(vsubuhm, 0, 17);
7101 GEN_VXFORM(vsubuwm, 0, 18);
7102 GEN_VXFORM(vsubudm, 0, 19);
7103 GEN_VXFORM(vmaxub, 1, 0);
7104 GEN_VXFORM(vmaxuh, 1, 1);
7105 GEN_VXFORM(vmaxuw, 1, 2);
7106 GEN_VXFORM(vmaxud, 1, 3);
7107 GEN_VXFORM(vmaxsb, 1, 4);
7108 GEN_VXFORM(vmaxsh, 1, 5);
7109 GEN_VXFORM(vmaxsw, 1, 6);
7110 GEN_VXFORM(vmaxsd, 1, 7);
7111 GEN_VXFORM(vminub, 1, 8);
7112 GEN_VXFORM(vminuh, 1, 9);
7113 GEN_VXFORM(vminuw, 1, 10);
7114 GEN_VXFORM(vminud, 1, 11);
7115 GEN_VXFORM(vminsb, 1, 12);
7116 GEN_VXFORM(vminsh, 1, 13);
7117 GEN_VXFORM(vminsw, 1, 14);
7118 GEN_VXFORM(vminsd, 1, 15);
7119 GEN_VXFORM(vavgub, 1, 16);
7120 GEN_VXFORM(vavguh, 1, 17);
7121 GEN_VXFORM(vavguw, 1, 18);
7122 GEN_VXFORM(vavgsb, 1, 20);
7123 GEN_VXFORM(vavgsh, 1, 21);
7124 GEN_VXFORM(vavgsw, 1, 22);
7125 GEN_VXFORM(vmrghb, 6, 0);
7126 GEN_VXFORM(vmrghh, 6, 1);
7127 GEN_VXFORM(vmrghw, 6, 2);
7128 GEN_VXFORM(vmrglb, 6, 4);
7129 GEN_VXFORM(vmrglh, 6, 5);
7130 GEN_VXFORM(vmrglw, 6, 6);
7131
7132 static void gen_vmrgew(DisasContext *ctx)
7133 {
7134 TCGv_i64 tmp;
7135 int VT, VA, VB;
7136 if (unlikely(!ctx->altivec_enabled)) {
7137 gen_exception(ctx, POWERPC_EXCP_VPU);
7138 return;
7139 }
7140 VT = rD(ctx->opcode);
7141 VA = rA(ctx->opcode);
7142 VB = rB(ctx->opcode);
7143 tmp = tcg_temp_new_i64();
7144 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7145 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7146 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7147 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7148 tcg_temp_free_i64(tmp);
7149 }
7150
7151 static void gen_vmrgow(DisasContext *ctx)
7152 {
7153 int VT, VA, VB;
7154 if (unlikely(!ctx->altivec_enabled)) {
7155 gen_exception(ctx, POWERPC_EXCP_VPU);
7156 return;
7157 }
7158 VT = rD(ctx->opcode);
7159 VA = rA(ctx->opcode);
7160 VB = rB(ctx->opcode);
7161
7162 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7163 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7164 }
7165
7166 GEN_VXFORM(vmuloub, 4, 0);
7167 GEN_VXFORM(vmulouh, 4, 1);
7168 GEN_VXFORM(vmulouw, 4, 2);
7169 GEN_VXFORM(vmuluwm, 4, 2);
7170 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7171 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7172 GEN_VXFORM(vmulosb, 4, 4);
7173 GEN_VXFORM(vmulosh, 4, 5);
7174 GEN_VXFORM(vmulosw, 4, 6);
7175 GEN_VXFORM(vmuleub, 4, 8);
7176 GEN_VXFORM(vmuleuh, 4, 9);
7177 GEN_VXFORM(vmuleuw, 4, 10);
7178 GEN_VXFORM(vmulesb, 4, 12);
7179 GEN_VXFORM(vmulesh, 4, 13);
7180 GEN_VXFORM(vmulesw, 4, 14);
7181 GEN_VXFORM(vslb, 2, 4);
7182 GEN_VXFORM(vslh, 2, 5);
7183 GEN_VXFORM(vslw, 2, 6);
7184 GEN_VXFORM(vsld, 2, 23);
7185 GEN_VXFORM(vsrb, 2, 8);
7186 GEN_VXFORM(vsrh, 2, 9);
7187 GEN_VXFORM(vsrw, 2, 10);
7188 GEN_VXFORM(vsrd, 2, 27);
7189 GEN_VXFORM(vsrab, 2, 12);
7190 GEN_VXFORM(vsrah, 2, 13);
7191 GEN_VXFORM(vsraw, 2, 14);
7192 GEN_VXFORM(vsrad, 2, 15);
7193 GEN_VXFORM(vslo, 6, 16);
7194 GEN_VXFORM(vsro, 6, 17);
7195 GEN_VXFORM(vaddcuw, 0, 6);
7196 GEN_VXFORM(vsubcuw, 0, 22);
7197 GEN_VXFORM_ENV(vaddubs, 0, 8);
7198 GEN_VXFORM_ENV(vadduhs, 0, 9);
7199 GEN_VXFORM_ENV(vadduws, 0, 10);
7200 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7201 GEN_VXFORM_ENV(vaddshs, 0, 13);
7202 GEN_VXFORM_ENV(vaddsws, 0, 14);
7203 GEN_VXFORM_ENV(vsububs, 0, 24);
7204 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7205 GEN_VXFORM_ENV(vsubuws, 0, 26);
7206 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7207 GEN_VXFORM_ENV(vsubshs, 0, 29);
7208 GEN_VXFORM_ENV(vsubsws, 0, 30);
7209 GEN_VXFORM(vadduqm, 0, 4);
7210 GEN_VXFORM(vaddcuq, 0, 5);
7211 GEN_VXFORM3(vaddeuqm, 30, 0);
7212 GEN_VXFORM3(vaddecuq, 30, 0);
7213 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7214 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7215 GEN_VXFORM(vsubuqm, 0, 20);
7216 GEN_VXFORM(vsubcuq, 0, 21);
7217 GEN_VXFORM3(vsubeuqm, 31, 0);
7218 GEN_VXFORM3(vsubecuq, 31, 0);
7219 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7220 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7221 GEN_VXFORM(vrlb, 2, 0);
7222 GEN_VXFORM(vrlh, 2, 1);
7223 GEN_VXFORM(vrlw, 2, 2);
7224 GEN_VXFORM(vrld, 2, 3);
7225 GEN_VXFORM(vsl, 2, 7);
7226 GEN_VXFORM(vsr, 2, 11);
7227 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7228 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7229 GEN_VXFORM_ENV(vpkudum, 7, 17);
7230 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7231 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7232 GEN_VXFORM_ENV(vpkudus, 7, 19);
7233 GEN_VXFORM_ENV(vpkshus, 7, 4);
7234 GEN_VXFORM_ENV(vpkswus, 7, 5);
7235 GEN_VXFORM_ENV(vpksdus, 7, 21);
7236 GEN_VXFORM_ENV(vpkshss, 7, 6);
7237 GEN_VXFORM_ENV(vpkswss, 7, 7);
7238 GEN_VXFORM_ENV(vpksdss, 7, 23);
7239 GEN_VXFORM(vpkpx, 7, 12);
7240 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7241 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7242 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7243 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7244 GEN_VXFORM_ENV(vsumsws, 4, 30);
7245 GEN_VXFORM_ENV(vaddfp, 5, 0);
7246 GEN_VXFORM_ENV(vsubfp, 5, 1);
7247 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7248 GEN_VXFORM_ENV(vminfp, 5, 17);
7249
7250 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7251 static void glue(gen_, name)(DisasContext *ctx) \
7252 { \
7253 TCGv_ptr ra, rb, rd; \
7254 if (unlikely(!ctx->altivec_enabled)) { \
7255 gen_exception(ctx, POWERPC_EXCP_VPU); \
7256 return; \
7257 } \
7258 ra = gen_avr_ptr(rA(ctx->opcode)); \
7259 rb = gen_avr_ptr(rB(ctx->opcode)); \
7260 rd = gen_avr_ptr(rD(ctx->opcode)); \
7261 gen_helper_##opname(cpu_env, rd, ra, rb); \
7262 tcg_temp_free_ptr(ra); \
7263 tcg_temp_free_ptr(rb); \
7264 tcg_temp_free_ptr(rd); \
7265 }
7266
7267 #define GEN_VXRFORM(name, opc2, opc3) \
7268 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7269 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7270
7271 /*
7272 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7273 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7274 * come from different versions of the ISA, so we must also support a
7275 * pair of flags for each instruction.
7276 */
7277 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7278 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7279 { \
7280 if ((Rc(ctx->opcode) == 0) && \
7281 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7282 if (Rc21(ctx->opcode) == 0) { \
7283 gen_##name0(ctx); \
7284 } else { \
7285 gen_##name0##_(ctx); \
7286 } \
7287 } else if ((Rc(ctx->opcode) == 1) && \
7288 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7289 if (Rc21(ctx->opcode) == 0) { \
7290 gen_##name1(ctx); \
7291 } else { \
7292 gen_##name1##_(ctx); \
7293 } \
7294 } else { \
7295 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7296 } \
7297 }
7298
7299 GEN_VXRFORM(vcmpequb, 3, 0)
7300 GEN_VXRFORM(vcmpequh, 3, 1)
7301 GEN_VXRFORM(vcmpequw, 3, 2)
7302 GEN_VXRFORM(vcmpequd, 3, 3)
7303 GEN_VXRFORM(vcmpgtsb, 3, 12)
7304 GEN_VXRFORM(vcmpgtsh, 3, 13)
7305 GEN_VXRFORM(vcmpgtsw, 3, 14)
7306 GEN_VXRFORM(vcmpgtsd, 3, 15)
7307 GEN_VXRFORM(vcmpgtub, 3, 8)
7308 GEN_VXRFORM(vcmpgtuh, 3, 9)
7309 GEN_VXRFORM(vcmpgtuw, 3, 10)
7310 GEN_VXRFORM(vcmpgtud, 3, 11)
7311 GEN_VXRFORM(vcmpeqfp, 3, 3)
7312 GEN_VXRFORM(vcmpgefp, 3, 7)
7313 GEN_VXRFORM(vcmpgtfp, 3, 11)
7314 GEN_VXRFORM(vcmpbfp, 3, 15)
7315
7316 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7317 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7318 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7319 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7320 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7321 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7322
7323 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7324 static void glue(gen_, name)(DisasContext *ctx) \
7325 { \
7326 TCGv_ptr rd; \
7327 TCGv_i32 simm; \
7328 if (unlikely(!ctx->altivec_enabled)) { \
7329 gen_exception(ctx, POWERPC_EXCP_VPU); \
7330 return; \
7331 } \
7332 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7333 rd = gen_avr_ptr(rD(ctx->opcode)); \
7334 gen_helper_##name (rd, simm); \
7335 tcg_temp_free_i32(simm); \
7336 tcg_temp_free_ptr(rd); \
7337 }
7338
7339 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7340 GEN_VXFORM_SIMM(vspltish, 6, 13);
7341 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7342
7343 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7344 static void glue(gen_, name)(DisasContext *ctx) \
7345 { \
7346 TCGv_ptr rb, rd; \
7347 if (unlikely(!ctx->altivec_enabled)) { \
7348 gen_exception(ctx, POWERPC_EXCP_VPU); \
7349 return; \
7350 } \
7351 rb = gen_avr_ptr(rB(ctx->opcode)); \
7352 rd = gen_avr_ptr(rD(ctx->opcode)); \
7353 gen_helper_##name (rd, rb); \
7354 tcg_temp_free_ptr(rb); \
7355 tcg_temp_free_ptr(rd); \
7356 }
7357
7358 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7359 static void glue(gen_, name)(DisasContext *ctx) \
7360 { \
7361 TCGv_ptr rb, rd; \
7362 \
7363 if (unlikely(!ctx->altivec_enabled)) { \
7364 gen_exception(ctx, POWERPC_EXCP_VPU); \
7365 return; \
7366 } \
7367 rb = gen_avr_ptr(rB(ctx->opcode)); \
7368 rd = gen_avr_ptr(rD(ctx->opcode)); \
7369 gen_helper_##name(cpu_env, rd, rb); \
7370 tcg_temp_free_ptr(rb); \
7371 tcg_temp_free_ptr(rd); \
7372 }
7373
7374 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7375 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7376 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7377 GEN_VXFORM_NOA(vupklsb, 7, 10);
7378 GEN_VXFORM_NOA(vupklsh, 7, 11);
7379 GEN_VXFORM_NOA(vupklsw, 7, 27);
7380 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7381 GEN_VXFORM_NOA(vupklpx, 7, 15);
7382 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7383 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7384 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7385 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7386 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7387 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7388 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7389 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7390
7391 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7392 static void glue(gen_, name)(DisasContext *ctx) \
7393 { \
7394 TCGv_ptr rd; \
7395 TCGv_i32 simm; \
7396 if (unlikely(!ctx->altivec_enabled)) { \
7397 gen_exception(ctx, POWERPC_EXCP_VPU); \
7398 return; \
7399 } \
7400 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7401 rd = gen_avr_ptr(rD(ctx->opcode)); \
7402 gen_helper_##name (rd, simm); \
7403 tcg_temp_free_i32(simm); \
7404 tcg_temp_free_ptr(rd); \
7405 }
7406
7407 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7408 static void glue(gen_, name)(DisasContext *ctx) \
7409 { \
7410 TCGv_ptr rb, rd; \
7411 TCGv_i32 uimm; \
7412 if (unlikely(!ctx->altivec_enabled)) { \
7413 gen_exception(ctx, POWERPC_EXCP_VPU); \
7414 return; \
7415 } \
7416 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7417 rb = gen_avr_ptr(rB(ctx->opcode)); \
7418 rd = gen_avr_ptr(rD(ctx->opcode)); \
7419 gen_helper_##name (rd, rb, uimm); \
7420 tcg_temp_free_i32(uimm); \
7421 tcg_temp_free_ptr(rb); \
7422 tcg_temp_free_ptr(rd); \
7423 }
7424
7425 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7426 static void glue(gen_, name)(DisasContext *ctx) \
7427 { \
7428 TCGv_ptr rb, rd; \
7429 TCGv_i32 uimm; \
7430 \
7431 if (unlikely(!ctx->altivec_enabled)) { \
7432 gen_exception(ctx, POWERPC_EXCP_VPU); \
7433 return; \
7434 } \
7435 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7436 rb = gen_avr_ptr(rB(ctx->opcode)); \
7437 rd = gen_avr_ptr(rD(ctx->opcode)); \
7438 gen_helper_##name(cpu_env, rd, rb, uimm); \
7439 tcg_temp_free_i32(uimm); \
7440 tcg_temp_free_ptr(rb); \
7441 tcg_temp_free_ptr(rd); \
7442 }
7443
7444 GEN_VXFORM_UIMM(vspltb, 6, 8);
7445 GEN_VXFORM_UIMM(vsplth, 6, 9);
7446 GEN_VXFORM_UIMM(vspltw, 6, 10);
7447 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7448 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7449 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7450 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7451
7452 static void gen_vsldoi(DisasContext *ctx)
7453 {
7454 TCGv_ptr ra, rb, rd;
7455 TCGv_i32 sh;
7456 if (unlikely(!ctx->altivec_enabled)) {
7457 gen_exception(ctx, POWERPC_EXCP_VPU);
7458 return;
7459 }
7460 ra = gen_avr_ptr(rA(ctx->opcode));
7461 rb = gen_avr_ptr(rB(ctx->opcode));
7462 rd = gen_avr_ptr(rD(ctx->opcode));
7463 sh = tcg_const_i32(VSH(ctx->opcode));
7464 gen_helper_vsldoi (rd, ra, rb, sh);
7465 tcg_temp_free_ptr(ra);
7466 tcg_temp_free_ptr(rb);
7467 tcg_temp_free_ptr(rd);
7468 tcg_temp_free_i32(sh);
7469 }
7470
7471 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7472 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7473 { \
7474 TCGv_ptr ra, rb, rc, rd; \
7475 if (unlikely(!ctx->altivec_enabled)) { \
7476 gen_exception(ctx, POWERPC_EXCP_VPU); \
7477 return; \
7478 } \
7479 ra = gen_avr_ptr(rA(ctx->opcode)); \
7480 rb = gen_avr_ptr(rB(ctx->opcode)); \
7481 rc = gen_avr_ptr(rC(ctx->opcode)); \
7482 rd = gen_avr_ptr(rD(ctx->opcode)); \
7483 if (Rc(ctx->opcode)) { \
7484 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7485 } else { \
7486 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7487 } \
7488 tcg_temp_free_ptr(ra); \
7489 tcg_temp_free_ptr(rb); \
7490 tcg_temp_free_ptr(rc); \
7491 tcg_temp_free_ptr(rd); \
7492 }
7493
7494 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7495
7496 static void gen_vmladduhm(DisasContext *ctx)
7497 {
7498 TCGv_ptr ra, rb, rc, rd;
7499 if (unlikely(!ctx->altivec_enabled)) {
7500 gen_exception(ctx, POWERPC_EXCP_VPU);
7501 return;
7502 }
7503 ra = gen_avr_ptr(rA(ctx->opcode));
7504 rb = gen_avr_ptr(rB(ctx->opcode));
7505 rc = gen_avr_ptr(rC(ctx->opcode));
7506 rd = gen_avr_ptr(rD(ctx->opcode));
7507 gen_helper_vmladduhm(rd, ra, rb, rc);
7508 tcg_temp_free_ptr(ra);
7509 tcg_temp_free_ptr(rb);
7510 tcg_temp_free_ptr(rc);
7511 tcg_temp_free_ptr(rd);
7512 }
7513
7514 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7515 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7516 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7517 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7518 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7519
7520 GEN_VXFORM_NOA(vclzb, 1, 28)
7521 GEN_VXFORM_NOA(vclzh, 1, 29)
7522 GEN_VXFORM_NOA(vclzw, 1, 30)
7523 GEN_VXFORM_NOA(vclzd, 1, 31)
7524 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7525 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7526 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7527 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7528 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7529 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7530 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7531 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7532 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7533 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7534 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7535 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7536 GEN_VXFORM(vbpermq, 6, 21);
7537 GEN_VXFORM_NOA(vgbbd, 6, 20);
7538 GEN_VXFORM(vpmsumb, 4, 16)
7539 GEN_VXFORM(vpmsumh, 4, 17)
7540 GEN_VXFORM(vpmsumw, 4, 18)
7541 GEN_VXFORM(vpmsumd, 4, 19)
7542
7543 #define GEN_BCD(op) \
7544 static void gen_##op(DisasContext *ctx) \
7545 { \
7546 TCGv_ptr ra, rb, rd; \
7547 TCGv_i32 ps; \
7548 \
7549 if (unlikely(!ctx->altivec_enabled)) { \
7550 gen_exception(ctx, POWERPC_EXCP_VPU); \
7551 return; \
7552 } \
7553 \
7554 ra = gen_avr_ptr(rA(ctx->opcode)); \
7555 rb = gen_avr_ptr(rB(ctx->opcode)); \
7556 rd = gen_avr_ptr(rD(ctx->opcode)); \
7557 \
7558 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7559 \
7560 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7561 \
7562 tcg_temp_free_ptr(ra); \
7563 tcg_temp_free_ptr(rb); \
7564 tcg_temp_free_ptr(rd); \
7565 tcg_temp_free_i32(ps); \
7566 }
7567
7568 GEN_BCD(bcdadd)
7569 GEN_BCD(bcdsub)
7570
7571 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7572 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7573 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7574 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7575 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7576 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7577 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7578 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7579
7580 static void gen_vsbox(DisasContext *ctx)
7581 {
7582 TCGv_ptr ra, rd;
7583 if (unlikely(!ctx->altivec_enabled)) {
7584 gen_exception(ctx, POWERPC_EXCP_VPU);
7585 return;
7586 }
7587 ra = gen_avr_ptr(rA(ctx->opcode));
7588 rd = gen_avr_ptr(rD(ctx->opcode));
7589 gen_helper_vsbox(rd, ra);
7590 tcg_temp_free_ptr(ra);
7591 tcg_temp_free_ptr(rd);
7592 }
7593
7594 GEN_VXFORM(vcipher, 4, 20)
7595 GEN_VXFORM(vcipherlast, 4, 20)
7596 GEN_VXFORM(vncipher, 4, 21)
7597 GEN_VXFORM(vncipherlast, 4, 21)
7598
7599 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7600 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7601 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7602 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7603
7604 #define VSHASIGMA(op) \
7605 static void gen_##op(DisasContext *ctx) \
7606 { \
7607 TCGv_ptr ra, rd; \
7608 TCGv_i32 st_six; \
7609 if (unlikely(!ctx->altivec_enabled)) { \
7610 gen_exception(ctx, POWERPC_EXCP_VPU); \
7611 return; \
7612 } \
7613 ra = gen_avr_ptr(rA(ctx->opcode)); \
7614 rd = gen_avr_ptr(rD(ctx->opcode)); \
7615 st_six = tcg_const_i32(rB(ctx->opcode)); \
7616 gen_helper_##op(rd, ra, st_six); \
7617 tcg_temp_free_ptr(ra); \
7618 tcg_temp_free_ptr(rd); \
7619 tcg_temp_free_i32(st_six); \
7620 }
7621
7622 VSHASIGMA(vshasigmaw)
7623 VSHASIGMA(vshasigmad)
7624
7625 GEN_VXFORM3(vpermxor, 22, 0xFF)
7626 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7627 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7628
7629 /*** VSX extension ***/
7630
7631 static inline TCGv_i64 cpu_vsrh(int n)
7632 {
7633 if (n < 32) {
7634 return cpu_fpr[n];
7635 } else {
7636 return cpu_avrh[n-32];
7637 }
7638 }
7639
7640 static inline TCGv_i64 cpu_vsrl(int n)
7641 {
7642 if (n < 32) {
7643 return cpu_vsr[n];
7644 } else {
7645 return cpu_avrl[n-32];
7646 }
7647 }
7648
7649 #define VSX_LOAD_SCALAR(name, operation) \
7650 static void gen_##name(DisasContext *ctx) \
7651 { \
7652 TCGv EA; \
7653 if (unlikely(!ctx->vsx_enabled)) { \
7654 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7655 return; \
7656 } \
7657 gen_set_access_type(ctx, ACCESS_INT); \
7658 EA = tcg_temp_new(); \
7659 gen_addr_reg_index(ctx, EA); \
7660 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7661 /* NOTE: cpu_vsrl is undefined */ \
7662 tcg_temp_free(EA); \
7663 }
7664
7665 VSX_LOAD_SCALAR(lxsdx, ld64)
7666 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7667 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7668 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7669
7670 static void gen_lxvd2x(DisasContext *ctx)
7671 {
7672 TCGv EA;
7673 if (unlikely(!ctx->vsx_enabled)) {
7674 gen_exception(ctx, POWERPC_EXCP_VSXU);
7675 return;
7676 }
7677 gen_set_access_type(ctx, ACCESS_INT);
7678 EA = tcg_temp_new();
7679 gen_addr_reg_index(ctx, EA);
7680 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7681 tcg_gen_addi_tl(EA, EA, 8);
7682 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7683 tcg_temp_free(EA);
7684 }
7685
7686 static void gen_lxvdsx(DisasContext *ctx)
7687 {
7688 TCGv EA;
7689 if (unlikely(!ctx->vsx_enabled)) {
7690 gen_exception(ctx, POWERPC_EXCP_VSXU);
7691 return;
7692 }
7693 gen_set_access_type(ctx, ACCESS_INT);
7694 EA = tcg_temp_new();
7695 gen_addr_reg_index(ctx, EA);
7696 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7697 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7698 tcg_temp_free(EA);
7699 }
7700
7701 static void gen_lxvw4x(DisasContext *ctx)
7702 {
7703 TCGv EA;
7704 TCGv_i64 tmp;
7705 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7706 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7707 if (unlikely(!ctx->vsx_enabled)) {
7708 gen_exception(ctx, POWERPC_EXCP_VSXU);
7709 return;
7710 }
7711 gen_set_access_type(ctx, ACCESS_INT);
7712 EA = tcg_temp_new();
7713 tmp = tcg_temp_new_i64();
7714
7715 gen_addr_reg_index(ctx, EA);
7716 gen_qemu_ld32u_i64(ctx, tmp, EA);
7717 tcg_gen_addi_tl(EA, EA, 4);
7718 gen_qemu_ld32u_i64(ctx, xth, EA);
7719 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7720
7721 tcg_gen_addi_tl(EA, EA, 4);
7722 gen_qemu_ld32u_i64(ctx, tmp, EA);
7723 tcg_gen_addi_tl(EA, EA, 4);
7724 gen_qemu_ld32u_i64(ctx, xtl, EA);
7725 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7726
7727 tcg_temp_free(EA);
7728 tcg_temp_free_i64(tmp);
7729 }
7730
7731 #define VSX_STORE_SCALAR(name, operation) \
7732 static void gen_##name(DisasContext *ctx) \
7733 { \
7734 TCGv EA; \
7735 if (unlikely(!ctx->vsx_enabled)) { \
7736 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7737 return; \
7738 } \
7739 gen_set_access_type(ctx, ACCESS_INT); \
7740 EA = tcg_temp_new(); \
7741 gen_addr_reg_index(ctx, EA); \
7742 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7743 tcg_temp_free(EA); \
7744 }
7745
7746 VSX_STORE_SCALAR(stxsdx, st64)
7747 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7748 VSX_STORE_SCALAR(stxsspx, st32fs)
7749
7750 static void gen_stxvd2x(DisasContext *ctx)
7751 {
7752 TCGv EA;
7753 if (unlikely(!ctx->vsx_enabled)) {
7754 gen_exception(ctx, POWERPC_EXCP_VSXU);
7755 return;
7756 }
7757 gen_set_access_type(ctx, ACCESS_INT);
7758 EA = tcg_temp_new();
7759 gen_addr_reg_index(ctx, EA);
7760 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7761 tcg_gen_addi_tl(EA, EA, 8);
7762 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7763 tcg_temp_free(EA);
7764 }
7765
7766 static void gen_stxvw4x(DisasContext *ctx)
7767 {
7768 TCGv_i64 tmp;
7769 TCGv EA;
7770 if (unlikely(!ctx->vsx_enabled)) {
7771 gen_exception(ctx, POWERPC_EXCP_VSXU);
7772 return;
7773 }
7774 gen_set_access_type(ctx, ACCESS_INT);
7775 EA = tcg_temp_new();
7776 gen_addr_reg_index(ctx, EA);
7777 tmp = tcg_temp_new_i64();
7778
7779 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7780 gen_qemu_st32_i64(ctx, tmp, EA);
7781 tcg_gen_addi_tl(EA, EA, 4);
7782 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7783
7784 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7785 tcg_gen_addi_tl(EA, EA, 4);
7786 gen_qemu_st32_i64(ctx, tmp, EA);
7787 tcg_gen_addi_tl(EA, EA, 4);
7788 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7789
7790 tcg_temp_free(EA);
7791 tcg_temp_free_i64(tmp);
7792 }
7793
7794 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7795 static void gen_##name(DisasContext *ctx) \
7796 { \
7797 if (xS(ctx->opcode) < 32) { \
7798 if (unlikely(!ctx->fpu_enabled)) { \
7799 gen_exception(ctx, POWERPC_EXCP_FPU); \
7800 return; \
7801 } \
7802 } else { \
7803 if (unlikely(!ctx->altivec_enabled)) { \
7804 gen_exception(ctx, POWERPC_EXCP_VPU); \
7805 return; \
7806 } \
7807 } \
7808 TCGv_i64 tmp = tcg_temp_new_i64(); \
7809 tcg_gen_##tcgop1(tmp, source); \
7810 tcg_gen_##tcgop2(target, tmp); \
7811 tcg_temp_free_i64(tmp); \
7812 }
7813
7814
7815 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7816 cpu_vsrh(xS(ctx->opcode)))
7817 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7818 cpu_gpr[rA(ctx->opcode)])
7819 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7820 cpu_gpr[rA(ctx->opcode)])
7821
7822 #if defined(TARGET_PPC64)
7823 #define MV_VSRD(name, target, source) \
7824 static void gen_##name(DisasContext *ctx) \
7825 { \
7826 if (xS(ctx->opcode) < 32) { \
7827 if (unlikely(!ctx->fpu_enabled)) { \
7828 gen_exception(ctx, POWERPC_EXCP_FPU); \
7829 return; \
7830 } \
7831 } else { \
7832 if (unlikely(!ctx->altivec_enabled)) { \
7833 gen_exception(ctx, POWERPC_EXCP_VPU); \
7834 return; \
7835 } \
7836 } \
7837 tcg_gen_mov_i64(target, source); \
7838 }
7839
7840 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7841 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7842
7843 #endif
7844
7845 static void gen_xxpermdi(DisasContext *ctx)
7846 {
7847 if (unlikely(!ctx->vsx_enabled)) {
7848 gen_exception(ctx, POWERPC_EXCP_VSXU);
7849 return;
7850 }
7851
7852 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7853 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7854 TCGv_i64 xh, xl;
7855
7856 xh = tcg_temp_new_i64();
7857 xl = tcg_temp_new_i64();
7858
7859 if ((DM(ctx->opcode) & 2) == 0) {
7860 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7861 } else {
7862 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7863 }
7864 if ((DM(ctx->opcode) & 1) == 0) {
7865 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7866 } else {
7867 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7868 }
7869
7870 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7871 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7872
7873 tcg_temp_free_i64(xh);
7874 tcg_temp_free_i64(xl);
7875 } else {
7876 if ((DM(ctx->opcode) & 2) == 0) {
7877 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7878 } else {
7879 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7880 }
7881 if ((DM(ctx->opcode) & 1) == 0) {
7882 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7883 } else {
7884 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7885 }
7886 }
7887 }
7888
7889 #define OP_ABS 1
7890 #define OP_NABS 2
7891 #define OP_NEG 3
7892 #define OP_CPSGN 4
7893 #define SGN_MASK_DP 0x8000000000000000ull
7894 #define SGN_MASK_SP 0x8000000080000000ull
7895
7896 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7897 static void glue(gen_, name)(DisasContext * ctx) \
7898 { \
7899 TCGv_i64 xb, sgm; \
7900 if (unlikely(!ctx->vsx_enabled)) { \
7901 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7902 return; \
7903 } \
7904 xb = tcg_temp_new_i64(); \
7905 sgm = tcg_temp_new_i64(); \
7906 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7907 tcg_gen_movi_i64(sgm, sgn_mask); \
7908 switch (op) { \
7909 case OP_ABS: { \
7910 tcg_gen_andc_i64(xb, xb, sgm); \
7911 break; \
7912 } \
7913 case OP_NABS: { \
7914 tcg_gen_or_i64(xb, xb, sgm); \
7915 break; \
7916 } \
7917 case OP_NEG: { \
7918 tcg_gen_xor_i64(xb, xb, sgm); \
7919 break; \
7920 } \
7921 case OP_CPSGN: { \
7922 TCGv_i64 xa = tcg_temp_new_i64(); \
7923 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7924 tcg_gen_and_i64(xa, xa, sgm); \
7925 tcg_gen_andc_i64(xb, xb, sgm); \
7926 tcg_gen_or_i64(xb, xb, xa); \
7927 tcg_temp_free_i64(xa); \
7928 break; \
7929 } \
7930 } \
7931 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7932 tcg_temp_free_i64(xb); \
7933 tcg_temp_free_i64(sgm); \
7934 }
7935
7936 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7937 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7938 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7939 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7940
7941 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7942 static void glue(gen_, name)(DisasContext * ctx) \
7943 { \
7944 TCGv_i64 xbh, xbl, sgm; \
7945 if (unlikely(!ctx->vsx_enabled)) { \
7946 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7947 return; \
7948 } \
7949 xbh = tcg_temp_new_i64(); \
7950 xbl = tcg_temp_new_i64(); \
7951 sgm = tcg_temp_new_i64(); \
7952 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7953 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7954 tcg_gen_movi_i64(sgm, sgn_mask); \
7955 switch (op) { \
7956 case OP_ABS: { \
7957 tcg_gen_andc_i64(xbh, xbh, sgm); \
7958 tcg_gen_andc_i64(xbl, xbl, sgm); \
7959 break; \
7960 } \
7961 case OP_NABS: { \
7962 tcg_gen_or_i64(xbh, xbh, sgm); \
7963 tcg_gen_or_i64(xbl, xbl, sgm); \
7964 break; \
7965 } \
7966 case OP_NEG: { \
7967 tcg_gen_xor_i64(xbh, xbh, sgm); \
7968 tcg_gen_xor_i64(xbl, xbl, sgm); \
7969 break; \
7970 } \
7971 case OP_CPSGN: { \
7972 TCGv_i64 xah = tcg_temp_new_i64(); \
7973 TCGv_i64 xal = tcg_temp_new_i64(); \
7974 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7975 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7976 tcg_gen_and_i64(xah, xah, sgm); \
7977 tcg_gen_and_i64(xal, xal, sgm); \
7978 tcg_gen_andc_i64(xbh, xbh, sgm); \
7979 tcg_gen_andc_i64(xbl, xbl, sgm); \
7980 tcg_gen_or_i64(xbh, xbh, xah); \
7981 tcg_gen_or_i64(xbl, xbl, xal); \
7982 tcg_temp_free_i64(xah); \
7983 tcg_temp_free_i64(xal); \
7984 break; \
7985 } \
7986 } \
7987 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7988 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7989 tcg_temp_free_i64(xbh); \
7990 tcg_temp_free_i64(xbl); \
7991 tcg_temp_free_i64(sgm); \
7992 }
7993
7994 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7995 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7996 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7997 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7998 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7999 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
8000 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
8001 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
8002
8003 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8004 static void gen_##name(DisasContext * ctx) \
8005 { \
8006 TCGv_i32 opc; \
8007 if (unlikely(!ctx->vsx_enabled)) { \
8008 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8009 return; \
8010 } \
8011 /* NIP cannot be restored if the memory exception comes from an helper */ \
8012 gen_update_nip(ctx, ctx->nip - 4); \
8013 opc = tcg_const_i32(ctx->opcode); \
8014 gen_helper_##name(cpu_env, opc); \
8015 tcg_temp_free_i32(opc); \
8016 }
8017
8018 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8019 static void gen_##name(DisasContext * ctx) \
8020 { \
8021 if (unlikely(!ctx->vsx_enabled)) { \
8022 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8023 return; \
8024 } \
8025 /* NIP cannot be restored if the exception comes */ \
8026 /* from a helper. */ \
8027 gen_update_nip(ctx, ctx->nip - 4); \
8028 \
8029 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8030 cpu_vsrh(xB(ctx->opcode))); \
8031 }
8032
8033 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8056 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8058 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8070
8071 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8072 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8073 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8074 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8075 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8076 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8077 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8078 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8079 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8080 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8081 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8082 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8083 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8084 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8085 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8086 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8087 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8088
8089 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8090 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8102 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8103 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8104 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8105 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8106 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8107 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8108 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8109 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8110 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8111 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8112 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8113 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8114 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8115 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8116 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8117 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8118 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8119 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8120 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8121 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8122 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8123 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8124 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8125
8126 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8127 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8128 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8129 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8130 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8131 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8132 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8133 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8134 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8135 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8136 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8137 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8138 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8139 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8140 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8141 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8142 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8143 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8144 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8145 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8146 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8147 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8148 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8149 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8150 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8151 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8152 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8153 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8154 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8155 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8156 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8157 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8158 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8159 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8160 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8161 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8162
8163 #define VSX_LOGICAL(name, tcg_op) \
8164 static void glue(gen_, name)(DisasContext * ctx) \
8165 { \
8166 if (unlikely(!ctx->vsx_enabled)) { \
8167 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8168 return; \
8169 } \
8170 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8171 cpu_vsrh(xB(ctx->opcode))); \
8172 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8173 cpu_vsrl(xB(ctx->opcode))); \
8174 }
8175
8176 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8177 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8178 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8179 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8180 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8181 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8182 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8183 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8184
8185 #define VSX_XXMRG(name, high) \
8186 static void glue(gen_, name)(DisasContext * ctx) \
8187 { \
8188 TCGv_i64 a0, a1, b0, b1; \
8189 if (unlikely(!ctx->vsx_enabled)) { \
8190 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8191 return; \
8192 } \
8193 a0 = tcg_temp_new_i64(); \
8194 a1 = tcg_temp_new_i64(); \
8195 b0 = tcg_temp_new_i64(); \
8196 b1 = tcg_temp_new_i64(); \
8197 if (high) { \
8198 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8199 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8200 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8201 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8202 } else { \
8203 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8204 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8205 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8206 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8207 } \
8208 tcg_gen_shri_i64(a0, a0, 32); \
8209 tcg_gen_shri_i64(b0, b0, 32); \
8210 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8211 b0, a0, 32, 32); \
8212 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8213 b1, a1, 32, 32); \
8214 tcg_temp_free_i64(a0); \
8215 tcg_temp_free_i64(a1); \
8216 tcg_temp_free_i64(b0); \
8217 tcg_temp_free_i64(b1); \
8218 }
8219
8220 VSX_XXMRG(xxmrghw, 1)
8221 VSX_XXMRG(xxmrglw, 0)
8222
8223 static void gen_xxsel(DisasContext * ctx)
8224 {
8225 TCGv_i64 a, b, c;
8226 if (unlikely(!ctx->vsx_enabled)) {
8227 gen_exception(ctx, POWERPC_EXCP_VSXU);
8228 return;
8229 }
8230 a = tcg_temp_new_i64();
8231 b = tcg_temp_new_i64();
8232 c = tcg_temp_new_i64();
8233
8234 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8235 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8236 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8237
8238 tcg_gen_and_i64(b, b, c);
8239 tcg_gen_andc_i64(a, a, c);
8240 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8241
8242 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8243 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8244 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8245
8246 tcg_gen_and_i64(b, b, c);
8247 tcg_gen_andc_i64(a, a, c);
8248 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8249
8250 tcg_temp_free_i64(a);
8251 tcg_temp_free_i64(b);
8252 tcg_temp_free_i64(c);
8253 }
8254
8255 static void gen_xxspltw(DisasContext *ctx)
8256 {
8257 TCGv_i64 b, b2;
8258 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8259 cpu_vsrl(xB(ctx->opcode)) :
8260 cpu_vsrh(xB(ctx->opcode));
8261
8262 if (unlikely(!ctx->vsx_enabled)) {
8263 gen_exception(ctx, POWERPC_EXCP_VSXU);
8264 return;
8265 }
8266
8267 b = tcg_temp_new_i64();
8268 b2 = tcg_temp_new_i64();
8269
8270 if (UIM(ctx->opcode) & 1) {
8271 tcg_gen_ext32u_i64(b, vsr);
8272 } else {
8273 tcg_gen_shri_i64(b, vsr, 32);
8274 }
8275
8276 tcg_gen_shli_i64(b2, b, 32);
8277 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8278 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8279
8280 tcg_temp_free_i64(b);
8281 tcg_temp_free_i64(b2);
8282 }
8283
8284 static void gen_xxsldwi(DisasContext *ctx)
8285 {
8286 TCGv_i64 xth, xtl;
8287 if (unlikely(!ctx->vsx_enabled)) {
8288 gen_exception(ctx, POWERPC_EXCP_VSXU);
8289 return;
8290 }
8291 xth = tcg_temp_new_i64();
8292 xtl = tcg_temp_new_i64();
8293
8294 switch (SHW(ctx->opcode)) {
8295 case 0: {
8296 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8297 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8298 break;
8299 }
8300 case 1: {
8301 TCGv_i64 t0 = tcg_temp_new_i64();
8302 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8303 tcg_gen_shli_i64(xth, xth, 32);
8304 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8305 tcg_gen_shri_i64(t0, t0, 32);
8306 tcg_gen_or_i64(xth, xth, t0);
8307 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8308 tcg_gen_shli_i64(xtl, xtl, 32);
8309 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8310 tcg_gen_shri_i64(t0, t0, 32);
8311 tcg_gen_or_i64(xtl, xtl, t0);
8312 tcg_temp_free_i64(t0);
8313 break;
8314 }
8315 case 2: {
8316 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8317 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8318 break;
8319 }
8320 case 3: {
8321 TCGv_i64 t0 = tcg_temp_new_i64();
8322 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8323 tcg_gen_shli_i64(xth, xth, 32);
8324 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8325 tcg_gen_shri_i64(t0, t0, 32);
8326 tcg_gen_or_i64(xth, xth, t0);
8327 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8328 tcg_gen_shli_i64(xtl, xtl, 32);
8329 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8330 tcg_gen_shri_i64(t0, t0, 32);
8331 tcg_gen_or_i64(xtl, xtl, t0);
8332 tcg_temp_free_i64(t0);
8333 break;
8334 }
8335 }
8336
8337 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8338 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8339
8340 tcg_temp_free_i64(xth);
8341 tcg_temp_free_i64(xtl);
8342 }
8343
8344 /*** Decimal Floating Point ***/
8345
8346 static inline TCGv_ptr gen_fprp_ptr(int reg)
8347 {
8348 TCGv_ptr r = tcg_temp_new_ptr();
8349 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8350 return r;
8351 }
8352
8353 #define GEN_DFP_T_A_B_Rc(name) \
8354 static void gen_##name(DisasContext *ctx) \
8355 { \
8356 TCGv_ptr rd, ra, rb; \
8357 if (unlikely(!ctx->fpu_enabled)) { \
8358 gen_exception(ctx, POWERPC_EXCP_FPU); \
8359 return; \
8360 } \
8361 gen_update_nip(ctx, ctx->nip - 4); \
8362 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8363 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8364 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8365 gen_helper_##name(cpu_env, rd, ra, rb); \
8366 if (unlikely(Rc(ctx->opcode) != 0)) { \
8367 gen_set_cr1_from_fpscr(ctx); \
8368 } \
8369 tcg_temp_free_ptr(rd); \
8370 tcg_temp_free_ptr(ra); \
8371 tcg_temp_free_ptr(rb); \
8372 }
8373
8374 #define GEN_DFP_BF_A_B(name) \
8375 static void gen_##name(DisasContext *ctx) \
8376 { \
8377 TCGv_ptr ra, rb; \
8378 if (unlikely(!ctx->fpu_enabled)) { \
8379 gen_exception(ctx, POWERPC_EXCP_FPU); \
8380 return; \
8381 } \
8382 gen_update_nip(ctx, ctx->nip - 4); \
8383 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8384 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8385 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8386 cpu_env, ra, rb); \
8387 tcg_temp_free_ptr(ra); \
8388 tcg_temp_free_ptr(rb); \
8389 }
8390
8391 #define GEN_DFP_BF_A_DCM(name) \
8392 static void gen_##name(DisasContext *ctx) \
8393 { \
8394 TCGv_ptr ra; \
8395 TCGv_i32 dcm; \
8396 if (unlikely(!ctx->fpu_enabled)) { \
8397 gen_exception(ctx, POWERPC_EXCP_FPU); \
8398 return; \
8399 } \
8400 gen_update_nip(ctx, ctx->nip - 4); \
8401 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8402 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8403 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8404 cpu_env, ra, dcm); \
8405 tcg_temp_free_ptr(ra); \
8406 tcg_temp_free_i32(dcm); \
8407 }
8408
8409 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8410 static void gen_##name(DisasContext *ctx) \
8411 { \
8412 TCGv_ptr rt, rb; \
8413 TCGv_i32 u32_1, u32_2; \
8414 if (unlikely(!ctx->fpu_enabled)) { \
8415 gen_exception(ctx, POWERPC_EXCP_FPU); \
8416 return; \
8417 } \
8418 gen_update_nip(ctx, ctx->nip - 4); \
8419 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8420 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8421 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8422 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8423 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8424 if (unlikely(Rc(ctx->opcode) != 0)) { \
8425 gen_set_cr1_from_fpscr(ctx); \
8426 } \
8427 tcg_temp_free_ptr(rt); \
8428 tcg_temp_free_ptr(rb); \
8429 tcg_temp_free_i32(u32_1); \
8430 tcg_temp_free_i32(u32_2); \
8431 }
8432
8433 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8434 static void gen_##name(DisasContext *ctx) \
8435 { \
8436 TCGv_ptr rt, ra, rb; \
8437 TCGv_i32 i32; \
8438 if (unlikely(!ctx->fpu_enabled)) { \
8439 gen_exception(ctx, POWERPC_EXCP_FPU); \
8440 return; \
8441 } \
8442 gen_update_nip(ctx, ctx->nip - 4); \
8443 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8444 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8445 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8446 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8447 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8448 if (unlikely(Rc(ctx->opcode) != 0)) { \
8449 gen_set_cr1_from_fpscr(ctx); \
8450 } \
8451 tcg_temp_free_ptr(rt); \
8452 tcg_temp_free_ptr(rb); \
8453 tcg_temp_free_ptr(ra); \
8454 tcg_temp_free_i32(i32); \
8455 }
8456
8457 #define GEN_DFP_T_B_Rc(name) \
8458 static void gen_##name(DisasContext *ctx) \
8459 { \
8460 TCGv_ptr rt, rb; \
8461 if (unlikely(!ctx->fpu_enabled)) { \
8462 gen_exception(ctx, POWERPC_EXCP_FPU); \
8463 return; \
8464 } \
8465 gen_update_nip(ctx, ctx->nip - 4); \
8466 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8467 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8468 gen_helper_##name(cpu_env, rt, rb); \
8469 if (unlikely(Rc(ctx->opcode) != 0)) { \
8470 gen_set_cr1_from_fpscr(ctx); \
8471 } \
8472 tcg_temp_free_ptr(rt); \
8473 tcg_temp_free_ptr(rb); \
8474 }
8475
8476 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8477 static void gen_##name(DisasContext *ctx) \
8478 { \
8479 TCGv_ptr rt, rs; \
8480 TCGv_i32 i32; \
8481 if (unlikely(!ctx->fpu_enabled)) { \
8482 gen_exception(ctx, POWERPC_EXCP_FPU); \
8483 return; \
8484 } \
8485 gen_update_nip(ctx, ctx->nip - 4); \
8486 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8487 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8488 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8489 gen_helper_##name(cpu_env, rt, rs, i32); \
8490 if (unlikely(Rc(ctx->opcode) != 0)) { \
8491 gen_set_cr1_from_fpscr(ctx); \
8492 } \
8493 tcg_temp_free_ptr(rt); \
8494 tcg_temp_free_ptr(rs); \
8495 tcg_temp_free_i32(i32); \
8496 }
8497
8498 GEN_DFP_T_A_B_Rc(dadd)
8499 GEN_DFP_T_A_B_Rc(daddq)
8500 GEN_DFP_T_A_B_Rc(dsub)
8501 GEN_DFP_T_A_B_Rc(dsubq)
8502 GEN_DFP_T_A_B_Rc(dmul)
8503 GEN_DFP_T_A_B_Rc(dmulq)
8504 GEN_DFP_T_A_B_Rc(ddiv)
8505 GEN_DFP_T_A_B_Rc(ddivq)
8506 GEN_DFP_BF_A_B(dcmpu)
8507 GEN_DFP_BF_A_B(dcmpuq)
8508 GEN_DFP_BF_A_B(dcmpo)
8509 GEN_DFP_BF_A_B(dcmpoq)
8510 GEN_DFP_BF_A_DCM(dtstdc)
8511 GEN_DFP_BF_A_DCM(dtstdcq)
8512 GEN_DFP_BF_A_DCM(dtstdg)
8513 GEN_DFP_BF_A_DCM(dtstdgq)
8514 GEN_DFP_BF_A_B(dtstex)
8515 GEN_DFP_BF_A_B(dtstexq)
8516 GEN_DFP_BF_A_B(dtstsf)
8517 GEN_DFP_BF_A_B(dtstsfq)
8518 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8519 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8520 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8521 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8522 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8523 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8524 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8525 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8526 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8527 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8528 GEN_DFP_T_B_Rc(dctdp)
8529 GEN_DFP_T_B_Rc(dctqpq)
8530 GEN_DFP_T_B_Rc(drsp)
8531 GEN_DFP_T_B_Rc(drdpq)
8532 GEN_DFP_T_B_Rc(dcffix)
8533 GEN_DFP_T_B_Rc(dcffixq)
8534 GEN_DFP_T_B_Rc(dctfix)
8535 GEN_DFP_T_B_Rc(dctfixq)
8536 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8537 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8538 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8539 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8540 GEN_DFP_T_B_Rc(dxex)
8541 GEN_DFP_T_B_Rc(dxexq)
8542 GEN_DFP_T_A_B_Rc(diex)
8543 GEN_DFP_T_A_B_Rc(diexq)
8544 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8545 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8546 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8547 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8548
8549 /*** SPE extension ***/
8550 /* Register moves */
8551
8552 static inline void gen_evmra(DisasContext *ctx)
8553 {
8554
8555 if (unlikely(!ctx->spe_enabled)) {
8556 gen_exception(ctx, POWERPC_EXCP_SPEU);
8557 return;
8558 }
8559
8560 TCGv_i64 tmp = tcg_temp_new_i64();
8561
8562 /* tmp := rA_lo + rA_hi << 32 */
8563 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8564
8565 /* spe_acc := tmp */
8566 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8567 tcg_temp_free_i64(tmp);
8568
8569 /* rD := rA */
8570 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8571 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8572 }
8573
8574 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8575 {
8576 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8577 }
8578
8579 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8580 {
8581 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8582 }
8583
8584 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8585 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8586 { \
8587 if (Rc(ctx->opcode)) \
8588 gen_##name1(ctx); \
8589 else \
8590 gen_##name0(ctx); \
8591 }
8592
8593 /* Handler for undefined SPE opcodes */
8594 static inline void gen_speundef(DisasContext *ctx)
8595 {
8596 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8597 }
8598
8599 /* SPE logic */
8600 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8601 static inline void gen_##name(DisasContext *ctx) \
8602 { \
8603 if (unlikely(!ctx->spe_enabled)) { \
8604 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8605 return; \
8606 } \
8607 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8608 cpu_gpr[rB(ctx->opcode)]); \
8609 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8610 cpu_gprh[rB(ctx->opcode)]); \
8611 }
8612
8613 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8614 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8615 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8616 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8617 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8618 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8619 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8620 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8621
8622 /* SPE logic immediate */
8623 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8624 static inline void gen_##name(DisasContext *ctx) \
8625 { \
8626 TCGv_i32 t0; \
8627 if (unlikely(!ctx->spe_enabled)) { \
8628 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8629 return; \
8630 } \
8631 t0 = tcg_temp_new_i32(); \
8632 \
8633 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8634 tcg_opi(t0, t0, rB(ctx->opcode)); \
8635 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8636 \
8637 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8638 tcg_opi(t0, t0, rB(ctx->opcode)); \
8639 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8640 \
8641 tcg_temp_free_i32(t0); \
8642 }
8643 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8644 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8645 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8646 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8647
8648 /* SPE arithmetic */
8649 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8650 static inline void gen_##name(DisasContext *ctx) \
8651 { \
8652 TCGv_i32 t0; \
8653 if (unlikely(!ctx->spe_enabled)) { \
8654 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8655 return; \
8656 } \
8657 t0 = tcg_temp_new_i32(); \
8658 \
8659 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8660 tcg_op(t0, t0); \
8661 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8662 \
8663 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8664 tcg_op(t0, t0); \
8665 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8666 \
8667 tcg_temp_free_i32(t0); \
8668 }
8669
8670 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8671 {
8672 TCGLabel *l1 = gen_new_label();
8673 TCGLabel *l2 = gen_new_label();
8674
8675 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8676 tcg_gen_neg_i32(ret, arg1);
8677 tcg_gen_br(l2);
8678 gen_set_label(l1);
8679 tcg_gen_mov_i32(ret, arg1);
8680 gen_set_label(l2);
8681 }
8682 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8683 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8684 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8685 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8686 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8687 {
8688 tcg_gen_addi_i32(ret, arg1, 0x8000);
8689 tcg_gen_ext16u_i32(ret, ret);
8690 }
8691 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8692 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8693 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8694
8695 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8696 static inline void gen_##name(DisasContext *ctx) \
8697 { \
8698 TCGv_i32 t0, t1; \
8699 if (unlikely(!ctx->spe_enabled)) { \
8700 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8701 return; \
8702 } \
8703 t0 = tcg_temp_new_i32(); \
8704 t1 = tcg_temp_new_i32(); \
8705 \
8706 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8707 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8708 tcg_op(t0, t0, t1); \
8709 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8710 \
8711 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8712 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8713 tcg_op(t0, t0, t1); \
8714 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8715 \
8716 tcg_temp_free_i32(t0); \
8717 tcg_temp_free_i32(t1); \
8718 }
8719
8720 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8721 {
8722 TCGLabel *l1 = gen_new_label();
8723 TCGLabel *l2 = gen_new_label();
8724 TCGv_i32 t0 = tcg_temp_local_new_i32();
8725
8726 /* No error here: 6 bits are used */
8727 tcg_gen_andi_i32(t0, arg2, 0x3F);
8728 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8729 tcg_gen_shr_i32(ret, arg1, t0);
8730 tcg_gen_br(l2);
8731 gen_set_label(l1);
8732 tcg_gen_movi_i32(ret, 0);
8733 gen_set_label(l2);
8734 tcg_temp_free_i32(t0);
8735 }
8736 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8737 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8738 {
8739 TCGLabel *l1 = gen_new_label();
8740 TCGLabel *l2 = gen_new_label();
8741 TCGv_i32 t0 = tcg_temp_local_new_i32();
8742
8743 /* No error here: 6 bits are used */
8744 tcg_gen_andi_i32(t0, arg2, 0x3F);
8745 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8746 tcg_gen_sar_i32(ret, arg1, t0);
8747 tcg_gen_br(l2);
8748 gen_set_label(l1);
8749 tcg_gen_movi_i32(ret, 0);
8750 gen_set_label(l2);
8751 tcg_temp_free_i32(t0);
8752 }
8753 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8754 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8755 {
8756 TCGLabel *l1 = gen_new_label();
8757 TCGLabel *l2 = gen_new_label();
8758 TCGv_i32 t0 = tcg_temp_local_new_i32();
8759
8760 /* No error here: 6 bits are used */
8761 tcg_gen_andi_i32(t0, arg2, 0x3F);
8762 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8763 tcg_gen_shl_i32(ret, arg1, t0);
8764 tcg_gen_br(l2);
8765 gen_set_label(l1);
8766 tcg_gen_movi_i32(ret, 0);
8767 gen_set_label(l2);
8768 tcg_temp_free_i32(t0);
8769 }
8770 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8771 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8772 {
8773 TCGv_i32 t0 = tcg_temp_new_i32();
8774 tcg_gen_andi_i32(t0, arg2, 0x1F);
8775 tcg_gen_rotl_i32(ret, arg1, t0);
8776 tcg_temp_free_i32(t0);
8777 }
8778 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8779 static inline void gen_evmergehi(DisasContext *ctx)
8780 {
8781 if (unlikely(!ctx->spe_enabled)) {
8782 gen_exception(ctx, POWERPC_EXCP_SPEU);
8783 return;
8784 }
8785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8786 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8787 }
8788 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8789 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8790 {
8791 tcg_gen_sub_i32(ret, arg2, arg1);
8792 }
8793 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8794
8795 /* SPE arithmetic immediate */
8796 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8797 static inline void gen_##name(DisasContext *ctx) \
8798 { \
8799 TCGv_i32 t0; \
8800 if (unlikely(!ctx->spe_enabled)) { \
8801 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8802 return; \
8803 } \
8804 t0 = tcg_temp_new_i32(); \
8805 \
8806 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8807 tcg_op(t0, t0, rA(ctx->opcode)); \
8808 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8809 \
8810 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8811 tcg_op(t0, t0, rA(ctx->opcode)); \
8812 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8813 \
8814 tcg_temp_free_i32(t0); \
8815 }
8816 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8817 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8818
8819 /* SPE comparison */
8820 #define GEN_SPEOP_COMP(name, tcg_cond) \
8821 static inline void gen_##name(DisasContext *ctx) \
8822 { \
8823 if (unlikely(!ctx->spe_enabled)) { \
8824 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8825 return; \
8826 } \
8827 TCGLabel *l1 = gen_new_label(); \
8828 TCGLabel *l2 = gen_new_label(); \
8829 TCGLabel *l3 = gen_new_label(); \
8830 TCGLabel *l4 = gen_new_label(); \
8831 \
8832 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8833 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8834 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8835 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8836 \
8837 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8838 cpu_gpr[rB(ctx->opcode)], l1); \
8839 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8840 tcg_gen_br(l2); \
8841 gen_set_label(l1); \
8842 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8843 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8844 gen_set_label(l2); \
8845 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8846 cpu_gprh[rB(ctx->opcode)], l3); \
8847 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8848 ~(CRF_CH | CRF_CH_AND_CL)); \
8849 tcg_gen_br(l4); \
8850 gen_set_label(l3); \
8851 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8852 CRF_CH | CRF_CH_OR_CL); \
8853 gen_set_label(l4); \
8854 }
8855 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8856 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8857 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8858 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8859 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8860
8861 /* SPE misc */
8862 static inline void gen_brinc(DisasContext *ctx)
8863 {
8864 /* Note: brinc is usable even if SPE is disabled */
8865 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8866 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8867 }
8868 static inline void gen_evmergelo(DisasContext *ctx)
8869 {
8870 if (unlikely(!ctx->spe_enabled)) {
8871 gen_exception(ctx, POWERPC_EXCP_SPEU);
8872 return;
8873 }
8874 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8875 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8876 }
8877 static inline void gen_evmergehilo(DisasContext *ctx)
8878 {
8879 if (unlikely(!ctx->spe_enabled)) {
8880 gen_exception(ctx, POWERPC_EXCP_SPEU);
8881 return;
8882 }
8883 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8884 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8885 }
8886 static inline void gen_evmergelohi(DisasContext *ctx)
8887 {
8888 if (unlikely(!ctx->spe_enabled)) {
8889 gen_exception(ctx, POWERPC_EXCP_SPEU);
8890 return;
8891 }
8892 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8893 TCGv tmp = tcg_temp_new();
8894 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8895 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8896 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8897 tcg_temp_free(tmp);
8898 } else {
8899 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8900 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8901 }
8902 }
8903 static inline void gen_evsplati(DisasContext *ctx)
8904 {
8905 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8906
8907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8908 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8909 }
8910 static inline void gen_evsplatfi(DisasContext *ctx)
8911 {
8912 uint64_t imm = rA(ctx->opcode) << 27;
8913
8914 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8915 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8916 }
8917
8918 static inline void gen_evsel(DisasContext *ctx)
8919 {
8920 TCGLabel *l1 = gen_new_label();
8921 TCGLabel *l2 = gen_new_label();
8922 TCGLabel *l3 = gen_new_label();
8923 TCGLabel *l4 = gen_new_label();
8924 TCGv_i32 t0 = tcg_temp_local_new_i32();
8925
8926 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8927 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8928 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8929 tcg_gen_br(l2);
8930 gen_set_label(l1);
8931 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8932 gen_set_label(l2);
8933 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8934 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8935 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8936 tcg_gen_br(l4);
8937 gen_set_label(l3);
8938 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8939 gen_set_label(l4);
8940 tcg_temp_free_i32(t0);
8941 }
8942
8943 static void gen_evsel0(DisasContext *ctx)
8944 {
8945 gen_evsel(ctx);
8946 }
8947
8948 static void gen_evsel1(DisasContext *ctx)
8949 {
8950 gen_evsel(ctx);
8951 }
8952
8953 static void gen_evsel2(DisasContext *ctx)
8954 {
8955 gen_evsel(ctx);
8956 }
8957
8958 static void gen_evsel3(DisasContext *ctx)
8959 {
8960 gen_evsel(ctx);
8961 }
8962
8963 /* Multiply */
8964
8965 static inline void gen_evmwumi(DisasContext *ctx)
8966 {
8967 TCGv_i64 t0, t1;
8968
8969 if (unlikely(!ctx->spe_enabled)) {
8970 gen_exception(ctx, POWERPC_EXCP_SPEU);
8971 return;
8972 }
8973
8974 t0 = tcg_temp_new_i64();
8975 t1 = tcg_temp_new_i64();
8976
8977 /* t0 := rA; t1 := rB */
8978 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8979 tcg_gen_ext32u_i64(t0, t0);
8980 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8981 tcg_gen_ext32u_i64(t1, t1);
8982
8983 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8984
8985 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8986
8987 tcg_temp_free_i64(t0);
8988 tcg_temp_free_i64(t1);
8989 }
8990
8991 static inline void gen_evmwumia(DisasContext *ctx)
8992 {
8993 TCGv_i64 tmp;
8994
8995 if (unlikely(!ctx->spe_enabled)) {
8996 gen_exception(ctx, POWERPC_EXCP_SPEU);
8997 return;
8998 }
8999
9000 gen_evmwumi(ctx); /* rD := rA * rB */
9001
9002 tmp = tcg_temp_new_i64();
9003
9004 /* acc := rD */
9005 gen_load_gpr64(tmp, rD(ctx->opcode));
9006 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9007 tcg_temp_free_i64(tmp);
9008 }
9009
9010 static inline void gen_evmwumiaa(DisasContext *ctx)
9011 {
9012 TCGv_i64 acc;
9013 TCGv_i64 tmp;
9014
9015 if (unlikely(!ctx->spe_enabled)) {
9016 gen_exception(ctx, POWERPC_EXCP_SPEU);
9017 return;
9018 }
9019
9020 gen_evmwumi(ctx); /* rD := rA * rB */
9021
9022 acc = tcg_temp_new_i64();
9023 tmp = tcg_temp_new_i64();
9024
9025 /* tmp := rD */
9026 gen_load_gpr64(tmp, rD(ctx->opcode));
9027
9028 /* Load acc */
9029 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9030
9031 /* acc := tmp + acc */
9032 tcg_gen_add_i64(acc, acc, tmp);
9033
9034 /* Store acc */
9035 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9036
9037 /* rD := acc */
9038 gen_store_gpr64(rD(ctx->opcode), acc);
9039
9040 tcg_temp_free_i64(acc);
9041 tcg_temp_free_i64(tmp);
9042 }
9043
9044 static inline void gen_evmwsmi(DisasContext *ctx)
9045 {
9046 TCGv_i64 t0, t1;
9047
9048 if (unlikely(!ctx->spe_enabled)) {
9049 gen_exception(ctx, POWERPC_EXCP_SPEU);
9050 return;
9051 }
9052
9053 t0 = tcg_temp_new_i64();
9054 t1 = tcg_temp_new_i64();
9055
9056 /* t0 := rA; t1 := rB */
9057 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9058 tcg_gen_ext32s_i64(t0, t0);
9059 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9060 tcg_gen_ext32s_i64(t1, t1);
9061
9062 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9063
9064 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9065
9066 tcg_temp_free_i64(t0);
9067 tcg_temp_free_i64(t1);
9068 }
9069
9070 static inline void gen_evmwsmia(DisasContext *ctx)
9071 {
9072 TCGv_i64 tmp;
9073
9074 gen_evmwsmi(ctx); /* rD := rA * rB */
9075
9076 tmp = tcg_temp_new_i64();
9077
9078 /* acc := rD */
9079 gen_load_gpr64(tmp, rD(ctx->opcode));
9080 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9081
9082 tcg_temp_free_i64(tmp);
9083 }
9084
9085 static inline void gen_evmwsmiaa(DisasContext *ctx)
9086 {
9087 TCGv_i64 acc = tcg_temp_new_i64();
9088 TCGv_i64 tmp = tcg_temp_new_i64();
9089
9090 gen_evmwsmi(ctx); /* rD := rA * rB */
9091
9092 acc = tcg_temp_new_i64();
9093 tmp = tcg_temp_new_i64();
9094
9095 /* tmp := rD */
9096 gen_load_gpr64(tmp, rD(ctx->opcode));
9097
9098 /* Load acc */
9099 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9100
9101 /* acc := tmp + acc */
9102 tcg_gen_add_i64(acc, acc, tmp);
9103
9104 /* Store acc */
9105 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9106
9107 /* rD := acc */
9108 gen_store_gpr64(rD(ctx->opcode), acc);
9109
9110 tcg_temp_free_i64(acc);
9111 tcg_temp_free_i64(tmp);
9112 }
9113
9114 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9115 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9116 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9117 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9118 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9119 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9120 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9121 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9122 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9123 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9124 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9125 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9126 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9127 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9128 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9129 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9130 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9131 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9132 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9133 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9134 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9135 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9136 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9137 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9138 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9139 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9140 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9141 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9142 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9143
9144 /* SPE load and stores */
9145 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9146 {
9147 target_ulong uimm = rB(ctx->opcode);
9148
9149 if (rA(ctx->opcode) == 0) {
9150 tcg_gen_movi_tl(EA, uimm << sh);
9151 } else {
9152 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9153 if (NARROW_MODE(ctx)) {
9154 tcg_gen_ext32u_tl(EA, EA);
9155 }
9156 }
9157 }
9158
9159 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9160 {
9161 TCGv_i64 t0 = tcg_temp_new_i64();
9162 gen_qemu_ld64(ctx, t0, addr);
9163 gen_store_gpr64(rD(ctx->opcode), t0);
9164 tcg_temp_free_i64(t0);
9165 }
9166
9167 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9168 {
9169 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9170 gen_addr_add(ctx, addr, addr, 4);
9171 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9172 }
9173
9174 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9175 {
9176 TCGv t0 = tcg_temp_new();
9177 gen_qemu_ld16u(ctx, t0, addr);
9178 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9179 gen_addr_add(ctx, addr, addr, 2);
9180 gen_qemu_ld16u(ctx, t0, addr);
9181 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9182 gen_addr_add(ctx, addr, addr, 2);
9183 gen_qemu_ld16u(ctx, t0, addr);
9184 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9185 gen_addr_add(ctx, addr, addr, 2);
9186 gen_qemu_ld16u(ctx, t0, addr);
9187 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9188 tcg_temp_free(t0);
9189 }
9190
9191 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9192 {
9193 TCGv t0 = tcg_temp_new();
9194 gen_qemu_ld16u(ctx, t0, addr);
9195 tcg_gen_shli_tl(t0, t0, 16);
9196 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9197 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9198 tcg_temp_free(t0);
9199 }
9200
9201 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9202 {
9203 TCGv t0 = tcg_temp_new();
9204 gen_qemu_ld16u(ctx, t0, addr);
9205 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9206 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9207 tcg_temp_free(t0);
9208 }
9209
9210 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9211 {
9212 TCGv t0 = tcg_temp_new();
9213 gen_qemu_ld16s(ctx, t0, addr);
9214 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9215 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9216 tcg_temp_free(t0);
9217 }
9218
9219 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9220 {
9221 TCGv t0 = tcg_temp_new();
9222 gen_qemu_ld16u(ctx, t0, addr);
9223 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9224 gen_addr_add(ctx, addr, addr, 2);
9225 gen_qemu_ld16u(ctx, t0, addr);
9226 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9227 tcg_temp_free(t0);
9228 }
9229
9230 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9231 {
9232 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9233 gen_addr_add(ctx, addr, addr, 2);
9234 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9235 }
9236
9237 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9238 {
9239 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9240 gen_addr_add(ctx, addr, addr, 2);
9241 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9242 }
9243
9244 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9245 {
9246 TCGv t0 = tcg_temp_new();
9247 gen_qemu_ld32u(ctx, t0, addr);
9248 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9249 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9250 tcg_temp_free(t0);
9251 }
9252
9253 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9254 {
9255 TCGv t0 = tcg_temp_new();
9256 gen_qemu_ld16u(ctx, t0, addr);
9257 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9258 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9259 gen_addr_add(ctx, addr, addr, 2);
9260 gen_qemu_ld16u(ctx, t0, addr);
9261 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9262 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9263 tcg_temp_free(t0);
9264 }
9265
9266 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9267 {
9268 TCGv_i64 t0 = tcg_temp_new_i64();
9269 gen_load_gpr64(t0, rS(ctx->opcode));
9270 gen_qemu_st64(ctx, t0, addr);
9271 tcg_temp_free_i64(t0);
9272 }
9273
9274 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9275 {
9276 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9277 gen_addr_add(ctx, addr, addr, 4);
9278 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9279 }
9280
9281 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9282 {
9283 TCGv t0 = tcg_temp_new();
9284 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9285 gen_qemu_st16(ctx, t0, addr);
9286 gen_addr_add(ctx, addr, addr, 2);
9287 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9288 gen_addr_add(ctx, addr, addr, 2);
9289 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9290 gen_qemu_st16(ctx, t0, addr);
9291 tcg_temp_free(t0);
9292 gen_addr_add(ctx, addr, addr, 2);
9293 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9294 }
9295
9296 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9297 {
9298 TCGv t0 = tcg_temp_new();
9299 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9300 gen_qemu_st16(ctx, t0, addr);
9301 gen_addr_add(ctx, addr, addr, 2);
9302 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9303 gen_qemu_st16(ctx, t0, addr);
9304 tcg_temp_free(t0);
9305 }
9306
9307 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9308 {
9309 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9310 gen_addr_add(ctx, addr, addr, 2);
9311 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9312 }
9313
9314 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9315 {
9316 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9317 }
9318
9319 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9320 {
9321 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9322 }
9323
9324 #define GEN_SPEOP_LDST(name, opc2, sh) \
9325 static void glue(gen_, name)(DisasContext *ctx) \
9326 { \
9327 TCGv t0; \
9328 if (unlikely(!ctx->spe_enabled)) { \
9329 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9330 return; \
9331 } \
9332 gen_set_access_type(ctx, ACCESS_INT); \
9333 t0 = tcg_temp_new(); \
9334 if (Rc(ctx->opcode)) { \
9335 gen_addr_spe_imm_index(ctx, t0, sh); \
9336 } else { \
9337 gen_addr_reg_index(ctx, t0); \
9338 } \
9339 gen_op_##name(ctx, t0); \
9340 tcg_temp_free(t0); \
9341 }
9342
9343 GEN_SPEOP_LDST(evldd, 0x00, 3);
9344 GEN_SPEOP_LDST(evldw, 0x01, 3);
9345 GEN_SPEOP_LDST(evldh, 0x02, 3);
9346 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9347 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9348 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9349 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9350 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9351 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9352 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9353 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9354
9355 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9356 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9357 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9358 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9359 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9360 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9361 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9362
9363 /* Multiply and add - TODO */
9364 #if 0
9365 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9366 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9367 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9368 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9370 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9371 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9372 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9373 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9374 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9375 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9376 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9377
9378 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9379 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9380 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9381 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9382 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9383 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9384 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9385 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9386 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9387 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9388 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9389 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9390
9391 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9392 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9393 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9394 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9395 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9396
9397 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9398 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9399 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9400 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9401 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9402 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9403 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9404 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9405 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9406 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9407 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9408 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9409
9410 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9411 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9412 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9413 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9414
9415 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9416 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9417 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9418 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9419 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9420 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9421 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9422 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9423 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9424 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9425 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9426 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9427
9428 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9429 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9430 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9431 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9432 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9433 #endif
9434
9435 /*** SPE floating-point extension ***/
9436 #define GEN_SPEFPUOP_CONV_32_32(name) \
9437 static inline void gen_##name(DisasContext *ctx) \
9438 { \
9439 TCGv_i32 t0 = tcg_temp_new_i32(); \
9440 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9441 gen_helper_##name(t0, cpu_env, t0); \
9442 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9443 tcg_temp_free_i32(t0); \
9444 }
9445 #define GEN_SPEFPUOP_CONV_32_64(name) \
9446 static inline void gen_##name(DisasContext *ctx) \
9447 { \
9448 TCGv_i64 t0 = tcg_temp_new_i64(); \
9449 TCGv_i32 t1 = tcg_temp_new_i32(); \
9450 gen_load_gpr64(t0, rB(ctx->opcode)); \
9451 gen_helper_##name(t1, cpu_env, t0); \
9452 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9453 tcg_temp_free_i64(t0); \
9454 tcg_temp_free_i32(t1); \
9455 }
9456 #define GEN_SPEFPUOP_CONV_64_32(name) \
9457 static inline void gen_##name(DisasContext *ctx) \
9458 { \
9459 TCGv_i64 t0 = tcg_temp_new_i64(); \
9460 TCGv_i32 t1 = tcg_temp_new_i32(); \
9461 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9462 gen_helper_##name(t0, cpu_env, t1); \
9463 gen_store_gpr64(rD(ctx->opcode), t0); \
9464 tcg_temp_free_i64(t0); \
9465 tcg_temp_free_i32(t1); \
9466 }
9467 #define GEN_SPEFPUOP_CONV_64_64(name) \
9468 static inline void gen_##name(DisasContext *ctx) \
9469 { \
9470 TCGv_i64 t0 = tcg_temp_new_i64(); \
9471 gen_load_gpr64(t0, rB(ctx->opcode)); \
9472 gen_helper_##name(t0, cpu_env, t0); \
9473 gen_store_gpr64(rD(ctx->opcode), t0); \
9474 tcg_temp_free_i64(t0); \
9475 }
9476 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9477 static inline void gen_##name(DisasContext *ctx) \
9478 { \
9479 TCGv_i32 t0, t1; \
9480 if (unlikely(!ctx->spe_enabled)) { \
9481 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9482 return; \
9483 } \
9484 t0 = tcg_temp_new_i32(); \
9485 t1 = tcg_temp_new_i32(); \
9486 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9487 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9488 gen_helper_##name(t0, cpu_env, t0, t1); \
9489 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9490 \
9491 tcg_temp_free_i32(t0); \
9492 tcg_temp_free_i32(t1); \
9493 }
9494 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9495 static inline void gen_##name(DisasContext *ctx) \
9496 { \
9497 TCGv_i64 t0, t1; \
9498 if (unlikely(!ctx->spe_enabled)) { \
9499 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9500 return; \
9501 } \
9502 t0 = tcg_temp_new_i64(); \
9503 t1 = tcg_temp_new_i64(); \
9504 gen_load_gpr64(t0, rA(ctx->opcode)); \
9505 gen_load_gpr64(t1, rB(ctx->opcode)); \
9506 gen_helper_##name(t0, cpu_env, t0, t1); \
9507 gen_store_gpr64(rD(ctx->opcode), t0); \
9508 tcg_temp_free_i64(t0); \
9509 tcg_temp_free_i64(t1); \
9510 }
9511 #define GEN_SPEFPUOP_COMP_32(name) \
9512 static inline void gen_##name(DisasContext *ctx) \
9513 { \
9514 TCGv_i32 t0, t1; \
9515 if (unlikely(!ctx->spe_enabled)) { \
9516 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9517 return; \
9518 } \
9519 t0 = tcg_temp_new_i32(); \
9520 t1 = tcg_temp_new_i32(); \
9521 \
9522 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9523 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9524 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9525 \
9526 tcg_temp_free_i32(t0); \
9527 tcg_temp_free_i32(t1); \
9528 }
9529 #define GEN_SPEFPUOP_COMP_64(name) \
9530 static inline void gen_##name(DisasContext *ctx) \
9531 { \
9532 TCGv_i64 t0, t1; \
9533 if (unlikely(!ctx->spe_enabled)) { \
9534 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9535 return; \
9536 } \
9537 t0 = tcg_temp_new_i64(); \
9538 t1 = tcg_temp_new_i64(); \
9539 gen_load_gpr64(t0, rA(ctx->opcode)); \
9540 gen_load_gpr64(t1, rB(ctx->opcode)); \
9541 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9542 tcg_temp_free_i64(t0); \
9543 tcg_temp_free_i64(t1); \
9544 }
9545
9546 /* Single precision floating-point vectors operations */
9547 /* Arithmetic */
9548 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9549 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9550 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9551 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9552 static inline void gen_evfsabs(DisasContext *ctx)
9553 {
9554 if (unlikely(!ctx->spe_enabled)) {
9555 gen_exception(ctx, POWERPC_EXCP_SPEU);
9556 return;
9557 }
9558 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9559 ~0x80000000);
9560 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9561 ~0x80000000);
9562 }
9563 static inline void gen_evfsnabs(DisasContext *ctx)
9564 {
9565 if (unlikely(!ctx->spe_enabled)) {
9566 gen_exception(ctx, POWERPC_EXCP_SPEU);
9567 return;
9568 }
9569 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9570 0x80000000);
9571 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9572 0x80000000);
9573 }
9574 static inline void gen_evfsneg(DisasContext *ctx)
9575 {
9576 if (unlikely(!ctx->spe_enabled)) {
9577 gen_exception(ctx, POWERPC_EXCP_SPEU);
9578 return;
9579 }
9580 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9581 0x80000000);
9582 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9583 0x80000000);
9584 }
9585
9586 /* Conversion */
9587 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9588 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9589 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9590 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9591 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9592 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9593 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9594 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9595 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9596 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9597
9598 /* Comparison */
9599 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9600 GEN_SPEFPUOP_COMP_64(evfscmplt);
9601 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9602 GEN_SPEFPUOP_COMP_64(evfststgt);
9603 GEN_SPEFPUOP_COMP_64(evfststlt);
9604 GEN_SPEFPUOP_COMP_64(evfststeq);
9605
9606 /* Opcodes definitions */
9607 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9608 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9609 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9610 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9611 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9612 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9613 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9614 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9615 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9616 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9617 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9618 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9619 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9620 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9621
9622 /* Single precision floating-point operations */
9623 /* Arithmetic */
9624 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9625 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9626 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9627 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9628 static inline void gen_efsabs(DisasContext *ctx)
9629 {
9630 if (unlikely(!ctx->spe_enabled)) {
9631 gen_exception(ctx, POWERPC_EXCP_SPEU);
9632 return;
9633 }
9634 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9635 }
9636 static inline void gen_efsnabs(DisasContext *ctx)
9637 {
9638 if (unlikely(!ctx->spe_enabled)) {
9639 gen_exception(ctx, POWERPC_EXCP_SPEU);
9640 return;
9641 }
9642 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9643 }
9644 static inline void gen_efsneg(DisasContext *ctx)
9645 {
9646 if (unlikely(!ctx->spe_enabled)) {
9647 gen_exception(ctx, POWERPC_EXCP_SPEU);
9648 return;
9649 }
9650 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9651 }
9652
9653 /* Conversion */
9654 GEN_SPEFPUOP_CONV_32_32(efscfui);
9655 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9656 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9657 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9658 GEN_SPEFPUOP_CONV_32_32(efsctui);
9659 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9660 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9661 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9662 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9663 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9664 GEN_SPEFPUOP_CONV_32_64(efscfd);
9665
9666 /* Comparison */
9667 GEN_SPEFPUOP_COMP_32(efscmpgt);
9668 GEN_SPEFPUOP_COMP_32(efscmplt);
9669 GEN_SPEFPUOP_COMP_32(efscmpeq);
9670 GEN_SPEFPUOP_COMP_32(efststgt);
9671 GEN_SPEFPUOP_COMP_32(efststlt);
9672 GEN_SPEFPUOP_COMP_32(efststeq);
9673
9674 /* Opcodes definitions */
9675 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9676 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9677 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9678 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9679 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9680 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9681 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9682 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9683 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9684 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9685 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9686 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9687 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9688 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9689
9690 /* Double precision floating-point operations */
9691 /* Arithmetic */
9692 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9693 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9694 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9695 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9696 static inline void gen_efdabs(DisasContext *ctx)
9697 {
9698 if (unlikely(!ctx->spe_enabled)) {
9699 gen_exception(ctx, POWERPC_EXCP_SPEU);
9700 return;
9701 }
9702 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9703 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9704 ~0x80000000);
9705 }
9706 static inline void gen_efdnabs(DisasContext *ctx)
9707 {
9708 if (unlikely(!ctx->spe_enabled)) {
9709 gen_exception(ctx, POWERPC_EXCP_SPEU);
9710 return;
9711 }
9712 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9713 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9714 0x80000000);
9715 }
9716 static inline void gen_efdneg(DisasContext *ctx)
9717 {
9718 if (unlikely(!ctx->spe_enabled)) {
9719 gen_exception(ctx, POWERPC_EXCP_SPEU);
9720 return;
9721 }
9722 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9723 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9724 0x80000000);
9725 }
9726
9727 /* Conversion */
9728 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9729 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9730 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9731 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9732 GEN_SPEFPUOP_CONV_32_64(efdctui);
9733 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9734 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9735 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9736 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9737 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9738 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9739 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9740 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9741 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9742 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9743
9744 /* Comparison */
9745 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9746 GEN_SPEFPUOP_COMP_64(efdcmplt);
9747 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9748 GEN_SPEFPUOP_COMP_64(efdtstgt);
9749 GEN_SPEFPUOP_COMP_64(efdtstlt);
9750 GEN_SPEFPUOP_COMP_64(efdtsteq);
9751
9752 /* Opcodes definitions */
9753 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9754 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9755 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9756 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9757 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9758 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9759 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9760 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9761 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9762 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9763 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9764 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9765 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9766 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9767 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9768 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9769
9770 static void gen_tbegin(DisasContext *ctx)
9771 {
9772 if (unlikely(!ctx->tm_enabled)) {
9773 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9774 return;
9775 }
9776 gen_helper_tbegin(cpu_env);
9777 }
9778
9779 #define GEN_TM_NOOP(name) \
9780 static inline void gen_##name(DisasContext *ctx) \
9781 { \
9782 if (unlikely(!ctx->tm_enabled)) { \
9783 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9784 return; \
9785 } \
9786 /* Because tbegin always fails in QEMU, these user \
9787 * space instructions all have a simple implementation: \
9788 * \
9789 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9790 * = 0b0 || 0b00 || 0b0 \
9791 */ \
9792 tcg_gen_movi_i32(cpu_crf[0], 0); \
9793 }
9794
9795 GEN_TM_NOOP(tend);
9796 GEN_TM_NOOP(tabort);
9797 GEN_TM_NOOP(tabortwc);
9798 GEN_TM_NOOP(tabortwci);
9799 GEN_TM_NOOP(tabortdc);
9800 GEN_TM_NOOP(tabortdci);
9801 GEN_TM_NOOP(tsr);
9802
9803 static void gen_tcheck(DisasContext *ctx)
9804 {
9805 if (unlikely(!ctx->tm_enabled)) {
9806 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9807 return;
9808 }
9809 /* Because tbegin always fails, the tcheck implementation
9810 * is simple:
9811 *
9812 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9813 * = 0b1 || 0b00 || 0b0
9814 */
9815 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9816 }
9817
9818 #if defined(CONFIG_USER_ONLY)
9819 #define GEN_TM_PRIV_NOOP(name) \
9820 static inline void gen_##name(DisasContext *ctx) \
9821 { \
9822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9823 }
9824
9825 #else
9826
9827 #define GEN_TM_PRIV_NOOP(name) \
9828 static inline void gen_##name(DisasContext *ctx) \
9829 { \
9830 if (unlikely(ctx->pr)) { \
9831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9832 return; \
9833 } \
9834 if (unlikely(!ctx->tm_enabled)) { \
9835 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9836 return; \
9837 } \
9838 /* Because tbegin always fails, the implementation is \
9839 * simple: \
9840 * \
9841 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9842 * = 0b0 || 0b00 | 0b0 \
9843 */ \
9844 tcg_gen_movi_i32(cpu_crf[0], 0); \
9845 }
9846
9847 #endif
9848
9849 GEN_TM_PRIV_NOOP(treclaim);
9850 GEN_TM_PRIV_NOOP(trechkpt);
9851
9852 static opcode_t opcodes[] = {
9853 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9854 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9855 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9856 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9857 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9858 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9859 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9860 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9861 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9862 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9863 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9864 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9865 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9866 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9867 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9868 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9869 #if defined(TARGET_PPC64)
9870 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9871 #endif
9872 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9873 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9874 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9875 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9877 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9878 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9879 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9880 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9881 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9882 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9883 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9884 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9885 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9886 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9887 #if defined(TARGET_PPC64)
9888 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9889 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9890 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9891 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9892 #endif
9893 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9894 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9895 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9896 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9897 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9898 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9899 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9900 #if defined(TARGET_PPC64)
9901 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9902 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9903 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9904 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9905 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9906 #endif
9907 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9908 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9909 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9910 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9911 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9912 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9913 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9914 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9915 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9916 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9917 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9918 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9919 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9920 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9921 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9922 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9923 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9924 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9925 #if defined(TARGET_PPC64)
9926 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9927 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9928 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9929 #endif
9930 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9931 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9932 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9933 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9934 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9935 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9936 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9937 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9938 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9939 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9940 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9941 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9942 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9943 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9944 #if defined(TARGET_PPC64)
9945 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9946 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9947 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9948 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9949 #endif
9950 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9951 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9952 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9953 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9954 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9955 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9956 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9957 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9958 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9959 #if defined(TARGET_PPC64)
9960 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9961 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9962 #endif
9963 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9964 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9965 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9966 #if defined(TARGET_PPC64)
9967 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9968 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9969 #endif
9970 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9971 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9972 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9973 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9974 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9975 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9976 #if defined(TARGET_PPC64)
9977 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9978 #endif
9979 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
9980 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9981 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9982 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9983 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9984 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9985 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9986 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9987 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9988 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9989 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9990 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9991 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9992 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9993 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9994 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9995 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9996 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9997 #if defined(TARGET_PPC64)
9998 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9999 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10000 PPC_SEGMENT_64B),
10001 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10002 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10003 PPC_SEGMENT_64B),
10004 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10005 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10006 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
10007 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
10008 #endif
10009 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10010 /* XXX Those instructions will need to be handled differently for
10011 * different ISA versions */
10012 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10013 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
10014 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10015 #if defined(TARGET_PPC64)
10016 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
10017 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10018 #endif
10019 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10020 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10021 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10022 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10023 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10024 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10025 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10026 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10027 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10028 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10029 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10030 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10031 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10032 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10033 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10034 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10035 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10036 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10037 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10038 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10039 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10040 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10041 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10042 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10043 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10044 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10045 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10046 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10047 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10048 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10049 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10050 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10051 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10052 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10053 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10054 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10055 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10056 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10057 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10058 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10059 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10060 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10061 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10062 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10063 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10064 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10065 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10066 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10067 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10068 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10069 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10070 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10071 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10072 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10073 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10074 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10075 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10076 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10077 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10078 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10079 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10080 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10081 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10082 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10083 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10084 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10085 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10086 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10087 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10088 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10089 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10090 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10091 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10092 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10093 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10094 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10095 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10096 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10097 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10098 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10099 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10100 PPC_NONE, PPC2_BOOKE206),
10101 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10102 PPC_NONE, PPC2_BOOKE206),
10103 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10104 PPC_NONE, PPC2_BOOKE206),
10105 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10106 PPC_NONE, PPC2_BOOKE206),
10107 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10108 PPC_NONE, PPC2_BOOKE206),
10109 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10110 PPC_NONE, PPC2_PRCNTL),
10111 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10112 PPC_NONE, PPC2_PRCNTL),
10113 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10114 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10115 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10116 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10117 PPC_BOOKE, PPC2_BOOKE206),
10118 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10119 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10120 PPC_BOOKE, PPC2_BOOKE206),
10121 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10122 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10123 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10124 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10125 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10126 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10127 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10128 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10129 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10130
10131 #undef GEN_INT_ARITH_ADD
10132 #undef GEN_INT_ARITH_ADD_CONST
10133 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10134 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10135 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10136 add_ca, compute_ca, compute_ov) \
10137 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10138 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10139 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10140 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10141 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10142 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10143 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10144 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10145 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10146 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10147 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10148
10149 #undef GEN_INT_ARITH_DIVW
10150 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10151 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10152 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10153 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10154 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10155 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10156 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10157 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10158 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10159 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10160
10161 #if defined(TARGET_PPC64)
10162 #undef GEN_INT_ARITH_DIVD
10163 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10164 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10165 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10166 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10167 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10168 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10169
10170 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10171 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10172 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10173 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10174
10175 #undef GEN_INT_ARITH_MUL_HELPER
10176 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10177 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10178 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10179 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10180 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10181 #endif
10182
10183 #undef GEN_INT_ARITH_SUBF
10184 #undef GEN_INT_ARITH_SUBF_CONST
10185 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10186 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10187 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10188 add_ca, compute_ca, compute_ov) \
10189 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10190 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10191 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10192 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10193 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10194 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10195 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10196 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10197 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10198 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10199 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10200
10201 #undef GEN_LOGICAL1
10202 #undef GEN_LOGICAL2
10203 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10204 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10205 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10206 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10207 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10208 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10209 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10210 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10211 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10212 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10213 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10214 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10215 #if defined(TARGET_PPC64)
10216 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10217 #endif
10218
10219 #if defined(TARGET_PPC64)
10220 #undef GEN_PPC64_R2
10221 #undef GEN_PPC64_R4
10222 #define GEN_PPC64_R2(name, opc1, opc2) \
10223 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10224 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10225 PPC_64B)
10226 #define GEN_PPC64_R4(name, opc1, opc2) \
10227 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10228 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10229 PPC_64B), \
10230 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10231 PPC_64B), \
10232 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10233 PPC_64B)
10234 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10235 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10236 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10237 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10238 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10239 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10240 #endif
10241
10242 #undef _GEN_FLOAT_ACB
10243 #undef GEN_FLOAT_ACB
10244 #undef _GEN_FLOAT_AB
10245 #undef GEN_FLOAT_AB
10246 #undef _GEN_FLOAT_AC
10247 #undef GEN_FLOAT_AC
10248 #undef GEN_FLOAT_B
10249 #undef GEN_FLOAT_BS
10250 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10251 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10252 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10253 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10254 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10255 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10256 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10257 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10258 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10259 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10260 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10261 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10262 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10263 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10264 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10265 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10266 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10267 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10268 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10269
10270 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10271 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10272 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10273 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10274 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10275 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10276 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10277 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10278 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10279 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10280 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10281 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10282 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10283 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10284 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10285 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10286 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10287 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10288 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10289 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10290 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10291 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10292 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10293 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10294 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10295 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10296 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10297 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10298 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10299 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10300 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10301
10302 #undef GEN_LD
10303 #undef GEN_LDU
10304 #undef GEN_LDUX
10305 #undef GEN_LDX_E
10306 #undef GEN_LDS
10307 #define GEN_LD(name, ldop, opc, type) \
10308 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10309 #define GEN_LDU(name, ldop, opc, type) \
10310 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10311 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10312 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10313 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10314 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10315 #define GEN_LDS(name, ldop, op, type) \
10316 GEN_LD(name, ldop, op | 0x20, type) \
10317 GEN_LDU(name, ldop, op | 0x21, type) \
10318 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10319 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10320
10321 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10322 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10323 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10324 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10325 #if defined(TARGET_PPC64)
10326 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10327 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10328 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10329 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10330 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10331 #endif
10332 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10333 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10334
10335 #undef GEN_ST
10336 #undef GEN_STU
10337 #undef GEN_STUX
10338 #undef GEN_STX_E
10339 #undef GEN_STS
10340 #define GEN_ST(name, stop, opc, type) \
10341 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10342 #define GEN_STU(name, stop, opc, type) \
10343 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10344 #define GEN_STUX(name, stop, opc2, opc3, type) \
10345 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10346 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10347 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10348 #define GEN_STS(name, stop, op, type) \
10349 GEN_ST(name, stop, op | 0x20, type) \
10350 GEN_STU(name, stop, op | 0x21, type) \
10351 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10352 GEN_STX(name, stop, 0x17, op | 0x00, type)
10353
10354 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10355 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10356 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10357 #if defined(TARGET_PPC64)
10358 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10359 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10360 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10361 #endif
10362 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10363 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10364
10365 #undef GEN_LDF
10366 #undef GEN_LDUF
10367 #undef GEN_LDUXF
10368 #undef GEN_LDXF
10369 #undef GEN_LDFS
10370 #define GEN_LDF(name, ldop, opc, type) \
10371 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10372 #define GEN_LDUF(name, ldop, opc, type) \
10373 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10374 #define GEN_LDUXF(name, ldop, opc, type) \
10375 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10376 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10377 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10378 #define GEN_LDFS(name, ldop, op, type) \
10379 GEN_LDF(name, ldop, op | 0x20, type) \
10380 GEN_LDUF(name, ldop, op | 0x21, type) \
10381 GEN_LDUXF(name, ldop, op | 0x01, type) \
10382 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10383
10384 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10385 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10386 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10387 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10388 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10389 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10390
10391 #undef GEN_STF
10392 #undef GEN_STUF
10393 #undef GEN_STUXF
10394 #undef GEN_STXF
10395 #undef GEN_STFS
10396 #define GEN_STF(name, stop, opc, type) \
10397 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10398 #define GEN_STUF(name, stop, opc, type) \
10399 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10400 #define GEN_STUXF(name, stop, opc, type) \
10401 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10402 #define GEN_STXF(name, stop, opc2, opc3, type) \
10403 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10404 #define GEN_STFS(name, stop, op, type) \
10405 GEN_STF(name, stop, op | 0x20, type) \
10406 GEN_STUF(name, stop, op | 0x21, type) \
10407 GEN_STUXF(name, stop, op | 0x01, type) \
10408 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10409
10410 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10411 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10412 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10413 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10414 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10415
10416 #undef GEN_CRLOGIC
10417 #define GEN_CRLOGIC(name, tcg_op, opc) \
10418 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10419 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10420 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10421 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10422 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10423 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10424 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10425 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10426 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10427
10428 #undef GEN_MAC_HANDLER
10429 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10430 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10431 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10432 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10433 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10434 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10435 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10436 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10437 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10438 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10439 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10440 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10441 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10442 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10443 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10444 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10445 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10446 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10447 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10448 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10449 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10450 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10451 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10452 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10453 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10454 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10455 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10456 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10457 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10458 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10459 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10460 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10461 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10462 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10463 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10464 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10465 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10466 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10467 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10468 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10469 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10470 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10471 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10472 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10473
10474 #undef GEN_VR_LDX
10475 #undef GEN_VR_STX
10476 #undef GEN_VR_LVE
10477 #undef GEN_VR_STVE
10478 #define GEN_VR_LDX(name, opc2, opc3) \
10479 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10480 #define GEN_VR_STX(name, opc2, opc3) \
10481 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10482 #define GEN_VR_LVE(name, opc2, opc3) \
10483 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10484 #define GEN_VR_STVE(name, opc2, opc3) \
10485 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10486 GEN_VR_LDX(lvx, 0x07, 0x03),
10487 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10488 GEN_VR_LVE(bx, 0x07, 0x00),
10489 GEN_VR_LVE(hx, 0x07, 0x01),
10490 GEN_VR_LVE(wx, 0x07, 0x02),
10491 GEN_VR_STX(svx, 0x07, 0x07),
10492 GEN_VR_STX(svxl, 0x07, 0x0F),
10493 GEN_VR_STVE(bx, 0x07, 0x04),
10494 GEN_VR_STVE(hx, 0x07, 0x05),
10495 GEN_VR_STVE(wx, 0x07, 0x06),
10496
10497 #undef GEN_VX_LOGICAL
10498 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10499 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10500
10501 #undef GEN_VX_LOGICAL_207
10502 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10503 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10504
10505 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10506 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10507 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10508 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10509 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10510 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10511 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10512 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10513
10514 #undef GEN_VXFORM
10515 #define GEN_VXFORM(name, opc2, opc3) \
10516 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10517
10518 #undef GEN_VXFORM_207
10519 #define GEN_VXFORM_207(name, opc2, opc3) \
10520 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10521
10522 #undef GEN_VXFORM_DUAL
10523 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10524 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10525
10526 #undef GEN_VXRFORM_DUAL
10527 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10528 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10529 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10530
10531 GEN_VXFORM(vaddubm, 0, 0),
10532 GEN_VXFORM(vadduhm, 0, 1),
10533 GEN_VXFORM(vadduwm, 0, 2),
10534 GEN_VXFORM_207(vaddudm, 0, 3),
10535 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10536 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10537 GEN_VXFORM(vsubuwm, 0, 18),
10538 GEN_VXFORM_207(vsubudm, 0, 19),
10539 GEN_VXFORM(vmaxub, 1, 0),
10540 GEN_VXFORM(vmaxuh, 1, 1),
10541 GEN_VXFORM(vmaxuw, 1, 2),
10542 GEN_VXFORM_207(vmaxud, 1, 3),
10543 GEN_VXFORM(vmaxsb, 1, 4),
10544 GEN_VXFORM(vmaxsh, 1, 5),
10545 GEN_VXFORM(vmaxsw, 1, 6),
10546 GEN_VXFORM_207(vmaxsd, 1, 7),
10547 GEN_VXFORM(vminub, 1, 8),
10548 GEN_VXFORM(vminuh, 1, 9),
10549 GEN_VXFORM(vminuw, 1, 10),
10550 GEN_VXFORM_207(vminud, 1, 11),
10551 GEN_VXFORM(vminsb, 1, 12),
10552 GEN_VXFORM(vminsh, 1, 13),
10553 GEN_VXFORM(vminsw, 1, 14),
10554 GEN_VXFORM_207(vminsd, 1, 15),
10555 GEN_VXFORM(vavgub, 1, 16),
10556 GEN_VXFORM(vavguh, 1, 17),
10557 GEN_VXFORM(vavguw, 1, 18),
10558 GEN_VXFORM(vavgsb, 1, 20),
10559 GEN_VXFORM(vavgsh, 1, 21),
10560 GEN_VXFORM(vavgsw, 1, 22),
10561 GEN_VXFORM(vmrghb, 6, 0),
10562 GEN_VXFORM(vmrghh, 6, 1),
10563 GEN_VXFORM(vmrghw, 6, 2),
10564 GEN_VXFORM(vmrglb, 6, 4),
10565 GEN_VXFORM(vmrglh, 6, 5),
10566 GEN_VXFORM(vmrglw, 6, 6),
10567 GEN_VXFORM_207(vmrgew, 6, 30),
10568 GEN_VXFORM_207(vmrgow, 6, 26),
10569 GEN_VXFORM(vmuloub, 4, 0),
10570 GEN_VXFORM(vmulouh, 4, 1),
10571 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10572 GEN_VXFORM(vmulosb, 4, 4),
10573 GEN_VXFORM(vmulosh, 4, 5),
10574 GEN_VXFORM_207(vmulosw, 4, 6),
10575 GEN_VXFORM(vmuleub, 4, 8),
10576 GEN_VXFORM(vmuleuh, 4, 9),
10577 GEN_VXFORM_207(vmuleuw, 4, 10),
10578 GEN_VXFORM(vmulesb, 4, 12),
10579 GEN_VXFORM(vmulesh, 4, 13),
10580 GEN_VXFORM_207(vmulesw, 4, 14),
10581 GEN_VXFORM(vslb, 2, 4),
10582 GEN_VXFORM(vslh, 2, 5),
10583 GEN_VXFORM(vslw, 2, 6),
10584 GEN_VXFORM_207(vsld, 2, 23),
10585 GEN_VXFORM(vsrb, 2, 8),
10586 GEN_VXFORM(vsrh, 2, 9),
10587 GEN_VXFORM(vsrw, 2, 10),
10588 GEN_VXFORM_207(vsrd, 2, 27),
10589 GEN_VXFORM(vsrab, 2, 12),
10590 GEN_VXFORM(vsrah, 2, 13),
10591 GEN_VXFORM(vsraw, 2, 14),
10592 GEN_VXFORM_207(vsrad, 2, 15),
10593 GEN_VXFORM(vslo, 6, 16),
10594 GEN_VXFORM(vsro, 6, 17),
10595 GEN_VXFORM(vaddcuw, 0, 6),
10596 GEN_VXFORM(vsubcuw, 0, 22),
10597 GEN_VXFORM(vaddubs, 0, 8),
10598 GEN_VXFORM(vadduhs, 0, 9),
10599 GEN_VXFORM(vadduws, 0, 10),
10600 GEN_VXFORM(vaddsbs, 0, 12),
10601 GEN_VXFORM(vaddshs, 0, 13),
10602 GEN_VXFORM(vaddsws, 0, 14),
10603 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10604 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10605 GEN_VXFORM(vsubuws, 0, 26),
10606 GEN_VXFORM(vsubsbs, 0, 28),
10607 GEN_VXFORM(vsubshs, 0, 29),
10608 GEN_VXFORM(vsubsws, 0, 30),
10609 GEN_VXFORM_207(vadduqm, 0, 4),
10610 GEN_VXFORM_207(vaddcuq, 0, 5),
10611 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10612 GEN_VXFORM_207(vsubuqm, 0, 20),
10613 GEN_VXFORM_207(vsubcuq, 0, 21),
10614 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10615 GEN_VXFORM(vrlb, 2, 0),
10616 GEN_VXFORM(vrlh, 2, 1),
10617 GEN_VXFORM(vrlw, 2, 2),
10618 GEN_VXFORM_207(vrld, 2, 3),
10619 GEN_VXFORM(vsl, 2, 7),
10620 GEN_VXFORM(vsr, 2, 11),
10621 GEN_VXFORM(vpkuhum, 7, 0),
10622 GEN_VXFORM(vpkuwum, 7, 1),
10623 GEN_VXFORM_207(vpkudum, 7, 17),
10624 GEN_VXFORM(vpkuhus, 7, 2),
10625 GEN_VXFORM(vpkuwus, 7, 3),
10626 GEN_VXFORM_207(vpkudus, 7, 19),
10627 GEN_VXFORM(vpkshus, 7, 4),
10628 GEN_VXFORM(vpkswus, 7, 5),
10629 GEN_VXFORM_207(vpksdus, 7, 21),
10630 GEN_VXFORM(vpkshss, 7, 6),
10631 GEN_VXFORM(vpkswss, 7, 7),
10632 GEN_VXFORM_207(vpksdss, 7, 23),
10633 GEN_VXFORM(vpkpx, 7, 12),
10634 GEN_VXFORM(vsum4ubs, 4, 24),
10635 GEN_VXFORM(vsum4sbs, 4, 28),
10636 GEN_VXFORM(vsum4shs, 4, 25),
10637 GEN_VXFORM(vsum2sws, 4, 26),
10638 GEN_VXFORM(vsumsws, 4, 30),
10639 GEN_VXFORM(vaddfp, 5, 0),
10640 GEN_VXFORM(vsubfp, 5, 1),
10641 GEN_VXFORM(vmaxfp, 5, 16),
10642 GEN_VXFORM(vminfp, 5, 17),
10643
10644 #undef GEN_VXRFORM1
10645 #undef GEN_VXRFORM
10646 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10647 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10648 #define GEN_VXRFORM(name, opc2, opc3) \
10649 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10650 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10651 GEN_VXRFORM(vcmpequb, 3, 0)
10652 GEN_VXRFORM(vcmpequh, 3, 1)
10653 GEN_VXRFORM(vcmpequw, 3, 2)
10654 GEN_VXRFORM(vcmpgtsb, 3, 12)
10655 GEN_VXRFORM(vcmpgtsh, 3, 13)
10656 GEN_VXRFORM(vcmpgtsw, 3, 14)
10657 GEN_VXRFORM(vcmpgtub, 3, 8)
10658 GEN_VXRFORM(vcmpgtuh, 3, 9)
10659 GEN_VXRFORM(vcmpgtuw, 3, 10)
10660 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10661 GEN_VXRFORM(vcmpgefp, 3, 7)
10662 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10663 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10664
10665 #undef GEN_VXFORM_SIMM
10666 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10667 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10668 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10669 GEN_VXFORM_SIMM(vspltish, 6, 13),
10670 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10671
10672 #undef GEN_VXFORM_NOA
10673 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10674 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10675 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10676 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10677 GEN_VXFORM_207(vupkhsw, 7, 25),
10678 GEN_VXFORM_NOA(vupklsb, 7, 10),
10679 GEN_VXFORM_NOA(vupklsh, 7, 11),
10680 GEN_VXFORM_207(vupklsw, 7, 27),
10681 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10682 GEN_VXFORM_NOA(vupklpx, 7, 15),
10683 GEN_VXFORM_NOA(vrefp, 5, 4),
10684 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10685 GEN_VXFORM_NOA(vexptefp, 5, 6),
10686 GEN_VXFORM_NOA(vlogefp, 5, 7),
10687 GEN_VXFORM_NOA(vrfim, 5, 11),
10688 GEN_VXFORM_NOA(vrfin, 5, 8),
10689 GEN_VXFORM_NOA(vrfip, 5, 10),
10690 GEN_VXFORM_NOA(vrfiz, 5, 9),
10691
10692 #undef GEN_VXFORM_UIMM
10693 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10694 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10695 GEN_VXFORM_UIMM(vspltb, 6, 8),
10696 GEN_VXFORM_UIMM(vsplth, 6, 9),
10697 GEN_VXFORM_UIMM(vspltw, 6, 10),
10698 GEN_VXFORM_UIMM(vcfux, 5, 12),
10699 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10700 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10701 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10702
10703 #undef GEN_VAFORM_PAIRED
10704 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10705 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10706 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10707 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10708 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10709 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10710 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10711 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10712
10713 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10714 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10715 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10716 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10717
10718 GEN_VXFORM_207(vbpermq, 6, 21),
10719 GEN_VXFORM_207(vgbbd, 6, 20),
10720 GEN_VXFORM_207(vpmsumb, 4, 16),
10721 GEN_VXFORM_207(vpmsumh, 4, 17),
10722 GEN_VXFORM_207(vpmsumw, 4, 18),
10723 GEN_VXFORM_207(vpmsumd, 4, 19),
10724
10725 GEN_VXFORM_207(vsbox, 4, 23),
10726
10727 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10728 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10729
10730 GEN_VXFORM_207(vshasigmaw, 1, 26),
10731 GEN_VXFORM_207(vshasigmad, 1, 27),
10732
10733 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10734
10735 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10736 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10737 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10738 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10739 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10740 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10741 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10742
10743 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10744 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10745 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10746 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10747 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10748
10749 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10750 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10751 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10752 #if defined(TARGET_PPC64)
10753 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10754 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10755 #endif
10756
10757 #undef GEN_XX2FORM
10758 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10759 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10760 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10761
10762 #undef GEN_XX3FORM
10763 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10764 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10765 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10766 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10767 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10768
10769 #undef GEN_XX2IFORM
10770 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10771 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10772 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10773 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10774 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10775
10776 #undef GEN_XX3_RC_FORM
10777 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10778 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10779 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10780 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10781 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10782 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10783 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10784 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10785 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10786
10787 #undef GEN_XX3FORM_DM
10788 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10789 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10790 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10791 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10792 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10793 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10794 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10795 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10796 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10797 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10798 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10799 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10800 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10801 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10802 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10803 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10804 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10805
10806 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10807 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10808 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10809 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10810
10811 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10812 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10813 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10814 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10815 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10816 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10817 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10818 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10819
10820 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10821 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10822 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10823 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10824 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10825 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10826 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10827 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10828 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10829 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10830 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10831 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10832 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10833 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10834 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10835 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10836 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10837 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10838 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10839 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10840 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10841 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10842 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10843 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10844 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10845 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10846 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10847 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10848 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10849 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10850 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10851 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10852 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10853 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10854 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10855 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10856
10857 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10858 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10859 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10860 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10861 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10862 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10863 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10864 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10865 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10866 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10867 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10868 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10869 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10870 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10871 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10872 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10873 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10874 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10875
10876 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10877 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10878 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10879 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10880 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10881 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10882 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10883 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10884 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10885 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10886 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10887 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10888 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10889 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10890 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10891 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10892 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10893 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10894 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10895 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10896 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10897 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10898 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10899 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10900 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10901 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10902 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10903 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10904 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10905 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10906 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10907 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10908 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10909 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10910 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10911 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10912
10913 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10914 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10915 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10916 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10917 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10918 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10919 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10920 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10921 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10922 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10923 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10924 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10925 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10926 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10927 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10928 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10929 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10930 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10931 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10932 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10933 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10934 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10935 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10936 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10937 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10938 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10939 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10940 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10941 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10942 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10943 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10944 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10945 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10946 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10947 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10948 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10949
10950 #undef VSX_LOGICAL
10951 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10952 GEN_XX3FORM(name, opc2, opc3, fl2)
10953
10954 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10955 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10956 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10957 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10958 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10959 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10960 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10961 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10962 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10963 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10964 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10965 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10966
10967 #define GEN_XXSEL_ROW(opc3) \
10968 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10969 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10970 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10971 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10972 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10973 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10974 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10975 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10976
10977 GEN_XXSEL_ROW(0x00)
10978 GEN_XXSEL_ROW(0x01)
10979 GEN_XXSEL_ROW(0x02)
10980 GEN_XXSEL_ROW(0x03)
10981 GEN_XXSEL_ROW(0x04)
10982 GEN_XXSEL_ROW(0x05)
10983 GEN_XXSEL_ROW(0x06)
10984 GEN_XXSEL_ROW(0x07)
10985 GEN_XXSEL_ROW(0x08)
10986 GEN_XXSEL_ROW(0x09)
10987 GEN_XXSEL_ROW(0x0A)
10988 GEN_XXSEL_ROW(0x0B)
10989 GEN_XXSEL_ROW(0x0C)
10990 GEN_XXSEL_ROW(0x0D)
10991 GEN_XXSEL_ROW(0x0E)
10992 GEN_XXSEL_ROW(0x0F)
10993 GEN_XXSEL_ROW(0x10)
10994 GEN_XXSEL_ROW(0x11)
10995 GEN_XXSEL_ROW(0x12)
10996 GEN_XXSEL_ROW(0x13)
10997 GEN_XXSEL_ROW(0x14)
10998 GEN_XXSEL_ROW(0x15)
10999 GEN_XXSEL_ROW(0x16)
11000 GEN_XXSEL_ROW(0x17)
11001 GEN_XXSEL_ROW(0x18)
11002 GEN_XXSEL_ROW(0x19)
11003 GEN_XXSEL_ROW(0x1A)
11004 GEN_XXSEL_ROW(0x1B)
11005 GEN_XXSEL_ROW(0x1C)
11006 GEN_XXSEL_ROW(0x1D)
11007 GEN_XXSEL_ROW(0x1E)
11008 GEN_XXSEL_ROW(0x1F)
11009
11010 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11011
11012 #undef GEN_DFP_T_A_B_Rc
11013 #undef GEN_DFP_BF_A_B
11014 #undef GEN_DFP_BF_A_DCM
11015 #undef GEN_DFP_T_B_U32_U32_Rc
11016 #undef GEN_DFP_T_A_B_I32_Rc
11017 #undef GEN_DFP_T_B_Rc
11018 #undef GEN_DFP_T_FPR_I32_Rc
11019
11020 #define _GEN_DFP_LONG(name, op1, op2, mask) \
11021 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11022
11023 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11024 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11025 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11026
11027 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11028 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11029 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11030 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11031 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11032
11033 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11034 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11035
11036 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11037 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11038 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11039
11040 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11041 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11042 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11043 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11044 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11045
11046 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11047 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11048
11049 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11050 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11051
11052 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11053 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11054
11055 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11056 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11057
11058 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11059 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11060
11061 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11062 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11063
11064 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11065 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11066
11067 #define GEN_DFP_BF_A_B(name, op1, op2) \
11068 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11069
11070 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11071 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11072
11073 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11074 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11075
11076 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11077 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11078
11079 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11080 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11081
11082 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11083 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11084
11085 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11086 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11087
11088 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11089 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11090
11091 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11092 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11093
11094 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11095 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11096
11097 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11098 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11099
11100 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11101 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11102
11103 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11104 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11105
11106 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11107 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11108
11109 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11110 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11111
11112 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11113 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11114
11115 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11116 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11117
11118 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11119 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11120
11121 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11122 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11123 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11124 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11125 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11126 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11127 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11128 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11129 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11130 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11131 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11132 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11133 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11134 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11135 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11136 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11137 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11138 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11139 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11140 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11141 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11142 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11143 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11144 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11145 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11146 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11147 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11148 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11149 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11150 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11151 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11152 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11153 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11154 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11155 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11156 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11157 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11158 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11159 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11160 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11161 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11162 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11163 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11164 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11165 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11166 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11167 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11168 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11169 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11170 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11171
11172 #undef GEN_SPE
11173 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11174 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11175 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11176 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11177 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11178 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11179 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11180 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11181 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11182 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11183 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11184 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11185 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11186 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11187 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11188 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11189 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11190 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11191 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11192 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11193 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11194 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11195 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11196 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11197 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11198 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11199 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11200 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11201 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11202 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11203 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11204
11205 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11206 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11207 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11208 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11209 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11210 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11211 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11212 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11213 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11214 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11215 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11216 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11217 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11218 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11219
11220 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11221 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11222 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11223 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11224 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11225 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11226 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11227 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11228 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11229 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11230 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11231 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11232 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11233 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11234
11235 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11236 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11237 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11238 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11239 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11240 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11241 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11242 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11243 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11244 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11245 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11246 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11247 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11248 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11249 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11250 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11251
11252 #undef GEN_SPEOP_LDST
11253 #define GEN_SPEOP_LDST(name, opc2, sh) \
11254 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11255 GEN_SPEOP_LDST(evldd, 0x00, 3),
11256 GEN_SPEOP_LDST(evldw, 0x01, 3),
11257 GEN_SPEOP_LDST(evldh, 0x02, 3),
11258 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11259 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11260 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11261 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11262 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11263 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11264 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11265 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11266
11267 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11268 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11269 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11270 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11271 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11272 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11273 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11274
11275 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11276 PPC_NONE, PPC2_TM),
11277 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11278 PPC_NONE, PPC2_TM),
11279 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11280 PPC_NONE, PPC2_TM),
11281 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11282 PPC_NONE, PPC2_TM),
11283 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11284 PPC_NONE, PPC2_TM),
11285 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11286 PPC_NONE, PPC2_TM),
11287 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11288 PPC_NONE, PPC2_TM),
11289 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11290 PPC_NONE, PPC2_TM),
11291 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11292 PPC_NONE, PPC2_TM),
11293 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11294 PPC_NONE, PPC2_TM),
11295 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11296 PPC_NONE, PPC2_TM),
11297 };
11298
11299 #include "helper_regs.h"
11300 #include "translate_init.c"
11301
11302 /*****************************************************************************/
11303 /* Misc PowerPC helpers */
11304 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11305 int flags)
11306 {
11307 #define RGPL 4
11308 #define RFPL 4
11309
11310 PowerPCCPU *cpu = POWERPC_CPU(cs);
11311 CPUPPCState *env = &cpu->env;
11312 int i;
11313
11314 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11315 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11316 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11317 cs->cpu_index);
11318 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11319 TARGET_FMT_lx " iidx %d didx %d\n",
11320 env->msr, env->spr[SPR_HID0],
11321 env->hflags, env->immu_idx, env->dmmu_idx);
11322 #if !defined(NO_TIMER_DUMP)
11323 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11324 #if !defined(CONFIG_USER_ONLY)
11325 " DECR %08" PRIu32
11326 #endif
11327 "\n",
11328 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11329 #if !defined(CONFIG_USER_ONLY)
11330 , cpu_ppc_load_decr(env)
11331 #endif
11332 );
11333 #endif
11334 for (i = 0; i < 32; i++) {
11335 if ((i & (RGPL - 1)) == 0)
11336 cpu_fprintf(f, "GPR%02d", i);
11337 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11338 if ((i & (RGPL - 1)) == (RGPL - 1))
11339 cpu_fprintf(f, "\n");
11340 }
11341 cpu_fprintf(f, "CR ");
11342 for (i = 0; i < 8; i++)
11343 cpu_fprintf(f, "%01x", env->crf[i]);
11344 cpu_fprintf(f, " [");
11345 for (i = 0; i < 8; i++) {
11346 char a = '-';
11347 if (env->crf[i] & 0x08)
11348 a = 'L';
11349 else if (env->crf[i] & 0x04)
11350 a = 'G';
11351 else if (env->crf[i] & 0x02)
11352 a = 'E';
11353 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11354 }
11355 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11356 env->reserve_addr);
11357 for (i = 0; i < 32; i++) {
11358 if ((i & (RFPL - 1)) == 0)
11359 cpu_fprintf(f, "FPR%02d", i);
11360 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11361 if ((i & (RFPL - 1)) == (RFPL - 1))
11362 cpu_fprintf(f, "\n");
11363 }
11364 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11365 #if !defined(CONFIG_USER_ONLY)
11366 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11367 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11368 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11369 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11370
11371 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11372 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11373 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11374 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11375
11376 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11377 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11378 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11379 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11380
11381 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11382 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11383 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11384 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11385 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11386
11387 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11388 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11389 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11390 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11391
11392 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11393 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11394 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11395 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11396
11397 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11398 " EPR " TARGET_FMT_lx "\n",
11399 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11400 env->spr[SPR_BOOKE_EPR]);
11401
11402 /* FSL-specific */
11403 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11404 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11405 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11406 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11407
11408 /*
11409 * IVORs are left out as they are large and do not change often --
11410 * they can be read with "p $ivor0", "p $ivor1", etc.
11411 */
11412 }
11413
11414 #if defined(TARGET_PPC64)
11415 if (env->flags & POWERPC_FLAG_CFAR) {
11416 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11417 }
11418 #endif
11419
11420 switch (env->mmu_model) {
11421 case POWERPC_MMU_32B:
11422 case POWERPC_MMU_601:
11423 case POWERPC_MMU_SOFT_6xx:
11424 case POWERPC_MMU_SOFT_74xx:
11425 #if defined(TARGET_PPC64)
11426 case POWERPC_MMU_64B:
11427 case POWERPC_MMU_2_03:
11428 case POWERPC_MMU_2_06:
11429 case POWERPC_MMU_2_06a:
11430 case POWERPC_MMU_2_07:
11431 case POWERPC_MMU_2_07a:
11432 #endif
11433 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11434 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11435 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11436 break;
11437 case POWERPC_MMU_BOOKE206:
11438 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11439 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11440 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11441 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11442
11443 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11444 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11445 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11446 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11447
11448 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11449 " TLB1CFG " TARGET_FMT_lx "\n",
11450 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11451 env->spr[SPR_BOOKE_TLB1CFG]);
11452 break;
11453 default:
11454 break;
11455 }
11456 #endif
11457
11458 #undef RGPL
11459 #undef RFPL
11460 }
11461
11462 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11463 fprintf_function cpu_fprintf, int flags)
11464 {
11465 #if defined(DO_PPC_STATISTICS)
11466 PowerPCCPU *cpu = POWERPC_CPU(cs);
11467 opc_handler_t **t1, **t2, **t3, *handler;
11468 int op1, op2, op3;
11469
11470 t1 = cpu->env.opcodes;
11471 for (op1 = 0; op1 < 64; op1++) {
11472 handler = t1[op1];
11473 if (is_indirect_opcode(handler)) {
11474 t2 = ind_table(handler);
11475 for (op2 = 0; op2 < 32; op2++) {
11476 handler = t2[op2];
11477 if (is_indirect_opcode(handler)) {
11478 t3 = ind_table(handler);
11479 for (op3 = 0; op3 < 32; op3++) {
11480 handler = t3[op3];
11481 if (handler->count == 0)
11482 continue;
11483 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11484 "%016" PRIx64 " %" PRId64 "\n",
11485 op1, op2, op3, op1, (op3 << 5) | op2,
11486 handler->oname,
11487 handler->count, handler->count);
11488 }
11489 } else {
11490 if (handler->count == 0)
11491 continue;
11492 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11493 "%016" PRIx64 " %" PRId64 "\n",
11494 op1, op2, op1, op2, handler->oname,
11495 handler->count, handler->count);
11496 }
11497 }
11498 } else {
11499 if (handler->count == 0)
11500 continue;
11501 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11502 " %" PRId64 "\n",
11503 op1, op1, handler->oname,
11504 handler->count, handler->count);
11505 }
11506 }
11507 #endif
11508 }
11509
11510 /*****************************************************************************/
11511 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11512 {
11513 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11514 CPUState *cs = CPU(cpu);
11515 DisasContext ctx, *ctxp = &ctx;
11516 opc_handler_t **table, *handler;
11517 target_ulong pc_start;
11518 int num_insns;
11519 int max_insns;
11520
11521 pc_start = tb->pc;
11522 ctx.nip = pc_start;
11523 ctx.tb = tb;
11524 ctx.exception = POWERPC_EXCP_NONE;
11525 ctx.spr_cb = env->spr_cb;
11526 ctx.pr = msr_pr;
11527 ctx.mem_idx = env->dmmu_idx;
11528 #if !defined(CONFIG_USER_ONLY)
11529 ctx.hv = msr_hv || !env->has_hv_mode;
11530 #endif
11531 ctx.insns_flags = env->insns_flags;
11532 ctx.insns_flags2 = env->insns_flags2;
11533 ctx.access_type = -1;
11534 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11535 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11536 #if defined(TARGET_PPC64)
11537 ctx.sf_mode = msr_is_64bit(env, env->msr);
11538 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11539 #endif
11540 if (env->mmu_model == POWERPC_MMU_32B ||
11541 env->mmu_model == POWERPC_MMU_601 ||
11542 (env->mmu_model & POWERPC_MMU_64B))
11543 ctx.lazy_tlb_flush = true;
11544
11545 ctx.fpu_enabled = msr_fp;
11546 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11547 ctx.spe_enabled = msr_spe;
11548 else
11549 ctx.spe_enabled = 0;
11550 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11551 ctx.altivec_enabled = msr_vr;
11552 else
11553 ctx.altivec_enabled = 0;
11554 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11555 ctx.vsx_enabled = msr_vsx;
11556 } else {
11557 ctx.vsx_enabled = 0;
11558 }
11559 #if defined(TARGET_PPC64)
11560 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11561 ctx.tm_enabled = msr_tm;
11562 } else {
11563 ctx.tm_enabled = 0;
11564 }
11565 #endif
11566 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11567 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11568 else
11569 ctx.singlestep_enabled = 0;
11570 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11571 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11572 if (unlikely(cs->singlestep_enabled)) {
11573 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11574 }
11575 #if defined (DO_SINGLE_STEP) && 0
11576 /* Single step trace mode */
11577 msr_se = 1;
11578 #endif
11579 num_insns = 0;
11580 max_insns = tb->cflags & CF_COUNT_MASK;
11581 if (max_insns == 0) {
11582 max_insns = CF_COUNT_MASK;
11583 }
11584 if (max_insns > TCG_MAX_INSNS) {
11585 max_insns = TCG_MAX_INSNS;
11586 }
11587
11588 gen_tb_start(tb);
11589 tcg_clear_temp_count();
11590 /* Set env in case of segfault during code fetch */
11591 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11592 tcg_gen_insn_start(ctx.nip);
11593 num_insns++;
11594
11595 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11596 gen_debug_exception(ctxp);
11597 /* The address covered by the breakpoint must be included in
11598 [tb->pc, tb->pc + tb->size) in order to for it to be
11599 properly cleared -- thus we increment the PC here so that
11600 the logic setting tb->size below does the right thing. */
11601 ctx.nip += 4;
11602 break;
11603 }
11604
11605 LOG_DISAS("----------------\n");
11606 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11607 ctx.nip, ctx.mem_idx, (int)msr_ir);
11608 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11609 gen_io_start();
11610 if (unlikely(need_byteswap(&ctx))) {
11611 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11612 } else {
11613 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11614 }
11615 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11616 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11617 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11618 ctx.nip += 4;
11619 table = env->opcodes;
11620 handler = table[opc1(ctx.opcode)];
11621 if (is_indirect_opcode(handler)) {
11622 table = ind_table(handler);
11623 handler = table[opc2(ctx.opcode)];
11624 if (is_indirect_opcode(handler)) {
11625 table = ind_table(handler);
11626 handler = table[opc3(ctx.opcode)];
11627 }
11628 }
11629 /* Is opcode *REALLY* valid ? */
11630 if (unlikely(handler->handler == &gen_invalid)) {
11631 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11632 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11633 opc1(ctx.opcode), opc2(ctx.opcode),
11634 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11635 } else {
11636 uint32_t inval;
11637
11638 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11639 inval = handler->inval2;
11640 } else {
11641 inval = handler->inval1;
11642 }
11643
11644 if (unlikely((ctx.opcode & inval) != 0)) {
11645 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11646 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11647 ctx.opcode & inval, opc1(ctx.opcode),
11648 opc2(ctx.opcode), opc3(ctx.opcode),
11649 ctx.opcode, ctx.nip - 4);
11650 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11651 break;
11652 }
11653 }
11654 (*(handler->handler))(&ctx);
11655 #if defined(DO_PPC_STATISTICS)
11656 handler->count++;
11657 #endif
11658 /* Check trace mode exceptions */
11659 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11660 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11661 ctx.exception != POWERPC_SYSCALL &&
11662 ctx.exception != POWERPC_EXCP_TRAP &&
11663 ctx.exception != POWERPC_EXCP_BRANCH)) {
11664 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11665 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11666 (cs->singlestep_enabled) ||
11667 singlestep ||
11668 num_insns >= max_insns)) {
11669 /* if we reach a page boundary or are single stepping, stop
11670 * generation
11671 */
11672 break;
11673 }
11674 if (tcg_check_temp_count()) {
11675 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11676 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11677 ctx.opcode);
11678 exit(1);
11679 }
11680 }
11681 if (tb->cflags & CF_LAST_IO)
11682 gen_io_end();
11683 if (ctx.exception == POWERPC_EXCP_NONE) {
11684 gen_goto_tb(&ctx, 0, ctx.nip);
11685 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11686 if (unlikely(cs->singlestep_enabled)) {
11687 gen_debug_exception(ctxp);
11688 }
11689 /* Generate the return instruction */
11690 tcg_gen_exit_tb(0);
11691 }
11692 gen_tb_end(tb, num_insns);
11693
11694 tb->size = ctx.nip - pc_start;
11695 tb->icount = num_insns;
11696
11697 #if defined(DEBUG_DISAS)
11698 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11699 && qemu_log_in_addr_range(pc_start)) {
11700 int flags;
11701 flags = env->bfd_mach;
11702 flags |= ctx.le_mode << 16;
11703 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11704 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11705 qemu_log("\n");
11706 }
11707 #endif
11708 }
11709
11710 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11711 target_ulong *data)
11712 {
11713 env->nip = data[0];
11714 }
Ray Wang's QEMU Repository