2 * MIPS internal definitions and helpers
4 * This work is licensed under the terms of the GNU GPL, version 2 or later.
5 * See the COPYING file in the top-level directory.
8 #ifndef MIPS_INTERNAL_H
9 #define MIPS_INTERNAL_H
11 #include "exec/memattrs.h"
13 #include "tcg/tcg-internal.h"
18 * MMU types, the first four entries have the same layout as the
23 MMU_TYPE_R4000
= 1, /* Standard TLB */
24 MMU_TYPE_BAT
= 2, /* Block Address Translation */
25 MMU_TYPE_FMT
= 3, /* Fixed Mapping */
26 MMU_TYPE_DVF
= 4, /* Dual VTLB and FTLB */
40 int32_t CP0_Config4_rw_bitmask
;
42 int32_t CP0_Config5_rw_bitmask
;
44 int32_t CP0_Config6_rw_bitmask
;
46 int32_t CP0_Config7_rw_bitmask
;
47 target_ulong CP0_LLAddr_rw_bitmask
;
51 * @CCRes: rate at which the coprocessor 0 counter increments
53 * The Count register acts as a timer, incrementing at a constant rate,
54 * whether or not an instruction is executed, retired, or any forward
55 * progress is made through the pipeline. The rate at which the counter
56 * increments is implementation dependent, and is a function of the
57 * pipeline clock of the processor, not the issue width of the processor.
60 int32_t CP0_Status_rw_bitmask
;
61 int32_t CP0_TCStatus_rw_bitmask
;
64 int32_t CP1_fcr31_rw_bitmask
;
69 int32_t CP0_SRSConf0_rw_bitmask
;
71 int32_t CP0_SRSConf1_rw_bitmask
;
73 int32_t CP0_SRSConf2_rw_bitmask
;
75 int32_t CP0_SRSConf3_rw_bitmask
;
77 int32_t CP0_SRSConf4_rw_bitmask
;
79 int32_t CP0_PageGrain_rw_bitmask
;
80 int32_t CP0_PageGrain
;
81 target_ulong CP0_EBaseWG_rw_bitmask
;
83 enum mips_mmu_types mmu_type
;
87 extern const char regnames
[32][3];
88 extern const char fregnames
[32][4];
90 extern const struct mips_def_t mips_defs
[];
91 extern const int mips_defs_number
;
93 int mips_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
94 int mips_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
96 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
97 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
98 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
99 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
100 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
102 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
103 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
105 #if !defined(CONFIG_USER_ONLY)
117 int get_physical_address(CPUMIPSState
*env
, hwaddr
*physical
,
118 int *prot
, target_ulong real_address
,
119 MMUAccessType access_type
, int mmu_idx
);
120 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
122 typedef struct r4k_tlb_t r4k_tlb_t
;
139 unsigned int EHINV
:1;
143 struct CPUMIPSTLBContext
{
146 int (*map_address
)(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
147 target_ulong address
, MMUAccessType access_type
);
148 void (*helper_tlbwi
)(CPUMIPSState
*env
);
149 void (*helper_tlbwr
)(CPUMIPSState
*env
);
150 void (*helper_tlbp
)(CPUMIPSState
*env
);
151 void (*helper_tlbr
)(CPUMIPSState
*env
);
152 void (*helper_tlbinv
)(CPUMIPSState
*env
);
153 void (*helper_tlbinvf
)(CPUMIPSState
*env
);
156 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
161 void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
);
162 void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
);
163 void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
);
165 extern const VMStateDescription vmstate_mips_cpu
;
167 #endif /* !CONFIG_USER_ONLY */
169 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState
*env
)
171 return (env
->CP0_Status
& (1 << CP0St_IE
)) &&
172 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
173 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
174 !(env
->hflags
& MIPS_HFLAG_DM
) &&
176 * Note that the TCStatus IXMT field is initialized to zero,
177 * and only MT capable cores can set it to one. So we don't
178 * need to check for MT capabilities here.
180 !(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_IXMT
));
183 /* Check if there is pending and not masked out interrupt */
184 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState
*env
)
190 pending
= env
->CP0_Cause
& CP0Ca_IP_mask
;
191 status
= env
->CP0_Status
& CP0Ca_IP_mask
;
193 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
195 * A MIPS configured with a vectorizing external interrupt controller
196 * will feed a vector into the Cause pending lines. The core treats
197 * the status lines as a vector level, not as individual masks.
199 r
= pending
> status
;
202 * A MIPS configured with compatibility or VInt (Vectored Interrupts)
203 * treats the pending lines as individual interrupt lines, the status
204 * lines are individual masks.
206 r
= (pending
& status
) != 0;
211 void msa_reset(CPUMIPSState
*env
);
214 uint32_t cpu_mips_get_count(CPUMIPSState
*env
);
215 void cpu_mips_store_count(CPUMIPSState
*env
, uint32_t value
);
216 void cpu_mips_store_compare(CPUMIPSState
*env
, uint32_t value
);
217 void cpu_mips_start_count(CPUMIPSState
*env
);
218 void cpu_mips_stop_count(CPUMIPSState
*env
);
220 static inline void mips_env_set_pc(CPUMIPSState
*env
, target_ulong value
)
222 env
->active_tc
.PC
= value
& ~(target_ulong
)1;
224 env
->hflags
|= MIPS_HFLAG_M16
;
226 env
->hflags
&= ~(MIPS_HFLAG_M16
);
230 static inline void restore_pamask(CPUMIPSState
*env
)
232 if (env
->hflags
& MIPS_HFLAG_ELPA
) {
233 env
->PAMask
= (1ULL << env
->PABITS
) - 1;
235 env
->PAMask
= PAMASK_BASE
;
239 static inline int mips_vpe_active(CPUMIPSState
*env
)
243 /* Check that the VPE is enabled. */
244 if (!(env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_EVP
))) {
247 /* Check that the VPE is activated. */
248 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))) {
253 * Now verify that there are active thread contexts in the VPE.
255 * This assumes the CPU model will internally reschedule threads
256 * if the active one goes to sleep. If there are no threads available
257 * the active one will be in a sleeping state, and we can turn off
260 if (!(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_A
))) {
261 /* TC is not activated. */
264 if (env
->active_tc
.CP0_TCHalt
& 1) {
265 /* TC is in halt state. */
272 static inline int mips_vp_active(CPUMIPSState
*env
)
274 CPUState
*other_cs
= first_cpu
;
276 /* Check if the VP disabled other VPs (which means the VP is enabled) */
277 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
281 /* Check if the virtual processor is disabled due to a DVP */
282 CPU_FOREACH(other_cs
) {
283 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
284 if ((&other_cpu
->env
!= env
) &&
285 ((other_cpu
->env
.CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
292 static inline void compute_hflags(CPUMIPSState
*env
)
294 env
->hflags
&= ~(MIPS_HFLAG_COP1X
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
|
295 MIPS_HFLAG_F64
| MIPS_HFLAG_FPU
| MIPS_HFLAG_KSU
|
296 MIPS_HFLAG_AWRAP
| MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
297 MIPS_HFLAG_DSP_R3
| MIPS_HFLAG_SBRI
| MIPS_HFLAG_MSA
|
298 MIPS_HFLAG_FRE
| MIPS_HFLAG_ELPA
| MIPS_HFLAG_ERL
);
299 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
300 env
->hflags
|= MIPS_HFLAG_ERL
;
302 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
303 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
304 !(env
->hflags
& MIPS_HFLAG_DM
)) {
305 env
->hflags
|= (env
->CP0_Status
>> CP0St_KSU
) &
308 #if defined(TARGET_MIPS64)
309 if ((env
->insn_flags
& ISA_MIPS3
) &&
310 (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_UM
) ||
311 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
312 (env
->CP0_Status
& (1 << CP0St_UX
)))) {
313 env
->hflags
|= MIPS_HFLAG_64
;
316 if (!(env
->insn_flags
& ISA_MIPS3
)) {
317 env
->hflags
|= MIPS_HFLAG_AWRAP
;
318 } else if (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
319 !(env
->CP0_Status
& (1 << CP0St_UX
))) {
320 env
->hflags
|= MIPS_HFLAG_AWRAP
;
321 } else if (env
->insn_flags
& ISA_MIPS_R6
) {
322 /* Address wrapping for Supervisor and Kernel is specified in R6 */
323 if ((((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_SM
) &&
324 !(env
->CP0_Status
& (1 << CP0St_SX
))) ||
325 (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_KM
) &&
326 !(env
->CP0_Status
& (1 << CP0St_KX
)))) {
327 env
->hflags
|= MIPS_HFLAG_AWRAP
;
331 if (((env
->CP0_Status
& (1 << CP0St_CU0
)) &&
332 !(env
->insn_flags
& ISA_MIPS_R6
)) ||
333 !(env
->hflags
& MIPS_HFLAG_KSU
)) {
334 env
->hflags
|= MIPS_HFLAG_CP0
;
336 if (env
->CP0_Status
& (1 << CP0St_CU1
)) {
337 env
->hflags
|= MIPS_HFLAG_FPU
;
339 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
340 env
->hflags
|= MIPS_HFLAG_F64
;
342 if (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_KM
) &&
343 (env
->CP0_Config5
& (1 << CP0C5_SBRI
))) {
344 env
->hflags
|= MIPS_HFLAG_SBRI
;
346 if (env
->insn_flags
& ASE_DSP_R3
) {
348 * Our cpu supports DSP R3 ASE, so enable
349 * access to DSP R3 resources.
351 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
352 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
355 } else if (env
->insn_flags
& ASE_DSP_R2
) {
357 * Our cpu supports DSP R2 ASE, so enable
358 * access to DSP R2 resources.
360 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
361 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
;
364 } else if (env
->insn_flags
& ASE_DSP
) {
366 * Our cpu supports DSP ASE, so enable
367 * access to DSP resources.
369 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
370 env
->hflags
|= MIPS_HFLAG_DSP
;
374 if (env
->insn_flags
& ISA_MIPS_R2
) {
375 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
376 env
->hflags
|= MIPS_HFLAG_COP1X
;
378 } else if (env
->insn_flags
& ISA_MIPS_R1
) {
379 if (env
->hflags
& MIPS_HFLAG_64
) {
380 env
->hflags
|= MIPS_HFLAG_COP1X
;
382 } else if (env
->insn_flags
& ISA_MIPS4
) {
384 * All supported MIPS IV CPUs use the XX (CU3) to enable
385 * and disable the MIPS IV extensions to the MIPS III ISA.
386 * Some other MIPS IV CPUs ignore the bit, so the check here
387 * would be too restrictive for them.
389 if (env
->CP0_Status
& (1U << CP0St_CU3
)) {
390 env
->hflags
|= MIPS_HFLAG_COP1X
;
393 if (ase_msa_available(env
)) {
394 if (env
->CP0_Config5
& (1 << CP0C5_MSAEn
)) {
395 env
->hflags
|= MIPS_HFLAG_MSA
;
398 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
399 if (env
->CP0_Config5
& (1 << CP0C5_FRE
)) {
400 env
->hflags
|= MIPS_HFLAG_FRE
;
403 if (env
->CP0_Config3
& (1 << CP0C3_LPA
)) {
404 if (env
->CP0_PageGrain
& (1 << CP0PG_ELPA
)) {
405 env
->hflags
|= MIPS_HFLAG_ELPA
;