hw/pci-host/pnv_phb4_pec.c

   1 /*
   2  * QEMU PowerPC PowerNV (POWER9) PHB4 model
   3  *
   4  * Copyright (c) 2018-2020, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "qapi/error.h"
  11 #include "qemu-common.h"
  12 #include "qemu/log.h"
  13 #include "target/ppc/cpu.h"
  14 #include "hw/ppc/fdt.h"
  15 #include "hw/pci-host/pnv_phb4_regs.h"
  16 #include "hw/pci-host/pnv_phb4.h"
  17 #include "hw/ppc/pnv_xscom.h"
  18 #include "hw/pci/pci_bridge.h"
  19 #include "hw/pci/pci_bus.h"
  20 #include "hw/ppc/pnv.h"
  21 #include "hw/qdev-properties.h"
  22 #include "sysemu/sysemu.h"
  23
  24 #include <libfdt.h>
  25
  26 #define phb_pec_error(pec, fmt, ...)                                    \
  27     qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n",        \
  28                   (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
  29
  30
  31 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr,
  32                                         unsigned size)
  33 {
  34     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  35     uint32_t reg = addr >> 3;
  36
  37     /* TODO: add list of allowed registers and error out if not */
  38     return pec->nest_regs[reg];
  39 }
  40
  41 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr,
  42                                      uint64_t val, unsigned size)
  43 {
  44     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  45     uint32_t reg = addr >> 3;
  46
  47     switch (reg) {
  48     case PEC_NEST_PBCQ_HW_CONFIG:
  49     case PEC_NEST_DROP_PRIO_CTRL:
  50     case PEC_NEST_PBCQ_ERR_INJECT:
  51     case PEC_NEST_PCI_NEST_CLK_TRACE_CTL:
  52     case PEC_NEST_PBCQ_PMON_CTRL:
  53     case PEC_NEST_PBCQ_PBUS_ADDR_EXT:
  54     case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT:
  55     case PEC_NEST_CAPP_CTRL:
  56     case PEC_NEST_PBCQ_READ_STK_OVR:
  57     case PEC_NEST_PBCQ_WRITE_STK_OVR:
  58     case PEC_NEST_PBCQ_STORE_STK_OVR:
  59     case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL:
  60         pec->nest_regs[reg] = val;
  61         break;
  62     default:
  63         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
  64                       addr, val);
  65     }
  66 }
  67
  68 static const MemoryRegionOps pnv_pec_nest_xscom_ops = {
  69     .read = pnv_pec_nest_xscom_read,
  70     .write = pnv_pec_nest_xscom_write,
  71     .valid.min_access_size = 8,
  72     .valid.max_access_size = 8,
  73     .impl.min_access_size = 8,
  74     .impl.max_access_size = 8,
  75     .endianness = DEVICE_BIG_ENDIAN,
  76 };
  77
  78 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr,
  79                                        unsigned size)
  80 {
  81     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  82     uint32_t reg = addr >> 3;
  83
  84     /* TODO: add list of allowed registers and error out if not */
  85     return pec->pci_regs[reg];
  86 }
  87
  88 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr,
  89                                     uint64_t val, unsigned size)
  90 {
  91     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  92     uint32_t reg = addr >> 3;
  93
  94     switch (reg) {
  95     case PEC_PCI_PBAIB_HW_CONFIG:
  96     case PEC_PCI_PBAIB_READ_STK_OVR:
  97         pec->pci_regs[reg] = val;
  98         break;
  99     default:
 100         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
 101                       addr, val);
 102     }
 103 }
 104
 105 static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
 106     .read = pnv_pec_pci_xscom_read,
 107     .write = pnv_pec_pci_xscom_write,
 108     .valid.min_access_size = 8,
 109     .valid.max_access_size = 8,
 110     .impl.min_access_size = 8,
 111     .impl.max_access_size = 8,
 112     .endianness = DEVICE_BIG_ENDIAN,
 113 };
 114
 115 static void pnv_pec_instance_init(Object *obj)
 116 {
 117     PnvPhb4PecState *pec = PNV_PHB4_PEC(obj);
 118     int i;
 119
 120     for (i = 0; i < PHB4_PEC_MAX_STACKS; i++) {
 121         object_initialize_child(obj, "stack[*]", &pec->stacks[i],
 122                                 TYPE_PNV_PHB4_PEC_STACK);
 123     }
 124 }
 125
 126 static void pnv_pec_realize(DeviceState *dev, Error **errp)
 127 {
 128     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 129     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
 130     char name[64];
 131     int i;
 132
 133     if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
 134         error_setg(errp, "invalid PEC index: %d", pec->index);
 135         return;
 136     }
 137
 138     pec->num_stacks = pecc->num_stacks[pec->index];
 139
 140     /* Create stacks */
 141     for (i = 0; i < pec->num_stacks; i++) {
 142         PnvPhb4PecStack *stack = &pec->stacks[i];
 143         Object *stk_obj = OBJECT(stack);
 144
 145         object_property_set_int(stk_obj, "stack-no", i, &error_abort);
 146         object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort);
 147         if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) {
 148             return;
 149         }
 150     }
 151     for (; i < PHB4_PEC_MAX_STACKS; i++) {
 152         object_unparent(OBJECT(&pec->stacks[i]));
 153     }
 154
 155     /* Initialize the XSCOM regions for the PEC registers */
 156     snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
 157              pec->index);
 158     pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev),
 159                           &pnv_pec_nest_xscom_ops, pec, name,
 160                           PHB4_PEC_NEST_REGS_COUNT);
 161
 162     snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id,
 163              pec->index);
 164     pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev),
 165                           &pnv_pec_pci_xscom_ops, pec, name,
 166                           PHB4_PEC_PCI_REGS_COUNT);
 167 }
 168
 169 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
 170                             int xscom_offset)
 171 {
 172     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 173     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev);
 174     uint32_t nbase = pecc->xscom_nest_base(pec);
 175     uint32_t pbase = pecc->xscom_pci_base(pec);
 176     int offset, i;
 177     char *name;
 178     uint32_t reg[] = {
 179         cpu_to_be32(nbase),
 180         cpu_to_be32(pecc->xscom_nest_size),
 181         cpu_to_be32(pbase),
 182         cpu_to_be32(pecc->xscom_pci_size),
 183     };
 184
 185     name = g_strdup_printf("pbcq@%x", nbase);
 186     offset = fdt_add_subnode(fdt, xscom_offset, name);
 187     _FDT(offset);
 188     g_free(name);
 189
 190     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 191
 192     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index)));
 193     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1)));
 194     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0)));
 195     _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
 196                       pecc->compat_size)));
 197
 198     for (i = 0; i < pec->num_stacks; i++) {
 199         int phb_id = pnv_phb4_pec_get_phb_id(pec, i);
 200         int stk_offset;
 201
 202         name = g_strdup_printf("stack@%x", i);
 203         stk_offset = fdt_add_subnode(fdt, offset, name);
 204         _FDT(stk_offset);
 205         g_free(name);
 206         _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat,
 207                           pecc->stk_compat_size)));
 208         _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i)));
 209         _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id)));
 210     }
 211
 212     return 0;
 213 }
 214
 215 static Property pnv_pec_properties[] = {
 216         DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
 217         DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
 218         DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
 219                          PnvChip *),
 220         DEFINE_PROP_END_OF_LIST(),
 221 };
 222
 223 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
 224 {
 225     return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
 226 }
 227
 228 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
 229 {
 230     return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index;
 231 }
 232
 233 /*
 234  * PEC0 -> 1 stack
 235  * PEC1 -> 2 stacks
 236  * PEC2 -> 3 stacks
 237  */
 238 static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 };
 239
 240 static void pnv_pec_class_init(ObjectClass *klass, void *data)
 241 {
 242     DeviceClass *dc = DEVICE_CLASS(klass);
 243     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 244     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
 245     static const char compat[] = "ibm,power9-pbcq";
 246     static const char stk_compat[] = "ibm,power9-phb-stack";
 247
 248     xdc->dt_xscom = pnv_pec_dt_xscom;
 249
 250     dc->realize = pnv_pec_realize;
 251     device_class_set_props(dc, pnv_pec_properties);
 252     dc->user_creatable = false;
 253
 254     pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
 255     pecc->xscom_pci_base  = pnv_pec_xscom_pci_base;
 256     pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE;
 257     pecc->xscom_pci_size  = PNV9_XSCOM_PEC_PCI_SIZE;
 258     pecc->compat = compat;
 259     pecc->compat_size = sizeof(compat);
 260     pecc->stk_compat = stk_compat;
 261     pecc->stk_compat_size = sizeof(stk_compat);
 262     pecc->version = PNV_PHB4_VERSION;
 263     pecc->num_stacks = pnv_pec_num_stacks;
 264 }
 265
 266 static const TypeInfo pnv_pec_type_info = {
 267     .name          = TYPE_PNV_PHB4_PEC,
 268     .parent        = TYPE_DEVICE,
 269     .instance_size = sizeof(PnvPhb4PecState),
 270     .instance_init = pnv_pec_instance_init,
 271     .class_init    = pnv_pec_class_init,
 272     .class_size    = sizeof(PnvPhb4PecClass),
 273     .interfaces    = (InterfaceInfo[]) {
 274         { TYPE_PNV_XSCOM_INTERFACE },
 275         { }
 276     }
 277 };
 278
 279 static void pnv_pec_stk_default_phb_realize(PnvPhb4PecStack *stack,
 280                                             Error **errp)
 281 {
 282     PnvPhb4PecState *pec = stack->pec;
 283     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
 284     int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no);
 285
 286     stack->phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4));
 287
 288     object_property_set_link(OBJECT(stack->phb), "pec", OBJECT(pec),
 289                              &error_abort);
 290     object_property_set_int(OBJECT(stack->phb), "chip-id", pec->chip_id,
 291                             &error_fatal);
 292     object_property_set_int(OBJECT(stack->phb), "index", phb_id,
 293                             &error_fatal);
 294     object_property_set_int(OBJECT(stack->phb), "version", pecc->version,
 295                             &error_fatal);
 296
 297     if (!sysbus_realize(SYS_BUS_DEVICE(stack->phb), errp)) {
 298         return;
 299     }
 300 }
 301
 302 static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
 303 {
 304     PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev);
 305
 306     if (!defaults_enabled()) {
 307         return;
 308     }
 309
 310     pnv_pec_stk_default_phb_realize(stack, errp);
 311 }
 312
 313 static Property pnv_pec_stk_properties[] = {
 314         DEFINE_PROP_UINT32("stack-no", PnvPhb4PecStack, stack_no, 0),
 315         DEFINE_PROP_LINK("pec", PnvPhb4PecStack, pec, TYPE_PNV_PHB4_PEC,
 316                          PnvPhb4PecState *),
 317         DEFINE_PROP_END_OF_LIST(),
 318 };
 319
 320 static void pnv_pec_stk_class_init(ObjectClass *klass, void *data)
 321 {
 322     DeviceClass *dc = DEVICE_CLASS(klass);
 323
 324     device_class_set_props(dc, pnv_pec_stk_properties);
 325     dc->realize = pnv_pec_stk_realize;
 326     dc->user_creatable = false;
 327
 328     /* TODO: reset regs ? */
 329 }
 330
 331 static const TypeInfo pnv_pec_stk_type_info = {
 332     .name          = TYPE_PNV_PHB4_PEC_STACK,
 333     .parent        = TYPE_DEVICE,
 334     .instance_size = sizeof(PnvPhb4PecStack),
 335     .class_init    = pnv_pec_stk_class_init,
 336     .interfaces    = (InterfaceInfo[]) {
 337         { TYPE_PNV_XSCOM_INTERFACE },
 338         { }
 339     }
 340 };
 341
 342 static void pnv_pec_register_types(void)
 343 {
 344     type_register_static(&pnv_pec_type_info);
 345     type_register_static(&pnv_pec_stk_type_info);
 346 }
 347
 348 type_init(pnv_pec_register_types);