| blob | b7e9afb97897940d5a7ac1fab01dfc5852956cee |
1 /*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
10 static inline TCGv_ptr gen_avr_ptr(int reg)
11 {
12 TCGv_ptr r = tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
14 return r;
15 }
17 #define GEN_VR_LDX(name, opc2, opc3) \
18 static void glue(gen_, name)(DisasContext *ctx) \
19 { \
20 TCGv EA; \
21 TCGv_i64 avr; \
22 if (unlikely(!ctx->altivec_enabled)) { \
23 gen_exception(ctx, POWERPC_EXCP_VPU); \
24 return; \
25 } \
26 gen_set_access_type(ctx, ACCESS_INT); \
27 avr = tcg_temp_new_i64(); \
28 EA = tcg_temp_new(); \
29 gen_addr_reg_index(ctx, EA); \
30 tcg_gen_andi_tl(EA, EA, ~0xf); \
31 /* \
32 * We only need to swap high and low halves. gen_qemu_ld64_i64 \
33 * does necessary 64-bit byteswap already. \
34 */ \
35 if (ctx->le_mode) { \
36 gen_qemu_ld64_i64(ctx, avr, EA); \
37 set_avr64(rD(ctx->opcode), avr, false); \
38 tcg_gen_addi_tl(EA, EA, 8); \
39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, true); \
41 } else { \
42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
44 tcg_gen_addi_tl(EA, EA, 8); \
45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, false); \
47 } \
48 tcg_temp_free(EA); \
49 tcg_temp_free_i64(avr); \
50 }
52 #define GEN_VR_STX(name, opc2, opc3) \
53 static void gen_st##name(DisasContext *ctx) \
54 { \
55 TCGv EA; \
56 TCGv_i64 avr; \
57 if (unlikely(!ctx->altivec_enabled)) { \
58 gen_exception(ctx, POWERPC_EXCP_VPU); \
59 return; \
60 } \
61 gen_set_access_type(ctx, ACCESS_INT); \
62 avr = tcg_temp_new_i64(); \
63 EA = tcg_temp_new(); \
64 gen_addr_reg_index(ctx, EA); \
65 tcg_gen_andi_tl(EA, EA, ~0xf); \
66 /* \
67 * We only need to swap high and low halves. gen_qemu_st64_i64 \
68 * does necessary 64-bit byteswap already. \
69 */ \
70 if (ctx->le_mode) { \
71 get_avr64(avr, rD(ctx->opcode), false); \
72 gen_qemu_st64_i64(ctx, avr, EA); \
73 tcg_gen_addi_tl(EA, EA, 8); \
74 get_avr64(avr, rD(ctx->opcode), true); \
75 gen_qemu_st64_i64(ctx, avr, EA); \
76 } else { \
77 get_avr64(avr, rD(ctx->opcode), true); \
78 gen_qemu_st64_i64(ctx, avr, EA); \
79 tcg_gen_addi_tl(EA, EA, 8); \
80 get_avr64(avr, rD(ctx->opcode), false); \
81 gen_qemu_st64_i64(ctx, avr, EA); \
82 } \
83 tcg_temp_free(EA); \
84 tcg_temp_free_i64(avr); \
85 }
87 #define GEN_VR_LVE(name, opc2, opc3, size) \
88 static void gen_lve##name(DisasContext *ctx) \
89 { \
90 TCGv EA; \
91 TCGv_ptr rs; \
92 if (unlikely(!ctx->altivec_enabled)) { \
93 gen_exception(ctx, POWERPC_EXCP_VPU); \
94 return; \
95 } \
96 gen_set_access_type(ctx, ACCESS_INT); \
97 EA = tcg_temp_new(); \
98 gen_addr_reg_index(ctx, EA); \
99 if (size > 1) { \
100 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
101 } \
102 rs = gen_avr_ptr(rS(ctx->opcode)); \
103 gen_helper_lve##name(cpu_env, rs, EA); \
104 tcg_temp_free(EA); \
105 tcg_temp_free_ptr(rs); \
106 }
108 #define GEN_VR_STVE(name, opc2, opc3, size) \
109 static void gen_stve##name(DisasContext *ctx) \
110 { \
111 TCGv EA; \
112 TCGv_ptr rs; \
113 if (unlikely(!ctx->altivec_enabled)) { \
114 gen_exception(ctx, POWERPC_EXCP_VPU); \
115 return; \
116 } \
117 gen_set_access_type(ctx, ACCESS_INT); \
118 EA = tcg_temp_new(); \
119 gen_addr_reg_index(ctx, EA); \
120 if (size > 1) { \
121 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
122 } \
123 rs = gen_avr_ptr(rS(ctx->opcode)); \
124 gen_helper_stve##name(cpu_env, rs, EA); \
125 tcg_temp_free(EA); \
126 tcg_temp_free_ptr(rs); \
127 }
129 GEN_VR_LDX(lvx, 0x07, 0x03);
130 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
131 GEN_VR_LDX(lvxl, 0x07, 0x0B);
133 GEN_VR_LVE(bx, 0x07, 0x00, 1);
134 GEN_VR_LVE(hx, 0x07, 0x01, 2);
135 GEN_VR_LVE(wx, 0x07, 0x02, 4);
137 GEN_VR_STX(svx, 0x07, 0x07);
138 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
139 GEN_VR_STX(svxl, 0x07, 0x0F);
141 GEN_VR_STVE(bx, 0x07, 0x04, 1);
142 GEN_VR_STVE(hx, 0x07, 0x05, 2);
143 GEN_VR_STVE(wx, 0x07, 0x06, 4);
145 static void gen_mfvscr(DisasContext *ctx)
146 {
147 TCGv_i32 t;
148 TCGv_i64 avr;
149 if (unlikely(!ctx->altivec_enabled)) {
150 gen_exception(ctx, POWERPC_EXCP_VPU);
151 return;
152 }
153 avr = tcg_temp_new_i64();
154 tcg_gen_movi_i64(avr, 0);
155 set_avr64(rD(ctx->opcode), avr, true);
156 t = tcg_temp_new_i32();
157 gen_helper_mfvscr(t, cpu_env);
158 tcg_gen_extu_i32_i64(avr, t);
159 set_avr64(rD(ctx->opcode), avr, false);
160 tcg_temp_free_i32(t);
161 tcg_temp_free_i64(avr);
162 }
164 static void gen_mtvscr(DisasContext *ctx)
165 {
166 TCGv_i32 val;
167 int bofs;
169 if (unlikely(!ctx->altivec_enabled)) {
170 gen_exception(ctx, POWERPC_EXCP_VPU);
171 return;
172 }
174 val = tcg_temp_new_i32();
175 bofs = avr_full_offset(rB(ctx->opcode));
176 #ifdef HOST_WORDS_BIGENDIAN
177 bofs += 3 * 4;
178 #endif
180 tcg_gen_ld_i32(val, cpu_env, bofs);
181 gen_helper_mtvscr(cpu_env, val);
182 tcg_temp_free_i32(val);
183 }
185 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \
186 static void glue(gen_, name)(DisasContext *ctx) \
187 { \
188 TCGv_i64 t0; \
189 TCGv_i64 t1; \
190 TCGv_i64 t2; \
191 TCGv_i64 avr; \
192 TCGv_i64 ten, z; \
193 \
194 if (unlikely(!ctx->altivec_enabled)) { \
195 gen_exception(ctx, POWERPC_EXCP_VPU); \
196 return; \
197 } \
198 \
199 t0 = tcg_temp_new_i64(); \
200 t1 = tcg_temp_new_i64(); \
201 t2 = tcg_temp_new_i64(); \
202 avr = tcg_temp_new_i64(); \
203 ten = tcg_const_i64(10); \
204 z = tcg_const_i64(0); \
205 \
206 if (add_cin) { \
207 get_avr64(avr, rA(ctx->opcode), false); \
208 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
209 get_avr64(avr, rB(ctx->opcode), false); \
210 tcg_gen_andi_i64(t2, avr, 0xF); \
211 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
212 set_avr64(rD(ctx->opcode), avr, false); \
213 } else { \
214 get_avr64(avr, rA(ctx->opcode), false); \
215 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
216 set_avr64(rD(ctx->opcode), avr, false); \
217 } \
218 \
219 if (ret_carry) { \
220 get_avr64(avr, rA(ctx->opcode), true); \
221 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
222 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
223 set_avr64(rD(ctx->opcode), avr, false); \
224 set_avr64(rD(ctx->opcode), z, true); \
225 } else { \
226 get_avr64(avr, rA(ctx->opcode), true); \
227 tcg_gen_mul_i64(t0, avr, ten); \
228 tcg_gen_add_i64(avr, t0, t2); \
229 set_avr64(rD(ctx->opcode), avr, true); \
230 } \
231 \
232 tcg_temp_free_i64(t0); \
233 tcg_temp_free_i64(t1); \
234 tcg_temp_free_i64(t2); \
235 tcg_temp_free_i64(avr); \
236 tcg_temp_free_i64(ten); \
237 tcg_temp_free_i64(z); \
238 } \
240 GEN_VX_VMUL10(vmul10uq, 0, 0);
241 GEN_VX_VMUL10(vmul10euq, 1, 0);
242 GEN_VX_VMUL10(vmul10cuq, 0, 1);
243 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
245 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
246 static void glue(gen_, name)(DisasContext *ctx) \
247 { \
248 if (unlikely(!ctx->altivec_enabled)) { \
249 gen_exception(ctx, POWERPC_EXCP_VPU); \
250 return; \
251 } \
252 \
253 tcg_op(vece, \
254 avr_full_offset(rD(ctx->opcode)), \
255 avr_full_offset(rA(ctx->opcode)), \
256 avr_full_offset(rB(ctx->opcode)), \
257 16, 16); \
258 }
260 /* Logical operations */
261 GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
262 GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
263 GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
264 GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
265 GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
266 GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
267 GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
268 GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
270 #define GEN_VXFORM(name, opc2, opc3) \
271 static void glue(gen_, name)(DisasContext *ctx) \
272 { \
273 TCGv_ptr ra, rb, rd; \
274 if (unlikely(!ctx->altivec_enabled)) { \
275 gen_exception(ctx, POWERPC_EXCP_VPU); \
276 return; \
277 } \
278 ra = gen_avr_ptr(rA(ctx->opcode)); \
279 rb = gen_avr_ptr(rB(ctx->opcode)); \
280 rd = gen_avr_ptr(rD(ctx->opcode)); \
281 gen_helper_##name(rd, ra, rb); \
282 tcg_temp_free_ptr(ra); \
283 tcg_temp_free_ptr(rb); \
284 tcg_temp_free_ptr(rd); \
285 }
287 #define GEN_VXFORM_TRANS(name, opc2, opc3) \
288 static void glue(gen_, name)(DisasContext *ctx) \
289 { \
290 if (unlikely(!ctx->altivec_enabled)) { \
291 gen_exception(ctx, POWERPC_EXCP_VPU); \
292 return; \
293 } \
294 trans_##name(ctx); \
295 }
297 #define GEN_VXFORM_ENV(name, opc2, opc3) \
298 static void glue(gen_, name)(DisasContext *ctx) \
299 { \
300 TCGv_ptr ra, rb, rd; \
301 if (unlikely(!ctx->altivec_enabled)) { \
302 gen_exception(ctx, POWERPC_EXCP_VPU); \
303 return; \
304 } \
305 ra = gen_avr_ptr(rA(ctx->opcode)); \
306 rb = gen_avr_ptr(rB(ctx->opcode)); \
307 rd = gen_avr_ptr(rD(ctx->opcode)); \
308 gen_helper_##name(cpu_env, rd, ra, rb); \
309 tcg_temp_free_ptr(ra); \
310 tcg_temp_free_ptr(rb); \
311 tcg_temp_free_ptr(rd); \
312 }
314 #define GEN_VXFORM3(name, opc2, opc3) \
315 static void glue(gen_, name)(DisasContext *ctx) \
316 { \
317 TCGv_ptr ra, rb, rc, rd; \
318 if (unlikely(!ctx->altivec_enabled)) { \
319 gen_exception(ctx, POWERPC_EXCP_VPU); \
320 return; \
321 } \
322 ra = gen_avr_ptr(rA(ctx->opcode)); \
323 rb = gen_avr_ptr(rB(ctx->opcode)); \
324 rc = gen_avr_ptr(rC(ctx->opcode)); \
325 rd = gen_avr_ptr(rD(ctx->opcode)); \
326 gen_helper_##name(rd, ra, rb, rc); \
327 tcg_temp_free_ptr(ra); \
328 tcg_temp_free_ptr(rb); \
329 tcg_temp_free_ptr(rc); \
330 tcg_temp_free_ptr(rd); \
331 }
333 /*
334 * Support for Altivec instruction pairs that use bit 31 (Rc) as
335 * an opcode bit. In general, these pairs come from different
336 * versions of the ISA, so we must also support a pair of flags for
337 * each instruction.
338 */
339 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
340 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
341 { \
342 if ((Rc(ctx->opcode) == 0) && \
343 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
344 gen_##name0(ctx); \
345 } else if ((Rc(ctx->opcode) == 1) && \
346 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
347 gen_##name1(ctx); \
348 } else { \
349 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
350 } \
351 }
353 /*
354 * We use this macro if one instruction is realized with direct
355 * translation, and second one with helper.
356 */
357 #define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
358 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
359 { \
360 if ((Rc(ctx->opcode) == 0) && \
361 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
362 if (unlikely(!ctx->altivec_enabled)) { \
363 gen_exception(ctx, POWERPC_EXCP_VPU); \
364 return; \
365 } \
366 trans_##name0(ctx); \
367 } else if ((Rc(ctx->opcode) == 1) && \
368 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
369 gen_##name1(ctx); \
370 } else { \
371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
372 } \
373 }
375 /* Adds support to provide invalid mask */
376 #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
377 name1, flg1, flg2_1, inval1) \
378 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
379 { \
380 if ((Rc(ctx->opcode) == 0) && \
381 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
382 !(ctx->opcode & inval0)) { \
383 gen_##name0(ctx); \
384 } else if ((Rc(ctx->opcode) == 1) && \
385 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
386 !(ctx->opcode & inval1)) { \
387 gen_##name1(ctx); \
388 } else { \
389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
390 } \
391 }
393 #define GEN_VXFORM_HETRO(name, opc2, opc3) \
394 static void glue(gen_, name)(DisasContext *ctx) \
395 { \
396 TCGv_ptr rb; \
397 if (unlikely(!ctx->altivec_enabled)) { \
398 gen_exception(ctx, POWERPC_EXCP_VPU); \
399 return; \
400 } \
401 rb = gen_avr_ptr(rB(ctx->opcode)); \
402 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
403 tcg_temp_free_ptr(rb); \
404 }
406 GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
407 GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
408 vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
409 GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
410 GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
411 vmul10ecuq, PPC_NONE, PPC2_ISA300)
412 GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
413 GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
414 GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
415 GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
416 GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
417 GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
418 GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
419 GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
420 GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
421 GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
422 GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
423 GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
424 GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
425 GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
426 GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
427 GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
428 GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
429 GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
430 GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
431 GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
432 GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
433 GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
434 GEN_VXFORM(vavgub, 1, 16);
435 GEN_VXFORM(vabsdub, 1, 16);
436 GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
437 vabsdub, PPC_NONE, PPC2_ISA300)
438 GEN_VXFORM(vavguh, 1, 17);
439 GEN_VXFORM(vabsduh, 1, 17);
440 GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
441 vabsduh, PPC_NONE, PPC2_ISA300)
442 GEN_VXFORM(vavguw, 1, 18);
443 GEN_VXFORM(vabsduw, 1, 18);
444 GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
445 vabsduw, PPC_NONE, PPC2_ISA300)
446 GEN_VXFORM(vavgsb, 1, 20);
447 GEN_VXFORM(vavgsh, 1, 21);
448 GEN_VXFORM(vavgsw, 1, 22);
449 GEN_VXFORM(vmrghb, 6, 0);
450 GEN_VXFORM(vmrghh, 6, 1);
451 GEN_VXFORM(vmrghw, 6, 2);
452 GEN_VXFORM(vmrglb, 6, 4);
453 GEN_VXFORM(vmrglh, 6, 5);
454 GEN_VXFORM(vmrglw, 6, 6);
456 static void trans_vmrgew(DisasContext *ctx)
457 {
458 int VT = rD(ctx->opcode);
459 int VA = rA(ctx->opcode);
460 int VB = rB(ctx->opcode);
461 TCGv_i64 tmp = tcg_temp_new_i64();
462 TCGv_i64 avr = tcg_temp_new_i64();
464 get_avr64(avr, VB, true);
465 tcg_gen_shri_i64(tmp, avr, 32);
466 get_avr64(avr, VA, true);
467 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
468 set_avr64(VT, avr, true);
470 get_avr64(avr, VB, false);
471 tcg_gen_shri_i64(tmp, avr, 32);
472 get_avr64(avr, VA, false);
473 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
474 set_avr64(VT, avr, false);
476 tcg_temp_free_i64(tmp);
477 tcg_temp_free_i64(avr);
478 }
480 static void trans_vmrgow(DisasContext *ctx)
481 {
482 int VT = rD(ctx->opcode);
483 int VA = rA(ctx->opcode);
484 int VB = rB(ctx->opcode);
485 TCGv_i64 t0 = tcg_temp_new_i64();
486 TCGv_i64 t1 = tcg_temp_new_i64();
487 TCGv_i64 avr = tcg_temp_new_i64();
489 get_avr64(t0, VB, true);
490 get_avr64(t1, VA, true);
491 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
492 set_avr64(VT, avr, true);
494 get_avr64(t0, VB, false);
495 get_avr64(t1, VA, false);
496 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
497 set_avr64(VT, avr, false);
499 tcg_temp_free_i64(t0);
500 tcg_temp_free_i64(t1);
501 tcg_temp_free_i64(avr);
502 }
504 /*
505 * lvsl VRT,RA,RB - Load Vector for Shift Left
506 *
507 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
508 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
509 * Bytes sh:sh+15 of X are placed into vD.
510 */
511 static void trans_lvsl(DisasContext *ctx)
512 {
513 int VT = rD(ctx->opcode);
514 TCGv_i64 result = tcg_temp_new_i64();
515 TCGv_i64 sh = tcg_temp_new_i64();
516 TCGv EA = tcg_temp_new();
518 /* Get sh(from description) by anding EA with 0xf. */
519 gen_addr_reg_index(ctx, EA);
520 tcg_gen_extu_tl_i64(sh, EA);
521 tcg_gen_andi_i64(sh, sh, 0xfULL);
523 /*
524 * Create bytes sh:sh+7 of X(from description) and place them in
525 * higher doubleword of vD.
526 */
527 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
528 tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
529 set_avr64(VT, result, true);
530 /*
531 * Create bytes sh+8:sh+15 of X(from description) and place them in
532 * lower doubleword of vD.
533 */
534 tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
535 set_avr64(VT, result, false);
537 tcg_temp_free_i64(result);
538 tcg_temp_free_i64(sh);
539 tcg_temp_free(EA);
540 }
542 /*
543 * lvsr VRT,RA,RB - Load Vector for Shift Right
544 *
545 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
546 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
547 * Bytes (16-sh):(31-sh) of X are placed into vD.
548 */
549 static void trans_lvsr(DisasContext *ctx)
550 {
551 int VT = rD(ctx->opcode);
552 TCGv_i64 result = tcg_temp_new_i64();
553 TCGv_i64 sh = tcg_temp_new_i64();
554 TCGv EA = tcg_temp_new();
557 /* Get sh(from description) by anding EA with 0xf. */
558 gen_addr_reg_index(ctx, EA);
559 tcg_gen_extu_tl_i64(sh, EA);
560 tcg_gen_andi_i64(sh, sh, 0xfULL);
562 /*
563 * Create bytes (16-sh):(23-sh) of X(from description) and place them in
564 * higher doubleword of vD.
565 */
566 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
567 tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
568 set_avr64(VT, result, true);
569 /*
570 * Create bytes (24-sh):(32-sh) of X(from description) and place them in
571 * lower doubleword of vD.
572 */
573 tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
574 set_avr64(VT, result, false);
576 tcg_temp_free_i64(result);
577 tcg_temp_free_i64(sh);
578 tcg_temp_free(EA);
579 }
581 /*
582 * vsl VRT,VRA,VRB - Vector Shift Left
583 *
584 * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
585 * Lowest 3 bits in each byte element of register vB must be identical or
586 * result is undefined.
587 */
588 static void trans_vsl(DisasContext *ctx)
589 {
590 int VT = rD(ctx->opcode);
591 int VA = rA(ctx->opcode);
592 int VB = rB(ctx->opcode);
593 TCGv_i64 avr = tcg_temp_new_i64();
594 TCGv_i64 sh = tcg_temp_new_i64();
595 TCGv_i64 carry = tcg_temp_new_i64();
596 TCGv_i64 tmp = tcg_temp_new_i64();
598 /* Place bits 125-127 of vB in 'sh'. */
599 get_avr64(avr, VB, false);
600 tcg_gen_andi_i64(sh, avr, 0x07ULL);
602 /*
603 * Save highest 'sh' bits of lower doubleword element of vA in variable
604 * 'carry' and perform shift on lower doubleword.
605 */
606 get_avr64(avr, VA, false);
607 tcg_gen_subfi_i64(tmp, 32, sh);
608 tcg_gen_shri_i64(carry, avr, 32);
609 tcg_gen_shr_i64(carry, carry, tmp);
610 tcg_gen_shl_i64(avr, avr, sh);
611 set_avr64(VT, avr, false);
613 /*
614 * Perform shift on higher doubleword element of vA and replace lowest
615 * 'sh' bits with 'carry'.
616 */
617 get_avr64(avr, VA, true);
618 tcg_gen_shl_i64(avr, avr, sh);
619 tcg_gen_or_i64(avr, avr, carry);
620 set_avr64(VT, avr, true);
622 tcg_temp_free_i64(avr);
623 tcg_temp_free_i64(sh);
624 tcg_temp_free_i64(carry);
625 tcg_temp_free_i64(tmp);
626 }
628 /*
629 * vsr VRT,VRA,VRB - Vector Shift Right
630 *
631 * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
632 * Lowest 3 bits in each byte element of register vB must be identical or
633 * result is undefined.
634 */
635 static void trans_vsr(DisasContext *ctx)
636 {
637 int VT = rD(ctx->opcode);
638 int VA = rA(ctx->opcode);
639 int VB = rB(ctx->opcode);
640 TCGv_i64 avr = tcg_temp_new_i64();
641 TCGv_i64 sh = tcg_temp_new_i64();
642 TCGv_i64 carry = tcg_temp_new_i64();
643 TCGv_i64 tmp = tcg_temp_new_i64();
645 /* Place bits 125-127 of vB in 'sh'. */
646 get_avr64(avr, VB, false);
647 tcg_gen_andi_i64(sh, avr, 0x07ULL);
649 /*
650 * Save lowest 'sh' bits of higher doubleword element of vA in variable
651 * 'carry' and perform shift on higher doubleword.
652 */
653 get_avr64(avr, VA, true);
654 tcg_gen_subfi_i64(tmp, 32, sh);
655 tcg_gen_shli_i64(carry, avr, 32);
656 tcg_gen_shl_i64(carry, carry, tmp);
657 tcg_gen_shr_i64(avr, avr, sh);
658 set_avr64(VT, avr, true);
659 /*
660 * Perform shift on lower doubleword element of vA and replace highest
661 * 'sh' bits with 'carry'.
662 */
663 get_avr64(avr, VA, false);
664 tcg_gen_shr_i64(avr, avr, sh);
665 tcg_gen_or_i64(avr, avr, carry);
666 set_avr64(VT, avr, false);
668 tcg_temp_free_i64(avr);
669 tcg_temp_free_i64(sh);
670 tcg_temp_free_i64(carry);
671 tcg_temp_free_i64(tmp);
672 }
674 /*
675 * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
676 *
677 * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
678 * register are concatenated and placed into ith byte of appropriate doubleword
679 * element in destination register.
680 *
681 * Following solution is done for both doubleword elements of source register
682 * in parallel, in order to reduce the number of instructions needed(that's why
683 * arrays are used):
684 * First, both doubleword elements of source register vB are placed in
685 * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
686 * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
687 * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
688 * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
689 * have to be shifted right for 7 and 8 places, respectively, in order to get
690 * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
691 * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
692 * After first 8 iteration(first loop), all the first bits are in their final
693 * places, all second bits but second bit from eight byte are in their places...
694 * only 1 eight bit from eight byte is in it's place). In second loop we do all
695 * operations symmetrically, in order to get other half of bits in their final
696 * spots. Results for first and second doubleword elements are saved in
697 * result[0] and result[1] respectively. In the end those results are saved in
698 * appropriate doubleword element of destination register vD.
699 */
700 static void trans_vgbbd(DisasContext *ctx)
701 {
702 int VT = rD(ctx->opcode);
703 int VB = rB(ctx->opcode);
704 TCGv_i64 tmp = tcg_temp_new_i64();
705 uint64_t mask = 0x8040201008040201ULL;
706 int i, j;
708 TCGv_i64 result[2];
709 result[0] = tcg_temp_new_i64();
710 result[1] = tcg_temp_new_i64();
711 TCGv_i64 avr[2];
712 avr[0] = tcg_temp_new_i64();
713 avr[1] = tcg_temp_new_i64();
714 TCGv_i64 tcg_mask = tcg_temp_new_i64();
716 tcg_gen_movi_i64(tcg_mask, mask);
717 for (j = 0; j < 2; j++) {
718 get_avr64(avr[j], VB, j);
719 tcg_gen_and_i64(result[j], avr[j], tcg_mask);
720 }
721 for (i = 1; i < 8; i++) {
722 tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
723 for (j = 0; j < 2; j++) {
724 tcg_gen_shri_i64(tmp, avr[j], i * 7);
725 tcg_gen_and_i64(tmp, tmp, tcg_mask);
726 tcg_gen_or_i64(result[j], result[j], tmp);
727 }
728 }
729 for (i = 1; i < 8; i++) {
730 tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
731 for (j = 0; j < 2; j++) {
732 tcg_gen_shli_i64(tmp, avr[j], i * 7);
733 tcg_gen_and_i64(tmp, tmp, tcg_mask);
734 tcg_gen_or_i64(result[j], result[j], tmp);
735 }
736 }
737 for (j = 0; j < 2; j++) {
738 set_avr64(VT, result[j], j);
739 }
741 tcg_temp_free_i64(tmp);
742 tcg_temp_free_i64(tcg_mask);
743 tcg_temp_free_i64(result[0]);
744 tcg_temp_free_i64(result[1]);
745 tcg_temp_free_i64(avr[0]);
746 tcg_temp_free_i64(avr[1]);
747 }
749 /*
750 * vclzw VRT,VRB - Vector Count Leading Zeros Word
751 *
752 * Counting the number of leading zero bits of each word element in source
753 * register and placing result in appropriate word element of destination
754 * register.
755 */
756 static void trans_vclzw(DisasContext *ctx)
757 {
758 int VT = rD(ctx->opcode);
759 int VB = rB(ctx->opcode);
760 TCGv_i32 tmp = tcg_temp_new_i32();
761 int i;
763 /* Perform count for every word element using tcg_gen_clzi_i32. */
764 for (i = 0; i < 4; i++) {
765 tcg_gen_ld_i32(tmp, cpu_env,
766 offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
767 tcg_gen_clzi_i32(tmp, tmp, 32);
768 tcg_gen_st_i32(tmp, cpu_env,
769 offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
770 }
772 tcg_temp_free_i32(tmp);
773 }
775 /*
776 * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
777 *
778 * Counting the number of leading zero bits of each doubleword element in source
779 * register and placing result in appropriate doubleword element of destination
780 * register.
781 */
782 static void trans_vclzd(DisasContext *ctx)
783 {
784 int VT = rD(ctx->opcode);
785 int VB = rB(ctx->opcode);
786 TCGv_i64 avr = tcg_temp_new_i64();
788 /* high doubleword */
789 get_avr64(avr, VB, true);
790 tcg_gen_clzi_i64(avr, avr, 64);
791 set_avr64(VT, avr, true);
793 /* low doubleword */
794 get_avr64(avr, VB, false);
795 tcg_gen_clzi_i64(avr, avr, 64);
796 set_avr64(VT, avr, false);
798 tcg_temp_free_i64(avr);
799 }
801 GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
802 GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
803 GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
804 GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
805 GEN_VXFORM(vrlwnm, 2, 6);
806 GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
807 vrlwnm, PPC_NONE, PPC2_ISA300)
808 GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);
809 GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);
810 GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);
811 GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);
812 GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);
813 GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);
814 GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);
815 GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);
816 GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);
817 GEN_VXFORM(vsrv, 2, 28);
818 GEN_VXFORM(vslv, 2, 29);
819 GEN_VXFORM(vslo, 6, 16);
820 GEN_VXFORM(vsro, 6, 17);
821 GEN_VXFORM(vaddcuw, 0, 6);
822 GEN_VXFORM(vsubcuw, 0, 22);
824 #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
825 static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
826 TCGv_vec sat, TCGv_vec a, \
827 TCGv_vec b) \
828 { \
829 TCGv_vec x = tcg_temp_new_vec_matching(t); \
830 glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
831 glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
832 tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
833 tcg_gen_or_vec(VECE, sat, sat, x); \
834 tcg_temp_free_vec(x); \
835 } \
836 static void glue(gen_, NAME)(DisasContext *ctx) \
837 { \
838 static const TCGOpcode vecop_list[] = { \
839 glue(glue(INDEX_op_, NORM), _vec), \
840 glue(glue(INDEX_op_, SAT), _vec), \
841 INDEX_op_cmp_vec, 0 \
842 }; \
843 static const GVecGen4 g = { \
844 .fniv = glue(glue(gen_, NAME), _vec), \
845 .fno = glue(gen_helper_, NAME), \
846 .opt_opc = vecop_list, \
847 .write_aofs = true, \
848 .vece = VECE, \
849 }; \
850 if (unlikely(!ctx->altivec_enabled)) { \
851 gen_exception(ctx, POWERPC_EXCP_VPU); \
852 return; \
853 } \
854 tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
855 offsetof(CPUPPCState, vscr_sat), \
856 avr_full_offset(rA(ctx->opcode)), \
857 avr_full_offset(rB(ctx->opcode)), \
858 16, 16, &g); \
859 }
861 GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
862 GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
863 vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
864 GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
865 GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
866 vmul10euq, PPC_NONE, PPC2_ISA300)
867 GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
868 GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
869 GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
870 GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
871 GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
872 GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
873 GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
874 GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
875 GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
876 GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
877 GEN_VXFORM(vadduqm, 0, 4);
878 GEN_VXFORM(vaddcuq, 0, 5);
879 GEN_VXFORM3(vaddeuqm, 30, 0);
880 GEN_VXFORM3(vaddecuq, 30, 0);
881 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
882 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
883 GEN_VXFORM(vsubuqm, 0, 20);
884 GEN_VXFORM(vsubcuq, 0, 21);
885 GEN_VXFORM3(vsubeuqm, 31, 0);
886 GEN_VXFORM3(vsubecuq, 31, 0);
887 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
888 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
889 GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
890 GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
891 GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
892 GEN_VXFORM(vrlwmi, 2, 2);
893 GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
894 vrlwmi, PPC_NONE, PPC2_ISA300)
895 GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
896 GEN_VXFORM(vrldmi, 2, 3);
897 GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
898 vrldmi, PPC_NONE, PPC2_ISA300)
899 GEN_VXFORM_TRANS(vsl, 2, 7);
900 GEN_VXFORM(vrldnm, 2, 7);
901 GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
902 vrldnm, PPC_NONE, PPC2_ISA300)
903 GEN_VXFORM_TRANS(vsr, 2, 11);
904 GEN_VXFORM_ENV(vpkuhum, 7, 0);
905 GEN_VXFORM_ENV(vpkuwum, 7, 1);
906 GEN_VXFORM_ENV(vpkudum, 7, 17);
907 GEN_VXFORM_ENV(vpkuhus, 7, 2);
908 GEN_VXFORM_ENV(vpkuwus, 7, 3);
909 GEN_VXFORM_ENV(vpkudus, 7, 19);
910 GEN_VXFORM_ENV(vpkshus, 7, 4);
911 GEN_VXFORM_ENV(vpkswus, 7, 5);
912 GEN_VXFORM_ENV(vpksdus, 7, 21);
913 GEN_VXFORM_ENV(vpkshss, 7, 6);
914 GEN_VXFORM_ENV(vpkswss, 7, 7);
915 GEN_VXFORM_ENV(vpksdss, 7, 23);
916 GEN_VXFORM(vpkpx, 7, 12);
917 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
918 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
919 GEN_VXFORM_ENV(vsum4shs, 4, 25);
920 GEN_VXFORM_ENV(vsum2sws, 4, 26);
921 GEN_VXFORM_ENV(vsumsws, 4, 30);
922 GEN_VXFORM_ENV(vaddfp, 5, 0);
923 GEN_VXFORM_ENV(vsubfp, 5, 1);
924 GEN_VXFORM_ENV(vmaxfp, 5, 16);
925 GEN_VXFORM_ENV(vminfp, 5, 17);
926 GEN_VXFORM_HETRO(vextublx, 6, 24)
927 GEN_VXFORM_HETRO(vextuhlx, 6, 25)
928 GEN_VXFORM_HETRO(vextuwlx, 6, 26)
929 GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
930 vextuwlx, PPC_NONE, PPC2_ISA300)
931 GEN_VXFORM_HETRO(vextubrx, 6, 28)
932 GEN_VXFORM_HETRO(vextuhrx, 6, 29)
933 GEN_VXFORM_HETRO(vextuwrx, 6, 30)
934 GEN_VXFORM_TRANS(lvsl, 6, 31)
935 GEN_VXFORM_TRANS(lvsr, 6, 32)
936 GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
937 vextuwrx, PPC_NONE, PPC2_ISA300)
939 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
940 static void glue(gen_, name)(DisasContext *ctx) \
941 { \
942 TCGv_ptr ra, rb, rd; \
943 if (unlikely(!ctx->altivec_enabled)) { \
944 gen_exception(ctx, POWERPC_EXCP_VPU); \
945 return; \
946 } \
947 ra = gen_avr_ptr(rA(ctx->opcode)); \
948 rb = gen_avr_ptr(rB(ctx->opcode)); \
949 rd = gen_avr_ptr(rD(ctx->opcode)); \
950 gen_helper_##opname(cpu_env, rd, ra, rb); \
951 tcg_temp_free_ptr(ra); \
952 tcg_temp_free_ptr(rb); \
953 tcg_temp_free_ptr(rd); \
954 }
956 #define GEN_VXRFORM(name, opc2, opc3) \
957 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
958 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
960 /*
961 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
962 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
963 * come from different versions of the ISA, so we must also support a
964 * pair of flags for each instruction.
965 */
966 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
967 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
968 { \
969 if ((Rc(ctx->opcode) == 0) && \
970 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
971 if (Rc21(ctx->opcode) == 0) { \
972 gen_##name0(ctx); \
973 } else { \
974 gen_##name0##_(ctx); \
975 } \
976 } else if ((Rc(ctx->opcode) == 1) && \
977 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
978 if (Rc21(ctx->opcode) == 0) { \
979 gen_##name1(ctx); \
980 } else { \
981 gen_##name1##_(ctx); \
982 } \
983 } else { \
984 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
985 } \
986 }
988 static void do_vcmp_rc(int vrt)
989 {
990 TCGv_i64 tmp, set, clr;
992 tmp = tcg_temp_new_i64();
993 set = tcg_temp_new_i64();
994 clr = tcg_temp_new_i64();
996 get_avr64(tmp, vrt, true);
997 tcg_gen_mov_i64(set, tmp);
998 get_avr64(tmp, vrt, false);
999 tcg_gen_or_i64(clr, set, tmp);
1000 tcg_gen_and_i64(set, set, tmp);
1002 tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1003 tcg_gen_shli_i64(clr, clr, 1);
1005 tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
1006 tcg_gen_shli_i64(set, set, 3);
1008 tcg_gen_or_i64(tmp, set, clr);
1009 tcg_gen_extrl_i64_i32(cpu_crf[6], tmp);
1011 tcg_temp_free_i64(tmp);
1012 tcg_temp_free_i64(set);
1013 tcg_temp_free_i64(clr);
1014 }
1016 static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
1017 {
1018 REQUIRE_VECTOR(ctx);
1020 tcg_gen_gvec_cmp(cond, vece, avr_full_offset(a->vrt),
1021 avr_full_offset(a->vra), avr_full_offset(a->vrb), 16, 16);
1023 if (a->rc) {
1024 do_vcmp_rc(a->vrt);
1025 }
1027 return true;
1028 }
1030 TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
1031 TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
1032 TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
1033 TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1035 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
1036 TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
1037 TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
1038 TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1039 TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
1040 TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
1041 TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
1042 TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
1044 TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
1045 TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
1046 TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
1048 static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1049 {
1050 TCGv_vec t0, t1, zero;
1052 t0 = tcg_temp_new_vec_matching(t);
1053 t1 = tcg_temp_new_vec_matching(t);
1054 zero = tcg_constant_vec_matching(t, vece, 0);
1056 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
1057 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
1058 tcg_gen_cmp_vec(TCG_COND_NE, vece, t, a, b);
1060 tcg_gen_or_vec(vece, t, t, t0);
1061 tcg_gen_or_vec(vece, t, t, t1);
1063 tcg_temp_free_vec(t0);
1064 tcg_temp_free_vec(t1);
1065 }
1067 static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece)
1068 {
1069 static const TCGOpcode vecop_list[] = {
1070 INDEX_op_cmp_vec, 0
1071 };
1072 static const GVecGen3 ops[3] = {
1073 {
1074 .fniv = gen_vcmpnez_vec,
1075 .fno = gen_helper_VCMPNEZB,
1076 .opt_opc = vecop_list,
1077 .vece = MO_8
1078 },
1079 {
1080 .fniv = gen_vcmpnez_vec,
1081 .fno = gen_helper_VCMPNEZH,
1082 .opt_opc = vecop_list,
1083 .vece = MO_16
1084 },
1085 {
1086 .fniv = gen_vcmpnez_vec,
1087 .fno = gen_helper_VCMPNEZW,
1088 .opt_opc = vecop_list,
1089 .vece = MO_32
1090 }
1091 };
1093 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1094 REQUIRE_VECTOR(ctx);
1096 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
1097 avr_full_offset(a->vrb), 16, 16, &ops[vece]);
1099 if (a->rc) {
1100 do_vcmp_rc(a->vrt);
1101 }
1103 return true;
1104 }
1106 TRANS(VCMPNEZB, do_vcmpnez, MO_8)
1107 TRANS(VCMPNEZH, do_vcmpnez, MO_16)
1108 TRANS(VCMPNEZW, do_vcmpnez, MO_32)
1110 static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
1111 {
1112 TCGv_i64 t0, t1, t2;
1114 t0 = tcg_temp_new_i64();
1115 t1 = tcg_temp_new_i64();
1116 t2 = tcg_temp_new_i64();
1118 get_avr64(t0, a->vra, true);
1119 get_avr64(t1, a->vrb, true);
1120 tcg_gen_xor_i64(t2, t0, t1);
1122 get_avr64(t0, a->vra, false);
1123 get_avr64(t1, a->vrb, false);
1124 tcg_gen_xor_i64(t1, t0, t1);
1126 tcg_gen_or_i64(t1, t1, t2);
1127 tcg_gen_setcondi_i64(TCG_COND_EQ, t1, t1, 0);
1128 tcg_gen_neg_i64(t1, t1);
1130 set_avr64(a->vrt, t1, true);
1131 set_avr64(a->vrt, t1, false);
1133 if (a->rc) {
1134 tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
1135 tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
1136 tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
1137 }
1139 tcg_temp_free_i64(t0);
1140 tcg_temp_free_i64(t1);
1141 tcg_temp_free_i64(t2);
1143 return true;
1144 }
1146 GEN_VXRFORM(vcmpeqfp, 3, 3)
1147 GEN_VXRFORM(vcmpgefp, 3, 7)
1148 GEN_VXRFORM(vcmpgtfp, 3, 11)
1149 GEN_VXRFORM(vcmpbfp, 3, 15)
1151 static void gen_vsplti(DisasContext *ctx, int vece)
1152 {
1153 int simm;
1155 if (unlikely(!ctx->altivec_enabled)) {
1156 gen_exception(ctx, POWERPC_EXCP_VPU);
1157 return;
1158 }
1160 simm = SIMM5(ctx->opcode);
1161 tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
1162 }
1164 #define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
1165 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
1167 GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
1168 GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
1169 GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
1171 #define GEN_VXFORM_NOA(name, opc2, opc3) \
1172 static void glue(gen_, name)(DisasContext *ctx) \
1173 { \
1174 TCGv_ptr rb, rd; \
1175 if (unlikely(!ctx->altivec_enabled)) { \
1176 gen_exception(ctx, POWERPC_EXCP_VPU); \
1177 return; \
1178 } \
1179 rb = gen_avr_ptr(rB(ctx->opcode)); \
1180 rd = gen_avr_ptr(rD(ctx->opcode)); \
1181 gen_helper_##name(rd, rb); \
1182 tcg_temp_free_ptr(rb); \
1183 tcg_temp_free_ptr(rd); \
1184 }
1186 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
1187 static void glue(gen_, name)(DisasContext *ctx) \
1188 { \
1189 TCGv_ptr rb, rd; \
1190 \
1191 if (unlikely(!ctx->altivec_enabled)) { \
1192 gen_exception(ctx, POWERPC_EXCP_VPU); \
1193 return; \
1194 } \
1195 rb = gen_avr_ptr(rB(ctx->opcode)); \
1196 rd = gen_avr_ptr(rD(ctx->opcode)); \
1197 gen_helper_##name(cpu_env, rd, rb); \
1198 tcg_temp_free_ptr(rb); \
1199 tcg_temp_free_ptr(rd); \
1200 }
1202 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
1203 static void glue(gen_, name)(DisasContext *ctx) \
1204 { \
1205 TCGv_ptr rb, rd; \
1206 if (unlikely(!ctx->altivec_enabled)) { \
1207 gen_exception(ctx, POWERPC_EXCP_VPU); \
1208 return; \
1209 } \
1210 rb = gen_avr_ptr(rB(ctx->opcode)); \
1211 rd = gen_avr_ptr(rD(ctx->opcode)); \
1212 gen_helper_##name(rd, rb); \
1213 tcg_temp_free_ptr(rb); \
1214 tcg_temp_free_ptr(rd); \
1215 }
1217 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
1218 static void glue(gen_, name)(DisasContext *ctx) \
1219 { \
1220 TCGv_ptr rb; \
1221 if (unlikely(!ctx->altivec_enabled)) { \
1222 gen_exception(ctx, POWERPC_EXCP_VPU); \
1223 return; \
1224 } \
1225 rb = gen_avr_ptr(rB(ctx->opcode)); \
1226 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
1227 tcg_temp_free_ptr(rb); \
1228 }
1229 GEN_VXFORM_NOA(vupkhsb, 7, 8);
1230 GEN_VXFORM_NOA(vupkhsh, 7, 9);
1231 GEN_VXFORM_NOA(vupkhsw, 7, 25);
1232 GEN_VXFORM_NOA(vupklsb, 7, 10);
1233 GEN_VXFORM_NOA(vupklsh, 7, 11);
1234 GEN_VXFORM_NOA(vupklsw, 7, 27);
1235 GEN_VXFORM_NOA(vupkhpx, 7, 13);
1236 GEN_VXFORM_NOA(vupklpx, 7, 15);
1237 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
1238 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
1239 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
1240 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
1241 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
1242 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
1243 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
1244 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
1245 GEN_VXFORM_NOA(vprtybw, 1, 24);
1246 GEN_VXFORM_NOA(vprtybd, 1, 24);
1247 GEN_VXFORM_NOA(vprtybq, 1, 24);
1249 static void gen_vsplt(DisasContext *ctx, int vece)
1250 {
1251 int uimm, dofs, bofs;
1253 if (unlikely(!ctx->altivec_enabled)) {
1254 gen_exception(ctx, POWERPC_EXCP_VPU);
1255 return;
1256 }
1258 uimm = UIMM5(ctx->opcode);
1259 bofs = avr_full_offset(rB(ctx->opcode));
1260 dofs = avr_full_offset(rD(ctx->opcode));
1262 /* Experimental testing shows that hardware masks the immediate. */
1263 bofs += (uimm << vece) & 15;
1264 #ifndef HOST_WORDS_BIGENDIAN
1265 bofs ^= 15;
1266 bofs &= ~((1 << vece) - 1);
1267 #endif
1269 tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
1270 }
1272 #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
1273 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
1275 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
1276 static void glue(gen_, name)(DisasContext *ctx) \
1277 { \
1278 TCGv_ptr rb, rd; \
1279 TCGv_i32 uimm; \
1280 \
1281 if (unlikely(!ctx->altivec_enabled)) { \
1282 gen_exception(ctx, POWERPC_EXCP_VPU); \
1283 return; \
1284 } \
1285 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
1286 rb = gen_avr_ptr(rB(ctx->opcode)); \
1287 rd = gen_avr_ptr(rD(ctx->opcode)); \
1288 gen_helper_##name(cpu_env, rd, rb, uimm); \
1289 tcg_temp_free_i32(uimm); \
1290 tcg_temp_free_ptr(rb); \
1291 tcg_temp_free_ptr(rd); \
1292 }
1294 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
1295 static void glue(gen_, name)(DisasContext *ctx) \
1296 { \
1297 TCGv_ptr rb, rd; \
1298 uint8_t uimm = UIMM4(ctx->opcode); \
1299 TCGv_i32 t0; \
1300 if (unlikely(!ctx->altivec_enabled)) { \
1301 gen_exception(ctx, POWERPC_EXCP_VPU); \
1302 return; \
1303 } \
1304 if (uimm > splat_max) { \
1305 uimm = 0; \
1306 } \
1307 t0 = tcg_temp_new_i32(); \
1308 tcg_gen_movi_i32(t0, uimm); \
1309 rb = gen_avr_ptr(rB(ctx->opcode)); \
1310 rd = gen_avr_ptr(rD(ctx->opcode)); \
1311 gen_helper_##name(rd, rb, t0); \
1312 tcg_temp_free_i32(t0); \
1313 tcg_temp_free_ptr(rb); \
1314 tcg_temp_free_ptr(rd); \
1315 }
1317 GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
1318 GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
1319 GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
1320 GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
1321 GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
1322 GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
1323 GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
1324 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
1325 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
1326 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
1327 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
1328 GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
1329 vextractub, PPC_NONE, PPC2_ISA300);
1330 GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
1331 vextractuh, PPC_NONE, PPC2_ISA300);
1332 GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
1333 vextractuw, PPC_NONE, PPC2_ISA300);
1335 static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
1336 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
1337 {
1338 TCGv_ptr vrt, vra, vrb;
1339 TCGv rc;
1341 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1342 REQUIRE_VECTOR(ctx);
1344 vrt = gen_avr_ptr(a->vrt);
1345 vra = gen_avr_ptr(a->vra);
1346 vrb = gen_avr_ptr(a->vrb);
1347 rc = tcg_temp_new();
1349 tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
1350 if (right) {
1351 tcg_gen_subfi_tl(rc, 32 - size, rc);
1352 }
1353 gen_helper(cpu_env, vrt, vra, vrb, rc);
1355 tcg_temp_free_ptr(vrt);
1356 tcg_temp_free_ptr(vra);
1357 tcg_temp_free_ptr(vrb);
1358 tcg_temp_free(rc);
1359 return true;
1360 }
1362 TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
1363 TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
1364 TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
1365 TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
1367 TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
1368 TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
1369 TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
1370 TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
1372 static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1373 TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1374 {
1375 TCGv_ptr t;
1376 TCGv idx;
1378 t = gen_avr_ptr(vrt);
1379 idx = tcg_temp_new();
1381 tcg_gen_andi_tl(idx, ra, 0xF);
1382 if (right) {
1383 tcg_gen_subfi_tl(idx, 16 - size, idx);
1384 }
1386 gen_helper(cpu_env, t, rb, idx);
1388 tcg_temp_free_ptr(t);
1389 tcg_temp_free(idx);
1391 return true;
1392 }
1394 static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1395 int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1396 {
1397 bool ok;
1398 TCGv_i64 val;
1400 val = tcg_temp_new_i64();
1401 get_avr64(val, vrb, true);
1402 ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
1404 tcg_temp_free_i64(val);
1405 return ok;
1406 }
1408 static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1409 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1410 {
1411 bool ok;
1412 TCGv_i64 val;
1414 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1415 REQUIRE_VECTOR(ctx);
1417 val = tcg_temp_new_i64();
1418 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1420 ok = do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_helper);
1422 tcg_temp_free_i64(val);
1423 return ok;
1424 }
1426 static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1427 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1428 {
1429 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1430 REQUIRE_VECTOR(ctx);
1432 return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
1433 gen_helper);
1434 }
1436 static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1437 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1438 {
1439 bool ok;
1440 TCGv_i64 val;
1442 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1443 REQUIRE_VECTOR(ctx);
1445 if (a->uim > (16 - size)) {
1446 /*
1447 * PowerISA v3.1 says that the resulting value is undefined in this
1448 * case, so just log a guest error and leave VRT unchanged. The
1449 * real hardware would do a partial insert, e.g. if VRT is zeroed and
1450 * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
1451 * VRT = 0x0000...00001234, but we don't bother to reproduce this
1452 * behavior as software shouldn't rely on it.
1453 */
1454 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
1455 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1456 16 - size);
1457 return true;
1458 }
1460 val = tcg_temp_new_i64();
1461 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1463 ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
1464 gen_helper);
1466 tcg_temp_free_i64(val);
1467 return ok;
1468 }
1470 static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
1471 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1472 {
1473 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1474 REQUIRE_VECTOR(ctx);
1476 if (a->uim > (16 - size)) {
1477 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
1478 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
1479 16 - size);
1480 return true;
1481 }
1483 return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
1484 gen_helper);
1485 }
1487 TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
1488 TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
1489 TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
1490 TRANS(VINSDLX, do_vinsx_VX, 8, false, gen_helper_VINSDLX)
1492 TRANS(VINSBRX, do_vinsx_VX, 1, true, gen_helper_VINSBLX)
1493 TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
1494 TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
1495 TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
1497 TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
1498 TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
1500 TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
1501 TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
1502 TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
1504 TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
1505 TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
1506 TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
1508 TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
1509 TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
1510 TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
1511 TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
1513 static void gen_vsldoi(DisasContext *ctx)
1514 {
1515 TCGv_ptr ra, rb, rd;
1516 TCGv_i32 sh;
1517 if (unlikely(!ctx->altivec_enabled)) {
1518 gen_exception(ctx, POWERPC_EXCP_VPU);
1519 return;
1520 }
1521 ra = gen_avr_ptr(rA(ctx->opcode));
1522 rb = gen_avr_ptr(rB(ctx->opcode));
1523 rd = gen_avr_ptr(rD(ctx->opcode));
1524 sh = tcg_const_i32(VSH(ctx->opcode));
1525 gen_helper_vsldoi(rd, ra, rb, sh);
1526 tcg_temp_free_ptr(ra);
1527 tcg_temp_free_ptr(rb);
1528 tcg_temp_free_ptr(rd);
1529 tcg_temp_free_i32(sh);
1530 }
1532 static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
1533 {
1534 TCGv_i64 t0, t1, t2;
1536 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1537 REQUIRE_VECTOR(ctx);
1539 t0 = tcg_temp_new_i64();
1540 t1 = tcg_temp_new_i64();
1542 get_avr64(t0, a->vra, true);
1543 get_avr64(t1, a->vra, false);
1545 if (a->sh != 0) {
1546 t2 = tcg_temp_new_i64();
1548 get_avr64(t2, a->vrb, true);
1550 tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
1551 tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
1553 tcg_temp_free_i64(t2);
1554 }
1556 set_avr64(a->vrt, t0, true);
1557 set_avr64(a->vrt, t1, false);
1559 tcg_temp_free_i64(t0);
1560 tcg_temp_free_i64(t1);
1562 return true;
1563 }
1565 static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
1566 {
1567 TCGv_i64 t2, t1, t0;
1569 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1570 REQUIRE_VECTOR(ctx);
1572 t0 = tcg_temp_new_i64();
1573 t1 = tcg_temp_new_i64();
1575 get_avr64(t0, a->vrb, false);
1576 get_avr64(t1, a->vrb, true);
1578 if (a->sh != 0) {
1579 t2 = tcg_temp_new_i64();
1581 get_avr64(t2, a->vra, false);
1583 tcg_gen_extract2_i64(t0, t0, t1, a->sh);
1584 tcg_gen_extract2_i64(t1, t1, t2, a->sh);
1586 tcg_temp_free_i64(t2);
1587 }
1589 set_avr64(a->vrt, t0, false);
1590 set_avr64(a->vrt, t1, true);
1592 tcg_temp_free_i64(t0);
1593 tcg_temp_free_i64(t1);
1595 return true;
1596 }
1598 static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1599 {
1600 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1601 REQUIRE_VECTOR(ctx);
1603 tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
1604 (8 << vece) - 1, 16, 16);
1606 return true;
1607 }
1609 TRANS(VEXPANDBM, do_vexpand, MO_8)
1610 TRANS(VEXPANDHM, do_vexpand, MO_16)
1611 TRANS(VEXPANDWM, do_vexpand, MO_32)
1612 TRANS(VEXPANDDM, do_vexpand, MO_64)
1614 static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
1615 {
1616 TCGv_i64 tmp;
1618 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1619 REQUIRE_VECTOR(ctx);
1621 tmp = tcg_temp_new_i64();
1623 get_avr64(tmp, a->vrb, true);
1624 tcg_gen_sari_i64(tmp, tmp, 63);
1625 set_avr64(a->vrt, tmp, false);
1626 set_avr64(a->vrt, tmp, true);
1628 tcg_temp_free_i64(tmp);
1629 return true;
1630 }
1632 static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1633 {
1634 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
1635 mask = dup_const(vece, 1 << (elem_width - 1));
1636 uint64_t i, j;
1637 TCGv_i64 lo, hi, t0, t1;
1639 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1640 REQUIRE_VECTOR(ctx);
1642 hi = tcg_temp_new_i64();
1643 lo = tcg_temp_new_i64();
1644 t0 = tcg_temp_new_i64();
1645 t1 = tcg_temp_new_i64();
1647 get_avr64(lo, a->vrb, false);
1648 get_avr64(hi, a->vrb, true);
1650 tcg_gen_andi_i64(lo, lo, mask);
1651 tcg_gen_andi_i64(hi, hi, mask);
1653 /*
1654 * Gather the most significant bit of each element in the highest element
1655 * element. E.g. for bytes:
1656 * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
1657 * & dup(1 << (elem_width - 1))
1658 * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
1659 * << 32 - 4
1660 * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
1661 * |
1662 * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
1663 * << 16 - 2
1664 * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
1665 * |
1666 * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
1667 * << 8 - 1
1668 * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
1669 * |
1670 * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
1671 */
1672 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
1673 tcg_gen_shli_i64(t0, hi, j - i);
1674 tcg_gen_shli_i64(t1, lo, j - i);
1675 tcg_gen_or_i64(hi, hi, t0);
1676 tcg_gen_or_i64(lo, lo, t1);
1677 }
1679 tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
1680 tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
1681 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
1683 tcg_temp_free_i64(hi);
1684 tcg_temp_free_i64(lo);
1685 tcg_temp_free_i64(t0);
1686 tcg_temp_free_i64(t1);
1688 return true;
1689 }
1691 TRANS(VEXTRACTBM, do_vextractm, MO_8)
1692 TRANS(VEXTRACTHM, do_vextractm, MO_16)
1693 TRANS(VEXTRACTWM, do_vextractm, MO_32)
1694 TRANS(VEXTRACTDM, do_vextractm, MO_64)
1696 static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
1697 {
1698 TCGv_i64 tmp;
1700 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1701 REQUIRE_VECTOR(ctx);
1703 tmp = tcg_temp_new_i64();
1705 get_avr64(tmp, a->vrb, true);
1706 tcg_gen_shri_i64(tmp, tmp, 63);
1707 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
1709 tcg_temp_free_i64(tmp);
1711 return true;
1712 }
1714 static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
1715 {
1716 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece;
1717 uint64_t c;
1718 int i, j;
1719 TCGv_i64 hi, lo, t0, t1;
1721 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1722 REQUIRE_VECTOR(ctx);
1724 hi = tcg_temp_new_i64();
1725 lo = tcg_temp_new_i64();
1726 t0 = tcg_temp_new_i64();
1727 t1 = tcg_temp_new_i64();
1729 tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]);
1730 tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half);
1731 tcg_gen_extract_i64(lo, t0, 0, elem_count_half);
1733 /*
1734 * Spread the bits into their respective elements.
1735 * E.g. for bytes:
1736 * 00000000000000000000000000000000000000000000000000000000abcdefgh
1737 * << 32 - 4
1738 * 0000000000000000000000000000abcdefgh0000000000000000000000000000
1739 * |
1740 * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh
1741 * << 16 - 2
1742 * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000
1743 * |
1744 * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh
1745 * << 8 - 1
1746 * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000
1747 * |
1748 * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh
1749 * & dup(1)
1750 * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
1751 * * 0xff
1752 * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
1753 */
1754 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
1755 tcg_gen_shli_i64(t0, hi, j - i);
1756 tcg_gen_shli_i64(t1, lo, j - i);
1757 tcg_gen_or_i64(hi, hi, t0);
1758 tcg_gen_or_i64(lo, lo, t1);
1759 }
1761 c = dup_const(vece, 1);
1762 tcg_gen_andi_i64(hi, hi, c);
1763 tcg_gen_andi_i64(lo, lo, c);
1765 c = MAKE_64BIT_MASK(0, elem_width);
1766 tcg_gen_muli_i64(hi, hi, c);
1767 tcg_gen_muli_i64(lo, lo, c);
1769 set_avr64(a->vrt, lo, false);
1770 set_avr64(a->vrt, hi, true);
1772 tcg_temp_free_i64(hi);
1773 tcg_temp_free_i64(lo);
1774 tcg_temp_free_i64(t0);
1775 tcg_temp_free_i64(t1);
1777 return true;
1778 }
1780 TRANS(MTVSRBM, do_mtvsrm, MO_8)
1781 TRANS(MTVSRHM, do_mtvsrm, MO_16)
1782 TRANS(MTVSRWM, do_mtvsrm, MO_32)
1783 TRANS(MTVSRDM, do_mtvsrm, MO_64)
1785 static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a)
1786 {
1787 TCGv_i64 tmp;
1789 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1790 REQUIRE_VECTOR(ctx);
1792 tmp = tcg_temp_new_i64();
1794 tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]);
1795 tcg_gen_sextract_i64(tmp, tmp, 0, 1);
1796 set_avr64(a->vrt, tmp, false);
1797 set_avr64(a->vrt, tmp, true);
1799 tcg_temp_free_i64(tmp);
1801 return true;
1802 }
1804 static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
1805 {
1806 const uint64_t mask = dup_const(MO_8, 1);
1807 uint64_t hi, lo;
1809 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1810 REQUIRE_VECTOR(ctx);
1812 hi = extract16(a->b, 8, 8);
1813 lo = extract16(a->b, 0, 8);
1815 for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) {
1816 hi |= hi << (j - i);
1817 lo |= lo << (j - i);
1818 }
1820 hi = (hi & mask) * 0xFF;
1821 lo = (lo & mask) * 0xFF;
1823 set_avr64(a->vrt, tcg_constant_i64(hi), true);
1824 set_avr64(a->vrt, tcg_constant_i64(lo), false);
1826 return true;
1827 }
1829 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
1830 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
1831 { \
1832 TCGv_ptr ra, rb, rc, rd; \
1833 if (unlikely(!ctx->altivec_enabled)) { \
1834 gen_exception(ctx, POWERPC_EXCP_VPU); \
1835 return; \
1836 } \
1837 ra = gen_avr_ptr(rA(ctx->opcode)); \
1838 rb = gen_avr_ptr(rB(ctx->opcode)); \
1839 rc = gen_avr_ptr(rC(ctx->opcode)); \
1840 rd = gen_avr_ptr(rD(ctx->opcode)); \
1841 if (Rc(ctx->opcode)) { \
1842 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
1843 } else { \
1844 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
1845 } \
1846 tcg_temp_free_ptr(ra); \
1847 tcg_temp_free_ptr(rb); \
1848 tcg_temp_free_ptr(rc); \
1849 tcg_temp_free_ptr(rd); \
1850 }
1852 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
1854 static void gen_vmladduhm(DisasContext *ctx)
1855 {
1856 TCGv_ptr ra, rb, rc, rd;
1857 if (unlikely(!ctx->altivec_enabled)) {
1858 gen_exception(ctx, POWERPC_EXCP_VPU);
1859 return;
1860 }
1861 ra = gen_avr_ptr(rA(ctx->opcode));
1862 rb = gen_avr_ptr(rB(ctx->opcode));
1863 rc = gen_avr_ptr(rC(ctx->opcode));
1864 rd = gen_avr_ptr(rD(ctx->opcode));
1865 gen_helper_vmladduhm(rd, ra, rb, rc);
1866 tcg_temp_free_ptr(ra);
1867 tcg_temp_free_ptr(rb);
1868 tcg_temp_free_ptr(rc);
1869 tcg_temp_free_ptr(rd);
1870 }
1872 static void gen_vpermr(DisasContext *ctx)
1873 {
1874 TCGv_ptr ra, rb, rc, rd;
1875 if (unlikely(!ctx->altivec_enabled)) {
1876 gen_exception(ctx, POWERPC_EXCP_VPU);
1877 return;
1878 }
1879 ra = gen_avr_ptr(rA(ctx->opcode));
1880 rb = gen_avr_ptr(rB(ctx->opcode));
1881 rc = gen_avr_ptr(rC(ctx->opcode));
1882 rd = gen_avr_ptr(rD(ctx->opcode));
1883 gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
1884 tcg_temp_free_ptr(ra);
1885 tcg_temp_free_ptr(rb);
1886 tcg_temp_free_ptr(rc);
1887 tcg_temp_free_ptr(rd);
1888 }
1890 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
1891 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
1892 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
1893 GEN_VAFORM_PAIRED(vsel, vperm, 21)
1894 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
1896 GEN_VXFORM_NOA(vclzb, 1, 28)
1897 GEN_VXFORM_NOA(vclzh, 1, 29)
1898 GEN_VXFORM_TRANS(vclzw, 1, 30)
1899 GEN_VXFORM_TRANS(vclzd, 1, 31)
1900 GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
1901 GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
1903 static void gen_vexts_i64(TCGv_i64 t, TCGv_i64 b, int64_t s)
1904 {
1905 tcg_gen_sextract_i64(t, b, 0, 64 - s);
1906 }
1908 static void gen_vexts_i32(TCGv_i32 t, TCGv_i32 b, int32_t s)
1909 {
1910 tcg_gen_sextract_i32(t, b, 0, 32 - s);
1911 }
1913 static void gen_vexts_vec(unsigned vece, TCGv_vec t, TCGv_vec b, int64_t s)
1914 {
1915 tcg_gen_shli_vec(vece, t, b, s);
1916 tcg_gen_sari_vec(vece, t, t, s);
1917 }
1919 static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, unsigned vece, int64_t s)
1920 {
1921 static const TCGOpcode vecop_list[] = {
1922 INDEX_op_shli_vec, INDEX_op_sari_vec, 0
1923 };
1925 static const GVecGen2i op[2] = {
1926 {
1927 .fni4 = gen_vexts_i32,
1928 .fniv = gen_vexts_vec,
1929 .opt_opc = vecop_list,
1930 .vece = MO_32
1931 },
1932 {
1933 .fni8 = gen_vexts_i64,
1934 .fniv = gen_vexts_vec,
1935 .opt_opc = vecop_list,
1936 .vece = MO_64
1937 },
1938 };
1940 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1941 REQUIRE_VECTOR(ctx);
1943 tcg_gen_gvec_2i(avr_full_offset(a->vrt), avr_full_offset(a->vrb),
1944 16, 16, s, &op[vece - MO_32]);
1946 return true;
1947 }
1949 TRANS(VEXTSB2W, do_vexts, MO_32, 24);
1950 TRANS(VEXTSH2W, do_vexts, MO_32, 16);
1951 TRANS(VEXTSB2D, do_vexts, MO_64, 56);
1952 TRANS(VEXTSH2D, do_vexts, MO_64, 48);
1953 TRANS(VEXTSW2D, do_vexts, MO_64, 32);
1955 static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
1956 {
1957 TCGv_i64 tmp;
1959 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1960 REQUIRE_VECTOR(ctx);
1962 tmp = tcg_temp_new_i64();
1964 get_avr64(tmp, a->vrb, false);
1965 set_avr64(a->vrt, tmp, false);
1966 tcg_gen_sari_i64(tmp, tmp, 63);
1967 set_avr64(a->vrt, tmp, true);
1969 tcg_temp_free_i64(tmp);
1970 return true;
1971 }
1973 GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
1974 GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
1975 GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
1976 GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
1977 GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
1978 GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
1979 GEN_VXFORM_NOA(vpopcntb, 1, 28)
1980 GEN_VXFORM_NOA(vpopcnth, 1, 29)
1981 GEN_VXFORM_NOA(vpopcntw, 1, 30)
1982 GEN_VXFORM_NOA(vpopcntd, 1, 31)
1983 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
1984 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
1985 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
1986 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
1987 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
1988 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
1989 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
1990 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
1991 GEN_VXFORM(vbpermd, 6, 23);
1992 GEN_VXFORM(vbpermq, 6, 21);
1993 GEN_VXFORM_TRANS(vgbbd, 6, 20);
1994 GEN_VXFORM(vpmsumb, 4, 16)
1995 GEN_VXFORM(vpmsumh, 4, 17)
1996 GEN_VXFORM(vpmsumw, 4, 18)
1997 GEN_VXFORM(vpmsumd, 4, 19)
1999 #define GEN_BCD(op) \
2000 static void gen_##op(DisasContext *ctx) \
2001 { \
2002 TCGv_ptr ra, rb, rd; \
2003 TCGv_i32 ps; \
2004 \
2005 if (unlikely(!ctx->altivec_enabled)) { \
2006 gen_exception(ctx, POWERPC_EXCP_VPU); \
2007 return; \
2008 } \
2009 \
2010 ra = gen_avr_ptr(rA(ctx->opcode)); \
2011 rb = gen_avr_ptr(rB(ctx->opcode)); \
2012 rd = gen_avr_ptr(rD(ctx->opcode)); \
2013 \
2014 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2015 \
2016 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
2017 \
2018 tcg_temp_free_ptr(ra); \
2019 tcg_temp_free_ptr(rb); \
2020 tcg_temp_free_ptr(rd); \
2021 tcg_temp_free_i32(ps); \
2022 }
2024 #define GEN_BCD2(op) \
2025 static void gen_##op(DisasContext *ctx) \
2026 { \
2027 TCGv_ptr rd, rb; \
2028 TCGv_i32 ps; \
2029 \
2030 if (unlikely(!ctx->altivec_enabled)) { \
2031 gen_exception(ctx, POWERPC_EXCP_VPU); \
2032 return; \
2033 } \
2034 \
2035 rb = gen_avr_ptr(rB(ctx->opcode)); \
2036 rd = gen_avr_ptr(rD(ctx->opcode)); \
2037 \
2038 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2039 \
2040 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
2041 \
2042 tcg_temp_free_ptr(rb); \
2043 tcg_temp_free_ptr(rd); \
2044 tcg_temp_free_i32(ps); \
2045 }
2047 GEN_BCD(bcdadd)
2048 GEN_BCD(bcdsub)
2049 GEN_BCD2(bcdcfn)
2050 GEN_BCD2(bcdctn)
2051 GEN_BCD2(bcdcfz)
2052 GEN_BCD2(bcdctz)
2053 GEN_BCD2(bcdcfsq)
2054 GEN_BCD2(bcdctsq)
2055 GEN_BCD2(bcdsetsgn)
2056 GEN_BCD(bcdcpsgn);
2057 GEN_BCD(bcds);
2058 GEN_BCD(bcdus);
2059 GEN_BCD(bcdsr);
2060 GEN_BCD(bcdtrunc);
2061 GEN_BCD(bcdutrunc);
2063 static void gen_xpnd04_1(DisasContext *ctx)
2064 {
2065 switch (opc4(ctx->opcode)) {
2066 case 0:
2067 gen_bcdctsq(ctx);
2068 break;
2069 case 2:
2070 gen_bcdcfsq(ctx);
2071 break;
2072 case 4:
2073 gen_bcdctz(ctx);
2074 break;
2075 case 5:
2076 gen_bcdctn(ctx);
2077 break;
2078 case 6:
2079 gen_bcdcfz(ctx);
2080 break;
2081 case 7:
2082 gen_bcdcfn(ctx);
2083 break;
2084 case 31:
2085 gen_bcdsetsgn(ctx);
2086 break;
2087 default:
2088 gen_invalid(ctx);
2089 break;
2090 }
2091 }
2093 static void gen_xpnd04_2(DisasContext *ctx)
2094 {
2095 switch (opc4(ctx->opcode)) {
2096 case 0:
2097 gen_bcdctsq(ctx);
2098 break;
2099 case 2:
2100 gen_bcdcfsq(ctx);
2101 break;
2102 case 4:
2103 gen_bcdctz(ctx);
2104 break;
2105 case 6:
2106 gen_bcdcfz(ctx);
2107 break;
2108 case 7:
2109 gen_bcdcfn(ctx);
2110 break;
2111 case 31:
2112 gen_bcdsetsgn(ctx);
2113 break;
2114 default:
2115 gen_invalid(ctx);
2116 break;
2117 }
2118 }
2121 GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
2122 xpnd04_1, PPC_NONE, PPC2_ISA300)
2123 GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
2124 xpnd04_2, PPC_NONE, PPC2_ISA300)
2126 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
2127 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2128 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
2129 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2130 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
2131 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2132 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
2133 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2134 GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
2135 bcdcpsgn, PPC_NONE, PPC2_ISA300)
2136 GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
2137 bcds, PPC_NONE, PPC2_ISA300)
2138 GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
2139 bcdus, PPC_NONE, PPC2_ISA300)
2140 GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
2141 bcdtrunc, PPC_NONE, PPC2_ISA300)
2142 GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
2143 bcdtrunc, PPC_NONE, PPC2_ISA300)
2144 GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
2145 bcdutrunc, PPC_NONE, PPC2_ISA300)
2148 static void gen_vsbox(DisasContext *ctx)
2149 {
2150 TCGv_ptr ra, rd;
2151 if (unlikely(!ctx->altivec_enabled)) {
2152 gen_exception(ctx, POWERPC_EXCP_VPU);
2153 return;
2154 }
2155 ra = gen_avr_ptr(rA(ctx->opcode));
2156 rd = gen_avr_ptr(rD(ctx->opcode));
2157 gen_helper_vsbox(rd, ra);
2158 tcg_temp_free_ptr(ra);
2159 tcg_temp_free_ptr(rd);
2160 }
2162 GEN_VXFORM(vcipher, 4, 20)
2163 GEN_VXFORM(vcipherlast, 4, 20)
2164 GEN_VXFORM(vncipher, 4, 21)
2165 GEN_VXFORM(vncipherlast, 4, 21)
2167 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
2168 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2169 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
2170 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2172 #define VSHASIGMA(op) \
2173 static void gen_##op(DisasContext *ctx) \
2174 { \
2175 TCGv_ptr ra, rd; \
2176 TCGv_i32 st_six; \
2177 if (unlikely(!ctx->altivec_enabled)) { \
2178 gen_exception(ctx, POWERPC_EXCP_VPU); \
2179 return; \
2180 } \
2181 ra = gen_avr_ptr(rA(ctx->opcode)); \
2182 rd = gen_avr_ptr(rD(ctx->opcode)); \
2183 st_six = tcg_const_i32(rB(ctx->opcode)); \
2184 gen_helper_##op(rd, ra, st_six); \
2185 tcg_temp_free_ptr(ra); \
2186 tcg_temp_free_ptr(rd); \
2187 tcg_temp_free_i32(st_six); \
2188 }
2190 VSHASIGMA(vshasigmaw)
2191 VSHASIGMA(vshasigmad)
2193 GEN_VXFORM3(vpermxor, 22, 0xFF)
2194 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
2195 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
2197 static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
2198 {
2199 static const GVecGen3 g = {
2200 .fni8 = gen_helper_CFUGED,
2201 .vece = MO_64,
2202 };
2204 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2205 REQUIRE_VECTOR(ctx);
2207 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2208 avr_full_offset(a->vrb), 16, 16, &g);
2210 return true;
2211 }
2213 static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
2214 {
2215 static const GVecGen3i g = {
2216 .fni8 = do_cntzdm,
2217 .vece = MO_64,
2218 };
2220 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2221 REQUIRE_VECTOR(ctx);
2223 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2224 avr_full_offset(a->vrb), 16, 16, false, &g);
2226 return true;
2227 }
2229 static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
2230 {
2231 static const GVecGen3i g = {
2232 .fni8 = do_cntzdm,
2233 .vece = MO_64,
2234 };
2236 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2237 REQUIRE_VECTOR(ctx);
2239 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2240 avr_full_offset(a->vrb), 16, 16, true, &g);
2242 return true;
2243 }
2245 static bool trans_VPDEPD(DisasContext *ctx, arg_VX *a)
2246 {
2247 static const GVecGen3 g = {
2248 .fni8 = gen_helper_PDEPD,
2249 .vece = MO_64,
2250 };
2252 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2253 REQUIRE_VECTOR(ctx);
2255 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2256 avr_full_offset(a->vrb), 16, 16, &g);
2258 return true;
2259 }
2261 static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
2262 {
2263 static const GVecGen3 g = {
2264 .fni8 = gen_helper_PEXTD,
2265 .vece = MO_64,
2266 };
2268 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2269 REQUIRE_VECTOR(ctx);
2271 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2272 avr_full_offset(a->vrb), 16, 16, &g);
2274 return true;
2275 }
2277 static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA *a)
2278 {
2279 TCGv_i64 rl, rh, src1, src2;
2280 int dw;
2282 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2283 REQUIRE_VECTOR(ctx);
2285 rh = tcg_temp_new_i64();
2286 rl = tcg_temp_new_i64();
2287 src1 = tcg_temp_new_i64();
2288 src2 = tcg_temp_new_i64();
2290 get_avr64(rl, a->rc, false);
2291 get_avr64(rh, a->rc, true);
2293 for (dw = 0; dw < 2; dw++) {
2294 get_avr64(src1, a->vra, dw);
2295 get_avr64(src2, a->vrb, dw);
2296 tcg_gen_mulu2_i64(src1, src2, src1, src2);
2297 tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
2298 }
2300 set_avr64(a->vrt, rl, false);
2301 set_avr64(a->vrt, rh, true);
2303 tcg_temp_free_i64(rl);
2304 tcg_temp_free_i64(rh);
2305 tcg_temp_free_i64(src1);
2306 tcg_temp_free_i64(src2);
2308 return true;
2309 }
2311 static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
2312 {
2313 TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
2315 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2316 REQUIRE_VECTOR(ctx);
2318 tmp0 = tcg_temp_new_i64();
2319 tmp1 = tcg_temp_new_i64();
2320 prod1h = tcg_temp_new_i64();
2321 prod1l = tcg_temp_new_i64();
2322 prod0h = tcg_temp_new_i64();
2323 prod0l = tcg_temp_new_i64();
2324 zero = tcg_constant_i64(0);
2326 /* prod1 = vsr[vra+32].dw[1] * vsr[vrb+32].dw[1] */
2327 get_avr64(tmp0, a->vra, false);
2328 get_avr64(tmp1, a->vrb, false);
2329 tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
2331 /* prod0 = vsr[vra+32].dw[0] * vsr[vrb+32].dw[0] */
2332 get_avr64(tmp0, a->vra, true);
2333 get_avr64(tmp1, a->vrb, true);
2334 tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
2336 /* Sum lower 64-bits elements */
2337 get_avr64(tmp1, a->rc, false);
2338 tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
2339 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
2341 /*
2342 * Discard lower 64-bits, leaving the carry into bit 64.
2343 * Then sum the higher 64-bit elements.
2344 */
2345 get_avr64(tmp1, a->rc, true);
2346 tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero);
2347 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero);
2348 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0h, zero);
2350 /* Discard 64 more bits to complete the CHOP128(temp >> 128) */
2351 set_avr64(a->vrt, tmp0, false);
2352 set_avr64(a->vrt, zero, true);
2354 tcg_temp_free_i64(tmp0);
2355 tcg_temp_free_i64(tmp1);
2356 tcg_temp_free_i64(prod1h);
2357 tcg_temp_free_i64(prod1l);
2358 tcg_temp_free_i64(prod0h);
2359 tcg_temp_free_i64(prod0l);
2361 return true;
2362 }
2364 static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
2365 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
2366 {
2367 TCGv_ptr ra, rb, rd;
2368 REQUIRE_VECTOR(ctx);
2370 ra = gen_avr_ptr(a->vra);
2371 rb = gen_avr_ptr(a->vrb);
2372 rd = gen_avr_ptr(a->vrt);
2373 gen_helper(rd, ra, rb);
2374 tcg_temp_free_ptr(ra);
2375 tcg_temp_free_ptr(rb);
2376 tcg_temp_free_ptr(rd);
2378 return true;
2379 }
2381 static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
2382 void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
2383 {
2384 TCGv_i64 vra, vrb, vrt0, vrt1;
2385 REQUIRE_VECTOR(ctx);
2387 vra = tcg_temp_new_i64();
2388 vrb = tcg_temp_new_i64();
2389 vrt0 = tcg_temp_new_i64();
2390 vrt1 = tcg_temp_new_i64();
2392 get_avr64(vra, a->vra, even);
2393 get_avr64(vrb, a->vrb, even);
2394 gen_mul(vrt0, vrt1, vra, vrb);
2395 set_avr64(a->vrt, vrt0, false);
2396 set_avr64(a->vrt, vrt1, true);
2398 tcg_temp_free_i64(vra);
2399 tcg_temp_free_i64(vrb);
2400 tcg_temp_free_i64(vrt0);
2401 tcg_temp_free_i64(vrt1);
2403 return true;
2404 }
2406 static bool trans_VMULLD(DisasContext *ctx, arg_VX *a)
2407 {
2408 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2409 REQUIRE_VECTOR(ctx);
2411 tcg_gen_gvec_mul(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->vra),
2412 avr_full_offset(a->vrb), 16, 16);
2414 return true;
2415 }
2417 TRANS_FLAGS2(ALTIVEC_207, VMULESB, do_vx_helper, gen_helper_VMULESB)
2418 TRANS_FLAGS2(ALTIVEC_207, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
2419 TRANS_FLAGS2(ALTIVEC_207, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
2420 TRANS_FLAGS2(ALTIVEC_207, VMULOUB, do_vx_helper, gen_helper_VMULOUB)
2421 TRANS_FLAGS2(ALTIVEC_207, VMULESH, do_vx_helper, gen_helper_VMULESH)
2422 TRANS_FLAGS2(ALTIVEC_207, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
2423 TRANS_FLAGS2(ALTIVEC_207, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
2424 TRANS_FLAGS2(ALTIVEC_207, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
2425 TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
2426 TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
2427 TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
2428 TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
2429 TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
2430 TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
2431 TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
2432 TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
2434 static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2435 {
2436 TCGv_i64 hh, lh, temp;
2438 uint64_t c;
2439 hh = tcg_temp_new_i64();
2440 lh = tcg_temp_new_i64();
2441 temp = tcg_temp_new_i64();
2443 c = 0xFFFFFFFF;
2445 if (sign) {
2446 tcg_gen_ext32s_i64(lh, a);
2447 tcg_gen_ext32s_i64(temp, b);
2448 } else {
2449 tcg_gen_andi_i64(lh, a, c);
2450 tcg_gen_andi_i64(temp, b, c);
2451 }
2452 tcg_gen_mul_i64(lh, lh, temp);
2454 if (sign) {
2455 tcg_gen_sari_i64(hh, a, 32);
2456 tcg_gen_sari_i64(temp, b, 32);
2457 } else {
2458 tcg_gen_shri_i64(hh, a, 32);
2459 tcg_gen_shri_i64(temp, b, 32);
2460 }
2461 tcg_gen_mul_i64(hh, hh, temp);
2463 tcg_gen_shri_i64(lh, lh, 32);
2464 tcg_gen_andi_i64(hh, hh, c << 32);
2465 tcg_gen_or_i64(t, hh, lh);
2467 tcg_temp_free_i64(hh);
2468 tcg_temp_free_i64(lh);
2469 tcg_temp_free_i64(temp);
2470 }
2472 static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
2473 {
2474 TCGv_i64 tlow;
2476 tlow = tcg_temp_new_i64();
2477 if (sign) {
2478 tcg_gen_muls2_i64(tlow, t, a, b);
2479 } else {
2480 tcg_gen_mulu2_i64(tlow, t, a, b);
2481 }
2483 tcg_temp_free_i64(tlow);
2484 }
2486 static bool do_vx_mulh(DisasContext *ctx, arg_VX *a, bool sign,
2487 void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, bool))
2488 {
2489 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2490 REQUIRE_VECTOR(ctx);
2492 TCGv_i64 vra, vrb, vrt;
2493 int i;
2495 vra = tcg_temp_new_i64();
2496 vrb = tcg_temp_new_i64();
2497 vrt = tcg_temp_new_i64();
2499 for (i = 0; i < 2; i++) {
2500 get_avr64(vra, a->vra, i);
2501 get_avr64(vrb, a->vrb, i);
2502 get_avr64(vrt, a->vrt, i);
2504 func(vrt, vra, vrb, sign);
2506 set_avr64(a->vrt, vrt, i);
2507 }
2509 tcg_temp_free_i64(vra);
2510 tcg_temp_free_i64(vrb);
2511 tcg_temp_free_i64(vrt);
2513 return true;
2515 }
2517 TRANS(VMULHSW, do_vx_mulh, true , do_vx_vmulhw_i64)
2518 TRANS(VMULHSD, do_vx_mulh, true , do_vx_vmulhd_i64)
2519 TRANS(VMULHUW, do_vx_mulh, false, do_vx_vmulhw_i64)
2520 TRANS(VMULHUD, do_vx_mulh, false, do_vx_vmulhd_i64)
2522 #undef GEN_VR_LDX
2523 #undef GEN_VR_STX
2524 #undef GEN_VR_LVE
2525 #undef GEN_VR_STVE
2527 #undef GEN_VX_LOGICAL
2528 #undef GEN_VX_LOGICAL_207
2529 #undef GEN_VXFORM
2530 #undef GEN_VXFORM_207
2531 #undef GEN_VXFORM_DUAL
2532 #undef GEN_VXRFORM_DUAL
2533 #undef GEN_VXRFORM1
2534 #undef GEN_VXRFORM
2535 #undef GEN_VXFORM_VSPLTI
2536 #undef GEN_VXFORM_NOA
2537 #undef GEN_VXFORM_UIMM
2538 #undef GEN_VAFORM_PAIRED
2540 #undef GEN_BCD2