disas/nanomips.cpp

   1 /*
   2  *  Source file for nanoMIPS disassembler component of QEMU
   3  *
   4  *  Copyright (C) 2018  Wave Computing, Inc.
   5  *  Copyright (C) 2018  Matthew Fortune <matthew.fortune@mips.com>
   6  *  Copyright (C) 2018  Aleksandar Markovic <amarkovic@wavecomp.com>
   7  *
   8  *  This program is free software: you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation, either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
  20  *
  21  */
  22
  23 /*
  24  *  Documentation used while implementing this component:
  25  *
  26  *  [1] "MIPS® Architecture Base: nanoMIPS32(tm) Instruction Set Technical
  27  *      Reference Manual", Revision 01.01, April 27, 2018
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "disas/dis-asm.h"
  32
  33 #include <cstring>
  34 #include <stdexcept>
  35 #include <sstream>
  36 #include <stdio.h>
  37 #include <stdarg.h>
  38
  39 #include "nanomips.h"
  40
  41 #define IMGASSERTONCE(test)
  42
  43
  44 int nanomips_dis(char *buf,
  45                  unsigned address,
  46                  unsigned short one,
  47                  unsigned short two,
  48                  unsigned short three)
  49 {
  50     std::string disasm;
  51     uint16 bits[3] = {one, two, three};
  52
  53     NMD::TABLE_ENTRY_TYPE type;
  54     NMD d(address, NMD::ALL_ATTRIBUTES);
  55     int size = d.Disassemble(bits, disasm, type);
  56
  57     strcpy(buf, disasm.c_str());
  58     return size;
  59 }
  60
  61 int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info)
  62 {
  63     int status;
  64     bfd_byte buffer[2];
  65     uint16_t insn1 = 0, insn2 = 0, insn3 = 0;
  66     char buf[200];
  67
  68     info->bytes_per_chunk = 2;
  69     info->display_endian = info->endian;
  70     info->insn_info_valid = 1;
  71     info->branch_delay_insns = 0;
  72     info->data_size = 0;
  73     info->insn_type = dis_nonbranch;
  74     info->target = 0;
  75     info->target2 = 0;
  76
  77     status = (*info->read_memory_func)(memaddr, buffer, 2, info);
  78     if (status != 0) {
  79         (*info->memory_error_func)(status, memaddr, info);
  80         return -1;
  81     }
  82
  83     if (info->endian == BFD_ENDIAN_BIG) {
  84         insn1 = bfd_getb16(buffer);
  85     } else {
  86         insn1 = bfd_getl16(buffer);
  87     }
  88     (*info->fprintf_func)(info->stream, "%04x ", insn1);
  89
  90     /* Handle 32-bit opcodes.  */
  91     if ((insn1 & 0x1000) == 0) {
  92         status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info);
  93         if (status != 0) {
  94             (*info->memory_error_func)(status, memaddr + 2, info);
  95             return -1;
  96         }
  97
  98         if (info->endian == BFD_ENDIAN_BIG) {
  99             insn2 = bfd_getb16(buffer);
 100         } else {
 101             insn2 = bfd_getl16(buffer);
 102         }
 103         (*info->fprintf_func)(info->stream, "%04x ", insn2);
 104     } else {
 105         (*info->fprintf_func)(info->stream, "     ");
 106     }
 107     /* Handle 48-bit opcodes.  */
 108     if ((insn1 >> 10) == 0x18) {
 109         status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info);
 110         if (status != 0) {
 111             (*info->memory_error_func)(status, memaddr + 4, info);
 112             return -1;
 113         }
 114
 115         if (info->endian == BFD_ENDIAN_BIG) {
 116             insn3 = bfd_getb16(buffer);
 117         } else {
 118             insn3 = bfd_getl16(buffer);
 119         }
 120         (*info->fprintf_func)(info->stream, "%04x ", insn3);
 121     } else {
 122         (*info->fprintf_func)(info->stream, "     ");
 123     }
 124
 125     int length = nanomips_dis(buf, memaddr, insn1, insn2, insn3);
 126
 127     /* FIXME: Should probably use a hash table on the major opcode here.  */
 128
 129     (*info->fprintf_func) (info->stream, "%s", buf);
 130     if (length > 0) {
 131         return length / 8;
 132     }
 133
 134     info->insn_type = dis_noninsn;
 135
 136     return insn3 ? 6 : insn2 ? 4 : 2;
 137 }
 138
 139
 140 namespace img
 141 {
 142     address addr32(address a)
 143     {
 144         return a;
 145     }
 146
 147     std::string format(const char *format, ...)
 148     {
 149         char buffer[256];
 150         va_list args;
 151         va_start(args, format);
 152         int err = vsprintf(buffer, format, args);
 153         if (err < 0) {
 154             perror(buffer);
 155         }
 156         va_end(args);
 157         return buffer;
 158     }
 159
 160     std::string format(const char *format,
 161                        std::string s)
 162     {
 163         char buffer[256];
 164
 165         sprintf(buffer, format, s.c_str());
 166
 167         return buffer;
 168     }
 169
 170     std::string format(const char *format,
 171                        std::string s1,
 172                        std::string s2)
 173     {
 174         char buffer[256];
 175
 176         sprintf(buffer, format, s1.c_str(), s2.c_str());
 177
 178         return buffer;
 179     }
 180
 181     std::string format(const char *format,
 182                        std::string s1,
 183                        std::string s2,
 184                        std::string s3)
 185     {
 186         char buffer[256];
 187
 188         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str());
 189
 190         return buffer;
 191     }
 192
 193     std::string format(const char *format,
 194                        std::string s1,
 195                        std::string s2,
 196                        std::string s3,
 197                        std::string s4)
 198     {
 199         char buffer[256];
 200
 201         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),
 202                                 s4.c_str());
 203
 204         return buffer;
 205     }
 206
 207     std::string format(const char *format,
 208                        std::string s1,
 209                        std::string s2,
 210                        std::string s3,
 211                        std::string s4,
 212                        std::string s5)
 213     {
 214         char buffer[256];
 215
 216         sprintf(buffer, format, s1.c_str(), s2.c_str(), s3.c_str(),
 217                                 s4.c_str(), s5.c_str());
 218
 219         return buffer;
 220     }
 221
 222     std::string format(const char *format,
 223                        uint64 d,
 224                        std::string s2)
 225     {
 226         char buffer[256];
 227
 228         sprintf(buffer, format, d, s2.c_str());
 229
 230         return buffer;
 231     }
 232
 233     std::string format(const char *format,
 234                        std::string s1,
 235                        uint64 d,
 236                        std::string s2)
 237     {
 238         char buffer[256];
 239
 240         sprintf(buffer, format, s1.c_str(), d, s2.c_str());
 241
 242         return buffer;
 243     }
 244
 245     std::string format(const char *format,
 246                        std::string s1,
 247                        std::string s2,
 248                        uint64 d)
 249     {
 250         char buffer[256];
 251
 252         sprintf(buffer, format, s1.c_str(), s2.c_str(), d);
 253
 254         return buffer;
 255     }
 256
 257     char as_char(int c)
 258     {
 259         return static_cast<char>(c);
 260     }
 261 };
 262
 263
 264 std::string to_string(img::address a)
 265 {
 266     char buffer[256];
 267     sprintf(buffer, "0x%" PRIx64, a);
 268     return buffer;
 269 }
 270
 271
 272 uint64 extract_bits(uint64 data, uint32 bit_offset, uint32 bit_size)
 273 {
 274     return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size);
 275 }
 276
 277
 278 int64 sign_extend(int64 data, int msb)
 279 {
 280     uint64 shift = 63 - msb;
 281     return (data << shift) >> shift;
 282 }
 283
 284
 285 uint64 NMD::renumber_registers(uint64 index, uint64 *register_list,
 286                                size_t register_list_size)
 287 {
 288     if (index < register_list_size) {
 289         return register_list[index];
 290     }
 291
 292     throw std::runtime_error(img::format(
 293                    "Invalid register mapping index %" PRIu64
 294                    ", size of list = %zu",
 295                    index, register_list_size));
 296 }
 297
 298
 299 /*
 300  * NMD::decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type
 301  *
 302  *   Map a 4-bit code to the 5-bit register space according to this pattern:
 303  *
 304  *                              1                   0
 305  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 306  *                    | | | | | | | | | | | | | | | |
 307  *                    | | | | | | | | | | | | | | | |
 308  *                    | | | | | | | | | | | └---------------┐
 309  *                    | | | | | | | | | | └---------------┐ |
 310  *                    | | | | | | | | | └---------------┐ | |
 311  *                    | | | | | | | | └---------------┐ | | |
 312  *                    | | | | | | | |         | | | | | | | |
 313  *                    | | | | | | | |         | | | | | | | |
 314  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 315  *      3                   2                   1                   0
 316  *
 317  *   Used in handling following instructions:
 318  *
 319  *     - ADDU[4X4]
 320  *     - LW[4X4]
 321  *     - MOVEP[REV]
 322  *     - MUL[4X4]
 323  *     - SW[4X4]
 324  */
 325 uint64 NMD::decode_gpr_gpr4(uint64 d)
 326 {
 327     static uint64 register_list[] = {  8,  9, 10, 11,  4,  5,  6,  7,
 328                                       16, 17, 18, 19, 20, 21, 22, 23 };
 329     return renumber_registers(d, register_list,
 330                sizeof(register_list) / sizeof(register_list[0]));
 331 }
 332
 333
 334 /*
 335  * NMD::decode_gpr_gpr4_zero() - decoder for 'gpr4.zero' gpr encoding type
 336  *
 337  *   Map a 4-bit code to the 5-bit register space according to this pattern:
 338  *
 339  *                              1                   0
 340  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 341  *                    | | | | | | | | | | | | | | | |
 342  *                    | | | | | | | | | | | | └---------------------┐
 343  *                    | | | | | | | | | | | └---------------┐       |
 344  *                    | | | | | | | | | | └---------------┐ |       |
 345  *                    | | | | | | | | | └---------------┐ | |       |
 346  *                    | | | | | | | | └---------------┐ | | |       |
 347  *                    | | | | | | | |           | | | | | | |       |
 348  *                    | | | | | | | |           | | | | | | |       |
 349  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 350  *      3                   2                   1                   0
 351  *
 352  *   This pattern is the same one used for 'gpr4' gpr encoding type, except for
 353  * the input value 3, that is mapped to the output value 0 instead of 11.
 354  *
 355  *   Used in handling following instructions:
 356  *
 357  *     - MOVE.BALC
 358  *     - MOVEP
 359  *     - SW[4X4]
 360  */
 361 uint64 NMD::decode_gpr_gpr4_zero(uint64 d)
 362 {
 363     static uint64 register_list[] = {  8,  9, 10,  0,  4,  5,  6,  7,
 364                                       16, 17, 18, 19, 20, 21, 22, 23 };
 365     return renumber_registers(d, register_list,
 366                sizeof(register_list) / sizeof(register_list[0]));
 367 }
 368
 369
 370 /*
 371  * NMD::decode_gpr_gpr3() - decoder for 'gpr3' gpr encoding type
 372  *
 373  *   Map a 3-bit code to the 5-bit register space according to this pattern:
 374  *
 375  *                            7 6 5 4 3 2 1 0
 376  *                            | | | | | | | |
 377  *                            | | | | | | | |
 378  *                            | | | └-----------------------┐
 379  *                            | | └-----------------------┐ |
 380  *                            | └-----------------------┐ | |
 381  *                            └-----------------------┐ | | |
 382  *                                    | | | |         | | | |
 383  *                            ┌-------┘ | | |         | | | |
 384  *                            | ┌-------┘ | |         | | | |
 385  *                            | | ┌-------┘ |         | | | |
 386  *                            | | | ┌-------┘         | | | |
 387  *                            | | | |                 | | | |
 388  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 389  *      3                   2                   1                   0
 390  *
 391  *   Used in handling following instructions:
 392  *
 393  *     - ADDIU[R1.SP]
 394  *     - ADDIU[R2]
 395  *     - ADDU[16]
 396  *     - AND[16]
 397  *     - ANDI[16]
 398  *     - BEQC[16]
 399  *     - BEQZC[16]
 400  *     - BNEC[16]
 401  *     - BNEZC[16]
 402  *     - LB[16]
 403  *     - LBU[16]
 404  *     - LH[16]
 405  *     - LHU[16]
 406  *     - LI[16]
 407  *     - LW[16]
 408  *     - LW[GP16]
 409  *     - LWXS[16]
 410  *     - NOT[16]
 411  *     - OR[16]
 412  *     - SB[16]
 413  *     - SH[16]
 414  *     - SLL[16]
 415  *     - SRL[16]
 416  *     - SUBU[16]
 417  *     - SW[16]
 418  *     - XOR[16]
 419  */
 420 uint64 NMD::decode_gpr_gpr3(uint64 d)
 421 {
 422     static uint64 register_list[] = { 16, 17, 18, 19,  4,  5,  6,  7 };
 423     return renumber_registers(d, register_list,
 424                sizeof(register_list) / sizeof(register_list[0]));
 425 }
 426
 427
 428 /*
 429  * NMD::decode_gpr_gpr3_src_store() - decoder for 'gpr3.src.store' gpr encoding
 430  *     type
 431  *
 432  *   Map a 3-bit code to the 5-bit register space according to this pattern:
 433  *
 434  *                            7 6 5 4 3 2 1 0
 435  *                            | | | | | | | |
 436  *                            | | | | | | | └-----------------------┐
 437  *                            | | | └-----------------------┐       |
 438  *                            | | └-----------------------┐ |       |
 439  *                            | └-----------------------┐ | |       |
 440  *                            └-----------------------┐ | | |       |
 441  *                                    | | |           | | | |       |
 442  *                            ┌-------┘ | |           | | | |       |
 443  *                            | ┌-------┘ |           | | | |       |
 444  *                            | | ┌-------┘           | | | |       |
 445  *                            | | |                   | | | |       |
 446  *                            | | |                   | | | |       |
 447  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 448  *      3                   2                   1                   0
 449  *
 450  *   This pattern is the same one used for 'gpr3' gpr encoding type, except for
 451  * the input value 0, that is mapped to the output value 0 instead of 16.
 452  *
 453  *   Used in handling following instructions:
 454  *
 455  *     - SB[16]
 456  *     - SH[16]
 457  *     - SW[16]
 458  *     - SW[GP16]
 459  */
 460 uint64 NMD::decode_gpr_gpr3_src_store(uint64 d)
 461 {
 462     static uint64 register_list[] = {  0, 17, 18, 19,  4,  5,  6,  7 };
 463     return renumber_registers(d, register_list,
 464                sizeof(register_list) / sizeof(register_list[0]));
 465 }
 466
 467
 468 /*
 469  * NMD::decode_gpr_gpr2_reg1() - decoder for 'gpr2.reg1' gpr encoding type
 470  *
 471  *   Map a 2-bit code to the 5-bit register space according to this pattern:
 472  *
 473  *                                3 2 1 0
 474  *                                | | | |
 475  *                                | | | |
 476  *                                | | | └-------------------┐
 477  *                                | | └-------------------┐ |
 478  *                                | └-------------------┐ | |
 479  *                                └-------------------┐ | | |
 480  *                                                    | | | |
 481  *                                                    | | | |
 482  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 483  *      3                   2                   1                   0
 484  *
 485  *   Used in handling following instructions:
 486  *
 487  *     - MOVEP
 488  *     - MOVEP[REV]
 489  */
 490 uint64 NMD::decode_gpr_gpr2_reg1(uint64 d)
 491 {
 492     static uint64 register_list[] = {  4,  5,  6,  7 };
 493     return renumber_registers(d, register_list,
 494                sizeof(register_list) / sizeof(register_list[0]));
 495 }
 496
 497
 498 /*
 499  * NMD::decode_gpr_gpr2_reg2() - decoder for 'gpr2.reg2' gpr encoding type
 500  *
 501  *   Map a 2-bit code to the 5-bit register space according to this pattern:
 502  *
 503  *                                3 2 1 0
 504  *                                | | | |
 505  *                                | | | |
 506  *                                | | | └-----------------┐
 507  *                                | | └-----------------┐ |
 508  *                                | └-----------------┐ | |
 509  *                                └-----------------┐ | | |
 510  *                                                  | | | |
 511  *                                                  | | | |
 512  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 513  *      3                   2                   1                   0
 514  *
 515  *   Used in handling following instructions:
 516  *
 517  *     - MOVEP
 518  *     - MOVEP[REV]
 519  */
 520 uint64 NMD::decode_gpr_gpr2_reg2(uint64 d)
 521 {
 522     static uint64 register_list[] = {  5,  6,  7,  8 };
 523     return renumber_registers(d, register_list,
 524                sizeof(register_list) / sizeof(register_list[0]));
 525 }
 526
 527
 528 /*
 529  * NMD::decode_gpr_gpr1() - decoder for 'gpr1' gpr encoding type
 530  *
 531  *   Map a 1-bit code to the 5-bit register space according to this pattern:
 532  *
 533  *                                  1 0
 534  *                                  | |
 535  *                                  | |
 536  *                                  | └---------------------┐
 537  *                                  └---------------------┐ |
 538  *                                                        | |
 539  *                                                        | |
 540  *                                                        | |
 541  *                                                        | |
 542  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 543  *      3                   2                   1                   0
 544  *
 545  *   Used in handling following instruction:
 546  *
 547  *     - MOVE.BALC
 548  */
 549 uint64 NMD::decode_gpr_gpr1(uint64 d)
 550 {
 551     static uint64 register_list[] = {  4,  5 };
 552     return renumber_registers(d, register_list,
 553                sizeof(register_list) / sizeof(register_list[0]));
 554 }
 555
 556
 557 uint64 NMD::copy(uint64 d)
 558 {
 559     return d;
 560 }
 561
 562
 563 int64 NMD::copy(int64 d)
 564 {
 565     return d;
 566 }
 567
 568
 569 int64 NMD::neg_copy(uint64 d)
 570 {
 571     return 0ll - d;
 572 }
 573
 574
 575 int64 NMD::neg_copy(int64 d)
 576 {
 577     return -d;
 578 }
 579
 580
 581 /* strange wrapper around  gpr3 */
 582 uint64 NMD::encode_rs3_and_check_rs3_ge_rt3(uint64 d)
 583 {
 584 return decode_gpr_gpr3(d);
 585 }
 586
 587
 588 /* strange wrapper around  gpr3 */
 589 uint64 NMD::encode_rs3_and_check_rs3_lt_rt3(uint64 d)
 590 {
 591     return decode_gpr_gpr3(d);
 592 }
 593
 594
 595 /* nop - done by extraction function */
 596 uint64 NMD::encode_s_from_address(uint64 d)
 597 {
 598     return d;
 599 }
 600
 601
 602 /* nop - done by extraction function */
 603 uint64 NMD::encode_u_from_address(uint64 d)
 604 {
 605     return d;
 606 }
 607
 608
 609 /* nop - done by extraction function */
 610 uint64 NMD::encode_s_from_s_hi(uint64 d)
 611 {
 612     return d;
 613 }
 614
 615
 616 uint64 NMD::encode_count3_from_count(uint64 d)
 617 {
 618     IMGASSERTONCE(d < 8);
 619     return d == 0ull ? 8ull : d;
 620 }
 621
 622
 623 uint64 NMD::encode_shift3_from_shift(uint64 d)
 624 {
 625     IMGASSERTONCE(d < 8);
 626     return d == 0ull ? 8ull : d;
 627 }
 628
 629
 630 /* special value for load literal */
 631 int64 NMD::encode_eu_from_s_li16(uint64 d)
 632 {
 633     IMGASSERTONCE(d < 128);
 634     return d == 127 ? -1 : (int64)d;
 635 }
 636
 637
 638 uint64 NMD::encode_msbd_from_size(uint64 d)
 639 {
 640     IMGASSERTONCE(d < 32);
 641     return d + 1;
 642 }
 643
 644
 645 uint64 NMD::encode_eu_from_u_andi16(uint64 d)
 646 {
 647     IMGASSERTONCE(d < 16);
 648     if (d == 12) {
 649         return 0x00ffull;
 650     }
 651     if (d == 13) {
 652         return 0xffffull;
 653     }
 654     return d;
 655 }
 656
 657
 658 uint64 NMD::encode_msbd_from_pos_and_size(uint64 d)
 659 {
 660     IMGASSERTONCE(0);
 661     return d;
 662 }
 663
 664
 665 /* save16 / restore16   ???? */
 666 uint64 NMD::encode_rt1_from_rt(uint64 d)
 667 {
 668     return d ? 31 : 30;
 669 }
 670
 671
 672 /* ? */
 673 uint64 NMD::encode_lsb_from_pos_and_size(uint64 d)
 674 {
 675     return d;
 676 }
 677
 678
 679 std::string NMD::save_restore_list(uint64 rt, uint64 count, uint64 gp)
 680 {
 681     std::string str;
 682
 683     for (uint64 counter = 0; counter != count; counter++) {
 684         bool use_gp = gp && (counter == count - 1);
 685         uint64 this_rt = use_gp ? 28 : ((rt & 0x10) | (rt + counter)) & 0x1f;
 686         str += img::format(",%s", GPR(this_rt));
 687     }
 688
 689     return str;
 690 }
 691
 692
 693 std::string NMD::GPR(uint64 reg)
 694 {
 695     static const char *gpr_reg[32] = {
 696         "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
 697         "a4",   "a5",   "a6",   "a7",   "r12",  "r13",  "r14",  "r15",
 698         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
 699         "r24",  "r25",  "k0",   "k1",   "gp",   "sp",   "fp",   "ra"
 700     };
 701
 702     if (reg < 32) {
 703         return gpr_reg[reg];
 704     }
 705
 706     throw std::runtime_error(img::format("Invalid GPR register index %" PRIu64,
 707                                          reg));
 708 }
 709
 710
 711 std::string NMD::FPR(uint64 reg)
 712 {
 713     static const char *fpr_reg[32] = {
 714         "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
 715         "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
 716         "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
 717         "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
 718     };
 719
 720     if (reg < 32) {
 721         return fpr_reg[reg];
 722     }
 723
 724     throw std::runtime_error(img::format("Invalid FPR register index %" PRIu64,
 725                                          reg));
 726 }
 727
 728
 729 std::string NMD::AC(uint64 reg)
 730 {
 731     static const char *ac_reg[4] = {
 732         "ac0",  "ac1",  "ac2",  "ac3"
 733     };
 734
 735     if (reg < 4) {
 736         return ac_reg[reg];
 737     }
 738
 739     throw std::runtime_error(img::format("Invalid AC register index %" PRIu64,
 740                                          reg));
 741 }
 742
 743
 744 std::string NMD::IMMEDIATE(uint64 value)
 745 {
 746     return img::format("0x%" PRIx64, value);
 747 }
 748
 749
 750 std::string NMD::IMMEDIATE(int64 value)
 751 {
 752     return img::format("%" PRId64, value);
 753 }
 754
 755
 756 std::string NMD::CPR(uint64 reg)
 757 {
 758     /* needs more work */
 759     return img::format("CP%" PRIu64, reg);
 760 }
 761
 762
 763 std::string NMD::ADDRESS(uint64 value, int instruction_size)
 764 {
 765     /* token for string replace */
 766     /* const char TOKEN_REPLACE = (char)0xa2; */
 767     img::address address = m_pc + value + instruction_size;
 768     /* symbol replacement */
 769     /* return img::as_char(TOKEN_REPLACE) + to_string(address); */
 770     return to_string(address);
 771 }
 772
 773
 774 uint64 NMD::extract_op_code_value(const uint16 * data, int size)
 775 {
 776     switch (size) {
 777     case 16:
 778         return data[0];
 779     case 32:
 780         return ((uint64)data[0] << 16) | data[1];
 781     case 48:
 782         return ((uint64)data[0] << 32) | ((uint64)data[1] << 16) | data[2];
 783     default:
 784         return data[0];
 785     }
 786 }
 787
 788
 789 int NMD::Disassemble(const uint16 * data, std::string & dis,
 790                      NMD::TABLE_ENTRY_TYPE & type)
 791 {
 792     return Disassemble(data, dis, type, MAJOR, 2);
 793 }
 794
 795
 796 /*
 797  * Recurse through tables until the instruction is found then return
 798  * the string and size
 799  *
 800  * inputs:
 801  *      pointer to a word stream,
 802  *      disassember table and size
 803  * returns:
 804  *      instruction size    - negative is error
 805  *      disassembly string  - on error will constain error string
 806  */
 807 int NMD::Disassemble(const uint16 * data, std::string & dis,
 808                      NMD::TABLE_ENTRY_TYPE & type, const Pool *table,
 809                      int table_size)
 810 {
 811     try
 812     {
 813         for (int i = 0; i < table_size; i++) {
 814             uint64 op_code = extract_op_code_value(data,
 815                                  table[i].instructions_size);
 816             if ((op_code & table[i].mask) == table[i].value) {
 817                 /* possible match */
 818                 conditional_function cond = table[i].condition;
 819                 if ((cond == 0) || (this->*cond)(op_code)) {
 820                     try
 821                     {
 822                         if (table[i].type == pool) {
 823                             return Disassemble(data, dis, type,
 824                                                table[i].next_table,
 825                                                table[i].next_table_size);
 826                         } else if ((table[i].type == instruction) ||
 827                                    (table[i].type == call_instruction) ||
 828                                    (table[i].type == branch_instruction) ||
 829                                    (table[i].type == return_instruction)) {
 830                             if ((table[i].attributes != 0) &&
 831                                 (m_requested_instruction_categories &
 832                                  table[i].attributes) == 0) {
 833                                 /*
 834                                  * failed due to instruction having
 835                                  * an ASE attribute and the requested version
 836                                  * not having that attribute
 837                                  */
 838                                 dis = "ASE attribute mismatch";
 839                                 return -5;
 840                             }
 841                             disassembly_function dis_fn = table[i].disassembly;
 842                             if (dis_fn == 0) {
 843                                 dis = "disassembler failure - bad table entry";
 844                                 return -6;
 845                             }
 846                             type = table[i].type;
 847                             dis = (this->*dis_fn)(op_code);
 848                             return table[i].instructions_size;
 849                         } else {
 850                             dis = "reserved instruction";
 851                             return -2;
 852                         }
 853                     }
 854                     catch (std::runtime_error & e)
 855                     {
 856                         dis = e.what();
 857                         return -3;          /* runtime error */
 858                     }
 859                 }
 860             }
 861         }
 862     }
 863     catch (std::exception & e)
 864     {
 865         dis = e.what();
 866         return -4;          /* runtime error */
 867     }
 868
 869     dis = "failed to disassemble";
 870     return -1;      /* failed to disassemble        */
 871 }
 872
 873
 874 uint64 NMD::extract_code_18_to_0(uint64 instruction)
 875 {
 876     uint64 value = 0;
 877     value |= extract_bits(instruction, 0, 19);
 878     return value;
 879 }
 880
 881
 882 uint64 NMD::extract_shift3_2_1_0(uint64 instruction)
 883 {
 884     uint64 value = 0;
 885     value |= extract_bits(instruction, 0, 3);
 886     return value;
 887 }
 888
 889
 890 uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction)
 891 {
 892     uint64 value = 0;
 893     value |= extract_bits(instruction, 3, 9) << 3;
 894     return value;
 895 }
 896
 897
 898 uint64 NMD::extract_count_3_2_1_0(uint64 instruction)
 899 {
 900     uint64 value = 0;
 901     value |= extract_bits(instruction, 0, 4);
 902     return value;
 903 }
 904
 905
 906 uint64 NMD::extract_rtz3_9_8_7(uint64 instruction)
 907 {
 908     uint64 value = 0;
 909     value |= extract_bits(instruction, 7, 3);
 910     return value;
 911 }
 912
 913
 914 uint64 NMD::extract_u_17_to_1__s1(uint64 instruction)
 915 {
 916     uint64 value = 0;
 917     value |= extract_bits(instruction, 1, 17) << 1;
 918     return value;
 919 }
 920
 921
 922 int64 NMD::extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction)
 923 {
 924     int64 value = 0;
 925     value |= extract_bits(instruction, 11, 10);
 926     value = sign_extend(value, 9);
 927     return value;
 928 }
 929
 930
 931 int64 NMD::extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction)
 932 {
 933     int64 value = 0;
 934     value |= extract_bits(instruction, 0, 1) << 11;
 935     value |= extract_bits(instruction, 1, 10) << 1;
 936     value = sign_extend(value, 11);
 937     return value;
 938 }
 939
 940
 941 uint64 NMD::extract_u_10(uint64 instruction)
 942 {
 943     uint64 value = 0;
 944     value |= extract_bits(instruction, 10, 1);
 945     return value;
 946 }
 947
 948
 949 uint64 NMD::extract_rtz4_27_26_25_23_22_21(uint64 instruction)
 950 {
 951     uint64 value = 0;
 952     value |= extract_bits(instruction, 21, 3);
 953     value |= extract_bits(instruction, 25, 1) << 3;
 954     return value;
 955 }
 956
 957
 958 uint64 NMD::extract_sa_15_14_13_12_11(uint64 instruction)
 959 {
 960     uint64 value = 0;
 961     value |= extract_bits(instruction, 11, 5);
 962     return value;
 963 }
 964
 965
 966 uint64 NMD::extract_shift_4_3_2_1_0(uint64 instruction)
 967 {
 968     uint64 value = 0;
 969     value |= extract_bits(instruction, 0, 5);
 970     return value;
 971 }
 972
 973
 974 uint64 NMD::extract_shiftx_10_9_8_7__s1(uint64 instruction)
 975 {
 976     uint64 value = 0;
 977     value |= extract_bits(instruction, 7, 4) << 1;
 978     return value;
 979 }
 980
 981
 982 uint64 NMD::extract_hint_25_24_23_22_21(uint64 instruction)
 983 {
 984     uint64 value = 0;
 985     value |= extract_bits(instruction, 21, 5);
 986     return value;
 987 }
 988
 989
 990 uint64 NMD::extract_count3_14_13_12(uint64 instruction)
 991 {
 992     uint64 value = 0;
 993     value |= extract_bits(instruction, 12, 3);
 994     return value;
 995 }
 996
 997
 998 int64 NMD::extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction)
 999 {
1000     int64 value = 0;
1001     value |= extract_bits(instruction, 0, 1) << 31;
1002     value |= extract_bits(instruction, 2, 10) << 21;
1003     value |= extract_bits(instruction, 12, 9) << 12;
1004     value = sign_extend(value, 31);
1005     return value;
1006 }
1007
1008
1009 int64 NMD::extract_s__se7_0_6_5_4_3_2_1_s1(uint64 instruction)
1010 {
1011     int64 value = 0;
1012     value |= extract_bits(instruction, 0, 1) << 7;
1013     value |= extract_bits(instruction, 1, 6) << 1;
1014     value = sign_extend(value, 7);
1015     return value;
1016 }
1017
1018
1019 uint64 NMD::extract_u2_10_9(uint64 instruction)
1020 {
1021     uint64 value = 0;
1022     value |= extract_bits(instruction, 9, 2);
1023     return value;
1024 }
1025
1026
1027 uint64 NMD::extract_code_25_24_23_22_21_20_19_18_17_16(uint64 instruction)
1028 {
1029     uint64 value = 0;
1030     value |= extract_bits(instruction, 16, 10);
1031     return value;
1032 }
1033
1034
1035 uint64 NMD::extract_rs_20_19_18_17_16(uint64 instruction)
1036 {
1037     uint64 value = 0;
1038     value |= extract_bits(instruction, 16, 5);
1039     return value;
1040 }
1041
1042
1043 uint64 NMD::extract_u_2_1__s1(uint64 instruction)
1044 {
1045     uint64 value = 0;
1046     value |= extract_bits(instruction, 1, 2) << 1;
1047     return value;
1048 }
1049
1050
1051 uint64 NMD::extract_stripe_6(uint64 instruction)
1052 {
1053     uint64 value = 0;
1054     value |= extract_bits(instruction, 6, 1);
1055     return value;
1056 }
1057
1058
1059 uint64 NMD::extract_ac_15_14(uint64 instruction)
1060 {
1061     uint64 value = 0;
1062     value |= extract_bits(instruction, 14, 2);
1063     return value;
1064 }
1065
1066
1067 uint64 NMD::extract_shift_20_19_18_17_16(uint64 instruction)
1068 {
1069     uint64 value = 0;
1070     value |= extract_bits(instruction, 16, 5);
1071     return value;
1072 }
1073
1074
1075 uint64 NMD::extract_rdl_25_24(uint64 instruction)
1076 {
1077     uint64 value = 0;
1078     value |= extract_bits(instruction, 24, 1);
1079     return value;
1080 }
1081
1082
1083 int64 NMD::extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(uint64 instruction)
1084 {
1085     int64 value = 0;
1086     value |= extract_bits(instruction, 0, 1) << 10;
1087     value |= extract_bits(instruction, 1, 9) << 1;
1088     value = sign_extend(value, 10);
1089     return value;
1090 }
1091
1092
1093 uint64 NMD::extract_eu_6_5_4_3_2_1_0(uint64 instruction)
1094 {
1095     uint64 value = 0;
1096     value |= extract_bits(instruction, 0, 7);
1097     return value;
1098 }
1099
1100
1101 uint64 NMD::extract_shift_5_4_3_2_1_0(uint64 instruction)
1102 {
1103     uint64 value = 0;
1104     value |= extract_bits(instruction, 0, 6);
1105     return value;
1106 }
1107
1108
1109 uint64 NMD::extract_count_19_18_17_16(uint64 instruction)
1110 {
1111     uint64 value = 0;
1112     value |= extract_bits(instruction, 16, 4);
1113     return value;
1114 }
1115
1116
1117 uint64 NMD::extract_code_2_1_0(uint64 instruction)
1118 {
1119     uint64 value = 0;
1120     value |= extract_bits(instruction, 0, 3);
1121     return value;
1122 }
1123
1124
1125 uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction)
1126 {
1127     uint64 value = 0;
1128     value |= extract_bits(instruction, 0, 12);
1129     return value;
1130 }
1131
1132
1133 uint64 NMD::extract_rs_4_3_2_1_0(uint64 instruction)
1134 {
1135     uint64 value = 0;
1136     value |= extract_bits(instruction, 0, 5);
1137     return value;
1138 }
1139
1140
1141 uint64 NMD::extract_u_20_to_3__s3(uint64 instruction)
1142 {
1143     uint64 value = 0;
1144     value |= extract_bits(instruction, 3, 18) << 3;
1145     return value;
1146 }
1147
1148
1149 uint64 NMD::extract_u_3_2_1_0__s2(uint64 instruction)
1150 {
1151     uint64 value = 0;
1152     value |= extract_bits(instruction, 0, 4) << 2;
1153     return value;
1154 }
1155
1156
1157 uint64 NMD::extract_cofun_25_24_23(uint64 instruction)
1158 {
1159     uint64 value = 0;
1160     value |= extract_bits(instruction, 3, 23);
1161     return value;
1162 }
1163
1164
1165 uint64 NMD::extract_u_2_1_0__s2(uint64 instruction)
1166 {
1167     uint64 value = 0;
1168     value |= extract_bits(instruction, 0, 3) << 2;
1169     return value;
1170 }
1171
1172
1173 uint64 NMD::extract_rd3_3_2_1(uint64 instruction)
1174 {
1175     uint64 value = 0;
1176     value |= extract_bits(instruction, 1, 3);
1177     return value;
1178 }
1179
1180
1181 uint64 NMD::extract_sa_15_14_13_12(uint64 instruction)
1182 {
1183     uint64 value = 0;
1184     value |= extract_bits(instruction, 12, 4);
1185     return value;
1186 }
1187
1188
1189 uint64 NMD::extract_rt_25_24_23_22_21(uint64 instruction)
1190 {
1191     uint64 value = 0;
1192     value |= extract_bits(instruction, 21, 5);
1193     return value;
1194 }
1195
1196
1197 uint64 NMD::extract_ru_7_6_5_4_3(uint64 instruction)
1198 {
1199     uint64 value = 0;
1200     value |= extract_bits(instruction, 3, 5);
1201     return value;
1202 }
1203
1204
1205 uint64 NMD::extract_u_17_to_0(uint64 instruction)
1206 {
1207     uint64 value = 0;
1208     value |= extract_bits(instruction, 0, 18);
1209     return value;
1210 }
1211
1212
1213 uint64 NMD::extract_rsz4_4_2_1_0(uint64 instruction)
1214 {
1215     uint64 value = 0;
1216     value |= extract_bits(instruction, 0, 3);
1217     value |= extract_bits(instruction, 4, 1) << 3;
1218     return value;
1219 }
1220
1221
1222 int64 NMD::extract_s__se21_0_20_to_1_s1(uint64 instruction)
1223 {
1224     int64 value = 0;
1225     value |= extract_bits(instruction, 0, 1) << 21;
1226     value |= extract_bits(instruction, 1, 20) << 1;
1227     value = sign_extend(value, 21);
1228     return value;
1229 }
1230
1231
1232 uint64 NMD::extract_op_25_to_3(uint64 instruction)
1233 {
1234     uint64 value = 0;
1235     value |= extract_bits(instruction, 3, 23);
1236     return value;
1237 }
1238
1239
1240 uint64 NMD::extract_rs4_4_2_1_0(uint64 instruction)
1241 {
1242     uint64 value = 0;
1243     value |= extract_bits(instruction, 0, 3);
1244     value |= extract_bits(instruction, 4, 1) << 3;
1245     return value;
1246 }
1247
1248
1249 uint64 NMD::extract_bit_23_22_21(uint64 instruction)
1250 {
1251     uint64 value = 0;
1252     value |= extract_bits(instruction, 21, 3);
1253     return value;
1254 }
1255
1256
1257 uint64 NMD::extract_rt_41_40_39_38_37(uint64 instruction)
1258 {
1259     uint64 value = 0;
1260     value |= extract_bits(instruction, 37, 5);
1261     return value;
1262 }
1263
1264
1265 int64 NMD::extract_shift__se5_21_20_19_18_17_16(uint64 instruction)
1266 {
1267     int64 value = 0;
1268     value |= extract_bits(instruction, 16, 6);
1269     value = sign_extend(value, 5);
1270     return value;
1271 }
1272
1273
1274 uint64 NMD::extract_rd2_3_8(uint64 instruction)
1275 {
1276     uint64 value = 0;
1277     value |= extract_bits(instruction, 3, 1) << 1;
1278     value |= extract_bits(instruction, 8, 1);
1279     return value;
1280 }
1281
1282
1283 uint64 NMD::extract_code_17_to_0(uint64 instruction)
1284 {
1285     uint64 value = 0;
1286     value |= extract_bits(instruction, 0, 18);
1287     return value;
1288 }
1289
1290
1291 uint64 NMD::extract_size_20_19_18_17_16(uint64 instruction)
1292 {
1293     uint64 value = 0;
1294     value |= extract_bits(instruction, 16, 5);
1295     return value;
1296 }
1297
1298
1299 int64 NMD::extract_s__se8_15_7_6_5_4_3_2_s2(uint64 instruction)
1300 {
1301     int64 value = 0;
1302     value |= extract_bits(instruction, 2, 6) << 2;
1303     value |= extract_bits(instruction, 15, 1) << 8;
1304     value = sign_extend(value, 8);
1305     return value;
1306 }
1307
1308
1309 uint64 NMD::extract_u_15_to_0(uint64 instruction)
1310 {
1311     uint64 value = 0;
1312     value |= extract_bits(instruction, 0, 16);
1313     return value;
1314 }
1315
1316
1317 uint64 NMD::extract_fs_20_19_18_17_16(uint64 instruction)
1318 {
1319     uint64 value = 0;
1320     value |= extract_bits(instruction, 16, 5);
1321     return value;
1322 }
1323
1324
1325 int64 NMD::extract_s__se8_15_7_6_5_4_3_2_1_0(uint64 instruction)
1326 {
1327     int64 value = 0;
1328     value |= extract_bits(instruction, 0, 8);
1329     value |= extract_bits(instruction, 15, 1) << 8;
1330     value = sign_extend(value, 8);
1331     return value;
1332 }
1333
1334
1335 uint64 NMD::extract_stype_20_19_18_17_16(uint64 instruction)
1336 {
1337     uint64 value = 0;
1338     value |= extract_bits(instruction, 16, 5);
1339     return value;
1340 }
1341
1342
1343 uint64 NMD::extract_rtl_11(uint64 instruction)
1344 {
1345     uint64 value = 0;
1346     value |= extract_bits(instruction, 9, 1);
1347     return value;
1348 }
1349
1350
1351 uint64 NMD::extract_hs_20_19_18_17_16(uint64 instruction)
1352 {
1353     uint64 value = 0;
1354     value |= extract_bits(instruction, 16, 5);
1355     return value;
1356 }
1357
1358
1359 uint64 NMD::extract_sel_13_12_11(uint64 instruction)
1360 {
1361     uint64 value = 0;
1362     value |= extract_bits(instruction, 11, 3);
1363     return value;
1364 }
1365
1366
1367 uint64 NMD::extract_lsb_4_3_2_1_0(uint64 instruction)
1368 {
1369     uint64 value = 0;
1370     value |= extract_bits(instruction, 0, 5);
1371     return value;
1372 }
1373
1374
1375 uint64 NMD::extract_gp_2(uint64 instruction)
1376 {
1377     uint64 value = 0;
1378     value |= extract_bits(instruction, 2, 1);
1379     return value;
1380 }
1381
1382
1383 uint64 NMD::extract_rt3_9_8_7(uint64 instruction)
1384 {
1385     uint64 value = 0;
1386     value |= extract_bits(instruction, 7, 3);
1387     return value;
1388 }
1389
1390
1391 uint64 NMD::extract_ft_25_24_23_22_21(uint64 instruction)
1392 {
1393     uint64 value = 0;
1394     value |= extract_bits(instruction, 21, 5);
1395     return value;
1396 }
1397
1398
1399 uint64 NMD::extract_u_17_16_15_14_13_12_11(uint64 instruction)
1400 {
1401     uint64 value = 0;
1402     value |= extract_bits(instruction, 11, 7);
1403     return value;
1404 }
1405
1406
1407 uint64 NMD::extract_cs_20_19_18_17_16(uint64 instruction)
1408 {
1409     uint64 value = 0;
1410     value |= extract_bits(instruction, 16, 5);
1411     return value;
1412 }
1413
1414
1415 uint64 NMD::extract_rt4_9_7_6_5(uint64 instruction)
1416 {
1417     uint64 value = 0;
1418     value |= extract_bits(instruction, 5, 3);
1419     value |= extract_bits(instruction, 9, 1) << 3;
1420     return value;
1421 }
1422
1423
1424 uint64 NMD::extract_msbt_10_9_8_7_6(uint64 instruction)
1425 {
1426     uint64 value = 0;
1427     value |= extract_bits(instruction, 6, 5);
1428     return value;
1429 }
1430
1431
1432 uint64 NMD::extract_u_5_4_3_2_1_0__s2(uint64 instruction)
1433 {
1434     uint64 value = 0;
1435     value |= extract_bits(instruction, 0, 6) << 2;
1436     return value;
1437 }
1438
1439
1440 uint64 NMD::extract_sa_15_14_13(uint64 instruction)
1441 {
1442     uint64 value = 0;
1443     value |= extract_bits(instruction, 13, 3);
1444     return value;
1445 }
1446
1447
1448 int64 NMD::extract_s__se14_0_13_to_1_s1(uint64 instruction)
1449 {
1450     int64 value = 0;
1451     value |= extract_bits(instruction, 0, 1) << 14;
1452     value |= extract_bits(instruction, 1, 13) << 1;
1453     value = sign_extend(value, 14);
1454     return value;
1455 }
1456
1457
1458 uint64 NMD::extract_rs3_6_5_4(uint64 instruction)
1459 {
1460     uint64 value = 0;
1461     value |= extract_bits(instruction, 4, 3);
1462     return value;
1463 }
1464
1465
1466 uint64 NMD::extract_u_31_to_0__s32(uint64 instruction)
1467 {
1468     uint64 value = 0;
1469     value |= extract_bits(instruction, 0, 32) << 32;
1470     return value;
1471 }
1472
1473
1474 uint64 NMD::extract_shift_10_9_8_7_6(uint64 instruction)
1475 {
1476     uint64 value = 0;
1477     value |= extract_bits(instruction, 6, 5);
1478     return value;
1479 }
1480
1481
1482 uint64 NMD::extract_cs_25_24_23_22_21(uint64 instruction)
1483 {
1484     uint64 value = 0;
1485     value |= extract_bits(instruction, 21, 5);
1486     return value;
1487 }
1488
1489
1490 uint64 NMD::extract_shiftx_11_10_9_8_7_6(uint64 instruction)
1491 {
1492     uint64 value = 0;
1493     value |= extract_bits(instruction, 6, 6);
1494     return value;
1495 }
1496
1497
1498 uint64 NMD::extract_rt_9_8_7_6_5(uint64 instruction)
1499 {
1500     uint64 value = 0;
1501     value |= extract_bits(instruction, 5, 5);
1502     return value;
1503 }
1504
1505
1506 uint64 NMD::extract_op_25_24_23_22_21(uint64 instruction)
1507 {
1508     uint64 value = 0;
1509     value |= extract_bits(instruction, 21, 5);
1510     return value;
1511 }
1512
1513
1514 uint64 NMD::extract_u_6_5_4_3_2_1_0__s2(uint64 instruction)
1515 {
1516     uint64 value = 0;
1517     value |= extract_bits(instruction, 0, 7) << 2;
1518     return value;
1519 }
1520
1521
1522 uint64 NMD::extract_bit_16_15_14_13_12_11(uint64 instruction)
1523 {
1524     uint64 value = 0;
1525     value |= extract_bits(instruction, 11, 6);
1526     return value;
1527 }
1528
1529
1530 uint64 NMD::extract_mask_20_19_18_17_16_15_14(uint64 instruction)
1531 {
1532     uint64 value = 0;
1533     value |= extract_bits(instruction, 14, 7);
1534     return value;
1535 }
1536
1537
1538 uint64 NMD::extract_eu_3_2_1_0(uint64 instruction)
1539 {
1540     uint64 value = 0;
1541     value |= extract_bits(instruction, 0, 4);
1542     return value;
1543 }
1544
1545
1546 uint64 NMD::extract_u_7_6_5_4__s4(uint64 instruction)
1547 {
1548     uint64 value = 0;
1549     value |= extract_bits(instruction, 4, 4) << 4;
1550     return value;
1551 }
1552
1553
1554 int64 NMD::extract_s__se8_15_7_6_5_4_3_s3(uint64 instruction)
1555 {
1556     int64 value = 0;
1557     value |= extract_bits(instruction, 3, 5) << 3;
1558     value |= extract_bits(instruction, 15, 1) << 8;
1559     value = sign_extend(value, 8);
1560     return value;
1561 }
1562
1563
1564 uint64 NMD::extract_ft_15_14_13_12_11(uint64 instruction)
1565 {
1566     uint64 value = 0;
1567     value |= extract_bits(instruction, 11, 5);
1568     return value;
1569 }
1570
1571
1572 int64 NMD::extract_s__se31_15_to_0_31_to_16(uint64 instruction)
1573 {
1574     int64 value = 0;
1575     value |= extract_bits(instruction, 0, 16) << 16;
1576     value |= extract_bits(instruction, 16, 16);
1577     value = sign_extend(value, 31);
1578     return value;
1579 }
1580
1581
1582 uint64 NMD::extract_u_20_19_18_17_16_15_14_13(uint64 instruction)
1583 {
1584     uint64 value = 0;
1585     value |= extract_bits(instruction, 13, 8);
1586     return value;
1587 }
1588
1589
1590 uint64 NMD::extract_u_17_to_2__s2(uint64 instruction)
1591 {
1592     uint64 value = 0;
1593     value |= extract_bits(instruction, 2, 16) << 2;
1594     return value;
1595 }
1596
1597
1598 uint64 NMD::extract_rd_15_14_13_12_11(uint64 instruction)
1599 {
1600     uint64 value = 0;
1601     value |= extract_bits(instruction, 11, 5);
1602     return value;
1603 }
1604
1605
1606 uint64 NMD::extract_c0s_20_19_18_17_16(uint64 instruction)
1607 {
1608     uint64 value = 0;
1609     value |= extract_bits(instruction, 16, 5);
1610     return value;
1611 }
1612
1613
1614 uint64 NMD::extract_code_1_0(uint64 instruction)
1615 {
1616     uint64 value = 0;
1617     value |= extract_bits(instruction, 0, 2);
1618     return value;
1619 }
1620
1621
1622 int64 NMD::extract_s__se25_0_24_to_1_s1(uint64 instruction)
1623 {
1624     int64 value = 0;
1625     value |= extract_bits(instruction, 0, 1) << 25;
1626     value |= extract_bits(instruction, 1, 24) << 1;
1627     value = sign_extend(value, 25);
1628     return value;
1629 }
1630
1631
1632 uint64 NMD::extract_u_1_0(uint64 instruction)
1633 {
1634     uint64 value = 0;
1635     value |= extract_bits(instruction, 0, 2);
1636     return value;
1637 }
1638
1639
1640 uint64 NMD::extract_u_3_8__s2(uint64 instruction)
1641 {
1642     uint64 value = 0;
1643     value |= extract_bits(instruction, 3, 1) << 3;
1644     value |= extract_bits(instruction, 8, 1) << 2;
1645     return value;
1646 }
1647
1648
1649 uint64 NMD::extract_fd_15_14_13_12_11(uint64 instruction)
1650 {
1651     uint64 value = 0;
1652     value |= extract_bits(instruction, 11, 5);
1653     return value;
1654 }
1655
1656
1657 uint64 NMD::extract_u_4_3_2_1_0__s2(uint64 instruction)
1658 {
1659     uint64 value = 0;
1660     value |= extract_bits(instruction, 0, 5) << 2;
1661     return value;
1662 }
1663
1664
1665 uint64 NMD::extract_rtz4_9_7_6_5(uint64 instruction)
1666 {
1667     uint64 value = 0;
1668     value |= extract_bits(instruction, 5, 3);
1669     value |= extract_bits(instruction, 9, 1) << 3;
1670     return value;
1671 }
1672
1673
1674 uint64 NMD::extract_sel_15_14_13_12_11(uint64 instruction)
1675 {
1676     uint64 value = 0;
1677     value |= extract_bits(instruction, 11, 5);
1678     return value;
1679 }
1680
1681
1682 uint64 NMD::extract_ct_25_24_23_22_21(uint64 instruction)
1683 {
1684     uint64 value = 0;
1685     value |= extract_bits(instruction, 21, 5);
1686     return value;
1687 }
1688
1689
1690 uint64 NMD::extract_u_20_to_2__s2(uint64 instruction)
1691 {
1692     uint64 value = 0;
1693     value |= extract_bits(instruction, 2, 19) << 2;
1694     return value;
1695 }
1696
1697
1698 int64 NMD::extract_s__se3_4_2_1_0(uint64 instruction)
1699 {
1700     int64 value = 0;
1701     value |= extract_bits(instruction, 0, 3);
1702     value |= extract_bits(instruction, 4, 1) << 3;
1703     value = sign_extend(value, 3);
1704     return value;
1705 }
1706
1707
1708 uint64 NMD::extract_u_3_2_1_0__s1(uint64 instruction)
1709 {
1710     uint64 value = 0;
1711     value |= extract_bits(instruction, 0, 4) << 1;
1712     return value;
1713 }
1714
1715
1716
1717 bool NMD::ADDIU_32__cond(uint64 instruction)
1718 {
1719     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1720     return rt != 0;
1721 }
1722
1723
1724 bool NMD::ADDIU_RS5__cond(uint64 instruction)
1725 {
1726     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1727     return rt != 0;
1728 }
1729
1730
1731 bool NMD::BALRSC_cond(uint64 instruction)
1732 {
1733     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1734     return rt != 0;
1735 }
1736
1737
1738 bool NMD::BEQC_16__cond(uint64 instruction)
1739 {
1740     uint64 rs3 = extract_rs3_6_5_4(instruction);
1741     uint64 rt3 = extract_rt3_9_8_7(instruction);
1742     uint64 u = extract_u_3_2_1_0__s1(instruction);
1743     return rs3 < rt3 && u != 0;
1744 }
1745
1746
1747 bool NMD::BNEC_16__cond(uint64 instruction)
1748 {
1749     uint64 rs3 = extract_rs3_6_5_4(instruction);
1750     uint64 rt3 = extract_rt3_9_8_7(instruction);
1751     uint64 u = extract_u_3_2_1_0__s1(instruction);
1752     return rs3 >= rt3 && u != 0;
1753 }
1754
1755
1756 bool NMD::MOVE_cond(uint64 instruction)
1757 {
1758     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1759     return rt != 0;
1760 }
1761
1762
1763 bool NMD::P16_BR1_cond(uint64 instruction)
1764 {
1765     uint64 u = extract_u_3_2_1_0__s1(instruction);
1766     return u != 0;
1767 }
1768
1769
1770 bool NMD::PREF_S9__cond(uint64 instruction)
1771 {
1772     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1773     return hint != 31;
1774 }
1775
1776
1777 bool NMD::PREFE_cond(uint64 instruction)
1778 {
1779     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1780     return hint != 31;
1781 }
1782
1783
1784 bool NMD::SLTU_cond(uint64 instruction)
1785 {
1786     uint64 rd = extract_rd_15_14_13_12_11(instruction);
1787     return rd != 0;
1788 }
1789
1790
1791
1792 /*
1793  * ABS.D fd, fs - Floating Point Absolute Value
1794  *
1795  *   3         2         1
1796  *  10987654321098765432109876543210
1797  *  010001     00000          000101
1798  *    fmt -----
1799  *               fs -----
1800  *                    fd -----
1801  */
1802 std::string NMD::ABS_D(uint64 instruction)
1803 {
1804     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1805     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1806
1807     std::string fs = FPR(copy(fs_value));
1808     std::string fd = FPR(copy(fd_value));
1809
1810     return img::format("ABS.D %s, %s", fd, fs);
1811 }
1812
1813
1814 /*
1815  * ABS.S fd, fs - Floating Point Absolute Value
1816  *
1817  *   3         2         1
1818  *  10987654321098765432109876543210
1819  *  010001     00000          000101
1820  *    fmt -----
1821  *               fd -----
1822  *                    fs -----
1823  */
1824 std::string NMD::ABS_S(uint64 instruction)
1825 {
1826     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1827     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1828
1829     std::string fs = FPR(copy(fs_value));
1830     std::string fd = FPR(copy(fd_value));
1831
1832     return img::format("ABS.S %s, %s", fd, fs);
1833 }
1834
1835
1836 /*
1837  * [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
1838  *         with 16-bit saturation
1839  *
1840  *   3         2         1
1841  *  10987654321098765432109876543210
1842  *  001000          0001000100111111
1843  *     rt -----
1844  *          rs -----
1845  */
1846 std::string NMD::ABSQ_S_PH(uint64 instruction)
1847 {
1848     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1849     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1850
1851     std::string rt = GPR(copy(rt_value));
1852     std::string rs = GPR(copy(rs_value));
1853
1854     return img::format("ABSQ_S.PH %s, %s", rt, rs);
1855 }
1856
1857
1858 /*
1859  * [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
1860  *         with 8-bit saturation
1861  *
1862  *   3         2         1
1863  *  10987654321098765432109876543210
1864  *  001000          0000000100111111
1865  *     rt -----
1866  *          rs -----
1867  */
1868 std::string NMD::ABSQ_S_QB(uint64 instruction)
1869 {
1870     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1871     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1872
1873     std::string rt = GPR(copy(rt_value));
1874     std::string rs = GPR(copy(rs_value));
1875
1876     return img::format("ABSQ_S.QB %s, %s", rt, rs);
1877 }
1878
1879
1880 /*
1881  * [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
1882  *         saturation
1883  *
1884  *   3         2         1
1885  *  10987654321098765432109876543210
1886  *  001000          0010000100111111
1887  *     rt -----
1888  *          rs -----
1889  */
1890 std::string NMD::ABSQ_S_W(uint64 instruction)
1891 {
1892     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1893     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1894
1895     std::string rt = GPR(copy(rt_value));
1896     std::string rs = GPR(copy(rs_value));
1897
1898     return img::format("ABSQ_S.W %s, %s", rt, rs);
1899 }
1900
1901
1902 /*
1903  *
1904  *
1905  *   3         2         1
1906  *  10987654321098765432109876543210
1907  *  001000          0010000100111111
1908  *     rt -----
1909  *          rs -----
1910  */
1911 std::string NMD::ACLR(uint64 instruction)
1912 {
1913     uint64 bit_value = extract_bit_23_22_21(instruction);
1914     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1915     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
1916
1917     std::string bit = IMMEDIATE(copy(bit_value));
1918     std::string s = IMMEDIATE(copy(s_value));
1919     std::string rs = GPR(copy(rs_value));
1920
1921     return img::format("ACLR %s, %s(%s)", bit, s, rs);
1922 }
1923
1924
1925 /*
1926  *
1927  *
1928  *   3         2         1
1929  *  10987654321098765432109876543210
1930  *  001000          0010000100111111
1931  *     rt -----
1932  *          rs -----
1933  */
1934 std::string NMD::ADD(uint64 instruction)
1935 {
1936     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1937     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1938     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1939
1940     std::string rd = GPR(copy(rd_value));
1941     std::string rs = GPR(copy(rs_value));
1942     std::string rt = GPR(copy(rt_value));
1943
1944     return img::format("ADD %s, %s, %s", rd, rs, rt);
1945 }
1946
1947
1948 /*
1949  * ADD.D fd, fs, ft - Floating Point Add
1950  *
1951  *   3         2         1
1952  *  10987654321098765432109876543210
1953  *  010001                    000101
1954  *    fmt -----
1955  *          ft -----
1956  *               fs -----
1957  *                    fd -----
1958  */
1959 std::string NMD::ADD_D(uint64 instruction)
1960 {
1961     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1962     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1963     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1964
1965     std::string ft = FPR(copy(ft_value));
1966     std::string fs = FPR(copy(fs_value));
1967     std::string fd = FPR(copy(fd_value));
1968
1969     return img::format("ADD.D %s, %s, %s", fd, fs, ft);
1970 }
1971
1972
1973 /*
1974  * ADD.S fd, fs, ft - Floating Point Add
1975  *
1976  *   3         2         1
1977  *  10987654321098765432109876543210
1978  *  010001                    000101
1979  *    fmt -----
1980  *          ft -----
1981  *               fs -----
1982  *                    fd -----
1983  */
1984 std::string NMD::ADD_S(uint64 instruction)
1985 {
1986     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1987     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1988     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1989
1990     std::string ft = FPR(copy(ft_value));
1991     std::string fs = FPR(copy(fs_value));
1992     std::string fd = FPR(copy(fd_value));
1993
1994     return img::format("ADD.S %s, %s, %s", fd, fs, ft);
1995 }
1996
1997
1998 /*
1999  *
2000  *
2001  *   3         2         1
2002  *  10987654321098765432109876543210
2003  *  001000          0010000100111111
2004  *     rt -----
2005  *          rs -----
2006  */
2007 std::string NMD::ADDIU_32_(uint64 instruction)
2008 {
2009     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2010     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2011     uint64 u_value = extract_u_15_to_0(instruction);
2012
2013     std::string rt = GPR(copy(rt_value));
2014     std::string rs = GPR(copy(rs_value));
2015     std::string u = IMMEDIATE(copy(u_value));
2016
2017     return img::format("ADDIU %s, %s, %s", rt, rs, u);
2018 }
2019
2020
2021 /*
2022  *
2023  *
2024  *   3         2         1
2025  *  10987654321098765432109876543210
2026  *  001000          0010000100111111
2027  *     rt -----
2028  *          rs -----
2029  */
2030 std::string NMD::ADDIU_48_(uint64 instruction)
2031 {
2032     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2033     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
2034
2035     std::string rt = GPR(copy(rt_value));
2036     std::string s = IMMEDIATE(copy(s_value));
2037
2038     return img::format("ADDIU %s, %s", rt, s);
2039 }
2040
2041
2042 /*
2043  *
2044  *
2045  *   3         2         1
2046  *  10987654321098765432109876543210
2047  *  001000          0010000100111111
2048  *     rt -----
2049  *          rs -----
2050  */
2051 std::string NMD::ADDIU_GP48_(uint64 instruction)
2052 {
2053     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2054     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
2055
2056     std::string rt = GPR(copy(rt_value));
2057     std::string s = IMMEDIATE(copy(s_value));
2058
2059     return img::format("ADDIU %s, $%d, %s", rt, 28, s);
2060 }
2061
2062
2063 /*
2064  *
2065  *
2066  *   3         2         1
2067  *  10987654321098765432109876543210
2068  *  001000          0010000100111111
2069  *     rt -----
2070  *          rs -----
2071  */
2072 std::string NMD::ADDIU_GP_B_(uint64 instruction)
2073 {
2074     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2075     uint64 u_value = extract_u_17_to_0(instruction);
2076
2077     std::string rt = GPR(copy(rt_value));
2078     std::string u = IMMEDIATE(copy(u_value));
2079
2080     return img::format("ADDIU %s, $%d, %s", rt, 28, u);
2081 }
2082
2083
2084 /*
2085  *
2086  *
2087  *   3         2         1
2088  *  10987654321098765432109876543210
2089  *  001000          0010000100111111
2090  *     rt -----
2091  *          rs -----
2092  */
2093 std::string NMD::ADDIU_GP_W_(uint64 instruction)
2094 {
2095     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2096     uint64 u_value = extract_u_20_to_2__s2(instruction);
2097
2098     std::string rt = GPR(copy(rt_value));
2099     std::string u = IMMEDIATE(copy(u_value));
2100
2101     return img::format("ADDIU %s, $%d, %s", rt, 28, u);
2102 }
2103
2104
2105 /*
2106  *
2107  *
2108  *   3         2         1
2109  *  10987654321098765432109876543210
2110  *  001000          0010000100111111
2111  *     rt -----
2112  *          rs -----
2113  */
2114 std::string NMD::ADDIU_NEG_(uint64 instruction)
2115 {
2116     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2117     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2118     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2119
2120     std::string rt = GPR(copy(rt_value));
2121     std::string rs = GPR(copy(rs_value));
2122     std::string u = IMMEDIATE(neg_copy(u_value));
2123
2124     return img::format("ADDIU %s, %s, %s", rt, rs, u);
2125 }
2126
2127
2128 /*
2129  *
2130  *
2131  *   3         2         1
2132  *  10987654321098765432109876543210
2133  *  001000          0010000100111111
2134  *     rt -----
2135  *          rs -----
2136  */
2137 std::string NMD::ADDIU_R1_SP_(uint64 instruction)
2138 {
2139     uint64 u_value = extract_u_5_4_3_2_1_0__s2(instruction);
2140     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2141
2142     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2143     std::string u = IMMEDIATE(copy(u_value));
2144
2145     return img::format("ADDIU %s, $%d, %s", rt3, 29, u);
2146 }
2147
2148
2149 /*
2150  *
2151  *
2152  *   3         2         1
2153  *  10987654321098765432109876543210
2154  *  001000          0010000100111111
2155  *     rt -----
2156  *          rs -----
2157  */
2158 std::string NMD::ADDIU_R2_(uint64 instruction)
2159 {
2160     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2161     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2162     uint64 u_value = extract_u_2_1_0__s2(instruction);
2163
2164     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2165     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2166     std::string u = IMMEDIATE(copy(u_value));
2167
2168     return img::format("ADDIU %s, %s, %s", rt3, rs3, u);
2169 }
2170
2171
2172 /*
2173  * ADDIU[RS5] rt, s5 - Add Signed Word and Set Carry Bit
2174  *
2175  *  5432109876543210
2176  *  100100      1
2177  *     rt -----
2178  *           s - ---
2179  */
2180 std::string NMD::ADDIU_RS5_(uint64 instruction)
2181 {
2182     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
2183     int64 s_value = extract_s__se3_4_2_1_0(instruction);
2184
2185     std::string rt = GPR(copy(rt_value));
2186     std::string s = IMMEDIATE(copy(s_value));
2187
2188     return img::format("ADDIU %s, %s", rt, s);
2189 }
2190
2191
2192 /*
2193  *
2194  *
2195  *   3         2         1
2196  *  10987654321098765432109876543210
2197  *  001000               x1110000101
2198  *     rt -----
2199  *          rs -----
2200  *               rd -----
2201  */
2202 std::string NMD::ADDIUPC_32_(uint64 instruction)
2203 {
2204     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2205     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
2206
2207     std::string rt = GPR(copy(rt_value));
2208     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2209
2210     return img::format("ADDIUPC %s, %s", rt, s);
2211 }
2212
2213
2214 /*
2215  *
2216  *
2217  *   3         2         1
2218  *  10987654321098765432109876543210
2219  *  001000               x1110000101
2220  *     rt -----
2221  *          rs -----
2222  *               rd -----
2223  */
2224 std::string NMD::ADDIUPC_48_(uint64 instruction)
2225 {
2226     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
2227     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
2228
2229     std::string rt = GPR(copy(rt_value));
2230     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
2231
2232     return img::format("ADDIUPC %s, %s", rt, s);
2233 }
2234
2235
2236 /*
2237  * [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
2238  *
2239  *   3         2         1
2240  *  10987654321098765432109876543210
2241  *  001000               00000001101
2242  *     rt -----
2243  *          rs -----
2244  *               rd -----
2245  */
2246 std::string NMD::ADDQ_PH(uint64 instruction)
2247 {
2248     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2249     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2250     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2251
2252     std::string rd = GPR(copy(rd_value));
2253     std::string rs = GPR(copy(rs_value));
2254     std::string rt = GPR(copy(rt_value));
2255
2256     return img::format("ADDQ.PH %s, %s, %s", rd, rs, rt);
2257 }
2258
2259
2260 /*
2261  * [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
2262  *         saturation
2263  *
2264  *   3         2         1
2265  *  10987654321098765432109876543210
2266  *  001000               10000001101
2267  *     rt -----
2268  *          rs -----
2269  *               rd -----
2270  */
2271 std::string NMD::ADDQ_S_PH(uint64 instruction)
2272 {
2273     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2274     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2275     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2276
2277     std::string rd = GPR(copy(rd_value));
2278     std::string rs = GPR(copy(rs_value));
2279     std::string rt = GPR(copy(rt_value));
2280
2281     return img::format("ADDQ_S.PH %s, %s, %s", rd, rs, rt);
2282 }
2283
2284
2285 /*
2286  * [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
2287  *
2288  *   3         2         1
2289  *  10987654321098765432109876543210
2290  *  001000               x1100000101
2291  *     rt -----
2292  *          rs -----
2293  *               rd -----
2294  */
2295 std::string NMD::ADDQ_S_W(uint64 instruction)
2296 {
2297     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2298     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2299     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2300
2301     std::string rd = GPR(copy(rd_value));
2302     std::string rs = GPR(copy(rs_value));
2303     std::string rt = GPR(copy(rt_value));
2304
2305     return img::format("ADDQ_S.W %s, %s, %s", rd, rs, rt);
2306 }
2307
2308
2309 /*
2310  * [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
2311  *         right to halve results
2312  *
2313  *   3         2         1
2314  *  10987654321098765432109876543210
2315  *  001000               00001001101
2316  *     rt -----
2317  *          rs -----
2318  *               rd -----
2319  */
2320 std::string NMD::ADDQH_PH(uint64 instruction)
2321 {
2322     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2323     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2324     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2325
2326     std::string rd = GPR(copy(rd_value));
2327     std::string rs = GPR(copy(rs_value));
2328     std::string rt = GPR(copy(rt_value));
2329
2330     return img::format("ADDQH.PH %s, %s, %s", rd, rs, rt);
2331 }
2332
2333
2334 /*
2335  * [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
2336  *         right to halve results with rounding
2337  *
2338  *   3         2         1
2339  *  10987654321098765432109876543210
2340  *  001000               10001001101
2341  *     rt -----
2342  *          rs -----
2343  *               rd -----
2344  */
2345 std::string NMD::ADDQH_R_PH(uint64 instruction)
2346 {
2347     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2348     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2349     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2350
2351     std::string rd = GPR(copy(rd_value));
2352     std::string rs = GPR(copy(rs_value));
2353     std::string rt = GPR(copy(rt_value));
2354
2355     return img::format("ADDQH_R.PH %s, %s, %s", rd, rs, rt);
2356 }
2357
2358
2359 /*
2360  * [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
2361  *         results with rounding
2362  *
2363  *   3         2         1
2364  *  10987654321098765432109876543210
2365  *  001000               00010001101
2366  *     rt -----
2367  *          rs -----
2368  *               rd -----
2369  */
2370 std::string NMD::ADDQH_R_W(uint64 instruction)
2371 {
2372     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2373     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2374     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2375
2376     std::string rd = GPR(copy(rd_value));
2377     std::string rs = GPR(copy(rs_value));
2378     std::string rt = GPR(copy(rt_value));
2379
2380     return img::format("ADDQH_R.W %s, %s, %s", rd, rs, rt);
2381 }
2382
2383
2384 /*
2385  * [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
2386  *         results
2387  *
2388  *   3         2         1
2389  *  10987654321098765432109876543210
2390  *  001000               10010001101
2391  *     rt -----
2392  *          rs -----
2393  *               rd -----
2394  */
2395 std::string NMD::ADDQH_W(uint64 instruction)
2396 {
2397     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2398     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2399     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2400
2401     std::string rd = GPR(copy(rd_value));
2402     std::string rs = GPR(copy(rs_value));
2403     std::string rt = GPR(copy(rt_value));
2404
2405     return img::format("ADDQH.W %s, %s, %s", rd, rs, rt);
2406 }
2407
2408
2409 /*
2410  * [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
2411  *
2412  *   3         2         1
2413  *  10987654321098765432109876543210
2414  *  001000               x1110000101
2415  *     rt -----
2416  *          rs -----
2417  *               rd -----
2418  */
2419 std::string NMD::ADDSC(uint64 instruction)
2420 {
2421     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2422     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2423     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2424
2425     std::string rd = GPR(copy(rd_value));
2426     std::string rs = GPR(copy(rs_value));
2427     std::string rt = GPR(copy(rt_value));
2428
2429     return img::format("ADDSC %s, %s, %s", rd, rs, rt);
2430 }
2431
2432
2433 /*
2434  * ADDU[16] rd3, rs3, rt3 -
2435  *
2436  *  5432109876543210
2437  *  101100         0
2438  *    rt3 ---
2439  *       rs3 ---
2440  *          rd3 ---
2441  */
2442 std::string NMD::ADDU_16_(uint64 instruction)
2443 {
2444     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2445     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2446     uint64 rd3_value = extract_rd3_3_2_1(instruction);
2447
2448     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2449     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2450     std::string rd3 = GPR(decode_gpr_gpr3(rd3_value));
2451
2452     return img::format("ADDU %s, %s, %s", rd3, rs3, rt3);
2453 }
2454
2455
2456 /*
2457  *
2458  *
2459  *   3         2         1
2460  *  10987654321098765432109876543210
2461  *  001000               x1110000101
2462  *     rt -----
2463  *          rs -----
2464  *               rd -----
2465  */
2466 std::string NMD::ADDU_32_(uint64 instruction)
2467 {
2468     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2469     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2470     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2471
2472     std::string rd = GPR(copy(rd_value));
2473     std::string rs = GPR(copy(rs_value));
2474     std::string rt = GPR(copy(rt_value));
2475
2476     return img::format("ADDU %s, %s, %s", rd, rs, rt);
2477 }
2478
2479
2480 /*
2481  *
2482  *
2483  *   3         2         1
2484  *  10987654321098765432109876543210
2485  *  001000               x1110000101
2486  *     rt -----
2487  *          rs -----
2488  *               rd -----
2489  */
2490 std::string NMD::ADDU_4X4_(uint64 instruction)
2491 {
2492     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
2493     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
2494
2495     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
2496     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
2497
2498     return img::format("ADDU %s, %s", rs4, rt4);
2499 }
2500
2501
2502 /*
2503  * [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
2504  *
2505  *   3         2         1
2506  *  10987654321098765432109876543210
2507  *  001000               00100001101
2508  *     rt -----
2509  *          rs -----
2510  *               rd -----
2511  */
2512 std::string NMD::ADDU_PH(uint64 instruction)
2513 {
2514     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2515     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2516     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2517
2518     std::string rd = GPR(copy(rd_value));
2519     std::string rs = GPR(copy(rs_value));
2520     std::string rt = GPR(copy(rt_value));
2521
2522     return img::format("ADDU.PH %s, %s, %s", rd, rs, rt);
2523 }
2524
2525
2526 /*
2527  * ADDU.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2528  *
2529  *   3         2         1
2530  *  10987654321098765432109876543210
2531  *  001000               00011001101
2532  *     rt -----
2533  *          rs -----
2534  *               rd -----
2535  */
2536 std::string NMD::ADDU_QB(uint64 instruction)
2537 {
2538     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2539     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2540     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2541
2542     std::string rd = GPR(copy(rd_value));
2543     std::string rs = GPR(copy(rs_value));
2544     std::string rt = GPR(copy(rt_value));
2545
2546     return img::format("ADDU.QB %s, %s, %s", rd, rs, rt);
2547 }
2548
2549
2550 /*
2551  * [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
2552  *         saturation
2553  *
2554  *   3         2         1
2555  *  10987654321098765432109876543210
2556  *  001000               10100001101
2557  *     rt -----
2558  *          rs -----
2559  *               rd -----
2560  */
2561 std::string NMD::ADDU_S_PH(uint64 instruction)
2562 {
2563     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2564     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2565     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2566
2567     std::string rd = GPR(copy(rd_value));
2568     std::string rs = GPR(copy(rs_value));
2569     std::string rt = GPR(copy(rt_value));
2570
2571     return img::format("ADDU_S.PH %s, %s, %s", rd, rs, rt);
2572 }
2573
2574
2575 /*
2576  * ADDU_S.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2577  *
2578  *   3         2         1
2579  *  10987654321098765432109876543210
2580  *  001000               10011001101
2581  *     rt -----
2582  *          rs -----
2583  *               rd -----
2584  */
2585 std::string NMD::ADDU_S_QB(uint64 instruction)
2586 {
2587     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2588     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2589     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2590
2591     std::string rd = GPR(copy(rd_value));
2592     std::string rs = GPR(copy(rs_value));
2593     std::string rt = GPR(copy(rt_value));
2594
2595     return img::format("ADDU_S.QB %s, %s, %s", rd, rs, rt);
2596 }
2597
2598
2599 /*
2600  * ADDUH.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2601  *                       to Halve Results
2602  *
2603  *   3         2         1
2604  *  10987654321098765432109876543210
2605  *  001000               00101001101
2606  *     rt -----
2607  *          rs -----
2608  *               rd -----
2609  */
2610 std::string NMD::ADDUH_QB(uint64 instruction)
2611 {
2612     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2613     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2614     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2615
2616     std::string rd = GPR(copy(rd_value));
2617     std::string rs = GPR(copy(rs_value));
2618     std::string rt = GPR(copy(rt_value));
2619
2620     return img::format("ADDUH.QB %s, %s, %s", rd, rs, rt);
2621 }
2622
2623
2624 /*
2625  * ADDUH_R.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2626  *                         to Halve Results
2627  *
2628  *   3         2         1
2629  *  10987654321098765432109876543210
2630  *  001000               10101001101
2631  *     rt -----
2632  *          rs -----
2633  *               rd -----
2634  */
2635 std::string NMD::ADDUH_R_QB(uint64 instruction)
2636 {
2637     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2638     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2639     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2640
2641     std::string rd = GPR(copy(rd_value));
2642     std::string rs = GPR(copy(rs_value));
2643     std::string rt = GPR(copy(rt_value));
2644
2645     return img::format("ADDUH_R.QB %s, %s, %s", rd, rs, rt);
2646 }
2647
2648 /*
2649  * ADDWC rd, rt, rs - Add Word with Carry Bit
2650  *
2651  *   3         2         1
2652  *  10987654321098765432109876543210
2653  *  001000               x1111000101
2654  *     rt -----
2655  *          rs -----
2656  *               rd -----
2657  */
2658 std::string NMD::ADDWC(uint64 instruction)
2659 {
2660     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2661     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2662     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2663
2664     std::string rd = GPR(copy(rd_value));
2665     std::string rs = GPR(copy(rs_value));
2666     std::string rt = GPR(copy(rt_value));
2667
2668     return img::format("ADDWC %s, %s, %s", rd, rs, rt);
2669 }
2670
2671
2672 /*
2673  *
2674  *
2675  *   3         2         1
2676  *  10987654321098765432109876543210
2677  *  001000               x1110000101
2678  *     rt -----
2679  *          rs -----
2680  *               rd -----
2681  */
2682 std::string NMD::ALUIPC(uint64 instruction)
2683 {
2684     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2685     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
2686
2687     std::string rt = GPR(copy(rt_value));
2688     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2689
2690     return img::format("ALUIPC %s, %%pcrel_hi(%s)", rt, s);
2691 }
2692
2693
2694 /*
2695  * AND[16] rt3, rs3 -
2696  *
2697  *  5432109876543210
2698  *  101100
2699  *    rt3 ---
2700  *       rs3 ---
2701  *           eu ----
2702  */
2703 std::string NMD::AND_16_(uint64 instruction)
2704 {
2705     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2706     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2707
2708     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2709     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2710
2711     return img::format("AND %s, %s", rs3, rt3);
2712 }
2713
2714
2715 /*
2716  *
2717  *
2718  *   3         2         1
2719  *  10987654321098765432109876543210
2720  *  001000               x1110000101
2721  *     rt -----
2722  *          rs -----
2723  *               rd -----
2724  */
2725 std::string NMD::AND_32_(uint64 instruction)
2726 {
2727     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2728     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2729     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2730
2731     std::string rd = GPR(copy(rd_value));
2732     std::string rs = GPR(copy(rs_value));
2733     std::string rt = GPR(copy(rt_value));
2734
2735     return img::format("AND %s, %s, %s", rd, rs, rt);
2736 }
2737
2738
2739 /*
2740  * ANDI rt, rs, u -
2741  *
2742  *  5432109876543210
2743  *  101100
2744  *    rt3 ---
2745  *       rs3 ---
2746  *           eu ----
2747  */
2748 std::string NMD::ANDI_16_(uint64 instruction)
2749 {
2750     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2751     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2752     uint64 eu_value = extract_eu_3_2_1_0(instruction);
2753
2754     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
2755     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
2756     std::string eu = IMMEDIATE(encode_eu_from_u_andi16(eu_value));
2757
2758     return img::format("ANDI %s, %s, %s", rt3, rs3, eu);
2759 }
2760
2761
2762 /*
2763  *
2764  *
2765  *   3         2         1
2766  *  10987654321098765432109876543210
2767  *  001000               x1110000101
2768  *     rt -----
2769  *          rs -----
2770  *               rd -----
2771  */
2772 std::string NMD::ANDI_32_(uint64 instruction)
2773 {
2774     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2775     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2776     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2777
2778     std::string rt = GPR(copy(rt_value));
2779     std::string rs = GPR(copy(rs_value));
2780     std::string u = IMMEDIATE(copy(u_value));
2781
2782     return img::format("ANDI %s, %s, %s", rt, rs, u);
2783 }
2784
2785
2786 /*
2787  *
2788  *
2789  *   3         2         1
2790  *  10987654321098765432109876543210
2791  *  001000               x1110000101
2792  *     rt -----
2793  *          rs -----
2794  *               rd -----
2795  */
2796 std::string NMD::APPEND(uint64 instruction)
2797 {
2798     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2799     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2800     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
2801
2802     std::string rt = GPR(copy(rt_value));
2803     std::string rs = GPR(copy(rs_value));
2804     std::string sa = IMMEDIATE(copy(sa_value));
2805
2806     return img::format("APPEND %s, %s, %s", rt, rs, sa);
2807 }
2808
2809
2810 /*
2811  *
2812  *
2813  *   3         2         1
2814  *  10987654321098765432109876543210
2815  *  001000               x1110000101
2816  *     rt -----
2817  *          rs -----
2818  *               rd -----
2819  */
2820 std::string NMD::ASET(uint64 instruction)
2821 {
2822     uint64 bit_value = extract_bit_23_22_21(instruction);
2823     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2824     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
2825
2826     std::string bit = IMMEDIATE(copy(bit_value));
2827     std::string s = IMMEDIATE(copy(s_value));
2828     std::string rs = GPR(copy(rs_value));
2829
2830     return img::format("ASET %s, %s(%s)", bit, s, rs);
2831 }
2832
2833
2834 /*
2835  *
2836  *
2837  *   3         2         1
2838  *  10987654321098765432109876543210
2839  *  001000               x1110000101
2840  *     rt -----
2841  *          rs -----
2842  *               rd -----
2843  */
2844 std::string NMD::BALC_16_(uint64 instruction)
2845 {
2846     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2847
2848     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
2849
2850     return img::format("BALC %s", s);
2851 }
2852
2853
2854 /*
2855  *
2856  *
2857  *   3         2         1
2858  *  10987654321098765432109876543210
2859  *  001000               x1110000101
2860  *     rt -----
2861  *          rs -----
2862  *               rd -----
2863  */
2864 std::string NMD::BALC_32_(uint64 instruction)
2865 {
2866     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2867
2868     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2869
2870     return img::format("BALC %s", s);
2871 }
2872
2873
2874 /*
2875  *
2876  *
2877  *   3         2         1
2878  *  10987654321098765432109876543210
2879  *  001000               x1110000101
2880  *     rt -----
2881  *          rs -----
2882  *               rd -----
2883  */
2884 std::string NMD::BALRSC(uint64 instruction)
2885 {
2886     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2887     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2888
2889     std::string rt = GPR(copy(rt_value));
2890     std::string rs = GPR(copy(rs_value));
2891
2892     return img::format("BALRSC %s, %s", rt, rs);
2893 }
2894
2895
2896 /*
2897  *
2898  *
2899  *   3         2         1
2900  *  10987654321098765432109876543210
2901  *  001000               x1110000101
2902  *     rt -----
2903  *          rs -----
2904  *               rd -----
2905  */
2906 std::string NMD::BBEQZC(uint64 instruction)
2907 {
2908     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2909     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2910     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2911
2912     std::string rt = GPR(copy(rt_value));
2913     std::string bit = IMMEDIATE(copy(bit_value));
2914     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2915
2916     return img::format("BBEQZC %s, %s, %s", rt, bit, s);
2917 }
2918
2919
2920 /*
2921  *
2922  *
2923  *   3         2         1
2924  *  10987654321098765432109876543210
2925  *  001000               x1110000101
2926  *     rt -----
2927  *          rs -----
2928  *               rd -----
2929  */
2930 std::string NMD::BBNEZC(uint64 instruction)
2931 {
2932     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2933     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2934     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2935
2936     std::string rt = GPR(copy(rt_value));
2937     std::string bit = IMMEDIATE(copy(bit_value));
2938     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2939
2940     return img::format("BBNEZC %s, %s, %s", rt, bit, s);
2941 }
2942
2943
2944 /*
2945  *
2946  *
2947  *   3         2         1
2948  *  10987654321098765432109876543210
2949  *  001000               x1110000101
2950  *     rt -----
2951  *          rs -----
2952  *               rd -----
2953  */
2954 std::string NMD::BC_16_(uint64 instruction)
2955 {
2956     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2957
2958     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
2959
2960     return img::format("BC %s", s);
2961 }
2962
2963
2964 /*
2965  *
2966  *
2967  *   3         2         1
2968  *  10987654321098765432109876543210
2969  *  001000               x1110000101
2970  *     rt -----
2971  *          rs -----
2972  *               rd -----
2973  */
2974 std::string NMD::BC_32_(uint64 instruction)
2975 {
2976     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2977
2978     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
2979
2980     return img::format("BC %s", s);
2981 }
2982
2983
2984 /*
2985  *
2986  *
2987  *   3         2         1
2988  *  10987654321098765432109876543210
2989  *  001000               x1110000101
2990  *     rt -----
2991  *          rs -----
2992  *               rd -----
2993  */
2994 std::string NMD::BC1EQZC(uint64 instruction)
2995 {
2996     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
2997     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2998
2999     std::string ft = FPR(copy(ft_value));
3000     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3001
3002     return img::format("BC1EQZC %s, %s", ft, s);
3003 }
3004
3005
3006 /*
3007  *
3008  *
3009  *   3         2         1
3010  *  10987654321098765432109876543210
3011  *  001000               x1110000101
3012  *     rt -----
3013  *          rs -----
3014  *               rd -----
3015  */
3016 std::string NMD::BC1NEZC(uint64 instruction)
3017 {
3018     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3019     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3020
3021     std::string ft = FPR(copy(ft_value));
3022     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3023
3024     return img::format("BC1NEZC %s, %s", ft, s);
3025 }
3026
3027
3028 /*
3029  *
3030  *
3031  *   3         2         1
3032  *  10987654321098765432109876543210
3033  *  001000               x1110000101
3034  *     rt -----
3035  *          rs -----
3036  *               rd -----
3037  */
3038 std::string NMD::BC2EQZC(uint64 instruction)
3039 {
3040     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
3041     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3042
3043     std::string ct = CPR(copy(ct_value));
3044     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3045
3046     return img::format("BC2EQZC %s, %s", ct, s);
3047 }
3048
3049
3050 /*
3051  *
3052  *
3053  *   3         2         1
3054  *  10987654321098765432109876543210
3055  *  001000               x1110000101
3056  *     rt -----
3057  *          rs -----
3058  *               rd -----
3059  */
3060 std::string NMD::BC2NEZC(uint64 instruction)
3061 {
3062     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
3063     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3064
3065     std::string ct = CPR(copy(ct_value));
3066     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3067
3068     return img::format("BC2NEZC %s, %s", ct, s);
3069 }
3070
3071
3072 /*
3073  *
3074  *
3075  *   3         2         1
3076  *  10987654321098765432109876543210
3077  *  001000               x1110000101
3078  *     rt -----
3079  *          rs -----
3080  *               rd -----
3081  */
3082 std::string NMD::BEQC_16_(uint64 instruction)
3083 {
3084     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3085     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3086     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
3087
3088     std::string rs3 = GPR(encode_rs3_and_check_rs3_lt_rt3(rs3_value));
3089     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3090     std::string u = ADDRESS(encode_u_from_address(u_value), 2);
3091
3092     return img::format("BEQC %s, %s, %s", rs3, rt3, u);
3093 }
3094
3095
3096 /*
3097  *
3098  *
3099  *   3         2         1
3100  *  10987654321098765432109876543210
3101  *  001000               x1110000101
3102  *     rt -----
3103  *          rs -----
3104  *               rd -----
3105  */
3106 std::string NMD::BEQC_32_(uint64 instruction)
3107 {
3108     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3109     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3110     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3111
3112     std::string rs = GPR(copy(rs_value));
3113     std::string rt = GPR(copy(rt_value));
3114     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3115
3116     return img::format("BEQC %s, %s, %s", rs, rt, s);
3117 }
3118
3119
3120 /*
3121  *
3122  *
3123  *   3         2         1
3124  *  10987654321098765432109876543210
3125  *  001000               x1110000101
3126  *     rt -----
3127  *          rs -----
3128  *               rd -----
3129  */
3130 std::string NMD::BEQIC(uint64 instruction)
3131 {
3132     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3133     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3134     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3135
3136     std::string rt = GPR(copy(rt_value));
3137     std::string u = IMMEDIATE(copy(u_value));
3138     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3139
3140     return img::format("BEQIC %s, %s, %s", rt, u, s);
3141 }
3142
3143
3144 /*
3145  *
3146  *
3147  *   3         2         1
3148  *  10987654321098765432109876543210
3149  *  001000               x1110000101
3150  *     rt -----
3151  *          rs -----
3152  *               rd -----
3153  */
3154 std::string NMD::BEQZC_16_(uint64 instruction)
3155 {
3156     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3157     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
3158
3159     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3160     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
3161
3162     return img::format("BEQZC %s, %s", rt3, s);
3163 }
3164
3165
3166 /*
3167  *
3168  *
3169  *   3         2         1
3170  *  10987654321098765432109876543210
3171  *  001000               x1110000101
3172  *     rt -----
3173  *          rs -----
3174  *               rd -----
3175  */
3176 std::string NMD::BGEC(uint64 instruction)
3177 {
3178     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3179     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3180     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3181
3182     std::string rs = GPR(copy(rs_value));
3183     std::string rt = GPR(copy(rt_value));
3184     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3185
3186     return img::format("BGEC %s, %s, %s", rs, rt, s);
3187 }
3188
3189
3190 /*
3191  *
3192  *
3193  *   3         2         1
3194  *  10987654321098765432109876543210
3195  *  001000               x1110000101
3196  *     rt -----
3197  *          rs -----
3198  *               rd -----
3199  */
3200 std::string NMD::BGEIC(uint64 instruction)
3201 {
3202     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3203     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3204     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3205
3206     std::string rt = GPR(copy(rt_value));
3207     std::string u = IMMEDIATE(copy(u_value));
3208     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3209
3210     return img::format("BGEIC %s, %s, %s", rt, u, s);
3211 }
3212
3213
3214 /*
3215  *
3216  *
3217  *   3         2         1
3218  *  10987654321098765432109876543210
3219  *  001000               x1110000101
3220  *     rt -----
3221  *          rs -----
3222  *               rd -----
3223  */
3224 std::string NMD::BGEIUC(uint64 instruction)
3225 {
3226     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3227     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3228     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3229
3230     std::string rt = GPR(copy(rt_value));
3231     std::string u = IMMEDIATE(copy(u_value));
3232     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3233
3234     return img::format("BGEIUC %s, %s, %s", rt, u, s);
3235 }
3236
3237
3238 /*
3239  *
3240  *
3241  *   3         2         1
3242  *  10987654321098765432109876543210
3243  *  001000               x1110000101
3244  *     rt -----
3245  *          rs -----
3246  *               rd -----
3247  */
3248 std::string NMD::BGEUC(uint64 instruction)
3249 {
3250     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3251     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3252     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3253
3254     std::string rs = GPR(copy(rs_value));
3255     std::string rt = GPR(copy(rt_value));
3256     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3257
3258     return img::format("BGEUC %s, %s, %s", rs, rt, s);
3259 }
3260
3261
3262 /*
3263  *
3264  *
3265  *   3         2         1
3266  *  10987654321098765432109876543210
3267  *  001000               x1110000101
3268  *     rt -----
3269  *          rs -----
3270  *               rd -----
3271  */
3272 std::string NMD::BLTC(uint64 instruction)
3273 {
3274     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3275     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3276     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3277
3278     std::string rs = GPR(copy(rs_value));
3279     std::string rt = GPR(copy(rt_value));
3280     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3281
3282     return img::format("BLTC %s, %s, %s", rs, rt, s);
3283 }
3284
3285
3286 /*
3287  *
3288  *
3289  *   3         2         1
3290  *  10987654321098765432109876543210
3291  *  001000               x1110000101
3292  *     rt -----
3293  *          rs -----
3294  *               rd -----
3295  */
3296 std::string NMD::BLTIC(uint64 instruction)
3297 {
3298     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3299     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3300     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3301
3302     std::string rt = GPR(copy(rt_value));
3303     std::string u = IMMEDIATE(copy(u_value));
3304     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3305
3306     return img::format("BLTIC %s, %s, %s", rt, u, s);
3307 }
3308
3309
3310 /*
3311  *
3312  *
3313  *   3         2         1
3314  *  10987654321098765432109876543210
3315  *  001000               x1110000101
3316  *     rt -----
3317  *          rs -----
3318  *               rd -----
3319  */
3320 std::string NMD::BLTIUC(uint64 instruction)
3321 {
3322     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3323     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3324     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3325
3326     std::string rt = GPR(copy(rt_value));
3327     std::string u = IMMEDIATE(copy(u_value));
3328     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3329
3330     return img::format("BLTIUC %s, %s, %s", rt, u, s);
3331 }
3332
3333
3334 /*
3335  *
3336  *
3337  *   3         2         1
3338  *  10987654321098765432109876543210
3339  *  001000               x1110000101
3340  *     rt -----
3341  *          rs -----
3342  *               rd -----
3343  */
3344 std::string NMD::BLTUC(uint64 instruction)
3345 {
3346     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3347     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3348     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3349
3350     std::string rs = GPR(copy(rs_value));
3351     std::string rt = GPR(copy(rt_value));
3352     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3353
3354     return img::format("BLTUC %s, %s, %s", rs, rt, s);
3355 }
3356
3357
3358 /*
3359  *
3360  *
3361  *   3         2         1
3362  *  10987654321098765432109876543210
3363  *  001000               x1110000101
3364  *     rt -----
3365  *          rs -----
3366  *               rd -----
3367  */
3368 std::string NMD::BNEC_16_(uint64 instruction)
3369 {
3370     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3371     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3372     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
3373
3374     std::string rs3 = GPR(encode_rs3_and_check_rs3_ge_rt3(rs3_value));
3375     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3376     std::string u = ADDRESS(encode_u_from_address(u_value), 2);
3377
3378     return img::format("BNEC %s, %s, %s", rs3, rt3, u);
3379 }
3380
3381
3382 /*
3383  *
3384  *
3385  *   3         2         1
3386  *  10987654321098765432109876543210
3387  *  001000               x1110000101
3388  *     rt -----
3389  *          rs -----
3390  *               rd -----
3391  */
3392 std::string NMD::BNEC_32_(uint64 instruction)
3393 {
3394     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3395     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3396     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3397
3398     std::string rs = GPR(copy(rs_value));
3399     std::string rt = GPR(copy(rt_value));
3400     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3401
3402     return img::format("BNEC %s, %s, %s", rs, rt, s);
3403 }
3404
3405
3406 /*
3407  *
3408  *
3409  *   3         2         1
3410  *  10987654321098765432109876543210
3411  *  001000               x1110000101
3412  *     rt -----
3413  *          rs -----
3414  *               rd -----
3415  */
3416 std::string NMD::BNEIC(uint64 instruction)
3417 {
3418     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3419     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3420     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3421
3422     std::string rt = GPR(copy(rt_value));
3423     std::string u = IMMEDIATE(copy(u_value));
3424     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3425
3426     return img::format("BNEIC %s, %s, %s", rt, u, s);
3427 }
3428
3429
3430 /*
3431  *
3432  *
3433  *   3         2         1
3434  *  10987654321098765432109876543210
3435  *  001000               x1110000101
3436  *     rt -----
3437  *          rs -----
3438  *               rd -----
3439  */
3440 std::string NMD::BNEZC_16_(uint64 instruction)
3441 {
3442     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3443     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
3444
3445     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
3446     std::string s = ADDRESS(encode_s_from_address(s_value), 2);
3447
3448     return img::format("BNEZC %s, %s", rt3, s);
3449 }
3450
3451
3452 /*
3453  * [DSP] BPOSGE32C offset - Branch on greater than or equal to value 32 in
3454  *   DSPControl Pos field
3455  *
3456  *   3         2         1
3457  *  10987654321098765432109876543210
3458  *  100010xxxxx0010001
3459  *            s[13:1] -------------
3460  *                           s[14] -
3461  */
3462 std::string NMD::BPOSGE32C(uint64 instruction)
3463 {
3464     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3465
3466     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
3467
3468     return img::format("BPOSGE32C %s", s);
3469 }
3470
3471
3472 /*
3473  *
3474  *
3475  *   3         2         1
3476  *  10987654321098765432109876543210
3477  *  001000               x1110000101
3478  *     rt -----
3479  *          rs -----
3480  *               rd -----
3481  */
3482 std::string NMD::BREAK_16_(uint64 instruction)
3483 {
3484     uint64 code_value = extract_code_2_1_0(instruction);
3485
3486     std::string code = IMMEDIATE(copy(code_value));
3487
3488     return img::format("BREAK %s", code);
3489 }
3490
3491
3492 /*
3493  * BREAK code - Break. Cause a Breakpoint exception
3494  *
3495  *   3         2         1
3496  *  10987654321098765432109876543210
3497  *  001000               x1110000101
3498  *     rt -----
3499  *          rs -----
3500  *               rd -----
3501  */
3502 std::string NMD::BREAK_32_(uint64 instruction)
3503 {
3504     uint64 code_value = extract_code_18_to_0(instruction);
3505
3506     std::string code = IMMEDIATE(copy(code_value));
3507
3508     return img::format("BREAK %s", code);
3509 }
3510
3511
3512 /*
3513  *
3514  *
3515  *   3         2         1
3516  *  10987654321098765432109876543210
3517  *  001000               x1110000101
3518  *     rt -----
3519  *          rs -----
3520  *               rd -----
3521  */
3522 std::string NMD::BRSC(uint64 instruction)
3523 {
3524     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3525
3526     std::string rs = GPR(copy(rs_value));
3527
3528     return img::format("BRSC %s", rs);
3529 }
3530
3531
3532 /*
3533  *
3534  *
3535  *   3         2         1
3536  *  10987654321098765432109876543210
3537  *  001000               x1110000101
3538  *     rt -----
3539  *          rs -----
3540  *               rd -----
3541  */
3542 std::string NMD::CACHE(uint64 instruction)
3543 {
3544     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3545     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3546     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3547
3548     std::string op = IMMEDIATE(copy(op_value));
3549     std::string s = IMMEDIATE(copy(s_value));
3550     std::string rs = GPR(copy(rs_value));
3551
3552     return img::format("CACHE %s, %s(%s)", op, s, rs);
3553 }
3554
3555
3556 /*
3557  *
3558  *
3559  *   3         2         1
3560  *  10987654321098765432109876543210
3561  *  001000               x1110000101
3562  *     rt -----
3563  *          rs -----
3564  *               rd -----
3565  */
3566 std::string NMD::CACHEE(uint64 instruction)
3567 {
3568     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3569     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3570     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3571
3572     std::string op = IMMEDIATE(copy(op_value));
3573     std::string s = IMMEDIATE(copy(s_value));
3574     std::string rs = GPR(copy(rs_value));
3575
3576     return img::format("CACHEE %s, %s(%s)", op, s, rs);
3577 }
3578
3579
3580 /*
3581  *
3582  *
3583  *   3         2         1
3584  *  10987654321098765432109876543210
3585  *  001000               x1110000101
3586  *     rt -----
3587  *          rs -----
3588  *               rd -----
3589  */
3590 std::string NMD::CEIL_L_D(uint64 instruction)
3591 {
3592     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3593     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3594
3595     std::string ft = FPR(copy(ft_value));
3596     std::string fs = FPR(copy(fs_value));
3597
3598     return img::format("CEIL.L.D %s, %s", ft, fs);
3599 }
3600
3601
3602 /*
3603  *
3604  *
3605  *   3         2         1
3606  *  10987654321098765432109876543210
3607  *  001000               x1110000101
3608  *     rt -----
3609  *          rs -----
3610  *               rd -----
3611  */
3612 std::string NMD::CEIL_L_S(uint64 instruction)
3613 {
3614     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3615     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3616
3617     std::string ft = FPR(copy(ft_value));
3618     std::string fs = FPR(copy(fs_value));
3619
3620     return img::format("CEIL.L.S %s, %s", ft, fs);
3621 }
3622
3623
3624 /*
3625  *
3626  *
3627  *   3         2         1
3628  *  10987654321098765432109876543210
3629  *  001000               x1110000101
3630  *     rt -----
3631  *          rs -----
3632  *               rd -----
3633  */
3634 std::string NMD::CEIL_W_D(uint64 instruction)
3635 {
3636     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3637     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3638
3639     std::string ft = FPR(copy(ft_value));
3640     std::string fs = FPR(copy(fs_value));
3641
3642     return img::format("CEIL.W.D %s, %s", ft, fs);
3643 }
3644
3645
3646 /*
3647  *
3648  *
3649  *   3         2         1
3650  *  10987654321098765432109876543210
3651  *  001000               x1110000101
3652  *     rt -----
3653  *          rs -----
3654  *               rd -----
3655  */
3656 std::string NMD::CEIL_W_S(uint64 instruction)
3657 {
3658     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3659     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3660
3661     std::string ft = FPR(copy(ft_value));
3662     std::string fs = FPR(copy(fs_value));
3663
3664     return img::format("CEIL.W.S %s, %s", ft, fs);
3665 }
3666
3667
3668 /*
3669  *
3670  *
3671  *   3         2         1
3672  *  10987654321098765432109876543210
3673  *  001000               x1110000101
3674  *     rt -----
3675  *          rs -----
3676  *               rd -----
3677  */
3678 std::string NMD::CFC1(uint64 instruction)
3679 {
3680     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3681     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3682
3683     std::string rt = GPR(copy(rt_value));
3684     std::string cs = CPR(copy(cs_value));
3685
3686     return img::format("CFC1 %s, %s", rt, cs);
3687 }
3688
3689
3690 /*
3691  *
3692  *
3693  *   3         2         1
3694  *  10987654321098765432109876543210
3695  *  001000               x1110000101
3696  *     rt -----
3697  *          rs -----
3698  *               rd -----
3699  */
3700 std::string NMD::CFC2(uint64 instruction)
3701 {
3702     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3703     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3704
3705     std::string rt = GPR(copy(rt_value));
3706     std::string cs = CPR(copy(cs_value));
3707
3708     return img::format("CFC2 %s, %s", rt, cs);
3709 }
3710
3711
3712 /*
3713  *
3714  *
3715  *   3         2         1
3716  *  10987654321098765432109876543210
3717  *  001000               x1110000101
3718  *     rt -----
3719  *          rs -----
3720  *               rd -----
3721  */
3722 std::string NMD::CLASS_D(uint64 instruction)
3723 {
3724     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3725     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3726
3727     std::string ft = FPR(copy(ft_value));
3728     std::string fs = FPR(copy(fs_value));
3729
3730     return img::format("CLASS.D %s, %s", ft, fs);
3731 }
3732
3733
3734 /*
3735  *
3736  *
3737  *   3         2         1
3738  *  10987654321098765432109876543210
3739  *  001000               x1110000101
3740  *     rt -----
3741  *          rs -----
3742  *               rd -----
3743  */
3744 std::string NMD::CLASS_S(uint64 instruction)
3745 {
3746     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3747     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3748
3749     std::string ft = FPR(copy(ft_value));
3750     std::string fs = FPR(copy(fs_value));
3751
3752     return img::format("CLASS.S %s, %s", ft, fs);
3753 }
3754
3755
3756 /*
3757  *
3758  *
3759  *   3         2         1
3760  *  10987654321098765432109876543210
3761  *  001000               x1110000101
3762  *     rt -----
3763  *          rs -----
3764  *               rd -----
3765  */
3766 std::string NMD::CLO(uint64 instruction)
3767 {
3768     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3769     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3770
3771     std::string rt = GPR(copy(rt_value));
3772     std::string rs = GPR(copy(rs_value));
3773
3774     return img::format("CLO %s, %s", rt, rs);
3775 }
3776
3777
3778 /*
3779  *
3780  *
3781  *   3         2         1
3782  *  10987654321098765432109876543210
3783  *  001000               x1110000101
3784  *     rt -----
3785  *          rs -----
3786  *               rd -----
3787  */
3788 std::string NMD::CLZ(uint64 instruction)
3789 {
3790     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3791     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3792
3793     std::string rt = GPR(copy(rt_value));
3794     std::string rs = GPR(copy(rs_value));
3795
3796     return img::format("CLZ %s, %s", rt, rs);
3797 }
3798
3799
3800 /*
3801  *
3802  *
3803  *   3         2         1
3804  *  10987654321098765432109876543210
3805  *  001000               x1110000101
3806  *     rt -----
3807  *          rs -----
3808  *               rd -----
3809  */
3810 std::string NMD::CMP_AF_D(uint64 instruction)
3811 {
3812     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3813     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3814     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3815
3816     std::string fd = FPR(copy(fd_value));
3817     std::string fs = FPR(copy(fs_value));
3818     std::string ft = FPR(copy(ft_value));
3819
3820     return img::format("CMP.AF.D %s, %s, %s", fd, fs, ft);
3821 }
3822
3823
3824 /*
3825  *
3826  *
3827  *   3         2         1
3828  *  10987654321098765432109876543210
3829  *  001000               x1110000101
3830  *     rt -----
3831  *          rs -----
3832  *               rd -----
3833  */
3834 std::string NMD::CMP_AF_S(uint64 instruction)
3835 {
3836     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3837     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3838     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3839
3840     std::string fd = FPR(copy(fd_value));
3841     std::string fs = FPR(copy(fs_value));
3842     std::string ft = FPR(copy(ft_value));
3843
3844     return img::format("CMP.AF.S %s, %s, %s", fd, fs, ft);
3845 }
3846
3847
3848 /*
3849  *
3850  *
3851  *   3         2         1
3852  *  10987654321098765432109876543210
3853  *  001000               x1110000101
3854  *     rt -----
3855  *          rs -----
3856  *               rd -----
3857  */
3858 std::string NMD::CMP_EQ_D(uint64 instruction)
3859 {
3860     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3861     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3862     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3863
3864     std::string fd = FPR(copy(fd_value));
3865     std::string fs = FPR(copy(fs_value));
3866     std::string ft = FPR(copy(ft_value));
3867
3868     return img::format("CMP.EQ.D %s, %s, %s", fd, fs, ft);
3869 }
3870
3871
3872 /*
3873  * [DSP] CMP.EQ.PH rs, rt - Compare vectors of signed integer halfword values
3874  *
3875  *   3         2         1
3876  *  10987654321098765432109876543210
3877  *  001000          xxxxxx0000000101
3878  *     rt -----
3879  *          rs -----
3880  */
3881 std::string NMD::CMP_EQ_PH(uint64 instruction)
3882 {
3883     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3884     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3885
3886     std::string rs = GPR(copy(rs_value));
3887     std::string rt = GPR(copy(rt_value));
3888
3889     return img::format("CMP.EQ.PH %s, %s", rs, rt);
3890 }
3891
3892
3893 /*
3894  *
3895  *
3896  *   3         2         1
3897  *  10987654321098765432109876543210
3898  *  001000               x1110000101
3899  *     rt -----
3900  *          rs -----
3901  *               rd -----
3902  */
3903 std::string NMD::CMP_EQ_S(uint64 instruction)
3904 {
3905     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3906     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3907     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3908
3909     std::string fd = FPR(copy(fd_value));
3910     std::string fs = FPR(copy(fs_value));
3911     std::string ft = FPR(copy(ft_value));
3912
3913     return img::format("CMP.EQ.S %s, %s, %s", fd, fs, ft);
3914 }
3915
3916
3917 /*
3918  *
3919  *
3920  *   3         2         1
3921  *  10987654321098765432109876543210
3922  *  001000               x1110000101
3923  *     rt -----
3924  *          rs -----
3925  *               rd -----
3926  */
3927 std::string NMD::CMP_LE_D(uint64 instruction)
3928 {
3929     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3930     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3931     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3932
3933     std::string fd = FPR(copy(fd_value));
3934     std::string fs = FPR(copy(fs_value));
3935     std::string ft = FPR(copy(ft_value));
3936
3937     return img::format("CMP.LE.D %s, %s, %s", fd, fs, ft);
3938 }
3939
3940
3941 /*
3942  * [DSP] CMP.LE.PH rs, rt - Compare vectors of signed integer halfword values
3943  *
3944  *   3         2         1
3945  *  10987654321098765432109876543210
3946  *  001000          xxxxxx0010000101
3947  *     rt -----
3948  *          rs -----
3949  */
3950 std::string NMD::CMP_LE_PH(uint64 instruction)
3951 {
3952     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3953     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3954
3955     std::string rs = GPR(copy(rs_value));
3956     std::string rt = GPR(copy(rt_value));
3957
3958     return img::format("CMP.LE.PH %s, %s", rs, rt);
3959 }
3960
3961
3962 /*
3963  *
3964  *
3965  *   3         2         1
3966  *  10987654321098765432109876543210
3967  *  001000               x1110000101
3968  *     rt -----
3969  *          rs -----
3970  *               rd -----
3971  */
3972 std::string NMD::CMP_LE_S(uint64 instruction)
3973 {
3974     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3975     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3976     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3977
3978     std::string fd = FPR(copy(fd_value));
3979     std::string fs = FPR(copy(fs_value));
3980     std::string ft = FPR(copy(ft_value));
3981
3982     return img::format("CMP.LE.S %s, %s, %s", fd, fs, ft);
3983 }
3984
3985
3986 /*
3987  *
3988  *
3989  *   3         2         1
3990  *  10987654321098765432109876543210
3991  *  001000               x1110000101
3992  *     rt -----
3993  *          rs -----
3994  *               rd -----
3995  */
3996 std::string NMD::CMP_LT_D(uint64 instruction)
3997 {
3998     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3999     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4000     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4001
4002     std::string fd = FPR(copy(fd_value));
4003     std::string fs = FPR(copy(fs_value));
4004     std::string ft = FPR(copy(ft_value));
4005
4006     return img::format("CMP.LT.D %s, %s, %s", fd, fs, ft);
4007 }
4008
4009
4010 /*
4011  * [DSP] CMP.LT.PH rs, rt - Compare vectors of signed integer halfword values
4012  *
4013  *   3         2         1
4014  *  10987654321098765432109876543210
4015  *  001000          xxxxxx0001000101
4016  *     rt -----
4017  *          rs -----
4018  */
4019 std::string NMD::CMP_LT_PH(uint64 instruction)
4020 {
4021     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4022     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4023
4024     std::string rs = GPR(copy(rs_value));
4025     std::string rt = GPR(copy(rt_value));
4026
4027     return img::format("CMP.LT.PH %s, %s", rs, rt);
4028 }
4029
4030
4031 /*
4032  *
4033  *
4034  *   3         2         1
4035  *  10987654321098765432109876543210
4036  *  001000               x1110000101
4037  *     rt -----
4038  *          rs -----
4039  *               rd -----
4040  */
4041 std::string NMD::CMP_LT_S(uint64 instruction)
4042 {
4043     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4044     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4045     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4046
4047     std::string fd = FPR(copy(fd_value));
4048     std::string fs = FPR(copy(fs_value));
4049     std::string ft = FPR(copy(ft_value));
4050
4051     return img::format("CMP.LT.S %s, %s, %s", fd, fs, ft);
4052 }
4053
4054
4055 /*
4056  *
4057  *
4058  *   3         2         1
4059  *  10987654321098765432109876543210
4060  *  001000               x1110000101
4061  *     rt -----
4062  *          rs -----
4063  *               rd -----
4064  */
4065 std::string NMD::CMP_NE_D(uint64 instruction)
4066 {
4067     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4068     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4069     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4070
4071     std::string fd = FPR(copy(fd_value));
4072     std::string fs = FPR(copy(fs_value));
4073     std::string ft = FPR(copy(ft_value));
4074
4075     return img::format("CMP.NE.D %s, %s, %s", fd, fs, ft);
4076 }
4077
4078
4079 /*
4080  *
4081  *
4082  *   3         2         1
4083  *  10987654321098765432109876543210
4084  *  001000               x1110000101
4085  *     rt -----
4086  *          rs -----
4087  *               rd -----
4088  */
4089 std::string NMD::CMP_NE_S(uint64 instruction)
4090 {
4091     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4092     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4093     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4094
4095     std::string fd = FPR(copy(fd_value));
4096     std::string fs = FPR(copy(fs_value));
4097     std::string ft = FPR(copy(ft_value));
4098
4099     return img::format("CMP.NE.S %s, %s, %s", fd, fs, ft);
4100 }
4101
4102
4103 /*
4104  *
4105  *
4106  *   3         2         1
4107  *  10987654321098765432109876543210
4108  *  001000               x1110000101
4109  *     rt -----
4110  *          rs -----
4111  *               rd -----
4112  */
4113 std::string NMD::CMP_OR_D(uint64 instruction)
4114 {
4115     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4116     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4117     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4118
4119     std::string fd = FPR(copy(fd_value));
4120     std::string fs = FPR(copy(fs_value));
4121     std::string ft = FPR(copy(ft_value));
4122
4123     return img::format("CMP.OR.D %s, %s, %s", fd, fs, ft);
4124 }
4125
4126
4127 /*
4128  *
4129  *
4130  *   3         2         1
4131  *  10987654321098765432109876543210
4132  *  001000               x1110000101
4133  *     rt -----
4134  *          rs -----
4135  *               rd -----
4136  */
4137 std::string NMD::CMP_OR_S(uint64 instruction)
4138 {
4139     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4140     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4141     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4142
4143     std::string fd = FPR(copy(fd_value));
4144     std::string fs = FPR(copy(fs_value));
4145     std::string ft = FPR(copy(ft_value));
4146
4147     return img::format("CMP.OR.S %s, %s, %s", fd, fs, ft);
4148 }
4149
4150
4151 /*
4152  *
4153  *
4154  *   3         2         1
4155  *  10987654321098765432109876543210
4156  *  001000               x1110000101
4157  *     rt -----
4158  *          rs -----
4159  *               rd -----
4160  */
4161 std::string NMD::CMP_SAF_D(uint64 instruction)
4162 {
4163     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4164     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4165     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4166
4167     std::string fd = FPR(copy(fd_value));
4168     std::string fs = FPR(copy(fs_value));
4169     std::string ft = FPR(copy(ft_value));
4170
4171     return img::format("CMP.SAF.D %s, %s, %s", fd, fs, ft);
4172 }
4173
4174
4175 /*
4176  *
4177  *
4178  *   3         2         1
4179  *  10987654321098765432109876543210
4180  *  001000               x1110000101
4181  *     rt -----
4182  *          rs -----
4183  *               rd -----
4184  */
4185 std::string NMD::CMP_SAF_S(uint64 instruction)
4186 {
4187     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4188     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4189     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4190
4191     std::string fd = FPR(copy(fd_value));
4192     std::string fs = FPR(copy(fs_value));
4193     std::string ft = FPR(copy(ft_value));
4194
4195     return img::format("CMP.SAF.S %s, %s, %s", fd, fs, ft);
4196 }
4197
4198
4199 /*
4200  *
4201  *
4202  *   3         2         1
4203  *  10987654321098765432109876543210
4204  *  001000               x1110000101
4205  *     rt -----
4206  *          rs -----
4207  *               rd -----
4208  */
4209 std::string NMD::CMP_SEQ_D(uint64 instruction)
4210 {
4211     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4212     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4213     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4214
4215     std::string fd = FPR(copy(fd_value));
4216     std::string fs = FPR(copy(fs_value));
4217     std::string ft = FPR(copy(ft_value));
4218
4219     return img::format("CMP.SEQ.D %s, %s, %s", fd, fs, ft);
4220 }
4221
4222
4223 /*
4224  *
4225  *
4226  *   3         2         1
4227  *  10987654321098765432109876543210
4228  *  001000               x1110000101
4229  *     rt -----
4230  *          rs -----
4231  *               rd -----
4232  */
4233 std::string NMD::CMP_SEQ_S(uint64 instruction)
4234 {
4235     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4236     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4237     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4238
4239     std::string fd = FPR(copy(fd_value));
4240     std::string fs = FPR(copy(fs_value));
4241     std::string ft = FPR(copy(ft_value));
4242
4243     return img::format("CMP.SEQ.S %s, %s, %s", fd, fs, ft);
4244 }
4245
4246
4247 /*
4248  *
4249  *
4250  *   3         2         1
4251  *  10987654321098765432109876543210
4252  *  001000               x1110000101
4253  *     rt -----
4254  *          rs -----
4255  *               rd -----
4256  */
4257 std::string NMD::CMP_SLE_D(uint64 instruction)
4258 {
4259     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4260     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4261     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4262
4263     std::string fd = FPR(copy(fd_value));
4264     std::string fs = FPR(copy(fs_value));
4265     std::string ft = FPR(copy(ft_value));
4266
4267     return img::format("CMP.SLE.D %s, %s, %s", fd, fs, ft);
4268 }
4269
4270
4271 /*
4272  *
4273  *
4274  *   3         2         1
4275  *  10987654321098765432109876543210
4276  *  001000               x1110000101
4277  *     rt -----
4278  *          rs -----
4279  *               rd -----
4280  */
4281 std::string NMD::CMP_SLE_S(uint64 instruction)
4282 {
4283     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4284     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4285     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4286
4287     std::string fd = FPR(copy(fd_value));
4288     std::string fs = FPR(copy(fs_value));
4289     std::string ft = FPR(copy(ft_value));
4290
4291     return img::format("CMP.SLE.S %s, %s, %s", fd, fs, ft);
4292 }
4293
4294
4295 /*
4296  *
4297  *
4298  *   3         2         1
4299  *  10987654321098765432109876543210
4300  *  001000               x1110000101
4301  *     rt -----
4302  *          rs -----
4303  *               rd -----
4304  */
4305 std::string NMD::CMP_SLT_D(uint64 instruction)
4306 {
4307     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4308     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4309     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4310
4311     std::string fd = FPR(copy(fd_value));
4312     std::string fs = FPR(copy(fs_value));
4313     std::string ft = FPR(copy(ft_value));
4314
4315     return img::format("CMP.SLT.D %s, %s, %s", fd, fs, ft);
4316 }
4317
4318
4319 /*
4320  *
4321  *
4322  *   3         2         1
4323  *  10987654321098765432109876543210
4324  *  001000               x1110000101
4325  *     rt -----
4326  *          rs -----
4327  *               rd -----
4328  */
4329 std::string NMD::CMP_SLT_S(uint64 instruction)
4330 {
4331     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4332     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4333     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4334
4335     std::string fd = FPR(copy(fd_value));
4336     std::string fs = FPR(copy(fs_value));
4337     std::string ft = FPR(copy(ft_value));
4338
4339     return img::format("CMP.SLT.S %s, %s, %s", fd, fs, ft);
4340 }
4341
4342
4343 /*
4344  *
4345  *
4346  *   3         2         1
4347  *  10987654321098765432109876543210
4348  *  001000               x1110000101
4349  *     rt -----
4350  *          rs -----
4351  *               rd -----
4352  */
4353 std::string NMD::CMP_SNE_D(uint64 instruction)
4354 {
4355     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4356     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4357     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4358
4359     std::string fd = FPR(copy(fd_value));
4360     std::string fs = FPR(copy(fs_value));
4361     std::string ft = FPR(copy(ft_value));
4362
4363     return img::format("CMP.SNE.D %s, %s, %s", fd, fs, ft);
4364 }
4365
4366
4367 /*
4368  *
4369  *
4370  *   3         2         1
4371  *  10987654321098765432109876543210
4372  *  001000               x1110000101
4373  *     rt -----
4374  *          rs -----
4375  *               rd -----
4376  */
4377 std::string NMD::CMP_SNE_S(uint64 instruction)
4378 {
4379     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4380     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4381     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4382
4383     std::string fd = FPR(copy(fd_value));
4384     std::string fs = FPR(copy(fs_value));
4385     std::string ft = FPR(copy(ft_value));
4386
4387     return img::format("CMP.SNE.S %s, %s, %s", fd, fs, ft);
4388 }
4389
4390
4391 /*
4392  *
4393  *
4394  *   3         2         1
4395  *  10987654321098765432109876543210
4396  *  001000               x1110000101
4397  *     rt -----
4398  *          rs -----
4399  *               rd -----
4400  */
4401 std::string NMD::CMP_SOR_D(uint64 instruction)
4402 {
4403     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4404     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4405     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4406
4407     std::string fd = FPR(copy(fd_value));
4408     std::string fs = FPR(copy(fs_value));
4409     std::string ft = FPR(copy(ft_value));
4410
4411     return img::format("CMP.SOR.D %s, %s, %s", fd, fs, ft);
4412 }
4413
4414
4415 /*
4416  *
4417  *
4418  *   3         2         1
4419  *  10987654321098765432109876543210
4420  *  001000               x1110000101
4421  *     rt -----
4422  *          rs -----
4423  *               rd -----
4424  */
4425 std::string NMD::CMP_SOR_S(uint64 instruction)
4426 {
4427     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4428     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4429     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4430
4431     std::string fd = FPR(copy(fd_value));
4432     std::string fs = FPR(copy(fs_value));
4433     std::string ft = FPR(copy(ft_value));
4434
4435     return img::format("CMP.SOR.S %s, %s, %s", fd, fs, ft);
4436 }
4437
4438
4439 /*
4440  *
4441  *
4442  *   3         2         1
4443  *  10987654321098765432109876543210
4444  *  001000               x1110000101
4445  *     rt -----
4446  *          rs -----
4447  *               rd -----
4448  */
4449 std::string NMD::CMP_SUEQ_D(uint64 instruction)
4450 {
4451     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4452     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4453     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4454
4455     std::string fd = FPR(copy(fd_value));
4456     std::string fs = FPR(copy(fs_value));
4457     std::string ft = FPR(copy(ft_value));
4458
4459     return img::format("CMP.SUEQ.D %s, %s, %s", fd, fs, ft);
4460 }
4461
4462
4463 /*
4464  *
4465  *
4466  *   3         2         1
4467  *  10987654321098765432109876543210
4468  *  001000               x1110000101
4469  *     rt -----
4470  *          rs -----
4471  *               rd -----
4472  */
4473 std::string NMD::CMP_SUEQ_S(uint64 instruction)
4474 {
4475     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4476     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4477     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4478
4479     std::string fd = FPR(copy(fd_value));
4480     std::string fs = FPR(copy(fs_value));
4481     std::string ft = FPR(copy(ft_value));
4482
4483     return img::format("CMP.SUEQ.S %s, %s, %s", fd, fs, ft);
4484 }
4485
4486
4487 /*
4488  *
4489  *
4490  *   3         2         1
4491  *  10987654321098765432109876543210
4492  *  001000               x1110000101
4493  *     rt -----
4494  *          rs -----
4495  *               rd -----
4496  */
4497 std::string NMD::CMP_SULE_D(uint64 instruction)
4498 {
4499     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4500     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4501     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4502
4503     std::string fd = FPR(copy(fd_value));
4504     std::string fs = FPR(copy(fs_value));
4505     std::string ft = FPR(copy(ft_value));
4506
4507     return img::format("CMP.SULE.D %s, %s, %s", fd, fs, ft);
4508 }
4509
4510
4511 /*
4512  *
4513  *
4514  *   3         2         1
4515  *  10987654321098765432109876543210
4516  *  001000               x1110000101
4517  *     rt -----
4518  *          rs -----
4519  *               rd -----
4520  */
4521 std::string NMD::CMP_SULE_S(uint64 instruction)
4522 {
4523     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4524     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4525     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4526
4527     std::string fd = FPR(copy(fd_value));
4528     std::string fs = FPR(copy(fs_value));
4529     std::string ft = FPR(copy(ft_value));
4530
4531     return img::format("CMP.SULE.S %s, %s, %s", fd, fs, ft);
4532 }
4533
4534
4535 /*
4536  *
4537  *
4538  *   3         2         1
4539  *  10987654321098765432109876543210
4540  *  001000               x1110000101
4541  *     rt -----
4542  *          rs -----
4543  *               rd -----
4544  */
4545 std::string NMD::CMP_SULT_D(uint64 instruction)
4546 {
4547     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4548     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4549     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4550
4551     std::string fd = FPR(copy(fd_value));
4552     std::string fs = FPR(copy(fs_value));
4553     std::string ft = FPR(copy(ft_value));
4554
4555     return img::format("CMP.SULT.D %s, %s, %s", fd, fs, ft);
4556 }
4557
4558
4559 /*
4560  *
4561  *
4562  *   3         2         1
4563  *  10987654321098765432109876543210
4564  *  001000               x1110000101
4565  *     rt -----
4566  *          rs -----
4567  *               rd -----
4568  */
4569 std::string NMD::CMP_SULT_S(uint64 instruction)
4570 {
4571     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4572     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4573     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4574
4575     std::string fd = FPR(copy(fd_value));
4576     std::string fs = FPR(copy(fs_value));
4577     std::string ft = FPR(copy(ft_value));
4578
4579     return img::format("CMP.SULT.S %s, %s, %s", fd, fs, ft);
4580 }
4581
4582
4583 /*
4584  *
4585  *
4586  *   3         2         1
4587  *  10987654321098765432109876543210
4588  *  001000               x1110000101
4589  *     rt -----
4590  *          rs -----
4591  *               rd -----
4592  */
4593 std::string NMD::CMP_SUN_D(uint64 instruction)
4594 {
4595     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4596     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4597     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4598
4599     std::string fd = FPR(copy(fd_value));
4600     std::string fs = FPR(copy(fs_value));
4601     std::string ft = FPR(copy(ft_value));
4602
4603     return img::format("CMP.SUN.D %s, %s, %s", fd, fs, ft);
4604 }
4605
4606
4607 /*
4608  *
4609  *
4610  *   3         2         1
4611  *  10987654321098765432109876543210
4612  *  001000               x1110000101
4613  *     rt -----
4614  *          rs -----
4615  *               rd -----
4616  */
4617 std::string NMD::CMP_SUNE_D(uint64 instruction)
4618 {
4619     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4620     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4621     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4622
4623     std::string fd = FPR(copy(fd_value));
4624     std::string fs = FPR(copy(fs_value));
4625     std::string ft = FPR(copy(ft_value));
4626
4627     return img::format("CMP.SUNE.D %s, %s, %s", fd, fs, ft);
4628 }
4629
4630
4631 /*
4632  *
4633  *
4634  *   3         2         1
4635  *  10987654321098765432109876543210
4636  *  001000               x1110000101
4637  *     rt -----
4638  *          rs -----
4639  *               rd -----
4640  */
4641 std::string NMD::CMP_SUNE_S(uint64 instruction)
4642 {
4643     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4644     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4645     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4646
4647     std::string fd = FPR(copy(fd_value));
4648     std::string fs = FPR(copy(fs_value));
4649     std::string ft = FPR(copy(ft_value));
4650
4651     return img::format("CMP.SUNE.S %s, %s, %s", fd, fs, ft);
4652 }
4653
4654
4655 /*
4656  *
4657  *
4658  *   3         2         1
4659  *  10987654321098765432109876543210
4660  *  001000               x1110000101
4661  *     rt -----
4662  *          rs -----
4663  *               rd -----
4664  */
4665 std::string NMD::CMP_SUN_S(uint64 instruction)
4666 {
4667     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4668     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4669     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4670
4671     std::string fd = FPR(copy(fd_value));
4672     std::string fs = FPR(copy(fs_value));
4673     std::string ft = FPR(copy(ft_value));
4674
4675     return img::format("CMP.SUN.S %s, %s, %s", fd, fs, ft);
4676 }
4677
4678
4679 /*
4680  *
4681  *
4682  *   3         2         1
4683  *  10987654321098765432109876543210
4684  *  001000               x1110000101
4685  *     rt -----
4686  *          rs -----
4687  *               rd -----
4688  */
4689 std::string NMD::CMP_UEQ_D(uint64 instruction)
4690 {
4691     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4692     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4693     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4694
4695     std::string fd = FPR(copy(fd_value));
4696     std::string fs = FPR(copy(fs_value));
4697     std::string ft = FPR(copy(ft_value));
4698
4699     return img::format("CMP.UEQ.D %s, %s, %s", fd, fs, ft);
4700 }
4701
4702
4703 /*
4704  *
4705  *
4706  *   3         2         1
4707  *  10987654321098765432109876543210
4708  *  001000               x1110000101
4709  *     rt -----
4710  *          rs -----
4711  *               rd -----
4712  */
4713 std::string NMD::CMP_UEQ_S(uint64 instruction)
4714 {
4715     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4716     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4717     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4718
4719     std::string fd = FPR(copy(fd_value));
4720     std::string fs = FPR(copy(fs_value));
4721     std::string ft = FPR(copy(ft_value));
4722
4723     return img::format("CMP.UEQ.S %s, %s, %s", fd, fs, ft);
4724 }
4725
4726
4727 /*
4728  *
4729  *
4730  *   3         2         1
4731  *  10987654321098765432109876543210
4732  *  001000               x1110000101
4733  *     rt -----
4734  *          rs -----
4735  *               rd -----
4736  */
4737 std::string NMD::CMP_ULE_D(uint64 instruction)
4738 {
4739     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4740     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4741     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4742
4743     std::string fd = FPR(copy(fd_value));
4744     std::string fs = FPR(copy(fs_value));
4745     std::string ft = FPR(copy(ft_value));
4746
4747     return img::format("CMP.ULE.D %s, %s, %s", fd, fs, ft);
4748 }
4749
4750
4751 /*
4752  *
4753  *
4754  *   3         2         1
4755  *  10987654321098765432109876543210
4756  *  001000               x1110000101
4757  *     rt -----
4758  *          rs -----
4759  *               rd -----
4760  */
4761 std::string NMD::CMP_ULE_S(uint64 instruction)
4762 {
4763     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4764     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4765     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4766
4767     std::string fd = FPR(copy(fd_value));
4768     std::string fs = FPR(copy(fs_value));
4769     std::string ft = FPR(copy(ft_value));
4770
4771     return img::format("CMP.ULE.S %s, %s, %s", fd, fs, ft);
4772 }
4773
4774
4775 /*
4776  *
4777  *
4778  *   3         2         1
4779  *  10987654321098765432109876543210
4780  *  001000               x1110000101
4781  *     rt -----
4782  *          rs -----
4783  *               rd -----
4784  */
4785 std::string NMD::CMP_ULT_D(uint64 instruction)
4786 {
4787     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4788     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4789     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4790
4791     std::string fd = FPR(copy(fd_value));
4792     std::string fs = FPR(copy(fs_value));
4793     std::string ft = FPR(copy(ft_value));
4794
4795     return img::format("CMP.ULT.D %s, %s, %s", fd, fs, ft);
4796 }
4797
4798
4799 /*
4800  *
4801  *
4802  *   3         2         1
4803  *  10987654321098765432109876543210
4804  *  001000               x1110000101
4805  *     rt -----
4806  *          rs -----
4807  *               rd -----
4808  */
4809 std::string NMD::CMP_ULT_S(uint64 instruction)
4810 {
4811     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4812     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4813     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4814
4815     std::string fd = FPR(copy(fd_value));
4816     std::string fs = FPR(copy(fs_value));
4817     std::string ft = FPR(copy(ft_value));
4818
4819     return img::format("CMP.ULT.S %s, %s, %s", fd, fs, ft);
4820 }
4821
4822
4823 /*
4824  *
4825  *
4826  *   3         2         1
4827  *  10987654321098765432109876543210
4828  *  001000               x1110000101
4829  *     rt -----
4830  *          rs -----
4831  *               rd -----
4832  */
4833 std::string NMD::CMP_UN_D(uint64 instruction)
4834 {
4835     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4836     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4837     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4838
4839     std::string fd = FPR(copy(fd_value));
4840     std::string fs = FPR(copy(fs_value));
4841     std::string ft = FPR(copy(ft_value));
4842
4843     return img::format("CMP.UN.D %s, %s, %s", fd, fs, ft);
4844 }
4845
4846
4847 /*
4848  *
4849  *
4850  *   3         2         1
4851  *  10987654321098765432109876543210
4852  *  001000               x1110000101
4853  *     rt -----
4854  *          rs -----
4855  *               rd -----
4856  */
4857 std::string NMD::CMP_UNE_D(uint64 instruction)
4858 {
4859     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4860     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4861     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4862
4863     std::string fd = FPR(copy(fd_value));
4864     std::string fs = FPR(copy(fs_value));
4865     std::string ft = FPR(copy(ft_value));
4866
4867     return img::format("CMP.UNE.D %s, %s, %s", fd, fs, ft);
4868 }
4869
4870
4871 /*
4872  *
4873  *
4874  *   3         2         1
4875  *  10987654321098765432109876543210
4876  *  001000               x1110000101
4877  *     rt -----
4878  *          rs -----
4879  *               rd -----
4880  */
4881 std::string NMD::CMP_UNE_S(uint64 instruction)
4882 {
4883     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4884     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4885     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4886
4887     std::string fd = FPR(copy(fd_value));
4888     std::string fs = FPR(copy(fs_value));
4889     std::string ft = FPR(copy(ft_value));
4890
4891     return img::format("CMP.UNE.S %s, %s, %s", fd, fs, ft);
4892 }
4893
4894
4895 /*
4896  *
4897  *
4898  *   3         2         1
4899  *  10987654321098765432109876543210
4900  *  001000               x1110000101
4901  *     rt -----
4902  *          rs -----
4903  *               rd -----
4904  */
4905 std::string NMD::CMP_UN_S(uint64 instruction)
4906 {
4907     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4908     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4909     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4910
4911     std::string fd = FPR(copy(fd_value));
4912     std::string fs = FPR(copy(fs_value));
4913     std::string ft = FPR(copy(ft_value));
4914
4915     return img::format("CMP.UN.S %s, %s, %s", fd, fs, ft);
4916 }
4917
4918
4919 /*
4920  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4921  *   four bytes and write result to GPR and DSPControl
4922  *
4923  *   3         2         1
4924  *  10987654321098765432109876543210
4925  *  001000               x0110000101
4926  *     rt -----
4927  *          rs -----
4928  *               rd -----
4929  */
4930 std::string NMD::CMPGDU_EQ_QB(uint64 instruction)
4931 {
4932     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4933     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4934     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4935
4936     std::string rd = GPR(copy(rd_value));
4937     std::string rs = GPR(copy(rs_value));
4938     std::string rt = GPR(copy(rt_value));
4939
4940     return img::format("CMPGDU.EQ.QB %s, %s, %s", rd, rs, rt);
4941 }
4942
4943
4944 /*
4945  * [DSP] CMPGDU.LE.QB rd, rs, rt - Compare unsigned vector of
4946  *   four bytes and write result to GPR and DSPControl
4947  *
4948  *   3         2         1
4949  *  10987654321098765432109876543210
4950  *  001000               x1000000101
4951  *     rt -----
4952  *          rs -----
4953  *               rd -----
4954  */
4955 std::string NMD::CMPGDU_LE_QB(uint64 instruction)
4956 {
4957     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4958     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4959     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4960
4961     std::string rd = GPR(copy(rd_value));
4962     std::string rs = GPR(copy(rs_value));
4963     std::string rt = GPR(copy(rt_value));
4964
4965     return img::format("CMPGDU.LE.QB %s, %s, %s", rd, rs, rt);
4966 }
4967
4968
4969 /*
4970  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4971  *   four bytes and write result to GPR and DSPControl
4972  *
4973  *   3         2         1
4974  *  10987654321098765432109876543210
4975  *  001000               x0111000101
4976  *     rt -----
4977  *          rs -----
4978  *               rd -----
4979  */
4980 std::string NMD::CMPGDU_LT_QB(uint64 instruction)
4981 {
4982     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4983     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4984     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4985
4986     std::string rd = GPR(copy(rd_value));
4987     std::string rs = GPR(copy(rs_value));
4988     std::string rt = GPR(copy(rt_value));
4989
4990     return img::format("CMPGDU.LT.QB %s, %s, %s", rd, rs, rt);
4991 }
4992
4993
4994 /*
4995  * [DSP] CMPGU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4996  *   byte values and write result to a GPR
4997  *
4998  *   3         2         1
4999  *  10987654321098765432109876543210
5000  *  001000               x0011000101
5001  *     rt -----
5002  *          rs -----
5003  *               rd -----
5004  */
5005 std::string NMD::CMPGU_EQ_QB(uint64 instruction)
5006 {
5007     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5008     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5009     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5010
5011     std::string rd = GPR(copy(rd_value));
5012     std::string rs = GPR(copy(rs_value));
5013     std::string rt = GPR(copy(rt_value));
5014
5015     return img::format("CMPGU.EQ.QB %s, %s, %s", rd, rs, rt);
5016 }
5017
5018
5019 /*
5020  * [DSP] CMPGU.LE.QB rd, rs, rt - Compare vectors of unsigned
5021  *   byte values and write result to a GPR
5022  *
5023  *   3         2         1
5024  *  10987654321098765432109876543210
5025  *  001000               x0101000101
5026  *     rt -----
5027  *          rs -----
5028  *               rd -----
5029  */
5030 std::string NMD::CMPGU_LE_QB(uint64 instruction)
5031 {
5032     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5033     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5034     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5035
5036     std::string rd = GPR(copy(rd_value));
5037     std::string rs = GPR(copy(rs_value));
5038     std::string rt = GPR(copy(rt_value));
5039
5040     return img::format("CMPGU.LE.QB %s, %s, %s", rd, rs, rt);
5041 }
5042
5043
5044 /*
5045  * [DSP] CMPGU.LT.QB rd, rs, rt - Compare vectors of unsigned
5046  *   byte values and write result to a GPR
5047  *
5048  *   3         2         1
5049  *  10987654321098765432109876543210
5050  *  001000               x0100000101
5051  *     rt -----
5052  *          rs -----
5053  *               rd -----
5054  */
5055 std::string NMD::CMPGU_LT_QB(uint64 instruction)
5056 {
5057     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5058     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5059     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5060
5061     std::string rd = GPR(copy(rd_value));
5062     std::string rs = GPR(copy(rs_value));
5063     std::string rt = GPR(copy(rt_value));
5064
5065     return img::format("CMPGU.LT.QB %s, %s, %s", rd, rs, rt);
5066 }
5067
5068
5069 /*
5070  * [DSP] CMPU.EQ.QB rd, rs, rt - Compare vectors of unsigned
5071  *   byte values
5072  *
5073  *   3         2         1
5074  *  10987654321098765432109876543210
5075  *  001000          xxxxxx1001000101
5076  *     rt -----
5077  *          rs -----
5078  */
5079 std::string NMD::CMPU_EQ_QB(uint64 instruction)
5080 {
5081     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5082     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5083
5084     std::string rs = GPR(copy(rs_value));
5085     std::string rt = GPR(copy(rt_value));
5086
5087     return img::format("CMPU.EQ.QB %s, %s", rs, rt);
5088 }
5089
5090
5091 /*
5092  * [DSP] CMPU.LE.QB rd, rs, rt - Compare vectors of unsigned
5093  *   byte values
5094  *
5095  *   3         2         1
5096  *  10987654321098765432109876543210
5097  *  001000          xxxxxx1011000101
5098  *     rt -----
5099  *          rs -----
5100  */
5101 std::string NMD::CMPU_LE_QB(uint64 instruction)
5102 {
5103     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5104     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5105
5106     std::string rs = GPR(copy(rs_value));
5107     std::string rt = GPR(copy(rt_value));
5108
5109     return img::format("CMPU.LE.QB %s, %s", rs, rt);
5110 }
5111
5112
5113 /*
5114  * [DSP] CMPU.LT.QB rd, rs, rt - Compare vectors of unsigned
5115  *   byte values
5116  *
5117  *   3         2         1
5118  *  10987654321098765432109876543210
5119  *  001000          xxxxxx1010000101
5120  *     rt -----
5121  *          rs -----
5122  */
5123 std::string NMD::CMPU_LT_QB(uint64 instruction)
5124 {
5125     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5126     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5127
5128     std::string rs = GPR(copy(rs_value));
5129     std::string rt = GPR(copy(rt_value));
5130
5131     return img::format("CMPU.LT.QB %s, %s", rs, rt);
5132 }
5133
5134
5135 /*
5136  *
5137  *
5138  *   3         2         1
5139  *  10987654321098765432109876543210
5140  *  001000               x1110000101
5141  *     rt -----
5142  *          rs -----
5143  *               rd -----
5144  */
5145 std::string NMD::COP2_1(uint64 instruction)
5146 {
5147     uint64 cofun_value = extract_cofun_25_24_23(instruction);
5148
5149     std::string cofun = IMMEDIATE(copy(cofun_value));
5150
5151     return img::format("COP2_1 %s", cofun);
5152 }
5153
5154
5155 /*
5156  *
5157  *
5158  *   3         2         1
5159  *  10987654321098765432109876543210
5160  *  001000               x1110000101
5161  *     rt -----
5162  *          rs -----
5163  *               rd -----
5164  */
5165 std::string NMD::CTC1(uint64 instruction)
5166 {
5167     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5168     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5169
5170     std::string rt = GPR(copy(rt_value));
5171     std::string cs = CPR(copy(cs_value));
5172
5173     return img::format("CTC1 %s, %s", rt, cs);
5174 }
5175
5176
5177 /*
5178  *
5179  *
5180  *   3         2         1
5181  *  10987654321098765432109876543210
5182  *  001000               x1110000101
5183  *     rt -----
5184  *          rs -----
5185  *               rd -----
5186  */
5187 std::string NMD::CTC2(uint64 instruction)
5188 {
5189     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5190     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5191
5192     std::string rt = GPR(copy(rt_value));
5193     std::string cs = CPR(copy(cs_value));
5194
5195     return img::format("CTC2 %s, %s", rt, cs);
5196 }
5197
5198
5199 /*
5200  *
5201  *
5202  *   3         2         1
5203  *  10987654321098765432109876543210
5204  *  001000               x1110000101
5205  *     rt -----
5206  *          rs -----
5207  *               rd -----
5208  */
5209 std::string NMD::CVT_D_L(uint64 instruction)
5210 {
5211     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5212     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5213
5214     std::string ft = FPR(copy(ft_value));
5215     std::string fs = FPR(copy(fs_value));
5216
5217     return img::format("CVT.D.L %s, %s", ft, fs);
5218 }
5219
5220
5221 /*
5222  *
5223  *
5224  *   3         2         1
5225  *  10987654321098765432109876543210
5226  *  001000               x1110000101
5227  *     rt -----
5228  *          rs -----
5229  *               rd -----
5230  */
5231 std::string NMD::CVT_D_S(uint64 instruction)
5232 {
5233     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5234     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5235
5236     std::string ft = FPR(copy(ft_value));
5237     std::string fs = FPR(copy(fs_value));
5238
5239     return img::format("CVT.D.S %s, %s", ft, fs);
5240 }
5241
5242
5243 /*
5244  *
5245  *
5246  *   3         2         1
5247  *  10987654321098765432109876543210
5248  *  001000               x1110000101
5249  *     rt -----
5250  *          rs -----
5251  *               rd -----
5252  */
5253 std::string NMD::CVT_D_W(uint64 instruction)
5254 {
5255     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5256     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5257
5258     std::string ft = FPR(copy(ft_value));
5259     std::string fs = FPR(copy(fs_value));
5260
5261     return img::format("CVT.D.W %s, %s", ft, fs);
5262 }
5263
5264
5265 /*
5266  *
5267  *
5268  *   3         2         1
5269  *  10987654321098765432109876543210
5270  *  001000               x1110000101
5271  *     rt -----
5272  *          rs -----
5273  *               rd -----
5274  */
5275 std::string NMD::CVT_L_D(uint64 instruction)
5276 {
5277     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5278     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5279
5280     std::string ft = FPR(copy(ft_value));
5281     std::string fs = FPR(copy(fs_value));
5282
5283     return img::format("CVT.L.D %s, %s", ft, fs);
5284 }
5285
5286
5287 /*
5288  *
5289  *
5290  *   3         2         1
5291  *  10987654321098765432109876543210
5292  *  001000               x1110000101
5293  *     rt -----
5294  *          rs -----
5295  *               rd -----
5296  */
5297 std::string NMD::CVT_L_S(uint64 instruction)
5298 {
5299     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5300     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5301
5302     std::string ft = FPR(copy(ft_value));
5303     std::string fs = FPR(copy(fs_value));
5304
5305     return img::format("CVT.L.S %s, %s", ft, fs);
5306 }
5307
5308
5309 /*
5310  *
5311  *
5312  *   3         2         1
5313  *  10987654321098765432109876543210
5314  *  001000               x1110000101
5315  *     rt -----
5316  *          rs -----
5317  *               rd -----
5318  */
5319 std::string NMD::CVT_S_D(uint64 instruction)
5320 {
5321     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5322     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5323
5324     std::string ft = FPR(copy(ft_value));
5325     std::string fs = FPR(copy(fs_value));
5326
5327     return img::format("CVT.S.D %s, %s", ft, fs);
5328 }
5329
5330
5331 /*
5332  *
5333  *
5334  *   3         2         1
5335  *  10987654321098765432109876543210
5336  *  001000               x1110000101
5337  *     rt -----
5338  *          rs -----
5339  *               rd -----
5340  */
5341 std::string NMD::CVT_S_L(uint64 instruction)
5342 {
5343     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5344     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5345
5346     std::string ft = FPR(copy(ft_value));
5347     std::string fs = FPR(copy(fs_value));
5348
5349     return img::format("CVT.S.L %s, %s", ft, fs);
5350 }
5351
5352
5353 /*
5354  *
5355  *
5356  *   3         2         1
5357  *  10987654321098765432109876543210
5358  *  001000               x1110000101
5359  *     rt -----
5360  *          rs -----
5361  *               rd -----
5362  */
5363 std::string NMD::CVT_S_PL(uint64 instruction)
5364 {
5365     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5366     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5367
5368     std::string ft = FPR(copy(ft_value));
5369     std::string fs = FPR(copy(fs_value));
5370
5371     return img::format("CVT.S.PL %s, %s", ft, fs);
5372 }
5373
5374
5375 /*
5376  *
5377  *
5378  *   3         2         1
5379  *  10987654321098765432109876543210
5380  *  001000               x1110000101
5381  *     rt -----
5382  *          rs -----
5383  *               rd -----
5384  */
5385 std::string NMD::CVT_S_PU(uint64 instruction)
5386 {
5387     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5388     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5389
5390     std::string ft = FPR(copy(ft_value));
5391     std::string fs = FPR(copy(fs_value));
5392
5393     return img::format("CVT.S.PU %s, %s", ft, fs);
5394 }
5395
5396
5397 /*
5398  *
5399  *
5400  *   3         2         1
5401  *  10987654321098765432109876543210
5402  *  001000               x1110000101
5403  *     rt -----
5404  *          rs -----
5405  *               rd -----
5406  */
5407 std::string NMD::CVT_S_W(uint64 instruction)
5408 {
5409     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5410     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5411
5412     std::string ft = FPR(copy(ft_value));
5413     std::string fs = FPR(copy(fs_value));
5414
5415     return img::format("CVT.S.W %s, %s", ft, fs);
5416 }
5417
5418
5419 /*
5420  *
5421  *
5422  *   3         2         1
5423  *  10987654321098765432109876543210
5424  *  001000               x1110000101
5425  *     rt -----
5426  *          rs -----
5427  *               rd -----
5428  */
5429 std::string NMD::CVT_W_D(uint64 instruction)
5430 {
5431     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5432     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5433
5434     std::string ft = FPR(copy(ft_value));
5435     std::string fs = FPR(copy(fs_value));
5436
5437     return img::format("CVT.W.D %s, %s", ft, fs);
5438 }
5439
5440
5441 /*
5442  *
5443  *
5444  *   3         2         1
5445  *  10987654321098765432109876543210
5446  *  001000               x1110000101
5447  *     rt -----
5448  *          rs -----
5449  *               rd -----
5450  */
5451 std::string NMD::CVT_W_S(uint64 instruction)
5452 {
5453     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5454     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5455
5456     std::string ft = FPR(copy(ft_value));
5457     std::string fs = FPR(copy(fs_value));
5458
5459     return img::format("CVT.W.S %s, %s", ft, fs);
5460 }
5461
5462
5463 /*
5464  *
5465  *
5466  *   3         2         1
5467  *  10987654321098765432109876543210
5468  *  001000               x1110000101
5469  *     rt -----
5470  *          rs -----
5471  *               rd -----
5472  */
5473 std::string NMD::DADDIU_48_(uint64 instruction)
5474 {
5475     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
5476     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
5477
5478     std::string rt = GPR(copy(rt_value));
5479     std::string s = IMMEDIATE(copy(s_value));
5480
5481     return img::format("DADDIU %s, %s", rt, s);
5482 }
5483
5484
5485 /*
5486  *
5487  *
5488  *   3         2         1
5489  *  10987654321098765432109876543210
5490  *  001000               x1110000101
5491  *     rt -----
5492  *          rs -----
5493  *               rd -----
5494  */
5495 std::string NMD::DADDIU_NEG_(uint64 instruction)
5496 {
5497     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5498     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5499     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5500
5501     std::string rt = GPR(copy(rt_value));
5502     std::string rs = GPR(copy(rs_value));
5503     std::string u = IMMEDIATE(neg_copy(u_value));
5504
5505     return img::format("DADDIU %s, %s, %s", rt, rs, u);
5506 }
5507
5508
5509 /*
5510  *
5511  *
5512  *   3         2         1
5513  *  10987654321098765432109876543210
5514  *  001000               x1110000101
5515  *     rt -----
5516  *          rs -----
5517  *               rd -----
5518  */
5519 std::string NMD::DADDIU_U12_(uint64 instruction)
5520 {
5521     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5522     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5523     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5524
5525     std::string rt = GPR(copy(rt_value));
5526     std::string rs = GPR(copy(rs_value));
5527     std::string u = IMMEDIATE(copy(u_value));
5528
5529     return img::format("DADDIU %s, %s, %s", rt, rs, u);
5530 }
5531
5532
5533 /*
5534  *
5535  *
5536  *   3         2         1
5537  *  10987654321098765432109876543210
5538  *  001000               x1110000101
5539  *     rt -----
5540  *          rs -----
5541  *               rd -----
5542  */
5543 std::string NMD::DADD(uint64 instruction)
5544 {
5545     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5546     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5547     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5548
5549     std::string rd = GPR(copy(rd_value));
5550     std::string rs = GPR(copy(rs_value));
5551     std::string rt = GPR(copy(rt_value));
5552
5553     return img::format("DADD %s, %s, %s", rd, rs, rt);
5554 }
5555
5556
5557 /*
5558  *
5559  *
5560  *   3         2         1
5561  *  10987654321098765432109876543210
5562  *  001000               x1110000101
5563  *     rt -----
5564  *          rs -----
5565  *               rd -----
5566  */
5567 std::string NMD::DADDU(uint64 instruction)
5568 {
5569     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5570     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5571     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5572
5573     std::string rd = GPR(copy(rd_value));
5574     std::string rs = GPR(copy(rs_value));
5575     std::string rt = GPR(copy(rt_value));
5576
5577     return img::format("DADDU %s, %s, %s", rd, rs, rt);
5578 }
5579
5580
5581 /*
5582  *
5583  *
5584  *   3         2         1
5585  *  10987654321098765432109876543210
5586  *  001000               x1110000101
5587  *     rt -----
5588  *          rs -----
5589  *               rd -----
5590  */
5591 std::string NMD::DCLO(uint64 instruction)
5592 {
5593     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5594     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5595
5596     std::string rt = GPR(copy(rt_value));
5597     std::string rs = GPR(copy(rs_value));
5598
5599     return img::format("DCLO %s, %s", rt, rs);
5600 }
5601
5602
5603 /*
5604  *
5605  *
5606  *   3         2         1
5607  *  10987654321098765432109876543210
5608  *  001000               x1110000101
5609  *     rt -----
5610  *          rs -----
5611  *               rd -----
5612  */
5613 std::string NMD::DCLZ(uint64 instruction)
5614 {
5615     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5616     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5617
5618     std::string rt = GPR(copy(rt_value));
5619     std::string rs = GPR(copy(rs_value));
5620
5621     return img::format("DCLZ %s, %s", rt, rs);
5622 }
5623
5624
5625 /*
5626  *
5627  *
5628  *   3         2         1
5629  *  10987654321098765432109876543210
5630  *  001000               x1110000101
5631  *     rt -----
5632  *          rs -----
5633  *               rd -----
5634  */
5635 std::string NMD::DDIV(uint64 instruction)
5636 {
5637     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5638     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5639     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5640
5641     std::string rd = GPR(copy(rd_value));
5642     std::string rs = GPR(copy(rs_value));
5643     std::string rt = GPR(copy(rt_value));
5644
5645     return img::format("DDIV %s, %s, %s", rd, rs, rt);
5646 }
5647
5648
5649 /*
5650  *
5651  *
5652  *   3         2         1
5653  *  10987654321098765432109876543210
5654  *  001000               x1110000101
5655  *     rt -----
5656  *          rs -----
5657  *               rd -----
5658  */
5659 std::string NMD::DDIVU(uint64 instruction)
5660 {
5661     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5662     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5663     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5664
5665     std::string rd = GPR(copy(rd_value));
5666     std::string rs = GPR(copy(rs_value));
5667     std::string rt = GPR(copy(rt_value));
5668
5669     return img::format("DDIVU %s, %s, %s", rd, rs, rt);
5670 }
5671
5672
5673 /*
5674  *
5675  *
5676  *   3         2         1
5677  *  10987654321098765432109876543210
5678  *  001000               x1110000101
5679  *     rt -----
5680  *          rs -----
5681  *               rd -----
5682  */
5683 std::string NMD::DERET(uint64 instruction)
5684 {
5685     (void)instruction;
5686
5687     return "DERET ";
5688 }
5689
5690
5691 /*
5692  *
5693  *
5694  *   3         2         1
5695  *  10987654321098765432109876543210
5696  *  001000               x1110000101
5697  *     rt -----
5698  *          rs -----
5699  *               rd -----
5700  */
5701 std::string NMD::DEXTM(uint64 instruction)
5702 {
5703     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5704     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5705     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5706     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5707
5708     std::string rt = GPR(copy(rt_value));
5709     std::string rs = GPR(copy(rs_value));
5710     std::string lsb = IMMEDIATE(copy(lsb_value));
5711     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5712
5713     return img::format("DEXTM %s, %s, %s, %s", rt, rs, lsb, msbd);
5714 }
5715
5716
5717 /*
5718  *
5719  *
5720  *   3         2         1
5721  *  10987654321098765432109876543210
5722  *  001000               x1110000101
5723  *     rt -----
5724  *          rs -----
5725  *               rd -----
5726  */
5727 std::string NMD::DEXT(uint64 instruction)
5728 {
5729     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5730     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5731     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5732     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5733
5734     std::string rt = GPR(copy(rt_value));
5735     std::string rs = GPR(copy(rs_value));
5736     std::string lsb = IMMEDIATE(copy(lsb_value));
5737     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5738
5739     return img::format("DEXT %s, %s, %s, %s", rt, rs, lsb, msbd);
5740 }
5741
5742
5743 /*
5744  *
5745  *
5746  *   3         2         1
5747  *  10987654321098765432109876543210
5748  *  001000               x1110000101
5749  *     rt -----
5750  *          rs -----
5751  *               rd -----
5752  */
5753 std::string NMD::DEXTU(uint64 instruction)
5754 {
5755     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5756     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5757     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5758     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5759
5760     std::string rt = GPR(copy(rt_value));
5761     std::string rs = GPR(copy(rs_value));
5762     std::string lsb = IMMEDIATE(copy(lsb_value));
5763     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
5764
5765     return img::format("DEXTU %s, %s, %s, %s", rt, rs, lsb, msbd);
5766 }
5767
5768
5769 /*
5770  *
5771  *
5772  *   3         2         1
5773  *  10987654321098765432109876543210
5774  *  001000               x1110000101
5775  *     rt -----
5776  *          rs -----
5777  *               rd -----
5778  */
5779 std::string NMD::DINSM(uint64 instruction)
5780 {
5781     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5782     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5783     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5784     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5785
5786     std::string rt = GPR(copy(rt_value));
5787     std::string rs = GPR(copy(rs_value));
5788     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5789     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5790     /* !!!!!!!!!! - no conversion function */
5791
5792     return img::format("DINSM %s, %s, %s, %s", rt, rs, pos, size);
5793     /* hand edited */
5794 }
5795
5796
5797 /*
5798  *
5799  *
5800  *   3         2         1
5801  *  10987654321098765432109876543210
5802  *  001000               x1110000101
5803  *     rt -----
5804  *          rs -----
5805  *               rd -----
5806  */
5807 std::string NMD::DINS(uint64 instruction)
5808 {
5809     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5810     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5811     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5812     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5813
5814     std::string rt = GPR(copy(rt_value));
5815     std::string rs = GPR(copy(rs_value));
5816     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5817     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5818     /* !!!!!!!!!! - no conversion function */
5819
5820     return img::format("DINS %s, %s, %s, %s", rt, rs, pos, size);
5821     /* hand edited */
5822 }
5823
5824
5825 /*
5826  *
5827  *
5828  *   3         2         1
5829  *  10987654321098765432109876543210
5830  *  001000               x1110000101
5831  *     rt -----
5832  *          rs -----
5833  *               rd -----
5834  */
5835 std::string NMD::DINSU(uint64 instruction)
5836 {
5837     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5838     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5839     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5840     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5841
5842     std::string rt = GPR(copy(rt_value));
5843     std::string rs = GPR(copy(rs_value));
5844     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
5845     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
5846     /* !!!!!!!!!! - no conversion function */
5847
5848     return img::format("DINSU %s, %s, %s, %s", rt, rs, pos, size);
5849     /* hand edited */
5850 }
5851
5852
5853 /*
5854  *
5855  *
5856  *   3         2         1
5857  *  10987654321098765432109876543210
5858  *  001000               x1110000101
5859  *     rt -----
5860  *          rs -----
5861  *               rd -----
5862  */
5863 std::string NMD::DI(uint64 instruction)
5864 {
5865     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5866
5867     std::string rt = GPR(copy(rt_value));
5868
5869     return img::format("DI %s", rt);
5870 }
5871
5872
5873 /*
5874  *
5875  *
5876  *   3         2         1
5877  *  10987654321098765432109876543210
5878  *  001000               x1110000101
5879  *     rt -----
5880  *          rs -----
5881  *               rd -----
5882  */
5883 std::string NMD::DIV(uint64 instruction)
5884 {
5885     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5886     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5887     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5888
5889     std::string rd = GPR(copy(rd_value));
5890     std::string rs = GPR(copy(rs_value));
5891     std::string rt = GPR(copy(rt_value));
5892
5893     return img::format("DIV %s, %s, %s", rd, rs, rt);
5894 }
5895
5896
5897 /*
5898  *
5899  *
5900  *   3         2         1
5901  *  10987654321098765432109876543210
5902  *  001000               x1110000101
5903  *     rt -----
5904  *          rs -----
5905  *               rd -----
5906  */
5907 std::string NMD::DIV_D(uint64 instruction)
5908 {
5909     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5910     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5911     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5912
5913     std::string fd = FPR(copy(fd_value));
5914     std::string fs = FPR(copy(fs_value));
5915     std::string ft = FPR(copy(ft_value));
5916
5917     return img::format("DIV.D %s, %s, %s", fd, fs, ft);
5918 }
5919
5920
5921 /*
5922  *
5923  *
5924  *   3         2         1
5925  *  10987654321098765432109876543210
5926  *  001000               x1110000101
5927  *     rt -----
5928  *          rs -----
5929  *               rd -----
5930  */
5931 std::string NMD::DIV_S(uint64 instruction)
5932 {
5933     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5934     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5935     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5936
5937     std::string fd = FPR(copy(fd_value));
5938     std::string fs = FPR(copy(fs_value));
5939     std::string ft = FPR(copy(ft_value));
5940
5941     return img::format("DIV.S %s, %s, %s", fd, fs, ft);
5942 }
5943
5944
5945 /*
5946  *
5947  *
5948  *   3         2         1
5949  *  10987654321098765432109876543210
5950  *  001000               x1110000101
5951  *     rt -----
5952  *          rs -----
5953  *               rd -----
5954  */
5955 std::string NMD::DIVU(uint64 instruction)
5956 {
5957     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5958     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5959     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5960
5961     std::string rd = GPR(copy(rd_value));
5962     std::string rs = GPR(copy(rs_value));
5963     std::string rt = GPR(copy(rt_value));
5964
5965     return img::format("DIVU %s, %s, %s", rd, rs, rt);
5966 }
5967
5968
5969 /*
5970  *
5971  *
5972  *   3         2         1
5973  *  10987654321098765432109876543210
5974  *  001000               x1110000101
5975  *     rt -----
5976  *          rs -----
5977  *               rd -----
5978  */
5979 std::string NMD::DLSA(uint64 instruction)
5980 {
5981     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5982     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5983     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5984     uint64 u2_value = extract_u2_10_9(instruction);
5985
5986     std::string rd = GPR(copy(rd_value));
5987     std::string rs = GPR(copy(rs_value));
5988     std::string rt = GPR(copy(rt_value));
5989     std::string u2 = IMMEDIATE(copy(u2_value));
5990
5991     return img::format("DLSA %s, %s, %s, %s", rd, rs, rt, u2);
5992 }
5993
5994
5995 /*
5996  *
5997  *
5998  *   3         2         1
5999  *  10987654321098765432109876543210
6000  *  001000               x1110000101
6001  *     rt -----
6002  *          rs -----
6003  *               rd -----
6004  */
6005 std::string NMD::DLUI_48_(uint64 instruction)
6006 {
6007     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
6008     uint64 u_value = extract_u_31_to_0__s32(instruction);
6009
6010     std::string rt = GPR(copy(rt_value));
6011     std::string u = IMMEDIATE(copy(u_value));
6012
6013     return img::format("DLUI %s, %s", rt, u);
6014 }
6015
6016
6017 /*
6018  *
6019  *
6020  *   3         2         1
6021  *  10987654321098765432109876543210
6022  *  001000               x1110000101
6023  *     rt -----
6024  *          rs -----
6025  *               rd -----
6026  */
6027 std::string NMD::DMFC0(uint64 instruction)
6028 {
6029     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6030     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6031     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6032
6033     std::string rt = GPR(copy(rt_value));
6034     std::string c0s = CPR(copy(c0s_value));
6035     std::string sel = IMMEDIATE(copy(sel_value));
6036
6037     return img::format("DMFC0 %s, %s, %s", rt, c0s, sel);
6038 }
6039
6040
6041 /*
6042  *
6043  *
6044  *   3         2         1
6045  *  10987654321098765432109876543210
6046  *  001000               x1110000101
6047  *     rt -----
6048  *          rs -----
6049  *               rd -----
6050  */
6051 std::string NMD::DMFC1(uint64 instruction)
6052 {
6053     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6054     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
6055
6056     std::string rt = GPR(copy(rt_value));
6057     std::string fs = FPR(copy(fs_value));
6058
6059     return img::format("DMFC1 %s, %s", rt, fs);
6060 }
6061
6062
6063 /*
6064  *
6065  *
6066  *   3         2         1
6067  *  10987654321098765432109876543210
6068  *  001000               x1110000101
6069  *     rt -----
6070  *          rs -----
6071  *               rd -----
6072  */
6073 std::string NMD::DMFC2(uint64 instruction)
6074 {
6075     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6076     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
6077
6078     std::string rt = GPR(copy(rt_value));
6079     std::string cs = CPR(copy(cs_value));
6080
6081     return img::format("DMFC2 %s, %s", rt, cs);
6082 }
6083
6084
6085 /*
6086  *
6087  *
6088  *   3         2         1
6089  *  10987654321098765432109876543210
6090  *  001000               x1110000101
6091  *     rt -----
6092  *          rs -----
6093  *               rd -----
6094  */
6095 std::string NMD::DMFGC0(uint64 instruction)
6096 {
6097     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6098     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6099     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6100
6101     std::string rt = GPR(copy(rt_value));
6102     std::string c0s = CPR(copy(c0s_value));
6103     std::string sel = IMMEDIATE(copy(sel_value));
6104
6105     return img::format("DMFGC0 %s, %s, %s", rt, c0s, sel);
6106 }
6107
6108
6109 /*
6110  *
6111  *
6112  *   3         2         1
6113  *  10987654321098765432109876543210
6114  *  001000               x1110000101
6115  *     rt -----
6116  *          rs -----
6117  *               rd -----
6118  */
6119 std::string NMD::DMOD(uint64 instruction)
6120 {
6121     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6122     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6123     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6124
6125     std::string rd = GPR(copy(rd_value));
6126     std::string rs = GPR(copy(rs_value));
6127     std::string rt = GPR(copy(rt_value));
6128
6129     return img::format("DMOD %s, %s, %s", rd, rs, rt);
6130 }
6131
6132
6133 /*
6134  *
6135  *
6136  *   3         2         1
6137  *  10987654321098765432109876543210
6138  *  001000               x1110000101
6139  *     rt -----
6140  *          rs -----
6141  *               rd -----
6142  */
6143 std::string NMD::DMODU(uint64 instruction)
6144 {
6145     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6146     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6147     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6148
6149     std::string rd = GPR(copy(rd_value));
6150     std::string rs = GPR(copy(rs_value));
6151     std::string rt = GPR(copy(rt_value));
6152
6153     return img::format("DMODU %s, %s, %s", rd, rs, rt);
6154 }
6155
6156
6157 /*
6158  *
6159  *
6160  *   3         2         1
6161  *  10987654321098765432109876543210
6162  *  001000               x1110000101
6163  *     rt -----
6164  *          rs -----
6165  *               rd -----
6166  */
6167 std::string NMD::DMTC0(uint64 instruction)
6168 {
6169     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6170     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6171     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6172
6173     std::string rt = GPR(copy(rt_value));
6174     std::string c0s = CPR(copy(c0s_value));
6175     std::string sel = IMMEDIATE(copy(sel_value));
6176
6177     return img::format("DMTC0 %s, %s, %s", rt, c0s, sel);
6178 }
6179
6180
6181 /*
6182  *
6183  *
6184  *   3         2         1
6185  *  10987654321098765432109876543210
6186  *  001000               x1110000101
6187  *     rt -----
6188  *          rs -----
6189  *               rd -----
6190  */
6191 std::string NMD::DMTC1(uint64 instruction)
6192 {
6193     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6194     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
6195
6196     std::string rt = GPR(copy(rt_value));
6197     std::string fs = FPR(copy(fs_value));
6198
6199     return img::format("DMTC1 %s, %s", rt, fs);
6200 }
6201
6202
6203 /*
6204  *
6205  *
6206  *   3         2         1
6207  *  10987654321098765432109876543210
6208  *  001000               x1110000101
6209  *     rt -----
6210  *          rs -----
6211  *               rd -----
6212  */
6213 std::string NMD::DMTC2(uint64 instruction)
6214 {
6215     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6216     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
6217
6218     std::string rt = GPR(copy(rt_value));
6219     std::string cs = CPR(copy(cs_value));
6220
6221     return img::format("DMTC2 %s, %s", rt, cs);
6222 }
6223
6224
6225 /*
6226  *
6227  *
6228  *   3         2         1
6229  *  10987654321098765432109876543210
6230  *  001000               x1110000101
6231  *     rt -----
6232  *          rs -----
6233  *               rd -----
6234  */
6235 std::string NMD::DMTGC0(uint64 instruction)
6236 {
6237     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6238     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
6239     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
6240
6241     std::string rt = GPR(copy(rt_value));
6242     std::string c0s = CPR(copy(c0s_value));
6243     std::string sel = IMMEDIATE(copy(sel_value));
6244
6245     return img::format("DMTGC0 %s, %s, %s", rt, c0s, sel);
6246 }
6247
6248
6249 /*
6250  *
6251  *
6252  *   3         2         1
6253  *  10987654321098765432109876543210
6254  *  001000               x1110000101
6255  *     rt -----
6256  *          rs -----
6257  *               rd -----
6258  */
6259 std::string NMD::DMT(uint64 instruction)
6260 {
6261     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6262
6263     std::string rt = GPR(copy(rt_value));
6264
6265     return img::format("DMT %s", rt);
6266 }
6267
6268
6269 /*
6270  *
6271  *
6272  *   3         2         1
6273  *  10987654321098765432109876543210
6274  *  001000               x1110000101
6275  *     rt -----
6276  *          rs -----
6277  *               rd -----
6278  */
6279 std::string NMD::DMUH(uint64 instruction)
6280 {
6281     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6282     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6283     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6284
6285     std::string rd = GPR(copy(rd_value));
6286     std::string rs = GPR(copy(rs_value));
6287     std::string rt = GPR(copy(rt_value));
6288
6289     return img::format("DMUH %s, %s, %s", rd, rs, rt);
6290 }
6291
6292
6293 /*
6294  *
6295  *
6296  *   3         2         1
6297  *  10987654321098765432109876543210
6298  *  001000               x1110000101
6299  *     rt -----
6300  *          rs -----
6301  *               rd -----
6302  */
6303 std::string NMD::DMUHU(uint64 instruction)
6304 {
6305     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6306     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6307     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6308
6309     std::string rd = GPR(copy(rd_value));
6310     std::string rs = GPR(copy(rs_value));
6311     std::string rt = GPR(copy(rt_value));
6312
6313     return img::format("DMUHU %s, %s, %s", rd, rs, rt);
6314 }
6315
6316
6317 /*
6318  *
6319  *
6320  *   3         2         1
6321  *  10987654321098765432109876543210
6322  *  001000               x1110000101
6323  *     rt -----
6324  *          rs -----
6325  *               rd -----
6326  */
6327 std::string NMD::DMUL(uint64 instruction)
6328 {
6329     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6330     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6331     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6332
6333     std::string rd = GPR(copy(rd_value));
6334     std::string rs = GPR(copy(rs_value));
6335     std::string rt = GPR(copy(rt_value));
6336
6337     return img::format("DMUL %s, %s, %s", rd, rs, rt);
6338 }
6339
6340
6341 /*
6342  *
6343  *
6344  *   3         2         1
6345  *  10987654321098765432109876543210
6346  *  001000               x1110000101
6347  *     rt -----
6348  *          rs -----
6349  *               rd -----
6350  */
6351 std::string NMD::DMULU(uint64 instruction)
6352 {
6353     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6354     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6355     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6356
6357     std::string rd = GPR(copy(rd_value));
6358     std::string rs = GPR(copy(rs_value));
6359     std::string rt = GPR(copy(rt_value));
6360
6361     return img::format("DMULU %s, %s, %s", rd, rs, rt);
6362 }
6363
6364
6365 /*
6366  * [DSP] DPA.W.PH ac, rs, rt - Dot product with accumulate on
6367  *   vector integer halfword elements
6368  *
6369  *   3         2         1
6370  *  10987654321098765432109876543210
6371  *  001000            00000010111111
6372  *     rt -----
6373  *          rs -----
6374  *               ac --
6375  */
6376 std::string NMD::DPA_W_PH(uint64 instruction)
6377 {
6378     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6379     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6380     uint64 ac_value = extract_ac_15_14(instruction);
6381
6382     std::string ac = AC(copy(ac_value));
6383     std::string rs = GPR(copy(rs_value));
6384     std::string rt = GPR(copy(rt_value));
6385
6386     return img::format("DPA.W.PH %s, %s, %s", ac, rs, rt);
6387 }
6388
6389
6390 /*
6391  *
6392  *
6393  *   3         2         1
6394  *  10987654321098765432109876543210
6395  *  001000               x1110000101
6396  *     rt -----
6397  *          rs -----
6398  *               rd -----
6399  */
6400 std::string NMD::DPAQ_SA_L_W(uint64 instruction)
6401 {
6402     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6403     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6404     uint64 ac_value = extract_ac_15_14(instruction);
6405
6406     std::string ac = AC(copy(ac_value));
6407     std::string rs = GPR(copy(rs_value));
6408     std::string rt = GPR(copy(rt_value));
6409
6410     return img::format("DPAQ_SA.L.W %s, %s, %s", ac, rs, rt);
6411 }
6412
6413
6414 /*
6415  *
6416  *
6417  *   3         2         1
6418  *  10987654321098765432109876543210
6419  *  001000               x1110000101
6420  *     rt -----
6421  *          rs -----
6422  *               rd -----
6423  */
6424 std::string NMD::DPAQ_S_W_PH(uint64 instruction)
6425 {
6426     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6427     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6428     uint64 ac_value = extract_ac_15_14(instruction);
6429
6430     std::string ac = AC(copy(ac_value));
6431     std::string rs = GPR(copy(rs_value));
6432     std::string rt = GPR(copy(rt_value));
6433
6434     return img::format("DPAQ_S.W.PH %s, %s, %s", ac, rs, rt);
6435 }
6436
6437
6438 /*
6439  *
6440  *
6441  *   3         2         1
6442  *  10987654321098765432109876543210
6443  *  001000               x1110000101
6444  *     rt -----
6445  *          rs -----
6446  *               rd -----
6447  */
6448 std::string NMD::DPAQX_SA_W_PH(uint64 instruction)
6449 {
6450     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6451     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6452     uint64 ac_value = extract_ac_15_14(instruction);
6453
6454     std::string ac = AC(copy(ac_value));
6455     std::string rs = GPR(copy(rs_value));
6456     std::string rt = GPR(copy(rt_value));
6457
6458     return img::format("DPAQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6459 }
6460
6461
6462 /*
6463  *
6464  *
6465  *   3         2         1
6466  *  10987654321098765432109876543210
6467  *  001000               x1110000101
6468  *     rt -----
6469  *          rs -----
6470  *               rd -----
6471  */
6472 std::string NMD::DPAQX_S_W_PH(uint64 instruction)
6473 {
6474     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6475     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6476     uint64 ac_value = extract_ac_15_14(instruction);
6477
6478     std::string ac = AC(copy(ac_value));
6479     std::string rs = GPR(copy(rs_value));
6480     std::string rt = GPR(copy(rt_value));
6481
6482     return img::format("DPAQX_S.W.PH %s, %s, %s", ac, rs, rt);
6483 }
6484
6485
6486 /*
6487  *
6488  *
6489  *   3         2         1
6490  *  10987654321098765432109876543210
6491  *  001000               x1110000101
6492  *     rt -----
6493  *          rs -----
6494  *               rd -----
6495  */
6496 std::string NMD::DPAU_H_QBL(uint64 instruction)
6497 {
6498     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6499     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6500     uint64 ac_value = extract_ac_15_14(instruction);
6501
6502     std::string ac = AC(copy(ac_value));
6503     std::string rs = GPR(copy(rs_value));
6504     std::string rt = GPR(copy(rt_value));
6505
6506     return img::format("DPAU.H.QBL %s, %s, %s", ac, rs, rt);
6507 }
6508
6509
6510 /*
6511  *
6512  *
6513  *   3         2         1
6514  *  10987654321098765432109876543210
6515  *  001000               x1110000101
6516  *     rt -----
6517  *          rs -----
6518  *               rd -----
6519  */
6520 std::string NMD::DPAU_H_QBR(uint64 instruction)
6521 {
6522     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6523     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6524     uint64 ac_value = extract_ac_15_14(instruction);
6525
6526     std::string ac = AC(copy(ac_value));
6527     std::string rs = GPR(copy(rs_value));
6528     std::string rt = GPR(copy(rt_value));
6529
6530     return img::format("DPAU.H.QBR %s, %s, %s", ac, rs, rt);
6531 }
6532
6533
6534 /*
6535  *
6536  *
6537  *   3         2         1
6538  *  10987654321098765432109876543210
6539  *  001000               x1110000101
6540  *     rt -----
6541  *          rs -----
6542  *               rd -----
6543  */
6544 std::string NMD::DPAX_W_PH(uint64 instruction)
6545 {
6546     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6547     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6548     uint64 ac_value = extract_ac_15_14(instruction);
6549
6550     std::string ac = AC(copy(ac_value));
6551     std::string rs = GPR(copy(rs_value));
6552     std::string rt = GPR(copy(rt_value));
6553
6554     return img::format("DPAX.W.PH %s, %s, %s", ac, rs, rt);
6555 }
6556
6557
6558 /*
6559  *
6560  *
6561  *   3         2         1
6562  *  10987654321098765432109876543210
6563  *  001000               x1110000101
6564  *     rt -----
6565  *          rs -----
6566  *               rd -----
6567  */
6568 std::string NMD::DPS_W_PH(uint64 instruction)
6569 {
6570     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6571     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6572     uint64 ac_value = extract_ac_15_14(instruction);
6573
6574     std::string ac = AC(copy(ac_value));
6575     std::string rs = GPR(copy(rs_value));
6576     std::string rt = GPR(copy(rt_value));
6577
6578     return img::format("DPS.W.PH %s, %s, %s", ac, rs, rt);
6579 }
6580
6581
6582 /*
6583  *
6584  *
6585  *   3         2         1
6586  *  10987654321098765432109876543210
6587  *  001000               x1110000101
6588  *     rt -----
6589  *          rs -----
6590  *               rd -----
6591  */
6592 std::string NMD::DPSQ_SA_L_W(uint64 instruction)
6593 {
6594     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6595     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6596     uint64 ac_value = extract_ac_15_14(instruction);
6597
6598     std::string ac = AC(copy(ac_value));
6599     std::string rs = GPR(copy(rs_value));
6600     std::string rt = GPR(copy(rt_value));
6601
6602     return img::format("DPSQ_SA.L.W %s, %s, %s", ac, rs, rt);
6603 }
6604
6605
6606 /*
6607  *
6608  *
6609  *   3         2         1
6610  *  10987654321098765432109876543210
6611  *  001000               x1110000101
6612  *     rt -----
6613  *          rs -----
6614  *               rd -----
6615  */
6616 std::string NMD::DPSQ_S_W_PH(uint64 instruction)
6617 {
6618     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6619     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6620     uint64 ac_value = extract_ac_15_14(instruction);
6621
6622     std::string ac = AC(copy(ac_value));
6623     std::string rs = GPR(copy(rs_value));
6624     std::string rt = GPR(copy(rt_value));
6625
6626     return img::format("DPSQ_S.W.PH %s, %s, %s", ac, rs, rt);
6627 }
6628
6629
6630 /*
6631  *
6632  *
6633  *   3         2         1
6634  *  10987654321098765432109876543210
6635  *  001000               x1110000101
6636  *     rt -----
6637  *          rs -----
6638  *               rd -----
6639  */
6640 std::string NMD::DPSQX_SA_W_PH(uint64 instruction)
6641 {
6642     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6643     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6644     uint64 ac_value = extract_ac_15_14(instruction);
6645
6646     std::string ac = AC(copy(ac_value));
6647     std::string rs = GPR(copy(rs_value));
6648     std::string rt = GPR(copy(rt_value));
6649
6650     return img::format("DPSQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6651 }
6652
6653
6654 /*
6655  *
6656  *
6657  *   3         2         1
6658  *  10987654321098765432109876543210
6659  *  001000               x1110000101
6660  *     rt -----
6661  *          rs -----
6662  *               rd -----
6663  */
6664 std::string NMD::DPSQX_S_W_PH(uint64 instruction)
6665 {
6666     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6667     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6668     uint64 ac_value = extract_ac_15_14(instruction);
6669
6670     std::string ac = AC(copy(ac_value));
6671     std::string rs = GPR(copy(rs_value));
6672     std::string rt = GPR(copy(rt_value));
6673
6674     return img::format("DPSQX_S.W.PH %s, %s, %s", ac, rs, rt);
6675 }
6676
6677
6678 /*
6679  *
6680  *
6681  *   3         2         1
6682  *  10987654321098765432109876543210
6683  *  001000               x1110000101
6684  *     rt -----
6685  *          rs -----
6686  *               rd -----
6687  */
6688 std::string NMD::DPSU_H_QBL(uint64 instruction)
6689 {
6690     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6691     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6692     uint64 ac_value = extract_ac_15_14(instruction);
6693
6694     std::string ac = AC(copy(ac_value));
6695     std::string rs = GPR(copy(rs_value));
6696     std::string rt = GPR(copy(rt_value));
6697
6698     return img::format("DPSU.H.QBL %s, %s, %s", ac, rs, rt);
6699 }
6700
6701
6702 /*
6703  *
6704  *
6705  *   3         2         1
6706  *  10987654321098765432109876543210
6707  *  001000               x1110000101
6708  *     rt -----
6709  *          rs -----
6710  *               rd -----
6711  */
6712 std::string NMD::DPSU_H_QBR(uint64 instruction)
6713 {
6714     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6715     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6716     uint64 ac_value = extract_ac_15_14(instruction);
6717
6718     std::string ac = AC(copy(ac_value));
6719     std::string rs = GPR(copy(rs_value));
6720     std::string rt = GPR(copy(rt_value));
6721
6722     return img::format("DPSU.H.QBR %s, %s, %s", ac, rs, rt);
6723 }
6724
6725
6726 /*
6727  *
6728  *
6729  *   3         2         1
6730  *  10987654321098765432109876543210
6731  *  001000               x1110000101
6732  *     rt -----
6733  *          rs -----
6734  *               rd -----
6735  */
6736 std::string NMD::DPSX_W_PH(uint64 instruction)
6737 {
6738     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6739     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6740     uint64 ac_value = extract_ac_15_14(instruction);
6741
6742     std::string ac = AC(copy(ac_value));
6743     std::string rs = GPR(copy(rs_value));
6744     std::string rt = GPR(copy(rt_value));
6745
6746     return img::format("DPSX.W.PH %s, %s, %s", ac, rs, rt);
6747 }
6748
6749
6750 /*
6751  * DROTR -
6752  *
6753  *   3         2         1
6754  *  10987654321098765432109876543210
6755  *  001000               x1110000101
6756  *     rt -----
6757  *          rs -----
6758  *               rd -----
6759  */
6760 std::string NMD::DROTR(uint64 instruction)
6761 {
6762     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6763     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6764     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6765
6766     std::string rt = GPR(copy(rt_value));
6767     std::string rs = GPR(copy(rs_value));
6768     std::string shift = IMMEDIATE(copy(shift_value));
6769
6770     return img::format("DROTR %s, %s, %s", rt, rs, shift);
6771 }
6772
6773
6774 /*
6775  * DROTR[32] -
6776  *
6777  *   3         2         1
6778  *  10987654321098765432109876543210
6779  *  10o000          1100xxx0110
6780  *     rt -----
6781  *          rs -----
6782  *                       shift -----
6783  */
6784 std::string NMD::DROTR32(uint64 instruction)
6785 {
6786     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6787     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6788     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6789
6790     std::string rt = GPR(copy(rt_value));
6791     std::string rs = GPR(copy(rs_value));
6792     std::string shift = IMMEDIATE(copy(shift_value));
6793
6794     return img::format("DROTR32 %s, %s, %s", rt, rs, shift);
6795 }
6796
6797
6798 /*
6799  *
6800  *
6801  *   3         2         1
6802  *  10987654321098765432109876543210
6803  *  001000               x1110000101
6804  *     rt -----
6805  *          rs -----
6806  *               rd -----
6807  */
6808 std::string NMD::DROTRV(uint64 instruction)
6809 {
6810     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6811     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6812     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6813
6814     std::string rd = GPR(copy(rd_value));
6815     std::string rs = GPR(copy(rs_value));
6816     std::string rt = GPR(copy(rt_value));
6817
6818     return img::format("DROTRV %s, %s, %s", rd, rs, rt);
6819 }
6820
6821
6822 /*
6823  *
6824  *
6825  *   3         2         1
6826  *  10987654321098765432109876543210
6827  *  001000               x1110000101
6828  *     rt -----
6829  *          rs -----
6830  *               rd -----
6831  */
6832 std::string NMD::DROTX(uint64 instruction)
6833 {
6834     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6835     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6836     uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction);
6837     uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction);
6838
6839     std::string rt = GPR(copy(rt_value));
6840     std::string rs = GPR(copy(rs_value));
6841     std::string shift = IMMEDIATE(copy(shift_value));
6842     std::string shiftx = IMMEDIATE(copy(shiftx_value));
6843
6844     return img::format("DROTX %s, %s, %s, %s", rt, rs, shift, shiftx);
6845 }
6846
6847
6848 /*
6849  * DSLL -
6850  *
6851  *   3         2         1
6852  *  10987654321098765432109876543210
6853  *  10o000          1100xxx0000
6854  *     rt -----
6855  *          rs -----
6856  *                       shift -----
6857  */
6858 std::string NMD::DSLL(uint64 instruction)
6859 {
6860     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6861     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6862     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6863
6864     std::string rt = GPR(copy(rt_value));
6865     std::string rs = GPR(copy(rs_value));
6866     std::string shift = IMMEDIATE(copy(shift_value));
6867
6868     return img::format("DSLL %s, %s, %s", rt, rs, shift);
6869 }
6870
6871
6872 /*
6873  * DSLL[32] -
6874  *
6875  *   3         2         1
6876  *  10987654321098765432109876543210
6877  *  10o000          1100xxx0000
6878  *     rt -----
6879  *          rs -----
6880  *                       shift -----
6881  */
6882 std::string NMD::DSLL32(uint64 instruction)
6883 {
6884     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6885     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6886     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6887
6888     std::string rt = GPR(copy(rt_value));
6889     std::string rs = GPR(copy(rs_value));
6890     std::string shift = IMMEDIATE(copy(shift_value));
6891
6892     return img::format("DSLL32 %s, %s, %s", rt, rs, shift);
6893 }
6894
6895
6896 /*
6897  *
6898  *
6899  *   3         2         1
6900  *  10987654321098765432109876543210
6901  *  001000               x1110000101
6902  *     rt -----
6903  *          rs -----
6904  *               rd -----
6905  */
6906 std::string NMD::DSLLV(uint64 instruction)
6907 {
6908     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6909     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6910     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6911
6912     std::string rd = GPR(copy(rd_value));
6913     std::string rs = GPR(copy(rs_value));
6914     std::string rt = GPR(copy(rt_value));
6915
6916     return img::format("DSLLV %s, %s, %s", rd, rs, rt);
6917 }
6918
6919
6920 /*
6921  * DSRA -
6922  *
6923  *   3         2         1
6924  *  10987654321098765432109876543210
6925  *  10o000          1100xxx0100
6926  *     rt -----
6927  *          rs -----
6928  *                       shift -----
6929  */
6930 std::string NMD::DSRA(uint64 instruction)
6931 {
6932     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6933     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6934     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6935
6936     std::string rt = GPR(copy(rt_value));
6937     std::string rs = GPR(copy(rs_value));
6938     std::string shift = IMMEDIATE(copy(shift_value));
6939
6940     return img::format("DSRA %s, %s, %s", rt, rs, shift);
6941 }
6942
6943
6944 /*
6945  * DSRA[32] -
6946  *
6947  *   3         2         1
6948  *  10987654321098765432109876543210
6949  *  10o000          1100xxx0100
6950  *     rt -----
6951  *          rs -----
6952  *                       shift -----
6953  */
6954 std::string NMD::DSRA32(uint64 instruction)
6955 {
6956     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6957     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6958     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6959
6960     std::string rt = GPR(copy(rt_value));
6961     std::string rs = GPR(copy(rs_value));
6962     std::string shift = IMMEDIATE(copy(shift_value));
6963
6964     return img::format("DSRA32 %s, %s, %s", rt, rs, shift);
6965 }
6966
6967
6968 /*
6969  *
6970  *
6971  *   3         2         1
6972  *  10987654321098765432109876543210
6973  *  001000               x1110000101
6974  *     rt -----
6975  *          rs -----
6976  *               rd -----
6977  */
6978 std::string NMD::DSRAV(uint64 instruction)
6979 {
6980     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6981     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6982     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6983
6984     std::string rd = GPR(copy(rd_value));
6985     std::string rs = GPR(copy(rs_value));
6986     std::string rt = GPR(copy(rt_value));
6987
6988     return img::format("DSRAV %s, %s, %s", rd, rs, rt);
6989 }
6990
6991
6992 /*
6993  * DSRL -
6994  *
6995  *   3         2         1
6996  *  10987654321098765432109876543210
6997  *  10o000          1100xxx0100
6998  *     rt -----
6999  *          rs -----
7000  *                       shift -----
7001  */
7002 std::string NMD::DSRL(uint64 instruction)
7003 {
7004     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7005     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7006     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
7007
7008     std::string rt = GPR(copy(rt_value));
7009     std::string rs = GPR(copy(rs_value));
7010     std::string shift = IMMEDIATE(copy(shift_value));
7011
7012     return img::format("DSRL %s, %s, %s", rt, rs, shift);
7013 }
7014
7015
7016 /*
7017  * DSRL[32] -
7018  *
7019  *   3         2         1
7020  *  10987654321098765432109876543210
7021  *  10o000          1100xxx0010
7022  *     rt -----
7023  *          rs -----
7024  *                       shift -----
7025  */
7026 std::string NMD::DSRL32(uint64 instruction)
7027 {
7028     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7029     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7030     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
7031
7032     std::string rt = GPR(copy(rt_value));
7033     std::string rs = GPR(copy(rs_value));
7034     std::string shift = IMMEDIATE(copy(shift_value));
7035
7036     return img::format("DSRL32 %s, %s, %s", rt, rs, shift);
7037 }
7038
7039
7040 /*
7041  *
7042  *
7043  *   3         2         1
7044  *  10987654321098765432109876543210
7045  *  001000               x1110000101
7046  *     rt -----
7047  *          rs -----
7048  *               rd -----
7049  */
7050 std::string NMD::DSRLV(uint64 instruction)
7051 {
7052     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7053     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7054     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7055
7056     std::string rd = GPR(copy(rd_value));
7057     std::string rs = GPR(copy(rs_value));
7058     std::string rt = GPR(copy(rt_value));
7059
7060     return img::format("DSRLV %s, %s, %s", rd, rs, rt);
7061 }
7062
7063
7064 /*
7065  *
7066  *
7067  *   3         2         1
7068  *  10987654321098765432109876543210
7069  *  001000               x1110000101
7070  *     rt -----
7071  *          rs -----
7072  *               rd -----
7073  */
7074 std::string NMD::DSUB(uint64 instruction)
7075 {
7076     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7077     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7078     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7079
7080     std::string rd = GPR(copy(rd_value));
7081     std::string rs = GPR(copy(rs_value));
7082     std::string rt = GPR(copy(rt_value));
7083
7084     return img::format("DSUB %s, %s, %s", rd, rs, rt);
7085 }
7086
7087
7088 /*
7089  *
7090  *
7091  *   3         2         1
7092  *  10987654321098765432109876543210
7093  *  001000               x1110000101
7094  *     rt -----
7095  *          rs -----
7096  *               rd -----
7097  */
7098 std::string NMD::DSUBU(uint64 instruction)
7099 {
7100     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7101     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7102     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7103
7104     std::string rd = GPR(copy(rd_value));
7105     std::string rs = GPR(copy(rs_value));
7106     std::string rt = GPR(copy(rt_value));
7107
7108     return img::format("DSUBU %s, %s, %s", rd, rs, rt);
7109 }
7110
7111
7112 /*
7113  *
7114  *
7115  *   3         2         1
7116  *  10987654321098765432109876543210
7117  *  001000               x1110000101
7118  *     rt -----
7119  *          rs -----
7120  *               rd -----
7121  */
7122 std::string NMD::DVPE(uint64 instruction)
7123 {
7124     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7125
7126     std::string rt = GPR(copy(rt_value));
7127
7128     return img::format("DVPE %s", rt);
7129 }
7130
7131
7132 /*
7133  *
7134  *
7135  *   3         2         1
7136  *  10987654321098765432109876543210
7137  *  001000               x1110000101
7138  *     rt -----
7139  *          rs -----
7140  *               rd -----
7141  */
7142 std::string NMD::DVP(uint64 instruction)
7143 {
7144     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7145
7146     std::string rt = GPR(copy(rt_value));
7147
7148     return img::format("DVP %s", rt);
7149 }
7150
7151
7152 /*
7153  *
7154  *
7155  *   3         2         1
7156  *  10987654321098765432109876543210
7157  *  001000               x1110000101
7158  *     rt -----
7159  *          rs -----
7160  *               rd -----
7161  */
7162 std::string NMD::EHB(uint64 instruction)
7163 {
7164     (void)instruction;
7165
7166     return "EHB ";
7167 }
7168
7169
7170 /*
7171  *
7172  *
7173  *   3         2         1
7174  *  10987654321098765432109876543210
7175  *  001000               x1110000101
7176  *     rt -----
7177  *          rs -----
7178  *               rd -----
7179  */
7180 std::string NMD::EI(uint64 instruction)
7181 {
7182     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7183
7184     std::string rt = GPR(copy(rt_value));
7185
7186     return img::format("EI %s", rt);
7187 }
7188
7189
7190 /*
7191  *
7192  *
7193  *   3         2         1
7194  *  10987654321098765432109876543210
7195  *  001000               x1110000101
7196  *     rt -----
7197  *          rs -----
7198  *               rd -----
7199  */
7200 std::string NMD::EMT(uint64 instruction)
7201 {
7202     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7203
7204     std::string rt = GPR(copy(rt_value));
7205
7206     return img::format("EMT %s", rt);
7207 }
7208
7209
7210 /*
7211  *
7212  *
7213  *   3         2         1
7214  *  10987654321098765432109876543210
7215  *  001000               x1110000101
7216  *     rt -----
7217  *          rs -----
7218  *               rd -----
7219  */
7220 std::string NMD::ERET(uint64 instruction)
7221 {
7222     (void)instruction;
7223
7224     return "ERET ";
7225 }
7226
7227
7228 /*
7229  *
7230  *
7231  *   3         2         1
7232  *  10987654321098765432109876543210
7233  *  001000               x1110000101
7234  *     rt -----
7235  *          rs -----
7236  *               rd -----
7237  */
7238 std::string NMD::ERETNC(uint64 instruction)
7239 {
7240     (void)instruction;
7241
7242     return "ERETNC ";
7243 }
7244
7245
7246 /*
7247  *
7248  *
7249  *   3         2         1
7250  *  10987654321098765432109876543210
7251  *  001000               x1110000101
7252  *     rt -----
7253  *          rs -----
7254  *               rd -----
7255  */
7256 std::string NMD::EVP(uint64 instruction)
7257 {
7258     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7259
7260     std::string rt = GPR(copy(rt_value));
7261
7262     return img::format("EVP %s", rt);
7263 }
7264
7265
7266 /*
7267  *
7268  *
7269  *   3         2         1
7270  *  10987654321098765432109876543210
7271  *  001000               x1110000101
7272  *     rt -----
7273  *          rs -----
7274  *               rd -----
7275  */
7276 std::string NMD::EVPE(uint64 instruction)
7277 {
7278     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7279
7280     std::string rt = GPR(copy(rt_value));
7281
7282     return img::format("EVPE %s", rt);
7283 }
7284
7285
7286 /*
7287  *
7288  *
7289  *   3         2         1
7290  *  10987654321098765432109876543210
7291  *  001000               x1110000101
7292  *     rt -----
7293  *          rs -----
7294  *               rd -----
7295  */
7296 std::string NMD::EXT(uint64 instruction)
7297 {
7298     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7299     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7300     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7301     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7302
7303     std::string rt = GPR(copy(rt_value));
7304     std::string rs = GPR(copy(rs_value));
7305     std::string lsb = IMMEDIATE(copy(lsb_value));
7306     std::string msbd = IMMEDIATE(encode_msbd_from_size(msbd_value));
7307
7308     return img::format("EXT %s, %s, %s, %s", rt, rs, lsb, msbd);
7309 }
7310
7311
7312 /*
7313  *
7314  *
7315  *   3         2         1
7316  *  10987654321098765432109876543210
7317  *  001000               x1110000101
7318  *     rt -----
7319  *          rs -----
7320  *               rd -----
7321  */
7322 std::string NMD::EXTD(uint64 instruction)
7323 {
7324     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7325     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7326     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7327     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7328
7329     std::string rd = GPR(copy(rd_value));
7330     std::string rs = GPR(copy(rs_value));
7331     std::string rt = GPR(copy(rt_value));
7332     std::string shift = IMMEDIATE(copy(shift_value));
7333
7334     return img::format("EXTD %s, %s, %s, %s", rd, rs, rt, shift);
7335 }
7336
7337
7338 /*
7339  *
7340  *
7341  *   3         2         1
7342  *  10987654321098765432109876543210
7343  *  001000               x1110000101
7344  *     rt -----
7345  *          rs -----
7346  *               rd -----
7347  */
7348 std::string NMD::EXTD32(uint64 instruction)
7349 {
7350     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7351     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7352     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7353     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7354
7355     std::string rd = GPR(copy(rd_value));
7356     std::string rs = GPR(copy(rs_value));
7357     std::string rt = GPR(copy(rt_value));
7358     std::string shift = IMMEDIATE(copy(shift_value));
7359
7360     return img::format("EXTD32 %s, %s, %s, %s", rd, rs, rt, shift);
7361 }
7362
7363
7364 /*
7365  *
7366  *
7367  *   3         2         1
7368  *  10987654321098765432109876543210
7369  *  001000               x1110000101
7370  *     rt -----
7371  *          rs -----
7372  *               rd -----
7373  */
7374 std::string NMD::EXTPDP(uint64 instruction)
7375 {
7376     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7377     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7378     uint64 ac_value = extract_ac_15_14(instruction);
7379
7380     std::string rt = GPR(copy(rt_value));
7381     std::string ac = AC(copy(ac_value));
7382     std::string size = IMMEDIATE(copy(size_value));
7383
7384     return img::format("EXTPDP %s, %s, %s", rt, ac, size);
7385 }
7386
7387
7388 /*
7389  *
7390  *
7391  *   3         2         1
7392  *  10987654321098765432109876543210
7393  *  001000               x1110000101
7394  *     rt -----
7395  *          rs -----
7396  *               rd -----
7397  */
7398 std::string NMD::EXTPDPV(uint64 instruction)
7399 {
7400     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7401     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7402     uint64 ac_value = extract_ac_15_14(instruction);
7403
7404     std::string rt = GPR(copy(rt_value));
7405     std::string ac = AC(copy(ac_value));
7406     std::string rs = GPR(copy(rs_value));
7407
7408     return img::format("EXTPDPV %s, %s, %s", rt, ac, rs);
7409 }
7410
7411
7412 /*
7413  *
7414  *
7415  *   3         2         1
7416  *  10987654321098765432109876543210
7417  *  001000               x1110000101
7418  *     rt -----
7419  *          rs -----
7420  *               rd -----
7421  */
7422 std::string NMD::EXTP(uint64 instruction)
7423 {
7424     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7425     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7426     uint64 ac_value = extract_ac_15_14(instruction);
7427
7428     std::string rt = GPR(copy(rt_value));
7429     std::string ac = AC(copy(ac_value));
7430     std::string size = IMMEDIATE(copy(size_value));
7431
7432     return img::format("EXTP %s, %s, %s", rt, ac, size);
7433 }
7434
7435
7436 /*
7437  *
7438  *
7439  *   3         2         1
7440  *  10987654321098765432109876543210
7441  *  001000               x1110000101
7442  *     rt -----
7443  *          rs -----
7444  *               rd -----
7445  */
7446 std::string NMD::EXTPV(uint64 instruction)
7447 {
7448     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7449     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7450     uint64 ac_value = extract_ac_15_14(instruction);
7451
7452     std::string rt = GPR(copy(rt_value));
7453     std::string ac = AC(copy(ac_value));
7454     std::string rs = GPR(copy(rs_value));
7455
7456     return img::format("EXTPV %s, %s, %s", rt, ac, rs);
7457 }
7458
7459
7460 /*
7461  * [DSP] EXTR_RS.W rt, ac, shift - Extract word value from accumulator to GPR
7462  *   with right shift
7463  *
7464  *   3         2         1
7465  *  10987654321098765432109876543210
7466  *  001000            10111001111111
7467  *     rt -----
7468  *       shift -----
7469  *               ac --
7470  */
7471 std::string NMD::EXTR_RS_W(uint64 instruction)
7472 {
7473     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7474     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7475     uint64 ac_value = extract_ac_15_14(instruction);
7476
7477     std::string rt = GPR(copy(rt_value));
7478     std::string ac = AC(copy(ac_value));
7479     std::string shift = IMMEDIATE(copy(shift_value));
7480
7481     return img::format("EXTR_RS.W %s, %s, %s", rt, ac, shift);
7482 }
7483
7484
7485 /*
7486  * [DSP] EXTR_R.W rt, ac, shift - Extract word value from accumulator to GPR
7487  *   with right shift
7488  *
7489  *   3         2         1
7490  *  10987654321098765432109876543210
7491  *  001000            01111001111111
7492  *     rt -----
7493  *       shift -----
7494  *               ac --
7495  */
7496 std::string NMD::EXTR_R_W(uint64 instruction)
7497 {
7498     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7499     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7500     uint64 ac_value = extract_ac_15_14(instruction);
7501
7502     std::string rt = GPR(copy(rt_value));
7503     std::string ac = AC(copy(ac_value));
7504     std::string shift = IMMEDIATE(copy(shift_value));
7505
7506     return img::format("EXTR_R.W %s, %s, %s", rt, ac, shift);
7507 }
7508
7509
7510 /*
7511  * [DSP] EXTR_S.H rt, ac, shift - Extract halfword value from accumulator
7512  *   to GPR with right shift and saturate
7513  *
7514  *   3         2         1
7515  *  10987654321098765432109876543210
7516  *  001000            11111001111111
7517  *     rt -----
7518  *       shift -----
7519  *               ac --
7520  */
7521 std::string NMD::EXTR_S_H(uint64 instruction)
7522 {
7523     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7524     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7525     uint64 ac_value = extract_ac_15_14(instruction);
7526
7527     std::string rt = GPR(copy(rt_value));
7528     std::string ac = AC(copy(ac_value));
7529     std::string shift = IMMEDIATE(copy(shift_value));
7530
7531     return img::format("EXTR_S.H %s, %s, %s", rt, ac, shift);
7532 }
7533
7534
7535 /*
7536  * [DSP] EXTR.W rt, ac, shift - Extract word value from accumulator to GPR
7537  *   with right shift
7538  *
7539  *   3         2         1
7540  *  10987654321098765432109876543210
7541  *  001000            00111001111111
7542  *     rt -----
7543  *       shift -----
7544  *               ac --
7545  */
7546 std::string NMD::EXTR_W(uint64 instruction)
7547 {
7548     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7549     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7550     uint64 ac_value = extract_ac_15_14(instruction);
7551
7552     std::string rt = GPR(copy(rt_value));
7553     std::string ac = AC(copy(ac_value));
7554     std::string shift = IMMEDIATE(copy(shift_value));
7555
7556     return img::format("EXTR.W %s, %s, %s", rt, ac, shift);
7557 }
7558
7559
7560 /*
7561  * [DSP] EXTRV_RS.W rt, ac, rs - Extract word value with variable
7562  *   right shift from accumulator to GPR
7563  *
7564  *   3         2         1
7565  *  10987654321098765432109876543210
7566  *  001000            10111010111111
7567  *     rt -----
7568  *          rs -----
7569  *               ac --
7570  */
7571 std::string NMD::EXTRV_RS_W(uint64 instruction)
7572 {
7573     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7574     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7575     uint64 ac_value = extract_ac_15_14(instruction);
7576
7577     std::string rt = GPR(copy(rt_value));
7578     std::string ac = AC(copy(ac_value));
7579     std::string rs = GPR(copy(rs_value));
7580
7581     return img::format("EXTRV_RS.W %s, %s, %s", rt, ac, rs);
7582 }
7583
7584
7585 /*
7586  * [DSP] EXTRV_R.W rt, ac, rs - Extract word value with variable
7587  *   right shift from accumulator to GPR
7588  *
7589  *   3         2         1
7590  *  10987654321098765432109876543210
7591  *  001000            01111010111111
7592  *     rt -----
7593  *          rs -----
7594  *               ac --
7595  */
7596 std::string NMD::EXTRV_R_W(uint64 instruction)
7597 {
7598     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7599     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7600     uint64 ac_value = extract_ac_15_14(instruction);
7601
7602     std::string rt = GPR(copy(rt_value));
7603     std::string ac = AC(copy(ac_value));
7604     std::string rs = GPR(copy(rs_value));
7605
7606     return img::format("EXTRV_R.W %s, %s, %s", rt, ac, rs);
7607 }
7608
7609
7610 /*
7611  * [DSP] EXTRV_S.H rt, ac, rs - Extract halfword value variable from
7612  *   accumulator to GPR with right shift and saturate
7613  *
7614  *   3         2         1
7615  *  10987654321098765432109876543210
7616  *  001000            11111010111111
7617  *     rt -----
7618  *          rs -----
7619  *               ac --
7620  */
7621 std::string NMD::EXTRV_S_H(uint64 instruction)
7622 {
7623     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7624     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7625     uint64 ac_value = extract_ac_15_14(instruction);
7626
7627     std::string rt = GPR(copy(rt_value));
7628     std::string ac = AC(copy(ac_value));
7629     std::string rs = GPR(copy(rs_value));
7630
7631     return img::format("EXTRV_S.H %s, %s, %s", rt, ac, rs);
7632 }
7633
7634
7635 /*
7636  * [DSP] EXTRV.W rt, ac, rs - Extract word value with variable
7637  *   right shift from accumulator to GPR
7638  *
7639  *   3         2         1
7640  *  10987654321098765432109876543210
7641  *  001000            00111010111111
7642  *     rt -----
7643  *          rs -----
7644  *               ac --
7645  */
7646 std::string NMD::EXTRV_W(uint64 instruction)
7647 {
7648     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7649     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7650     uint64 ac_value = extract_ac_15_14(instruction);
7651
7652     std::string rt = GPR(copy(rt_value));
7653     std::string ac = AC(copy(ac_value));
7654     std::string rs = GPR(copy(rs_value));
7655
7656     return img::format("EXTRV.W %s, %s, %s", rt, ac, rs);
7657 }
7658
7659
7660 /*
7661  * EXTW - Extract Word
7662  *
7663  *   3         2         1
7664  *  10987654321098765432109876543210
7665  *  001000                    011111
7666  *     rt -----
7667  *          rs -----
7668  *               rd -----
7669  *                 shift -----
7670  */
7671 std::string NMD::EXTW(uint64 instruction)
7672 {
7673     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7674     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7675     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7676     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7677
7678     std::string rd = GPR(copy(rd_value));
7679     std::string rs = GPR(copy(rs_value));
7680     std::string rt = GPR(copy(rt_value));
7681     std::string shift = IMMEDIATE(copy(shift_value));
7682
7683     return img::format("EXTW %s, %s, %s, %s", rd, rs, rt, shift);
7684 }
7685
7686
7687 /*
7688  *
7689  *
7690  *   3         2         1
7691  *  10987654321098765432109876543210
7692  *  001000               x1110000101
7693  *     rt -----
7694  *          rs -----
7695  *               rd -----
7696  */
7697 std::string NMD::FLOOR_L_D(uint64 instruction)
7698 {
7699     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7700     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7701
7702     std::string ft = FPR(copy(ft_value));
7703     std::string fs = FPR(copy(fs_value));
7704
7705     return img::format("FLOOR.L.D %s, %s", ft, fs);
7706 }
7707
7708
7709 /*
7710  *
7711  *
7712  *   3         2         1
7713  *  10987654321098765432109876543210
7714  *  001000               x1110000101
7715  *     rt -----
7716  *          rs -----
7717  *               rd -----
7718  */
7719 std::string NMD::FLOOR_L_S(uint64 instruction)
7720 {
7721     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7722     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7723
7724     std::string ft = FPR(copy(ft_value));
7725     std::string fs = FPR(copy(fs_value));
7726
7727     return img::format("FLOOR.L.S %s, %s", ft, fs);
7728 }
7729
7730
7731 /*
7732  *
7733  *
7734  *   3         2         1
7735  *  10987654321098765432109876543210
7736  *  001000               x1110000101
7737  *     rt -----
7738  *          rs -----
7739  *               rd -----
7740  */
7741 std::string NMD::FLOOR_W_D(uint64 instruction)
7742 {
7743     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7744     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7745
7746     std::string ft = FPR(copy(ft_value));
7747     std::string fs = FPR(copy(fs_value));
7748
7749     return img::format("FLOOR.W.D %s, %s", ft, fs);
7750 }
7751
7752
7753 /*
7754  *
7755  *
7756  *   3         2         1
7757  *  10987654321098765432109876543210
7758  *  001000               x1110000101
7759  *     rt -----
7760  *          rs -----
7761  *               rd -----
7762  */
7763 std::string NMD::FLOOR_W_S(uint64 instruction)
7764 {
7765     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7766     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7767
7768     std::string ft = FPR(copy(ft_value));
7769     std::string fs = FPR(copy(fs_value));
7770
7771     return img::format("FLOOR.W.S %s, %s", ft, fs);
7772 }
7773
7774
7775 /*
7776  *
7777  *
7778  *   3         2         1
7779  *  10987654321098765432109876543210
7780  *  001000               x1110000101
7781  *     rt -----
7782  *          rs -----
7783  *               rd -----
7784  */
7785 std::string NMD::FORK(uint64 instruction)
7786 {
7787     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7788     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7789     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7790
7791     std::string rd = GPR(copy(rd_value));
7792     std::string rs = GPR(copy(rs_value));
7793     std::string rt = GPR(copy(rt_value));
7794
7795     return img::format("FORK %s, %s, %s", rd, rs, rt);
7796 }
7797
7798
7799 /*
7800  *
7801  *
7802  *   3         2         1
7803  *  10987654321098765432109876543210
7804  *  001000               x1110000101
7805  *     rt -----
7806  *          rs -----
7807  *               rd -----
7808  */
7809 std::string NMD::HYPCALL(uint64 instruction)
7810 {
7811     uint64 code_value = extract_code_17_to_0(instruction);
7812
7813     std::string code = IMMEDIATE(copy(code_value));
7814
7815     return img::format("HYPCALL %s", code);
7816 }
7817
7818
7819 /*
7820  *
7821  *
7822  *   3         2         1
7823  *  10987654321098765432109876543210
7824  *  001000               x1110000101
7825  *     rt -----
7826  *          rs -----
7827  *               rd -----
7828  */
7829 std::string NMD::HYPCALL_16_(uint64 instruction)
7830 {
7831     uint64 code_value = extract_code_1_0(instruction);
7832
7833     std::string code = IMMEDIATE(copy(code_value));
7834
7835     return img::format("HYPCALL %s", code);
7836 }
7837
7838
7839 /*
7840  *
7841  *
7842  *   3         2         1
7843  *  10987654321098765432109876543210
7844  *  001000               x1110000101
7845  *     rt -----
7846  *          rs -----
7847  *               rd -----
7848  */
7849 std::string NMD::INS(uint64 instruction)
7850 {
7851     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7852     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7853     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7854     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7855
7856     std::string rt = GPR(copy(rt_value));
7857     std::string rs = GPR(copy(rs_value));
7858     std::string pos = IMMEDIATE(encode_lsb_from_pos_and_size(lsb_value));
7859     std::string size = IMMEDIATE(encode_lsb_from_pos_and_size(msbd_value));
7860     /* !!!!!!!!!! - no conversion function */
7861
7862     return img::format("INS %s, %s, %s, %s", rt, rs, pos, size);
7863     /* hand edited */
7864 }
7865
7866
7867 /*
7868  * [DSP] INSV rt, rs - Insert bit field variable
7869  *
7870  *   3         2         1
7871  *  10987654321098765432109876543210
7872  *  001000          0100000100111111
7873  *     rt -----
7874  *          rs -----
7875  */
7876 std::string NMD::INSV(uint64 instruction)
7877 {
7878     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7879     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7880
7881     std::string rt = GPR(copy(rt_value));
7882     std::string rs = GPR(copy(rs_value));
7883
7884     return img::format("INSV %s, %s", rt, rs);
7885 }
7886
7887
7888 /*
7889  *
7890  *
7891  *   3         2         1
7892  *  10987654321098765432109876543210
7893  *  001000               x1110000101
7894  *     rt -----
7895  *          rs -----
7896  *               rd -----
7897  */
7898 std::string NMD::IRET(uint64 instruction)
7899 {
7900     (void)instruction;
7901
7902     return "IRET ";
7903 }
7904
7905
7906 /*
7907  *
7908  *
7909  *   3         2         1
7910  *  10987654321098765432109876543210
7911  *  001000               x1110000101
7912  *     rt -----
7913  *          rs -----
7914  *               rd -----
7915  */
7916 std::string NMD::JALRC_16_(uint64 instruction)
7917 {
7918     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7919
7920     std::string rt = GPR(copy(rt_value));
7921
7922     return img::format("JALRC $%d, %s", 31, rt);
7923 }
7924
7925
7926 /*
7927  *
7928  *
7929  *   3         2         1
7930  *  10987654321098765432109876543210
7931  *  001000               x1110000101
7932  *     rt -----
7933  *          rs -----
7934  *               rd -----
7935  */
7936 std::string NMD::JALRC_32_(uint64 instruction)
7937 {
7938     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7939     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7940
7941     std::string rt = GPR(copy(rt_value));
7942     std::string rs = GPR(copy(rs_value));
7943
7944     return img::format("JALRC %s, %s", rt, rs);
7945 }
7946
7947
7948 /*
7949  *
7950  *
7951  *   3         2         1
7952  *  10987654321098765432109876543210
7953  *  001000               x1110000101
7954  *     rt -----
7955  *          rs -----
7956  *               rd -----
7957  */
7958 std::string NMD::JALRC_HB(uint64 instruction)
7959 {
7960     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7961     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7962
7963     std::string rt = GPR(copy(rt_value));
7964     std::string rs = GPR(copy(rs_value));
7965
7966     return img::format("JALRC.HB %s, %s", rt, rs);
7967 }
7968
7969
7970 /*
7971  *
7972  *
7973  *   3         2         1
7974  *  10987654321098765432109876543210
7975  *  001000               x1110000101
7976  *     rt -----
7977  *          rs -----
7978  *               rd -----
7979  */
7980 std::string NMD::JRC(uint64 instruction)
7981 {
7982     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7983
7984     std::string rt = GPR(copy(rt_value));
7985
7986     return img::format("JRC %s", rt);
7987 }
7988
7989
7990 /*
7991  *
7992  *
7993  *   3         2         1
7994  *  10987654321098765432109876543210
7995  *  001000               x1110000101
7996  *     rt -----
7997  *          rs -----
7998  *               rd -----
7999  */
8000 std::string NMD::LB_16_(uint64 instruction)
8001 {
8002     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8003     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8004     uint64 u_value = extract_u_1_0(instruction);
8005
8006     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8007     std::string u = IMMEDIATE(copy(u_value));
8008     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8009
8010     return img::format("LB %s, %s(%s)", rt3, u, rs3);
8011 }
8012
8013
8014 /*
8015  *
8016  *
8017  *   3         2         1
8018  *  10987654321098765432109876543210
8019  *  001000               x1110000101
8020  *     rt -----
8021  *          rs -----
8022  *               rd -----
8023  */
8024 std::string NMD::LB_GP_(uint64 instruction)
8025 {
8026     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8027     uint64 u_value = extract_u_17_to_0(instruction);
8028
8029     std::string rt = GPR(copy(rt_value));
8030     std::string u = IMMEDIATE(copy(u_value));
8031
8032     return img::format("LB %s, %s($%d)", rt, u, 28);
8033 }
8034
8035
8036 /*
8037  *
8038  *
8039  *   3         2         1
8040  *  10987654321098765432109876543210
8041  *  001000               x1110000101
8042  *     rt -----
8043  *          rs -----
8044  *               rd -----
8045  */
8046 std::string NMD::LB_S9_(uint64 instruction)
8047 {
8048     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8049     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8050     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8051
8052     std::string rt = GPR(copy(rt_value));
8053     std::string s = IMMEDIATE(copy(s_value));
8054     std::string rs = GPR(copy(rs_value));
8055
8056     return img::format("LB %s, %s(%s)", rt, s, rs);
8057 }
8058
8059
8060 /*
8061  *
8062  *
8063  *   3         2         1
8064  *  10987654321098765432109876543210
8065  *  001000               x1110000101
8066  *     rt -----
8067  *          rs -----
8068  *               rd -----
8069  */
8070 std::string NMD::LB_U12_(uint64 instruction)
8071 {
8072     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8073     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8074     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8075
8076     std::string rt = GPR(copy(rt_value));
8077     std::string u = IMMEDIATE(copy(u_value));
8078     std::string rs = GPR(copy(rs_value));
8079
8080     return img::format("LB %s, %s(%s)", rt, u, rs);
8081 }
8082
8083
8084 /*
8085  *
8086  *
8087  *   3         2         1
8088  *  10987654321098765432109876543210
8089  *  001000               x1110000101
8090  *     rt -----
8091  *          rs -----
8092  *               rd -----
8093  */
8094 std::string NMD::LBE(uint64 instruction)
8095 {
8096     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8098     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8099
8100     std::string rt = GPR(copy(rt_value));
8101     std::string s = IMMEDIATE(copy(s_value));
8102     std::string rs = GPR(copy(rs_value));
8103
8104     return img::format("LBE %s, %s(%s)", rt, s, rs);
8105 }
8106
8107
8108 /*
8109  *
8110  *
8111  *   3         2         1
8112  *  10987654321098765432109876543210
8113  *  001000               x1110000101
8114  *     rt -----
8115  *          rs -----
8116  *               rd -----
8117  */
8118 std::string NMD::LBU_16_(uint64 instruction)
8119 {
8120     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8121     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8122     uint64 u_value = extract_u_1_0(instruction);
8123
8124     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8125     std::string u = IMMEDIATE(copy(u_value));
8126     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8127
8128     return img::format("LBU %s, %s(%s)", rt3, u, rs3);
8129 }
8130
8131
8132 /*
8133  *
8134  *
8135  *   3         2         1
8136  *  10987654321098765432109876543210
8137  *  001000               x1110000101
8138  *     rt -----
8139  *          rs -----
8140  *               rd -----
8141  */
8142 std::string NMD::LBU_GP_(uint64 instruction)
8143 {
8144     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8145     uint64 u_value = extract_u_17_to_0(instruction);
8146
8147     std::string rt = GPR(copy(rt_value));
8148     std::string u = IMMEDIATE(copy(u_value));
8149
8150     return img::format("LBU %s, %s($%d)", rt, u, 28);
8151 }
8152
8153
8154 /*
8155  *
8156  *
8157  *   3         2         1
8158  *  10987654321098765432109876543210
8159  *  001000               x1110000101
8160  *     rt -----
8161  *          rs -----
8162  *               rd -----
8163  */
8164 std::string NMD::LBU_S9_(uint64 instruction)
8165 {
8166     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8167     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8168     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8169
8170     std::string rt = GPR(copy(rt_value));
8171     std::string s = IMMEDIATE(copy(s_value));
8172     std::string rs = GPR(copy(rs_value));
8173
8174     return img::format("LBU %s, %s(%s)", rt, s, rs);
8175 }
8176
8177
8178 /*
8179  *
8180  *
8181  *   3         2         1
8182  *  10987654321098765432109876543210
8183  *  001000               x1110000101
8184  *     rt -----
8185  *          rs -----
8186  *               rd -----
8187  */
8188 std::string NMD::LBU_U12_(uint64 instruction)
8189 {
8190     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8191     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8192     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8193
8194     std::string rt = GPR(copy(rt_value));
8195     std::string u = IMMEDIATE(copy(u_value));
8196     std::string rs = GPR(copy(rs_value));
8197
8198     return img::format("LBU %s, %s(%s)", rt, u, rs);
8199 }
8200
8201
8202 /*
8203  *
8204  *
8205  *   3         2         1
8206  *  10987654321098765432109876543210
8207  *  001000               x1110000101
8208  *     rt -----
8209  *          rs -----
8210  *               rd -----
8211  */
8212 std::string NMD::LBUE(uint64 instruction)
8213 {
8214     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8215     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8216     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8217
8218     std::string rt = GPR(copy(rt_value));
8219     std::string s = IMMEDIATE(copy(s_value));
8220     std::string rs = GPR(copy(rs_value));
8221
8222     return img::format("LBUE %s, %s(%s)", rt, s, rs);
8223 }
8224
8225
8226 /*
8227  *
8228  *
8229  *   3         2         1
8230  *  10987654321098765432109876543210
8231  *  001000               x1110000101
8232  *     rt -----
8233  *          rs -----
8234  *               rd -----
8235  */
8236 std::string NMD::LBUX(uint64 instruction)
8237 {
8238     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8239     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8240     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8241
8242     std::string rd = GPR(copy(rd_value));
8243     std::string rs = GPR(copy(rs_value));
8244     std::string rt = GPR(copy(rt_value));
8245
8246     return img::format("LBUX %s, %s(%s)", rd, rs, rt);
8247 }
8248
8249
8250 /*
8251  *
8252  *
8253  *   3         2         1
8254  *  10987654321098765432109876543210
8255  *  001000               x1110000101
8256  *     rt -----
8257  *          rs -----
8258  *               rd -----
8259  */
8260 std::string NMD::LBX(uint64 instruction)
8261 {
8262     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8263     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8264     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8265
8266     std::string rd = GPR(copy(rd_value));
8267     std::string rs = GPR(copy(rs_value));
8268     std::string rt = GPR(copy(rt_value));
8269
8270     return img::format("LBX %s, %s(%s)", rd, rs, rt);
8271 }
8272
8273
8274 /*
8275  *
8276  *
8277  *   3         2         1
8278  *  10987654321098765432109876543210
8279  *  001000               x1110000101
8280  *     rt -----
8281  *          rs -----
8282  *               rd -----
8283  */
8284 std::string NMD::LD_GP_(uint64 instruction)
8285 {
8286     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8287     uint64 u_value = extract_u_20_to_3__s3(instruction);
8288
8289     std::string rt = GPR(copy(rt_value));
8290     std::string u = IMMEDIATE(copy(u_value));
8291
8292     return img::format("LD %s, %s($%d)", rt, u, 28);
8293 }
8294
8295
8296 /*
8297  *
8298  *
8299  *   3         2         1
8300  *  10987654321098765432109876543210
8301  *  001000               x1110000101
8302  *     rt -----
8303  *          rs -----
8304  *               rd -----
8305  */
8306 std::string NMD::LD_S9_(uint64 instruction)
8307 {
8308     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8309     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8310     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8311
8312     std::string rt = GPR(copy(rt_value));
8313     std::string s = IMMEDIATE(copy(s_value));
8314     std::string rs = GPR(copy(rs_value));
8315
8316     return img::format("LD %s, %s(%s)", rt, s, rs);
8317 }
8318
8319
8320 /*
8321  *
8322  *
8323  *   3         2         1
8324  *  10987654321098765432109876543210
8325  *  001000               x1110000101
8326  *     rt -----
8327  *          rs -----
8328  *               rd -----
8329  */
8330 std::string NMD::LD_U12_(uint64 instruction)
8331 {
8332     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8333     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8334     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8335
8336     std::string rt = GPR(copy(rt_value));
8337     std::string u = IMMEDIATE(copy(u_value));
8338     std::string rs = GPR(copy(rs_value));
8339
8340     return img::format("LD %s, %s(%s)", rt, u, rs);
8341 }
8342
8343
8344 /*
8345  *
8346  *
8347  *   3         2         1
8348  *  10987654321098765432109876543210
8349  *  001000               x1110000101
8350  *     rt -----
8351  *          rs -----
8352  *               rd -----
8353  */
8354 std::string NMD::LDC1_GP_(uint64 instruction)
8355 {
8356     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8357     uint64 u_value = extract_u_17_to_2__s2(instruction);
8358
8359     std::string ft = FPR(copy(ft_value));
8360     std::string u = IMMEDIATE(copy(u_value));
8361
8362     return img::format("LDC1 %s, %s($%d)", ft, u, 28);
8363 }
8364
8365
8366 /*
8367  *
8368  *
8369  *   3         2         1
8370  *  10987654321098765432109876543210
8371  *  001000               x1110000101
8372  *     rt -----
8373  *          rs -----
8374  *               rd -----
8375  */
8376 std::string NMD::LDC1_S9_(uint64 instruction)
8377 {
8378     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8379     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8380     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8381
8382     std::string ft = FPR(copy(ft_value));
8383     std::string s = IMMEDIATE(copy(s_value));
8384     std::string rs = GPR(copy(rs_value));
8385
8386     return img::format("LDC1 %s, %s(%s)", ft, s, rs);
8387 }
8388
8389
8390 /*
8391  *
8392  *
8393  *   3         2         1
8394  *  10987654321098765432109876543210
8395  *  001000               x1110000101
8396  *     rt -----
8397  *          rs -----
8398  *               rd -----
8399  */
8400 std::string NMD::LDC1_U12_(uint64 instruction)
8401 {
8402     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8403     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8404     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8405
8406     std::string ft = FPR(copy(ft_value));
8407     std::string u = IMMEDIATE(copy(u_value));
8408     std::string rs = GPR(copy(rs_value));
8409
8410     return img::format("LDC1 %s, %s(%s)", ft, u, rs);
8411 }
8412
8413
8414 /*
8415  *
8416  *
8417  *   3         2         1
8418  *  10987654321098765432109876543210
8419  *  001000               x1110000101
8420  *     rt -----
8421  *          rs -----
8422  *               rd -----
8423  */
8424 std::string NMD::LDC1XS(uint64 instruction)
8425 {
8426     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8427     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8428     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8429
8430     std::string ft = FPR(copy(ft_value));
8431     std::string rs = GPR(copy(rs_value));
8432     std::string rt = GPR(copy(rt_value));
8433
8434     return img::format("LDC1XS %s, %s(%s)", ft, rs, rt);
8435 }
8436
8437
8438 /*
8439  *
8440  *
8441  *   3         2         1
8442  *  10987654321098765432109876543210
8443  *  001000               x1110000101
8444  *     rt -----
8445  *          rs -----
8446  *               rd -----
8447  */
8448 std::string NMD::LDC1X(uint64 instruction)
8449 {
8450     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8451     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8452     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8453
8454     std::string ft = FPR(copy(ft_value));
8455     std::string rs = GPR(copy(rs_value));
8456     std::string rt = GPR(copy(rt_value));
8457
8458     return img::format("LDC1X %s, %s(%s)", ft, rs, rt);
8459 }
8460
8461
8462 /*
8463  *
8464  *
8465  *   3         2         1
8466  *  10987654321098765432109876543210
8467  *  001000               x1110000101
8468  *     rt -----
8469  *          rs -----
8470  *               rd -----
8471  */
8472 std::string NMD::LDC2(uint64 instruction)
8473 {
8474     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
8475     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8476     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8477
8478     std::string ct = CPR(copy(ct_value));
8479     std::string s = IMMEDIATE(copy(s_value));
8480     std::string rs = GPR(copy(rs_value));
8481
8482     return img::format("LDC2 %s, %s(%s)", ct, s, rs);
8483 }
8484
8485
8486 /*
8487  *
8488  *
8489  *   3         2         1
8490  *  10987654321098765432109876543210
8491  *  001000               x1110000101
8492  *     rt -----
8493  *          rs -----
8494  *               rd -----
8495  */
8496 std::string NMD::LDM(uint64 instruction)
8497 {
8498     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8499     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8500     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8501     uint64 count3_value = extract_count3_14_13_12(instruction);
8502
8503     std::string rt = GPR(copy(rt_value));
8504     std::string s = IMMEDIATE(copy(s_value));
8505     std::string rs = GPR(copy(rs_value));
8506     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
8507
8508     return img::format("LDM %s, %s(%s), %s", rt, s, rs, count3);
8509 }
8510
8511
8512 /*
8513  *
8514  *
8515  *   3         2         1
8516  *  10987654321098765432109876543210
8517  *  001000               x1110000101
8518  *     rt -----
8519  *          rs -----
8520  *               rd -----
8521  */
8522 std::string NMD::LDPC_48_(uint64 instruction)
8523 {
8524     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8525     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8526
8527     std::string rt = GPR(copy(rt_value));
8528     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
8529
8530     return img::format("LDPC %s, %s", rt, s);
8531 }
8532
8533
8534 /*
8535  *
8536  *
8537  *   3         2         1
8538  *  10987654321098765432109876543210
8539  *  001000               x1110000101
8540  *     rt -----
8541  *          rs -----
8542  *               rd -----
8543  */
8544 std::string NMD::LDX(uint64 instruction)
8545 {
8546     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8547     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8548     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8549
8550     std::string rd = GPR(copy(rd_value));
8551     std::string rs = GPR(copy(rs_value));
8552     std::string rt = GPR(copy(rt_value));
8553
8554     return img::format("LDX %s, %s(%s)", rd, rs, rt);
8555 }
8556
8557
8558 /*
8559  *
8560  *
8561  *   3         2         1
8562  *  10987654321098765432109876543210
8563  *  001000               x1110000101
8564  *     rt -----
8565  *          rs -----
8566  *               rd -----
8567  */
8568 std::string NMD::LDXS(uint64 instruction)
8569 {
8570     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8571     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8572     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8573
8574     std::string rd = GPR(copy(rd_value));
8575     std::string rs = GPR(copy(rs_value));
8576     std::string rt = GPR(copy(rt_value));
8577
8578     return img::format("LDXS %s, %s(%s)", rd, rs, rt);
8579 }
8580
8581
8582 /*
8583  *
8584  *
8585  *   3         2         1
8586  *  10987654321098765432109876543210
8587  *  001000               x1110000101
8588  *     rt -----
8589  *          rs -----
8590  *               rd -----
8591  */
8592 std::string NMD::LH_16_(uint64 instruction)
8593 {
8594     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8595     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8596     uint64 u_value = extract_u_2_1__s1(instruction);
8597
8598     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8599     std::string u = IMMEDIATE(copy(u_value));
8600     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8601
8602     return img::format("LH %s, %s(%s)", rt3, u, rs3);
8603 }
8604
8605
8606 /*
8607  *
8608  *
8609  *   3         2         1
8610  *  10987654321098765432109876543210
8611  *  001000               x1110000101
8612  *     rt -----
8613  *          rs -----
8614  *               rd -----
8615  */
8616 std::string NMD::LH_GP_(uint64 instruction)
8617 {
8618     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8619     uint64 u_value = extract_u_17_to_1__s1(instruction);
8620
8621     std::string rt = GPR(copy(rt_value));
8622     std::string u = IMMEDIATE(copy(u_value));
8623
8624     return img::format("LH %s, %s($%d)", rt, u, 28);
8625 }
8626
8627
8628 /*
8629  *
8630  *
8631  *   3         2         1
8632  *  10987654321098765432109876543210
8633  *  001000               x1110000101
8634  *     rt -----
8635  *          rs -----
8636  *               rd -----
8637  */
8638 std::string NMD::LH_S9_(uint64 instruction)
8639 {
8640     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8641     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8642     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8643
8644     std::string rt = GPR(copy(rt_value));
8645     std::string s = IMMEDIATE(copy(s_value));
8646     std::string rs = GPR(copy(rs_value));
8647
8648     return img::format("LH %s, %s(%s)", rt, s, rs);
8649 }
8650
8651
8652 /*
8653  *
8654  *
8655  *   3         2         1
8656  *  10987654321098765432109876543210
8657  *  001000               x1110000101
8658  *     rt -----
8659  *          rs -----
8660  *               rd -----
8661  */
8662 std::string NMD::LH_U12_(uint64 instruction)
8663 {
8664     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8665     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8666     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8667
8668     std::string rt = GPR(copy(rt_value));
8669     std::string u = IMMEDIATE(copy(u_value));
8670     std::string rs = GPR(copy(rs_value));
8671
8672     return img::format("LH %s, %s(%s)", rt, u, rs);
8673 }
8674
8675
8676 /*
8677  *
8678  *
8679  *   3         2         1
8680  *  10987654321098765432109876543210
8681  *  001000               x1110000101
8682  *     rt -----
8683  *          rs -----
8684  *               rd -----
8685  */
8686 std::string NMD::LHE(uint64 instruction)
8687 {
8688     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8689     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8690     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8691
8692     std::string rt = GPR(copy(rt_value));
8693     std::string s = IMMEDIATE(copy(s_value));
8694     std::string rs = GPR(copy(rs_value));
8695
8696     return img::format("LHE %s, %s(%s)", rt, s, rs);
8697 }
8698
8699
8700 /*
8701  *
8702  *
8703  *   3         2         1
8704  *  10987654321098765432109876543210
8705  *  001000               x1110000101
8706  *     rt -----
8707  *          rs -----
8708  *               rd -----
8709  */
8710 std::string NMD::LHU_16_(uint64 instruction)
8711 {
8712     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8713     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8714     uint64 u_value = extract_u_2_1__s1(instruction);
8715
8716     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8717     std::string u = IMMEDIATE(copy(u_value));
8718     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
8719
8720     return img::format("LHU %s, %s(%s)", rt3, u, rs3);
8721 }
8722
8723
8724 /*
8725  *
8726  *
8727  *   3         2         1
8728  *  10987654321098765432109876543210
8729  *  001000               x1110000101
8730  *     rt -----
8731  *          rs -----
8732  *               rd -----
8733  */
8734 std::string NMD::LHU_GP_(uint64 instruction)
8735 {
8736     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8737     uint64 u_value = extract_u_17_to_1__s1(instruction);
8738
8739     std::string rt = GPR(copy(rt_value));
8740     std::string u = IMMEDIATE(copy(u_value));
8741
8742     return img::format("LHU %s, %s($%d)", rt, u, 28);
8743 }
8744
8745
8746 /*
8747  *
8748  *
8749  *   3         2         1
8750  *  10987654321098765432109876543210
8751  *  001000               x1110000101
8752  *     rt -----
8753  *          rs -----
8754  *               rd -----
8755  */
8756 std::string NMD::LHU_S9_(uint64 instruction)
8757 {
8758     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8759     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8760     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8761
8762     std::string rt = GPR(copy(rt_value));
8763     std::string s = IMMEDIATE(copy(s_value));
8764     std::string rs = GPR(copy(rs_value));
8765
8766     return img::format("LHU %s, %s(%s)", rt, s, rs);
8767 }
8768
8769
8770 /*
8771  *
8772  *
8773  *   3         2         1
8774  *  10987654321098765432109876543210
8775  *  001000               x1110000101
8776  *     rt -----
8777  *          rs -----
8778  *               rd -----
8779  */
8780 std::string NMD::LHU_U12_(uint64 instruction)
8781 {
8782     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8783     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8784     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8785
8786     std::string rt = GPR(copy(rt_value));
8787     std::string u = IMMEDIATE(copy(u_value));
8788     std::string rs = GPR(copy(rs_value));
8789
8790     return img::format("LHU %s, %s(%s)", rt, u, rs);
8791 }
8792
8793
8794 /*
8795  *
8796  *
8797  *   3         2         1
8798  *  10987654321098765432109876543210
8799  *  001000               x1110000101
8800  *     rt -----
8801  *          rs -----
8802  *               rd -----
8803  */
8804 std::string NMD::LHUE(uint64 instruction)
8805 {
8806     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8807     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8808     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8809
8810     std::string rt = GPR(copy(rt_value));
8811     std::string s = IMMEDIATE(copy(s_value));
8812     std::string rs = GPR(copy(rs_value));
8813
8814     return img::format("LHUE %s, %s(%s)", rt, s, rs);
8815 }
8816
8817
8818 /*
8819  *
8820  *
8821  *   3         2         1
8822  *  10987654321098765432109876543210
8823  *  001000               x1110000101
8824  *     rt -----
8825  *          rs -----
8826  *               rd -----
8827  */
8828 std::string NMD::LHUX(uint64 instruction)
8829 {
8830     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8831     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8832     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8833
8834     std::string rd = GPR(copy(rd_value));
8835     std::string rs = GPR(copy(rs_value));
8836     std::string rt = GPR(copy(rt_value));
8837
8838     return img::format("LHUX %s, %s(%s)", rd, rs, rt);
8839 }
8840
8841
8842 /*
8843  *
8844  *
8845  *   3         2         1
8846  *  10987654321098765432109876543210
8847  *  001000               x1110000101
8848  *     rt -----
8849  *          rs -----
8850  *               rd -----
8851  */
8852 std::string NMD::LHUXS(uint64 instruction)
8853 {
8854     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8855     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8856     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8857
8858     std::string rd = GPR(copy(rd_value));
8859     std::string rs = GPR(copy(rs_value));
8860     std::string rt = GPR(copy(rt_value));
8861
8862     return img::format("LHUXS %s, %s(%s)", rd, rs, rt);
8863 }
8864
8865
8866 /*
8867  *
8868  *
8869  *   3         2         1
8870  *  10987654321098765432109876543210
8871  *  001000               x1110000101
8872  *     rt -----
8873  *          rs -----
8874  *               rd -----
8875  */
8876 std::string NMD::LHXS(uint64 instruction)
8877 {
8878     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8879     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8880     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8881
8882     std::string rd = GPR(copy(rd_value));
8883     std::string rs = GPR(copy(rs_value));
8884     std::string rt = GPR(copy(rt_value));
8885
8886     return img::format("LHXS %s, %s(%s)", rd, rs, rt);
8887 }
8888
8889
8890 /*
8891  *
8892  *
8893  *   3         2         1
8894  *  10987654321098765432109876543210
8895  *  001000               x1110000101
8896  *     rt -----
8897  *          rs -----
8898  *               rd -----
8899  */
8900 std::string NMD::LHX(uint64 instruction)
8901 {
8902     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8903     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8904     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8905
8906     std::string rd = GPR(copy(rd_value));
8907     std::string rs = GPR(copy(rs_value));
8908     std::string rt = GPR(copy(rt_value));
8909
8910     return img::format("LHX %s, %s(%s)", rd, rs, rt);
8911 }
8912
8913
8914 /*
8915  *
8916  *
8917  *   3         2         1
8918  *  10987654321098765432109876543210
8919  *  001000               x1110000101
8920  *     rt -----
8921  *          rs -----
8922  *               rd -----
8923  */
8924 std::string NMD::LI_16_(uint64 instruction)
8925 {
8926     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8927     uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction);
8928
8929     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
8930     std::string eu = IMMEDIATE(encode_eu_from_s_li16(eu_value));
8931
8932     return img::format("LI %s, %s", rt3, eu);
8933 }
8934
8935
8936 /*
8937  *
8938  *
8939  *   3         2         1
8940  *  10987654321098765432109876543210
8941  *  001000               x1110000101
8942  *     rt -----
8943  *          rs -----
8944  *               rd -----
8945  */
8946 std::string NMD::LI_48_(uint64 instruction)
8947 {
8948     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8949     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8950
8951     std::string rt = GPR(copy(rt_value));
8952     std::string s = IMMEDIATE(copy(s_value));
8953
8954     return img::format("LI %s, %s", rt, s);
8955 }
8956
8957
8958 /*
8959  *
8960  *
8961  *   3         2         1
8962  *  10987654321098765432109876543210
8963  *  001000               x1110000101
8964  *     rt -----
8965  *          rs -----
8966  *               rd -----
8967  */
8968 std::string NMD::LL(uint64 instruction)
8969 {
8970     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8971     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8972     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
8973
8974     std::string rt = GPR(copy(rt_value));
8975     std::string s = IMMEDIATE(copy(s_value));
8976     std::string rs = GPR(copy(rs_value));
8977
8978     return img::format("LL %s, %s(%s)", rt, s, rs);
8979 }
8980
8981
8982 /*
8983  *
8984  *
8985  *   3         2         1
8986  *  10987654321098765432109876543210
8987  *  001000               x1110000101
8988  *     rt -----
8989  *          rs -----
8990  *               rd -----
8991  */
8992 std::string NMD::LLD(uint64 instruction)
8993 {
8994     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8995     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8996     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
8997
8998     std::string rt = GPR(copy(rt_value));
8999     std::string s = IMMEDIATE(copy(s_value));
9000     std::string rs = GPR(copy(rs_value));
9001
9002     return img::format("LLD %s, %s(%s)", rt, s, rs);
9003 }
9004
9005
9006 /*
9007  *
9008  *
9009  *   3         2         1
9010  *  10987654321098765432109876543210
9011  *  001000               x1110000101
9012  *     rt -----
9013  *          rs -----
9014  *               rd -----
9015  */
9016 std::string NMD::LLDP(uint64 instruction)
9017 {
9018     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9019     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9020     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9021
9022     std::string rt = GPR(copy(rt_value));
9023     std::string ru = GPR(copy(ru_value));
9024     std::string rs = GPR(copy(rs_value));
9025
9026     return img::format("LLDP %s, %s, (%s)", rt, ru, rs);
9027 }
9028
9029
9030 /*
9031  *
9032  *
9033  *   3         2         1
9034  *  10987654321098765432109876543210
9035  *  001000               x1110000101
9036  *     rt -----
9037  *          rs -----
9038  *               rd -----
9039  */
9040 std::string NMD::LLE(uint64 instruction)
9041 {
9042     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9043     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9044     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
9045
9046     std::string rt = GPR(copy(rt_value));
9047     std::string s = IMMEDIATE(copy(s_value));
9048     std::string rs = GPR(copy(rs_value));
9049
9050     return img::format("LLE %s, %s(%s)", rt, s, rs);
9051 }
9052
9053
9054 /*
9055  *
9056  *
9057  *   3         2         1
9058  *  10987654321098765432109876543210
9059  *  001000               x1110000101
9060  *     rt -----
9061  *          rs -----
9062  *               rd -----
9063  */
9064 std::string NMD::LLWP(uint64 instruction)
9065 {
9066     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9067     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9068     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9069
9070     std::string rt = GPR(copy(rt_value));
9071     std::string ru = GPR(copy(ru_value));
9072     std::string rs = GPR(copy(rs_value));
9073
9074     return img::format("LLWP %s, %s, (%s)", rt, ru, rs);
9075 }
9076
9077
9078 /*
9079  *
9080  *
9081  *   3         2         1
9082  *  10987654321098765432109876543210
9083  *  001000               x1110000101
9084  *     rt -----
9085  *          rs -----
9086  *               rd -----
9087  */
9088 std::string NMD::LLWPE(uint64 instruction)
9089 {
9090     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9091     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9092     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
9093
9094     std::string rt = GPR(copy(rt_value));
9095     std::string ru = GPR(copy(ru_value));
9096     std::string rs = GPR(copy(rs_value));
9097
9098     return img::format("LLWPE %s, %s, (%s)", rt, ru, rs);
9099 }
9100
9101
9102 /*
9103  *
9104  *
9105  *   3         2         1
9106  *  10987654321098765432109876543210
9107  *  001000               x1110000101
9108  *     rt -----
9109  *          rs -----
9110  *               rd -----
9111  */
9112 std::string NMD::LSA(uint64 instruction)
9113 {
9114     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9115     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9116     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9117     uint64 u2_value = extract_u2_10_9(instruction);
9118
9119     std::string rd = GPR(copy(rd_value));
9120     std::string rs = GPR(copy(rs_value));
9121     std::string rt = GPR(copy(rt_value));
9122     std::string u2 = IMMEDIATE(copy(u2_value));
9123
9124     return img::format("LSA %s, %s, %s, %s", rd, rs, rt, u2);
9125 }
9126
9127
9128 /*
9129  *
9130  *
9131  *   3         2         1
9132  *  10987654321098765432109876543210
9133  *  001000               x1110000101
9134  *     rt -----
9135  *          rs -----
9136  *               rd -----
9137  */
9138 std::string NMD::LUI(uint64 instruction)
9139 {
9140     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9141     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
9142
9143     std::string rt = GPR(copy(rt_value));
9144     std::string s = IMMEDIATE(copy(s_value));
9145
9146     return img::format("LUI %s, %%hi(%s)", rt, s);
9147 }
9148
9149
9150 /*
9151  *
9152  *
9153  *   3         2         1
9154  *  10987654321098765432109876543210
9155  *  001000               x1110000101
9156  *     rt -----
9157  *          rs -----
9158  *               rd -----
9159  */
9160 std::string NMD::LW_16_(uint64 instruction)
9161 {
9162     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9163     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9164     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
9165
9166     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
9167     std::string u = IMMEDIATE(copy(u_value));
9168     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
9169
9170     return img::format("LW %s, %s(%s)", rt3, u, rs3);
9171 }
9172
9173
9174 /*
9175  *
9176  *
9177  *   3         2         1
9178  *  10987654321098765432109876543210
9179  *  001000               x1110000101
9180  *     rt -----
9181  *          rs -----
9182  *               rd -----
9183  */
9184 std::string NMD::LW_4X4_(uint64 instruction)
9185 {
9186     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
9187     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
9188     uint64 u_value = extract_u_3_8__s2(instruction);
9189
9190     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
9191     std::string u = IMMEDIATE(copy(u_value));
9192     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
9193
9194     return img::format("LW %s, %s(%s)", rt4, u, rs4);
9195 }
9196
9197
9198 /*
9199  *
9200  *
9201  *   3         2         1
9202  *  10987654321098765432109876543210
9203  *  001000               x1110000101
9204  *     rt -----
9205  *          rs -----
9206  *               rd -----
9207  */
9208 std::string NMD::LW_GP_(uint64 instruction)
9209 {
9210     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9211     uint64 u_value = extract_u_20_to_2__s2(instruction);
9212
9213     std::string rt = GPR(copy(rt_value));
9214     std::string u = IMMEDIATE(copy(u_value));
9215
9216     return img::format("LW %s, %s($%d)", rt, u, 28);
9217 }
9218
9219
9220 /*
9221  *
9222  *
9223  *   3         2         1
9224  *  10987654321098765432109876543210
9225  *  001000               x1110000101
9226  *     rt -----
9227  *          rs -----
9228  *               rd -----
9229  */
9230 std::string NMD::LW_GP16_(uint64 instruction)
9231 {
9232     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9233     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
9234
9235     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
9236     std::string u = IMMEDIATE(copy(u_value));
9237
9238     return img::format("LW %s, %s($%d)", rt3, u, 28);
9239 }
9240
9241
9242 /*
9243  *
9244  *
9245  *   3         2         1
9246  *  10987654321098765432109876543210
9247  *  001000               x1110000101
9248  *     rt -----
9249  *          rs -----
9250  *               rd -----
9251  */
9252 std::string NMD::LW_S9_(uint64 instruction)
9253 {
9254     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9255     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9256     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9257
9258     std::string rt = GPR(copy(rt_value));
9259     std::string s = IMMEDIATE(copy(s_value));
9260     std::string rs = GPR(copy(rs_value));
9261
9262     return img::format("LW %s, %s(%s)", rt, s, rs);
9263 }
9264
9265
9266 /*
9267  *
9268  *
9269  *   3         2         1
9270  *  10987654321098765432109876543210
9271  *  001000               x1110000101
9272  *     rt -----
9273  *          rs -----
9274  *               rd -----
9275  */
9276 std::string NMD::LW_SP_(uint64 instruction)
9277 {
9278     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
9279     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
9280
9281     std::string rt = GPR(copy(rt_value));
9282     std::string u = IMMEDIATE(copy(u_value));
9283
9284     return img::format("LW %s, %s($%d)", rt, u, 29);
9285 }
9286
9287
9288 /*
9289  *
9290  *
9291  *   3         2         1
9292  *  10987654321098765432109876543210
9293  *  001000               x1110000101
9294  *     rt -----
9295  *          rs -----
9296  *               rd -----
9297  */
9298 std::string NMD::LW_U12_(uint64 instruction)
9299 {
9300     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9301     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9302     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9303
9304     std::string rt = GPR(copy(rt_value));
9305     std::string u = IMMEDIATE(copy(u_value));
9306     std::string rs = GPR(copy(rs_value));
9307
9308     return img::format("LW %s, %s(%s)", rt, u, rs);
9309 }
9310
9311
9312 /*
9313  *
9314  *
9315  *   3         2         1
9316  *  10987654321098765432109876543210
9317  *  001000               x1110000101
9318  *     rt -----
9319  *          rs -----
9320  *               rd -----
9321  */
9322 std::string NMD::LWC1_GP_(uint64 instruction)
9323 {
9324     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9325     uint64 u_value = extract_u_17_to_2__s2(instruction);
9326
9327     std::string ft = FPR(copy(ft_value));
9328     std::string u = IMMEDIATE(copy(u_value));
9329
9330     return img::format("LWC1 %s, %s($%d)", ft, u, 28);
9331 }
9332
9333
9334 /*
9335  *
9336  *
9337  *   3         2         1
9338  *  10987654321098765432109876543210
9339  *  001000               x1110000101
9340  *     rt -----
9341  *          rs -----
9342  *               rd -----
9343  */
9344 std::string NMD::LWC1_S9_(uint64 instruction)
9345 {
9346     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9347     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9348     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9349
9350     std::string ft = FPR(copy(ft_value));
9351     std::string s = IMMEDIATE(copy(s_value));
9352     std::string rs = GPR(copy(rs_value));
9353
9354     return img::format("LWC1 %s, %s(%s)", ft, s, rs);
9355 }
9356
9357
9358 /*
9359  *
9360  *
9361  *   3         2         1
9362  *  10987654321098765432109876543210
9363  *  001000               x1110000101
9364  *     rt -----
9365  *          rs -----
9366  *               rd -----
9367  */
9368 std::string NMD::LWC1_U12_(uint64 instruction)
9369 {
9370     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9371     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9372     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9373
9374     std::string ft = FPR(copy(ft_value));
9375     std::string u = IMMEDIATE(copy(u_value));
9376     std::string rs = GPR(copy(rs_value));
9377
9378     return img::format("LWC1 %s, %s(%s)", ft, u, rs);
9379 }
9380
9381
9382 /*
9383  *
9384  *
9385  *   3         2         1
9386  *  10987654321098765432109876543210
9387  *  001000               x1110000101
9388  *     rt -----
9389  *          rs -----
9390  *               rd -----
9391  */
9392 std::string NMD::LWC1X(uint64 instruction)
9393 {
9394     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9395     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9396     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9397
9398     std::string ft = FPR(copy(ft_value));
9399     std::string rs = GPR(copy(rs_value));
9400     std::string rt = GPR(copy(rt_value));
9401
9402     return img::format("LWC1X %s, %s(%s)", ft, rs, rt);
9403 }
9404
9405
9406 /*
9407  *
9408  *
9409  *   3         2         1
9410  *  10987654321098765432109876543210
9411  *  001000               x1110000101
9412  *     rt -----
9413  *          rs -----
9414  *               rd -----
9415  */
9416 std::string NMD::LWC1XS(uint64 instruction)
9417 {
9418     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9419     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9420     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9421
9422     std::string ft = FPR(copy(ft_value));
9423     std::string rs = GPR(copy(rs_value));
9424     std::string rt = GPR(copy(rt_value));
9425
9426     return img::format("LWC1XS %s, %s(%s)", ft, rs, rt);
9427 }
9428
9429
9430 /*
9431  *
9432  *
9433  *   3         2         1
9434  *  10987654321098765432109876543210
9435  *  001000               x1110000101
9436  *     rt -----
9437  *          rs -----
9438  *               rd -----
9439  */
9440 std::string NMD::LWC2(uint64 instruction)
9441 {
9442     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
9443     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9444     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9445
9446     std::string ct = CPR(copy(ct_value));
9447     std::string s = IMMEDIATE(copy(s_value));
9448     std::string rs = GPR(copy(rs_value));
9449
9450     return img::format("LWC2 %s, %s(%s)", ct, s, rs);
9451 }
9452
9453
9454 /*
9455  *
9456  *
9457  *   3         2         1
9458  *  10987654321098765432109876543210
9459  *  001000               x1110000101
9460  *     rt -----
9461  *          rs -----
9462  *               rd -----
9463  */
9464 std::string NMD::LWE(uint64 instruction)
9465 {
9466     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9467     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9468     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9469
9470     std::string rt = GPR(copy(rt_value));
9471     std::string s = IMMEDIATE(copy(s_value));
9472     std::string rs = GPR(copy(rs_value));
9473
9474     return img::format("LWE %s, %s(%s)", rt, s, rs);
9475 }
9476
9477
9478 /*
9479  *
9480  *
9481  *   3         2         1
9482  *  10987654321098765432109876543210
9483  *  001000               x1110000101
9484  *     rt -----
9485  *          rs -----
9486  *               rd -----
9487  */
9488 std::string NMD::LWM(uint64 instruction)
9489 {
9490     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9491     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9492     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9493     uint64 count3_value = extract_count3_14_13_12(instruction);
9494
9495     std::string rt = GPR(copy(rt_value));
9496     std::string s = IMMEDIATE(copy(s_value));
9497     std::string rs = GPR(copy(rs_value));
9498     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
9499
9500     return img::format("LWM %s, %s(%s), %s", rt, s, rs, count3);
9501 }
9502
9503
9504 /*
9505  *
9506  *
9507  *   3         2         1
9508  *  10987654321098765432109876543210
9509  *  001000               x1110000101
9510  *     rt -----
9511  *          rs -----
9512  *               rd -----
9513  */
9514 std::string NMD::LWPC_48_(uint64 instruction)
9515 {
9516     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
9517     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
9518
9519     std::string rt = GPR(copy(rt_value));
9520     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
9521
9522     return img::format("LWPC %s, %s", rt, s);
9523 }
9524
9525
9526 /*
9527  *
9528  *
9529  *   3         2         1
9530  *  10987654321098765432109876543210
9531  *  001000               x1110000101
9532  *     rt -----
9533  *          rs -----
9534  *               rd -----
9535  */
9536 std::string NMD::LWU_GP_(uint64 instruction)
9537 {
9538     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9539     uint64 u_value = extract_u_17_to_2__s2(instruction);
9540
9541     std::string rt = GPR(copy(rt_value));
9542     std::string u = IMMEDIATE(copy(u_value));
9543
9544     return img::format("LWU %s, %s($%d)", rt, u, 28);
9545 }
9546
9547
9548 /*
9549  *
9550  *
9551  *   3         2         1
9552  *  10987654321098765432109876543210
9553  *  001000               x1110000101
9554  *     rt -----
9555  *          rs -----
9556  *               rd -----
9557  */
9558 std::string NMD::LWU_S9_(uint64 instruction)
9559 {
9560     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9561     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9562     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9563
9564     std::string rt = GPR(copy(rt_value));
9565     std::string s = IMMEDIATE(copy(s_value));
9566     std::string rs = GPR(copy(rs_value));
9567
9568     return img::format("LWU %s, %s(%s)", rt, s, rs);
9569 }
9570
9571
9572 /*
9573  *
9574  *
9575  *   3         2         1
9576  *  10987654321098765432109876543210
9577  *  001000               x1110000101
9578  *     rt -----
9579  *          rs -----
9580  *               rd -----
9581  */
9582 std::string NMD::LWU_U12_(uint64 instruction)
9583 {
9584     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9585     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9586     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9587
9588     std::string rt = GPR(copy(rt_value));
9589     std::string u = IMMEDIATE(copy(u_value));
9590     std::string rs = GPR(copy(rs_value));
9591
9592     return img::format("LWU %s, %s(%s)", rt, u, rs);
9593 }
9594
9595
9596 /*
9597  *
9598  *
9599  *   3         2         1
9600  *  10987654321098765432109876543210
9601  *  001000               x1110000101
9602  *     rt -----
9603  *          rs -----
9604  *               rd -----
9605  */
9606 std::string NMD::LWUX(uint64 instruction)
9607 {
9608     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9609     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9610     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9611
9612     std::string rd = GPR(copy(rd_value));
9613     std::string rs = GPR(copy(rs_value));
9614     std::string rt = GPR(copy(rt_value));
9615
9616     return img::format("LWUX %s, %s(%s)", rd, rs, rt);
9617 }
9618
9619
9620 /*
9621  *
9622  *
9623  *   3         2         1
9624  *  10987654321098765432109876543210
9625  *  001000               x1110000101
9626  *     rt -----
9627  *          rs -----
9628  *               rd -----
9629  */
9630 std::string NMD::LWUXS(uint64 instruction)
9631 {
9632     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9633     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9634     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9635
9636     std::string rd = GPR(copy(rd_value));
9637     std::string rs = GPR(copy(rs_value));
9638     std::string rt = GPR(copy(rt_value));
9639
9640     return img::format("LWUXS %s, %s(%s)", rd, rs, rt);
9641 }
9642
9643
9644 /*
9645  *
9646  *
9647  *   3         2         1
9648  *  10987654321098765432109876543210
9649  *  001000               x1110000101
9650  *     rt -----
9651  *          rs -----
9652  *               rd -----
9653  */
9654 std::string NMD::LWX(uint64 instruction)
9655 {
9656     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9657     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9658     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9659
9660     std::string rd = GPR(copy(rd_value));
9661     std::string rs = GPR(copy(rs_value));
9662     std::string rt = GPR(copy(rt_value));
9663
9664     return img::format("LWX %s, %s(%s)", rd, rs, rt);
9665 }
9666
9667
9668 /*
9669  *
9670  *
9671  *   3         2         1
9672  *  10987654321098765432109876543210
9673  *  001000               x1110000101
9674  *     rt -----
9675  *          rs -----
9676  *               rd -----
9677  */
9678 std::string NMD::LWXS_16_(uint64 instruction)
9679 {
9680     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9681     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9682     uint64 rd3_value = extract_rd3_3_2_1(instruction);
9683
9684     std::string rd3 = GPR(decode_gpr_gpr3(rd3_value));
9685     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
9686     std::string rt3 = IMMEDIATE(decode_gpr_gpr3(rt3_value));
9687
9688     return img::format("LWXS %s, %s(%s)", rd3, rs3, rt3);
9689 }
9690
9691
9692 /*
9693  *
9694  *
9695  *   3         2         1
9696  *  10987654321098765432109876543210
9697  *  001000               x1110000101
9698  *     rt -----
9699  *          rs -----
9700  *               rd -----
9701  */
9702 std::string NMD::LWXS_32_(uint64 instruction)
9703 {
9704     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9705     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9706     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9707
9708     std::string rd = GPR(copy(rd_value));
9709     std::string rs = GPR(copy(rs_value));
9710     std::string rt = GPR(copy(rt_value));
9711
9712     return img::format("LWXS %s, %s(%s)", rd, rs, rt);
9713 }
9714
9715
9716 /*
9717  * [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
9718  *         accumulator
9719  *
9720  *   3         2         1
9721  *  10987654321098765432109876543210
9722  *  001000               x1110000101
9723  *     rt -----
9724  *          rs -----
9725  *               rd -----
9726  */
9727 std::string NMD::MADD_DSP_(uint64 instruction)
9728 {
9729     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9730     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9731     uint64 ac_value = extract_ac_15_14(instruction);
9732
9733     std::string ac = AC(copy(ac_value));
9734     std::string rs = GPR(copy(rs_value));
9735     std::string rt = GPR(copy(rt_value));
9736
9737     return img::format("MADD %s, %s, %s", ac, rs, rt);
9738 }
9739
9740
9741 /*
9742  *
9743  *
9744  *   3         2         1
9745  *  10987654321098765432109876543210
9746  *  001000               x1110000101
9747  *     rt -----
9748  *          rs -----
9749  *               rd -----
9750  */
9751 std::string NMD::MADDF_D(uint64 instruction)
9752 {
9753     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9754     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9755     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9756
9757     std::string fd = FPR(copy(fd_value));
9758     std::string fs = FPR(copy(fs_value));
9759     std::string ft = FPR(copy(ft_value));
9760
9761     return img::format("MADDF.D %s, %s, %s", fd, fs, ft);
9762 }
9763
9764
9765 /*
9766  *
9767  *
9768  *   3         2         1
9769  *  10987654321098765432109876543210
9770  *  001000               x1110000101
9771  *     rt -----
9772  *          rs -----
9773  *               rd -----
9774  */
9775 std::string NMD::MADDF_S(uint64 instruction)
9776 {
9777     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9778     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9779     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9780
9781     std::string fd = FPR(copy(fd_value));
9782     std::string fs = FPR(copy(fs_value));
9783     std::string ft = FPR(copy(ft_value));
9784
9785     return img::format("MADDF.S %s, %s, %s", fd, fs, ft);
9786 }
9787
9788
9789 /*
9790  * [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
9791  *         specified accumulator
9792  *
9793  *   3         2         1
9794  *  10987654321098765432109876543210
9795  *  001000               x1110000101
9796  *     rt -----
9797  *          rs -----
9798  *               rd -----
9799  */
9800 std::string NMD::MADDU_DSP_(uint64 instruction)
9801 {
9802     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9803     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9804     uint64 ac_value = extract_ac_15_14(instruction);
9805
9806     std::string ac = AC(copy(ac_value));
9807     std::string rs = GPR(copy(rs_value));
9808     std::string rt = GPR(copy(rt_value));
9809
9810     return img::format("MADDU %s, %s, %s", ac, rs, rt);
9811 }
9812
9813
9814 /*
9815  * [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
9816  *         fractional halfword elements with accumulation
9817  *
9818  *   3         2         1
9819  *  10987654321098765432109876543210
9820  *  001000               x1110000101
9821  *     rt -----
9822  *          rs -----
9823  *               rd -----
9824  */
9825 std::string NMD::MAQ_S_W_PHL(uint64 instruction)
9826 {
9827     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9828     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9829     uint64 ac_value = extract_ac_15_14(instruction);
9830
9831     std::string ac = AC(copy(ac_value));
9832     std::string rs = GPR(copy(rs_value));
9833     std::string rt = GPR(copy(rt_value));
9834
9835     return img::format("MAQ_S.W.PHL %s, %s, %s", ac, rs, rt);
9836 }
9837
9838
9839 /*
9840  * [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
9841  *         fractional halfword elements with accumulation
9842  *
9843  *   3         2         1
9844  *  10987654321098765432109876543210
9845  *  001000               x1110000101
9846  *     rt -----
9847  *          rs -----
9848  *               rd -----
9849  */
9850 std::string NMD::MAQ_S_W_PHR(uint64 instruction)
9851 {
9852     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9853     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9854     uint64 ac_value = extract_ac_15_14(instruction);
9855
9856     std::string ac = AC(copy(ac_value));
9857     std::string rs = GPR(copy(rs_value));
9858     std::string rt = GPR(copy(rt_value));
9859
9860     return img::format("MAQ_S.W.PHR %s, %s, %s", ac, rs, rt);
9861 }
9862
9863
9864 /*
9865  * [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
9866  *         fractional halfword elements with saturating accumulation
9867  *
9868  *   3         2         1
9869  *  10987654321098765432109876543210
9870  *  001000               x1110000101
9871  *     rt -----
9872  *          rs -----
9873  *               rd -----
9874  */
9875 std::string NMD::MAQ_SA_W_PHL(uint64 instruction)
9876 {
9877     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9878     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9879     uint64 ac_value = extract_ac_15_14(instruction);
9880
9881     std::string ac = AC(copy(ac_value));
9882     std::string rs = GPR(copy(rs_value));
9883     std::string rt = GPR(copy(rt_value));
9884
9885     return img::format("MAQ_SA.W.PHL %s, %s, %s", ac, rs, rt);
9886 }
9887
9888
9889 /*
9890  * [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
9891  *         fractional halfword elements with saturating accumulation
9892  *
9893  *   3         2         1
9894  *  10987654321098765432109876543210
9895  *  001000               x1110000101
9896  *     rt -----
9897  *          rs -----
9898  *               rd -----
9899  */
9900 std::string NMD::MAQ_SA_W_PHR(uint64 instruction)
9901 {
9902     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9903     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9904     uint64 ac_value = extract_ac_15_14(instruction);
9905
9906     std::string ac = AC(copy(ac_value));
9907     std::string rs = GPR(copy(rs_value));
9908     std::string rt = GPR(copy(rt_value));
9909
9910     return img::format("MAQ_SA.W.PHR %s, %s, %s", ac, rs, rt);
9911 }
9912
9913
9914 /*
9915  *
9916  *
9917  *   3         2         1
9918  *  10987654321098765432109876543210
9919  *  001000               x1110000101
9920  *     rt -----
9921  *          rs -----
9922  *               rd -----
9923  */
9924 std::string NMD::MAX_D(uint64 instruction)
9925 {
9926     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9927     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9928     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9929
9930     std::string fd = FPR(copy(fd_value));
9931     std::string fs = FPR(copy(fs_value));
9932     std::string ft = FPR(copy(ft_value));
9933
9934     return img::format("MAX.D %s, %s, %s", fd, fs, ft);
9935 }
9936
9937
9938 /*
9939  *
9940  *
9941  *   3         2         1
9942  *  10987654321098765432109876543210
9943  *  001000               x1110000101
9944  *     rt -----
9945  *          rs -----
9946  *               rd -----
9947  */
9948 std::string NMD::MAX_S(uint64 instruction)
9949 {
9950     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9951     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9952     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9953
9954     std::string fd = FPR(copy(fd_value));
9955     std::string fs = FPR(copy(fs_value));
9956     std::string ft = FPR(copy(ft_value));
9957
9958     return img::format("MAX.S %s, %s, %s", fd, fs, ft);
9959 }
9960
9961
9962 /*
9963  *
9964  *
9965  *   3         2         1
9966  *  10987654321098765432109876543210
9967  *  001000               x1110000101
9968  *     rt -----
9969  *          rs -----
9970  *               rd -----
9971  */
9972 std::string NMD::MAXA_D(uint64 instruction)
9973 {
9974     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9975     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9976     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9977
9978     std::string fd = FPR(copy(fd_value));
9979     std::string fs = FPR(copy(fs_value));
9980     std::string ft = FPR(copy(ft_value));
9981
9982     return img::format("MAXA.D %s, %s, %s", fd, fs, ft);
9983 }
9984
9985
9986 /*
9987  *
9988  *
9989  *   3         2         1
9990  *  10987654321098765432109876543210
9991  *  001000               x1110000101
9992  *     rt -----
9993  *          rs -----
9994  *               rd -----
9995  */
9996 std::string NMD::MAXA_S(uint64 instruction)
9997 {
9998     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9999     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10000     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10001
10002     std::string fd = FPR(copy(fd_value));
10003     std::string fs = FPR(copy(fs_value));
10004     std::string ft = FPR(copy(ft_value));
10005
10006     return img::format("MAXA.S %s, %s, %s", fd, fs, ft);
10007 }
10008
10009
10010 /*
10011  *
10012  *
10013  *   3         2         1
10014  *  10987654321098765432109876543210
10015  *  001000               x1110000101
10016  *     rt -----
10017  *          rs -----
10018  *               rd -----
10019  */
10020 std::string NMD::MFC0(uint64 instruction)
10021 {
10022     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10023     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10024     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10025
10026     std::string rt = GPR(copy(rt_value));
10027     std::string c0s = CPR(copy(c0s_value));
10028     std::string sel = IMMEDIATE(copy(sel_value));
10029
10030     return img::format("MFC0 %s, %s, %s", rt, c0s, sel);
10031 }
10032
10033
10034 /*
10035  *
10036  *
10037  *   3         2         1
10038  *  10987654321098765432109876543210
10039  *  001000               x1110000101
10040  *     rt -----
10041  *          rs -----
10042  *               rd -----
10043  */
10044 std::string NMD::MFC1(uint64 instruction)
10045 {
10046     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10047     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10048
10049     std::string rt = GPR(copy(rt_value));
10050     std::string fs = FPR(copy(fs_value));
10051
10052     return img::format("MFC1 %s, %s", rt, fs);
10053 }
10054
10055
10056 /*
10057  *
10058  *
10059  *   3         2         1
10060  *  10987654321098765432109876543210
10061  *  001000               x1110000101
10062  *     rt -----
10063  *          rs -----
10064  *               rd -----
10065  */
10066 std::string NMD::MFC2(uint64 instruction)
10067 {
10068     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10069     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10070
10071     std::string rt = GPR(copy(rt_value));
10072     std::string cs = CPR(copy(cs_value));
10073
10074     return img::format("MFC2 %s, %s", rt, cs);
10075 }
10076
10077
10078 /*
10079  *
10080  *
10081  *   3         2         1
10082  *  10987654321098765432109876543210
10083  *  001000               x1110000101
10084  *     rt -----
10085  *          rs -----
10086  *               rd -----
10087  */
10088 std::string NMD::MFGC0(uint64 instruction)
10089 {
10090     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10091     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10092     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10093
10094     std::string rt = GPR(copy(rt_value));
10095     std::string c0s = CPR(copy(c0s_value));
10096     std::string sel = IMMEDIATE(copy(sel_value));
10097
10098     return img::format("MFGC0 %s, %s, %s", rt, c0s, sel);
10099 }
10100
10101
10102 /*
10103  *
10104  *
10105  *   3         2         1
10106  *  10987654321098765432109876543210
10107  *  001000               x1110000101
10108  *     rt -----
10109  *          rs -----
10110  *               rd -----
10111  */
10112 std::string NMD::MFHC0(uint64 instruction)
10113 {
10114     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10115     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10116     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10117
10118     std::string rt = GPR(copy(rt_value));
10119     std::string c0s = CPR(copy(c0s_value));
10120     std::string sel = IMMEDIATE(copy(sel_value));
10121
10122     return img::format("MFHC0 %s, %s, %s", rt, c0s, sel);
10123 }
10124
10125
10126 /*
10127  *
10128  *
10129  *   3         2         1
10130  *  10987654321098765432109876543210
10131  *  001000               x1110000101
10132  *     rt -----
10133  *          rs -----
10134  *               rd -----
10135  */
10136 std::string NMD::MFHC1(uint64 instruction)
10137 {
10138     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10139     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10140
10141     std::string rt = GPR(copy(rt_value));
10142     std::string fs = FPR(copy(fs_value));
10143
10144     return img::format("MFHC1 %s, %s", rt, fs);
10145 }
10146
10147
10148 /*
10149  *
10150  *
10151  *   3         2         1
10152  *  10987654321098765432109876543210
10153  *  001000               x1110000101
10154  *     rt -----
10155  *          rs -----
10156  *               rd -----
10157  */
10158 std::string NMD::MFHC2(uint64 instruction)
10159 {
10160     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10161     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10162
10163     std::string rt = GPR(copy(rt_value));
10164     std::string cs = CPR(copy(cs_value));
10165
10166     return img::format("MFHC2 %s, %s", rt, cs);
10167 }
10168
10169
10170 /*
10171  *
10172  *
10173  *   3         2         1
10174  *  10987654321098765432109876543210
10175  *  001000               x1110000101
10176  *     rt -----
10177  *          rs -----
10178  *               rd -----
10179  */
10180 std::string NMD::MFHGC0(uint64 instruction)
10181 {
10182     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10183     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10184     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10185
10186     std::string rt = GPR(copy(rt_value));
10187     std::string c0s = CPR(copy(c0s_value));
10188     std::string sel = IMMEDIATE(copy(sel_value));
10189
10190     return img::format("MFHGC0 %s, %s, %s", rt, c0s, sel);
10191 }
10192
10193
10194 /*
10195  * [DSP] MFHI rs, ac - Move from HI register
10196  *
10197  *   3         2         1
10198  *  10987654321098765432109876543210
10199  *  001000     xxxxx  00000001111111
10200  *     rt -----
10201  *               ac --
10202  */
10203 std::string NMD::MFHI_DSP_(uint64 instruction)
10204 {
10205     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10206     uint64 ac_value = extract_ac_15_14(instruction);
10207
10208     std::string rt = GPR(copy(rt_value));
10209     std::string ac = AC(copy(ac_value));
10210
10211     return img::format("MFHI %s, %s", rt, ac);
10212 }
10213
10214
10215 /*
10216  *
10217  *
10218  *   3         2         1
10219  *  10987654321098765432109876543210
10220  *  001000               x1110000101
10221  *     rt -----
10222  *          rs -----
10223  *               rd -----
10224  */
10225 std::string NMD::MFHTR(uint64 instruction)
10226 {
10227     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10228     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10229     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10230     uint64 u_value = extract_u_10(instruction);
10231
10232     std::string rt = GPR(copy(rt_value));
10233     std::string c0s = IMMEDIATE(copy(c0s_value));
10234     std::string u = IMMEDIATE(copy(u_value));
10235     std::string sel = IMMEDIATE(copy(sel_value));
10236
10237     return img::format("MFHTR %s, %s, %s, %s", rt, c0s, u, sel);
10238 }
10239
10240
10241 /*
10242  * [DSP] MFLO rs, ac - Move from HI register
10243  *
10244  *   3         2         1
10245  *  10987654321098765432109876543210
10246  *  001000     xxxxx  01000001111111
10247  *     rt -----
10248  *               ac --
10249  */
10250 std::string NMD::MFLO_DSP_(uint64 instruction)
10251 {
10252     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10253     uint64 ac_value = extract_ac_15_14(instruction);
10254
10255     std::string rt = GPR(copy(rt_value));
10256     std::string ac = AC(copy(ac_value));
10257
10258     return img::format("MFLO %s, %s", rt, ac);
10259 }
10260
10261
10262 /*
10263  *
10264  *
10265  *   3         2         1
10266  *  10987654321098765432109876543210
10267  *  001000               x1110000101
10268  *     rt -----
10269  *          rs -----
10270  *               rd -----
10271  */
10272 std::string NMD::MFTR(uint64 instruction)
10273 {
10274     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10275     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10276     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10277     uint64 u_value = extract_u_10(instruction);
10278
10279     std::string rt = GPR(copy(rt_value));
10280     std::string c0s = IMMEDIATE(copy(c0s_value));
10281     std::string u = IMMEDIATE(copy(u_value));
10282     std::string sel = IMMEDIATE(copy(sel_value));
10283
10284     return img::format("MFTR %s, %s, %s, %s", rt, c0s, u, sel);
10285 }
10286
10287
10288 /*
10289  *
10290  *
10291  *   3         2         1
10292  *  10987654321098765432109876543210
10293  *  001000               x1110000101
10294  *     rt -----
10295  *          rs -----
10296  *               rd -----
10297  */
10298 std::string NMD::MIN_D(uint64 instruction)
10299 {
10300     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10301     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10302     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10303
10304     std::string fd = FPR(copy(fd_value));
10305     std::string fs = FPR(copy(fs_value));
10306     std::string ft = FPR(copy(ft_value));
10307
10308     return img::format("MIN.D %s, %s, %s", fd, fs, ft);
10309 }
10310
10311
10312 /*
10313  *
10314  *
10315  *   3         2         1
10316  *  10987654321098765432109876543210
10317  *  001000               x1110000101
10318  *     rt -----
10319  *          rs -----
10320  *               rd -----
10321  */
10322 std::string NMD::MIN_S(uint64 instruction)
10323 {
10324     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10325     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10326     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10327
10328     std::string fd = FPR(copy(fd_value));
10329     std::string fs = FPR(copy(fs_value));
10330     std::string ft = FPR(copy(ft_value));
10331
10332     return img::format("MIN.S %s, %s, %s", fd, fs, ft);
10333 }
10334
10335
10336 /*
10337  *
10338  *
10339  *   3         2         1
10340  *  10987654321098765432109876543210
10341  *  001000               x1110000101
10342  *     rt -----
10343  *          rs -----
10344  *               rd -----
10345  */
10346 std::string NMD::MINA_D(uint64 instruction)
10347 {
10348     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10349     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10350     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10351
10352     std::string fd = FPR(copy(fd_value));
10353     std::string fs = FPR(copy(fs_value));
10354     std::string ft = FPR(copy(ft_value));
10355
10356     return img::format("MINA.D %s, %s, %s", fd, fs, ft);
10357 }
10358
10359
10360 /*
10361  *
10362  *
10363  *   3         2         1
10364  *  10987654321098765432109876543210
10365  *  001000               x1110000101
10366  *     rt -----
10367  *          rs -----
10368  *               rd -----
10369  */
10370 std::string NMD::MINA_S(uint64 instruction)
10371 {
10372     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10373     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10374     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10375
10376     std::string fd = FPR(copy(fd_value));
10377     std::string fs = FPR(copy(fs_value));
10378     std::string ft = FPR(copy(ft_value));
10379
10380     return img::format("MINA.S %s, %s, %s", fd, fs, ft);
10381 }
10382
10383
10384 /*
10385  *
10386  *
10387  *   3         2         1
10388  *  10987654321098765432109876543210
10389  *  001000               x1110000101
10390  *     rt -----
10391  *          rs -----
10392  *               rd -----
10393  */
10394 std::string NMD::MOD(uint64 instruction)
10395 {
10396     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10397     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10398     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10399
10400     std::string rd = GPR(copy(rd_value));
10401     std::string rs = GPR(copy(rs_value));
10402     std::string rt = GPR(copy(rt_value));
10403
10404     return img::format("MOD %s, %s, %s", rd, rs, rt);
10405 }
10406
10407
10408 /*
10409  * [DSP] MODSUB rd, rs, rt - Modular subtraction on an index value
10410  *
10411  *   3         2         1
10412  *  10987654321098765432109876543210
10413  *  001000               x1110000101
10414  *     rt -----
10415  *          rs -----
10416  *               rd -----
10417  */
10418 std::string NMD::MODSUB(uint64 instruction)
10419 {
10420     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10421     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10422     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10423
10424     std::string rd = GPR(copy(rd_value));
10425     std::string rs = GPR(copy(rs_value));
10426     std::string rt = GPR(copy(rt_value));
10427
10428     return img::format("MODSUB %s, %s, %s", rd, rs, rt);
10429 }
10430
10431
10432 /*
10433  *
10434  *
10435  *   3         2         1
10436  *  10987654321098765432109876543210
10437  *  001000               x1010010101
10438  *     rt -----
10439  *          rs -----
10440  *               rd -----
10441  */
10442 std::string NMD::MODU(uint64 instruction)
10443 {
10444     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10445     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10446     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10447
10448     std::string rd = GPR(copy(rd_value));
10449     std::string rs = GPR(copy(rs_value));
10450     std::string rt = GPR(copy(rt_value));
10451
10452     return img::format("MODU %s, %s, %s", rd, rs, rt);
10453 }
10454
10455
10456 /*
10457  *
10458  *
10459  *   3         2         1
10460  *  10987654321098765432109876543210
10461  *  001000               x1110000101
10462  *     rt -----
10463  *          rs -----
10464  *               rd -----
10465  */
10466 std::string NMD::MOV_D(uint64 instruction)
10467 {
10468     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10469     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10470
10471     std::string ft = FPR(copy(ft_value));
10472     std::string fs = FPR(copy(fs_value));
10473
10474     return img::format("MOV.D %s, %s", ft, fs);
10475 }
10476
10477
10478 /*
10479  *
10480  *
10481  *   3         2         1
10482  *  10987654321098765432109876543210
10483  *  001000               x1110000101
10484  *     rt -----
10485  *          rs -----
10486  *               rd -----
10487  */
10488 std::string NMD::MOV_S(uint64 instruction)
10489 {
10490     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10491     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10492
10493     std::string ft = FPR(copy(ft_value));
10494     std::string fs = FPR(copy(fs_value));
10495
10496     return img::format("MOV.S %s, %s", ft, fs);
10497 }
10498
10499
10500 /*
10501  *
10502  *
10503  *   3         2         1
10504  *  10987654321098765432109876543210
10505  *  001000               x1110000101
10506  *     rt -----
10507  *          rs -----
10508  *               rd -----
10509  */
10510 std::string NMD::MOVE_BALC(uint64 instruction)
10511 {
10512     uint64 rtz4_value = extract_rtz4_27_26_25_23_22_21(instruction);
10513     uint64 rd1_value = extract_rdl_25_24(instruction);
10514     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
10515
10516     std::string rd1 = GPR(decode_gpr_gpr1(rd1_value));
10517     std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value));
10518     std::string s = ADDRESS(encode_s_from_address(s_value), 4);
10519
10520     return img::format("MOVE.BALC %s, %s, %s", rd1, rtz4, s);
10521 }
10522
10523
10524 /*
10525  *
10526  *
10527  *   3         2         1
10528  *  10987654321098765432109876543210
10529  *  001000               x1110000101
10530  *     rt -----
10531  *          rs -----
10532  *               rd -----
10533  */
10534 std::string NMD::MOVEP(uint64 instruction)
10535 {
10536     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
10537     uint64 rd2_value = extract_rd2_3_8(instruction);
10538     uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction);
10539
10540     std::string rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value));
10541     std::string re2 = GPR(decode_gpr_gpr2_reg2(rd2_value));
10542     /* !!!!!!!!!! - no conversion function */
10543     std::string rsz4 = GPR(decode_gpr_gpr4_zero(rsz4_value));
10544     std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value));
10545
10546     return img::format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4);
10547     /* hand edited */
10548 }
10549
10550
10551 /*
10552  *
10553  *
10554  *   3         2         1
10555  *  10987654321098765432109876543210
10556  *  001000               x1110000101
10557  *     rt -----
10558  *          rs -----
10559  *               rd -----
10560  */
10561 std::string NMD::MOVEP_REV_(uint64 instruction)
10562 {
10563     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
10564     uint64 rd2_value = extract_rd2_3_8(instruction);
10565     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
10566
10567     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
10568     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
10569     std::string rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value));
10570     std::string rs2 = GPR(decode_gpr_gpr2_reg2(rd2_value));
10571     /* !!!!!!!!!! - no conversion function */
10572
10573     return img::format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2);
10574     /* hand edited */
10575 }
10576
10577
10578 /*
10579  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10580  *
10581  *   3         2         1
10582  *  10987654321098765432109876543210
10583  *  001000               00010001101
10584  *     rt -----
10585  *          rs -----
10586  *               rd -----
10587  */
10588 std::string NMD::MOVE(uint64 instruction)
10589 {
10590     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
10591     uint64 rs_value = extract_rs_4_3_2_1_0(instruction);
10592
10593     std::string rt = GPR(copy(rt_value));
10594     std::string rs = GPR(copy(rs_value));
10595
10596     return img::format("MOVE %s, %s", rt, rs);
10597 }
10598
10599
10600 /*
10601  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10602  *
10603  *   3         2         1
10604  *  10987654321098765432109876543210
10605  *  001000               00010001101
10606  *     rt -----
10607  *          rs -----
10608  *               rd -----
10609  */
10610 std::string NMD::MOVN(uint64 instruction)
10611 {
10612     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10613     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10614     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10615
10616     std::string rd = GPR(copy(rd_value));
10617     std::string rs = GPR(copy(rs_value));
10618     std::string rt = GPR(copy(rt_value));
10619
10620     return img::format("MOVN %s, %s, %s", rd, rs, rt);
10621 }
10622
10623
10624 /*
10625  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10626  *
10627  *   3         2         1
10628  *  10987654321098765432109876543210
10629  *  001000               00010001101
10630  *     rt -----
10631  *          rs -----
10632  *               rd -----
10633  */
10634 std::string NMD::MOVZ(uint64 instruction)
10635 {
10636     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10637     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10638     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10639
10640     std::string rd = GPR(copy(rd_value));
10641     std::string rs = GPR(copy(rs_value));
10642     std::string rt = GPR(copy(rt_value));
10643
10644     return img::format("MOVZ %s, %s, %s", rd, rs, rt);
10645 }
10646
10647
10648 /*
10649  * [DSP] MSUB ac, rs, rt - Multiply word and subtract from accumulator
10650  *
10651  *   3         2         1
10652  *  10987654321098765432109876543210
10653  *  001000            10101010111111
10654  *     rt -----
10655  *          rs -----
10656  *               ac --
10657  */
10658 std::string NMD::MSUB_DSP_(uint64 instruction)
10659 {
10660     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10661     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10662     uint64 ac_value = extract_ac_15_14(instruction);
10663
10664     std::string ac = AC(copy(ac_value));
10665     std::string rs = GPR(copy(rs_value));
10666     std::string rt = GPR(copy(rt_value));
10667
10668     return img::format("MSUB %s, %s, %s", ac, rs, rt);
10669 }
10670
10671
10672 /*
10673  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10674  *
10675  *   3         2         1
10676  *  10987654321098765432109876543210
10677  *  001000               00010001101
10678  *     rt -----
10679  *          rs -----
10680  *               rd -----
10681  */
10682 std::string NMD::MSUBF_D(uint64 instruction)
10683 {
10684     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10685     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10686     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10687
10688     std::string fd = FPR(copy(fd_value));
10689     std::string fs = FPR(copy(fs_value));
10690     std::string ft = FPR(copy(ft_value));
10691
10692     return img::format("MSUBF.D %s, %s, %s", fd, fs, ft);
10693 }
10694
10695
10696 /*
10697  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10698  *
10699  *   3         2         1
10700  *  10987654321098765432109876543210
10701  *  001000               00010001101
10702  *     rt -----
10703  *          rs -----
10704  *               rd -----
10705  */
10706 std::string NMD::MSUBF_S(uint64 instruction)
10707 {
10708     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10709     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10710     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10711
10712     std::string fd = FPR(copy(fd_value));
10713     std::string fs = FPR(copy(fs_value));
10714     std::string ft = FPR(copy(ft_value));
10715
10716     return img::format("MSUBF.S %s, %s, %s", fd, fs, ft);
10717 }
10718
10719
10720 /*
10721  * [DSP] MSUBU ac, rs, rt - Multiply word and add to accumulator
10722  *
10723  *   3         2         1
10724  *  10987654321098765432109876543210
10725  *  001000            11101010111111
10726  *     rt -----
10727  *          rs -----
10728  *               ac --
10729  */
10730 std::string NMD::MSUBU_DSP_(uint64 instruction)
10731 {
10732     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10733     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10734     uint64 ac_value = extract_ac_15_14(instruction);
10735
10736     std::string ac = AC(copy(ac_value));
10737     std::string rs = GPR(copy(rs_value));
10738     std::string rt = GPR(copy(rt_value));
10739
10740     return img::format("MSUBU %s, %s, %s", ac, rs, rt);
10741 }
10742
10743
10744 /*
10745  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10746  *
10747  *   3         2         1
10748  *  10987654321098765432109876543210
10749  *  001000               00010001101
10750  *     rt -----
10751  *          rs -----
10752  *               rd -----
10753  */
10754 std::string NMD::MTC0(uint64 instruction)
10755 {
10756     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10757     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10758     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10759
10760     std::string rt = GPR(copy(rt_value));
10761     std::string c0s = CPR(copy(c0s_value));
10762     std::string sel = IMMEDIATE(copy(sel_value));
10763
10764     return img::format("MTC0 %s, %s, %s", rt, c0s, sel);
10765 }
10766
10767
10768 /*
10769  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10770  *
10771  *   3         2         1
10772  *  10987654321098765432109876543210
10773  *  001000               00010001101
10774  *     rt -----
10775  *          rs -----
10776  *               rd -----
10777  */
10778 std::string NMD::MTC1(uint64 instruction)
10779 {
10780     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10781     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10782
10783     std::string rt = GPR(copy(rt_value));
10784     std::string fs = FPR(copy(fs_value));
10785
10786     return img::format("MTC1 %s, %s", rt, fs);
10787 }
10788
10789
10790 /*
10791  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10792  *
10793  *   3         2         1
10794  *  10987654321098765432109876543210
10795  *  001000               00010001101
10796  *     rt -----
10797  *          rs -----
10798  *               rd -----
10799  */
10800 std::string NMD::MTC2(uint64 instruction)
10801 {
10802     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10803     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10804
10805     std::string rt = GPR(copy(rt_value));
10806     std::string cs = CPR(copy(cs_value));
10807
10808     return img::format("MTC2 %s, %s", rt, cs);
10809 }
10810
10811
10812 /*
10813  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10814  *
10815  *   3         2         1
10816  *  10987654321098765432109876543210
10817  *  001000               00010001101
10818  *     rt -----
10819  *          rs -----
10820  *               rd -----
10821  */
10822 std::string NMD::MTGC0(uint64 instruction)
10823 {
10824     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10825     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10826     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10827
10828     std::string rt = GPR(copy(rt_value));
10829     std::string c0s = CPR(copy(c0s_value));
10830     std::string sel = IMMEDIATE(copy(sel_value));
10831
10832     return img::format("MTGC0 %s, %s, %s", rt, c0s, sel);
10833 }
10834
10835
10836 /*
10837  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10838  *
10839  *   3         2         1
10840  *  10987654321098765432109876543210
10841  *  001000               00010001101
10842  *     rt -----
10843  *          rs -----
10844  *               rd -----
10845  */
10846 std::string NMD::MTHC0(uint64 instruction)
10847 {
10848     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10849     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10850     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10851
10852     std::string rt = GPR(copy(rt_value));
10853     std::string c0s = CPR(copy(c0s_value));
10854     std::string sel = IMMEDIATE(copy(sel_value));
10855
10856     return img::format("MTHC0 %s, %s, %s", rt, c0s, sel);
10857 }
10858
10859
10860 /*
10861  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10862  *
10863  *   3         2         1
10864  *  10987654321098765432109876543210
10865  *  001000               00010001101
10866  *     rt -----
10867  *          rs -----
10868  *               rd -----
10869  */
10870 std::string NMD::MTHC1(uint64 instruction)
10871 {
10872     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10873     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10874
10875     std::string rt = GPR(copy(rt_value));
10876     std::string fs = FPR(copy(fs_value));
10877
10878     return img::format("MTHC1 %s, %s", rt, fs);
10879 }
10880
10881
10882 /*
10883  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10884  *
10885  *   3         2         1
10886  *  10987654321098765432109876543210
10887  *  001000               00010001101
10888  *     rt -----
10889  *          rs -----
10890  *               rd -----
10891  */
10892 std::string NMD::MTHC2(uint64 instruction)
10893 {
10894     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10895     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10896
10897     std::string rt = GPR(copy(rt_value));
10898     std::string cs = CPR(copy(cs_value));
10899
10900     return img::format("MTHC2 %s, %s", rt, cs);
10901 }
10902
10903
10904 /*
10905  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10906  *
10907  *   3         2         1
10908  *  10987654321098765432109876543210
10909  *  001000               00010001101
10910  *     rt -----
10911  *          rs -----
10912  *               rd -----
10913  */
10914 std::string NMD::MTHGC0(uint64 instruction)
10915 {
10916     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10917     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10918     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10919
10920     std::string rt = GPR(copy(rt_value));
10921     std::string c0s = CPR(copy(c0s_value));
10922     std::string sel = IMMEDIATE(copy(sel_value));
10923
10924     return img::format("MTHGC0 %s, %s, %s", rt, c0s, sel);
10925 }
10926
10927
10928 /*
10929  * [DSP] MTHI rs, ac - Move to HI register
10930  *
10931  *   3         2         1
10932  *  10987654321098765432109876543210
10933  *  001000xxxxx       10000001111111
10934  *          rs -----
10935  *               ac --
10936  */
10937 std::string NMD::MTHI_DSP_(uint64 instruction)
10938 {
10939     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10940     uint64 ac_value = extract_ac_15_14(instruction);
10941
10942     std::string rs = GPR(copy(rs_value));
10943     std::string ac = AC(copy(ac_value));
10944
10945     return img::format("MTHI %s, %s", rs, ac);
10946 }
10947
10948
10949 /*
10950  * [DSP] MTHLIP rs, ac - Copy LO to HI and a GPR to LO and increment pos by 32
10951  *
10952  *   3         2         1
10953  *  10987654321098765432109876543210
10954  *  001000xxxxx       00001001111111
10955  *          rs -----
10956  *               ac --
10957  */
10958 std::string NMD::MTHLIP(uint64 instruction)
10959 {
10960     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10961     uint64 ac_value = extract_ac_15_14(instruction);
10962
10963     std::string rs = GPR(copy(rs_value));
10964     std::string ac = AC(copy(ac_value));
10965
10966     return img::format("MTHLIP %s, %s", rs, ac);
10967 }
10968
10969
10970 /*
10971  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10972  *
10973  *   3         2         1
10974  *  10987654321098765432109876543210
10975  *  001000               00010001101
10976  *     rt -----
10977  *          rs -----
10978  *               rd -----
10979  */
10980 std::string NMD::MTHTR(uint64 instruction)
10981 {
10982     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10983     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10984     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10985     uint64 u_value = extract_u_10(instruction);
10986
10987     std::string rt = GPR(copy(rt_value));
10988     std::string c0s = IMMEDIATE(copy(c0s_value));
10989     std::string u = IMMEDIATE(copy(u_value));
10990     std::string sel = IMMEDIATE(copy(sel_value));
10991
10992     return img::format("MTHTR %s, %s, %s, %s", rt, c0s, u, sel);
10993 }
10994
10995
10996 /*
10997  * [DSP] MTLO rs, ac - Move to LO register
10998  *
10999  *   3         2         1
11000  *  10987654321098765432109876543210
11001  *  001000xxxxx       11000001111111
11002  *          rs -----
11003  *               ac --
11004  */
11005 std::string NMD::MTLO_DSP_(uint64 instruction)
11006 {
11007     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11008     uint64 ac_value = extract_ac_15_14(instruction);
11009
11010     std::string rs = GPR(copy(rs_value));
11011     std::string ac = AC(copy(ac_value));
11012
11013     return img::format("MTLO %s, %s", rs, ac);
11014 }
11015
11016
11017 /*
11018  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11019  *
11020  *   3         2         1
11021  *  10987654321098765432109876543210
11022  *  001000               00010001101
11023  *     rt -----
11024  *          rs -----
11025  *               rd -----
11026  */
11027 std::string NMD::MTTR(uint64 instruction)
11028 {
11029     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11030     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
11031     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
11032     uint64 u_value = extract_u_10(instruction);
11033
11034     std::string rt = GPR(copy(rt_value));
11035     std::string c0s = IMMEDIATE(copy(c0s_value));
11036     std::string u = IMMEDIATE(copy(u_value));
11037     std::string sel = IMMEDIATE(copy(sel_value));
11038
11039     return img::format("MTTR %s, %s, %s, %s", rt, c0s, u, sel);
11040 }
11041
11042
11043 /*
11044  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11045  *
11046  *   3         2         1
11047  *  10987654321098765432109876543210
11048  *  001000               00010001101
11049  *     rt -----
11050  *          rs -----
11051  *               rd -----
11052  */
11053 std::string NMD::MUH(uint64 instruction)
11054 {
11055     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11056     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11057     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11058
11059     std::string rd = GPR(copy(rd_value));
11060     std::string rs = GPR(copy(rs_value));
11061     std::string rt = GPR(copy(rt_value));
11062
11063     return img::format("MUH %s, %s, %s", rd, rs, rt);
11064 }
11065
11066
11067 /*
11068  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11069  *
11070  *   3         2         1
11071  *  10987654321098765432109876543210
11072  *  001000               00010001101
11073  *     rt -----
11074  *          rs -----
11075  *               rd -----
11076  */
11077 std::string NMD::MUHU(uint64 instruction)
11078 {
11079     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11080     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11081     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11082
11083     std::string rd = GPR(copy(rd_value));
11084     std::string rs = GPR(copy(rs_value));
11085     std::string rt = GPR(copy(rt_value));
11086
11087     return img::format("MUHU %s, %s, %s", rd, rs, rt);
11088 }
11089
11090
11091 /*
11092  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11093  *
11094  *   3         2         1
11095  *  10987654321098765432109876543210
11096  *  001000               00010001101
11097  *     rt -----
11098  *          rs -----
11099  *               rd -----
11100  */
11101 std::string NMD::MUL_32_(uint64 instruction)
11102 {
11103     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11104     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11105     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11106
11107     std::string rd = GPR(copy(rd_value));
11108     std::string rs = GPR(copy(rs_value));
11109     std::string rt = GPR(copy(rt_value));
11110
11111     return img::format("MUL %s, %s, %s", rd, rs, rt);
11112 }
11113
11114
11115 /*
11116  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11117  *
11118  *   3         2         1
11119  *  10987654321098765432109876543210
11120  *  001000               00010001101
11121  *     rt -----
11122  *          rs -----
11123  *               rd -----
11124  */
11125 std::string NMD::MUL_4X4_(uint64 instruction)
11126 {
11127     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
11128     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
11129
11130     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
11131     std::string rt4 = GPR(decode_gpr_gpr4(rt4_value));
11132
11133     return img::format("MUL %s, %s", rs4, rt4);
11134 }
11135
11136
11137 /*
11138  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11139  *
11140  *   3         2         1
11141  *  10987654321098765432109876543210
11142  *  001000               00010001101
11143  *     rt -----
11144  *          rs -----
11145  *               rd -----
11146  */
11147 std::string NMD::MUL_D(uint64 instruction)
11148 {
11149     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11150     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11151     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
11152
11153     std::string fd = FPR(copy(fd_value));
11154     std::string fs = FPR(copy(fs_value));
11155     std::string ft = FPR(copy(ft_value));
11156
11157     return img::format("MUL.D %s, %s, %s", fd, fs, ft);
11158 }
11159
11160
11161 /*
11162  * [DSP] MUL.PH rd, rs, rt - Multiply vector integer half words to same size
11163  *   products
11164  *
11165  *   3         2         1
11166  *  10987654321098765432109876543210
11167  *  001000               00000101101
11168  *     rt -----
11169  *          rs -----
11170  *               rd -----
11171  */
11172 std::string NMD::MUL_PH(uint64 instruction)
11173 {
11174     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11175     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11176     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11177
11178     std::string rd = GPR(copy(rd_value));
11179     std::string rs = GPR(copy(rs_value));
11180     std::string rt = GPR(copy(rt_value));
11181
11182     return img::format("MUL.PH %s, %s, %s", rd, rs, rt);
11183 }
11184
11185
11186 /*
11187  * [DSP] MUL_S.PH rd, rs, rt - Multiply vector integer half words to same size
11188  *   products (saturated)
11189  *
11190  *   3         2         1
11191  *  10987654321098765432109876543210
11192  *  001000               10000101101
11193  *     rt -----
11194  *          rs -----
11195  *               rd -----
11196  */
11197 std::string NMD::MUL_S_PH(uint64 instruction)
11198 {
11199     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11200     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11201     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11202
11203     std::string rd = GPR(copy(rd_value));
11204     std::string rs = GPR(copy(rs_value));
11205     std::string rt = GPR(copy(rt_value));
11206
11207     return img::format("MUL_S.PH %s, %s, %s", rd, rs, rt);
11208 }
11209
11210
11211 /*
11212  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11213  *
11214  *   3         2         1
11215  *  10987654321098765432109876543210
11216  *  001000               00010001101
11217  *     rt -----
11218  *          rs -----
11219  *               rd -----
11220  */
11221 std::string NMD::MUL_S(uint64 instruction)
11222 {
11223     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11224     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11225     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
11226
11227     std::string fd = FPR(copy(fd_value));
11228     std::string fs = FPR(copy(fs_value));
11229     std::string ft = FPR(copy(ft_value));
11230
11231     return img::format("MUL.S %s, %s, %s", fd, fs, ft);
11232 }
11233
11234
11235 /*
11236  * [DSP] MULEQ_S.W.PHL rd, rs, rt - Multiply vector fractional left halfwords
11237  *   to expanded width products
11238  *
11239  *   3         2         1
11240  *  10987654321098765432109876543210
11241  *  001000               x0000100101
11242  *     rt -----
11243  *          rs -----
11244  *               rd -----
11245  */
11246 std::string NMD::MULEQ_S_W_PHL(uint64 instruction)
11247 {
11248     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11249     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11250     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11251
11252     std::string rd = GPR(copy(rd_value));
11253     std::string rs = GPR(copy(rs_value));
11254     std::string rt = GPR(copy(rt_value));
11255
11256     return img::format("MULEQ_S.W.PHL %s, %s, %s", rd, rs, rt);
11257 }
11258
11259
11260 /*
11261  * [DSP] MULEQ_S.W.PHR rd, rs, rt - Multiply vector fractional right halfwords
11262  *   to expanded width products
11263  *
11264  *   3         2         1
11265  *  10987654321098765432109876543210
11266  *  001000               x0001100101
11267  *     rt -----
11268  *          rs -----
11269  *               rd -----
11270  */
11271 std::string NMD::MULEQ_S_W_PHR(uint64 instruction)
11272 {
11273     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11274     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11275     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11276
11277     std::string rd = GPR(copy(rd_value));
11278     std::string rs = GPR(copy(rs_value));
11279     std::string rt = GPR(copy(rt_value));
11280
11281     return img::format("MULEQ_S.W.PHR %s, %s, %s", rd, rs, rt);
11282 }
11283
11284
11285 /*
11286  * [DSP] MULEU_S.PH.QBL rd, rs, rt - Multiply vector fractional left bytes
11287  *   by halfwords to halfword products
11288  *
11289  *   3         2         1
11290  *  10987654321098765432109876543210
11291  *  001000               x0010010101
11292  *     rt -----
11293  *          rs -----
11294  *               rd -----
11295  */
11296 std::string NMD::MULEU_S_PH_QBL(uint64 instruction)
11297 {
11298     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11299     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11300     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11301
11302     std::string rd = GPR(copy(rd_value));
11303     std::string rs = GPR(copy(rs_value));
11304     std::string rt = GPR(copy(rt_value));
11305
11306     return img::format("MULEU_S.PH.QBL %s, %s, %s", rd, rs, rt);
11307 }
11308
11309
11310 /*
11311  * [DSP] MULEU_S.PH.QBR rd, rs, rt - Multiply vector fractional right bytes
11312  *   by halfwords to halfword products
11313  *
11314  *   3         2         1
11315  *  10987654321098765432109876543210
11316  *  001000               x0011010101
11317  *     rt -----
11318  *          rs -----
11319  *               rd -----
11320  */
11321 std::string NMD::MULEU_S_PH_QBR(uint64 instruction)
11322 {
11323     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11324     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11325     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11326
11327     std::string rd = GPR(copy(rd_value));
11328     std::string rs = GPR(copy(rs_value));
11329     std::string rt = GPR(copy(rt_value));
11330
11331     return img::format("MULEU_S.PH.QBR %s, %s, %s", rd, rs, rt);
11332 }
11333
11334
11335 /*
11336  * [DSP] MULQ_RS.PH rd, rs, rt - Multiply vector fractional halfwords
11337  *   to fractional halfword products
11338  *
11339  *   3         2         1
11340  *  10987654321098765432109876543210
11341  *  001000               x0100010101
11342  *     rt -----
11343  *          rs -----
11344  *               rd -----
11345  */
11346 std::string NMD::MULQ_RS_PH(uint64 instruction)
11347 {
11348     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11349     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11350     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11351
11352     std::string rd = GPR(copy(rd_value));
11353     std::string rs = GPR(copy(rs_value));
11354     std::string rt = GPR(copy(rt_value));
11355
11356     return img::format("MULQ_RS.PH %s, %s, %s", rd, rs, rt);
11357 }
11358
11359
11360 /*
11361  * [DSP] MULQ_RS.W rd, rs, rt - Multiply fractional words to same size
11362  *   product with saturation and rounding
11363  *
11364  *   3         2         1
11365  *  10987654321098765432109876543210
11366  *  001000               x0110010101
11367  *     rt -----
11368  *          rs -----
11369  *               rd -----
11370  */
11371 std::string NMD::MULQ_RS_W(uint64 instruction)
11372 {
11373     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11374     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11375     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11376
11377     std::string rd = GPR(copy(rd_value));
11378     std::string rs = GPR(copy(rs_value));
11379     std::string rt = GPR(copy(rt_value));
11380
11381     return img::format("MULQ_RS.W %s, %s, %s", rd, rs, rt);
11382 }
11383
11384
11385 /*
11386  * [DSP] MULQ_S.PH rd, rs, rt - Multiply fractional halfwords to same size
11387  *   products
11388  *
11389  *   3         2         1
11390  *  10987654321098765432109876543210
11391  *  001000               x0101010101
11392  *     rt -----
11393  *          rs -----
11394  *               rd -----
11395  */
11396 std::string NMD::MULQ_S_PH(uint64 instruction)
11397 {
11398     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11399     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11400     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11401
11402     std::string rd = GPR(copy(rd_value));
11403     std::string rs = GPR(copy(rs_value));
11404     std::string rt = GPR(copy(rt_value));
11405
11406     return img::format("MULQ_S.PH %s, %s, %s", rd, rs, rt);
11407 }
11408
11409
11410 /*
11411  * [DSP] MULQ_S.W rd, rs, rt - Multiply fractional words to same size product
11412  *   with saturation
11413  *
11414  *   3         2         1
11415  *  10987654321098765432109876543210
11416  *  001000               x0111010101
11417  *     rt -----
11418  *          rs -----
11419  *               rd -----
11420  */
11421 std::string NMD::MULQ_S_W(uint64 instruction)
11422 {
11423     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11424     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11425     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11426
11427     std::string rd = GPR(copy(rd_value));
11428     std::string rs = GPR(copy(rs_value));
11429     std::string rt = GPR(copy(rt_value));
11430
11431     return img::format("MULQ_S.W %s, %s, %s", rd, rs, rt);
11432 }
11433
11434
11435 /*
11436  * [DSP] MULSA.W.PH ac, rs, rt - Multiply and subtract vector integer halfword
11437  *   elements and accumulate
11438  *
11439  *   3         2         1
11440  *  10987654321098765432109876543210
11441  *  001000            10110010111111
11442  *     rt -----
11443  *          rs -----
11444  *               ac --
11445  */
11446 std::string NMD::MULSA_W_PH(uint64 instruction)
11447 {
11448     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11449     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11450     uint64 ac_value = extract_ac_15_14(instruction);
11451
11452     std::string ac = AC(copy(ac_value));
11453     std::string rs = GPR(copy(rs_value));
11454     std::string rt = GPR(copy(rt_value));
11455
11456     return img::format("MULSA.W.PH %s, %s, %s", ac, rs, rt);
11457 }
11458
11459
11460 /*
11461  * [DSP] MULSAQ_S.W.PH ac, rs, rt - Multiply and subtract vector fractional
11462  *   halfwords and accumulate
11463  *
11464  *   3         2         1
11465  *  10987654321098765432109876543210
11466  *  001000            11110010111111
11467  *     rt -----
11468  *          rs -----
11469  *               ac --
11470  */
11471 std::string NMD::MULSAQ_S_W_PH(uint64 instruction)
11472 {
11473     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11474     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11475     uint64 ac_value = extract_ac_15_14(instruction);
11476
11477     std::string ac = AC(copy(ac_value));
11478     std::string rs = GPR(copy(rs_value));
11479     std::string rt = GPR(copy(rt_value));
11480
11481     return img::format("MULSAQ_S.W.PH %s, %s, %s", ac, rs, rt);
11482 }
11483
11484
11485 /*
11486  * [DSP] MULT ac, rs, rt - Multiply word
11487  *
11488  *   3         2         1
11489  *  10987654321098765432109876543210
11490  *  001000            00110010111111
11491  *     rt -----
11492  *          rs -----
11493  *               ac --
11494  */
11495 std::string NMD::MULT_DSP_(uint64 instruction)
11496 {
11497     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11498     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11499     uint64 ac_value = extract_ac_15_14(instruction);
11500
11501     std::string ac = AC(copy(ac_value));
11502     std::string rs = GPR(copy(rs_value));
11503     std::string rt = GPR(copy(rt_value));
11504
11505     return img::format("MULT %s, %s, %s", ac, rs, rt);
11506 }
11507
11508
11509 /*
11510  * [DSP] MULTU ac, rs, rt - Multiply unsigned word
11511  *
11512  *   3         2         1
11513  *  10987654321098765432109876543210
11514  *  001000            01110010111111
11515  *     rt -----
11516  *          rs -----
11517  *               ac --
11518  */
11519 std::string NMD::MULTU_DSP_(uint64 instruction)
11520 {
11521     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11522     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11523     uint64 ac_value = extract_ac_15_14(instruction);
11524
11525     std::string ac = AC(copy(ac_value));
11526     std::string rs = GPR(copy(rs_value));
11527     std::string rt = GPR(copy(rt_value));
11528
11529     return img::format("MULTU %s, %s, %s", ac, rs, rt);
11530 }
11531
11532
11533 /*
11534  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11535  *
11536  *   3         2         1
11537  *  10987654321098765432109876543210
11538  *  001000               00010001101
11539  *     rt -----
11540  *          rs -----
11541  *               rd -----
11542  */
11543 std::string NMD::MULU(uint64 instruction)
11544 {
11545     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11546     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11547     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11548
11549     std::string rd = GPR(copy(rd_value));
11550     std::string rs = GPR(copy(rs_value));
11551     std::string rt = GPR(copy(rt_value));
11552
11553     return img::format("MULU %s, %s, %s", rd, rs, rt);
11554 }
11555
11556
11557 /*
11558  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11559  *
11560  *   3         2         1
11561  *  10987654321098765432109876543210
11562  *  001000               00010001101
11563  *     rt -----
11564  *          rs -----
11565  *               rd -----
11566  */
11567 std::string NMD::NEG_D(uint64 instruction)
11568 {
11569     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11570     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11571
11572     std::string ft = FPR(copy(ft_value));
11573     std::string fs = FPR(copy(fs_value));
11574
11575     return img::format("NEG.D %s, %s", ft, fs);
11576 }
11577
11578
11579 /*
11580  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11581  *
11582  *   3         2         1
11583  *  10987654321098765432109876543210
11584  *  001000               00010001101
11585  *     rt -----
11586  *          rs -----
11587  *               rd -----
11588  */
11589 std::string NMD::NEG_S(uint64 instruction)
11590 {
11591     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11592     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11593
11594     std::string ft = FPR(copy(ft_value));
11595     std::string fs = FPR(copy(fs_value));
11596
11597     return img::format("NEG.S %s, %s", ft, fs);
11598 }
11599
11600
11601 /*
11602  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11603  *
11604  *   3         2         1
11605  *  10987654321098765432109876543210
11606  *  001000               00010001101
11607  *     rt -----
11608  *          rs -----
11609  *               rd -----
11610  */
11611 std::string NMD::NOP_16_(uint64 instruction)
11612 {
11613     (void)instruction;
11614
11615     return "NOP ";
11616 }
11617
11618
11619 /*
11620  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11621  *
11622  *   3         2         1
11623  *  10987654321098765432109876543210
11624  *  001000               00010001101
11625  *     rt -----
11626  *          rs -----
11627  *               rd -----
11628  */
11629 std::string NMD::NOP_32_(uint64 instruction)
11630 {
11631     (void)instruction;
11632
11633     return "NOP ";
11634 }
11635
11636
11637 /*
11638  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11639  *
11640  *   3         2         1
11641  *  10987654321098765432109876543210
11642  *  001000               00010001101
11643  *     rt -----
11644  *          rs -----
11645  *               rd -----
11646  */
11647 std::string NMD::NOR(uint64 instruction)
11648 {
11649     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11650     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11651     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11652
11653     std::string rd = GPR(copy(rd_value));
11654     std::string rs = GPR(copy(rs_value));
11655     std::string rt = GPR(copy(rt_value));
11656
11657     return img::format("NOR %s, %s, %s", rd, rs, rt);
11658 }
11659
11660
11661 /*
11662  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11663  *
11664  *   3         2         1
11665  *  10987654321098765432109876543210
11666  *  001000               00010001101
11667  *     rt -----
11668  *          rs -----
11669  *               rd -----
11670  */
11671 std::string NMD::NOT_16_(uint64 instruction)
11672 {
11673     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11674     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11675
11676     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
11677     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
11678
11679     return img::format("NOT %s, %s", rt3, rs3);
11680 }
11681
11682
11683 /*
11684  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11685  *
11686  *   3         2         1
11687  *  10987654321098765432109876543210
11688  *  001000               00010001101
11689  *     rt -----
11690  *          rs -----
11691  *               rd -----
11692  */
11693 std::string NMD::OR_16_(uint64 instruction)
11694 {
11695     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11696     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11697
11698     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
11699     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
11700
11701     return img::format("OR %s, %s", rs3, rt3);
11702 }
11703
11704
11705 /*
11706  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11707  *
11708  *   3         2         1
11709  *  10987654321098765432109876543210
11710  *  001000               00010001101
11711  *     rt -----
11712  *          rs -----
11713  *               rd -----
11714  */
11715 std::string NMD::OR_32_(uint64 instruction)
11716 {
11717     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11718     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11719     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11720
11721     std::string rd = GPR(copy(rd_value));
11722     std::string rs = GPR(copy(rs_value));
11723     std::string rt = GPR(copy(rt_value));
11724
11725     return img::format("OR %s, %s, %s", rd, rs, rt);
11726 }
11727
11728
11729 /*
11730  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11731  *
11732  *   3         2         1
11733  *  10987654321098765432109876543210
11734  *  001000               00010001101
11735  *     rt -----
11736  *          rs -----
11737  *               rd -----
11738  */
11739 std::string NMD::ORI(uint64 instruction)
11740 {
11741     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11742     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11743     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
11744
11745     std::string rt = GPR(copy(rt_value));
11746     std::string rs = GPR(copy(rs_value));
11747     std::string u = IMMEDIATE(copy(u_value));
11748
11749     return img::format("ORI %s, %s, %s", rt, rs, u);
11750 }
11751
11752
11753 /*
11754  * [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
11755  *         source register and left halfword from another source register
11756  *
11757  *   3         2         1
11758  *  10987654321098765432109876543210
11759  *  001000               00010001101
11760  *     rt -----
11761  *          rs -----
11762  *               rd -----
11763  */
11764 std::string NMD::PACKRL_PH(uint64 instruction)
11765 {
11766     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11767     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11768     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11769
11770     std::string rd = GPR(copy(rd_value));
11771     std::string rs = GPR(copy(rs_value));
11772     std::string rt = GPR(copy(rt_value));
11773
11774     return img::format("PACKRL.PH %s, %s, %s", rd, rs, rt);
11775 }
11776
11777
11778 /*
11779  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11780  *
11781  *   3         2         1
11782  *  10987654321098765432109876543210
11783  *  001000               00010001101
11784  *     rt -----
11785  *          rs -----
11786  *               rd -----
11787  */
11788 std::string NMD::PAUSE(uint64 instruction)
11789 {
11790     (void)instruction;
11791
11792     return "PAUSE ";
11793 }
11794
11795
11796 /*
11797  * [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
11798  *         code bits
11799  *
11800  *   3         2         1
11801  *  10987654321098765432109876543210
11802  *  001000               00010001101
11803  *     rt -----
11804  *          rs -----
11805  *               rd -----
11806  */
11807 std::string NMD::PICK_PH(uint64 instruction)
11808 {
11809     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11810     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11811     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11812
11813     std::string rd = GPR(copy(rd_value));
11814     std::string rs = GPR(copy(rs_value));
11815     std::string rt = GPR(copy(rt_value));
11816
11817     return img::format("PICK.PH %s, %s, %s", rd, rs, rt);
11818 }
11819
11820
11821 /*
11822  * [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
11823  *         code bits
11824  *
11825  *   3         2         1
11826  *  10987654321098765432109876543210
11827  *  001000               00010001101
11828  *     rt -----
11829  *          rs -----
11830  *               rd -----
11831  */
11832 std::string NMD::PICK_QB(uint64 instruction)
11833 {
11834     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11835     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11836     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11837
11838     std::string rd = GPR(copy(rd_value));
11839     std::string rs = GPR(copy(rs_value));
11840     std::string rt = GPR(copy(rt_value));
11841
11842     return img::format("PICK.QB %s, %s, %s", rd, rs, rt);
11843 }
11844
11845
11846 /*
11847  * [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
11848  *         of a paired halfword
11849  *
11850  *   3         2         1
11851  *  10987654321098765432109876543210
11852  *  001000               00010001101
11853  *     rt -----
11854  *          rs -----
11855  *               rd -----
11856  */
11857 std::string NMD::PRECEQ_W_PHL(uint64 instruction)
11858 {
11859     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11860     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11861
11862     std::string rt = GPR(copy(rt_value));
11863     std::string rs = GPR(copy(rs_value));
11864
11865     return img::format("PRECEQ.W.PHL %s, %s", rt, rs);
11866 }
11867
11868
11869 /*
11870  * [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
11871  *         of a paired halfword
11872  *
11873  *   3         2         1
11874  *  10987654321098765432109876543210
11875  *  001000               00010001101
11876  *     rt -----
11877  *          rs -----
11878  *               rd -----
11879  */
11880 std::string NMD::PRECEQ_W_PHR(uint64 instruction)
11881 {
11882     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11883     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11884
11885     std::string rt = GPR(copy(rt_value));
11886     std::string rs = GPR(copy(rs_value));
11887
11888     return img::format("PRECEQ.W.PHR %s, %s", rt, rs);
11889 }
11890
11891
11892 /*
11893  * [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
11894  *         left-alternate elements of a quad byte vector
11895  *
11896  *   3         2         1
11897  *  10987654321098765432109876543210
11898  *  001000               00010001101
11899  *     rt -----
11900  *          rs -----
11901  *               rd -----
11902  */
11903 std::string NMD::PRECEQU_PH_QBLA(uint64 instruction)
11904 {
11905     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11906     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11907
11908     std::string rt = GPR(copy(rt_value));
11909     std::string rs = GPR(copy(rs_value));
11910
11911     return img::format("PRECEQU.PH.QBLA %s, %s", rt, rs);
11912 }
11913
11914
11915 /*
11916  * [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
11917  *         elements of a quad byte vector
11918  *
11919  *   3         2         1
11920  *  10987654321098765432109876543210
11921  *  001000               00010001101
11922  *     rt -----
11923  *          rs -----
11924  *               rd -----
11925  */
11926 std::string NMD::PRECEQU_PH_QBL(uint64 instruction)
11927 {
11928     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11929     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11930
11931     std::string rt = GPR(copy(rt_value));
11932     std::string rs = GPR(copy(rs_value));
11933
11934     return img::format("PRECEQU.PH.QBL %s, %s", rt, rs);
11935 }
11936
11937
11938 /*
11939  * [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
11940  *         right-alternate elements of a quad byte vector
11941  *
11942  *   3         2         1
11943  *  10987654321098765432109876543210
11944  *  001000               00010001101
11945  *     rt -----
11946  *          rs -----
11947  *               rd -----
11948  */
11949 std::string NMD::PRECEQU_PH_QBRA(uint64 instruction)
11950 {
11951     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11952     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11953
11954     std::string rt = GPR(copy(rt_value));
11955     std::string rs = GPR(copy(rs_value));
11956
11957     return img::format("PRECEQU.PH.QBRA %s, %s", rt, rs);
11958 }
11959
11960
11961 /*
11962  * [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
11963  *         elements of a quad byte vector
11964  *
11965  *   3         2         1
11966  *  10987654321098765432109876543210
11967  *  001000               00010001101
11968  *     rt -----
11969  *          rs -----
11970  *               rd -----
11971  */
11972 std::string NMD::PRECEQU_PH_QBR(uint64 instruction)
11973 {
11974     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11975     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11976
11977     std::string rt = GPR(copy(rt_value));
11978     std::string rs = GPR(copy(rs_value));
11979
11980     return img::format("PRECEQU.PH.QBR %s, %s", rt, rs);
11981 }
11982
11983
11984 /*
11985  * [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
11986  *         left-alternate elements of a quad byte vector to four unsigned
11987  *         halfwords
11988  *
11989  *   3         2         1
11990  *  10987654321098765432109876543210
11991  *  001000               00010001101
11992  *     rt -----
11993  *          rs -----
11994  *               rd -----
11995  */
11996 std::string NMD::PRECEU_PH_QBLA(uint64 instruction)
11997 {
11998     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11999     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12000
12001     std::string rt = GPR(copy(rt_value));
12002     std::string rs = GPR(copy(rs_value));
12003
12004     return img::format("PRECEU.PH.QBLA %s, %s", rt, rs);
12005 }
12006
12007
12008 /*
12009  * [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
12010  *         elements of a quad byte vector to form unsigned halfwords
12011  *
12012  *   3         2         1
12013  *  10987654321098765432109876543210
12014  *  001000               00010001101
12015  *     rt -----
12016  *          rs -----
12017  *               rd -----
12018  */
12019 std::string NMD::PRECEU_PH_QBL(uint64 instruction)
12020 {
12021     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12022     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12023
12024     std::string rt = GPR(copy(rt_value));
12025     std::string rs = GPR(copy(rs_value));
12026
12027     return img::format("PRECEU.PH.QBL %s, %s", rt, rs);
12028 }
12029
12030
12031 /*
12032  * [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
12033  *         right-alternate elements of a quad byte vector to form four
12034  *         unsigned halfwords
12035  *
12036  *   3         2         1
12037  *  10987654321098765432109876543210
12038  *  001000               00010001101
12039  *     rt -----
12040  *          rs -----
12041  *               rd -----
12042  */
12043 std::string NMD::PRECEU_PH_QBRA(uint64 instruction)
12044 {
12045     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12046     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12047
12048     std::string rt = GPR(copy(rt_value));
12049     std::string rs = GPR(copy(rs_value));
12050
12051     return img::format("PRECEU.PH.QBRA %s, %s", rt, rs);
12052 }
12053
12054
12055 /*
12056  * [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
12057  *         elements of a quad byte vector to form unsigned halfwords
12058  *
12059  *   3         2         1
12060  *  10987654321098765432109876543210
12061  *  001000               00010001101
12062  *     rt -----
12063  *          rs -----
12064  *               rd -----
12065  */
12066 std::string NMD::PRECEU_PH_QBR(uint64 instruction)
12067 {
12068     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12069     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12070
12071     std::string rt = GPR(copy(rt_value));
12072     std::string rs = GPR(copy(rs_value));
12073
12074     return img::format("PRECEU.PH.QBR %s, %s", rt, rs);
12075 }
12076
12077
12078 /*
12079  * [DSP] PRECR.QB.PH rd, rs, rt - Reduce the precision of four integer
12080  *   halfwords to four bytes
12081  *
12082  *   3         2         1
12083  *  10987654321098765432109876543210
12084  *  001000               x0001101101
12085  *     rt -----
12086  *          rs -----
12087  *               rd -----
12088  */
12089 std::string NMD::PRECR_QB_PH(uint64 instruction)
12090 {
12091     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12092     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12093     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12094
12095     std::string rd = GPR(copy(rd_value));
12096     std::string rs = GPR(copy(rs_value));
12097     std::string rt = GPR(copy(rt_value));
12098
12099     return img::format("PRECR.QB.PH %s, %s, %s", rd, rs, rt);
12100 }
12101
12102
12103 /*
12104  * [DSP] PRECR_SRA.PH.W rt, rs, sa - Reduce the precision of two integer
12105  *   words to halfwords after a right shift
12106  *
12107  *   3         2         1
12108  *  10987654321098765432109876543210
12109  *  001000               x1110000101
12110  *     rt -----
12111  *          rs -----
12112  *               rd -----
12113  */
12114 std::string NMD::PRECR_SRA_PH_W(uint64 instruction)
12115 {
12116     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12117     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12118     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12119
12120     std::string rt = GPR(copy(rt_value));
12121     std::string rs = GPR(copy(rs_value));
12122     std::string sa = IMMEDIATE(copy(sa_value));
12123
12124     return img::format("PRECR_SRA.PH.W %s, %s, %s", rt, rs, sa);
12125 }
12126
12127
12128 /*
12129  * [DSP] PRECR_SRA_R.PH.W rt, rs, sa - Reduce the precision of two integer
12130  *   words to halfwords after a right shift with rounding
12131  *
12132  *   3         2         1
12133  *  10987654321098765432109876543210
12134  *  001000               x1110000101
12135  *     rt -----
12136  *          rs -----
12137  *               rd -----
12138  */
12139 std::string NMD::PRECR_SRA_R_PH_W(uint64 instruction)
12140 {
12141     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12142     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12143     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12144
12145     std::string rt = GPR(copy(rt_value));
12146     std::string rs = GPR(copy(rs_value));
12147     std::string sa = IMMEDIATE(copy(sa_value));
12148
12149     return img::format("PRECR_SRA_R.PH.W %s, %s, %s", rt, rs, sa);
12150 }
12151
12152
12153 /*
12154  * [DSP] PRECRQ.PH.W rd, rs, rt - Reduce the precision of fractional
12155  *   words to fractional halfwords
12156  *
12157  *   3         2         1
12158  *  10987654321098765432109876543210
12159  *  001000               x1110000101
12160  *     rt -----
12161  *          rs -----
12162  *               rd -----
12163  */
12164 std::string NMD::PRECRQ_PH_W(uint64 instruction)
12165 {
12166     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12167     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12168     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12169
12170     std::string rd = GPR(copy(rd_value));
12171     std::string rs = GPR(copy(rs_value));
12172     std::string rt = GPR(copy(rt_value));
12173
12174     return img::format("PRECRQ.PH.W %s, %s, %s", rd, rs, rt);
12175 }
12176
12177
12178 /*
12179  * [DSP] PRECRQ.QB.PH rd, rs, rt - Reduce the precision of four fractional
12180  *   halfwords to four bytes
12181  *
12182  *   3         2         1
12183  *  10987654321098765432109876543210
12184  *  001000               x0010101101
12185  *     rt -----
12186  *          rs -----
12187  *               rd -----
12188  */
12189 std::string NMD::PRECRQ_QB_PH(uint64 instruction)
12190 {
12191     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12192     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12193     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12194
12195     std::string rd = GPR(copy(rd_value));
12196     std::string rs = GPR(copy(rs_value));
12197     std::string rt = GPR(copy(rt_value));
12198
12199     return img::format("PRECRQ.QB.PH %s, %s, %s", rd, rs, rt);
12200 }
12201
12202
12203 /*
12204  * [DSP] PRECRQ_RS.PH.W rd, rs, rt - Reduce the precision of fractional
12205  *   words to halfwords with rounding and saturation
12206  *
12207  *   3         2         1
12208  *  10987654321098765432109876543210
12209  *  001000               x1110000101
12210  *     rt -----
12211  *          rs -----
12212  *               rd -----
12213  */
12214 std::string NMD::PRECRQ_RS_PH_W(uint64 instruction)
12215 {
12216     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12217     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12218     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12219
12220     std::string rd = GPR(copy(rd_value));
12221     std::string rs = GPR(copy(rs_value));
12222     std::string rt = GPR(copy(rt_value));
12223
12224     return img::format("PRECRQ_RS.PH.W %s, %s, %s", rd, rs, rt);
12225 }
12226
12227
12228 /*
12229  * [DSP] PRECRQU_S.QB.PH rd, rs, rt - Reduce the precision of fractional
12230  *   halfwords to unsigned bytes with saturation
12231  *
12232  *   3         2         1
12233  *  10987654321098765432109876543210
12234  *  001000               x1110000101
12235  *     rt -----
12236  *          rs -----
12237  *               rd -----
12238  */
12239 std::string NMD::PRECRQU_S_QB_PH(uint64 instruction)
12240 {
12241     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12242     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12243     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12244
12245     std::string rd = GPR(copy(rd_value));
12246     std::string rs = GPR(copy(rs_value));
12247     std::string rt = GPR(copy(rt_value));
12248
12249     return img::format("PRECRQU_S.QB.PH %s, %s, %s", rd, rs, rt);
12250 }
12251
12252
12253 /*
12254  *
12255  *
12256  *   3         2         1
12257  *  10987654321098765432109876543210
12258  *  001000               x1110000101
12259  *     rt -----
12260  *          rs -----
12261  *               rd -----
12262  */
12263 std::string NMD::PREF_S9_(uint64 instruction)
12264 {
12265     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12266     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12267     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12268
12269     std::string hint = IMMEDIATE(copy(hint_value));
12270     std::string s = IMMEDIATE(copy(s_value));
12271     std::string rs = GPR(copy(rs_value));
12272
12273     return img::format("PREF %s, %s(%s)", hint, s, rs);
12274 }
12275
12276
12277 /*
12278  *
12279  *
12280  *   3         2         1
12281  *  10987654321098765432109876543210
12282  *  001000               x1110000101
12283  *     rt -----
12284  *          rs -----
12285  *               rd -----
12286  */
12287 std::string NMD::PREF_U12_(uint64 instruction)
12288 {
12289     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12290     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12291     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12292
12293     std::string hint = IMMEDIATE(copy(hint_value));
12294     std::string u = IMMEDIATE(copy(u_value));
12295     std::string rs = GPR(copy(rs_value));
12296
12297     return img::format("PREF %s, %s(%s)", hint, u, rs);
12298 }
12299
12300
12301 /*
12302  *
12303  *
12304  *   3         2         1
12305  *  10987654321098765432109876543210
12306  *  001000               x1110000101
12307  *     rt -----
12308  *          rs -----
12309  *               rd -----
12310  */
12311 std::string NMD::PREFE(uint64 instruction)
12312 {
12313     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
12314     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12315     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12316
12317     std::string hint = IMMEDIATE(copy(hint_value));
12318     std::string s = IMMEDIATE(copy(s_value));
12319     std::string rs = GPR(copy(rs_value));
12320
12321     return img::format("PREFE %s, %s(%s)", hint, s, rs);
12322 }
12323
12324
12325 /*
12326  * [DSP] PREPEND rt, rs, sa - Right shift and prepend bits to the MSB
12327  *
12328  *   3         2         1
12329  *  10987654321098765432109876543210
12330  *  001000               x1110000101
12331  *     rt -----
12332  *          rs -----
12333  *               rd -----
12334  */
12335 std::string NMD::PREPEND(uint64 instruction)
12336 {
12337     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12338     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12339     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
12340
12341     std::string rt = GPR(copy(rt_value));
12342     std::string rs = GPR(copy(rs_value));
12343     std::string sa = IMMEDIATE(copy(sa_value));
12344
12345     return img::format("PREPEND %s, %s, %s", rt, rs, sa);
12346 }
12347
12348
12349 /*
12350  * [DSP] RADDU.W.QB rt, rs - Unsigned reduction add of vector quad bytes
12351  *
12352  *   3         2         1
12353  *  10987654321098765432109876543210
12354  *  001000          1111000100111111
12355  *     rt -----
12356  *          rs -----
12357  */
12358 std::string NMD::RADDU_W_QB(uint64 instruction)
12359 {
12360     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12361     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12362
12363     std::string rt = GPR(copy(rt_value));
12364     std::string rs = GPR(copy(rs_value));
12365
12366     return img::format("RADDU.W.QB %s, %s", rt, rs);
12367 }
12368
12369
12370 /*
12371  * [DSP] RDDSP rt, mask - Read DSPControl register fields to a GPR
12372  *
12373  *   3         2         1
12374  *  10987654321098765432109876543210
12375  *  001000            00011001111111
12376  *     rt -----
12377  *        mask -------
12378  */
12379 std::string NMD::RDDSP(uint64 instruction)
12380 {
12381     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12382     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
12383
12384     std::string rt = GPR(copy(rt_value));
12385     std::string mask = IMMEDIATE(copy(mask_value));
12386
12387     return img::format("RDDSP %s, %s", rt, mask);
12388 }
12389
12390
12391 /*
12392  *
12393  *
12394  *   3         2         1
12395  *  10987654321098765432109876543210
12396  *  001000               x1110000101
12397  *     rt -----
12398  *          rs -----
12399  *               rd -----
12400  */
12401 std::string NMD::RDHWR(uint64 instruction)
12402 {
12403     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12404     uint64 hs_value = extract_hs_20_19_18_17_16(instruction);
12405     uint64 sel_value = extract_sel_13_12_11(instruction);
12406
12407     std::string rt = GPR(copy(rt_value));
12408     std::string hs = CPR(copy(hs_value));
12409     std::string sel = IMMEDIATE(copy(sel_value));
12410
12411     return img::format("RDHWR %s, %s, %s", rt, hs, sel);
12412 }
12413
12414
12415 /*
12416  *
12417  *
12418  *   3         2         1
12419  *  10987654321098765432109876543210
12420  *  001000               x1110000101
12421  *     rt -----
12422  *          rs -----
12423  *               rd -----
12424  */
12425 std::string NMD::RDPGPR(uint64 instruction)
12426 {
12427     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12428     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12429
12430     std::string rt = GPR(copy(rt_value));
12431     std::string rs = GPR(copy(rs_value));
12432
12433     return img::format("RDPGPR %s, %s", rt, rs);
12434 }
12435
12436
12437 /*
12438  *
12439  *
12440  *   3         2         1
12441  *  10987654321098765432109876543210
12442  *  001000               x1110000101
12443  *     rt -----
12444  *          rs -----
12445  *               rd -----
12446  */
12447 std::string NMD::RECIP_D(uint64 instruction)
12448 {
12449     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12450     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12451
12452     std::string ft = FPR(copy(ft_value));
12453     std::string fs = FPR(copy(fs_value));
12454
12455     return img::format("RECIP.D %s, %s", ft, fs);
12456 }
12457
12458
12459 /*
12460  *
12461  *
12462  *   3         2         1
12463  *  10987654321098765432109876543210
12464  *  001000               x1110000101
12465  *     rt -----
12466  *          rs -----
12467  *               rd -----
12468  */
12469 std::string NMD::RECIP_S(uint64 instruction)
12470 {
12471     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12472     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12473
12474     std::string ft = FPR(copy(ft_value));
12475     std::string fs = FPR(copy(fs_value));
12476
12477     return img::format("RECIP.S %s, %s", ft, fs);
12478 }
12479
12480
12481 /*
12482  * [DSP] REPL.PH rd, s - Replicate immediate integer into all vector element
12483  *   positions
12484  *
12485  *   3         2         1
12486  *  10987654321098765432109876543210
12487  *  001000               x0000111101
12488  *     rt -----
12489  *           s ----------
12490  */
12491 std::string NMD::REPL_PH(uint64 instruction)
12492 {
12493     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12494     int64 s_value = extract_s__se9_20_19_18_17_16_15_14_13_12_11(instruction);
12495
12496     std::string rt = GPR(copy(rt_value));
12497     std::string s = IMMEDIATE(copy(s_value));
12498
12499     return img::format("REPL.PH %s, %s", rt, s);
12500 }
12501
12502
12503 /*
12504  * [DSP] REPL.QB rd, u - Replicate immediate integer into all vector element
12505  *   positions
12506  *
12507  *   3         2         1
12508  *  10987654321098765432109876543210
12509  *  001000             x010111111111
12510  *     rt -----
12511  *           u --------
12512  */
12513 std::string NMD::REPL_QB(uint64 instruction)
12514 {
12515     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12516     uint64 u_value = extract_u_20_19_18_17_16_15_14_13(instruction);
12517
12518     std::string rt = GPR(copy(rt_value));
12519     std::string u = IMMEDIATE(copy(u_value));
12520
12521     return img::format("REPL.QB %s, %s", rt, u);
12522 }
12523
12524
12525 /*
12526  * [DSP] REPLV.PH rt, rs - Replicate a halfword into all vector element
12527  *   positions
12528  *
12529  *   3         2         1
12530  *  10987654321098765432109876543210
12531  *  001000          0000001100111111
12532  *     rt -----
12533  *          rs -----
12534  */
12535 std::string NMD::REPLV_PH(uint64 instruction)
12536 {
12537     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12538     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12539
12540     std::string rt = GPR(copy(rt_value));
12541     std::string rs = GPR(copy(rs_value));
12542
12543     return img::format("REPLV.PH %s, %s", rt, rs);
12544 }
12545
12546
12547 /*
12548  * [DSP] REPLV.QB rt, rs - Replicate byte into all vector element positions
12549  *
12550  *   3         2         1
12551  *  10987654321098765432109876543210
12552  *  001000          0001001100111111
12553  *     rt -----
12554  *          rs -----
12555  */
12556 std::string NMD::REPLV_QB(uint64 instruction)
12557 {
12558     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12559     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12560
12561     std::string rt = GPR(copy(rt_value));
12562     std::string rs = GPR(copy(rs_value));
12563
12564     return img::format("REPLV.QB %s, %s", rt, rs);
12565 }
12566
12567
12568 /*
12569  *
12570  *
12571  *   3         2         1
12572  *  10987654321098765432109876543210
12573  *  001000               x1110000101
12574  *     rt -----
12575  *          rs -----
12576  *               rd -----
12577  */
12578 std::string NMD::RESTORE_32_(uint64 instruction)
12579 {
12580     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12581     uint64 count_value = extract_count_19_18_17_16(instruction);
12582     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12583     uint64 gp_value = extract_gp_2(instruction);
12584
12585     std::string u = IMMEDIATE(copy(u_value));
12586     return img::format("RESTORE %s%s", u,
12587                save_restore_list(rt_value, count_value, gp_value));
12588 }
12589
12590
12591 /*
12592  *
12593  *
12594  *   3         2         1
12595  *  10987654321098765432109876543210
12596  *  001000               x1110000101
12597  *     rt -----
12598  *          rs -----
12599  *               rd -----
12600  */
12601 std::string NMD::RESTORE_JRC_16_(uint64 instruction)
12602 {
12603     uint64 rt1_value = extract_rtl_11(instruction);
12604     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12605     uint64 count_value = extract_count_3_2_1_0(instruction);
12606
12607     std::string u = IMMEDIATE(copy(u_value));
12608     return img::format("RESTORE.JRC %s%s", u,
12609         save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));
12610 }
12611
12612
12613 /*
12614  *
12615  *
12616  *   3         2         1
12617  *  10987654321098765432109876543210
12618  *  001000               x1110000101
12619  *     rt -----
12620  *          rs -----
12621  *               rd -----
12622  */
12623 std::string NMD::RESTORE_JRC_32_(uint64 instruction)
12624 {
12625     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12626     uint64 count_value = extract_count_19_18_17_16(instruction);
12627     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12628     uint64 gp_value = extract_gp_2(instruction);
12629
12630     std::string u = IMMEDIATE(copy(u_value));
12631     return img::format("RESTORE.JRC %s%s", u,
12632                save_restore_list(rt_value, count_value, gp_value));
12633 }
12634
12635
12636 /*
12637  *
12638  *
12639  *   3         2         1
12640  *  10987654321098765432109876543210
12641  *  001000               x1110000101
12642  *     rt -----
12643  *          rs -----
12644  *               rd -----
12645  */
12646 std::string NMD::RESTOREF(uint64 instruction)
12647 {
12648     uint64 count_value = extract_count_19_18_17_16(instruction);
12649     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12650
12651     std::string u = IMMEDIATE(copy(u_value));
12652     std::string count = IMMEDIATE(copy(count_value));
12653
12654     return img::format("RESTOREF %s, %s", u, count);
12655 }
12656
12657
12658 /*
12659  *
12660  *
12661  *   3         2         1
12662  *  10987654321098765432109876543210
12663  *  001000               x1110000101
12664  *     rt -----
12665  *          rs -----
12666  *               rd -----
12667  */
12668 std::string NMD::RINT_D(uint64 instruction)
12669 {
12670     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12671     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12672
12673     std::string ft = FPR(copy(ft_value));
12674     std::string fs = FPR(copy(fs_value));
12675
12676     return img::format("RINT.D %s, %s", ft, fs);
12677 }
12678
12679
12680 /*
12681  *
12682  *
12683  *   3         2         1
12684  *  10987654321098765432109876543210
12685  *  001000               x1110000101
12686  *     rt -----
12687  *          rs -----
12688  *               rd -----
12689  */
12690 std::string NMD::RINT_S(uint64 instruction)
12691 {
12692     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12693     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12694
12695     std::string ft = FPR(copy(ft_value));
12696     std::string fs = FPR(copy(fs_value));
12697
12698     return img::format("RINT.S %s, %s", ft, fs);
12699 }
12700
12701
12702 /*
12703  *
12704  *
12705  *   3         2         1
12706  *  10987654321098765432109876543210
12707  *  001000               x1110000101
12708  *     rt -----
12709  *          rs -----
12710  *               rd -----
12711  */
12712 std::string NMD::ROTR(uint64 instruction)
12713 {
12714     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12715     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12716     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12717
12718     std::string rt = GPR(copy(rt_value));
12719     std::string rs = GPR(copy(rs_value));
12720     std::string shift = IMMEDIATE(copy(shift_value));
12721
12722     return img::format("ROTR %s, %s, %s", rt, rs, shift);
12723 }
12724
12725
12726 /*
12727  *
12728  *
12729  *   3         2         1
12730  *  10987654321098765432109876543210
12731  *  001000               x1110000101
12732  *     rt -----
12733  *          rs -----
12734  *               rd -----
12735  */
12736 std::string NMD::ROTRV(uint64 instruction)
12737 {
12738     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12739     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12740     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12741
12742     std::string rd = GPR(copy(rd_value));
12743     std::string rs = GPR(copy(rs_value));
12744     std::string rt = GPR(copy(rt_value));
12745
12746     return img::format("ROTRV %s, %s, %s", rd, rs, rt);
12747 }
12748
12749
12750 /*
12751  *
12752  *
12753  *   3         2         1
12754  *  10987654321098765432109876543210
12755  *  001000               x1110000101
12756  *     rt -----
12757  *          rs -----
12758  *               rd -----
12759  */
12760 std::string NMD::ROTX(uint64 instruction)
12761 {
12762     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12763     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12764     uint64 shiftx_value = extract_shiftx_10_9_8_7__s1(instruction);
12765     uint64 stripe_value = extract_stripe_6(instruction);
12766     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12767
12768     std::string rt = GPR(copy(rt_value));
12769     std::string rs = GPR(copy(rs_value));
12770     std::string shift = IMMEDIATE(copy(shift_value));
12771     std::string shiftx = IMMEDIATE(copy(shiftx_value));
12772     std::string stripe = IMMEDIATE(copy(stripe_value));
12773
12774     return img::format("ROTX %s, %s, %s, %s, %s",
12775                        rt, rs, shift, shiftx, stripe);
12776 }
12777
12778
12779 /*
12780  *
12781  *
12782  *   3         2         1
12783  *  10987654321098765432109876543210
12784  *  001000               x1110000101
12785  *     rt -----
12786  *          rs -----
12787  *               rd -----
12788  */
12789 std::string NMD::ROUND_L_D(uint64 instruction)
12790 {
12791     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12792     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12793
12794     std::string ft = FPR(copy(ft_value));
12795     std::string fs = FPR(copy(fs_value));
12796
12797     return img::format("ROUND.L.D %s, %s", ft, fs);
12798 }
12799
12800
12801 /*
12802  *
12803  *
12804  *   3         2         1
12805  *  10987654321098765432109876543210
12806  *  001000               x1110000101
12807  *     rt -----
12808  *          rs -----
12809  *               rd -----
12810  */
12811 std::string NMD::ROUND_L_S(uint64 instruction)
12812 {
12813     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12814     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12815
12816     std::string ft = FPR(copy(ft_value));
12817     std::string fs = FPR(copy(fs_value));
12818
12819     return img::format("ROUND.L.S %s, %s", ft, fs);
12820 }
12821
12822
12823 /*
12824  *
12825  *
12826  *   3         2         1
12827  *  10987654321098765432109876543210
12828  *  001000               x1110000101
12829  *     rt -----
12830  *          rs -----
12831  *               rd -----
12832  */
12833 std::string NMD::ROUND_W_D(uint64 instruction)
12834 {
12835     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12836     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12837
12838     std::string ft = FPR(copy(ft_value));
12839     std::string fs = FPR(copy(fs_value));
12840
12841     return img::format("ROUND.W.D %s, %s", ft, fs);
12842 }
12843
12844
12845 /*
12846  *
12847  *
12848  *   3         2         1
12849  *  10987654321098765432109876543210
12850  *  001000               x1110000101
12851  *     rt -----
12852  *          rs -----
12853  *               rd -----
12854  */
12855 std::string NMD::ROUND_W_S(uint64 instruction)
12856 {
12857     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12858     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12859
12860     std::string ft = FPR(copy(ft_value));
12861     std::string fs = FPR(copy(fs_value));
12862
12863     return img::format("ROUND.W.S %s, %s", ft, fs);
12864 }
12865
12866
12867 /*
12868  *
12869  *
12870  *   3         2         1
12871  *  10987654321098765432109876543210
12872  *  001000               x1110000101
12873  *     rt -----
12874  *          rs -----
12875  *               rd -----
12876  */
12877 std::string NMD::RSQRT_D(uint64 instruction)
12878 {
12879     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12880     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12881
12882     std::string ft = FPR(copy(ft_value));
12883     std::string fs = FPR(copy(fs_value));
12884
12885     return img::format("RSQRT.D %s, %s", ft, fs);
12886 }
12887
12888
12889 /*
12890  *
12891  *
12892  *   3         2         1
12893  *  10987654321098765432109876543210
12894  *  001000               x1110000101
12895  *     rt -----
12896  *          rs -----
12897  *               rd -----
12898  */
12899 std::string NMD::RSQRT_S(uint64 instruction)
12900 {
12901     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12902     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12903
12904     std::string ft = FPR(copy(ft_value));
12905     std::string fs = FPR(copy(fs_value));
12906
12907     return img::format("RSQRT.S %s, %s", ft, fs);
12908 }
12909
12910
12911 /*
12912  *
12913  *
12914  *   3         2         1
12915  *  10987654321098765432109876543210
12916  *  001000               01001001101
12917  *     rt -----
12918  *          rs -----
12919  *               rd -----
12920  */
12921 std::string NMD::SAVE_16_(uint64 instruction)
12922 {
12923     uint64 rt1_value = extract_rtl_11(instruction);
12924     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12925     uint64 count_value = extract_count_3_2_1_0(instruction);
12926
12927     std::string u = IMMEDIATE(copy(u_value));
12928     return img::format("SAVE %s%s", u,
12929         save_restore_list(encode_rt1_from_rt(rt1_value), count_value, 0));
12930 }
12931
12932
12933 /*
12934  *
12935  *
12936  *   3         2         1
12937  *  10987654321098765432109876543210
12938  *  001000               01001001101
12939  *     rt -----
12940  *          rs -----
12941  *               rd -----
12942  */
12943 std::string NMD::SAVE_32_(uint64 instruction)
12944 {
12945     uint64 count_value = extract_count_19_18_17_16(instruction);
12946     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12947     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12948     uint64 gp_value = extract_gp_2(instruction);
12949
12950     std::string u = IMMEDIATE(copy(u_value));
12951     return img::format("SAVE %s%s", u,
12952                save_restore_list(rt_value, count_value, gp_value));
12953 }
12954
12955
12956 /*
12957  *
12958  *
12959  *   3         2         1
12960  *  10987654321098765432109876543210
12961  *  001000               01001001101
12962  *     rt -----
12963  *          rs -----
12964  *               rd -----
12965  */
12966 std::string NMD::SAVEF(uint64 instruction)
12967 {
12968     uint64 count_value = extract_count_19_18_17_16(instruction);
12969     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12970
12971     std::string u = IMMEDIATE(copy(u_value));
12972     std::string count = IMMEDIATE(copy(count_value));
12973
12974     return img::format("SAVEF %s, %s", u, count);
12975 }
12976
12977
12978 /*
12979  *
12980  *
12981  *   3         2         1
12982  *  10987654321098765432109876543210
12983  *  001000               01001001101
12984  *     rt -----
12985  *          rs -----
12986  *               rd -----
12987  */
12988 std::string NMD::SB_16_(uint64 instruction)
12989 {
12990     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
12991     uint64 rs3_value = extract_rs3_6_5_4(instruction);
12992     uint64 u_value = extract_u_1_0(instruction);
12993
12994     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
12995     std::string u = IMMEDIATE(copy(u_value));
12996     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
12997
12998     return img::format("SB %s, %s(%s)", rtz3, u, rs3);
12999 }
13000
13001
13002 /*
13003  *
13004  *
13005  *   3         2         1
13006  *  10987654321098765432109876543210
13007  *  001000               01001001101
13008  *     rt -----
13009  *          rs -----
13010  *               rd -----
13011  */
13012 std::string NMD::SB_GP_(uint64 instruction)
13013 {
13014     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13015     uint64 u_value = extract_u_17_to_0(instruction);
13016
13017     std::string rt = GPR(copy(rt_value));
13018     std::string u = IMMEDIATE(copy(u_value));
13019
13020     return img::format("SB %s, %s($%d)", rt, u, 28);
13021 }
13022
13023
13024 /*
13025  *
13026  *
13027  *   3         2         1
13028  *  10987654321098765432109876543210
13029  *  001000               01001001101
13030  *     rt -----
13031  *          rs -----
13032  *               rd -----
13033  */
13034 std::string NMD::SB_S9_(uint64 instruction)
13035 {
13036     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13037     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13038     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13039
13040     std::string rt = GPR(copy(rt_value));
13041     std::string s = IMMEDIATE(copy(s_value));
13042     std::string rs = GPR(copy(rs_value));
13043
13044     return img::format("SB %s, %s(%s)", rt, s, rs);
13045 }
13046
13047
13048 /*
13049  *
13050  *
13051  *   3         2         1
13052  *  10987654321098765432109876543210
13053  *  001000               01001001101
13054  *     rt -----
13055  *          rs -----
13056  *               rd -----
13057  */
13058 std::string NMD::SB_U12_(uint64 instruction)
13059 {
13060     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13061     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13062     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13063
13064     std::string rt = GPR(copy(rt_value));
13065     std::string u = IMMEDIATE(copy(u_value));
13066     std::string rs = GPR(copy(rs_value));
13067
13068     return img::format("SB %s, %s(%s)", rt, u, rs);
13069 }
13070
13071
13072 /*
13073  *
13074  *
13075  *   3         2         1
13076  *  10987654321098765432109876543210
13077  *  001000               01001001101
13078  *     rt -----
13079  *          rs -----
13080  *               rd -----
13081  */
13082 std::string NMD::SBE(uint64 instruction)
13083 {
13084     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13085     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13086     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13087
13088     std::string rt = GPR(copy(rt_value));
13089     std::string s = IMMEDIATE(copy(s_value));
13090     std::string rs = GPR(copy(rs_value));
13091
13092     return img::format("SBE %s, %s(%s)", rt, s, rs);
13093 }
13094
13095
13096 /*
13097  *
13098  *
13099  *   3         2         1
13100  *  10987654321098765432109876543210
13101  *  001000               01001001101
13102  *     rt -----
13103  *          rs -----
13104  *               rd -----
13105  */
13106 std::string NMD::SBX(uint64 instruction)
13107 {
13108     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13109     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13110     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13111
13112     std::string rd = GPR(copy(rd_value));
13113     std::string rs = GPR(copy(rs_value));
13114     std::string rt = GPR(copy(rt_value));
13115
13116     return img::format("SBX %s, %s(%s)", rd, rs, rt);
13117 }
13118
13119
13120 /*
13121  *
13122  *
13123  *   3         2         1
13124  *  10987654321098765432109876543210
13125  *  001000               01001001101
13126  *     rt -----
13127  *          rs -----
13128  *               rd -----
13129  */
13130 std::string NMD::SC(uint64 instruction)
13131 {
13132     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13133     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13134     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
13135
13136     std::string rt = GPR(copy(rt_value));
13137     std::string s = IMMEDIATE(copy(s_value));
13138     std::string rs = GPR(copy(rs_value));
13139
13140     return img::format("SC %s, %s(%s)", rt, s, rs);
13141 }
13142
13143
13144 /*
13145  *
13146  *
13147  *   3         2         1
13148  *  10987654321098765432109876543210
13149  *  001000               01001001101
13150  *     rt -----
13151  *          rs -----
13152  *               rd -----
13153  */
13154 std::string NMD::SCD(uint64 instruction)
13155 {
13156     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13157     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13158     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
13159
13160     std::string rt = GPR(copy(rt_value));
13161     std::string s = IMMEDIATE(copy(s_value));
13162     std::string rs = GPR(copy(rs_value));
13163
13164     return img::format("SCD %s, %s(%s)", rt, s, rs);
13165 }
13166
13167
13168 /*
13169  *
13170  *
13171  *   3         2         1
13172  *  10987654321098765432109876543210
13173  *  001000               01001001101
13174  *     rt -----
13175  *          rs -----
13176  *               rd -----
13177  */
13178 std::string NMD::SCDP(uint64 instruction)
13179 {
13180     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13181     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13182     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13183
13184     std::string rt = GPR(copy(rt_value));
13185     std::string ru = GPR(copy(ru_value));
13186     std::string rs = GPR(copy(rs_value));
13187
13188     return img::format("SCDP %s, %s, (%s)", rt, ru, rs);
13189 }
13190
13191
13192 /*
13193  *
13194  *
13195  *   3         2         1
13196  *  10987654321098765432109876543210
13197  *  001000               01001001101
13198  *     rt -----
13199  *          rs -----
13200  *               rd -----
13201  */
13202 std::string NMD::SCE(uint64 instruction)
13203 {
13204     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13205     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13206     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
13207
13208     std::string rt = GPR(copy(rt_value));
13209     std::string s = IMMEDIATE(copy(s_value));
13210     std::string rs = GPR(copy(rs_value));
13211
13212     return img::format("SCE %s, %s(%s)", rt, s, rs);
13213 }
13214
13215
13216 /*
13217  *
13218  *
13219  *   3         2         1
13220  *  10987654321098765432109876543210
13221  *  001000               01001001101
13222  *     rt -----
13223  *          rs -----
13224  *               rd -----
13225  */
13226 std::string NMD::SCWP(uint64 instruction)
13227 {
13228     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13229     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13230     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13231
13232     std::string rt = GPR(copy(rt_value));
13233     std::string ru = GPR(copy(ru_value));
13234     std::string rs = GPR(copy(rs_value));
13235
13236     return img::format("SCWP %s, %s, (%s)", rt, ru, rs);
13237 }
13238
13239
13240 /*
13241  *
13242  *
13243  *   3         2         1
13244  *  10987654321098765432109876543210
13245  *  001000               01001001101
13246  *     rt -----
13247  *          rs -----
13248  *               rd -----
13249  */
13250 std::string NMD::SCWPE(uint64 instruction)
13251 {
13252     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13253     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13254     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
13255
13256     std::string rt = GPR(copy(rt_value));
13257     std::string ru = GPR(copy(ru_value));
13258     std::string rs = GPR(copy(rs_value));
13259
13260     return img::format("SCWPE %s, %s, (%s)", rt, ru, rs);
13261 }
13262
13263
13264 /*
13265  *
13266  *
13267  *   3         2         1
13268  *  10987654321098765432109876543210
13269  *  001000               01001001101
13270  *     rt -----
13271  *          rs -----
13272  *               rd -----
13273  */
13274 std::string NMD::SD_GP_(uint64 instruction)
13275 {
13276     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13277     uint64 u_value = extract_u_20_to_3__s3(instruction);
13278
13279     std::string rt = GPR(copy(rt_value));
13280     std::string u = IMMEDIATE(copy(u_value));
13281
13282     return img::format("SD %s, %s($%d)", rt, u, 28);
13283 }
13284
13285
13286 /*
13287  *
13288  *
13289  *   3         2         1
13290  *  10987654321098765432109876543210
13291  *  001000               01001001101
13292  *     rt -----
13293  *          rs -----
13294  *               rd -----
13295  */
13296 std::string NMD::SD_S9_(uint64 instruction)
13297 {
13298     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13299     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13300     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13301
13302     std::string rt = GPR(copy(rt_value));
13303     std::string s = IMMEDIATE(copy(s_value));
13304     std::string rs = GPR(copy(rs_value));
13305
13306     return img::format("SD %s, %s(%s)", rt, s, rs);
13307 }
13308
13309
13310 /*
13311  *
13312  *
13313  *   3         2         1
13314  *  10987654321098765432109876543210
13315  *  001000               01001001101
13316  *     rt -----
13317  *          rs -----
13318  *               rd -----
13319  */
13320 std::string NMD::SD_U12_(uint64 instruction)
13321 {
13322     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13323     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13324     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13325
13326     std::string rt = GPR(copy(rt_value));
13327     std::string u = IMMEDIATE(copy(u_value));
13328     std::string rs = GPR(copy(rs_value));
13329
13330     return img::format("SD %s, %s(%s)", rt, u, rs);
13331 }
13332
13333
13334 /*
13335  *
13336  *
13337  *   3         2         1
13338  *  10987654321098765432109876543210
13339  *  001000               01001001101
13340  *     rt -----
13341  *          rs -----
13342  *               rd -----
13343  */
13344 std::string NMD::SDBBP_16_(uint64 instruction)
13345 {
13346     uint64 code_value = extract_code_2_1_0(instruction);
13347
13348     std::string code = IMMEDIATE(copy(code_value));
13349
13350     return img::format("SDBBP %s", code);
13351 }
13352
13353
13354 /*
13355  *
13356  *
13357  *   3         2         1
13358  *  10987654321098765432109876543210
13359  *  001000               01001001101
13360  *     rt -----
13361  *          rs -----
13362  *               rd -----
13363  */
13364 std::string NMD::SDBBP_32_(uint64 instruction)
13365 {
13366     uint64 code_value = extract_code_18_to_0(instruction);
13367
13368     std::string code = IMMEDIATE(copy(code_value));
13369
13370     return img::format("SDBBP %s", code);
13371 }
13372
13373
13374 /*
13375  *
13376  *
13377  *   3         2         1
13378  *  10987654321098765432109876543210
13379  *  001000               01001001101
13380  *     rt -----
13381  *          rs -----
13382  *               rd -----
13383  */
13384 std::string NMD::SDC1_GP_(uint64 instruction)
13385 {
13386     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13387     uint64 u_value = extract_u_17_to_2__s2(instruction);
13388
13389     std::string ft = FPR(copy(ft_value));
13390     std::string u = IMMEDIATE(copy(u_value));
13391
13392     return img::format("SDC1 %s, %s($%d)", ft, u, 28);
13393 }
13394
13395
13396 /*
13397  *
13398  *
13399  *   3         2         1
13400  *  10987654321098765432109876543210
13401  *  001000               01001001101
13402  *     rt -----
13403  *          rs -----
13404  *               rd -----
13405  */
13406 std::string NMD::SDC1_S9_(uint64 instruction)
13407 {
13408     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13409     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13410     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13411
13412     std::string ft = FPR(copy(ft_value));
13413     std::string s = IMMEDIATE(copy(s_value));
13414     std::string rs = GPR(copy(rs_value));
13415
13416     return img::format("SDC1 %s, %s(%s)", ft, s, rs);
13417 }
13418
13419
13420 /*
13421  *
13422  *
13423  *   3         2         1
13424  *  10987654321098765432109876543210
13425  *  001000               01001001101
13426  *     rt -----
13427  *          rs -----
13428  *               rd -----
13429  */
13430 std::string NMD::SDC1_U12_(uint64 instruction)
13431 {
13432     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13433     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13434     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13435
13436     std::string ft = FPR(copy(ft_value));
13437     std::string u = IMMEDIATE(copy(u_value));
13438     std::string rs = GPR(copy(rs_value));
13439
13440     return img::format("SDC1 %s, %s(%s)", ft, u, rs);
13441 }
13442
13443
13444 /*
13445  *
13446  *
13447  *   3         2         1
13448  *  10987654321098765432109876543210
13449  *  001000               01001001101
13450  *     rt -----
13451  *          rs -----
13452  *               rd -----
13453  */
13454 std::string NMD::SDC1X(uint64 instruction)
13455 {
13456     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13457     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13458     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13459
13460     std::string ft = FPR(copy(ft_value));
13461     std::string rs = GPR(copy(rs_value));
13462     std::string rt = GPR(copy(rt_value));
13463
13464     return img::format("SDC1X %s, %s(%s)", ft, rs, rt);
13465 }
13466
13467
13468 /*
13469  *
13470  *
13471  *   3         2         1
13472  *  10987654321098765432109876543210
13473  *  001000               01001001101
13474  *     rt -----
13475  *          rs -----
13476  *               rd -----
13477  */
13478 std::string NMD::SDC1XS(uint64 instruction)
13479 {
13480     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13481     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13482     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13483
13484     std::string ft = FPR(copy(ft_value));
13485     std::string rs = GPR(copy(rs_value));
13486     std::string rt = GPR(copy(rt_value));
13487
13488     return img::format("SDC1XS %s, %s(%s)", ft, rs, rt);
13489 }
13490
13491
13492 /*
13493  *
13494  *
13495  *   3         2         1
13496  *  10987654321098765432109876543210
13497  *  001000               01001001101
13498  *     rt -----
13499  *          rs -----
13500  *               rd -----
13501  */
13502 std::string NMD::SDC2(uint64 instruction)
13503 {
13504     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
13505     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13506     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13507
13508     std::string cs = CPR(copy(cs_value));
13509     std::string s = IMMEDIATE(copy(s_value));
13510     std::string rs = GPR(copy(rs_value));
13511
13512     return img::format("SDC2 %s, %s(%s)", cs, s, rs);
13513 }
13514
13515
13516 /*
13517  *
13518  *
13519  *   3         2         1
13520  *  10987654321098765432109876543210
13521  *  001000               01001001101
13522  *     rt -----
13523  *          rs -----
13524  *               rd -----
13525  */
13526 std::string NMD::SDM(uint64 instruction)
13527 {
13528     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13529     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13530     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13531     uint64 count3_value = extract_count3_14_13_12(instruction);
13532
13533     std::string rt = GPR(copy(rt_value));
13534     std::string s = IMMEDIATE(copy(s_value));
13535     std::string rs = GPR(copy(rs_value));
13536     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
13537
13538     return img::format("SDM %s, %s(%s), %s", rt, s, rs, count3);
13539 }
13540
13541
13542 /*
13543  *
13544  *
13545  *   3         2         1
13546  *  10987654321098765432109876543210
13547  *  001000               01001001101
13548  *     rt -----
13549  *          rs -----
13550  *               rd -----
13551  */
13552 std::string NMD::SDPC_48_(uint64 instruction)
13553 {
13554     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
13555     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
13556
13557     std::string rt = GPR(copy(rt_value));
13558     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
13559
13560     return img::format("SDPC %s, %s", rt, s);
13561 }
13562
13563
13564 /*
13565  *
13566  *
13567  *   3         2         1
13568  *  10987654321098765432109876543210
13569  *  001000               01001001101
13570  *     rt -----
13571  *          rs -----
13572  *               rd -----
13573  */
13574 std::string NMD::SDXS(uint64 instruction)
13575 {
13576     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13577     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13578     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13579
13580     std::string rd = GPR(copy(rd_value));
13581     std::string rs = GPR(copy(rs_value));
13582     std::string rt = GPR(copy(rt_value));
13583
13584     return img::format("SDXS %s, %s(%s)", rd, rs, rt);
13585 }
13586
13587
13588 /*
13589  *
13590  *
13591  *   3         2         1
13592  *  10987654321098765432109876543210
13593  *  001000               01001001101
13594  *     rt -----
13595  *          rs -----
13596  *               rd -----
13597  */
13598 std::string NMD::SDX(uint64 instruction)
13599 {
13600     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13601     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13602     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13603
13604     std::string rd = GPR(copy(rd_value));
13605     std::string rs = GPR(copy(rs_value));
13606     std::string rt = GPR(copy(rt_value));
13607
13608     return img::format("SDX %s, %s(%s)", rd, rs, rt);
13609 }
13610
13611
13612 /*
13613  *
13614  *
13615  *   3         2         1
13616  *  10987654321098765432109876543210
13617  *  001000               01001001101
13618  *     rt -----
13619  *          rs -----
13620  *               rd -----
13621  */
13622 std::string NMD::SEB(uint64 instruction)
13623 {
13624     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13625     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13626
13627     std::string rt = GPR(copy(rt_value));
13628     std::string rs = GPR(copy(rs_value));
13629
13630     return img::format("SEB %s, %s", rt, rs);
13631 }
13632
13633
13634 /*
13635  *
13636  *
13637  *   3         2         1
13638  *  10987654321098765432109876543210
13639  *  001000               01001001101
13640  *     rt -----
13641  *          rs -----
13642  *               rd -----
13643  */
13644 std::string NMD::SEH(uint64 instruction)
13645 {
13646     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13647     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13648
13649     std::string rt = GPR(copy(rt_value));
13650     std::string rs = GPR(copy(rs_value));
13651
13652     return img::format("SEH %s, %s", rt, rs);
13653 }
13654
13655
13656 /*
13657  *
13658  *
13659  *   3         2         1
13660  *  10987654321098765432109876543210
13661  *  001000               01001001101
13662  *     rt -----
13663  *          rs -----
13664  *               rd -----
13665  */
13666 std::string NMD::SEL_D(uint64 instruction)
13667 {
13668     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13669     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13670     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13671
13672     std::string fd = FPR(copy(fd_value));
13673     std::string fs = FPR(copy(fs_value));
13674     std::string ft = FPR(copy(ft_value));
13675
13676     return img::format("SEL.D %s, %s, %s", fd, fs, ft);
13677 }
13678
13679
13680 /*
13681  *
13682  *
13683  *   3         2         1
13684  *  10987654321098765432109876543210
13685  *  001000               01001001101
13686  *     rt -----
13687  *          rs -----
13688  *               rd -----
13689  */
13690 std::string NMD::SEL_S(uint64 instruction)
13691 {
13692     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13693     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13694     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13695
13696     std::string fd = FPR(copy(fd_value));
13697     std::string fs = FPR(copy(fs_value));
13698     std::string ft = FPR(copy(ft_value));
13699
13700     return img::format("SEL.S %s, %s, %s", fd, fs, ft);
13701 }
13702
13703
13704 /*
13705  *
13706  *
13707  *   3         2         1
13708  *  10987654321098765432109876543210
13709  *  001000               01001001101
13710  *     rt -----
13711  *          rs -----
13712  *               rd -----
13713  */
13714 std::string NMD::SELEQZ_D(uint64 instruction)
13715 {
13716     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13717     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13718     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13719
13720     std::string fd = FPR(copy(fd_value));
13721     std::string fs = FPR(copy(fs_value));
13722     std::string ft = FPR(copy(ft_value));
13723
13724     return img::format("SELEQZ.D %s, %s, %s", fd, fs, ft);
13725 }
13726
13727
13728 /*
13729  *
13730  *
13731  *   3         2         1
13732  *  10987654321098765432109876543210
13733  *  001000               01001001101
13734  *     rt -----
13735  *          rs -----
13736  *               rd -----
13737  */
13738 std::string NMD::SELEQZ_S(uint64 instruction)
13739 {
13740     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13741     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13742     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13743
13744     std::string fd = FPR(copy(fd_value));
13745     std::string fs = FPR(copy(fs_value));
13746     std::string ft = FPR(copy(ft_value));
13747
13748     return img::format("SELEQZ.S %s, %s, %s", fd, fs, ft);
13749 }
13750
13751
13752 /*
13753  *
13754  *
13755  *   3         2         1
13756  *  10987654321098765432109876543210
13757  *  001000               01001001101
13758  *     rt -----
13759  *          rs -----
13760  *               rd -----
13761  */
13762 std::string NMD::SELNEZ_D(uint64 instruction)
13763 {
13764     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13765     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13766     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13767
13768     std::string fd = FPR(copy(fd_value));
13769     std::string fs = FPR(copy(fs_value));
13770     std::string ft = FPR(copy(ft_value));
13771
13772     return img::format("SELNEZ.D %s, %s, %s", fd, fs, ft);
13773 }
13774
13775
13776 /*
13777  *
13778  *
13779  *   3         2         1
13780  *  10987654321098765432109876543210
13781  *  001000               01001001101
13782  *     rt -----
13783  *          rs -----
13784  *               rd -----
13785  */
13786 std::string NMD::SELNEZ_S(uint64 instruction)
13787 {
13788     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13789     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13790     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13791
13792     std::string fd = FPR(copy(fd_value));
13793     std::string fs = FPR(copy(fs_value));
13794     std::string ft = FPR(copy(ft_value));
13795
13796     return img::format("SELNEZ.S %s, %s, %s", fd, fs, ft);
13797 }
13798
13799
13800 /*
13801  *
13802  *
13803  *   3         2         1
13804  *  10987654321098765432109876543210
13805  *  001000               01001001101
13806  *     rt -----
13807  *          rs -----
13808  *               rd -----
13809  */
13810 std::string NMD::SEQI(uint64 instruction)
13811 {
13812     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13813     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13814     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13815
13816     std::string rt = GPR(copy(rt_value));
13817     std::string rs = GPR(copy(rs_value));
13818     std::string u = IMMEDIATE(copy(u_value));
13819
13820     return img::format("SEQI %s, %s, %s", rt, rs, u);
13821 }
13822
13823
13824 /*
13825  *
13826  *
13827  *   3         2         1
13828  *  10987654321098765432109876543210
13829  *  001000               01001001101
13830  *     rt -----
13831  *          rs -----
13832  *               rd -----
13833  */
13834 std::string NMD::SH_16_(uint64 instruction)
13835 {
13836     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
13837     uint64 rs3_value = extract_rs3_6_5_4(instruction);
13838     uint64 u_value = extract_u_2_1__s1(instruction);
13839
13840     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
13841     std::string u = IMMEDIATE(copy(u_value));
13842     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
13843
13844     return img::format("SH %s, %s(%s)", rtz3, u, rs3);
13845 }
13846
13847
13848 /*
13849  *
13850  *
13851  *   3         2         1
13852  *  10987654321098765432109876543210
13853  *  001000               01001001101
13854  *     rt -----
13855  *          rs -----
13856  *               rd -----
13857  */
13858 std::string NMD::SH_GP_(uint64 instruction)
13859 {
13860     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13861     uint64 u_value = extract_u_17_to_1__s1(instruction);
13862
13863     std::string rt = GPR(copy(rt_value));
13864     std::string u = IMMEDIATE(copy(u_value));
13865
13866     return img::format("SH %s, %s($%d)", rt, u, 28);
13867 }
13868
13869
13870 /*
13871  *
13872  *
13873  *   3         2         1
13874  *  10987654321098765432109876543210
13875  *  001000               01001001101
13876  *     rt -----
13877  *          rs -----
13878  *               rd -----
13879  */
13880 std::string NMD::SH_S9_(uint64 instruction)
13881 {
13882     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13883     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13884     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13885
13886     std::string rt = GPR(copy(rt_value));
13887     std::string s = IMMEDIATE(copy(s_value));
13888     std::string rs = GPR(copy(rs_value));
13889
13890     return img::format("SH %s, %s(%s)", rt, s, rs);
13891 }
13892
13893
13894 /*
13895  *
13896  *
13897  *   3         2         1
13898  *  10987654321098765432109876543210
13899  *  001000               01001001101
13900  *     rt -----
13901  *          rs -----
13902  *               rd -----
13903  */
13904 std::string NMD::SH_U12_(uint64 instruction)
13905 {
13906     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13907     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13908     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13909
13910     std::string rt = GPR(copy(rt_value));
13911     std::string u = IMMEDIATE(copy(u_value));
13912     std::string rs = GPR(copy(rs_value));
13913
13914     return img::format("SH %s, %s(%s)", rt, u, rs);
13915 }
13916
13917
13918 /*
13919  *
13920  *
13921  *   3         2         1
13922  *  10987654321098765432109876543210
13923  *  001000               01001001101
13924  *     rt -----
13925  *          rs -----
13926  *               rd -----
13927  */
13928 std::string NMD::SHE(uint64 instruction)
13929 {
13930     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13931     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13932     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13933
13934     std::string rt = GPR(copy(rt_value));
13935     std::string s = IMMEDIATE(copy(s_value));
13936     std::string rs = GPR(copy(rs_value));
13937
13938     return img::format("SHE %s, %s(%s)", rt, s, rs);
13939 }
13940
13941
13942 /*
13943  * [DSP] SHILO ac, shift - Shift an accumulator value leaving the result in
13944  *   the same accumulator
13945  *
13946  *   3         2         1
13947  *  10987654321098765432109876543210
13948  *  001000xxxx        xxxx0000011101
13949  *      shift ------
13950  *               ac --
13951  */
13952 std::string NMD::SHILO(uint64 instruction)
13953 {
13954     int64 shift_value = extract_shift__se5_21_20_19_18_17_16(instruction);
13955     uint64 ac_value = extract_ac_15_14(instruction);
13956
13957     std::string shift = IMMEDIATE(copy(shift_value));
13958     std::string ac = AC(copy(ac_value));
13959
13960     return img::format("SHILO %s, %s", ac, shift);
13961 }
13962
13963
13964 /*
13965  * [DSP] SHILOV ac, rs - Variable shift of accumulator value leaving the result
13966  *   in the same accumulator
13967  *
13968  *   3         2         1
13969  *  10987654321098765432109876543210
13970  *  001000xxxxx       01001001111111
13971  *          rs -----
13972  *               ac --
13973  */
13974 std::string NMD::SHILOV(uint64 instruction)
13975 {
13976     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13977     uint64 ac_value = extract_ac_15_14(instruction);
13978
13979     std::string rs = GPR(copy(rs_value));
13980     std::string ac = AC(copy(ac_value));
13981
13982     return img::format("SHILOV %s, %s", ac, rs);
13983 }
13984
13985
13986 /*
13987  * [DSP] SHLL.PH rt, rs, sa - Shift left logical vector pair halfwords
13988  *
13989  *   3         2         1
13990  *  10987654321098765432109876543210
13991  *  001000              001110110101
13992  *     rt -----
13993  *          rs -----
13994  *               sa ----
13995  */
13996 std::string NMD::SHLL_PH(uint64 instruction)
13997 {
13998     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13999     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14000     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14001
14002     std::string rt = GPR(copy(rt_value));
14003     std::string rs = GPR(copy(rs_value));
14004     std::string sa = IMMEDIATE(copy(sa_value));
14005
14006     return img::format("SHLL.PH %s, %s, %s", rt, rs, sa);
14007 }
14008
14009
14010 /*
14011  * [DSP] SHLL.QB rt, rs, sa - Shift left logical vector quad bytes
14012  *
14013  *   3         2         1
14014  *  10987654321098765432109876543210
14015  *  001000             0100001111111
14016  *     rt -----
14017  *          rs -----
14018  *               sa ---
14019  */
14020 std::string NMD::SHLL_QB(uint64 instruction)
14021 {
14022     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14023     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14024     uint64 sa_value = extract_sa_15_14_13(instruction);
14025
14026     std::string rt = GPR(copy(rt_value));
14027     std::string rs = GPR(copy(rs_value));
14028     std::string sa = IMMEDIATE(copy(sa_value));
14029
14030     return img::format("SHLL.QB %s, %s, %s", rt, rs, sa);
14031 }
14032
14033
14034 /*
14035  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical vector pair halfwords
14036  *   with saturation
14037  *
14038  *   3         2         1
14039  *  10987654321098765432109876543210
14040  *  001000              001110110101
14041  *     rt -----
14042  *          rs -----
14043  *               sa ----
14044  */
14045 std::string NMD::SHLL_S_PH(uint64 instruction)
14046 {
14047     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14048     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14049     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14050
14051     std::string rt = GPR(copy(rt_value));
14052     std::string rs = GPR(copy(rs_value));
14053     std::string sa = IMMEDIATE(copy(sa_value));
14054
14055     return img::format("SHLL_S.PH %s, %s, %s", rt, rs, sa);
14056 }
14057
14058
14059 /*
14060  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical word with saturation
14061  *
14062  *   3         2         1
14063  *  10987654321098765432109876543210
14064  *  001000               x1111110101
14065  *     rt -----
14066  *          rs -----
14067  *               sa -----
14068  */
14069 std::string NMD::SHLL_S_W(uint64 instruction)
14070 {
14071     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14072     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14073     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
14074
14075     std::string rt = GPR(copy(rt_value));
14076     std::string rs = GPR(copy(rs_value));
14077     std::string sa = IMMEDIATE(copy(sa_value));
14078
14079     return img::format("SHLL_S.W %s, %s, %s", rt, rs, sa);
14080 }
14081
14082
14083 /*
14084  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
14085  *   halfwords
14086  *
14087  *   3         2         1
14088  *  10987654321098765432109876543210
14089  *  001000               01110001101
14090  *     rt -----
14091  *          rs -----
14092  *               rd -----
14093  */
14094 std::string NMD::SHLLV_PH(uint64 instruction)
14095 {
14096     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14098     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14099
14100     std::string rd = GPR(copy(rd_value));
14101     std::string rt = GPR(copy(rt_value));
14102     std::string rs = GPR(copy(rs_value));
14103
14104     return img::format("SHLLV.PH %s, %s, %s", rd, rt, rs);
14105 }
14106
14107
14108 /*
14109  * [DSP] SHLLV_S.QB rd, rt, rs - Shift left logical variable vector quad bytes
14110  *
14111  *   3         2         1
14112  *  10987654321098765432109876543210
14113  *  001000               x1110010101
14114  *     rt -----
14115  *          rs -----
14116  *               rd -----
14117  */
14118 std::string NMD::SHLLV_QB(uint64 instruction)
14119 {
14120     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14121     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14122     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14123
14124     std::string rd = GPR(copy(rd_value));
14125     std::string rt = GPR(copy(rt_value));
14126     std::string rs = GPR(copy(rs_value));
14127
14128     return img::format("SHLLV.QB %s, %s, %s", rd, rt, rs);
14129 }
14130
14131
14132 /*
14133  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
14134  *   halfwords with saturation
14135  *
14136  *   3         2         1
14137  *  10987654321098765432109876543210
14138  *  001000               11110001101
14139  *     rt -----
14140  *          rs -----
14141  *               rd -----
14142  */
14143 std::string NMD::SHLLV_S_PH(uint64 instruction)
14144 {
14145     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14146     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14147     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14148
14149     std::string rd = GPR(copy(rd_value));
14150     std::string rt = GPR(copy(rt_value));
14151     std::string rs = GPR(copy(rs_value));
14152
14153     return img::format("SHLLV_S.PH %s, %s, %s", rd, rt, rs);
14154 }
14155
14156
14157 /*
14158  * [DSP] SHLLV_S.W rd, rt, rs - Shift left logical variable vector word
14159  *
14160  *   3         2         1
14161  *  10987654321098765432109876543210
14162  *  001000               x1111010101
14163  *     rt -----
14164  *          rs -----
14165  *               rd -----
14166  */
14167 std::string NMD::SHLLV_S_W(uint64 instruction)
14168 {
14169     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14170     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14171     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14172
14173     std::string rd = GPR(copy(rd_value));
14174     std::string rt = GPR(copy(rt_value));
14175     std::string rs = GPR(copy(rs_value));
14176
14177     return img::format("SHLLV_S.W %s, %s, %s", rd, rt, rs);
14178 }
14179
14180
14181 /*
14182  *
14183  *
14184  *   3         2         1
14185  *  10987654321098765432109876543210
14186  *  001000               01001001101
14187  *     rt -----
14188  *          rs -----
14189  *               rd -----
14190  */
14191 std::string NMD::SHRA_PH(uint64 instruction)
14192 {
14193     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14194     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14195     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14196
14197     std::string rt = GPR(copy(rt_value));
14198     std::string rs = GPR(copy(rs_value));
14199     std::string sa = IMMEDIATE(copy(sa_value));
14200
14201     return img::format("SHRA.PH %s, %s, %s", rt, rs, sa);
14202 }
14203
14204
14205 /*
14206  *
14207  *
14208  *   3         2         1
14209  *  10987654321098765432109876543210
14210  *  001000               01001001101
14211  *     rt -----
14212  *          rs -----
14213  *               rd -----
14214  */
14215 std::string NMD::SHRA_QB(uint64 instruction)
14216 {
14217     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14218     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14219     uint64 sa_value = extract_sa_15_14_13(instruction);
14220
14221     std::string rt = GPR(copy(rt_value));
14222     std::string rs = GPR(copy(rs_value));
14223     std::string sa = IMMEDIATE(copy(sa_value));
14224
14225     return img::format("SHRA.QB %s, %s, %s", rt, rs, sa);
14226 }
14227
14228
14229 /*
14230  *
14231  *
14232  *   3         2         1
14233  *  10987654321098765432109876543210
14234  *  001000               01001001101
14235  *     rt -----
14236  *          rs -----
14237  *               rd -----
14238  */
14239 std::string NMD::SHRA_R_PH(uint64 instruction)
14240 {
14241     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14242     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14243     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14244
14245     std::string rt = GPR(copy(rt_value));
14246     std::string rs = GPR(copy(rs_value));
14247     std::string sa = IMMEDIATE(copy(sa_value));
14248
14249     return img::format("SHRA_R.PH %s, %s, %s", rt, rs, sa);
14250 }
14251
14252
14253 /*
14254  *
14255  *
14256  *   3         2         1
14257  *  10987654321098765432109876543210
14258  *  001000               01001001101
14259  *     rt -----
14260  *          rs -----
14261  *               rd -----
14262  */
14263 std::string NMD::SHRA_R_QB(uint64 instruction)
14264 {
14265     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14266     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14267     uint64 sa_value = extract_sa_15_14_13(instruction);
14268
14269     std::string rt = GPR(copy(rt_value));
14270     std::string rs = GPR(copy(rs_value));
14271     std::string sa = IMMEDIATE(copy(sa_value));
14272
14273     return img::format("SHRA_R.QB %s, %s, %s", rt, rs, sa);
14274 }
14275
14276
14277 /*
14278  *
14279  *
14280  *   3         2         1
14281  *  10987654321098765432109876543210
14282  *  001000               01001001101
14283  *     rt -----
14284  *          rs -----
14285  *               rd -----
14286  */
14287 std::string NMD::SHRA_R_W(uint64 instruction)
14288 {
14289     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14290     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14291     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
14292
14293     std::string rt = GPR(copy(rt_value));
14294     std::string rs = GPR(copy(rs_value));
14295     std::string sa = IMMEDIATE(copy(sa_value));
14296
14297     return img::format("SHRA_R.W %s, %s, %s", rt, rs, sa);
14298 }
14299
14300
14301 /*
14302  *
14303  *
14304  *   3         2         1
14305  *  10987654321098765432109876543210
14306  *  001000               01001001101
14307  *     rt -----
14308  *          rs -----
14309  *               rd -----
14310  */
14311 std::string NMD::SHRAV_PH(uint64 instruction)
14312 {
14313     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14314     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14315     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14316
14317     std::string rd = GPR(copy(rd_value));
14318     std::string rt = GPR(copy(rt_value));
14319     std::string rs = GPR(copy(rs_value));
14320
14321     return img::format("SHRAV.PH %s, %s, %s", rd, rt, rs);
14322 }
14323
14324
14325 /*
14326  *
14327  *
14328  *   3         2         1
14329  *  10987654321098765432109876543210
14330  *  001000               01001001101
14331  *     rt -----
14332  *          rs -----
14333  *               rd -----
14334  */
14335 std::string NMD::SHRAV_QB(uint64 instruction)
14336 {
14337     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14338     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14339     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14340
14341     std::string rd = GPR(copy(rd_value));
14342     std::string rt = GPR(copy(rt_value));
14343     std::string rs = GPR(copy(rs_value));
14344
14345     return img::format("SHRAV.QB %s, %s, %s", rd, rt, rs);
14346 }
14347
14348
14349 /*
14350  *
14351  *
14352  *   3         2         1
14353  *  10987654321098765432109876543210
14354  *  001000               01001001101
14355  *     rt -----
14356  *          rs -----
14357  *               rd -----
14358  */
14359 std::string NMD::SHRAV_R_PH(uint64 instruction)
14360 {
14361     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14362     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14363     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14364
14365     std::string rd = GPR(copy(rd_value));
14366     std::string rt = GPR(copy(rt_value));
14367     std::string rs = GPR(copy(rs_value));
14368
14369     return img::format("SHRAV_R.PH %s, %s, %s", rd, rt, rs);
14370 }
14371
14372
14373 /*
14374  *
14375  *
14376  *   3         2         1
14377  *  10987654321098765432109876543210
14378  *  001000               01001001101
14379  *     rt -----
14380  *          rs -----
14381  *               rd -----
14382  */
14383 std::string NMD::SHRAV_R_QB(uint64 instruction)
14384 {
14385     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14386     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14387     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14388
14389     std::string rd = GPR(copy(rd_value));
14390     std::string rt = GPR(copy(rt_value));
14391     std::string rs = GPR(copy(rs_value));
14392
14393     return img::format("SHRAV_R.QB %s, %s, %s", rd, rt, rs);
14394 }
14395
14396
14397 /*
14398  *
14399  *
14400  *   3         2         1
14401  *  10987654321098765432109876543210
14402  *  001000               01001001101
14403  *     rt -----
14404  *          rs -----
14405  *               rd -----
14406  */
14407 std::string NMD::SHRAV_R_W(uint64 instruction)
14408 {
14409     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14410     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14411     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14412
14413     std::string rd = GPR(copy(rd_value));
14414     std::string rt = GPR(copy(rt_value));
14415     std::string rs = GPR(copy(rs_value));
14416
14417     return img::format("SHRAV_R.W %s, %s, %s", rd, rt, rs);
14418 }
14419
14420
14421 /*
14422  * [DSP] SHRL.PH rt, rs, sa - Shift right logical two halfwords
14423  *
14424  *   3         2         1
14425  *  10987654321098765432109876543210
14426  *  001000              001111111111
14427  *     rt -----
14428  *          rs -----
14429  *               sa ----
14430  */
14431 std::string NMD::SHRL_PH(uint64 instruction)
14432 {
14433     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14434     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14435     uint64 sa_value = extract_sa_15_14_13_12(instruction);
14436
14437     std::string rt = GPR(copy(rt_value));
14438     std::string rs = GPR(copy(rs_value));
14439     std::string sa = IMMEDIATE(copy(sa_value));
14440
14441     return img::format("SHRL.PH %s, %s, %s", rt, rs, sa);
14442 }
14443
14444
14445 /*
14446  * [DSP] SHRL.QB rt, rs, sa - Shift right logical vector quad bytes
14447  *
14448  *   3         2         1
14449  *  10987654321098765432109876543210
14450  *  001000             1100001111111
14451  *     rt -----
14452  *          rs -----
14453  *               sa ---
14454  */
14455 std::string NMD::SHRL_QB(uint64 instruction)
14456 {
14457     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14458     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14459     uint64 sa_value = extract_sa_15_14_13(instruction);
14460
14461     std::string rt = GPR(copy(rt_value));
14462     std::string rs = GPR(copy(rs_value));
14463     std::string sa = IMMEDIATE(copy(sa_value));
14464
14465     return img::format("SHRL.QB %s, %s, %s", rt, rs, sa);
14466 }
14467
14468
14469 /*
14470  * [DSP] SHLLV.PH rd, rt, rs - Shift right logical variable vector pair of
14471  *   halfwords
14472  *
14473  *   3         2         1
14474  *  10987654321098765432109876543210
14475  *  001000               x1100010101
14476  *     rt -----
14477  *          rs -----
14478  *               rd -----
14479  */
14480 std::string NMD::SHRLV_PH(uint64 instruction)
14481 {
14482     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14483     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14484     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14485
14486     std::string rd = GPR(copy(rd_value));
14487     std::string rt = GPR(copy(rt_value));
14488     std::string rs = GPR(copy(rs_value));
14489
14490     return img::format("SHRLV.PH %s, %s, %s", rd, rt, rs);
14491 }
14492
14493
14494 /*
14495  * [DSP] SHLLV.QB rd, rt, rs - Shift right logical variable vector quad bytes
14496  *
14497  *   3         2         1
14498  *  10987654321098765432109876543210
14499  *  001000               x1101010101
14500  *     rt -----
14501  *          rs -----
14502  *               rd -----
14503  */
14504 std::string NMD::SHRLV_QB(uint64 instruction)
14505 {
14506     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14507     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14508     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14509
14510     std::string rd = GPR(copy(rd_value));
14511     std::string rt = GPR(copy(rt_value));
14512     std::string rs = GPR(copy(rs_value));
14513
14514     return img::format("SHRLV.QB %s, %s, %s", rd, rt, rs);
14515 }
14516
14517
14518 /*
14519  *
14520  *
14521  *   3         2         1
14522  *  10987654321098765432109876543210
14523  *  001000               01001001101
14524  *     rt -----
14525  *          rs -----
14526  *               rd -----
14527  */
14528 std::string NMD::SHX(uint64 instruction)
14529 {
14530     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14531     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14532     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14533
14534     std::string rd = GPR(copy(rd_value));
14535     std::string rs = GPR(copy(rs_value));
14536     std::string rt = GPR(copy(rt_value));
14537
14538     return img::format("SHX %s, %s(%s)", rd, rs, rt);
14539 }
14540
14541
14542 /*
14543  *
14544  *
14545  *   3         2         1
14546  *  10987654321098765432109876543210
14547  *  001000               01001001101
14548  *     rt -----
14549  *          rs -----
14550  *               rd -----
14551  */
14552 std::string NMD::SHXS(uint64 instruction)
14553 {
14554     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14555     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14556     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14557
14558     std::string rd = GPR(copy(rd_value));
14559     std::string rs = GPR(copy(rs_value));
14560     std::string rt = GPR(copy(rt_value));
14561
14562     return img::format("SHXS %s, %s(%s)", rd, rs, rt);
14563 }
14564
14565
14566 /*
14567  *
14568  *
14569  *   3         2         1
14570  *  10987654321098765432109876543210
14571  *  001000               01001001101
14572  *     rt -----
14573  *          rs -----
14574  *               rd -----
14575  */
14576 std::string NMD::SIGRIE(uint64 instruction)
14577 {
14578     uint64 code_value = extract_code_18_to_0(instruction);
14579
14580     std::string code = IMMEDIATE(copy(code_value));
14581
14582     return img::format("SIGRIE %s", code);
14583 }
14584
14585
14586 /*
14587  *
14588  *
14589  *   3         2         1
14590  *  10987654321098765432109876543210
14591  *  001000               01001001101
14592  *     rt -----
14593  *          rs -----
14594  *               rd -----
14595  */
14596 std::string NMD::SLL_16_(uint64 instruction)
14597 {
14598     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14599     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14600     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14601
14602     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
14603     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
14604     std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));
14605
14606     return img::format("SLL %s, %s, %s", rt3, rs3, shift3);
14607 }
14608
14609
14610 /*
14611  *
14612  *
14613  *   3         2         1
14614  *  10987654321098765432109876543210
14615  *  001000               01001001101
14616  *     rt -----
14617  *          rs -----
14618  *               rd -----
14619  */
14620 std::string NMD::SLL_32_(uint64 instruction)
14621 {
14622     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14623     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14624     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14625
14626     std::string rt = GPR(copy(rt_value));
14627     std::string rs = GPR(copy(rs_value));
14628     std::string shift = IMMEDIATE(copy(shift_value));
14629
14630     return img::format("SLL %s, %s, %s", rt, rs, shift);
14631 }
14632
14633
14634 /*
14635  *
14636  *
14637  *   3         2         1
14638  *  10987654321098765432109876543210
14639  *  001000               01001001101
14640  *     rt -----
14641  *          rs -----
14642  *               rd -----
14643  */
14644 std::string NMD::SLLV(uint64 instruction)
14645 {
14646     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14647     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14648     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14649
14650     std::string rd = GPR(copy(rd_value));
14651     std::string rs = GPR(copy(rs_value));
14652     std::string rt = GPR(copy(rt_value));
14653
14654     return img::format("SLLV %s, %s, %s", rd, rs, rt);
14655 }
14656
14657
14658 /*
14659  *
14660  *
14661  *   3         2         1
14662  *  10987654321098765432109876543210
14663  *  001000               01001001101
14664  *     rt -----
14665  *          rs -----
14666  *               rd -----
14667  */
14668 std::string NMD::SLT(uint64 instruction)
14669 {
14670     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14671     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14672     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14673
14674     std::string rd = GPR(copy(rd_value));
14675     std::string rs = GPR(copy(rs_value));
14676     std::string rt = GPR(copy(rt_value));
14677
14678     return img::format("SLT %s, %s, %s", rd, rs, rt);
14679 }
14680
14681
14682 /*
14683  *
14684  *
14685  *   3         2         1
14686  *  10987654321098765432109876543210
14687  *  001000               01001001101
14688  *     rt -----
14689  *          rs -----
14690  *               rd -----
14691  */
14692 std::string NMD::SLTI(uint64 instruction)
14693 {
14694     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14695     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14696     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14697
14698     std::string rt = GPR(copy(rt_value));
14699     std::string rs = GPR(copy(rs_value));
14700     std::string u = IMMEDIATE(copy(u_value));
14701
14702     return img::format("SLTI %s, %s, %s", rt, rs, u);
14703 }
14704
14705
14706 /*
14707  *
14708  *
14709  *   3         2         1
14710  *  10987654321098765432109876543210
14711  *  001000               01001001101
14712  *     rt -----
14713  *          rs -----
14714  *               rd -----
14715  */
14716 std::string NMD::SLTIU(uint64 instruction)
14717 {
14718     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14719     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14720     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14721
14722     std::string rt = GPR(copy(rt_value));
14723     std::string rs = GPR(copy(rs_value));
14724     std::string u = IMMEDIATE(copy(u_value));
14725
14726     return img::format("SLTIU %s, %s, %s", rt, rs, u);
14727 }
14728
14729
14730 /*
14731  *
14732  *
14733  *   3         2         1
14734  *  10987654321098765432109876543210
14735  *  001000               01001001101
14736  *     rt -----
14737  *          rs -----
14738  *               rd -----
14739  */
14740 std::string NMD::SLTU(uint64 instruction)
14741 {
14742     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14743     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14744     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14745
14746     std::string rd = GPR(copy(rd_value));
14747     std::string rs = GPR(copy(rs_value));
14748     std::string rt = GPR(copy(rt_value));
14749
14750     return img::format("SLTU %s, %s, %s", rd, rs, rt);
14751 }
14752
14753
14754 /*
14755  *
14756  *
14757  *   3         2         1
14758  *  10987654321098765432109876543210
14759  *  001000               01001001101
14760  *     rt -----
14761  *          rs -----
14762  *               rd -----
14763  */
14764 std::string NMD::SOV(uint64 instruction)
14765 {
14766     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14767     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14768     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14769
14770     std::string rd = GPR(copy(rd_value));
14771     std::string rs = GPR(copy(rs_value));
14772     std::string rt = GPR(copy(rt_value));
14773
14774     return img::format("SOV %s, %s, %s", rd, rs, rt);
14775 }
14776
14777
14778 /*
14779  *
14780  *
14781  *   3         2         1
14782  *  10987654321098765432109876543210
14783  *  001000               01001001101
14784  *     rt -----
14785  *          rs -----
14786  *               rd -----
14787  */
14788 std::string NMD::SPECIAL2(uint64 instruction)
14789 {
14790     uint64 op_value = extract_op_25_to_3(instruction);
14791
14792     std::string op = IMMEDIATE(copy(op_value));
14793
14794     return img::format("SPECIAL2 %s", op);
14795 }
14796
14797
14798 /*
14799  *
14800  *
14801  *   3         2         1
14802  *  10987654321098765432109876543210
14803  *  001000               01001001101
14804  *     rt -----
14805  *          rs -----
14806  *               rd -----
14807  */
14808 std::string NMD::SQRT_D(uint64 instruction)
14809 {
14810     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14811     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14812
14813     std::string ft = FPR(copy(ft_value));
14814     std::string fs = FPR(copy(fs_value));
14815
14816     return img::format("SQRT.D %s, %s", ft, fs);
14817 }
14818
14819
14820 /*
14821  *
14822  *
14823  *   3         2         1
14824  *  10987654321098765432109876543210
14825  *  001000               01001001101
14826  *     rt -----
14827  *          rs -----
14828  *               rd -----
14829  */
14830 std::string NMD::SQRT_S(uint64 instruction)
14831 {
14832     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14833     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14834
14835     std::string ft = FPR(copy(ft_value));
14836     std::string fs = FPR(copy(fs_value));
14837
14838     return img::format("SQRT.S %s, %s", ft, fs);
14839 }
14840
14841
14842 /*
14843  * SRA rd, rt, sa - Shift Word Right Arithmetic
14844  *
14845  *   3         2         1
14846  *  10987654321098765432109876543210
14847  *  00000000000               000011
14848  *          rt -----
14849  *               rd -----
14850  *                    sa -----
14851  */
14852 std::string NMD::SRA(uint64 instruction)
14853 {
14854     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14855     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14856     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14857
14858     std::string rt = GPR(copy(rt_value));
14859     std::string rs = GPR(copy(rs_value));
14860     std::string shift = IMMEDIATE(copy(shift_value));
14861
14862     return img::format("SRA %s, %s, %s", rt, rs, shift);
14863 }
14864
14865
14866 /*
14867  * SRAV rd, rt, rs - Shift Word Right Arithmetic Variable
14868  *
14869  *   3         2         1
14870  *  10987654321098765432109876543210
14871  *  001000               00000000111
14872  *     rs -----
14873  *          rt -----
14874  *               rd -----
14875  */
14876 std::string NMD::SRAV(uint64 instruction)
14877 {
14878     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14879     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14880     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14881
14882     std::string rd = GPR(copy(rd_value));
14883     std::string rs = GPR(copy(rs_value));
14884     std::string rt = GPR(copy(rt_value));
14885
14886     return img::format("SRAV %s, %s, %s", rd, rs, rt);
14887 }
14888
14889
14890 /*
14891  *
14892  *
14893  *   3         2         1
14894  *  10987654321098765432109876543210
14895  *  001000               00000000111
14896  *     rs -----
14897  *          rt -----
14898  *               rd -----
14899  */
14900 std::string NMD::SRL_16_(uint64 instruction)
14901 {
14902     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14903     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14904     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14905
14906     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
14907     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
14908     std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value));
14909
14910     return img::format("SRL %s, %s, %s", rt3, rs3, shift3);
14911 }
14912
14913
14914 /*
14915  *
14916  *
14917  *   3         2         1
14918  *  10987654321098765432109876543210
14919  *  001000               01001001101
14920  *     rt -----
14921  *          rs -----
14922  *               rd -----
14923  */
14924 std::string NMD::SRL_32_(uint64 instruction)
14925 {
14926     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14927     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14928     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14929
14930     std::string rt = GPR(copy(rt_value));
14931     std::string rs = GPR(copy(rs_value));
14932     std::string shift = IMMEDIATE(copy(shift_value));
14933
14934     return img::format("SRL %s, %s, %s", rt, rs, shift);
14935 }
14936
14937
14938 /*
14939  *
14940  *
14941  *   3         2         1
14942  *  10987654321098765432109876543210
14943  *  001000               01001001101
14944  *     rt -----
14945  *          rs -----
14946  *               rd -----
14947  */
14948 std::string NMD::SRLV(uint64 instruction)
14949 {
14950     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14951     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14952     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14953
14954     std::string rd = GPR(copy(rd_value));
14955     std::string rs = GPR(copy(rs_value));
14956     std::string rt = GPR(copy(rt_value));
14957
14958     return img::format("SRLV %s, %s, %s", rd, rs, rt);
14959 }
14960
14961
14962 /*
14963  *
14964  *
14965  *   3         2         1
14966  *  10987654321098765432109876543210
14967  *  001000               01001001101
14968  *     rt -----
14969  *          rs -----
14970  *               rd -----
14971  */
14972 std::string NMD::SUB(uint64 instruction)
14973 {
14974     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14975     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14976     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14977
14978     std::string rd = GPR(copy(rd_value));
14979     std::string rs = GPR(copy(rs_value));
14980     std::string rt = GPR(copy(rt_value));
14981
14982     return img::format("SUB %s, %s, %s", rd, rs, rt);
14983 }
14984
14985
14986 /*
14987  *
14988  *
14989  *   3         2         1
14990  *  10987654321098765432109876543210
14991  *  001000               01001001101
14992  *     rt -----
14993  *          rs -----
14994  *               rd -----
14995  */
14996 std::string NMD::SUB_D(uint64 instruction)
14997 {
14998     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14999     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15000     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
15001
15002     std::string fd = FPR(copy(fd_value));
15003     std::string fs = FPR(copy(fs_value));
15004     std::string ft = FPR(copy(ft_value));
15005
15006     return img::format("SUB.D %s, %s, %s", fd, fs, ft);
15007 }
15008
15009
15010 /*
15011  *
15012  *
15013  *   3         2         1
15014  *  10987654321098765432109876543210
15015  *  001000               01001001101
15016  *     rt -----
15017  *          rs -----
15018  *               rd -----
15019  */
15020 std::string NMD::SUB_S(uint64 instruction)
15021 {
15022     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15023     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15024     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
15025
15026     std::string fd = FPR(copy(fd_value));
15027     std::string fs = FPR(copy(fs_value));
15028     std::string ft = FPR(copy(ft_value));
15029
15030     return img::format("SUB.S %s, %s, %s", fd, fs, ft);
15031 }
15032
15033
15034 /*
15035  *
15036  *
15037  *   3         2         1
15038  *  10987654321098765432109876543210
15039  *  001000               01001001101
15040  *     rt -----
15041  *          rs -----
15042  *               rd -----
15043  */
15044 std::string NMD::SUBQ_PH(uint64 instruction)
15045 {
15046     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15047     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15048     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15049
15050     std::string rd = GPR(copy(rd_value));
15051     std::string rs = GPR(copy(rs_value));
15052     std::string rt = GPR(copy(rt_value));
15053
15054     return img::format("SUBQ.PH %s, %s, %s", rd, rs, rt);
15055 }
15056
15057
15058 /*
15059  * [DSP] SUBQ.S.PH rd, rt, rs - Subtract fractional halfword vectors and shift
15060  *   right to halve results
15061  *
15062  *   3         2         1
15063  *  10987654321098765432109876543210
15064  *  001000               01001001101
15065  *     rt -----
15066  *          rs -----
15067  *               rd -----
15068  */
15069 std::string NMD::SUBQ_S_PH(uint64 instruction)
15070 {
15071     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15072     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15073     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15074
15075     std::string rd = GPR(copy(rd_value));
15076     std::string rs = GPR(copy(rs_value));
15077     std::string rt = GPR(copy(rt_value));
15078
15079     return img::format("SUBQ_S.PH %s, %s, %s", rd, rs, rt);
15080 }
15081
15082
15083 /*
15084  * [DSP] SUBQ.S.W rd, rt, rs - Subtract fractional halfword vectors and shift
15085  *   right to halve results
15086  *
15087  *   3         2         1
15088  *  10987654321098765432109876543210
15089  *  001000               01001001101
15090  *     rt -----
15091  *          rs -----
15092  *               rd -----
15093  */
15094 std::string NMD::SUBQ_S_W(uint64 instruction)
15095 {
15096     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15098     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15099
15100     std::string rd = GPR(copy(rd_value));
15101     std::string rs = GPR(copy(rs_value));
15102     std::string rt = GPR(copy(rt_value));
15103
15104     return img::format("SUBQ_S.W %s, %s, %s", rd, rs, rt);
15105 }
15106
15107
15108 /*
15109  * [DSP] SUBQH.PH rd, rt, rs - Subtract fractional halfword vectors and shift
15110  *   right to halve results
15111  *
15112  *   3         2         1
15113  *  10987654321098765432109876543210
15114  *  001000               01001001101
15115  *     rt -----
15116  *          rs -----
15117  *               rd -----
15118  */
15119 std::string NMD::SUBQH_PH(uint64 instruction)
15120 {
15121     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15122     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15123     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15124
15125     std::string rd = GPR(copy(rd_value));
15126     std::string rs = GPR(copy(rs_value));
15127     std::string rt = GPR(copy(rt_value));
15128
15129     return img::format("SUBQH.PH %s, %s, %s", rd, rs, rt);
15130 }
15131
15132
15133 /*
15134  * [DSP] SUBQH_R.PH rd, rt, rs - Subtract fractional halfword vectors and shift
15135  *   right to halve results
15136  *
15137  *   3         2         1
15138  *  10987654321098765432109876543210
15139  *  001000               01001001101
15140  *     rt -----
15141  *          rs -----
15142  *               rd -----
15143  */
15144 std::string NMD::SUBQH_R_PH(uint64 instruction)
15145 {
15146     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15147     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15148     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15149
15150     std::string rd = GPR(copy(rd_value));
15151     std::string rs = GPR(copy(rs_value));
15152     std::string rt = GPR(copy(rt_value));
15153
15154     return img::format("SUBQH_R.PH %s, %s, %s", rd, rs, rt);
15155 }
15156
15157
15158 /*
15159  * [DSP] SUBQH_R.W rd, rt, rs - Subtract fractional halfword vectors and shift
15160  *   right to halve results with rounding
15161  *
15162  *   3         2         1
15163  *  10987654321098765432109876543210
15164  *  001000               11001001101
15165  *     rt -----
15166  *          rs -----
15167  *               rd -----
15168  */
15169 std::string NMD::SUBQH_R_W(uint64 instruction)
15170 {
15171     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15172     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15173     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15174
15175     std::string rd = GPR(copy(rd_value));
15176     std::string rs = GPR(copy(rs_value));
15177     std::string rt = GPR(copy(rt_value));
15178
15179     return img::format("SUBQH_R.W %s, %s, %s", rd, rs, rt);
15180 }
15181
15182
15183 /*
15184  * [DSP] SUBQH.W rd, rs, rt - Subtract fractional words and shift right to
15185  *   halve results
15186  *
15187  *   3         2         1
15188  *  10987654321098765432109876543210
15189  *  001000               01010001101
15190  *     rt -----
15191  *          rs -----
15192  *               rd -----
15193  */
15194 std::string NMD::SUBQH_W(uint64 instruction)
15195 {
15196     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15197     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15198     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15199
15200     std::string rd = GPR(copy(rd_value));
15201     std::string rs = GPR(copy(rs_value));
15202     std::string rt = GPR(copy(rt_value));
15203
15204     return img::format("SUBQH.W %s, %s, %s", rd, rs, rt);
15205 }
15206
15207
15208 /*
15209  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15210  *
15211  *   3         2         1
15212  *  10987654321098765432109876543210
15213  *  001000               00010001101
15214  *     rt -----
15215  *          rs -----
15216  *               rd -----
15217  */
15218 std::string NMD::SUBU_16_(uint64 instruction)
15219 {
15220     uint64 rt3_value = extract_rt3_9_8_7(instruction);
15221     uint64 rs3_value = extract_rs3_6_5_4(instruction);
15222     uint64 rd3_value = extract_rd3_3_2_1(instruction);
15223
15224     std::string rd3 = GPR(decode_gpr_gpr3(rd3_value));
15225     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
15226     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
15227
15228     return img::format("SUBU %s, %s, %s", rd3, rs3, rt3);
15229 }
15230
15231
15232 /*
15233  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15234  *
15235  *   3         2         1
15236  *  10987654321098765432109876543210
15237  *  001000               00010001101
15238  *     rt -----
15239  *          rs -----
15240  *               rd -----
15241  */
15242 std::string NMD::SUBU_32_(uint64 instruction)
15243 {
15244     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15245     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15246     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15247
15248     std::string rd = GPR(copy(rd_value));
15249     std::string rs = GPR(copy(rs_value));
15250     std::string rt = GPR(copy(rt_value));
15251
15252     return img::format("SUBU %s, %s, %s", rd, rs, rt);
15253 }
15254
15255
15256 /*
15257  * [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
15258  *
15259  *   3         2         1
15260  *  10987654321098765432109876543210
15261  *  001000               01100001101
15262  *     rt -----
15263  *          rs -----
15264  *               rd -----
15265  */
15266 std::string NMD::SUBU_PH(uint64 instruction)
15267 {
15268     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15269     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15270     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15271
15272     std::string rd = GPR(copy(rd_value));
15273     std::string rs = GPR(copy(rs_value));
15274     std::string rt = GPR(copy(rt_value));
15275
15276     return img::format("SUBU.PH %s, %s, %s", rd, rs, rt);
15277 }
15278
15279
15280 /*
15281  * [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
15282  *
15283  *   3         2         1
15284  *  10987654321098765432109876543210
15285  *  001000               01011001101
15286  *     rt -----
15287  *          rs -----
15288  *               rd -----
15289  */
15290 std::string NMD::SUBU_QB(uint64 instruction)
15291 {
15292     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15293     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15294     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15295
15296     std::string rd = GPR(copy(rd_value));
15297     std::string rs = GPR(copy(rs_value));
15298     std::string rt = GPR(copy(rt_value));
15299
15300     return img::format("SUBU.QB %s, %s, %s", rd, rs, rt);
15301 }
15302
15303
15304 /*
15305  * [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
15306  *   8-bit saturation
15307  *
15308  *   3         2         1
15309  *  10987654321098765432109876543210
15310  *  001000               11100001101
15311  *     rt -----
15312  *          rs -----
15313  *               rd -----
15314  */
15315 std::string NMD::SUBU_S_PH(uint64 instruction)
15316 {
15317     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15318     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15319     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15320
15321     std::string rd = GPR(copy(rd_value));
15322     std::string rs = GPR(copy(rs_value));
15323     std::string rt = GPR(copy(rt_value));
15324
15325     return img::format("SUBU_S.PH %s, %s, %s", rd, rs, rt);
15326 }
15327
15328
15329 /*
15330  * [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
15331  *   8-bit saturation
15332  *
15333  *   3         2         1
15334  *  10987654321098765432109876543210
15335  *  001000               11011001101
15336  *     rt -----
15337  *          rs -----
15338  *               rd -----
15339  */
15340 std::string NMD::SUBU_S_QB(uint64 instruction)
15341 {
15342     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15343     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15344     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15345
15346     std::string rd = GPR(copy(rd_value));
15347     std::string rs = GPR(copy(rs_value));
15348     std::string rt = GPR(copy(rt_value));
15349
15350     return img::format("SUBU_S.QB %s, %s, %s", rd, rs, rt);
15351 }
15352
15353
15354 /*
15355  * [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
15356  *   to halve results
15357  *
15358  *   3         2         1
15359  *  10987654321098765432109876543210
15360  *  001000               01101001101
15361  *     rt -----
15362  *          rs -----
15363  *               rd -----
15364  */
15365 std::string NMD::SUBUH_QB(uint64 instruction)
15366 {
15367     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15368     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15369     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15370
15371     std::string rd = GPR(copy(rd_value));
15372     std::string rs = GPR(copy(rs_value));
15373     std::string rt = GPR(copy(rt_value));
15374
15375     return img::format("SUBUH.QB %s, %s, %s", rd, rs, rt);
15376 }
15377
15378
15379 /*
15380  * [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
15381  *   to halve results with rounding
15382  *
15383  *   3         2         1
15384  *  10987654321098765432109876543210
15385  *  001000               11101001101
15386  *     rt -----
15387  *          rs -----
15388  *               rd -----
15389  */
15390 std::string NMD::SUBUH_R_QB(uint64 instruction)
15391 {
15392     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15393     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15394     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15395
15396     std::string rd = GPR(copy(rd_value));
15397     std::string rs = GPR(copy(rs_value));
15398     std::string rt = GPR(copy(rt_value));
15399
15400     return img::format("SUBUH_R.QB %s, %s, %s", rd, rs, rt);
15401 }
15402
15403
15404 /*
15405  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15406  *
15407  *   3         2         1
15408  *  10987654321098765432109876543210
15409  *  001000               00010001101
15410  *     rt -----
15411  *          rs -----
15412  *               rd -----
15413  */
15414 std::string NMD::SW_16_(uint64 instruction)
15415 {
15416     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
15417     uint64 rs3_value = extract_rs3_6_5_4(instruction);
15418     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
15419
15420     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
15421     std::string u = IMMEDIATE(copy(u_value));
15422     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
15423
15424     return img::format("SW %s, %s(%s)", rtz3, u, rs3);
15425 }
15426
15427
15428 /*
15429  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15430  *
15431  *   3         2         1
15432  *  10987654321098765432109876543210
15433  *  001000               00010001101
15434  *     rt -----
15435  *          rs -----
15436  *               rd -----
15437  */
15438 std::string NMD::SW_4X4_(uint64 instruction)
15439 {
15440     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
15441     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
15442     uint64 u_value = extract_u_3_8__s2(instruction);
15443
15444     std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value));
15445     std::string u = IMMEDIATE(copy(u_value));
15446     std::string rs4 = GPR(decode_gpr_gpr4(rs4_value));
15447
15448     return img::format("SW %s, %s(%s)", rtz4, u, rs4);
15449 }
15450
15451
15452 /*
15453  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15454  *
15455  *   3         2         1
15456  *  10987654321098765432109876543210
15457  *  001000               00010001101
15458  *     rt -----
15459  *          rs -----
15460  *               rd -----
15461  */
15462 std::string NMD::SW_GP16_(uint64 instruction)
15463 {
15464     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
15465     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
15466
15467     std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value));
15468     std::string u = IMMEDIATE(copy(u_value));
15469
15470     return img::format("SW %s, %s($%d)", rtz3, u, 28);
15471 }
15472
15473
15474 /*
15475  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15476  *
15477  *   3         2         1
15478  *  10987654321098765432109876543210
15479  *  001000               00010001101
15480  *     rt -----
15481  *          rs -----
15482  *               rd -----
15483  */
15484 std::string NMD::SW_GP_(uint64 instruction)
15485 {
15486     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15487     uint64 u_value = extract_u_20_to_2__s2(instruction);
15488
15489     std::string rt = GPR(copy(rt_value));
15490     std::string u = IMMEDIATE(copy(u_value));
15491
15492     return img::format("SW %s, %s($%d)", rt, u, 28);
15493 }
15494
15495
15496 /*
15497  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15498  *
15499  *   3         2         1
15500  *  10987654321098765432109876543210
15501  *  001000               00010001101
15502  *     rt -----
15503  *          rs -----
15504  *               rd -----
15505  */
15506 std::string NMD::SW_S9_(uint64 instruction)
15507 {
15508     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15509     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15510     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15511
15512     std::string rt = GPR(copy(rt_value));
15513     std::string s = IMMEDIATE(copy(s_value));
15514     std::string rs = GPR(copy(rs_value));
15515
15516     return img::format("SW %s, %s(%s)", rt, s, rs);
15517 }
15518
15519
15520 /*
15521  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15522  *
15523  *   3         2         1
15524  *  10987654321098765432109876543210
15525  *  001000               00010001101
15526  *     rt -----
15527  *          rs -----
15528  *               rd -----
15529  */
15530 std::string NMD::SW_SP_(uint64 instruction)
15531 {
15532     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
15533     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
15534
15535     std::string rt = GPR(copy(rt_value));
15536     std::string u = IMMEDIATE(copy(u_value));
15537
15538     return img::format("SW %s, %s($%d)", rt, u, 29);
15539 }
15540
15541
15542 /*
15543  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15544  *
15545  *   3         2         1
15546  *  10987654321098765432109876543210
15547  *  001000               00010001101
15548  *     rt -----
15549  *          rs -----
15550  *               rd -----
15551  */
15552 std::string NMD::SW_U12_(uint64 instruction)
15553 {
15554     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15555     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15556     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15557
15558     std::string rt = GPR(copy(rt_value));
15559     std::string u = IMMEDIATE(copy(u_value));
15560     std::string rs = GPR(copy(rs_value));
15561
15562     return img::format("SW %s, %s(%s)", rt, u, rs);
15563 }
15564
15565
15566 /*
15567  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15568  *
15569  *   3         2         1
15570  *  10987654321098765432109876543210
15571  *  001000               00010001101
15572  *     rt -----
15573  *          rs -----
15574  *               rd -----
15575  */
15576 std::string NMD::SWC1_GP_(uint64 instruction)
15577 {
15578     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15579     uint64 u_value = extract_u_17_to_2__s2(instruction);
15580
15581     std::string ft = FPR(copy(ft_value));
15582     std::string u = IMMEDIATE(copy(u_value));
15583
15584     return img::format("SWC1 %s, %s($%d)", ft, u, 28);
15585 }
15586
15587
15588 /*
15589  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15590  *
15591  *   3         2         1
15592  *  10987654321098765432109876543210
15593  *  001000               00010001101
15594  *     rt -----
15595  *          rs -----
15596  *               rd -----
15597  */
15598 std::string NMD::SWC1_S9_(uint64 instruction)
15599 {
15600     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15601     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15602     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15603
15604     std::string ft = FPR(copy(ft_value));
15605     std::string s = IMMEDIATE(copy(s_value));
15606     std::string rs = GPR(copy(rs_value));
15607
15608     return img::format("SWC1 %s, %s(%s)", ft, s, rs);
15609 }
15610
15611
15612 /*
15613  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15614  *
15615  *   3         2         1
15616  *  10987654321098765432109876543210
15617  *  001000               00010001101
15618  *     rt -----
15619  *          rs -----
15620  *               rd -----
15621  */
15622 std::string NMD::SWC1_U12_(uint64 instruction)
15623 {
15624     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15625     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15626     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15627
15628     std::string ft = FPR(copy(ft_value));
15629     std::string u = IMMEDIATE(copy(u_value));
15630     std::string rs = GPR(copy(rs_value));
15631
15632     return img::format("SWC1 %s, %s(%s)", ft, u, rs);
15633 }
15634
15635
15636 /*
15637  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15638  *
15639  *   3         2         1
15640  *  10987654321098765432109876543210
15641  *  001000               00010001101
15642  *     rt -----
15643  *          rs -----
15644  *               rd -----
15645  */
15646 std::string NMD::SWC1X(uint64 instruction)
15647 {
15648     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15649     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15650     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15651
15652     std::string ft = FPR(copy(ft_value));
15653     std::string rs = GPR(copy(rs_value));
15654     std::string rt = GPR(copy(rt_value));
15655
15656     return img::format("SWC1X %s, %s(%s)", ft, rs, rt);
15657 }
15658
15659
15660 /*
15661  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15662  *
15663  *   3         2         1
15664  *  10987654321098765432109876543210
15665  *  001000               00010001101
15666  *     rt -----
15667  *          rs -----
15668  *               rd -----
15669  */
15670 std::string NMD::SWC1XS(uint64 instruction)
15671 {
15672     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15673     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15674     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15675
15676     std::string ft = FPR(copy(ft_value));
15677     std::string rs = GPR(copy(rs_value));
15678     std::string rt = GPR(copy(rt_value));
15679
15680     return img::format("SWC1XS %s, %s(%s)", ft, rs, rt);
15681 }
15682
15683
15684 /*
15685  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15686  *
15687  *   3         2         1
15688  *  10987654321098765432109876543210
15689  *  001000               00010001101
15690  *     rt -----
15691  *          rs -----
15692  *               rd -----
15693  */
15694 std::string NMD::SWC2(uint64 instruction)
15695 {
15696     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
15697     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15698     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15699
15700     std::string cs = CPR(copy(cs_value));
15701     std::string s = IMMEDIATE(copy(s_value));
15702     std::string rs = GPR(copy(rs_value));
15703
15704     return img::format("SWC2 %s, %s(%s)", cs, s, rs);
15705 }
15706
15707
15708 /*
15709  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15710  *
15711  *   3         2         1
15712  *  10987654321098765432109876543210
15713  *  001000               00010001101
15714  *     rt -----
15715  *          rs -----
15716  *               rd -----
15717  */
15718 std::string NMD::SWE(uint64 instruction)
15719 {
15720     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15721     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15722     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15723
15724     std::string rt = GPR(copy(rt_value));
15725     std::string s = IMMEDIATE(copy(s_value));
15726     std::string rs = GPR(copy(rs_value));
15727
15728     return img::format("SWE %s, %s(%s)", rt, s, rs);
15729 }
15730
15731
15732 /*
15733  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15734  *
15735  *   3         2         1
15736  *  10987654321098765432109876543210
15737  *  001000               00010001101
15738  *     rt -----
15739  *          rs -----
15740  *               rd -----
15741  */
15742 std::string NMD::SWM(uint64 instruction)
15743 {
15744     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15745     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15746     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15747     uint64 count3_value = extract_count3_14_13_12(instruction);
15748
15749     std::string rt = GPR(copy(rt_value));
15750     std::string s = IMMEDIATE(copy(s_value));
15751     std::string rs = GPR(copy(rs_value));
15752     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
15753
15754     return img::format("SWM %s, %s(%s), %s", rt, s, rs, count3);
15755 }
15756
15757
15758 /*
15759  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15760  *
15761  *   3         2         1
15762  *  10987654321098765432109876543210
15763  *  001000               00010001101
15764  *     rt -----
15765  *          rs -----
15766  *               rd -----
15767  */
15768 std::string NMD::SWPC_48_(uint64 instruction)
15769 {
15770     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
15771     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
15772
15773     std::string rt = GPR(copy(rt_value));
15774     std::string s = ADDRESS(encode_s_from_address(s_value), 6);
15775
15776     return img::format("SWPC %s, %s", rt, s);
15777 }
15778
15779
15780 /*
15781  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15782  *
15783  *   3         2         1
15784  *  10987654321098765432109876543210
15785  *  001000               00010001101
15786  *     rt -----
15787  *          rs -----
15788  *               rd -----
15789  */
15790 std::string NMD::SWX(uint64 instruction)
15791 {
15792     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15793     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15794     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15795
15796     std::string rd = GPR(copy(rd_value));
15797     std::string rs = GPR(copy(rs_value));
15798     std::string rt = GPR(copy(rt_value));
15799
15800     return img::format("SWX %s, %s(%s)", rd, rs, rt);
15801 }
15802
15803
15804 /*
15805  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15806  *
15807  *   3         2         1
15808  *  10987654321098765432109876543210
15809  *  001000               00010001101
15810  *     rt -----
15811  *          rs -----
15812  *               rd -----
15813  */
15814 std::string NMD::SWXS(uint64 instruction)
15815 {
15816     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15817     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15818     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15819
15820     std::string rd = GPR(copy(rd_value));
15821     std::string rs = GPR(copy(rs_value));
15822     std::string rt = GPR(copy(rt_value));
15823
15824     return img::format("SWXS %s, %s(%s)", rd, rs, rt);
15825 }
15826
15827
15828 /*
15829  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15830  *
15831  *   3         2         1
15832  *  10987654321098765432109876543210
15833  *  001000               00010001101
15834  *     rt -----
15835  *          rs -----
15836  *               rd -----
15837  */
15838 std::string NMD::SYNC(uint64 instruction)
15839 {
15840     uint64 stype_value = extract_stype_20_19_18_17_16(instruction);
15841
15842     std::string stype = IMMEDIATE(copy(stype_value));
15843
15844     return img::format("SYNC %s", stype);
15845 }
15846
15847
15848 /*
15849  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15850  *
15851  *   3         2         1
15852  *  10987654321098765432109876543210
15853  *  001000               00010001101
15854  *     rt -----
15855  *          rs -----
15856  *               rd -----
15857  */
15858 std::string NMD::SYNCI(uint64 instruction)
15859 {
15860     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15861     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15862
15863     std::string s = IMMEDIATE(copy(s_value));
15864     std::string rs = GPR(copy(rs_value));
15865
15866     return img::format("SYNCI %s(%s)", s, rs);
15867 }
15868
15869
15870 /*
15871  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15872  *
15873  *   3         2         1
15874  *  10987654321098765432109876543210
15875  *  001000               00010001101
15876  *     rt -----
15877  *          rs -----
15878  *               rd -----
15879  */
15880 std::string NMD::SYNCIE(uint64 instruction)
15881 {
15882     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15883     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15884
15885     std::string s = IMMEDIATE(copy(s_value));
15886     std::string rs = GPR(copy(rs_value));
15887
15888     return img::format("SYNCIE %s(%s)", s, rs);
15889 }
15890
15891
15892 /*
15893  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15894  *
15895  *   3         2         1
15896  *  10987654321098765432109876543210
15897  *  001000               00010001101
15898  *     rt -----
15899  *          rs -----
15900  *               rd -----
15901  */
15902 std::string NMD::SYSCALL_16_(uint64 instruction)
15903 {
15904     uint64 code_value = extract_code_1_0(instruction);
15905
15906     std::string code = IMMEDIATE(copy(code_value));
15907
15908     return img::format("SYSCALL %s", code);
15909 }
15910
15911
15912 /*
15913  * SYSCALL code - System Call. Cause a System Call Exception
15914  *
15915  *   3         2         1
15916  *  10987654321098765432109876543210
15917  *  00000000000010
15918  *           code ------------------
15919  */
15920 std::string NMD::SYSCALL_32_(uint64 instruction)
15921 {
15922     uint64 code_value = extract_code_17_to_0(instruction);
15923
15924     std::string code = IMMEDIATE(copy(code_value));
15925
15926     return img::format("SYSCALL %s", code);
15927 }
15928
15929
15930 /*
15931  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15932  *
15933  *   3         2         1
15934  *  10987654321098765432109876543210
15935  *  001000               00010001101
15936  *     rt -----
15937  *          rs -----
15938  *               rd -----
15939  */
15940 std::string NMD::TEQ(uint64 instruction)
15941 {
15942     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15943     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15944
15945     std::string rs = GPR(copy(rs_value));
15946     std::string rt = GPR(copy(rt_value));
15947
15948     return img::format("TEQ %s, %s", rs, rt);
15949 }
15950
15951
15952 /*
15953  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15954  *
15955  *   3         2         1
15956  *  10987654321098765432109876543210
15957  *  001000               00010001101
15958  *     rt -----
15959  *          rs -----
15960  *               rd -----
15961  */
15962 std::string NMD::TLBGINV(uint64 instruction)
15963 {
15964     (void)instruction;
15965
15966     return "TLBGINV ";
15967 }
15968
15969
15970 /*
15971  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15972  *
15973  *   3         2         1
15974  *  10987654321098765432109876543210
15975  *  001000               00010001101
15976  *     rt -----
15977  *          rs -----
15978  *               rd -----
15979  */
15980 std::string NMD::TLBGINVF(uint64 instruction)
15981 {
15982     (void)instruction;
15983
15984     return "TLBGINVF ";
15985 }
15986
15987
15988 /*
15989  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15990  *
15991  *   3         2         1
15992  *  10987654321098765432109876543210
15993  *  001000               00010001101
15994  *     rt -----
15995  *          rs -----
15996  *               rd -----
15997  */
15998 std::string NMD::TLBGP(uint64 instruction)
15999 {
16000     (void)instruction;
16001
16002     return "TLBGP ";
16003 }
16004
16005
16006 /*
16007  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16008  *
16009  *   3         2         1
16010  *  10987654321098765432109876543210
16011  *  001000               00010001101
16012  *     rt -----
16013  *          rs -----
16014  *               rd -----
16015  */
16016 std::string NMD::TLBGR(uint64 instruction)
16017 {
16018     (void)instruction;
16019
16020     return "TLBGR ";
16021 }
16022
16023
16024 /*
16025  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16026  *
16027  *   3         2         1
16028  *  10987654321098765432109876543210
16029  *  001000               00010001101
16030  *     rt -----
16031  *          rs -----
16032  *               rd -----
16033  */
16034 std::string NMD::TLBGWI(uint64 instruction)
16035 {
16036     (void)instruction;
16037
16038     return "TLBGWI ";
16039 }
16040
16041
16042 /*
16043  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16044  *
16045  *   3         2         1
16046  *  10987654321098765432109876543210
16047  *  001000               00010001101
16048  *     rt -----
16049  *          rs -----
16050  *               rd -----
16051  */
16052 std::string NMD::TLBGWR(uint64 instruction)
16053 {
16054     (void)instruction;
16055
16056     return "TLBGWR ";
16057 }
16058
16059
16060 /*
16061  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16062  *
16063  *   3         2         1
16064  *  10987654321098765432109876543210
16065  *  001000               00010001101
16066  *     rt -----
16067  *          rs -----
16068  *               rd -----
16069  */
16070 std::string NMD::TLBINV(uint64 instruction)
16071 {
16072     (void)instruction;
16073
16074     return "TLBINV ";
16075 }
16076
16077
16078 /*
16079  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16080  *
16081  *   3         2         1
16082  *  10987654321098765432109876543210
16083  *  001000               00010001101
16084  *     rt -----
16085  *          rs -----
16086  *               rd -----
16087  */
16088 std::string NMD::TLBINVF(uint64 instruction)
16089 {
16090     (void)instruction;
16091
16092     return "TLBINVF ";
16093 }
16094
16095
16096 /*
16097  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16098  *
16099  *   3         2         1
16100  *  10987654321098765432109876543210
16101  *  001000               00010001101
16102  *     rt -----
16103  *          rs -----
16104  *               rd -----
16105  */
16106 std::string NMD::TLBP(uint64 instruction)
16107 {
16108     (void)instruction;
16109
16110     return "TLBP ";
16111 }
16112
16113
16114 /*
16115  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16116  *
16117  *   3         2         1
16118  *  10987654321098765432109876543210
16119  *  001000               00010001101
16120  *     rt -----
16121  *          rs -----
16122  *               rd -----
16123  */
16124 std::string NMD::TLBR(uint64 instruction)
16125 {
16126     (void)instruction;
16127
16128     return "TLBR ";
16129 }
16130
16131
16132 /*
16133  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16134  *
16135  *   3         2         1
16136  *  10987654321098765432109876543210
16137  *  001000               00010001101
16138  *     rt -----
16139  *          rs -----
16140  *               rd -----
16141  */
16142 std::string NMD::TLBWI(uint64 instruction)
16143 {
16144     (void)instruction;
16145
16146     return "TLBWI ";
16147 }
16148
16149
16150 /*
16151  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16152  *
16153  *   3         2         1
16154  *  10987654321098765432109876543210
16155  *  001000               00010001101
16156  *     rt -----
16157  *          rs -----
16158  *               rd -----
16159  */
16160 std::string NMD::TLBWR(uint64 instruction)
16161 {
16162     (void)instruction;
16163
16164     return "TLBWR ";
16165 }
16166
16167
16168 /*
16169  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16170  *
16171  *   3         2         1
16172  *  10987654321098765432109876543210
16173  *  001000               00010001101
16174  *     rt -----
16175  *          rs -----
16176  *               rd -----
16177  */
16178 std::string NMD::TNE(uint64 instruction)
16179 {
16180     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16181     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16182
16183     std::string rs = GPR(copy(rs_value));
16184     std::string rt = GPR(copy(rt_value));
16185
16186     return img::format("TNE %s, %s", rs, rt);
16187 }
16188
16189
16190 /*
16191  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16192  *
16193  *   3         2         1
16194  *  10987654321098765432109876543210
16195  *  001000               00010001101
16196  *     rt -----
16197  *          rs -----
16198  *               rd -----
16199  */
16200 std::string NMD::TRUNC_L_D(uint64 instruction)
16201 {
16202     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16203     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16204
16205     std::string ft = FPR(copy(ft_value));
16206     std::string fs = FPR(copy(fs_value));
16207
16208     return img::format("TRUNC.L.D %s, %s", ft, fs);
16209 }
16210
16211
16212 /*
16213  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16214  *
16215  *   3         2         1
16216  *  10987654321098765432109876543210
16217  *  001000               00010001101
16218  *     rt -----
16219  *          rs -----
16220  *               rd -----
16221  */
16222 std::string NMD::TRUNC_L_S(uint64 instruction)
16223 {
16224     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16225     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16226
16227     std::string ft = FPR(copy(ft_value));
16228     std::string fs = FPR(copy(fs_value));
16229
16230     return img::format("TRUNC.L.S %s, %s", ft, fs);
16231 }
16232
16233
16234 /*
16235  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16236  *
16237  *   3         2         1
16238  *  10987654321098765432109876543210
16239  *  001000               00010001101
16240  *     rt -----
16241  *          rs -----
16242  *               rd -----
16243  */
16244 std::string NMD::TRUNC_W_D(uint64 instruction)
16245 {
16246     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16247     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16248
16249     std::string ft = FPR(copy(ft_value));
16250     std::string fs = FPR(copy(fs_value));
16251
16252     return img::format("TRUNC.W.D %s, %s", ft, fs);
16253 }
16254
16255
16256 /*
16257  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16258  *
16259  *   3         2         1
16260  *  10987654321098765432109876543210
16261  *  001000               00010001101
16262  *     rt -----
16263  *          rs -----
16264  *               rd -----
16265  */
16266 std::string NMD::TRUNC_W_S(uint64 instruction)
16267 {
16268     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
16269     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
16270
16271     std::string ft = FPR(copy(ft_value));
16272     std::string fs = FPR(copy(fs_value));
16273
16274     return img::format("TRUNC.W.S %s, %s", ft, fs);
16275 }
16276
16277
16278 /*
16279  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16280  *
16281  *   3         2         1
16282  *  10987654321098765432109876543210
16283  *  001000               00010001101
16284  *     rt -----
16285  *          rs -----
16286  *               rd -----
16287  */
16288 std::string NMD::UALDM(uint64 instruction)
16289 {
16290     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16291     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16292     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16293     uint64 count3_value = extract_count3_14_13_12(instruction);
16294
16295     std::string rt = GPR(copy(rt_value));
16296     std::string s = IMMEDIATE(copy(s_value));
16297     std::string rs = GPR(copy(rs_value));
16298     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16299
16300     return img::format("UALDM %s, %s(%s), %s", rt, s, rs, count3);
16301 }
16302
16303
16304 /*
16305  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16306  *
16307  *   3         2         1
16308  *  10987654321098765432109876543210
16309  *  001000               00010001101
16310  *     rt -----
16311  *          rs -----
16312  *               rd -----
16313  */
16314 std::string NMD::UALH(uint64 instruction)
16315 {
16316     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16317     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16318     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16319
16320     std::string rt = GPR(copy(rt_value));
16321     std::string s = IMMEDIATE(copy(s_value));
16322     std::string rs = GPR(copy(rs_value));
16323
16324     return img::format("UALH %s, %s(%s)", rt, s, rs);
16325 }
16326
16327
16328 /*
16329  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16330  *
16331  *   3         2         1
16332  *  10987654321098765432109876543210
16333  *  001000               00010001101
16334  *     rt -----
16335  *          rs -----
16336  *               rd -----
16337  */
16338 std::string NMD::UALWM(uint64 instruction)
16339 {
16340     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16341     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16342     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16343     uint64 count3_value = extract_count3_14_13_12(instruction);
16344
16345     std::string rt = GPR(copy(rt_value));
16346     std::string s = IMMEDIATE(copy(s_value));
16347     std::string rs = GPR(copy(rs_value));
16348     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16349
16350     return img::format("UALWM %s, %s(%s), %s", rt, s, rs, count3);
16351 }
16352
16353
16354 /*
16355  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16356  *
16357  *   3         2         1
16358  *  10987654321098765432109876543210
16359  *  001000               00010001101
16360  *     rt -----
16361  *          rs -----
16362  *               rd -----
16363  */
16364 std::string NMD::UASDM(uint64 instruction)
16365 {
16366     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16367     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16368     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16369     uint64 count3_value = extract_count3_14_13_12(instruction);
16370
16371     std::string rt = GPR(copy(rt_value));
16372     std::string s = IMMEDIATE(copy(s_value));
16373     std::string rs = GPR(copy(rs_value));
16374     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16375
16376     return img::format("UASDM %s, %s(%s), %s", rt, s, rs, count3);
16377 }
16378
16379
16380 /*
16381  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16382  *
16383  *   3         2         1
16384  *  10987654321098765432109876543210
16385  *  001000               00010001101
16386  *     rt -----
16387  *          rs -----
16388  *               rd -----
16389  */
16390 std::string NMD::UASH(uint64 instruction)
16391 {
16392     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16393     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16394     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16395
16396     std::string rt = GPR(copy(rt_value));
16397     std::string s = IMMEDIATE(copy(s_value));
16398     std::string rs = GPR(copy(rs_value));
16399
16400     return img::format("UASH %s, %s(%s)", rt, s, rs);
16401 }
16402
16403
16404 /*
16405  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16406  *
16407  *   3         2         1
16408  *  10987654321098765432109876543210
16409  *  001000               00010001101
16410  *     rt -----
16411  *          rs -----
16412  *               rd -----
16413  */
16414 std::string NMD::UASWM(uint64 instruction)
16415 {
16416     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16417     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16418     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
16419     uint64 count3_value = extract_count3_14_13_12(instruction);
16420
16421     std::string rt = GPR(copy(rt_value));
16422     std::string s = IMMEDIATE(copy(s_value));
16423     std::string rs = GPR(copy(rs_value));
16424     std::string count3 = IMMEDIATE(encode_count3_from_count(count3_value));
16425
16426     return img::format("UASWM %s, %s(%s), %s", rt, s, rs, count3);
16427 }
16428
16429
16430 /*
16431  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16432  *
16433  *   3         2         1
16434  *  10987654321098765432109876543210
16435  *  001000               00010001101
16436  *     rt -----
16437  *          rs -----
16438  *               rd -----
16439  */
16440 std::string NMD::UDI(uint64 instruction)
16441 {
16442     uint64 op_value = extract_op_25_to_3(instruction);
16443
16444     std::string op = IMMEDIATE(copy(op_value));
16445
16446     return img::format("UDI %s", op);
16447 }
16448
16449
16450 /*
16451  * WAIT code - Enter Wait State
16452  *
16453  *   3         2         1
16454  *  10987654321098765432109876543210
16455  *  001000          1100001101111111
16456  *   code ----------
16457  */
16458 std::string NMD::WAIT(uint64 instruction)
16459 {
16460     uint64 code_value = extract_code_25_24_23_22_21_20_19_18_17_16(instruction);
16461
16462     std::string code = IMMEDIATE(copy(code_value));
16463
16464     return img::format("WAIT %s", code);
16465 }
16466
16467
16468 /*
16469  * [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
16470  *         register
16471  *
16472  *   3         2         1
16473  *  10987654321098765432109876543210
16474  *  001000            01011001111111
16475  *     rt -----
16476  *        mask -------
16477  */
16478 std::string NMD::WRDSP(uint64 instruction)
16479 {
16480     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16481     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
16482
16483     std::string rt = GPR(copy(rt_value));
16484     std::string mask = IMMEDIATE(copy(mask_value));
16485
16486     return img::format("WRDSP %s, %s", rt, mask);
16487 }
16488
16489
16490 /*
16491  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16492  *
16493  *   3         2         1
16494  *  10987654321098765432109876543210
16495  *  001000               00010001101
16496  *     rt -----
16497  *          rs -----
16498  *               rd -----
16499  */
16500 std::string NMD::WRPGPR(uint64 instruction)
16501 {
16502     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16503     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16504
16505     std::string rt = GPR(copy(rt_value));
16506     std::string rs = GPR(copy(rs_value));
16507
16508     return img::format("WRPGPR %s, %s", rt, rs);
16509 }
16510
16511
16512 /*
16513  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16514  *
16515  *   3         2         1
16516  *  10987654321098765432109876543210
16517  *  001000               00010001101
16518  *     rt -----
16519  *          rs -----
16520  *               rd -----
16521  */
16522 std::string NMD::XOR_16_(uint64 instruction)
16523 {
16524     uint64 rt3_value = extract_rt3_9_8_7(instruction);
16525     uint64 rs3_value = extract_rs3_6_5_4(instruction);
16526
16527     std::string rs3 = GPR(decode_gpr_gpr3(rs3_value));
16528     std::string rt3 = GPR(decode_gpr_gpr3(rt3_value));
16529
16530     return img::format("XOR %s, %s", rs3, rt3);
16531 }
16532
16533
16534 /*
16535  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16536  *
16537  *   3         2         1
16538  *  10987654321098765432109876543210
16539  *  001000               00010001101
16540  *     rt -----
16541  *          rs -----
16542  *               rd -----
16543  */
16544 std::string NMD::XOR_32_(uint64 instruction)
16545 {
16546     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16547     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16548     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
16549
16550     std::string rd = GPR(copy(rd_value));
16551     std::string rs = GPR(copy(rs_value));
16552     std::string rt = GPR(copy(rt_value));
16553
16554     return img::format("XOR %s, %s, %s", rd, rs, rt);
16555 }
16556
16557
16558 /*
16559  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16560  *
16561  *   3         2         1
16562  *  10987654321098765432109876543210
16563  *  001000               00010001101
16564  *     rt -----
16565  *          rs -----
16566  *               rd -----
16567  */
16568 std::string NMD::XORI(uint64 instruction)
16569 {
16570     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16571     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16572     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
16573
16574     std::string rt = GPR(copy(rt_value));
16575     std::string rs = GPR(copy(rs_value));
16576     std::string u = IMMEDIATE(copy(u_value));
16577
16578     return img::format("XORI %s, %s, %s", rt, rs, u);
16579 }
16580
16581
16582 /*
16583  * YIELD rt, rs -
16584  *
16585  *   3         2         1
16586  *  10987654321098765432109876543210
16587  *  001000               00010001101
16588  *     rt -----
16589  *          rs -----
16590  */
16591 std::string NMD::YIELD(uint64 instruction)
16592 {
16593     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16594     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16595
16596     std::string rt = GPR(copy(rt_value));
16597     std::string rs = GPR(copy(rs_value));
16598
16599     return img::format("YIELD %s, %s", rt, rs);
16600 }
16601
16602
16603
16604 /*
16605  *                nanoMIPS instruction pool organization
16606  *                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16607  *
16608  *
16609  *                 ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL
16610  *                 │
16611  *                 │                                      ┌─ P.TRAP
16612  *                 │                                      │
16613  *                 │                      ┌─ _POOL32A0_0 ─┼─ P.CMOVE
16614  *                 │                      │               │
16615  *                 │                      │               └─ P.SLTU
16616  *                 │        ┌─ _POOL32A0 ─┤
16617  *                 │        │             │
16618  *                 │        │             │
16619  *                 │        │             └─ _POOL32A0_1 ─── CRC32
16620  *                 │        │
16621  *                 ├─ P32A ─┤
16622  *                 │        │                           ┌─ PP.LSX
16623  *                 │        │             ┌─ P.LSX ─────┤
16624  *                 │        │             │             └─ PP.LSXS
16625  *                 │        └─ _POOL32A7 ─┤
16626  *                 │                      │             ┌─ POOL32Axf_4
16627  *                 │                      └─ POOL32Axf ─┤
16628  *                 │                                    └─ POOL32Axf_5
16629  *                 │
16630  *                 ├─ PBAL
16631  *                 │
16632  *                 ├─ P.GP.W   ┌─ PP.LSX
16633  *         ┌─ P32 ─┤           │
16634  *         │       ├─ P.GP.BH ─┴─ PP.LSXS
16635  *         │       │
16636  *         │       ├─ P.J ─────── PP.BALRSC
16637  *         │       │
16638  *         │       ├─ P48I
16639  *         │       │           ┌─ P.SR
16640  *         │       │           │
16641  *         │       │           ├─ P.SHIFT
16642  *         │       │           │
16643  *         │       ├─ P.U12 ───┼─ P.ROTX
16644  *         │       │           │
16645  *         │       │           ├─ P.INS
16646  *         │       │           │
16647  *         │       │           └─ P.EXT
16648  *         │       │
16649  *         │       ├─ P.LS.U12 ── P.PREF.U12
16650  *         │       │
16651  *         │       ├─ P.BR1 ───── P.BR3A
16652  *         │       │
16653  *         │       │           ┌─ P.LS.S0 ─── P16.SYSCALL
16654  *         │       │           │
16655  *         │       │           │           ┌─ P.LL
16656  *         │       │           ├─ P.LS.S1 ─┤
16657  *         │       │           │           └─ P.SC
16658  *         │       │           │
16659  *         │       │           │           ┌─ P.PREFE
16660  *  MAJOR ─┤       ├─ P.LS.S9 ─┤           │
16661  *         │       │           ├─ P.LS.E0 ─┼─ P.LLE
16662  *         │       │           │           │
16663  *         │       │           │           └─ P.SCE
16664  *         │       │           │
16665  *         │       │           ├─ P.LS.WM
16666  *         │       │           │
16667  *         │       │           └─ P.LS.UAWM
16668  *         │       │
16669  *         │       │
16670  *         │       ├─ P.BR2
16671  *         │       │
16672  *         │       ├─ P.BRI
16673  *         │       │
16674  *         │       └─ P.LUI
16675  *         │
16676  *         │
16677  *         │       ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL
16678  *         │       │
16679  *         │       ├─ P16.SR
16680  *         │       │
16681  *         │       ├─ P16.SHIFT
16682  *         │       │
16683  *         │       ├─ P16.4x4
16684  *         │       │
16685  *         │       ├─ P16C ────── POOL16C_0 ── POOL16C_00
16686  *         │       │
16687  *         └─ P16 ─┼─ P16.LB
16688  *                 │
16689  *                 ├─ P16.A1
16690  *                 │
16691  *                 ├─ P16.LH
16692  *                 │
16693  *                 ├─ P16.A2 ──── P.ADDIU[RS5]
16694  *                 │
16695  *                 ├─ P16.ADDU
16696  *                 │
16697  *                 └─ P16.BR ──┬─ P16.JRC
16698  *                             │
16699  *                             └─ P16.BR1
16700  *
16701  *
16702  *  (FP, DPS, and some minor instruction pools are omitted from the diagram)
16703  *
16704  */
16705
16706 NMD::Pool NMD::P_SYSCALL[2] = {
16707     { instruction         , 0                   , 0   , 32,
16708        0xfffc0000, 0x00080000, &NMD::SYSCALL_32_      , 0,
16709        0x0                 },        /* SYSCALL[32] */
16710     { instruction         , 0                   , 0   , 32,
16711        0xfffc0000, 0x000c0000, &NMD::HYPCALL          , 0,
16712        CP0_ | VZ_          },        /* HYPCALL */
16713 };
16714
16715
16716 NMD::Pool NMD::P_RI[4] = {
16717     { instruction         , 0                   , 0   , 32,
16718        0xfff80000, 0x00000000, &NMD::SIGRIE           , 0,
16719        0x0                 },        /* SIGRIE */
16720     { pool                , P_SYSCALL           , 2   , 32,
16721        0xfff80000, 0x00080000, 0                      , 0,
16722        0x0                 },        /* P.SYSCALL */
16723     { instruction         , 0                   , 0   , 32,
16724        0xfff80000, 0x00100000, &NMD::BREAK_32_        , 0,
16725        0x0                 },        /* BREAK[32] */
16726     { instruction         , 0                   , 0   , 32,
16727        0xfff80000, 0x00180000, &NMD::SDBBP_32_        , 0,
16728        EJTAG_              },        /* SDBBP[32] */
16729 };
16730
16731
16732 NMD::Pool NMD::P_ADDIU[2] = {
16733     { pool                , P_RI                , 4   , 32,
16734        0xffe00000, 0x00000000, 0                      , 0,
16735        0x0                 },        /* P.RI */
16736     { instruction         , 0                   , 0   , 32,
16737        0xfc000000, 0x00000000, &NMD::ADDIU_32_        , &NMD::ADDIU_32__cond   ,
16738        0x0                 },        /* ADDIU[32] */
16739 };
16740
16741
16742 NMD::Pool NMD::P_TRAP[2] = {
16743     { instruction         , 0                   , 0   , 32,
16744        0xfc0007ff, 0x20000000, &NMD::TEQ              , 0,
16745        XMMS_               },        /* TEQ */
16746     { instruction         , 0                   , 0   , 32,
16747        0xfc0007ff, 0x20000400, &NMD::TNE              , 0,
16748        XMMS_               },        /* TNE */
16749 };
16750
16751
16752 NMD::Pool NMD::P_CMOVE[2] = {
16753     { instruction         , 0                   , 0   , 32,
16754        0xfc0007ff, 0x20000210, &NMD::MOVZ             , 0,
16755        0x0                 },        /* MOVZ */
16756     { instruction         , 0                   , 0   , 32,
16757        0xfc0007ff, 0x20000610, &NMD::MOVN             , 0,
16758        0x0                 },        /* MOVN */
16759 };
16760
16761
16762 NMD::Pool NMD::P_D_MT_VPE[2] = {
16763     { instruction         , 0                   , 0   , 32,
16764        0xfc1f3fff, 0x20010ab0, &NMD::DMT              , 0,
16765        MT_                 },        /* DMT */
16766     { instruction         , 0                   , 0   , 32,
16767        0xfc1f3fff, 0x20000ab0, &NMD::DVPE             , 0,
16768        MT_                 },        /* DVPE */
16769 };
16770
16771
16772 NMD::Pool NMD::P_E_MT_VPE[2] = {
16773     { instruction         , 0                   , 0   , 32,
16774        0xfc1f3fff, 0x20010eb0, &NMD::EMT              , 0,
16775        MT_                 },        /* EMT */
16776     { instruction         , 0                   , 0   , 32,
16777        0xfc1f3fff, 0x20000eb0, &NMD::EVPE             , 0,
16778        MT_                 },        /* EVPE */
16779 };
16780
16781
16782 NMD::Pool NMD::_P_MT_VPE[2] = {
16783     { pool                , P_D_MT_VPE          , 2   , 32,
16784        0xfc003fff, 0x20000ab0, 0                      , 0,
16785        0x0                 },        /* P.D_MT_VPE */
16786     { pool                , P_E_MT_VPE          , 2   , 32,
16787        0xfc003fff, 0x20000eb0, 0                      , 0,
16788        0x0                 },        /* P.E_MT_VPE */
16789 };
16790
16791
16792 NMD::Pool NMD::P_MT_VPE[8] = {
16793     { reserved_block      , 0                   , 0   , 32,
16794        0xfc003bff, 0x200002b0, 0                      , 0,
16795        0x0                 },        /* P.MT_VPE~*(0) */
16796     { pool                , _P_MT_VPE           , 2   , 32,
16797        0xfc003bff, 0x20000ab0, 0                      , 0,
16798        0x0                 },        /* _P.MT_VPE */
16799     { reserved_block      , 0                   , 0   , 32,
16800        0xfc003bff, 0x200012b0, 0                      , 0,
16801        0x0                 },        /* P.MT_VPE~*(2) */
16802     { reserved_block      , 0                   , 0   , 32,
16803        0xfc003bff, 0x20001ab0, 0                      , 0,
16804        0x0                 },        /* P.MT_VPE~*(3) */
16805     { reserved_block      , 0                   , 0   , 32,
16806        0xfc003bff, 0x200022b0, 0                      , 0,
16807        0x0                 },        /* P.MT_VPE~*(4) */
16808     { reserved_block      , 0                   , 0   , 32,
16809        0xfc003bff, 0x20002ab0, 0                      , 0,
16810        0x0                 },        /* P.MT_VPE~*(5) */
16811     { reserved_block      , 0                   , 0   , 32,
16812        0xfc003bff, 0x200032b0, 0                      , 0,
16813        0x0                 },        /* P.MT_VPE~*(6) */
16814     { reserved_block      , 0                   , 0   , 32,
16815        0xfc003bff, 0x20003ab0, 0                      , 0,
16816        0x0                 },        /* P.MT_VPE~*(7) */
16817 };
16818
16819
16820 NMD::Pool NMD::P_DVP[2] = {
16821     { instruction         , 0                   , 0   , 32,
16822        0xfc00ffff, 0x20000390, &NMD::DVP              , 0,
16823        0x0                 },        /* DVP */
16824     { instruction         , 0                   , 0   , 32,
16825        0xfc00ffff, 0x20000790, &NMD::EVP              , 0,
16826        0x0                 },        /* EVP */
16827 };
16828
16829
16830 NMD::Pool NMD::P_SLTU[2] = {
16831     { pool                , P_DVP               , 2   , 32,
16832        0xfc00fbff, 0x20000390, 0                      , 0,
16833        0x0                 },        /* P.DVP */
16834     { instruction         , 0                   , 0   , 32,
16835        0xfc0003ff, 0x20000390, &NMD::SLTU             , &NMD::SLTU_cond        ,
16836        0x0                 },        /* SLTU */
16837 };
16838
16839
16840 NMD::Pool NMD::_POOL32A0[128] = {
16841     { pool                , P_TRAP              , 2   , 32,
16842        0xfc0003ff, 0x20000000, 0                      , 0,
16843        0x0                 },        /* P.TRAP */
16844     { instruction         , 0                   , 0   , 32,
16845        0xfc0003ff, 0x20000008, &NMD::SEB              , 0,
16846        XMMS_               },        /* SEB */
16847     { instruction         , 0                   , 0   , 32,
16848        0xfc0003ff, 0x20000010, &NMD::SLLV             , 0,
16849        0x0                 },        /* SLLV */
16850     { instruction         , 0                   , 0   , 32,
16851        0xfc0003ff, 0x20000018, &NMD::MUL_32_          , 0,
16852        0x0                 },        /* MUL[32] */
16853     { reserved_block      , 0                   , 0   , 32,
16854        0xfc0003ff, 0x20000020, 0                      , 0,
16855        0x0                 },        /* _POOL32A0~*(4) */
16856     { reserved_block      , 0                   , 0   , 32,
16857        0xfc0003ff, 0x20000028, 0                      , 0,
16858        0x0                 },        /* _POOL32A0~*(5) */
16859     { instruction         , 0                   , 0   , 32,
16860        0xfc0003ff, 0x20000030, &NMD::MFC0             , 0,
16861        0x0                 },        /* MFC0 */
16862     { instruction         , 0                   , 0   , 32,
16863        0xfc0003ff, 0x20000038, &NMD::MFHC0            , 0,
16864        CP0_ | MVH_         },        /* MFHC0 */
16865     { reserved_block      , 0                   , 0   , 32,
16866        0xfc0003ff, 0x20000040, 0                      , 0,
16867        0x0                 },        /* _POOL32A0~*(8) */
16868     { instruction         , 0                   , 0   , 32,
16869        0xfc0003ff, 0x20000048, &NMD::SEH              , 0,
16870        0x0                 },        /* SEH */
16871     { instruction         , 0                   , 0   , 32,
16872        0xfc0003ff, 0x20000050, &NMD::SRLV             , 0,
16873        0x0                 },        /* SRLV */
16874     { instruction         , 0                   , 0   , 32,
16875        0xfc0003ff, 0x20000058, &NMD::MUH              , 0,
16876        0x0                 },        /* MUH */
16877     { reserved_block      , 0                   , 0   , 32,
16878        0xfc0003ff, 0x20000060, 0                      , 0,
16879        0x0                 },        /* _POOL32A0~*(12) */
16880     { reserved_block      , 0                   , 0   , 32,
16881        0xfc0003ff, 0x20000068, 0                      , 0,
16882        0x0                 },        /* _POOL32A0~*(13) */
16883     { instruction         , 0                   , 0   , 32,
16884        0xfc0003ff, 0x20000070, &NMD::MTC0             , 0,
16885        CP0_                },        /* MTC0 */
16886     { instruction         , 0                   , 0   , 32,
16887        0xfc0003ff, 0x20000078, &NMD::MTHC0            , 0,
16888        CP0_ | MVH_         },        /* MTHC0 */
16889     { reserved_block      , 0                   , 0   , 32,
16890        0xfc0003ff, 0x20000080, 0                      , 0,
16891        0x0                 },        /* _POOL32A0~*(16) */
16892     { reserved_block      , 0                   , 0   , 32,
16893        0xfc0003ff, 0x20000088, 0                      , 0,
16894        0x0                 },        /* _POOL32A0~*(17) */
16895     { instruction         , 0                   , 0   , 32,
16896        0xfc0003ff, 0x20000090, &NMD::SRAV             , 0,
16897        0x0                 },        /* SRAV */
16898     { instruction         , 0                   , 0   , 32,
16899        0xfc0003ff, 0x20000098, &NMD::MULU             , 0,
16900        0x0                 },        /* MULU */
16901     { reserved_block      , 0                   , 0   , 32,
16902        0xfc0003ff, 0x200000a0, 0                      , 0,
16903        0x0                 },        /* _POOL32A0~*(20) */
16904     { reserved_block      , 0                   , 0   , 32,
16905        0xfc0003ff, 0x200000a8, 0                      , 0,
16906        0x0                 },        /* _POOL32A0~*(21) */
16907     { instruction         , 0                   , 0   , 32,
16908        0xfc0003ff, 0x200000b0, &NMD::MFGC0            , 0,
16909        CP0_ | VZ_          },        /* MFGC0 */
16910     { instruction         , 0                   , 0   , 32,
16911        0xfc0003ff, 0x200000b8, &NMD::MFHGC0           , 0,
16912        CP0_ | VZ_ | MVH_   },        /* MFHGC0 */
16913     { reserved_block      , 0                   , 0   , 32,
16914        0xfc0003ff, 0x200000c0, 0                      , 0,
16915        0x0                 },        /* _POOL32A0~*(24) */
16916     { reserved_block      , 0                   , 0   , 32,
16917        0xfc0003ff, 0x200000c8, 0                      , 0,
16918        0x0                 },        /* _POOL32A0~*(25) */
16919     { instruction         , 0                   , 0   , 32,
16920        0xfc0003ff, 0x200000d0, &NMD::ROTRV            , 0,
16921        0x0                 },        /* ROTRV */
16922     { instruction         , 0                   , 0   , 32,
16923        0xfc0003ff, 0x200000d8, &NMD::MUHU             , 0,
16924        0x0                 },        /* MUHU */
16925     { reserved_block      , 0                   , 0   , 32,
16926        0xfc0003ff, 0x200000e0, 0                      , 0,
16927        0x0                 },        /* _POOL32A0~*(28) */
16928     { reserved_block      , 0                   , 0   , 32,
16929        0xfc0003ff, 0x200000e8, 0                      , 0,
16930        0x0                 },        /* _POOL32A0~*(29) */
16931     { instruction         , 0                   , 0   , 32,
16932        0xfc0003ff, 0x200000f0, &NMD::MTGC0            , 0,
16933        CP0_ | VZ_          },        /* MTGC0 */
16934     { instruction         , 0                   , 0   , 32,
16935        0xfc0003ff, 0x200000f8, &NMD::MTHGC0           , 0,
16936        CP0_ | VZ_ | MVH_   },        /* MTHGC0 */
16937     { reserved_block      , 0                   , 0   , 32,
16938        0xfc0003ff, 0x20000100, 0                      , 0,
16939        0x0                 },        /* _POOL32A0~*(32) */
16940     { reserved_block      , 0                   , 0   , 32,
16941        0xfc0003ff, 0x20000108, 0                      , 0,
16942        0x0                 },        /* _POOL32A0~*(33) */
16943     { instruction         , 0                   , 0   , 32,
16944        0xfc0003ff, 0x20000110, &NMD::ADD              , 0,
16945        XMMS_               },        /* ADD */
16946     { instruction         , 0                   , 0   , 32,
16947        0xfc0003ff, 0x20000118, &NMD::DIV              , 0,
16948        0x0                 },        /* DIV */
16949     { reserved_block      , 0                   , 0   , 32,
16950        0xfc0003ff, 0x20000120, 0                      , 0,
16951        0x0                 },        /* _POOL32A0~*(36) */
16952     { reserved_block      , 0                   , 0   , 32,
16953        0xfc0003ff, 0x20000128, 0                      , 0,
16954        0x0                 },        /* _POOL32A0~*(37) */
16955     { instruction         , 0                   , 0   , 32,
16956        0xfc0003ff, 0x20000130, &NMD::DMFC0            , 0,
16957        CP0_ | MIPS64_      },        /* DMFC0 */
16958     { reserved_block      , 0                   , 0   , 32,
16959        0xfc0003ff, 0x20000138, 0                      , 0,
16960        0x0                 },        /* _POOL32A0~*(39) */
16961     { reserved_block      , 0                   , 0   , 32,
16962        0xfc0003ff, 0x20000140, 0                      , 0,
16963        0x0                 },        /* _POOL32A0~*(40) */
16964     { reserved_block      , 0                   , 0   , 32,
16965        0xfc0003ff, 0x20000148, 0                      , 0,
16966        0x0                 },        /* _POOL32A0~*(41) */
16967     { instruction         , 0                   , 0   , 32,
16968        0xfc0003ff, 0x20000150, &NMD::ADDU_32_         , 0,
16969        0x0                 },        /* ADDU[32] */
16970     { instruction         , 0                   , 0   , 32,
16971        0xfc0003ff, 0x20000158, &NMD::MOD              , 0,
16972        0x0                 },        /* MOD */
16973     { reserved_block      , 0                   , 0   , 32,
16974        0xfc0003ff, 0x20000160, 0                      , 0,
16975        0x0                 },        /* _POOL32A0~*(44) */
16976     { reserved_block      , 0                   , 0   , 32,
16977        0xfc0003ff, 0x20000168, 0                      , 0,
16978        0x0                 },        /* _POOL32A0~*(45) */
16979     { instruction         , 0                   , 0   , 32,
16980        0xfc0003ff, 0x20000170, &NMD::DMTC0            , 0,
16981        CP0_ | MIPS64_      },        /* DMTC0 */
16982     { reserved_block      , 0                   , 0   , 32,
16983        0xfc0003ff, 0x20000178, 0                      , 0,
16984        0x0                 },        /* _POOL32A0~*(47) */
16985     { reserved_block      , 0                   , 0   , 32,
16986        0xfc0003ff, 0x20000180, 0                      , 0,
16987        0x0                 },        /* _POOL32A0~*(48) */
16988     { reserved_block      , 0                   , 0   , 32,
16989        0xfc0003ff, 0x20000188, 0                      , 0,
16990        0x0                 },        /* _POOL32A0~*(49) */
16991     { instruction         , 0                   , 0   , 32,
16992        0xfc0003ff, 0x20000190, &NMD::SUB              , 0,
16993        XMMS_               },        /* SUB */
16994     { instruction         , 0                   , 0   , 32,
16995        0xfc0003ff, 0x20000198, &NMD::DIVU             , 0,
16996        0x0                 },        /* DIVU */
16997     { reserved_block      , 0                   , 0   , 32,
16998        0xfc0003ff, 0x200001a0, 0                      , 0,
16999        0x0                 },        /* _POOL32A0~*(52) */
17000     { reserved_block      , 0                   , 0   , 32,
17001        0xfc0003ff, 0x200001a8, 0                      , 0,
17002        0x0                 },        /* _POOL32A0~*(53) */
17003     { instruction         , 0                   , 0   , 32,
17004        0xfc0003ff, 0x200001b0, &NMD::DMFGC0           , 0,
17005        CP0_ | MIPS64_ | VZ_},        /* DMFGC0 */
17006     { reserved_block      , 0                   , 0   , 32,
17007        0xfc0003ff, 0x200001b8, 0                      , 0,
17008        0x0                 },        /* _POOL32A0~*(55) */
17009     { instruction         , 0                   , 0   , 32,
17010        0xfc0003ff, 0x200001c0, &NMD::RDHWR            , 0,
17011        XMMS_               },        /* RDHWR */
17012     { reserved_block      , 0                   , 0   , 32,
17013        0xfc0003ff, 0x200001c8, 0                      , 0,
17014        0x0                 },        /* _POOL32A0~*(57) */
17015     { instruction         , 0                   , 0   , 32,
17016        0xfc0003ff, 0x200001d0, &NMD::SUBU_32_         , 0,
17017        0x0                 },        /* SUBU[32] */
17018     { instruction         , 0                   , 0   , 32,
17019        0xfc0003ff, 0x200001d8, &NMD::MODU             , 0,
17020        0x0                 },        /* MODU */
17021     { reserved_block      , 0                   , 0   , 32,
17022        0xfc0003ff, 0x200001e0, 0                      , 0,
17023        0x0                 },        /* _POOL32A0~*(60) */
17024     { reserved_block      , 0                   , 0   , 32,
17025        0xfc0003ff, 0x200001e8, 0                      , 0,
17026        0x0                 },        /* _POOL32A0~*(61) */
17027     { instruction         , 0                   , 0   , 32,
17028        0xfc0003ff, 0x200001f0, &NMD::DMTGC0           , 0,
17029        CP0_ | MIPS64_ | VZ_},        /* DMTGC0 */
17030     { reserved_block      , 0                   , 0   , 32,
17031        0xfc0003ff, 0x200001f8, 0                      , 0,
17032        0x0                 },        /* _POOL32A0~*(63) */
17033     { reserved_block      , 0                   , 0   , 32,
17034        0xfc0003ff, 0x20000200, 0                      , 0,
17035        0x0                 },        /* _POOL32A0~*(64) */
17036     { reserved_block      , 0                   , 0   , 32,
17037        0xfc0003ff, 0x20000208, 0                      , 0,
17038        0x0                 },        /* _POOL32A0~*(65) */
17039     { pool                , P_CMOVE             , 2   , 32,
17040        0xfc0003ff, 0x20000210, 0                      , 0,
17041        0x0                 },        /* P.CMOVE */
17042     { reserved_block      , 0                   , 0   , 32,
17043        0xfc0003ff, 0x20000218, 0                      , 0,
17044        0x0                 },        /* _POOL32A0~*(67) */
17045     { reserved_block      , 0                   , 0   , 32,
17046        0xfc0003ff, 0x20000220, 0                      , 0,
17047        0x0                 },        /* _POOL32A0~*(68) */
17048     { instruction         , 0                   , 0   , 32,
17049        0xfc0003ff, 0x20000228, &NMD::FORK             , 0,
17050        MT_                 },        /* FORK */
17051     { instruction         , 0                   , 0   , 32,
17052        0xfc0003ff, 0x20000230, &NMD::MFTR             , 0,
17053        MT_                 },        /* MFTR */
17054     { instruction         , 0                   , 0   , 32,
17055        0xfc0003ff, 0x20000238, &NMD::MFHTR            , 0,
17056        MT_                 },        /* MFHTR */
17057     { reserved_block      , 0                   , 0   , 32,
17058        0xfc0003ff, 0x20000240, 0                      , 0,
17059        0x0                 },        /* _POOL32A0~*(72) */
17060     { reserved_block      , 0                   , 0   , 32,
17061        0xfc0003ff, 0x20000248, 0                      , 0,
17062        0x0                 },        /* _POOL32A0~*(73) */
17063     { instruction         , 0                   , 0   , 32,
17064        0xfc0003ff, 0x20000250, &NMD::AND_32_          , 0,
17065        0x0                 },        /* AND[32] */
17066     { reserved_block      , 0                   , 0   , 32,
17067        0xfc0003ff, 0x20000258, 0                      , 0,
17068        0x0                 },        /* _POOL32A0~*(75) */
17069     { reserved_block      , 0                   , 0   , 32,
17070        0xfc0003ff, 0x20000260, 0                      , 0,
17071        0x0                 },        /* _POOL32A0~*(76) */
17072     { instruction         , 0                   , 0   , 32,
17073        0xfc0003ff, 0x20000268, &NMD::YIELD            , 0,
17074        MT_                 },        /* YIELD */
17075     { instruction         , 0                   , 0   , 32,
17076        0xfc0003ff, 0x20000270, &NMD::MTTR             , 0,
17077        MT_                 },        /* MTTR */
17078     { instruction         , 0                   , 0   , 32,
17079        0xfc0003ff, 0x20000278, &NMD::MTHTR            , 0,
17080        MT_                 },        /* MTHTR */
17081     { reserved_block      , 0                   , 0   , 32,
17082        0xfc0003ff, 0x20000280, 0                      , 0,
17083        0x0                 },        /* _POOL32A0~*(80) */
17084     { reserved_block      , 0                   , 0   , 32,
17085        0xfc0003ff, 0x20000288, 0                      , 0,
17086        0x0                 },        /* _POOL32A0~*(81) */
17087     { instruction         , 0                   , 0   , 32,
17088        0xfc0003ff, 0x20000290, &NMD::OR_32_           , 0,
17089        0x0                 },        /* OR[32] */
17090     { reserved_block      , 0                   , 0   , 32,
17091        0xfc0003ff, 0x20000298, 0                      , 0,
17092        0x0                 },        /* _POOL32A0~*(83) */
17093     { reserved_block      , 0                   , 0   , 32,
17094        0xfc0003ff, 0x200002a0, 0                      , 0,
17095        0x0                 },        /* _POOL32A0~*(84) */
17096     { reserved_block      , 0                   , 0   , 32,
17097        0xfc0003ff, 0x200002a8, 0                      , 0,
17098        0x0                 },        /* _POOL32A0~*(85) */
17099     { pool                , P_MT_VPE            , 8   , 32,
17100        0xfc0003ff, 0x200002b0, 0                      , 0,
17101        0x0                 },        /* P.MT_VPE */
17102     { reserved_block      , 0                   , 0   , 32,
17103        0xfc0003ff, 0x200002b8, 0                      , 0,
17104        0x0                 },        /* _POOL32A0~*(87) */
17105     { reserved_block      , 0                   , 0   , 32,
17106        0xfc0003ff, 0x200002c0, 0                      , 0,
17107        0x0                 },        /* _POOL32A0~*(88) */
17108     { reserved_block      , 0                   , 0   , 32,
17109        0xfc0003ff, 0x200002c8, 0                      , 0,
17110        0x0                 },        /* _POOL32A0~*(89) */
17111     { instruction         , 0                   , 0   , 32,
17112        0xfc0003ff, 0x200002d0, &NMD::NOR              , 0,
17113        0x0                 },        /* NOR */
17114     { reserved_block      , 0                   , 0   , 32,
17115        0xfc0003ff, 0x200002d8, 0                      , 0,
17116        0x0                 },        /* _POOL32A0~*(91) */
17117     { reserved_block      , 0                   , 0   , 32,
17118        0xfc0003ff, 0x200002e0, 0                      , 0,
17119        0x0                 },        /* _POOL32A0~*(92) */
17120     { reserved_block      , 0                   , 0   , 32,
17121        0xfc0003ff, 0x200002e8, 0                      , 0,
17122        0x0                 },        /* _POOL32A0~*(93) */
17123     { reserved_block      , 0                   , 0   , 32,
17124        0xfc0003ff, 0x200002f0, 0                      , 0,
17125        0x0                 },        /* _POOL32A0~*(94) */
17126     { reserved_block      , 0                   , 0   , 32,
17127        0xfc0003ff, 0x200002f8, 0                      , 0,
17128        0x0                 },        /* _POOL32A0~*(95) */
17129     { reserved_block      , 0                   , 0   , 32,
17130        0xfc0003ff, 0x20000300, 0                      , 0,
17131        0x0                 },        /* _POOL32A0~*(96) */
17132     { reserved_block      , 0                   , 0   , 32,
17133        0xfc0003ff, 0x20000308, 0                      , 0,
17134        0x0                 },        /* _POOL32A0~*(97) */
17135     { instruction         , 0                   , 0   , 32,
17136        0xfc0003ff, 0x20000310, &NMD::XOR_32_          , 0,
17137        0x0                 },        /* XOR[32] */
17138     { reserved_block      , 0                   , 0   , 32,
17139        0xfc0003ff, 0x20000318, 0                      , 0,
17140        0x0                 },        /* _POOL32A0~*(99) */
17141     { reserved_block      , 0                   , 0   , 32,
17142        0xfc0003ff, 0x20000320, 0                      , 0,
17143        0x0                 },        /* _POOL32A0~*(100) */
17144     { reserved_block      , 0                   , 0   , 32,
17145        0xfc0003ff, 0x20000328, 0                      , 0,
17146        0x0                 },        /* _POOL32A0~*(101) */
17147     { reserved_block      , 0                   , 0   , 32,
17148        0xfc0003ff, 0x20000330, 0                      , 0,
17149        0x0                 },        /* _POOL32A0~*(102) */
17150     { reserved_block      , 0                   , 0   , 32,
17151        0xfc0003ff, 0x20000338, 0                      , 0,
17152        0x0                 },        /* _POOL32A0~*(103) */
17153     { reserved_block      , 0                   , 0   , 32,
17154        0xfc0003ff, 0x20000340, 0                      , 0,
17155        0x0                 },        /* _POOL32A0~*(104) */
17156     { reserved_block      , 0                   , 0   , 32,
17157        0xfc0003ff, 0x20000348, 0                      , 0,
17158        0x0                 },        /* _POOL32A0~*(105) */
17159     { instruction         , 0                   , 0   , 32,
17160        0xfc0003ff, 0x20000350, &NMD::SLT              , 0,
17161        0x0                 },        /* SLT */
17162     { reserved_block      , 0                   , 0   , 32,
17163        0xfc0003ff, 0x20000358, 0                      , 0,
17164        0x0                 },        /* _POOL32A0~*(107) */
17165     { reserved_block      , 0                   , 0   , 32,
17166        0xfc0003ff, 0x20000360, 0                      , 0,
17167        0x0                 },        /* _POOL32A0~*(108) */
17168     { reserved_block      , 0                   , 0   , 32,
17169        0xfc0003ff, 0x20000368, 0                      , 0,
17170        0x0                 },        /* _POOL32A0~*(109) */
17171     { reserved_block      , 0                   , 0   , 32,
17172        0xfc0003ff, 0x20000370, 0                      , 0,
17173        0x0                 },        /* _POOL32A0~*(110) */
17174     { reserved_block      , 0                   , 0   , 32,
17175        0xfc0003ff, 0x20000378, 0                      , 0,
17176        0x0                 },        /* _POOL32A0~*(111) */
17177     { reserved_block      , 0                   , 0   , 32,
17178        0xfc0003ff, 0x20000380, 0                      , 0,
17179        0x0                 },        /* _POOL32A0~*(112) */
17180     { reserved_block      , 0                   , 0   , 32,
17181        0xfc0003ff, 0x20000388, 0                      , 0,
17182        0x0                 },        /* _POOL32A0~*(113) */
17183     { pool                , P_SLTU              , 2   , 32,
17184        0xfc0003ff, 0x20000390, 0                      , 0,
17185        0x0                 },        /* P.SLTU */
17186     { reserved_block      , 0                   , 0   , 32,
17187        0xfc0003ff, 0x20000398, 0                      , 0,
17188        0x0                 },        /* _POOL32A0~*(115) */
17189     { reserved_block      , 0                   , 0   , 32,
17190        0xfc0003ff, 0x200003a0, 0                      , 0,
17191        0x0                 },        /* _POOL32A0~*(116) */
17192     { reserved_block      , 0                   , 0   , 32,
17193        0xfc0003ff, 0x200003a8, 0                      , 0,
17194        0x0                 },        /* _POOL32A0~*(117) */
17195     { reserved_block      , 0                   , 0   , 32,
17196        0xfc0003ff, 0x200003b0, 0                      , 0,
17197        0x0                 },        /* _POOL32A0~*(118) */
17198     { reserved_block      , 0                   , 0   , 32,
17199        0xfc0003ff, 0x200003b8, 0                      , 0,
17200        0x0                 },        /* _POOL32A0~*(119) */
17201     { reserved_block      , 0                   , 0   , 32,
17202        0xfc0003ff, 0x200003c0, 0                      , 0,
17203        0x0                 },        /* _POOL32A0~*(120) */
17204     { reserved_block      , 0                   , 0   , 32,
17205        0xfc0003ff, 0x200003c8, 0                      , 0,
17206        0x0                 },        /* _POOL32A0~*(121) */
17207     { instruction         , 0                   , 0   , 32,
17208        0xfc0003ff, 0x200003d0, &NMD::SOV              , 0,
17209        0x0                 },        /* SOV */
17210     { reserved_block      , 0                   , 0   , 32,
17211        0xfc0003ff, 0x200003d8, 0                      , 0,
17212        0x0                 },        /* _POOL32A0~*(123) */
17213     { reserved_block      , 0                   , 0   , 32,
17214        0xfc0003ff, 0x200003e0, 0                      , 0,
17215        0x0                 },        /* _POOL32A0~*(124) */
17216     { reserved_block      , 0                   , 0   , 32,
17217        0xfc0003ff, 0x200003e8, 0                      , 0,
17218        0x0                 },        /* _POOL32A0~*(125) */
17219     { reserved_block      , 0                   , 0   , 32,
17220        0xfc0003ff, 0x200003f0, 0                      , 0,
17221        0x0                 },        /* _POOL32A0~*(126) */
17222     { reserved_block      , 0                   , 0   , 32,
17223        0xfc0003ff, 0x200003f8, 0                      , 0,
17224        0x0                 },        /* _POOL32A0~*(127) */
17225 };
17226
17227
17228 NMD::Pool NMD::ADDQ__S__PH[2] = {
17229     { instruction         , 0                   , 0   , 32,
17230        0xfc0007ff, 0x2000000d, &NMD::ADDQ_PH          , 0,
17231        DSP_                },        /* ADDQ.PH */
17232     { instruction         , 0                   , 0   , 32,
17233        0xfc0007ff, 0x2000040d, &NMD::ADDQ_S_PH        , 0,
17234        DSP_                },        /* ADDQ_S.PH */
17235 };
17236
17237
17238 NMD::Pool NMD::MUL__S__PH[2] = {
17239     { instruction         , 0                   , 0   , 32,
17240        0xfc0007ff, 0x2000002d, &NMD::MUL_PH           , 0,
17241        DSP_                },        /* MUL.PH */
17242     { instruction         , 0                   , 0   , 32,
17243        0xfc0007ff, 0x2000042d, &NMD::MUL_S_PH         , 0,
17244        DSP_                },        /* MUL_S.PH */
17245 };
17246
17247
17248 NMD::Pool NMD::ADDQH__R__PH[2] = {
17249     { instruction         , 0                   , 0   , 32,
17250        0xfc0007ff, 0x2000004d, &NMD::ADDQH_PH         , 0,
17251        DSP_                },        /* ADDQH.PH */
17252     { instruction         , 0                   , 0   , 32,
17253        0xfc0007ff, 0x2000044d, &NMD::ADDQH_R_PH       , 0,
17254        DSP_                },        /* ADDQH_R.PH */
17255 };
17256
17257
17258 NMD::Pool NMD::ADDQH__R__W[2] = {
17259     { instruction         , 0                   , 0   , 32,
17260        0xfc0007ff, 0x2000008d, &NMD::ADDQH_W          , 0,
17261        DSP_                },        /* ADDQH.W */
17262     { instruction         , 0                   , 0   , 32,
17263        0xfc0007ff, 0x2000048d, &NMD::ADDQH_R_W        , 0,
17264        DSP_                },        /* ADDQH_R.W */
17265 };
17266
17267
17268 NMD::Pool NMD::ADDU__S__QB[2] = {
17269     { instruction         , 0                   , 0   , 32,
17270        0xfc0007ff, 0x200000cd, &NMD::ADDU_QB          , 0,
17271        DSP_                },        /* ADDU.QB */
17272     { instruction         , 0                   , 0   , 32,
17273        0xfc0007ff, 0x200004cd, &NMD::ADDU_S_QB        , 0,
17274        DSP_                },        /* ADDU_S.QB */
17275 };
17276
17277
17278 NMD::Pool NMD::ADDU__S__PH[2] = {
17279     { instruction         , 0                   , 0   , 32,
17280        0xfc0007ff, 0x2000010d, &NMD::ADDU_PH          , 0,
17281        DSP_                },        /* ADDU.PH */
17282     { instruction         , 0                   , 0   , 32,
17283        0xfc0007ff, 0x2000050d, &NMD::ADDU_S_PH        , 0,
17284        DSP_                },        /* ADDU_S.PH */
17285 };
17286
17287
17288 NMD::Pool NMD::ADDUH__R__QB[2] = {
17289     { instruction         , 0                   , 0   , 32,
17290        0xfc0007ff, 0x2000014d, &NMD::ADDUH_QB         , 0,
17291        DSP_                },        /* ADDUH.QB */
17292     { instruction         , 0                   , 0   , 32,
17293        0xfc0007ff, 0x2000054d, &NMD::ADDUH_R_QB       , 0,
17294        DSP_                },        /* ADDUH_R.QB */
17295 };
17296
17297
17298 NMD::Pool NMD::SHRAV__R__PH[2] = {
17299     { instruction         , 0                   , 0   , 32,
17300        0xfc0007ff, 0x2000018d, &NMD::SHRAV_PH         , 0,
17301        DSP_                },        /* SHRAV.PH */
17302     { instruction         , 0                   , 0   , 32,
17303        0xfc0007ff, 0x2000058d, &NMD::SHRAV_R_PH       , 0,
17304        DSP_                },        /* SHRAV_R.PH */
17305 };
17306
17307
17308 NMD::Pool NMD::SHRAV__R__QB[2] = {
17309     { instruction         , 0                   , 0   , 32,
17310        0xfc0007ff, 0x200001cd, &NMD::SHRAV_QB         , 0,
17311        DSP_                },        /* SHRAV.QB */
17312     { instruction         , 0                   , 0   , 32,
17313        0xfc0007ff, 0x200005cd, &NMD::SHRAV_R_QB       , 0,
17314        DSP_                },        /* SHRAV_R.QB */
17315 };
17316
17317
17318 NMD::Pool NMD::SUBQ__S__PH[2] = {
17319     { instruction         , 0                   , 0   , 32,
17320        0xfc0007ff, 0x2000020d, &NMD::SUBQ_PH          , 0,
17321        DSP_                },        /* SUBQ.PH */
17322     { instruction         , 0                   , 0   , 32,
17323        0xfc0007ff, 0x2000060d, &NMD::SUBQ_S_PH        , 0,
17324        DSP_                },        /* SUBQ_S.PH */
17325 };
17326
17327
17328 NMD::Pool NMD::SUBQH__R__PH[2] = {
17329     { instruction         , 0                   , 0   , 32,
17330        0xfc0007ff, 0x2000024d, &NMD::SUBQH_PH         , 0,
17331        DSP_                },        /* SUBQH.PH */
17332     { instruction         , 0                   , 0   , 32,
17333        0xfc0007ff, 0x2000064d, &NMD::SUBQH_R_PH       , 0,
17334        DSP_                },        /* SUBQH_R.PH */
17335 };
17336
17337
17338 NMD::Pool NMD::SUBQH__R__W[2] = {
17339     { instruction         , 0                   , 0   , 32,
17340        0xfc0007ff, 0x2000028d, &NMD::SUBQH_W          , 0,
17341        DSP_                },        /* SUBQH.W */
17342     { instruction         , 0                   , 0   , 32,
17343        0xfc0007ff, 0x2000068d, &NMD::SUBQH_R_W        , 0,
17344        DSP_                },        /* SUBQH_R.W */
17345 };
17346
17347
17348 NMD::Pool NMD::SUBU__S__QB[2] = {
17349     { instruction         , 0                   , 0   , 32,
17350        0xfc0007ff, 0x200002cd, &NMD::SUBU_QB          , 0,
17351        DSP_                },        /* SUBU.QB */
17352     { instruction         , 0                   , 0   , 32,
17353        0xfc0007ff, 0x200006cd, &NMD::SUBU_S_QB        , 0,
17354        DSP_                },        /* SUBU_S.QB */
17355 };
17356
17357
17358 NMD::Pool NMD::SUBU__S__PH[2] = {
17359     { instruction         , 0                   , 0   , 32,
17360        0xfc0007ff, 0x2000030d, &NMD::SUBU_PH          , 0,
17361        DSP_                },        /* SUBU.PH */
17362     { instruction         , 0                   , 0   , 32,
17363        0xfc0007ff, 0x2000070d, &NMD::SUBU_S_PH        , 0,
17364        DSP_                },        /* SUBU_S.PH */
17365 };
17366
17367
17368 NMD::Pool NMD::SHRA__R__PH[2] = {
17369     { instruction         , 0                   , 0   , 32,
17370        0xfc0007ff, 0x20000335, &NMD::SHRA_PH          , 0,
17371        DSP_                },        /* SHRA.PH */
17372     { instruction         , 0                   , 0   , 32,
17373        0xfc0007ff, 0x20000735, &NMD::SHRA_R_PH        , 0,
17374        DSP_                },        /* SHRA_R.PH */
17375 };
17376
17377
17378 NMD::Pool NMD::SUBUH__R__QB[2] = {
17379     { instruction         , 0                   , 0   , 32,
17380        0xfc0007ff, 0x2000034d, &NMD::SUBUH_QB         , 0,
17381        DSP_                },        /* SUBUH.QB */
17382     { instruction         , 0                   , 0   , 32,
17383        0xfc0007ff, 0x2000074d, &NMD::SUBUH_R_QB       , 0,
17384        DSP_                },        /* SUBUH_R.QB */
17385 };
17386
17387
17388 NMD::Pool NMD::SHLLV__S__PH[2] = {
17389     { instruction         , 0                   , 0   , 32,
17390        0xfc0007ff, 0x2000038d, &NMD::SHLLV_PH         , 0,
17391        DSP_                },        /* SHLLV.PH */
17392     { instruction         , 0                   , 0   , 32,
17393        0xfc0007ff, 0x2000078d, &NMD::SHLLV_S_PH       , 0,
17394        DSP_                },        /* SHLLV_S.PH */
17395 };
17396
17397
17398 NMD::Pool NMD::SHLL__S__PH[4] = {
17399     { instruction         , 0                   , 0   , 32,
17400        0xfc000fff, 0x200003b5, &NMD::SHLL_PH          , 0,
17401        DSP_                },        /* SHLL.PH */
17402     { reserved_block      , 0                   , 0   , 32,
17403        0xfc000fff, 0x200007b5, 0                      , 0,
17404        0x0                 },        /* SHLL[_S].PH~*(1) */
17405     { instruction         , 0                   , 0   , 32,
17406        0xfc000fff, 0x20000bb5, &NMD::SHLL_S_PH        , 0,
17407        DSP_                },        /* SHLL_S.PH */
17408     { reserved_block      , 0                   , 0   , 32,
17409        0xfc000fff, 0x20000fb5, 0                      , 0,
17410        0x0                 },        /* SHLL[_S].PH~*(3) */
17411 };
17412
17413
17414 NMD::Pool NMD::PRECR_SRA__R__PH_W[2] = {
17415     { instruction         , 0                   , 0   , 32,
17416        0xfc0007ff, 0x200003cd, &NMD::PRECR_SRA_PH_W   , 0,
17417        DSP_                },        /* PRECR_SRA.PH.W */
17418     { instruction         , 0                   , 0   , 32,
17419        0xfc0007ff, 0x200007cd, &NMD::PRECR_SRA_R_PH_W , 0,
17420        DSP_                },        /* PRECR_SRA_R.PH.W */
17421 };
17422
17423
17424 NMD::Pool NMD::_POOL32A5[128] = {
17425     { instruction         , 0                   , 0   , 32,
17426        0xfc0003ff, 0x20000005, &NMD::CMP_EQ_PH        , 0,
17427        DSP_                },        /* CMP.EQ.PH */
17428     { pool                , ADDQ__S__PH         , 2   , 32,
17429        0xfc0003ff, 0x2000000d, 0                      , 0,
17430        0x0                 },        /* ADDQ[_S].PH */
17431     { reserved_block      , 0                   , 0   , 32,
17432        0xfc0003ff, 0x20000015, 0                      , 0,
17433        0x0                 },        /* _POOL32A5~*(2) */
17434     { instruction         , 0                   , 0   , 32,
17435        0xfc0003ff, 0x2000001d, &NMD::SHILO            , 0,
17436        DSP_                },        /* SHILO */
17437     { instruction         , 0                   , 0   , 32,
17438        0xfc0003ff, 0x20000025, &NMD::MULEQ_S_W_PHL    , 0,
17439        DSP_                },        /* MULEQ_S.W.PHL */
17440     { pool                , MUL__S__PH          , 2   , 32,
17441        0xfc0003ff, 0x2000002d, 0                      , 0,
17442        0x0                 },        /* MUL[_S].PH */
17443     { reserved_block      , 0                   , 0   , 32,
17444        0xfc0003ff, 0x20000035, 0                      , 0,
17445        0x0                 },        /* _POOL32A5~*(6) */
17446     { instruction         , 0                   , 0   , 32,
17447        0xfc0003ff, 0x2000003d, &NMD::REPL_PH          , 0,
17448        DSP_                },        /* REPL.PH */
17449     { instruction         , 0                   , 0   , 32,
17450        0xfc0003ff, 0x20000045, &NMD::CMP_LT_PH        , 0,
17451        DSP_                },        /* CMP.LT.PH */
17452     { pool                , ADDQH__R__PH        , 2   , 32,
17453        0xfc0003ff, 0x2000004d, 0                      , 0,
17454        0x0                 },        /* ADDQH[_R].PH */
17455     { reserved_block      , 0                   , 0   , 32,
17456        0xfc0003ff, 0x20000055, 0                      , 0,
17457        0x0                 },        /* _POOL32A5~*(10) */
17458     { reserved_block      , 0                   , 0   , 32,
17459        0xfc0003ff, 0x2000005d, 0                      , 0,
17460        0x0                 },        /* _POOL32A5~*(11) */
17461     { instruction         , 0                   , 0   , 32,
17462        0xfc0003ff, 0x20000065, &NMD::MULEQ_S_W_PHR    , 0,
17463        DSP_                },        /* MULEQ_S.W.PHR */
17464     { instruction         , 0                   , 0   , 32,
17465        0xfc0003ff, 0x2000006d, &NMD::PRECR_QB_PH      , 0,
17466        DSP_                },        /* PRECR.QB.PH */
17467     { reserved_block      , 0                   , 0   , 32,
17468        0xfc0003ff, 0x20000075, 0                      , 0,
17469        0x0                 },        /* _POOL32A5~*(14) */
17470     { reserved_block      , 0                   , 0   , 32,
17471        0xfc0003ff, 0x2000007d, 0                      , 0,
17472        0x0                 },        /* _POOL32A5~*(15) */
17473     { instruction         , 0                   , 0   , 32,
17474        0xfc0003ff, 0x20000085, &NMD::CMP_LE_PH        , 0,
17475        DSP_                },        /* CMP.LE.PH */
17476     { pool                , ADDQH__R__W         , 2   , 32,
17477        0xfc0003ff, 0x2000008d, 0                      , 0,
17478        0x0                 },        /* ADDQH[_R].W */
17479     { instruction         , 0                   , 0   , 32,
17480        0xfc0003ff, 0x20000095, &NMD::MULEU_S_PH_QBL   , 0,
17481        DSP_                },        /* MULEU_S.PH.QBL */
17482     { reserved_block      , 0                   , 0   , 32,
17483        0xfc0003ff, 0x2000009d, 0                      , 0,
17484        0x0                 },        /* _POOL32A5~*(19) */
17485     { reserved_block      , 0                   , 0   , 32,
17486        0xfc0003ff, 0x200000a5, 0                      , 0,
17487        0x0                 },        /* _POOL32A5~*(20) */
17488     { instruction         , 0                   , 0   , 32,
17489        0xfc0003ff, 0x200000ad, &NMD::PRECRQ_QB_PH     , 0,
17490        DSP_                },        /* PRECRQ.QB.PH */
17491     { reserved_block      , 0                   , 0   , 32,
17492        0xfc0003ff, 0x200000b5, 0                      , 0,
17493        0x0                 },        /* _POOL32A5~*(22) */
17494     { reserved_block      , 0                   , 0   , 32,
17495        0xfc0003ff, 0x200000bd, 0                      , 0,
17496        0x0                 },        /* _POOL32A5~*(23) */
17497     { instruction         , 0                   , 0   , 32,
17498        0xfc0003ff, 0x200000c5, &NMD::CMPGU_EQ_QB      , 0,
17499        DSP_                },        /* CMPGU.EQ.QB */
17500     { pool                , ADDU__S__QB         , 2   , 32,
17501        0xfc0003ff, 0x200000cd, 0                      , 0,
17502        0x0                 },        /* ADDU[_S].QB */
17503     { instruction         , 0                   , 0   , 32,
17504        0xfc0003ff, 0x200000d5, &NMD::MULEU_S_PH_QBR   , 0,
17505        DSP_                },        /* MULEU_S.PH.QBR */
17506     { reserved_block      , 0                   , 0   , 32,
17507        0xfc0003ff, 0x200000dd, 0                      , 0,
17508        0x0                 },        /* _POOL32A5~*(27) */
17509     { reserved_block      , 0                   , 0   , 32,
17510        0xfc0003ff, 0x200000e5, 0                      , 0,
17511        0x0                 },        /* _POOL32A5~*(28) */
17512     { instruction         , 0                   , 0   , 32,
17513        0xfc0003ff, 0x200000ed, &NMD::PRECRQ_PH_W      , 0,
17514        DSP_                },        /* PRECRQ.PH.W */
17515     { reserved_block      , 0                   , 0   , 32,
17516        0xfc0003ff, 0x200000f5, 0                      , 0,
17517        0x0                 },        /* _POOL32A5~*(30) */
17518     { reserved_block      , 0                   , 0   , 32,
17519        0xfc0003ff, 0x200000fd, 0                      , 0,
17520        0x0                 },        /* _POOL32A5~*(31) */
17521     { instruction         , 0                   , 0   , 32,
17522        0xfc0003ff, 0x20000105, &NMD::CMPGU_LT_QB      , 0,
17523        DSP_                },        /* CMPGU.LT.QB */
17524     { pool                , ADDU__S__PH         , 2   , 32,
17525        0xfc0003ff, 0x2000010d, 0                      , 0,
17526        0x0                 },        /* ADDU[_S].PH */
17527     { instruction         , 0                   , 0   , 32,
17528        0xfc0003ff, 0x20000115, &NMD::MULQ_RS_PH       , 0,
17529        DSP_                },        /* MULQ_RS.PH */
17530     { reserved_block      , 0                   , 0   , 32,
17531        0xfc0003ff, 0x2000011d, 0                      , 0,
17532        0x0                 },        /* _POOL32A5~*(35) */
17533     { reserved_block      , 0                   , 0   , 32,
17534        0xfc0003ff, 0x20000125, 0                      , 0,
17535        0x0                 },        /* _POOL32A5~*(36) */
17536     { instruction         , 0                   , 0   , 32,
17537        0xfc0003ff, 0x2000012d, &NMD::PRECRQ_RS_PH_W   , 0,
17538        DSP_                },        /* PRECRQ_RS.PH.W */
17539     { reserved_block      , 0                   , 0   , 32,
17540        0xfc0003ff, 0x20000135, 0                      , 0,
17541        0x0                 },        /* _POOL32A5~*(38) */
17542     { reserved_block      , 0                   , 0   , 32,
17543        0xfc0003ff, 0x2000013d, 0                      , 0,
17544        0x0                 },        /* _POOL32A5~*(39) */
17545     { instruction         , 0                   , 0   , 32,
17546        0xfc0003ff, 0x20000145, &NMD::CMPGU_LE_QB      , 0,
17547        DSP_                },        /* CMPGU.LE.QB */
17548     { pool                , ADDUH__R__QB        , 2   , 32,
17549        0xfc0003ff, 0x2000014d, 0                      , 0,
17550        0x0                 },        /* ADDUH[_R].QB */
17551     { instruction         , 0                   , 0   , 32,
17552        0xfc0003ff, 0x20000155, &NMD::MULQ_S_PH        , 0,
17553        DSP_                },        /* MULQ_S.PH */
17554     { reserved_block      , 0                   , 0   , 32,
17555        0xfc0003ff, 0x2000015d, 0                      , 0,
17556        0x0                 },        /* _POOL32A5~*(43) */
17557     { reserved_block      , 0                   , 0   , 32,
17558        0xfc0003ff, 0x20000165, 0                      , 0,
17559        0x0                 },        /* _POOL32A5~*(44) */
17560     { instruction         , 0                   , 0   , 32,
17561        0xfc0003ff, 0x2000016d, &NMD::PRECRQU_S_QB_PH  , 0,
17562        DSP_                },        /* PRECRQU_S.QB.PH */
17563     { reserved_block      , 0                   , 0   , 32,
17564        0xfc0003ff, 0x20000175, 0                      , 0,
17565        0x0                 },        /* _POOL32A5~*(46) */
17566     { reserved_block      , 0                   , 0   , 32,
17567        0xfc0003ff, 0x2000017d, 0                      , 0,
17568        0x0                 },        /* _POOL32A5~*(47) */
17569     { instruction         , 0                   , 0   , 32,
17570        0xfc0003ff, 0x20000185, &NMD::CMPGDU_EQ_QB     , 0,
17571        DSP_                },        /* CMPGDU.EQ.QB */
17572     { pool                , SHRAV__R__PH        , 2   , 32,
17573        0xfc0003ff, 0x2000018d, 0                      , 0,
17574        0x0                 },        /* SHRAV[_R].PH */
17575     { instruction         , 0                   , 0   , 32,
17576        0xfc0003ff, 0x20000195, &NMD::MULQ_RS_W        , 0,
17577        DSP_                },        /* MULQ_RS.W */
17578     { reserved_block      , 0                   , 0   , 32,
17579        0xfc0003ff, 0x2000019d, 0                      , 0,
17580        0x0                 },        /* _POOL32A5~*(51) */
17581     { reserved_block      , 0                   , 0   , 32,
17582        0xfc0003ff, 0x200001a5, 0                      , 0,
17583        0x0                 },        /* _POOL32A5~*(52) */
17584     { instruction         , 0                   , 0   , 32,
17585        0xfc0003ff, 0x200001ad, &NMD::PACKRL_PH        , 0,
17586        DSP_                },        /* PACKRL.PH */
17587     { reserved_block      , 0                   , 0   , 32,
17588        0xfc0003ff, 0x200001b5, 0                      , 0,
17589        0x0                 },        /* _POOL32A5~*(54) */
17590     { reserved_block      , 0                   , 0   , 32,
17591        0xfc0003ff, 0x200001bd, 0                      , 0,
17592        0x0                 },        /* _POOL32A5~*(55) */
17593     { instruction         , 0                   , 0   , 32,
17594        0xfc0003ff, 0x200001c5, &NMD::CMPGDU_LT_QB     , 0,
17595        DSP_                },        /* CMPGDU.LT.QB */
17596     { pool                , SHRAV__R__QB        , 2   , 32,
17597        0xfc0003ff, 0x200001cd, 0                      , 0,
17598        0x0                 },        /* SHRAV[_R].QB */
17599     { instruction         , 0                   , 0   , 32,
17600        0xfc0003ff, 0x200001d5, &NMD::MULQ_S_W         , 0,
17601        DSP_                },        /* MULQ_S.W */
17602     { reserved_block      , 0                   , 0   , 32,
17603        0xfc0003ff, 0x200001dd, 0                      , 0,
17604        0x0                 },        /* _POOL32A5~*(59) */
17605     { reserved_block      , 0                   , 0   , 32,
17606        0xfc0003ff, 0x200001e5, 0                      , 0,
17607        0x0                 },        /* _POOL32A5~*(60) */
17608     { instruction         , 0                   , 0   , 32,
17609        0xfc0003ff, 0x200001ed, &NMD::PICK_QB          , 0,
17610        DSP_                },        /* PICK.QB */
17611     { reserved_block      , 0                   , 0   , 32,
17612        0xfc0003ff, 0x200001f5, 0                      , 0,
17613        0x0                 },        /* _POOL32A5~*(62) */
17614     { reserved_block      , 0                   , 0   , 32,
17615        0xfc0003ff, 0x200001fd, 0                      , 0,
17616        0x0                 },        /* _POOL32A5~*(63) */
17617     { instruction         , 0                   , 0   , 32,
17618        0xfc0003ff, 0x20000205, &NMD::CMPGDU_LE_QB     , 0,
17619        DSP_                },        /* CMPGDU.LE.QB */
17620     { pool                , SUBQ__S__PH         , 2   , 32,
17621        0xfc0003ff, 0x2000020d, 0                      , 0,
17622        0x0                 },        /* SUBQ[_S].PH */
17623     { instruction         , 0                   , 0   , 32,
17624        0xfc0003ff, 0x20000215, &NMD::APPEND           , 0,
17625        DSP_                },        /* APPEND */
17626     { reserved_block      , 0                   , 0   , 32,
17627        0xfc0003ff, 0x2000021d, 0                      , 0,
17628        0x0                 },        /* _POOL32A5~*(67) */
17629     { reserved_block      , 0                   , 0   , 32,
17630        0xfc0003ff, 0x20000225, 0                      , 0,
17631        0x0                 },        /* _POOL32A5~*(68) */
17632     { instruction         , 0                   , 0   , 32,
17633        0xfc0003ff, 0x2000022d, &NMD::PICK_PH          , 0,
17634        DSP_                },        /* PICK.PH */
17635     { reserved_block      , 0                   , 0   , 32,
17636        0xfc0003ff, 0x20000235, 0                      , 0,
17637        0x0                 },        /* _POOL32A5~*(70) */
17638     { reserved_block      , 0                   , 0   , 32,
17639        0xfc0003ff, 0x2000023d, 0                      , 0,
17640        0x0                 },        /* _POOL32A5~*(71) */
17641     { instruction         , 0                   , 0   , 32,
17642        0xfc0003ff, 0x20000245, &NMD::CMPU_EQ_QB       , 0,
17643        DSP_                },        /* CMPU.EQ.QB */
17644     { pool                , SUBQH__R__PH        , 2   , 32,
17645        0xfc0003ff, 0x2000024d, 0                      , 0,
17646        0x0                 },        /* SUBQH[_R].PH */
17647     { instruction         , 0                   , 0   , 32,
17648        0xfc0003ff, 0x20000255, &NMD::PREPEND          , 0,
17649        DSP_                },        /* PREPEND */
17650     { reserved_block      , 0                   , 0   , 32,
17651        0xfc0003ff, 0x2000025d, 0                      , 0,
17652        0x0                 },        /* _POOL32A5~*(75) */
17653     { reserved_block      , 0                   , 0   , 32,
17654        0xfc0003ff, 0x20000265, 0                      , 0,
17655        0x0                 },        /* _POOL32A5~*(76) */
17656     { reserved_block      , 0                   , 0   , 32,
17657        0xfc0003ff, 0x2000026d, 0                      , 0,
17658        0x0                 },        /* _POOL32A5~*(77) */
17659     { reserved_block      , 0                   , 0   , 32,
17660        0xfc0003ff, 0x20000275, 0                      , 0,
17661        0x0                 },        /* _POOL32A5~*(78) */
17662     { reserved_block      , 0                   , 0   , 32,
17663        0xfc0003ff, 0x2000027d, 0                      , 0,
17664        0x0                 },        /* _POOL32A5~*(79) */
17665     { instruction         , 0                   , 0   , 32,
17666        0xfc0003ff, 0x20000285, &NMD::CMPU_LT_QB       , 0,
17667        DSP_                },        /* CMPU.LT.QB */
17668     { pool                , SUBQH__R__W         , 2   , 32,
17669        0xfc0003ff, 0x2000028d, 0                      , 0,
17670        0x0                 },        /* SUBQH[_R].W */
17671     { instruction         , 0                   , 0   , 32,
17672        0xfc0003ff, 0x20000295, &NMD::MODSUB           , 0,
17673        DSP_                },        /* MODSUB */
17674     { reserved_block      , 0                   , 0   , 32,
17675        0xfc0003ff, 0x2000029d, 0                      , 0,
17676        0x0                 },        /* _POOL32A5~*(83) */
17677     { reserved_block      , 0                   , 0   , 32,
17678        0xfc0003ff, 0x200002a5, 0                      , 0,
17679        0x0                 },        /* _POOL32A5~*(84) */
17680     { reserved_block      , 0                   , 0   , 32,
17681        0xfc0003ff, 0x200002ad, 0                      , 0,
17682        0x0                 },        /* _POOL32A5~*(85) */
17683     { reserved_block      , 0                   , 0   , 32,
17684        0xfc0003ff, 0x200002b5, 0                      , 0,
17685        0x0                 },        /* _POOL32A5~*(86) */
17686     { reserved_block      , 0                   , 0   , 32,
17687        0xfc0003ff, 0x200002bd, 0                      , 0,
17688        0x0                 },        /* _POOL32A5~*(87) */
17689     { instruction         , 0                   , 0   , 32,
17690        0xfc0003ff, 0x200002c5, &NMD::CMPU_LE_QB       , 0,
17691        DSP_                },        /* CMPU.LE.QB */
17692     { pool                , SUBU__S__QB         , 2   , 32,
17693        0xfc0003ff, 0x200002cd, 0                      , 0,
17694        0x0                 },        /* SUBU[_S].QB */
17695     { instruction         , 0                   , 0   , 32,
17696        0xfc0003ff, 0x200002d5, &NMD::SHRAV_R_W        , 0,
17697        DSP_                },        /* SHRAV_R.W */
17698     { reserved_block      , 0                   , 0   , 32,
17699        0xfc0003ff, 0x200002dd, 0                      , 0,
17700        0x0                 },        /* _POOL32A5~*(91) */
17701     { reserved_block      , 0                   , 0   , 32,
17702        0xfc0003ff, 0x200002e5, 0                      , 0,
17703        0x0                 },        /* _POOL32A5~*(92) */
17704     { reserved_block      , 0                   , 0   , 32,
17705        0xfc0003ff, 0x200002ed, 0                      , 0,
17706        0x0                 },        /* _POOL32A5~*(93) */
17707     { instruction         , 0                   , 0   , 32,
17708        0xfc0003ff, 0x200002f5, &NMD::SHRA_R_W         , 0,
17709        DSP_                },        /* SHRA_R.W */
17710     { reserved_block      , 0                   , 0   , 32,
17711        0xfc0003ff, 0x200002fd, 0                      , 0,
17712        0x0                 },        /* _POOL32A5~*(95) */
17713     { instruction         , 0                   , 0   , 32,
17714        0xfc0003ff, 0x20000305, &NMD::ADDQ_S_W         , 0,
17715        DSP_                },        /* ADDQ_S.W */
17716     { pool                , SUBU__S__PH         , 2   , 32,
17717        0xfc0003ff, 0x2000030d, 0                      , 0,
17718        0x0                 },        /* SUBU[_S].PH */
17719     { instruction         , 0                   , 0   , 32,
17720        0xfc0003ff, 0x20000315, &NMD::SHRLV_PH         , 0,
17721        DSP_                },        /* SHRLV.PH */
17722     { reserved_block      , 0                   , 0   , 32,
17723        0xfc0003ff, 0x2000031d, 0                      , 0,
17724        0x0                 },        /* _POOL32A5~*(99) */
17725     { reserved_block      , 0                   , 0   , 32,
17726        0xfc0003ff, 0x20000325, 0                      , 0,
17727        0x0                 },        /* _POOL32A5~*(100) */
17728     { reserved_block      , 0                   , 0   , 32,
17729        0xfc0003ff, 0x2000032d, 0                      , 0,
17730        0x0                 },        /* _POOL32A5~*(101) */
17731     { pool                , SHRA__R__PH         , 2   , 32,
17732        0xfc0003ff, 0x20000335, 0                      , 0,
17733        0x0                 },        /* SHRA[_R].PH */
17734     { reserved_block      , 0                   , 0   , 32,
17735        0xfc0003ff, 0x2000033d, 0                      , 0,
17736        0x0                 },        /* _POOL32A5~*(103) */
17737     { instruction         , 0                   , 0   , 32,
17738        0xfc0003ff, 0x20000345, &NMD::SUBQ_S_W         , 0,
17739        DSP_                },        /* SUBQ_S.W */
17740     { pool                , SUBUH__R__QB        , 2   , 32,
17741        0xfc0003ff, 0x2000034d, 0                      , 0,
17742        0x0                 },        /* SUBUH[_R].QB */
17743     { instruction         , 0                   , 0   , 32,
17744        0xfc0003ff, 0x20000355, &NMD::SHRLV_QB         , 0,
17745        DSP_                },        /* SHRLV.QB */
17746     { reserved_block      , 0                   , 0   , 32,
17747        0xfc0003ff, 0x2000035d, 0                      , 0,
17748        0x0                 },        /* _POOL32A5~*(107) */
17749     { reserved_block      , 0                   , 0   , 32,
17750        0xfc0003ff, 0x20000365, 0                      , 0,
17751        0x0                 },        /* _POOL32A5~*(108) */
17752     { reserved_block      , 0                   , 0   , 32,
17753        0xfc0003ff, 0x2000036d, 0                      , 0,
17754        0x0                 },        /* _POOL32A5~*(109) */
17755     { reserved_block      , 0                   , 0   , 32,
17756        0xfc0003ff, 0x20000375, 0                      , 0,
17757        0x0                 },        /* _POOL32A5~*(110) */
17758     { reserved_block      , 0                   , 0   , 32,
17759        0xfc0003ff, 0x2000037d, 0                      , 0,
17760        0x0                 },        /* _POOL32A5~*(111) */
17761     { instruction         , 0                   , 0   , 32,
17762        0xfc0003ff, 0x20000385, &NMD::ADDSC            , 0,
17763        DSP_                },        /* ADDSC */
17764     { pool                , SHLLV__S__PH        , 2   , 32,
17765        0xfc0003ff, 0x2000038d, 0                      , 0,
17766        0x0                 },        /* SHLLV[_S].PH */
17767     { instruction         , 0                   , 0   , 32,
17768        0xfc0003ff, 0x20000395, &NMD::SHLLV_QB         , 0,
17769        DSP_                },        /* SHLLV.QB */
17770     { reserved_block      , 0                   , 0   , 32,
17771        0xfc0003ff, 0x2000039d, 0                      , 0,
17772        0x0                 },        /* _POOL32A5~*(115) */
17773     { reserved_block      , 0                   , 0   , 32,
17774        0xfc0003ff, 0x200003a5, 0                      , 0,
17775        0x0                 },        /* _POOL32A5~*(116) */
17776     { reserved_block      , 0                   , 0   , 32,
17777        0xfc0003ff, 0x200003ad, 0                      , 0,
17778        0x0                 },        /* _POOL32A5~*(117) */
17779     { pool                , SHLL__S__PH         , 4   , 32,
17780        0xfc0003ff, 0x200003b5, 0                      , 0,
17781        0x0                 },        /* SHLL[_S].PH */
17782     { reserved_block      , 0                   , 0   , 32,
17783        0xfc0003ff, 0x200003bd, 0                      , 0,
17784        0x0                 },        /* _POOL32A5~*(119) */
17785     { instruction         , 0                   , 0   , 32,
17786        0xfc0003ff, 0x200003c5, &NMD::ADDWC            , 0,
17787        DSP_                },        /* ADDWC */
17788     { pool                , PRECR_SRA__R__PH_W  , 2   , 32,
17789        0xfc0003ff, 0x200003cd, 0                      , 0,
17790        0x0                 },        /* PRECR_SRA[_R].PH.W */
17791     { instruction         , 0                   , 0   , 32,
17792        0xfc0003ff, 0x200003d5, &NMD::SHLLV_S_W        , 0,
17793        DSP_                },        /* SHLLV_S.W */
17794     { reserved_block      , 0                   , 0   , 32,
17795        0xfc0003ff, 0x200003dd, 0                      , 0,
17796        0x0                 },        /* _POOL32A5~*(123) */
17797     { reserved_block      , 0                   , 0   , 32,
17798        0xfc0003ff, 0x200003e5, 0                      , 0,
17799        0x0                 },        /* _POOL32A5~*(124) */
17800     { reserved_block      , 0                   , 0   , 32,
17801        0xfc0003ff, 0x200003ed, 0                      , 0,
17802        0x0                 },        /* _POOL32A5~*(125) */
17803     { instruction         , 0                   , 0   , 32,
17804        0xfc0003ff, 0x200003f5, &NMD::SHLL_S_W         , 0,
17805        DSP_                },        /* SHLL_S.W */
17806     { reserved_block      , 0                   , 0   , 32,
17807        0xfc0003ff, 0x200003fd, 0                      , 0,
17808        0x0                 },        /* _POOL32A5~*(127) */
17809 };
17810
17811
17812 NMD::Pool NMD::PP_LSX[16] = {
17813     { instruction         , 0                   , 0   , 32,
17814        0xfc0007ff, 0x20000007, &NMD::LBX              , 0,
17815        0x0                 },        /* LBX */
17816     { instruction         , 0                   , 0   , 32,
17817        0xfc0007ff, 0x20000087, &NMD::SBX              , 0,
17818        XMMS_               },        /* SBX */
17819     { instruction         , 0                   , 0   , 32,
17820        0xfc0007ff, 0x20000107, &NMD::LBUX             , 0,
17821        0x0                 },        /* LBUX */
17822     { reserved_block      , 0                   , 0   , 32,
17823        0xfc0007ff, 0x20000187, 0                      , 0,
17824        0x0                 },        /* PP.LSX~*(3) */
17825     { instruction         , 0                   , 0   , 32,
17826        0xfc0007ff, 0x20000207, &NMD::LHX              , 0,
17827        0x0                 },        /* LHX */
17828     { instruction         , 0                   , 0   , 32,
17829        0xfc0007ff, 0x20000287, &NMD::SHX              , 0,
17830        XMMS_               },        /* SHX */
17831     { instruction         , 0                   , 0   , 32,
17832        0xfc0007ff, 0x20000307, &NMD::LHUX             , 0,
17833        0x0                 },        /* LHUX */
17834     { instruction         , 0                   , 0   , 32,
17835        0xfc0007ff, 0x20000387, &NMD::LWUX             , 0,
17836        MIPS64_             },        /* LWUX */
17837     { instruction         , 0                   , 0   , 32,
17838        0xfc0007ff, 0x20000407, &NMD::LWX              , 0,
17839        0x0                 },        /* LWX */
17840     { instruction         , 0                   , 0   , 32,
17841        0xfc0007ff, 0x20000487, &NMD::SWX              , 0,
17842        XMMS_               },        /* SWX */
17843     { instruction         , 0                   , 0   , 32,
17844        0xfc0007ff, 0x20000507, &NMD::LWC1X            , 0,
17845        CP1_                },        /* LWC1X */
17846     { instruction         , 0                   , 0   , 32,
17847        0xfc0007ff, 0x20000587, &NMD::SWC1X            , 0,
17848        CP1_                },        /* SWC1X */
17849     { instruction         , 0                   , 0   , 32,
17850        0xfc0007ff, 0x20000607, &NMD::LDX              , 0,
17851        MIPS64_             },        /* LDX */
17852     { instruction         , 0                   , 0   , 32,
17853        0xfc0007ff, 0x20000687, &NMD::SDX              , 0,
17854        MIPS64_             },        /* SDX */
17855     { instruction         , 0                   , 0   , 32,
17856        0xfc0007ff, 0x20000707, &NMD::LDC1X            , 0,
17857        CP1_                },        /* LDC1X */
17858     { instruction         , 0                   , 0   , 32,
17859        0xfc0007ff, 0x20000787, &NMD::SDC1X            , 0,
17860        CP1_                },        /* SDC1X */
17861 };
17862
17863
17864 NMD::Pool NMD::PP_LSXS[16] = {
17865     { reserved_block      , 0                   , 0   , 32,
17866        0xfc0007ff, 0x20000047, 0                      , 0,
17867        0x0                 },        /* PP.LSXS~*(0) */
17868     { reserved_block      , 0                   , 0   , 32,
17869        0xfc0007ff, 0x200000c7, 0                      , 0,
17870        0x0                 },        /* PP.LSXS~*(1) */
17871     { reserved_block      , 0                   , 0   , 32,
17872        0xfc0007ff, 0x20000147, 0                      , 0,
17873        0x0                 },        /* PP.LSXS~*(2) */
17874     { reserved_block      , 0                   , 0   , 32,
17875        0xfc0007ff, 0x200001c7, 0                      , 0,
17876        0x0                 },        /* PP.LSXS~*(3) */
17877     { instruction         , 0                   , 0   , 32,
17878        0xfc0007ff, 0x20000247, &NMD::LHXS             , 0,
17879        0x0                 },        /* LHXS */
17880     { instruction         , 0                   , 0   , 32,
17881        0xfc0007ff, 0x200002c7, &NMD::SHXS             , 0,
17882        XMMS_               },        /* SHXS */
17883     { instruction         , 0                   , 0   , 32,
17884        0xfc0007ff, 0x20000347, &NMD::LHUXS            , 0,
17885        0x0                 },        /* LHUXS */
17886     { instruction         , 0                   , 0   , 32,
17887        0xfc0007ff, 0x200003c7, &NMD::LWUXS            , 0,
17888        MIPS64_             },        /* LWUXS */
17889     { instruction         , 0                   , 0   , 32,
17890        0xfc0007ff, 0x20000447, &NMD::LWXS_32_         , 0,
17891        0x0                 },        /* LWXS[32] */
17892     { instruction         , 0                   , 0   , 32,
17893        0xfc0007ff, 0x200004c7, &NMD::SWXS             , 0,
17894        XMMS_               },        /* SWXS */
17895     { instruction         , 0                   , 0   , 32,
17896        0xfc0007ff, 0x20000547, &NMD::LWC1XS           , 0,
17897        CP1_                },        /* LWC1XS */
17898     { instruction         , 0                   , 0   , 32,
17899        0xfc0007ff, 0x200005c7, &NMD::SWC1XS           , 0,
17900        CP1_                },        /* SWC1XS */
17901     { instruction         , 0                   , 0   , 32,
17902        0xfc0007ff, 0x20000647, &NMD::LDXS             , 0,
17903        MIPS64_             },        /* LDXS */
17904     { instruction         , 0                   , 0   , 32,
17905        0xfc0007ff, 0x200006c7, &NMD::SDXS             , 0,
17906        MIPS64_             },        /* SDXS */
17907     { instruction         , 0                   , 0   , 32,
17908        0xfc0007ff, 0x20000747, &NMD::LDC1XS           , 0,
17909        CP1_                },        /* LDC1XS */
17910     { instruction         , 0                   , 0   , 32,
17911        0xfc0007ff, 0x200007c7, &NMD::SDC1XS           , 0,
17912        CP1_                },        /* SDC1XS */
17913 };
17914
17915
17916 NMD::Pool NMD::P_LSX[2] = {
17917     { pool                , PP_LSX              , 16  , 32,
17918        0xfc00007f, 0x20000007, 0                      , 0,
17919        0x0                 },        /* PP.LSX */
17920     { pool                , PP_LSXS             , 16  , 32,
17921        0xfc00007f, 0x20000047, 0                      , 0,
17922        0x0                 },        /* PP.LSXS */
17923 };
17924
17925
17926 NMD::Pool NMD::POOL32Axf_1_0[4] = {
17927     { instruction         , 0                   , 0   , 32,
17928        0xfc003fff, 0x2000007f, &NMD::MFHI_DSP_        , 0,
17929        DSP_                },        /* MFHI[DSP] */
17930     { instruction         , 0                   , 0   , 32,
17931        0xfc003fff, 0x2000107f, &NMD::MFLO_DSP_        , 0,
17932        DSP_                },        /* MFLO[DSP] */
17933     { instruction         , 0                   , 0   , 32,
17934        0xfc003fff, 0x2000207f, &NMD::MTHI_DSP_        , 0,
17935        DSP_                },        /* MTHI[DSP] */
17936     { instruction         , 0                   , 0   , 32,
17937        0xfc003fff, 0x2000307f, &NMD::MTLO_DSP_        , 0,
17938        DSP_                },        /* MTLO[DSP] */
17939 };
17940
17941
17942 NMD::Pool NMD::POOL32Axf_1_1[4] = {
17943     { instruction         , 0                   , 0   , 32,
17944        0xfc003fff, 0x2000027f, &NMD::MTHLIP           , 0,
17945        DSP_                },        /* MTHLIP */
17946     { instruction         , 0                   , 0   , 32,
17947        0xfc003fff, 0x2000127f, &NMD::SHILOV           , 0,
17948        DSP_                },        /* SHILOV */
17949     { reserved_block      , 0                   , 0   , 32,
17950        0xfc003fff, 0x2000227f, 0                      , 0,
17951        0x0                 },        /* POOL32Axf_1_1~*(2) */
17952     { reserved_block      , 0                   , 0   , 32,
17953        0xfc003fff, 0x2000327f, 0                      , 0,
17954        0x0                 },        /* POOL32Axf_1_1~*(3) */
17955 };
17956
17957
17958 NMD::Pool NMD::POOL32Axf_1_3[4] = {
17959     { instruction         , 0                   , 0   , 32,
17960        0xfc003fff, 0x2000067f, &NMD::RDDSP            , 0,
17961        DSP_                },        /* RDDSP */
17962     { instruction         , 0                   , 0   , 32,
17963        0xfc003fff, 0x2000167f, &NMD::WRDSP            , 0,
17964        DSP_                },        /* WRDSP */
17965     { instruction         , 0                   , 0   , 32,
17966        0xfc003fff, 0x2000267f, &NMD::EXTP             , 0,
17967        DSP_                },        /* EXTP */
17968     { instruction         , 0                   , 0   , 32,
17969        0xfc003fff, 0x2000367f, &NMD::EXTPDP           , 0,
17970        DSP_                },        /* EXTPDP */
17971 };
17972
17973
17974 NMD::Pool NMD::POOL32Axf_1_4[2] = {
17975     { instruction         , 0                   , 0   , 32,
17976        0xfc001fff, 0x2000087f, &NMD::SHLL_QB          , 0,
17977        DSP_                },        /* SHLL.QB */
17978     { instruction         , 0                   , 0   , 32,
17979        0xfc001fff, 0x2000187f, &NMD::SHRL_QB          , 0,
17980        DSP_                },        /* SHRL.QB */
17981 };
17982
17983
17984 NMD::Pool NMD::MAQ_S_A__W_PHR[2] = {
17985     { instruction         , 0                   , 0   , 32,
17986        0xfc003fff, 0x20000a7f, &NMD::MAQ_S_W_PHR      , 0,
17987        DSP_                },        /* MAQ_S.W.PHR */
17988     { instruction         , 0                   , 0   , 32,
17989        0xfc003fff, 0x20002a7f, &NMD::MAQ_SA_W_PHR     , 0,
17990        DSP_                },        /* MAQ_SA.W.PHR */
17991 };
17992
17993
17994 NMD::Pool NMD::MAQ_S_A__W_PHL[2] = {
17995     { instruction         , 0                   , 0   , 32,
17996        0xfc003fff, 0x20001a7f, &NMD::MAQ_S_W_PHL      , 0,
17997        DSP_                },        /* MAQ_S.W.PHL */
17998     { instruction         , 0                   , 0   , 32,
17999        0xfc003fff, 0x20003a7f, &NMD::MAQ_SA_W_PHL     , 0,
18000        DSP_                },        /* MAQ_SA.W.PHL */
18001 };
18002
18003
18004 NMD::Pool NMD::POOL32Axf_1_5[2] = {
18005     { pool                , MAQ_S_A__W_PHR      , 2   , 32,
18006        0xfc001fff, 0x20000a7f, 0                      , 0,
18007        0x0                 },        /* MAQ_S[A].W.PHR */
18008     { pool                , MAQ_S_A__W_PHL      , 2   , 32,
18009        0xfc001fff, 0x20001a7f, 0                      , 0,
18010        0x0                 },        /* MAQ_S[A].W.PHL */
18011 };
18012
18013
18014 NMD::Pool NMD::POOL32Axf_1_7[4] = {
18015     { instruction         , 0                   , 0   , 32,
18016        0xfc003fff, 0x20000e7f, &NMD::EXTR_W           , 0,
18017        DSP_                },        /* EXTR.W */
18018     { instruction         , 0                   , 0   , 32,
18019        0xfc003fff, 0x20001e7f, &NMD::EXTR_R_W         , 0,
18020        DSP_                },        /* EXTR_R.W */
18021     { instruction         , 0                   , 0   , 32,
18022        0xfc003fff, 0x20002e7f, &NMD::EXTR_RS_W        , 0,
18023        DSP_                },        /* EXTR_RS.W */
18024     { instruction         , 0                   , 0   , 32,
18025        0xfc003fff, 0x20003e7f, &NMD::EXTR_S_H         , 0,
18026        DSP_                },        /* EXTR_S.H */
18027 };
18028
18029
18030 NMD::Pool NMD::POOL32Axf_1[8] = {
18031     { pool                , POOL32Axf_1_0       , 4   , 32,
18032        0xfc000fff, 0x2000007f, 0                      , 0,
18033        0x0                 },        /* POOL32Axf_1_0 */
18034     { pool                , POOL32Axf_1_1       , 4   , 32,
18035        0xfc000fff, 0x2000027f, 0                      , 0,
18036        0x0                 },        /* POOL32Axf_1_1 */
18037     { reserved_block      , 0                   , 0   , 32,
18038        0xfc000fff, 0x2000047f, 0                      , 0,
18039        0x0                 },        /* POOL32Axf_1~*(2) */
18040     { pool                , POOL32Axf_1_3       , 4   , 32,
18041        0xfc000fff, 0x2000067f, 0                      , 0,
18042        0x0                 },        /* POOL32Axf_1_3 */
18043     { pool                , POOL32Axf_1_4       , 2   , 32,
18044        0xfc000fff, 0x2000087f, 0                      , 0,
18045        0x0                 },        /* POOL32Axf_1_4 */
18046     { pool                , POOL32Axf_1_5       , 2   , 32,
18047        0xfc000fff, 0x20000a7f, 0                      , 0,
18048        0x0                 },        /* POOL32Axf_1_5 */
18049     { reserved_block      , 0                   , 0   , 32,
18050        0xfc000fff, 0x20000c7f, 0                      , 0,
18051        0x0                 },        /* POOL32Axf_1~*(6) */
18052     { pool                , POOL32Axf_1_7       , 4   , 32,
18053        0xfc000fff, 0x20000e7f, 0                      , 0,
18054        0x0                 },        /* POOL32Axf_1_7 */
18055 };
18056
18057
18058 NMD::Pool NMD::POOL32Axf_2_DSP__0_7[8] = {
18059     { instruction         , 0                   , 0   , 32,
18060        0xfc003fff, 0x200000bf, &NMD::DPA_W_PH         , 0,
18061        DSP_                },        /* DPA.W.PH */
18062     { instruction         , 0                   , 0   , 32,
18063        0xfc003fff, 0x200002bf, &NMD::DPAQ_S_W_PH      , 0,
18064        DSP_                },        /* DPAQ_S.W.PH */
18065     { instruction         , 0                   , 0   , 32,
18066        0xfc003fff, 0x200004bf, &NMD::DPS_W_PH         , 0,
18067        DSP_                },        /* DPS.W.PH */
18068     { instruction         , 0                   , 0   , 32,
18069        0xfc003fff, 0x200006bf, &NMD::DPSQ_S_W_PH      , 0,
18070        DSP_                },        /* DPSQ_S.W.PH */
18071     { reserved_block      , 0                   , 0   , 32,
18072        0xfc003fff, 0x200008bf, 0                      , 0,
18073        0x0                 },        /* POOL32Axf_2(DSP)_0_7~*(4) */
18074     { instruction         , 0                   , 0   , 32,
18075        0xfc003fff, 0x20000abf, &NMD::MADD_DSP_        , 0,
18076        DSP_                },        /* MADD[DSP] */
18077     { instruction         , 0                   , 0   , 32,
18078        0xfc003fff, 0x20000cbf, &NMD::MULT_DSP_        , 0,
18079        DSP_                },        /* MULT[DSP] */
18080     { instruction         , 0                   , 0   , 32,
18081        0xfc003fff, 0x20000ebf, &NMD::EXTRV_W          , 0,
18082        DSP_                },        /* EXTRV.W */
18083 };
18084
18085
18086 NMD::Pool NMD::POOL32Axf_2_DSP__8_15[8] = {
18087     { instruction         , 0                   , 0   , 32,
18088        0xfc003fff, 0x200010bf, &NMD::DPAX_W_PH        , 0,
18089        DSP_                },        /* DPAX.W.PH */
18090     { instruction         , 0                   , 0   , 32,
18091        0xfc003fff, 0x200012bf, &NMD::DPAQ_SA_L_W      , 0,
18092        DSP_                },        /* DPAQ_SA.L.W */
18093     { instruction         , 0                   , 0   , 32,
18094        0xfc003fff, 0x200014bf, &NMD::DPSX_W_PH        , 0,
18095        DSP_                },        /* DPSX.W.PH */
18096     { instruction         , 0                   , 0   , 32,
18097        0xfc003fff, 0x200016bf, &NMD::DPSQ_SA_L_W      , 0,
18098        DSP_                },        /* DPSQ_SA.L.W */
18099     { reserved_block      , 0                   , 0   , 32,
18100        0xfc003fff, 0x200018bf, 0                      , 0,
18101        0x0                 },        /* POOL32Axf_2(DSP)_8_15~*(4) */
18102     { instruction         , 0                   , 0   , 32,
18103        0xfc003fff, 0x20001abf, &NMD::MADDU_DSP_       , 0,
18104        DSP_                },        /* MADDU[DSP] */
18105     { instruction         , 0                   , 0   , 32,
18106        0xfc003fff, 0x20001cbf, &NMD::MULTU_DSP_       , 0,
18107        DSP_                },        /* MULTU[DSP] */
18108     { instruction         , 0                   , 0   , 32,
18109        0xfc003fff, 0x20001ebf, &NMD::EXTRV_R_W        , 0,
18110        DSP_                },        /* EXTRV_R.W */
18111 };
18112
18113
18114 NMD::Pool NMD::POOL32Axf_2_DSP__16_23[8] = {
18115     { instruction         , 0                   , 0   , 32,
18116        0xfc003fff, 0x200020bf, &NMD::DPAU_H_QBL       , 0,
18117        DSP_                },        /* DPAU.H.QBL */
18118     { instruction         , 0                   , 0   , 32,
18119        0xfc003fff, 0x200022bf, &NMD::DPAQX_S_W_PH     , 0,
18120        DSP_                },        /* DPAQX_S.W.PH */
18121     { instruction         , 0                   , 0   , 32,
18122        0xfc003fff, 0x200024bf, &NMD::DPSU_H_QBL       , 0,
18123        DSP_                },        /* DPSU.H.QBL */
18124     { instruction         , 0                   , 0   , 32,
18125        0xfc003fff, 0x200026bf, &NMD::DPSQX_S_W_PH     , 0,
18126        DSP_                },        /* DPSQX_S.W.PH */
18127     { instruction         , 0                   , 0   , 32,
18128        0xfc003fff, 0x200028bf, &NMD::EXTPV            , 0,
18129        DSP_                },        /* EXTPV */
18130     { instruction         , 0                   , 0   , 32,
18131        0xfc003fff, 0x20002abf, &NMD::MSUB_DSP_        , 0,
18132        DSP_                },        /* MSUB[DSP] */
18133     { instruction         , 0                   , 0   , 32,
18134        0xfc003fff, 0x20002cbf, &NMD::MULSA_W_PH       , 0,
18135        DSP_                },        /* MULSA.W.PH */
18136     { instruction         , 0                   , 0   , 32,
18137        0xfc003fff, 0x20002ebf, &NMD::EXTRV_RS_W       , 0,
18138        DSP_                },        /* EXTRV_RS.W */
18139 };
18140
18141
18142 NMD::Pool NMD::POOL32Axf_2_DSP__24_31[8] = {
18143     { instruction         , 0                   , 0   , 32,
18144        0xfc003fff, 0x200030bf, &NMD::DPAU_H_QBR       , 0,
18145        DSP_                },        /* DPAU.H.QBR */
18146     { instruction         , 0                   , 0   , 32,
18147        0xfc003fff, 0x200032bf, &NMD::DPAQX_SA_W_PH    , 0,
18148        DSP_                },        /* DPAQX_SA.W.PH */
18149     { instruction         , 0                   , 0   , 32,
18150        0xfc003fff, 0x200034bf, &NMD::DPSU_H_QBR       , 0,
18151        DSP_                },        /* DPSU.H.QBR */
18152     { instruction         , 0                   , 0   , 32,
18153        0xfc003fff, 0x200036bf, &NMD::DPSQX_SA_W_PH    , 0,
18154        DSP_                },        /* DPSQX_SA.W.PH */
18155     { instruction         , 0                   , 0   , 32,
18156        0xfc003fff, 0x200038bf, &NMD::EXTPDPV          , 0,
18157        DSP_                },        /* EXTPDPV */
18158     { instruction         , 0                   , 0   , 32,
18159        0xfc003fff, 0x20003abf, &NMD::MSUBU_DSP_       , 0,
18160        DSP_                },        /* MSUBU[DSP] */
18161     { instruction         , 0                   , 0   , 32,
18162        0xfc003fff, 0x20003cbf, &NMD::MULSAQ_S_W_PH    , 0,
18163        DSP_                },        /* MULSAQ_S.W.PH */
18164     { instruction         , 0                   , 0   , 32,
18165        0xfc003fff, 0x20003ebf, &NMD::EXTRV_S_H        , 0,
18166        DSP_                },        /* EXTRV_S.H */
18167 };
18168
18169
18170 NMD::Pool NMD::POOL32Axf_2[4] = {
18171     { pool                , POOL32Axf_2_DSP__0_7, 8   , 32,
18172        0xfc0031ff, 0x200000bf, 0                      , 0,
18173        0x0                 },        /* POOL32Axf_2(DSP)_0_7 */
18174     { pool                , POOL32Axf_2_DSP__8_15, 8   , 32,
18175        0xfc0031ff, 0x200010bf, 0                      , 0,
18176        0x0                 },        /* POOL32Axf_2(DSP)_8_15 */
18177     { pool                , POOL32Axf_2_DSP__16_23, 8   , 32,
18178        0xfc0031ff, 0x200020bf, 0                      , 0,
18179        0x0                 },        /* POOL32Axf_2(DSP)_16_23 */
18180     { pool                , POOL32Axf_2_DSP__24_31, 8   , 32,
18181        0xfc0031ff, 0x200030bf, 0                      , 0,
18182        0x0                 },        /* POOL32Axf_2(DSP)_24_31 */
18183 };
18184
18185
18186 NMD::Pool NMD::POOL32Axf_4[128] = {
18187     { instruction         , 0                   , 0   , 32,
18188        0xfc00ffff, 0x2000013f, &NMD::ABSQ_S_QB        , 0,
18189        DSP_                },        /* ABSQ_S.QB */
18190     { instruction         , 0                   , 0   , 32,
18191        0xfc00ffff, 0x2000033f, &NMD::REPLV_PH         , 0,
18192        DSP_                },        /* REPLV.PH */
18193     { reserved_block      , 0                   , 0   , 32,
18194        0xfc00ffff, 0x2000053f, 0                      , 0,
18195        0x0                 },        /* POOL32Axf_4~*(2) */
18196     { reserved_block      , 0                   , 0   , 32,
18197        0xfc00ffff, 0x2000073f, 0                      , 0,
18198        0x0                 },        /* POOL32Axf_4~*(3) */
18199     { reserved_block      , 0                   , 0   , 32,
18200        0xfc00ffff, 0x2000093f, 0                      , 0,
18201        0x0                 },        /* POOL32Axf_4~*(4) */
18202     { reserved_block      , 0                   , 0   , 32,
18203        0xfc00ffff, 0x20000b3f, 0                      , 0,
18204        0x0                 },        /* POOL32Axf_4~*(5) */
18205     { reserved_block      , 0                   , 0   , 32,
18206        0xfc00ffff, 0x20000d3f, 0                      , 0,
18207        0x0                 },        /* POOL32Axf_4~*(6) */
18208     { reserved_block      , 0                   , 0   , 32,
18209        0xfc00ffff, 0x20000f3f, 0                      , 0,
18210        0x0                 },        /* POOL32Axf_4~*(7) */
18211     { instruction         , 0                   , 0   , 32,
18212        0xfc00ffff, 0x2000113f, &NMD::ABSQ_S_PH        , 0,
18213        DSP_                },        /* ABSQ_S.PH */
18214     { instruction         , 0                   , 0   , 32,
18215        0xfc00ffff, 0x2000133f, &NMD::REPLV_QB         , 0,
18216        DSP_                },        /* REPLV.QB */
18217     { reserved_block      , 0                   , 0   , 32,
18218        0xfc00ffff, 0x2000153f, 0                      , 0,
18219        0x0                 },        /* POOL32Axf_4~*(10) */
18220     { reserved_block      , 0                   , 0   , 32,
18221        0xfc00ffff, 0x2000173f, 0                      , 0,
18222        0x0                 },        /* POOL32Axf_4~*(11) */
18223     { reserved_block      , 0                   , 0   , 32,
18224        0xfc00ffff, 0x2000193f, 0                      , 0,
18225        0x0                 },        /* POOL32Axf_4~*(12) */
18226     { reserved_block      , 0                   , 0   , 32,
18227        0xfc00ffff, 0x20001b3f, 0                      , 0,
18228        0x0                 },        /* POOL32Axf_4~*(13) */
18229     { reserved_block      , 0                   , 0   , 32,
18230        0xfc00ffff, 0x20001d3f, 0                      , 0,
18231        0x0                 },        /* POOL32Axf_4~*(14) */
18232     { reserved_block      , 0                   , 0   , 32,
18233        0xfc00ffff, 0x20001f3f, 0                      , 0,
18234        0x0                 },        /* POOL32Axf_4~*(15) */
18235     { instruction         , 0                   , 0   , 32,
18236        0xfc00ffff, 0x2000213f, &NMD::ABSQ_S_W         , 0,
18237        DSP_                },        /* ABSQ_S.W */
18238     { reserved_block      , 0                   , 0   , 32,
18239        0xfc00ffff, 0x2000233f, 0                      , 0,
18240        0x0                 },        /* POOL32Axf_4~*(17) */
18241     { reserved_block      , 0                   , 0   , 32,
18242        0xfc00ffff, 0x2000253f, 0                      , 0,
18243        0x0                 },        /* POOL32Axf_4~*(18) */
18244     { reserved_block      , 0                   , 0   , 32,
18245        0xfc00ffff, 0x2000273f, 0                      , 0,
18246        0x0                 },        /* POOL32Axf_4~*(19) */
18247     { reserved_block      , 0                   , 0   , 32,
18248        0xfc00ffff, 0x2000293f, 0                      , 0,
18249        0x0                 },        /* POOL32Axf_4~*(20) */
18250     { reserved_block      , 0                   , 0   , 32,
18251        0xfc00ffff, 0x20002b3f, 0                      , 0,
18252        0x0                 },        /* POOL32Axf_4~*(21) */
18253     { reserved_block      , 0                   , 0   , 32,
18254        0xfc00ffff, 0x20002d3f, 0                      , 0,
18255        0x0                 },        /* POOL32Axf_4~*(22) */
18256     { reserved_block      , 0                   , 0   , 32,
18257        0xfc00ffff, 0x20002f3f, 0                      , 0,
18258        0x0                 },        /* POOL32Axf_4~*(23) */
18259     { reserved_block      , 0                   , 0   , 32,
18260        0xfc00ffff, 0x2000313f, 0                      , 0,
18261        0x0                 },        /* POOL32Axf_4~*(24) */
18262     { reserved_block      , 0                   , 0   , 32,
18263        0xfc00ffff, 0x2000333f, 0                      , 0,
18264        0x0                 },        /* POOL32Axf_4~*(25) */
18265     { reserved_block      , 0                   , 0   , 32,
18266        0xfc00ffff, 0x2000353f, 0                      , 0,
18267        0x0                 },        /* POOL32Axf_4~*(26) */
18268     { reserved_block      , 0                   , 0   , 32,
18269        0xfc00ffff, 0x2000373f, 0                      , 0,
18270        0x0                 },        /* POOL32Axf_4~*(27) */
18271     { reserved_block      , 0                   , 0   , 32,
18272        0xfc00ffff, 0x2000393f, 0                      , 0,
18273        0x0                 },        /* POOL32Axf_4~*(28) */
18274     { reserved_block      , 0                   , 0   , 32,
18275        0xfc00ffff, 0x20003b3f, 0                      , 0,
18276        0x0                 },        /* POOL32Axf_4~*(29) */
18277     { reserved_block      , 0                   , 0   , 32,
18278        0xfc00ffff, 0x20003d3f, 0                      , 0,
18279        0x0                 },        /* POOL32Axf_4~*(30) */
18280     { reserved_block      , 0                   , 0   , 32,
18281        0xfc00ffff, 0x20003f3f, 0                      , 0,
18282        0x0                 },        /* POOL32Axf_4~*(31) */
18283     { instruction         , 0                   , 0   , 32,
18284        0xfc00ffff, 0x2000413f, &NMD::INSV             , 0,
18285        DSP_                },        /* INSV */
18286     { reserved_block      , 0                   , 0   , 32,
18287        0xfc00ffff, 0x2000433f, 0                      , 0,
18288        0x0                 },        /* POOL32Axf_4~*(33) */
18289     { reserved_block      , 0                   , 0   , 32,
18290        0xfc00ffff, 0x2000453f, 0                      , 0,
18291        0x0                 },        /* POOL32Axf_4~*(34) */
18292     { reserved_block      , 0                   , 0   , 32,
18293        0xfc00ffff, 0x2000473f, 0                      , 0,
18294        0x0                 },        /* POOL32Axf_4~*(35) */
18295     { reserved_block      , 0                   , 0   , 32,
18296        0xfc00ffff, 0x2000493f, 0                      , 0,
18297        0x0                 },        /* POOL32Axf_4~*(36) */
18298     { instruction         , 0                   , 0   , 32,
18299        0xfc00ffff, 0x20004b3f, &NMD::CLO              , 0,
18300        XMMS_               },        /* CLO */
18301     { instruction         , 0                   , 0   , 32,
18302        0xfc00ffff, 0x20004d3f, &NMD::MFC2             , 0,
18303        CP2_                },        /* MFC2 */
18304     { reserved_block      , 0                   , 0   , 32,
18305        0xfc00ffff, 0x20004f3f, 0                      , 0,
18306        0x0                 },        /* POOL32Axf_4~*(39) */
18307     { instruction         , 0                   , 0   , 32,
18308        0xfc00ffff, 0x2000513f, &NMD::PRECEQ_W_PHL     , 0,
18309        DSP_                },        /* PRECEQ.W.PHL */
18310     { reserved_block      , 0                   , 0   , 32,
18311        0xfc00ffff, 0x2000533f, 0                      , 0,
18312        0x0                 },        /* POOL32Axf_4~*(41) */
18313     { reserved_block      , 0                   , 0   , 32,
18314        0xfc00ffff, 0x2000553f, 0                      , 0,
18315        0x0                 },        /* POOL32Axf_4~*(42) */
18316     { reserved_block      , 0                   , 0   , 32,
18317        0xfc00ffff, 0x2000573f, 0                      , 0,
18318        0x0                 },        /* POOL32Axf_4~*(43) */
18319     { reserved_block      , 0                   , 0   , 32,
18320        0xfc00ffff, 0x2000593f, 0                      , 0,
18321        0x0                 },        /* POOL32Axf_4~*(44) */
18322     { instruction         , 0                   , 0   , 32,
18323        0xfc00ffff, 0x20005b3f, &NMD::CLZ              , 0,
18324        XMMS_               },        /* CLZ */
18325     { instruction         , 0                   , 0   , 32,
18326        0xfc00ffff, 0x20005d3f, &NMD::MTC2             , 0,
18327        CP2_                },        /* MTC2 */
18328     { reserved_block      , 0                   , 0   , 32,
18329        0xfc00ffff, 0x20005f3f, 0                      , 0,
18330        0x0                 },        /* POOL32Axf_4~*(47) */
18331     { instruction         , 0                   , 0   , 32,
18332        0xfc00ffff, 0x2000613f, &NMD::PRECEQ_W_PHR     , 0,
18333        DSP_                },        /* PRECEQ.W.PHR */
18334     { reserved_block      , 0                   , 0   , 32,
18335        0xfc00ffff, 0x2000633f, 0                      , 0,
18336        0x0                 },        /* POOL32Axf_4~*(49) */
18337     { reserved_block      , 0                   , 0   , 32,
18338        0xfc00ffff, 0x2000653f, 0                      , 0,
18339        0x0                 },        /* POOL32Axf_4~*(50) */
18340     { reserved_block      , 0                   , 0   , 32,
18341        0xfc00ffff, 0x2000673f, 0                      , 0,
18342        0x0                 },        /* POOL32Axf_4~*(51) */
18343     { reserved_block      , 0                   , 0   , 32,
18344        0xfc00ffff, 0x2000693f, 0                      , 0,
18345        0x0                 },        /* POOL32Axf_4~*(52) */
18346     { reserved_block      , 0                   , 0   , 32,
18347        0xfc00ffff, 0x20006b3f, 0                      , 0,
18348        0x0                 },        /* POOL32Axf_4~*(53) */
18349     { instruction         , 0                   , 0   , 32,
18350        0xfc00ffff, 0x20006d3f, &NMD::DMFC2            , 0,
18351        CP2_                },        /* DMFC2 */
18352     { reserved_block      , 0                   , 0   , 32,
18353        0xfc00ffff, 0x20006f3f, 0                      , 0,
18354        0x0                 },        /* POOL32Axf_4~*(55) */
18355     { instruction         , 0                   , 0   , 32,
18356        0xfc00ffff, 0x2000713f, &NMD::PRECEQU_PH_QBL   , 0,
18357        DSP_                },        /* PRECEQU.PH.QBL */
18358     { instruction         , 0                   , 0   , 32,
18359        0xfc00ffff, 0x2000733f, &NMD::PRECEQU_PH_QBLA  , 0,
18360        DSP_                },        /* PRECEQU.PH.QBLA */
18361     { reserved_block      , 0                   , 0   , 32,
18362        0xfc00ffff, 0x2000753f, 0                      , 0,
18363        0x0                 },        /* POOL32Axf_4~*(58) */
18364     { reserved_block      , 0                   , 0   , 32,
18365        0xfc00ffff, 0x2000773f, 0                      , 0,
18366        0x0                 },        /* POOL32Axf_4~*(59) */
18367     { reserved_block      , 0                   , 0   , 32,
18368        0xfc00ffff, 0x2000793f, 0                      , 0,
18369        0x0                 },        /* POOL32Axf_4~*(60) */
18370     { reserved_block      , 0                   , 0   , 32,
18371        0xfc00ffff, 0x20007b3f, 0                      , 0,
18372        0x0                 },        /* POOL32Axf_4~*(61) */
18373     { instruction         , 0                   , 0   , 32,
18374        0xfc00ffff, 0x20007d3f, &NMD::DMTC2            , 0,
18375        CP2_                },        /* DMTC2 */
18376     { reserved_block      , 0                   , 0   , 32,
18377        0xfc00ffff, 0x20007f3f, 0                      , 0,
18378        0x0                 },        /* POOL32Axf_4~*(63) */
18379     { reserved_block      , 0                   , 0   , 32,
18380        0xfc00ffff, 0x2000813f, 0                      , 0,
18381        0x0                 },        /* POOL32Axf_4~*(64) */
18382     { reserved_block      , 0                   , 0   , 32,
18383        0xfc00ffff, 0x2000833f, 0                      , 0,
18384        0x0                 },        /* POOL32Axf_4~*(65) */
18385     { reserved_block      , 0                   , 0   , 32,
18386        0xfc00ffff, 0x2000853f, 0                      , 0,
18387        0x0                 },        /* POOL32Axf_4~*(66) */
18388     { reserved_block      , 0                   , 0   , 32,
18389        0xfc00ffff, 0x2000873f, 0                      , 0,
18390        0x0                 },        /* POOL32Axf_4~*(67) */
18391     { reserved_block      , 0                   , 0   , 32,
18392        0xfc00ffff, 0x2000893f, 0                      , 0,
18393        0x0                 },        /* POOL32Axf_4~*(68) */
18394     { reserved_block      , 0                   , 0   , 32,
18395        0xfc00ffff, 0x20008b3f, 0                      , 0,
18396        0x0                 },        /* POOL32Axf_4~*(69) */
18397     { instruction         , 0                   , 0   , 32,
18398        0xfc00ffff, 0x20008d3f, &NMD::MFHC2            , 0,
18399        CP2_                },        /* MFHC2 */
18400     { reserved_block      , 0                   , 0   , 32,
18401        0xfc00ffff, 0x20008f3f, 0                      , 0,
18402        0x0                 },        /* POOL32Axf_4~*(71) */
18403     { instruction         , 0                   , 0   , 32,
18404        0xfc00ffff, 0x2000913f, &NMD::PRECEQU_PH_QBR   , 0,
18405        DSP_                },        /* PRECEQU.PH.QBR */
18406     { instruction         , 0                   , 0   , 32,
18407        0xfc00ffff, 0x2000933f, &NMD::PRECEQU_PH_QBRA  , 0,
18408        DSP_                },        /* PRECEQU.PH.QBRA */
18409     { reserved_block      , 0                   , 0   , 32,
18410        0xfc00ffff, 0x2000953f, 0                      , 0,
18411        0x0                 },        /* POOL32Axf_4~*(74) */
18412     { reserved_block      , 0                   , 0   , 32,
18413        0xfc00ffff, 0x2000973f, 0                      , 0,
18414        0x0                 },        /* POOL32Axf_4~*(75) */
18415     { reserved_block      , 0                   , 0   , 32,
18416        0xfc00ffff, 0x2000993f, 0                      , 0,
18417        0x0                 },        /* POOL32Axf_4~*(76) */
18418     { reserved_block      , 0                   , 0   , 32,
18419        0xfc00ffff, 0x20009b3f, 0                      , 0,
18420        0x0                 },        /* POOL32Axf_4~*(77) */
18421     { instruction         , 0                   , 0   , 32,
18422        0xfc00ffff, 0x20009d3f, &NMD::MTHC2            , 0,
18423        CP2_                },        /* MTHC2 */
18424     { reserved_block      , 0                   , 0   , 32,
18425        0xfc00ffff, 0x20009f3f, 0                      , 0,
18426        0x0                 },        /* POOL32Axf_4~*(79) */
18427     { reserved_block      , 0                   , 0   , 32,
18428        0xfc00ffff, 0x2000a13f, 0                      , 0,
18429        0x0                 },        /* POOL32Axf_4~*(80) */
18430     { reserved_block      , 0                   , 0   , 32,
18431        0xfc00ffff, 0x2000a33f, 0                      , 0,
18432        0x0                 },        /* POOL32Axf_4~*(81) */
18433     { reserved_block      , 0                   , 0   , 32,
18434        0xfc00ffff, 0x2000a53f, 0                      , 0,
18435        0x0                 },        /* POOL32Axf_4~*(82) */
18436     { reserved_block      , 0                   , 0   , 32,
18437        0xfc00ffff, 0x2000a73f, 0                      , 0,
18438        0x0                 },        /* POOL32Axf_4~*(83) */
18439     { reserved_block      , 0                   , 0   , 32,
18440        0xfc00ffff, 0x2000a93f, 0                      , 0,
18441        0x0                 },        /* POOL32Axf_4~*(84) */
18442     { reserved_block      , 0                   , 0   , 32,
18443        0xfc00ffff, 0x2000ab3f, 0                      , 0,
18444        0x0                 },        /* POOL32Axf_4~*(85) */
18445     { reserved_block      , 0                   , 0   , 32,
18446        0xfc00ffff, 0x2000ad3f, 0                      , 0,
18447        0x0                 },        /* POOL32Axf_4~*(86) */
18448     { reserved_block      , 0                   , 0   , 32,
18449        0xfc00ffff, 0x2000af3f, 0                      , 0,
18450        0x0                 },        /* POOL32Axf_4~*(87) */
18451     { instruction         , 0                   , 0   , 32,
18452        0xfc00ffff, 0x2000b13f, &NMD::PRECEU_PH_QBL    , 0,
18453        DSP_                },        /* PRECEU.PH.QBL */
18454     { instruction         , 0                   , 0   , 32,
18455        0xfc00ffff, 0x2000b33f, &NMD::PRECEU_PH_QBLA   , 0,
18456        DSP_                },        /* PRECEU.PH.QBLA */
18457     { reserved_block      , 0                   , 0   , 32,
18458        0xfc00ffff, 0x2000b53f, 0                      , 0,
18459        0x0                 },        /* POOL32Axf_4~*(90) */
18460     { reserved_block      , 0                   , 0   , 32,
18461        0xfc00ffff, 0x2000b73f, 0                      , 0,
18462        0x0                 },        /* POOL32Axf_4~*(91) */
18463     { reserved_block      , 0                   , 0   , 32,
18464        0xfc00ffff, 0x2000b93f, 0                      , 0,
18465        0x0                 },        /* POOL32Axf_4~*(92) */
18466     { reserved_block      , 0                   , 0   , 32,
18467        0xfc00ffff, 0x2000bb3f, 0                      , 0,
18468        0x0                 },        /* POOL32Axf_4~*(93) */
18469     { reserved_block      , 0                   , 0   , 32,
18470        0xfc00ffff, 0x2000bd3f, 0                      , 0,
18471        0x0                 },        /* POOL32Axf_4~*(94) */
18472     { reserved_block      , 0                   , 0   , 32,
18473        0xfc00ffff, 0x2000bf3f, 0                      , 0,
18474        0x0                 },        /* POOL32Axf_4~*(95) */
18475     { reserved_block      , 0                   , 0   , 32,
18476        0xfc00ffff, 0x2000c13f, 0                      , 0,
18477        0x0                 },        /* POOL32Axf_4~*(96) */
18478     { reserved_block      , 0                   , 0   , 32,
18479        0xfc00ffff, 0x2000c33f, 0                      , 0,
18480        0x0                 },        /* POOL32Axf_4~*(97) */
18481     { reserved_block      , 0                   , 0   , 32,
18482        0xfc00ffff, 0x2000c53f, 0                      , 0,
18483        0x0                 },        /* POOL32Axf_4~*(98) */
18484     { reserved_block      , 0                   , 0   , 32,
18485        0xfc00ffff, 0x2000c73f, 0                      , 0,
18486        0x0                 },        /* POOL32Axf_4~*(99) */
18487     { reserved_block      , 0                   , 0   , 32,
18488        0xfc00ffff, 0x2000c93f, 0                      , 0,
18489        0x0                 },        /* POOL32Axf_4~*(100) */
18490     { reserved_block      , 0                   , 0   , 32,
18491        0xfc00ffff, 0x2000cb3f, 0                      , 0,
18492        0x0                 },        /* POOL32Axf_4~*(101) */
18493     { instruction         , 0                   , 0   , 32,
18494        0xfc00ffff, 0x2000cd3f, &NMD::CFC2             , 0,
18495        CP2_                },        /* CFC2 */
18496     { reserved_block      , 0                   , 0   , 32,
18497        0xfc00ffff, 0x2000cf3f, 0                      , 0,
18498        0x0                 },        /* POOL32Axf_4~*(103) */
18499     { instruction         , 0                   , 0   , 32,
18500        0xfc00ffff, 0x2000d13f, &NMD::PRECEU_PH_QBR    , 0,
18501        DSP_                },        /* PRECEU.PH.QBR */
18502     { instruction         , 0                   , 0   , 32,
18503        0xfc00ffff, 0x2000d33f, &NMD::PRECEU_PH_QBRA   , 0,
18504        DSP_                },        /* PRECEU.PH.QBRA */
18505     { reserved_block      , 0                   , 0   , 32,
18506        0xfc00ffff, 0x2000d53f, 0                      , 0,
18507        0x0                 },        /* POOL32Axf_4~*(106) */
18508     { reserved_block      , 0                   , 0   , 32,
18509        0xfc00ffff, 0x2000d73f, 0                      , 0,
18510        0x0                 },        /* POOL32Axf_4~*(107) */
18511     { reserved_block      , 0                   , 0   , 32,
18512        0xfc00ffff, 0x2000d93f, 0                      , 0,
18513        0x0                 },        /* POOL32Axf_4~*(108) */
18514     { reserved_block      , 0                   , 0   , 32,
18515        0xfc00ffff, 0x2000db3f, 0                      , 0,
18516        0x0                 },        /* POOL32Axf_4~*(109) */
18517     { instruction         , 0                   , 0   , 32,
18518        0xfc00ffff, 0x2000dd3f, &NMD::CTC2             , 0,
18519        CP2_                },        /* CTC2 */
18520     { reserved_block      , 0                   , 0   , 32,
18521        0xfc00ffff, 0x2000df3f, 0                      , 0,
18522        0x0                 },        /* POOL32Axf_4~*(111) */
18523     { reserved_block      , 0                   , 0   , 32,
18524        0xfc00ffff, 0x2000e13f, 0                      , 0,
18525        0x0                 },        /* POOL32Axf_4~*(112) */
18526     { reserved_block      , 0                   , 0   , 32,
18527        0xfc00ffff, 0x2000e33f, 0                      , 0,
18528        0x0                 },        /* POOL32Axf_4~*(113) */
18529     { reserved_block      , 0                   , 0   , 32,
18530        0xfc00ffff, 0x2000e53f, 0                      , 0,
18531        0x0                 },        /* POOL32Axf_4~*(114) */
18532     { reserved_block      , 0                   , 0   , 32,
18533        0xfc00ffff, 0x2000e73f, 0                      , 0,
18534        0x0                 },        /* POOL32Axf_4~*(115) */
18535     { reserved_block      , 0                   , 0   , 32,
18536        0xfc00ffff, 0x2000e93f, 0                      , 0,
18537        0x0                 },        /* POOL32Axf_4~*(116) */
18538     { reserved_block      , 0                   , 0   , 32,
18539        0xfc00ffff, 0x2000eb3f, 0                      , 0,
18540        0x0                 },        /* POOL32Axf_4~*(117) */
18541     { reserved_block      , 0                   , 0   , 32,
18542        0xfc00ffff, 0x2000ed3f, 0                      , 0,
18543        0x0                 },        /* POOL32Axf_4~*(118) */
18544     { reserved_block      , 0                   , 0   , 32,
18545        0xfc00ffff, 0x2000ef3f, 0                      , 0,
18546        0x0                 },        /* POOL32Axf_4~*(119) */
18547     { instruction         , 0                   , 0   , 32,
18548        0xfc00ffff, 0x2000f13f, &NMD::RADDU_W_QB       , 0,
18549        DSP_                },        /* RADDU.W.QB */
18550     { reserved_block      , 0                   , 0   , 32,
18551        0xfc00ffff, 0x2000f33f, 0                      , 0,
18552        0x0                 },        /* POOL32Axf_4~*(121) */
18553     { reserved_block      , 0                   , 0   , 32,
18554        0xfc00ffff, 0x2000f53f, 0                      , 0,
18555        0x0                 },        /* POOL32Axf_4~*(122) */
18556     { reserved_block      , 0                   , 0   , 32,
18557        0xfc00ffff, 0x2000f73f, 0                      , 0,
18558        0x0                 },        /* POOL32Axf_4~*(123) */
18559     { reserved_block      , 0                   , 0   , 32,
18560        0xfc00ffff, 0x2000f93f, 0                      , 0,
18561        0x0                 },        /* POOL32Axf_4~*(124) */
18562     { reserved_block      , 0                   , 0   , 32,
18563        0xfc00ffff, 0x2000fb3f, 0                      , 0,
18564        0x0                 },        /* POOL32Axf_4~*(125) */
18565     { reserved_block      , 0                   , 0   , 32,
18566        0xfc00ffff, 0x2000fd3f, 0                      , 0,
18567        0x0                 },        /* POOL32Axf_4~*(126) */
18568     { reserved_block      , 0                   , 0   , 32,
18569        0xfc00ffff, 0x2000ff3f, 0                      , 0,
18570        0x0                 },        /* POOL32Axf_4~*(127) */
18571 };
18572
18573
18574 NMD::Pool NMD::POOL32Axf_5_group0[32] = {
18575     { instruction         , 0                   , 0   , 32,
18576        0xfc00ffff, 0x2000017f, &NMD::TLBGP            , 0,
18577        CP0_ | VZ_ | TLB_   },        /* TLBGP */
18578     { instruction         , 0                   , 0   , 32,
18579        0xfc00ffff, 0x2000037f, &NMD::TLBP             , 0,
18580        CP0_ | TLB_         },        /* TLBP */
18581     { instruction         , 0                   , 0   , 32,
18582        0xfc00ffff, 0x2000057f, &NMD::TLBGINV          , 0,
18583        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINV */
18584     { instruction         , 0                   , 0   , 32,
18585        0xfc00ffff, 0x2000077f, &NMD::TLBINV           , 0,
18586        CP0_ | TLB_ | TLBINV_},        /* TLBINV */
18587     { reserved_block      , 0                   , 0   , 32,
18588        0xfc00ffff, 0x2000097f, 0                      , 0,
18589        0x0                 },        /* POOL32Axf_5_group0~*(4) */
18590     { reserved_block      , 0                   , 0   , 32,
18591        0xfc00ffff, 0x20000b7f, 0                      , 0,
18592        0x0                 },        /* POOL32Axf_5_group0~*(5) */
18593     { reserved_block      , 0                   , 0   , 32,
18594        0xfc00ffff, 0x20000d7f, 0                      , 0,
18595        0x0                 },        /* POOL32Axf_5_group0~*(6) */
18596     { reserved_block      , 0                   , 0   , 32,
18597        0xfc00ffff, 0x20000f7f, 0                      , 0,
18598        0x0                 },        /* POOL32Axf_5_group0~*(7) */
18599     { instruction         , 0                   , 0   , 32,
18600        0xfc00ffff, 0x2000117f, &NMD::TLBGR            , 0,
18601        CP0_ | VZ_ | TLB_   },        /* TLBGR */
18602     { instruction         , 0                   , 0   , 32,
18603        0xfc00ffff, 0x2000137f, &NMD::TLBR             , 0,
18604        CP0_ | TLB_         },        /* TLBR */
18605     { instruction         , 0                   , 0   , 32,
18606        0xfc00ffff, 0x2000157f, &NMD::TLBGINVF         , 0,
18607        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINVF */
18608     { instruction         , 0                   , 0   , 32,
18609        0xfc00ffff, 0x2000177f, &NMD::TLBINVF          , 0,
18610        CP0_ | TLB_ | TLBINV_},        /* TLBINVF */
18611     { reserved_block      , 0                   , 0   , 32,
18612        0xfc00ffff, 0x2000197f, 0                      , 0,
18613        0x0                 },        /* POOL32Axf_5_group0~*(12) */
18614     { reserved_block      , 0                   , 0   , 32,
18615        0xfc00ffff, 0x20001b7f, 0                      , 0,
18616        0x0                 },        /* POOL32Axf_5_group0~*(13) */
18617     { reserved_block      , 0                   , 0   , 32,
18618        0xfc00ffff, 0x20001d7f, 0                      , 0,
18619        0x0                 },        /* POOL32Axf_5_group0~*(14) */
18620     { reserved_block      , 0                   , 0   , 32,
18621        0xfc00ffff, 0x20001f7f, 0                      , 0,
18622        0x0                 },        /* POOL32Axf_5_group0~*(15) */
18623     { instruction         , 0                   , 0   , 32,
18624        0xfc00ffff, 0x2000217f, &NMD::TLBGWI           , 0,
18625        CP0_ | VZ_ | TLB_   },        /* TLBGWI */
18626     { instruction         , 0                   , 0   , 32,
18627        0xfc00ffff, 0x2000237f, &NMD::TLBWI            , 0,
18628        CP0_ | TLB_         },        /* TLBWI */
18629     { reserved_block      , 0                   , 0   , 32,
18630        0xfc00ffff, 0x2000257f, 0                      , 0,
18631        0x0                 },        /* POOL32Axf_5_group0~*(18) */
18632     { reserved_block      , 0                   , 0   , 32,
18633        0xfc00ffff, 0x2000277f, 0                      , 0,
18634        0x0                 },        /* POOL32Axf_5_group0~*(19) */
18635     { reserved_block      , 0                   , 0   , 32,
18636        0xfc00ffff, 0x2000297f, 0                      , 0,
18637        0x0                 },        /* POOL32Axf_5_group0~*(20) */
18638     { reserved_block      , 0                   , 0   , 32,
18639        0xfc00ffff, 0x20002b7f, 0                      , 0,
18640        0x0                 },        /* POOL32Axf_5_group0~*(21) */
18641     { reserved_block      , 0                   , 0   , 32,
18642        0xfc00ffff, 0x20002d7f, 0                      , 0,
18643        0x0                 },        /* POOL32Axf_5_group0~*(22) */
18644     { reserved_block      , 0                   , 0   , 32,
18645        0xfc00ffff, 0x20002f7f, 0                      , 0,
18646        0x0                 },        /* POOL32Axf_5_group0~*(23) */
18647     { instruction         , 0                   , 0   , 32,
18648        0xfc00ffff, 0x2000317f, &NMD::TLBGWR           , 0,
18649        CP0_ | VZ_ | TLB_   },        /* TLBGWR */
18650     { instruction         , 0                   , 0   , 32,
18651        0xfc00ffff, 0x2000337f, &NMD::TLBWR            , 0,
18652        CP0_ | TLB_         },        /* TLBWR */
18653     { reserved_block      , 0                   , 0   , 32,
18654        0xfc00ffff, 0x2000357f, 0                      , 0,
18655        0x0                 },        /* POOL32Axf_5_group0~*(26) */
18656     { reserved_block      , 0                   , 0   , 32,
18657        0xfc00ffff, 0x2000377f, 0                      , 0,
18658        0x0                 },        /* POOL32Axf_5_group0~*(27) */
18659     { reserved_block      , 0                   , 0   , 32,
18660        0xfc00ffff, 0x2000397f, 0                      , 0,
18661        0x0                 },        /* POOL32Axf_5_group0~*(28) */
18662     { reserved_block      , 0                   , 0   , 32,
18663        0xfc00ffff, 0x20003b7f, 0                      , 0,
18664        0x0                 },        /* POOL32Axf_5_group0~*(29) */
18665     { reserved_block      , 0                   , 0   , 32,
18666        0xfc00ffff, 0x20003d7f, 0                      , 0,
18667        0x0                 },        /* POOL32Axf_5_group0~*(30) */
18668     { reserved_block      , 0                   , 0   , 32,
18669        0xfc00ffff, 0x20003f7f, 0                      , 0,
18670        0x0                 },        /* POOL32Axf_5_group0~*(31) */
18671 };
18672
18673
18674 NMD::Pool NMD::POOL32Axf_5_group1[32] = {
18675     { reserved_block      , 0                   , 0   , 32,
18676        0xfc00ffff, 0x2000417f, 0                      , 0,
18677        0x0                 },        /* POOL32Axf_5_group1~*(0) */
18678     { reserved_block      , 0                   , 0   , 32,
18679        0xfc00ffff, 0x2000437f, 0                      , 0,
18680        0x0                 },        /* POOL32Axf_5_group1~*(1) */
18681     { reserved_block      , 0                   , 0   , 32,
18682        0xfc00ffff, 0x2000457f, 0                      , 0,
18683        0x0                 },        /* POOL32Axf_5_group1~*(2) */
18684     { instruction         , 0                   , 0   , 32,
18685        0xfc00ffff, 0x2000477f, &NMD::DI               , 0,
18686        0x0                 },        /* DI */
18687     { reserved_block      , 0                   , 0   , 32,
18688        0xfc00ffff, 0x2000497f, 0                      , 0,
18689        0x0                 },        /* POOL32Axf_5_group1~*(4) */
18690     { reserved_block      , 0                   , 0   , 32,
18691        0xfc00ffff, 0x20004b7f, 0                      , 0,
18692        0x0                 },        /* POOL32Axf_5_group1~*(5) */
18693     { reserved_block      , 0                   , 0   , 32,
18694        0xfc00ffff, 0x20004d7f, 0                      , 0,
18695        0x0                 },        /* POOL32Axf_5_group1~*(6) */
18696     { reserved_block      , 0                   , 0   , 32,
18697        0xfc00ffff, 0x20004f7f, 0                      , 0,
18698        0x0                 },        /* POOL32Axf_5_group1~*(7) */
18699     { reserved_block      , 0                   , 0   , 32,
18700        0xfc00ffff, 0x2000517f, 0                      , 0,
18701        0x0                 },        /* POOL32Axf_5_group1~*(8) */
18702     { reserved_block      , 0                   , 0   , 32,
18703        0xfc00ffff, 0x2000537f, 0                      , 0,
18704        0x0                 },        /* POOL32Axf_5_group1~*(9) */
18705     { reserved_block      , 0                   , 0   , 32,
18706        0xfc00ffff, 0x2000557f, 0                      , 0,
18707        0x0                 },        /* POOL32Axf_5_group1~*(10) */
18708     { instruction         , 0                   , 0   , 32,
18709        0xfc00ffff, 0x2000577f, &NMD::EI               , 0,
18710        0x0                 },        /* EI */
18711     { reserved_block      , 0                   , 0   , 32,
18712        0xfc00ffff, 0x2000597f, 0                      , 0,
18713        0x0                 },        /* POOL32Axf_5_group1~*(12) */
18714     { reserved_block      , 0                   , 0   , 32,
18715        0xfc00ffff, 0x20005b7f, 0                      , 0,
18716        0x0                 },        /* POOL32Axf_5_group1~*(13) */
18717     { reserved_block      , 0                   , 0   , 32,
18718        0xfc00ffff, 0x20005d7f, 0                      , 0,
18719        0x0                 },        /* POOL32Axf_5_group1~*(14) */
18720     { reserved_block      , 0                   , 0   , 32,
18721        0xfc00ffff, 0x20005f7f, 0                      , 0,
18722        0x0                 },        /* POOL32Axf_5_group1~*(15) */
18723     { reserved_block      , 0                   , 0   , 32,
18724        0xfc00ffff, 0x2000617f, 0                      , 0,
18725        0x0                 },        /* POOL32Axf_5_group1~*(16) */
18726     { reserved_block      , 0                   , 0   , 32,
18727        0xfc00ffff, 0x2000637f, 0                      , 0,
18728        0x0                 },        /* POOL32Axf_5_group1~*(17) */
18729     { reserved_block      , 0                   , 0   , 32,
18730        0xfc00ffff, 0x2000657f, 0                      , 0,
18731        0x0                 },        /* POOL32Axf_5_group1~*(18) */
18732     { reserved_block      , 0                   , 0   , 32,
18733        0xfc00ffff, 0x2000677f, 0                      , 0,
18734        0x0                 },        /* POOL32Axf_5_group1~*(19) */
18735     { reserved_block      , 0                   , 0   , 32,
18736        0xfc00ffff, 0x2000697f, 0                      , 0,
18737        0x0                 },        /* POOL32Axf_5_group1~*(20) */
18738     { reserved_block      , 0                   , 0   , 32,
18739        0xfc00ffff, 0x20006b7f, 0                      , 0,
18740        0x0                 },        /* POOL32Axf_5_group1~*(21) */
18741     { reserved_block      , 0                   , 0   , 32,
18742        0xfc00ffff, 0x20006d7f, 0                      , 0,
18743        0x0                 },        /* POOL32Axf_5_group1~*(22) */
18744     { reserved_block      , 0                   , 0   , 32,
18745        0xfc00ffff, 0x20006f7f, 0                      , 0,
18746        0x0                 },        /* POOL32Axf_5_group1~*(23) */
18747     { reserved_block      , 0                   , 0   , 32,
18748        0xfc00ffff, 0x2000717f, 0                      , 0,
18749        0x0                 },        /* POOL32Axf_5_group1~*(24) */
18750     { reserved_block      , 0                   , 0   , 32,
18751        0xfc00ffff, 0x2000737f, 0                      , 0,
18752        0x0                 },        /* POOL32Axf_5_group1~*(25) */
18753     { reserved_block      , 0                   , 0   , 32,
18754        0xfc00ffff, 0x2000757f, 0                      , 0,
18755        0x0                 },        /* POOL32Axf_5_group1~*(26) */
18756     { reserved_block      , 0                   , 0   , 32,
18757        0xfc00ffff, 0x2000777f, 0                      , 0,
18758        0x0                 },        /* POOL32Axf_5_group1~*(27) */
18759     { reserved_block      , 0                   , 0   , 32,
18760        0xfc00ffff, 0x2000797f, 0                      , 0,
18761        0x0                 },        /* POOL32Axf_5_group1~*(28) */
18762     { reserved_block      , 0                   , 0   , 32,
18763        0xfc00ffff, 0x20007b7f, 0                      , 0,
18764        0x0                 },        /* POOL32Axf_5_group1~*(29) */
18765     { reserved_block      , 0                   , 0   , 32,
18766        0xfc00ffff, 0x20007d7f, 0                      , 0,
18767        0x0                 },        /* POOL32Axf_5_group1~*(30) */
18768     { reserved_block      , 0                   , 0   , 32,
18769        0xfc00ffff, 0x20007f7f, 0                      , 0,
18770        0x0                 },        /* POOL32Axf_5_group1~*(31) */
18771 };
18772
18773
18774 NMD::Pool NMD::ERETx[2] = {
18775     { instruction         , 0                   , 0   , 32,
18776        0xfc01ffff, 0x2000f37f, &NMD::ERET             , 0,
18777        0x0                 },        /* ERET */
18778     { instruction         , 0                   , 0   , 32,
18779        0xfc01ffff, 0x2001f37f, &NMD::ERETNC           , 0,
18780        0x0                 },        /* ERETNC */
18781 };
18782
18783
18784 NMD::Pool NMD::POOL32Axf_5_group3[32] = {
18785     { reserved_block      , 0                   , 0   , 32,
18786        0xfc00ffff, 0x2000c17f, 0                      , 0,
18787        0x0                 },        /* POOL32Axf_5_group3~*(0) */
18788     { instruction         , 0                   , 0   , 32,
18789        0xfc00ffff, 0x2000c37f, &NMD::WAIT             , 0,
18790        0x0                 },        /* WAIT */
18791     { reserved_block      , 0                   , 0   , 32,
18792        0xfc00ffff, 0x2000c57f, 0                      , 0,
18793        0x0                 },        /* POOL32Axf_5_group3~*(2) */
18794     { reserved_block      , 0                   , 0   , 32,
18795        0xfc00ffff, 0x2000c77f, 0                      , 0,
18796        0x0                 },        /* POOL32Axf_5_group3~*(3) */
18797     { reserved_block      , 0                   , 0   , 32,
18798        0xfc00ffff, 0x2000c97f, 0                      , 0,
18799        0x0                 },        /* POOL32Axf_5_group3~*(4) */
18800     { reserved_block      , 0                   , 0   , 32,
18801        0xfc00ffff, 0x2000cb7f, 0                      , 0,
18802        0x0                 },        /* POOL32Axf_5_group3~*(5) */
18803     { reserved_block      , 0                   , 0   , 32,
18804        0xfc00ffff, 0x2000cd7f, 0                      , 0,
18805        0x0                 },        /* POOL32Axf_5_group3~*(6) */
18806     { reserved_block      , 0                   , 0   , 32,
18807        0xfc00ffff, 0x2000cf7f, 0                      , 0,
18808        0x0                 },        /* POOL32Axf_5_group3~*(7) */
18809     { reserved_block      , 0                   , 0   , 32,
18810        0xfc00ffff, 0x2000d17f, 0                      , 0,
18811        0x0                 },        /* POOL32Axf_5_group3~*(8) */
18812     { instruction         , 0                   , 0   , 32,
18813        0xfc00ffff, 0x2000d37f, &NMD::IRET             , 0,
18814        MCU_                },        /* IRET */
18815     { reserved_block      , 0                   , 0   , 32,
18816        0xfc00ffff, 0x2000d57f, 0                      , 0,
18817        0x0                 },        /* POOL32Axf_5_group3~*(10) */
18818     { reserved_block      , 0                   , 0   , 32,
18819        0xfc00ffff, 0x2000d77f, 0                      , 0,
18820        0x0                 },        /* POOL32Axf_5_group3~*(11) */
18821     { reserved_block      , 0                   , 0   , 32,
18822        0xfc00ffff, 0x2000d97f, 0                      , 0,
18823        0x0                 },        /* POOL32Axf_5_group3~*(12) */
18824     { reserved_block      , 0                   , 0   , 32,
18825        0xfc00ffff, 0x2000db7f, 0                      , 0,
18826        0x0                 },        /* POOL32Axf_5_group3~*(13) */
18827     { reserved_block      , 0                   , 0   , 32,
18828        0xfc00ffff, 0x2000dd7f, 0                      , 0,
18829        0x0                 },        /* POOL32Axf_5_group3~*(14) */
18830     { reserved_block      , 0                   , 0   , 32,
18831        0xfc00ffff, 0x2000df7f, 0                      , 0,
18832        0x0                 },        /* POOL32Axf_5_group3~*(15) */
18833     { instruction         , 0                   , 0   , 32,
18834        0xfc00ffff, 0x2000e17f, &NMD::RDPGPR           , 0,
18835        CP0_                },        /* RDPGPR */
18836     { instruction         , 0                   , 0   , 32,
18837        0xfc00ffff, 0x2000e37f, &NMD::DERET            , 0,
18838        EJTAG_              },        /* DERET */
18839     { reserved_block      , 0                   , 0   , 32,
18840        0xfc00ffff, 0x2000e57f, 0                      , 0,
18841        0x0                 },        /* POOL32Axf_5_group3~*(18) */
18842     { reserved_block      , 0                   , 0   , 32,
18843        0xfc00ffff, 0x2000e77f, 0                      , 0,
18844        0x0                 },        /* POOL32Axf_5_group3~*(19) */
18845     { reserved_block      , 0                   , 0   , 32,
18846        0xfc00ffff, 0x2000e97f, 0                      , 0,
18847        0x0                 },        /* POOL32Axf_5_group3~*(20) */
18848     { reserved_block      , 0                   , 0   , 32,
18849        0xfc00ffff, 0x2000eb7f, 0                      , 0,
18850        0x0                 },        /* POOL32Axf_5_group3~*(21) */
18851     { reserved_block      , 0                   , 0   , 32,
18852        0xfc00ffff, 0x2000ed7f, 0                      , 0,
18853        0x0                 },        /* POOL32Axf_5_group3~*(22) */
18854     { reserved_block      , 0                   , 0   , 32,
18855        0xfc00ffff, 0x2000ef7f, 0                      , 0,
18856        0x0                 },        /* POOL32Axf_5_group3~*(23) */
18857     { instruction         , 0                   , 0   , 32,
18858        0xfc00ffff, 0x2000f17f, &NMD::WRPGPR           , 0,
18859        CP0_                },        /* WRPGPR */
18860     { pool                , ERETx               , 2   , 32,
18861        0xfc00ffff, 0x2000f37f, 0                      , 0,
18862        0x0                 },        /* ERETx */
18863     { reserved_block      , 0                   , 0   , 32,
18864        0xfc00ffff, 0x2000f57f, 0                      , 0,
18865        0x0                 },        /* POOL32Axf_5_group3~*(26) */
18866     { reserved_block      , 0                   , 0   , 32,
18867        0xfc00ffff, 0x2000f77f, 0                      , 0,
18868        0x0                 },        /* POOL32Axf_5_group3~*(27) */
18869     { reserved_block      , 0                   , 0   , 32,
18870        0xfc00ffff, 0x2000f97f, 0                      , 0,
18871        0x0                 },        /* POOL32Axf_5_group3~*(28) */
18872     { reserved_block      , 0                   , 0   , 32,
18873        0xfc00ffff, 0x2000fb7f, 0                      , 0,
18874        0x0                 },        /* POOL32Axf_5_group3~*(29) */
18875     { reserved_block      , 0                   , 0   , 32,
18876        0xfc00ffff, 0x2000fd7f, 0                      , 0,
18877        0x0                 },        /* POOL32Axf_5_group3~*(30) */
18878     { reserved_block      , 0                   , 0   , 32,
18879        0xfc00ffff, 0x2000ff7f, 0                      , 0,
18880        0x0                 },        /* POOL32Axf_5_group3~*(31) */
18881 };
18882
18883
18884 NMD::Pool NMD::POOL32Axf_5[4] = {
18885     { pool                , POOL32Axf_5_group0  , 32  , 32,
18886        0xfc00c1ff, 0x2000017f, 0                      , 0,
18887        0x0                 },        /* POOL32Axf_5_group0 */
18888     { pool                , POOL32Axf_5_group1  , 32  , 32,
18889        0xfc00c1ff, 0x2000417f, 0                      , 0,
18890        0x0                 },        /* POOL32Axf_5_group1 */
18891     { reserved_block      , 0                   , 0   , 32,
18892        0xfc00c1ff, 0x2000817f, 0                      , 0,
18893        0x0                 },        /* POOL32Axf_5~*(2) */
18894     { pool                , POOL32Axf_5_group3  , 32  , 32,
18895        0xfc00c1ff, 0x2000c17f, 0                      , 0,
18896        0x0                 },        /* POOL32Axf_5_group3 */
18897 };
18898
18899
18900 NMD::Pool NMD::SHRA__R__QB[2] = {
18901     { instruction         , 0                   , 0   , 32,
18902        0xfc001fff, 0x200001ff, &NMD::SHRA_QB          , 0,
18903        DSP_                },        /* SHRA.QB */
18904     { instruction         , 0                   , 0   , 32,
18905        0xfc001fff, 0x200011ff, &NMD::SHRA_R_QB        , 0,
18906        DSP_                },        /* SHRA_R.QB */
18907 };
18908
18909
18910 NMD::Pool NMD::POOL32Axf_7[8] = {
18911     { pool                , SHRA__R__QB         , 2   , 32,
18912        0xfc000fff, 0x200001ff, 0                      , 0,
18913        0x0                 },        /* SHRA[_R].QB */
18914     { instruction         , 0                   , 0   , 32,
18915        0xfc000fff, 0x200003ff, &NMD::SHRL_PH          , 0,
18916        DSP_                },        /* SHRL.PH */
18917     { instruction         , 0                   , 0   , 32,
18918        0xfc000fff, 0x200005ff, &NMD::REPL_QB          , 0,
18919        DSP_                },        /* REPL.QB */
18920     { reserved_block      , 0                   , 0   , 32,
18921        0xfc000fff, 0x200007ff, 0                      , 0,
18922        0x0                 },        /* POOL32Axf_7~*(3) */
18923     { reserved_block      , 0                   , 0   , 32,
18924        0xfc000fff, 0x200009ff, 0                      , 0,
18925        0x0                 },        /* POOL32Axf_7~*(4) */
18926     { reserved_block      , 0                   , 0   , 32,
18927        0xfc000fff, 0x20000bff, 0                      , 0,
18928        0x0                 },        /* POOL32Axf_7~*(5) */
18929     { reserved_block      , 0                   , 0   , 32,
18930        0xfc000fff, 0x20000dff, 0                      , 0,
18931        0x0                 },        /* POOL32Axf_7~*(6) */
18932     { reserved_block      , 0                   , 0   , 32,
18933        0xfc000fff, 0x20000fff, 0                      , 0,
18934        0x0                 },        /* POOL32Axf_7~*(7) */
18935 };
18936
18937
18938 NMD::Pool NMD::POOL32Axf[8] = {
18939     { reserved_block      , 0                   , 0   , 32,
18940        0xfc0001ff, 0x2000003f, 0                      , 0,
18941        0x0                 },        /* POOL32Axf~*(0) */
18942     { pool                , POOL32Axf_1         , 8   , 32,
18943        0xfc0001ff, 0x2000007f, 0                      , 0,
18944        0x0                 },        /* POOL32Axf_1 */
18945     { pool                , POOL32Axf_2         , 4   , 32,
18946        0xfc0001ff, 0x200000bf, 0                      , 0,
18947        0x0                 },        /* POOL32Axf_2 */
18948     { reserved_block      , 0                   , 0   , 32,
18949        0xfc0001ff, 0x200000ff, 0                      , 0,
18950        0x0                 },        /* POOL32Axf~*(3) */
18951     { pool                , POOL32Axf_4         , 128 , 32,
18952        0xfc0001ff, 0x2000013f, 0                      , 0,
18953        0x0                 },        /* POOL32Axf_4 */
18954     { pool                , POOL32Axf_5         , 4   , 32,
18955        0xfc0001ff, 0x2000017f, 0                      , 0,
18956        0x0                 },        /* POOL32Axf_5 */
18957     { reserved_block      , 0                   , 0   , 32,
18958        0xfc0001ff, 0x200001bf, 0                      , 0,
18959        0x0                 },        /* POOL32Axf~*(6) */
18960     { pool                , POOL32Axf_7         , 8   , 32,
18961        0xfc0001ff, 0x200001ff, 0                      , 0,
18962        0x0                 },        /* POOL32Axf_7 */
18963 };
18964
18965
18966 NMD::Pool NMD::_POOL32A7[8] = {
18967     { pool                , P_LSX               , 2   , 32,
18968        0xfc00003f, 0x20000007, 0                      , 0,
18969        0x0                 },        /* P.LSX */
18970     { instruction         , 0                   , 0   , 32,
18971        0xfc00003f, 0x2000000f, &NMD::LSA              , 0,
18972        0x0                 },        /* LSA */
18973     { reserved_block      , 0                   , 0   , 32,
18974        0xfc00003f, 0x20000017, 0                      , 0,
18975        0x0                 },        /* _POOL32A7~*(2) */
18976     { instruction         , 0                   , 0   , 32,
18977        0xfc00003f, 0x2000001f, &NMD::EXTW             , 0,
18978        0x0                 },        /* EXTW */
18979     { reserved_block      , 0                   , 0   , 32,
18980        0xfc00003f, 0x20000027, 0                      , 0,
18981        0x0                 },        /* _POOL32A7~*(4) */
18982     { reserved_block      , 0                   , 0   , 32,
18983        0xfc00003f, 0x2000002f, 0                      , 0,
18984        0x0                 },        /* _POOL32A7~*(5) */
18985     { reserved_block      , 0                   , 0   , 32,
18986        0xfc00003f, 0x20000037, 0                      , 0,
18987        0x0                 },        /* _POOL32A7~*(6) */
18988     { pool                , POOL32Axf           , 8   , 32,
18989        0xfc00003f, 0x2000003f, 0                      , 0,
18990        0x0                 },        /* POOL32Axf */
18991 };
18992
18993
18994 NMD::Pool NMD::P32A[8] = {
18995     { pool                , _POOL32A0           , 128 , 32,
18996        0xfc000007, 0x20000000, 0                      , 0,
18997        0x0                 },        /* _POOL32A0 */
18998     { instruction         , 0                   , 0   , 32,
18999        0xfc000007, 0x20000001, &NMD::SPECIAL2         , 0,
19000        UDI_                },        /* SPECIAL2 */
19001     { instruction         , 0                   , 0   , 32,
19002        0xfc000007, 0x20000002, &NMD::COP2_1           , 0,
19003        CP2_                },        /* COP2_1 */
19004     { instruction         , 0                   , 0   , 32,
19005        0xfc000007, 0x20000003, &NMD::UDI              , 0,
19006        UDI_                },        /* UDI */
19007     { reserved_block      , 0                   , 0   , 32,
19008        0xfc000007, 0x20000004, 0                      , 0,
19009        0x0                 },        /* P32A~*(4) */
19010     { pool                , _POOL32A5           , 128 , 32,
19011        0xfc000007, 0x20000005, 0                      , 0,
19012        0x0                 },        /* _POOL32A5 */
19013     { reserved_block      , 0                   , 0   , 32,
19014        0xfc000007, 0x20000006, 0                      , 0,
19015        0x0                 },        /* P32A~*(6) */
19016     { pool                , _POOL32A7           , 8   , 32,
19017        0xfc000007, 0x20000007, 0                      , 0,
19018        0x0                 },        /* _POOL32A7 */
19019 };
19020
19021
19022 NMD::Pool NMD::P_GP_D[2] = {
19023     { instruction         , 0                   , 0   , 32,
19024        0xfc000007, 0x40000001, &NMD::LD_GP_           , 0,
19025        MIPS64_             },        /* LD[GP] */
19026     { instruction         , 0                   , 0   , 32,
19027        0xfc000007, 0x40000005, &NMD::SD_GP_           , 0,
19028        MIPS64_             },        /* SD[GP] */
19029 };
19030
19031
19032 NMD::Pool NMD::P_GP_W[4] = {
19033     { instruction         , 0                   , 0   , 32,
19034        0xfc000003, 0x40000000, &NMD::ADDIU_GP_W_      , 0,
19035        0x0                 },        /* ADDIU[GP.W] */
19036     { pool                , P_GP_D              , 2   , 32,
19037        0xfc000003, 0x40000001, 0                      , 0,
19038        0x0                 },        /* P.GP.D */
19039     { instruction         , 0                   , 0   , 32,
19040        0xfc000003, 0x40000002, &NMD::LW_GP_           , 0,
19041        0x0                 },        /* LW[GP] */
19042     { instruction         , 0                   , 0   , 32,
19043        0xfc000003, 0x40000003, &NMD::SW_GP_           , 0,
19044        0x0                 },        /* SW[GP] */
19045 };
19046
19047
19048 NMD::Pool NMD::POOL48I[32] = {
19049     { instruction         , 0                   , 0   , 48,
19050        0xfc1f00000000ull, 0x600000000000ull, &NMD::LI_48_           , 0,
19051        XMMS_               },        /* LI[48] */
19052     { instruction         , 0                   , 0   , 48,
19053        0xfc1f00000000ull, 0x600100000000ull, &NMD::ADDIU_48_        , 0,
19054        XMMS_               },        /* ADDIU[48] */
19055     { instruction         , 0                   , 0   , 48,
19056        0xfc1f00000000ull, 0x600200000000ull, &NMD::ADDIU_GP48_      , 0,
19057        XMMS_               },        /* ADDIU[GP48] */
19058     { instruction         , 0                   , 0   , 48,
19059        0xfc1f00000000ull, 0x600300000000ull, &NMD::ADDIUPC_48_      , 0,
19060        XMMS_               },        /* ADDIUPC[48] */
19061     { reserved_block      , 0                   , 0   , 48,
19062        0xfc1f00000000ull, 0x600400000000ull, 0                      , 0,
19063        0x0                 },        /* POOL48I~*(4) */
19064     { reserved_block      , 0                   , 0   , 48,
19065        0xfc1f00000000ull, 0x600500000000ull, 0                      , 0,
19066        0x0                 },        /* POOL48I~*(5) */
19067     { reserved_block      , 0                   , 0   , 48,
19068        0xfc1f00000000ull, 0x600600000000ull, 0                      , 0,
19069        0x0                 },        /* POOL48I~*(6) */
19070     { reserved_block      , 0                   , 0   , 48,
19071        0xfc1f00000000ull, 0x600700000000ull, 0                      , 0,
19072        0x0                 },        /* POOL48I~*(7) */
19073     { reserved_block      , 0                   , 0   , 48,
19074        0xfc1f00000000ull, 0x600800000000ull, 0                      , 0,
19075        0x0                 },        /* POOL48I~*(8) */
19076     { reserved_block      , 0                   , 0   , 48,
19077        0xfc1f00000000ull, 0x600900000000ull, 0                      , 0,
19078        0x0                 },        /* POOL48I~*(9) */
19079     { reserved_block      , 0                   , 0   , 48,
19080        0xfc1f00000000ull, 0x600a00000000ull, 0                      , 0,
19081        0x0                 },        /* POOL48I~*(10) */
19082     { instruction         , 0                   , 0   , 48,
19083        0xfc1f00000000ull, 0x600b00000000ull, &NMD::LWPC_48_         , 0,
19084        XMMS_               },        /* LWPC[48] */
19085     { reserved_block      , 0                   , 0   , 48,
19086        0xfc1f00000000ull, 0x600c00000000ull, 0                      , 0,
19087        0x0                 },        /* POOL48I~*(12) */
19088     { reserved_block      , 0                   , 0   , 48,
19089        0xfc1f00000000ull, 0x600d00000000ull, 0                      , 0,
19090        0x0                 },        /* POOL48I~*(13) */
19091     { reserved_block      , 0                   , 0   , 48,
19092        0xfc1f00000000ull, 0x600e00000000ull, 0                      , 0,
19093        0x0                 },        /* POOL48I~*(14) */
19094     { instruction         , 0                   , 0   , 48,
19095        0xfc1f00000000ull, 0x600f00000000ull, &NMD::SWPC_48_         , 0,
19096        XMMS_               },        /* SWPC[48] */
19097     { reserved_block      , 0                   , 0   , 48,
19098        0xfc1f00000000ull, 0x601000000000ull, 0                      , 0,
19099        0x0                 },        /* POOL48I~*(16) */
19100     { instruction         , 0                   , 0   , 48,
19101        0xfc1f00000000ull, 0x601100000000ull, &NMD::DADDIU_48_       , 0,
19102        MIPS64_             },        /* DADDIU[48] */
19103     { reserved_block      , 0                   , 0   , 48,
19104        0xfc1f00000000ull, 0x601200000000ull, 0                      , 0,
19105        0x0                 },        /* POOL48I~*(18) */
19106     { reserved_block      , 0                   , 0   , 48,
19107        0xfc1f00000000ull, 0x601300000000ull, 0                      , 0,
19108        0x0                 },        /* POOL48I~*(19) */
19109     { instruction         , 0                   , 0   , 48,
19110        0xfc1f00000000ull, 0x601400000000ull, &NMD::DLUI_48_         , 0,
19111        MIPS64_             },        /* DLUI[48] */
19112     { reserved_block      , 0                   , 0   , 48,
19113        0xfc1f00000000ull, 0x601500000000ull, 0                      , 0,
19114        0x0                 },        /* POOL48I~*(21) */
19115     { reserved_block      , 0                   , 0   , 48,
19116        0xfc1f00000000ull, 0x601600000000ull, 0                      , 0,
19117        0x0                 },        /* POOL48I~*(22) */
19118     { reserved_block      , 0                   , 0   , 48,
19119        0xfc1f00000000ull, 0x601700000000ull, 0                      , 0,
19120        0x0                 },        /* POOL48I~*(23) */
19121     { reserved_block      , 0                   , 0   , 48,
19122        0xfc1f00000000ull, 0x601800000000ull, 0                      , 0,
19123        0x0                 },        /* POOL48I~*(24) */
19124     { reserved_block      , 0                   , 0   , 48,
19125        0xfc1f00000000ull, 0x601900000000ull, 0                      , 0,
19126        0x0                 },        /* POOL48I~*(25) */
19127     { reserved_block      , 0                   , 0   , 48,
19128        0xfc1f00000000ull, 0x601a00000000ull, 0                      , 0,
19129        0x0                 },        /* POOL48I~*(26) */
19130     { instruction         , 0                   , 0   , 48,
19131        0xfc1f00000000ull, 0x601b00000000ull, &NMD::LDPC_48_         , 0,
19132        MIPS64_             },        /* LDPC[48] */
19133     { reserved_block      , 0                   , 0   , 48,
19134        0xfc1f00000000ull, 0x601c00000000ull, 0                      , 0,
19135        0x0                 },        /* POOL48I~*(28) */
19136     { reserved_block      , 0                   , 0   , 48,
19137        0xfc1f00000000ull, 0x601d00000000ull, 0                      , 0,
19138        0x0                 },        /* POOL48I~*(29) */
19139     { reserved_block      , 0                   , 0   , 48,
19140        0xfc1f00000000ull, 0x601e00000000ull, 0                      , 0,
19141        0x0                 },        /* POOL48I~*(30) */
19142     { instruction         , 0                   , 0   , 48,
19143        0xfc1f00000000ull, 0x601f00000000ull, &NMD::SDPC_48_         , 0,
19144        MIPS64_             },        /* SDPC[48] */
19145 };
19146
19147
19148 NMD::Pool NMD::PP_SR[4] = {
19149     { instruction         , 0                   , 0   , 32,
19150        0xfc10f003, 0x80003000, &NMD::SAVE_32_         , 0,
19151        0x0                 },        /* SAVE[32] */
19152     { reserved_block      , 0                   , 0   , 32,
19153        0xfc10f003, 0x80003001, 0                      , 0,
19154        0x0                 },        /* PP.SR~*(1) */
19155     { instruction         , 0                   , 0   , 32,
19156        0xfc10f003, 0x80003002, &NMD::RESTORE_32_      , 0,
19157        0x0                 },        /* RESTORE[32] */
19158     { return_instruction  , 0                   , 0   , 32,
19159        0xfc10f003, 0x80003003, &NMD::RESTORE_JRC_32_  , 0,
19160        0x0                 },        /* RESTORE.JRC[32] */
19161 };
19162
19163
19164 NMD::Pool NMD::P_SR_F[8] = {
19165     { instruction         , 0                   , 0   , 32,
19166        0xfc10f007, 0x80103000, &NMD::SAVEF            , 0,
19167        CP1_                },        /* SAVEF */
19168     { instruction         , 0                   , 0   , 32,
19169        0xfc10f007, 0x80103001, &NMD::RESTOREF         , 0,
19170        CP1_                },        /* RESTOREF */
19171     { reserved_block      , 0                   , 0   , 32,
19172        0xfc10f007, 0x80103002, 0                      , 0,
19173        0x0                 },        /* P.SR.F~*(2) */
19174     { reserved_block      , 0                   , 0   , 32,
19175        0xfc10f007, 0x80103003, 0                      , 0,
19176        0x0                 },        /* P.SR.F~*(3) */
19177     { reserved_block      , 0                   , 0   , 32,
19178        0xfc10f007, 0x80103004, 0                      , 0,
19179        0x0                 },        /* P.SR.F~*(4) */
19180     { reserved_block      , 0                   , 0   , 32,
19181        0xfc10f007, 0x80103005, 0                      , 0,
19182        0x0                 },        /* P.SR.F~*(5) */
19183     { reserved_block      , 0                   , 0   , 32,
19184        0xfc10f007, 0x80103006, 0                      , 0,
19185        0x0                 },        /* P.SR.F~*(6) */
19186     { reserved_block      , 0                   , 0   , 32,
19187        0xfc10f007, 0x80103007, 0                      , 0,
19188        0x0                 },        /* P.SR.F~*(7) */
19189 };
19190
19191
19192 NMD::Pool NMD::P_SR[2] = {
19193     { pool                , PP_SR               , 4   , 32,
19194        0xfc10f000, 0x80003000, 0                      , 0,
19195        0x0                 },        /* PP.SR */
19196     { pool                , P_SR_F              , 8   , 32,
19197        0xfc10f000, 0x80103000, 0                      , 0,
19198        0x0                 },        /* P.SR.F */
19199 };
19200
19201
19202 NMD::Pool NMD::P_SLL[5] = {
19203     { instruction         , 0                   , 0   , 32,
19204        0xffe0f1ff, 0x8000c000, &NMD::NOP_32_          , 0,
19205        0x0                 },        /* NOP[32] */
19206     { instruction         , 0                   , 0   , 32,
19207        0xffe0f1ff, 0x8000c003, &NMD::EHB              , 0,
19208        0x0                 },        /* EHB */
19209     { instruction         , 0                   , 0   , 32,
19210        0xffe0f1ff, 0x8000c005, &NMD::PAUSE            , 0,
19211        0x0                 },        /* PAUSE */
19212     { instruction         , 0                   , 0   , 32,
19213        0xffe0f1ff, 0x8000c006, &NMD::SYNC             , 0,
19214        0x0                 },        /* SYNC */
19215     { instruction         , 0                   , 0   , 32,
19216        0xfc00f1e0, 0x8000c000, &NMD::SLL_32_          , 0,
19217        0x0                 },        /* SLL[32] */
19218 };
19219
19220
19221 NMD::Pool NMD::P_SHIFT[16] = {
19222     { pool                , P_SLL               , 5   , 32,
19223        0xfc00f1e0, 0x8000c000, 0                      , 0,
19224        0x0                 },        /* P.SLL */
19225     { reserved_block      , 0                   , 0   , 32,
19226        0xfc00f1e0, 0x8000c020, 0                      , 0,
19227        0x0                 },        /* P.SHIFT~*(1) */
19228     { instruction         , 0                   , 0   , 32,
19229        0xfc00f1e0, 0x8000c040, &NMD::SRL_32_          , 0,
19230        0x0                 },        /* SRL[32] */
19231     { reserved_block      , 0                   , 0   , 32,
19232        0xfc00f1e0, 0x8000c060, 0                      , 0,
19233        0x0                 },        /* P.SHIFT~*(3) */
19234     { instruction         , 0                   , 0   , 32,
19235        0xfc00f1e0, 0x8000c080, &NMD::SRA              , 0,
19236        0x0                 },        /* SRA */
19237     { reserved_block      , 0                   , 0   , 32,
19238        0xfc00f1e0, 0x8000c0a0, 0                      , 0,
19239        0x0                 },        /* P.SHIFT~*(5) */
19240     { instruction         , 0                   , 0   , 32,
19241        0xfc00f1e0, 0x8000c0c0, &NMD::ROTR             , 0,
19242        0x0                 },        /* ROTR */
19243     { reserved_block      , 0                   , 0   , 32,
19244        0xfc00f1e0, 0x8000c0e0, 0                      , 0,
19245        0x0                 },        /* P.SHIFT~*(7) */
19246     { instruction         , 0                   , 0   , 32,
19247        0xfc00f1e0, 0x8000c100, &NMD::DSLL             , 0,
19248        MIPS64_             },        /* DSLL */
19249     { instruction         , 0                   , 0   , 32,
19250        0xfc00f1e0, 0x8000c120, &NMD::DSLL32           , 0,
19251        MIPS64_             },        /* DSLL32 */
19252     { instruction         , 0                   , 0   , 32,
19253        0xfc00f1e0, 0x8000c140, &NMD::DSRL             , 0,
19254        MIPS64_             },        /* DSRL */
19255     { instruction         , 0                   , 0   , 32,
19256        0xfc00f1e0, 0x8000c160, &NMD::DSRL32           , 0,
19257        MIPS64_             },        /* DSRL32 */
19258     { instruction         , 0                   , 0   , 32,
19259        0xfc00f1e0, 0x8000c180, &NMD::DSRA             , 0,
19260        MIPS64_             },        /* DSRA */
19261     { instruction         , 0                   , 0   , 32,
19262        0xfc00f1e0, 0x8000c1a0, &NMD::DSRA32           , 0,
19263        MIPS64_             },        /* DSRA32 */
19264     { instruction         , 0                   , 0   , 32,
19265        0xfc00f1e0, 0x8000c1c0, &NMD::DROTR            , 0,
19266        MIPS64_             },        /* DROTR */
19267     { instruction         , 0                   , 0   , 32,
19268        0xfc00f1e0, 0x8000c1e0, &NMD::DROTR32          , 0,
19269        MIPS64_             },        /* DROTR32 */
19270 };
19271
19272
19273 NMD::Pool NMD::P_ROTX[4] = {
19274     { instruction         , 0                   , 0   , 32,
19275        0xfc00f820, 0x8000d000, &NMD::ROTX             , 0,
19276        XMMS_               },        /* ROTX */
19277     { reserved_block      , 0                   , 0   , 32,
19278        0xfc00f820, 0x8000d020, 0                      , 0,
19279        0x0                 },        /* P.ROTX~*(1) */
19280     { reserved_block      , 0                   , 0   , 32,
19281        0xfc00f820, 0x8000d800, 0                      , 0,
19282        0x0                 },        /* P.ROTX~*(2) */
19283     { reserved_block      , 0                   , 0   , 32,
19284        0xfc00f820, 0x8000d820, 0                      , 0,
19285        0x0                 },        /* P.ROTX~*(3) */
19286 };
19287
19288
19289 NMD::Pool NMD::P_INS[4] = {
19290     { instruction         , 0                   , 0   , 32,
19291        0xfc00f820, 0x8000e000, &NMD::INS              , 0,
19292        XMMS_               },        /* INS */
19293     { instruction         , 0                   , 0   , 32,
19294        0xfc00f820, 0x8000e020, &NMD::DINSU            , 0,
19295        MIPS64_             },        /* DINSU */
19296     { instruction         , 0                   , 0   , 32,
19297        0xfc00f820, 0x8000e800, &NMD::DINSM            , 0,
19298        MIPS64_             },        /* DINSM */
19299     { instruction         , 0                   , 0   , 32,
19300        0xfc00f820, 0x8000e820, &NMD::DINS             , 0,
19301        MIPS64_             },        /* DINS */
19302 };
19303
19304
19305 NMD::Pool NMD::P_EXT[4] = {
19306     { instruction         , 0                   , 0   , 32,
19307        0xfc00f820, 0x8000f000, &NMD::EXT              , 0,
19308        XMMS_               },        /* EXT */
19309     { instruction         , 0                   , 0   , 32,
19310        0xfc00f820, 0x8000f020, &NMD::DEXTU            , 0,
19311        MIPS64_             },        /* DEXTU */
19312     { instruction         , 0                   , 0   , 32,
19313        0xfc00f820, 0x8000f800, &NMD::DEXTM            , 0,
19314        MIPS64_             },        /* DEXTM */
19315     { instruction         , 0                   , 0   , 32,
19316        0xfc00f820, 0x8000f820, &NMD::DEXT             , 0,
19317        MIPS64_             },        /* DEXT */
19318 };
19319
19320
19321 NMD::Pool NMD::P_U12[16] = {
19322     { instruction         , 0                   , 0   , 32,
19323        0xfc00f000, 0x80000000, &NMD::ORI              , 0,
19324        0x0                 },        /* ORI */
19325     { instruction         , 0                   , 0   , 32,
19326        0xfc00f000, 0x80001000, &NMD::XORI             , 0,
19327        0x0                 },        /* XORI */
19328     { instruction         , 0                   , 0   , 32,
19329        0xfc00f000, 0x80002000, &NMD::ANDI_32_         , 0,
19330        0x0                 },        /* ANDI[32] */
19331     { pool                , P_SR                , 2   , 32,
19332        0xfc00f000, 0x80003000, 0                      , 0,
19333        0x0                 },        /* P.SR */
19334     { instruction         , 0                   , 0   , 32,
19335        0xfc00f000, 0x80004000, &NMD::SLTI             , 0,
19336        0x0                 },        /* SLTI */
19337     { instruction         , 0                   , 0   , 32,
19338        0xfc00f000, 0x80005000, &NMD::SLTIU            , 0,
19339        0x0                 },        /* SLTIU */
19340     { instruction         , 0                   , 0   , 32,
19341        0xfc00f000, 0x80006000, &NMD::SEQI             , 0,
19342        0x0                 },        /* SEQI */
19343     { reserved_block      , 0                   , 0   , 32,
19344        0xfc00f000, 0x80007000, 0                      , 0,
19345        0x0                 },        /* P.U12~*(7) */
19346     { instruction         , 0                   , 0   , 32,
19347        0xfc00f000, 0x80008000, &NMD::ADDIU_NEG_       , 0,
19348        0x0                 },        /* ADDIU[NEG] */
19349     { instruction         , 0                   , 0   , 32,
19350        0xfc00f000, 0x80009000, &NMD::DADDIU_U12_      , 0,
19351        MIPS64_             },        /* DADDIU[U12] */
19352     { instruction         , 0                   , 0   , 32,
19353        0xfc00f000, 0x8000a000, &NMD::DADDIU_NEG_      , 0,
19354        MIPS64_             },        /* DADDIU[NEG] */
19355     { instruction         , 0                   , 0   , 32,
19356        0xfc00f000, 0x8000b000, &NMD::DROTX            , 0,
19357        MIPS64_             },        /* DROTX */
19358     { pool                , P_SHIFT             , 16  , 32,
19359        0xfc00f000, 0x8000c000, 0                      , 0,
19360        0x0                 },        /* P.SHIFT */
19361     { pool                , P_ROTX              , 4   , 32,
19362        0xfc00f000, 0x8000d000, 0                      , 0,
19363        0x0                 },        /* P.ROTX */
19364     { pool                , P_INS               , 4   , 32,
19365        0xfc00f000, 0x8000e000, 0                      , 0,
19366        0x0                 },        /* P.INS */
19367     { pool                , P_EXT               , 4   , 32,
19368        0xfc00f000, 0x8000f000, 0                      , 0,
19369        0x0                 },        /* P.EXT */
19370 };
19371
19372
19373 NMD::Pool NMD::RINT_fmt[2] = {
19374     { instruction         , 0                   , 0   , 32,
19375        0xfc0003ff, 0xa0000020, &NMD::RINT_S           , 0,
19376        CP1_                },        /* RINT.S */
19377     { instruction         , 0                   , 0   , 32,
19378        0xfc0003ff, 0xa0000220, &NMD::RINT_D           , 0,
19379        CP1_                },        /* RINT.D */
19380 };
19381
19382
19383 NMD::Pool NMD::ADD_fmt0[2] = {
19384     { instruction         , 0                   , 0   , 32,
19385        0xfc0003ff, 0xa0000030, &NMD::ADD_S            , 0,
19386        CP1_                },        /* ADD.S */
19387     { reserved_block      , 0                   , 0   , 32,
19388        0xfc0003ff, 0xa0000230, 0                      , 0,
19389        CP1_                },        /* ADD.fmt0~*(1) */
19390 };
19391
19392
19393 NMD::Pool NMD::SELEQZ_fmt[2] = {
19394     { instruction         , 0                   , 0   , 32,
19395        0xfc0003ff, 0xa0000038, &NMD::SELEQZ_S         , 0,
19396        CP1_                },        /* SELEQZ.S */
19397     { instruction         , 0                   , 0   , 32,
19398        0xfc0003ff, 0xa0000238, &NMD::SELEQZ_D         , 0,
19399        CP1_                },        /* SELEQZ.D */
19400 };
19401
19402
19403 NMD::Pool NMD::CLASS_fmt[2] = {
19404     { instruction         , 0                   , 0   , 32,
19405        0xfc0003ff, 0xa0000060, &NMD::CLASS_S          , 0,
19406        CP1_                },        /* CLASS.S */
19407     { instruction         , 0                   , 0   , 32,
19408        0xfc0003ff, 0xa0000260, &NMD::CLASS_D          , 0,
19409        CP1_                },        /* CLASS.D */
19410 };
19411
19412
19413 NMD::Pool NMD::SUB_fmt0[2] = {
19414     { instruction         , 0                   , 0   , 32,
19415        0xfc0003ff, 0xa0000070, &NMD::SUB_S            , 0,
19416        CP1_                },        /* SUB.S */
19417     { reserved_block      , 0                   , 0   , 32,
19418        0xfc0003ff, 0xa0000270, 0                      , 0,
19419        CP1_                },        /* SUB.fmt0~*(1) */
19420 };
19421
19422
19423 NMD::Pool NMD::SELNEZ_fmt[2] = {
19424     { instruction         , 0                   , 0   , 32,
19425        0xfc0003ff, 0xa0000078, &NMD::SELNEZ_S         , 0,
19426        CP1_                },        /* SELNEZ.S */
19427     { instruction         , 0                   , 0   , 32,
19428        0xfc0003ff, 0xa0000278, &NMD::SELNEZ_D         , 0,
19429        CP1_                },        /* SELNEZ.D */
19430 };
19431
19432
19433 NMD::Pool NMD::MUL_fmt0[2] = {
19434     { instruction         , 0                   , 0   , 32,
19435        0xfc0003ff, 0xa00000b0, &NMD::MUL_S            , 0,
19436        CP1_                },        /* MUL.S */
19437     { reserved_block      , 0                   , 0   , 32,
19438        0xfc0003ff, 0xa00002b0, 0                      , 0,
19439        CP1_                },        /* MUL.fmt0~*(1) */
19440 };
19441
19442
19443 NMD::Pool NMD::SEL_fmt[2] = {
19444     { instruction         , 0                   , 0   , 32,
19445        0xfc0003ff, 0xa00000b8, &NMD::SEL_S            , 0,
19446        CP1_                },        /* SEL.S */
19447     { instruction         , 0                   , 0   , 32,
19448        0xfc0003ff, 0xa00002b8, &NMD::SEL_D            , 0,
19449        CP1_                },        /* SEL.D */
19450 };
19451
19452
19453 NMD::Pool NMD::DIV_fmt0[2] = {
19454     { instruction         , 0                   , 0   , 32,
19455        0xfc0003ff, 0xa00000f0, &NMD::DIV_S            , 0,
19456        CP1_                },        /* DIV.S */
19457     { reserved_block      , 0                   , 0   , 32,
19458        0xfc0003ff, 0xa00002f0, 0                      , 0,
19459        CP1_                },        /* DIV.fmt0~*(1) */
19460 };
19461
19462
19463 NMD::Pool NMD::ADD_fmt1[2] = {
19464     { instruction         , 0                   , 0   , 32,
19465        0xfc0003ff, 0xa0000130, &NMD::ADD_D            , 0,
19466        CP1_                },        /* ADD.D */
19467     { reserved_block      , 0                   , 0   , 32,
19468        0xfc0003ff, 0xa0000330, 0                      , 0,
19469        CP1_                },        /* ADD.fmt1~*(1) */
19470 };
19471
19472
19473 NMD::Pool NMD::SUB_fmt1[2] = {
19474     { instruction         , 0                   , 0   , 32,
19475        0xfc0003ff, 0xa0000170, &NMD::SUB_D            , 0,
19476        CP1_                },        /* SUB.D */
19477     { reserved_block      , 0                   , 0   , 32,
19478        0xfc0003ff, 0xa0000370, 0                      , 0,
19479        CP1_                },        /* SUB.fmt1~*(1) */
19480 };
19481
19482
19483 NMD::Pool NMD::MUL_fmt1[2] = {
19484     { instruction         , 0                   , 0   , 32,
19485        0xfc0003ff, 0xa00001b0, &NMD::MUL_D            , 0,
19486        CP1_                },        /* MUL.D */
19487     { reserved_block      , 0                   , 0   , 32,
19488        0xfc0003ff, 0xa00003b0, 0                      , 0,
19489        CP1_                },        /* MUL.fmt1~*(1) */
19490 };
19491
19492
19493 NMD::Pool NMD::MADDF_fmt[2] = {
19494     { instruction         , 0                   , 0   , 32,
19495        0xfc0003ff, 0xa00001b8, &NMD::MADDF_S          , 0,
19496        CP1_                },        /* MADDF.S */
19497     { instruction         , 0                   , 0   , 32,
19498        0xfc0003ff, 0xa00003b8, &NMD::MADDF_D          , 0,
19499        CP1_                },        /* MADDF.D */
19500 };
19501
19502
19503 NMD::Pool NMD::DIV_fmt1[2] = {
19504     { instruction         , 0                   , 0   , 32,
19505        0xfc0003ff, 0xa00001f0, &NMD::DIV_D            , 0,
19506        CP1_                },        /* DIV.D */
19507     { reserved_block      , 0                   , 0   , 32,
19508        0xfc0003ff, 0xa00003f0, 0                      , 0,
19509        CP1_                },        /* DIV.fmt1~*(1) */
19510 };
19511
19512
19513 NMD::Pool NMD::MSUBF_fmt[2] = {
19514     { instruction         , 0                   , 0   , 32,
19515        0xfc0003ff, 0xa00001f8, &NMD::MSUBF_S          , 0,
19516        CP1_                },        /* MSUBF.S */
19517     { instruction         , 0                   , 0   , 32,
19518        0xfc0003ff, 0xa00003f8, &NMD::MSUBF_D          , 0,
19519        CP1_                },        /* MSUBF.D */
19520 };
19521
19522
19523 NMD::Pool NMD::POOL32F_0[64] = {
19524     { reserved_block      , 0                   , 0   , 32,
19525        0xfc0001ff, 0xa0000000, 0                      , 0,
19526        CP1_                },        /* POOL32F_0~*(0) */
19527     { reserved_block      , 0                   , 0   , 32,
19528        0xfc0001ff, 0xa0000008, 0                      , 0,
19529        CP1_                },        /* POOL32F_0~*(1) */
19530     { reserved_block      , 0                   , 0   , 32,
19531        0xfc0001ff, 0xa0000010, 0                      , 0,
19532        CP1_                },        /* POOL32F_0~*(2) */
19533     { reserved_block      , 0                   , 0   , 32,
19534        0xfc0001ff, 0xa0000018, 0                      , 0,
19535        CP1_                },        /* POOL32F_0~*(3) */
19536     { pool                , RINT_fmt            , 2   , 32,
19537        0xfc0001ff, 0xa0000020, 0                      , 0,
19538        CP1_                },        /* RINT.fmt */
19539     { reserved_block      , 0                   , 0   , 32,
19540        0xfc0001ff, 0xa0000028, 0                      , 0,
19541        CP1_                },        /* POOL32F_0~*(5) */
19542     { pool                , ADD_fmt0            , 2   , 32,
19543        0xfc0001ff, 0xa0000030, 0                      , 0,
19544        CP1_                },        /* ADD.fmt0 */
19545     { pool                , SELEQZ_fmt          , 2   , 32,
19546        0xfc0001ff, 0xa0000038, 0                      , 0,
19547        CP1_                },        /* SELEQZ.fmt */
19548     { reserved_block      , 0                   , 0   , 32,
19549        0xfc0001ff, 0xa0000040, 0                      , 0,
19550        CP1_                },        /* POOL32F_0~*(8) */
19551     { reserved_block      , 0                   , 0   , 32,
19552        0xfc0001ff, 0xa0000048, 0                      , 0,
19553        CP1_                },        /* POOL32F_0~*(9) */
19554     { reserved_block      , 0                   , 0   , 32,
19555        0xfc0001ff, 0xa0000050, 0                      , 0,
19556        CP1_                },        /* POOL32F_0~*(10) */
19557     { reserved_block      , 0                   , 0   , 32,
19558        0xfc0001ff, 0xa0000058, 0                      , 0,
19559        CP1_                },        /* POOL32F_0~*(11) */
19560     { pool                , CLASS_fmt           , 2   , 32,
19561        0xfc0001ff, 0xa0000060, 0                      , 0,
19562        CP1_                },        /* CLASS.fmt */
19563     { reserved_block      , 0                   , 0   , 32,
19564        0xfc0001ff, 0xa0000068, 0                      , 0,
19565        CP1_                },        /* POOL32F_0~*(13) */
19566     { pool                , SUB_fmt0            , 2   , 32,
19567        0xfc0001ff, 0xa0000070, 0                      , 0,
19568        CP1_                },        /* SUB.fmt0 */
19569     { pool                , SELNEZ_fmt          , 2   , 32,
19570        0xfc0001ff, 0xa0000078, 0                      , 0,
19571        CP1_                },        /* SELNEZ.fmt */
19572     { reserved_block      , 0                   , 0   , 32,
19573        0xfc0001ff, 0xa0000080, 0                      , 0,
19574        CP1_                },        /* POOL32F_0~*(16) */
19575     { reserved_block      , 0                   , 0   , 32,
19576        0xfc0001ff, 0xa0000088, 0                      , 0,
19577        CP1_                },        /* POOL32F_0~*(17) */
19578     { reserved_block      , 0                   , 0   , 32,
19579        0xfc0001ff, 0xa0000090, 0                      , 0,
19580        CP1_                },        /* POOL32F_0~*(18) */
19581     { reserved_block      , 0                   , 0   , 32,
19582        0xfc0001ff, 0xa0000098, 0                      , 0,
19583        CP1_                },        /* POOL32F_0~*(19) */
19584     { reserved_block      , 0                   , 0   , 32,
19585        0xfc0001ff, 0xa00000a0, 0                      , 0,
19586        CP1_                },        /* POOL32F_0~*(20) */
19587     { reserved_block      , 0                   , 0   , 32,
19588        0xfc0001ff, 0xa00000a8, 0                      , 0,
19589        CP1_                },        /* POOL32F_0~*(21) */
19590     { pool                , MUL_fmt0            , 2   , 32,
19591        0xfc0001ff, 0xa00000b0, 0                      , 0,
19592        CP1_                },        /* MUL.fmt0 */
19593     { pool                , SEL_fmt             , 2   , 32,
19594        0xfc0001ff, 0xa00000b8, 0                      , 0,
19595        CP1_                },        /* SEL.fmt */
19596     { reserved_block      , 0                   , 0   , 32,
19597        0xfc0001ff, 0xa00000c0, 0                      , 0,
19598        CP1_                },        /* POOL32F_0~*(24) */
19599     { reserved_block      , 0                   , 0   , 32,
19600        0xfc0001ff, 0xa00000c8, 0                      , 0,
19601        CP1_                },        /* POOL32F_0~*(25) */
19602     { reserved_block      , 0                   , 0   , 32,
19603        0xfc0001ff, 0xa00000d0, 0                      , 0,
19604        CP1_                },        /* POOL32F_0~*(26) */
19605     { reserved_block      , 0                   , 0   , 32,
19606        0xfc0001ff, 0xa00000d8, 0                      , 0,
19607        CP1_                },        /* POOL32F_0~*(27) */
19608     { reserved_block      , 0                   , 0   , 32,
19609        0xfc0001ff, 0xa00000e0, 0                      , 0,
19610        CP1_                },        /* POOL32F_0~*(28) */
19611     { reserved_block      , 0                   , 0   , 32,
19612        0xfc0001ff, 0xa00000e8, 0                      , 0,
19613        CP1_                },        /* POOL32F_0~*(29) */
19614     { pool                , DIV_fmt0            , 2   , 32,
19615        0xfc0001ff, 0xa00000f0, 0                      , 0,
19616        CP1_                },        /* DIV.fmt0 */
19617     { reserved_block      , 0                   , 0   , 32,
19618        0xfc0001ff, 0xa00000f8, 0                      , 0,
19619        CP1_                },        /* POOL32F_0~*(31) */
19620     { reserved_block      , 0                   , 0   , 32,
19621        0xfc0001ff, 0xa0000100, 0                      , 0,
19622        CP1_                },        /* POOL32F_0~*(32) */
19623     { reserved_block      , 0                   , 0   , 32,
19624        0xfc0001ff, 0xa0000108, 0                      , 0,
19625        CP1_                },        /* POOL32F_0~*(33) */
19626     { reserved_block      , 0                   , 0   , 32,
19627        0xfc0001ff, 0xa0000110, 0                      , 0,
19628        CP1_                },        /* POOL32F_0~*(34) */
19629     { reserved_block      , 0                   , 0   , 32,
19630        0xfc0001ff, 0xa0000118, 0                      , 0,
19631        CP1_                },        /* POOL32F_0~*(35) */
19632     { reserved_block      , 0                   , 0   , 32,
19633        0xfc0001ff, 0xa0000120, 0                      , 0,
19634        CP1_                },        /* POOL32F_0~*(36) */
19635     { reserved_block      , 0                   , 0   , 32,
19636        0xfc0001ff, 0xa0000128, 0                      , 0,
19637        CP1_                },        /* POOL32F_0~*(37) */
19638     { pool                , ADD_fmt1            , 2   , 32,
19639        0xfc0001ff, 0xa0000130, 0                      , 0,
19640        CP1_                },        /* ADD.fmt1 */
19641     { reserved_block      , 0                   , 0   , 32,
19642        0xfc0001ff, 0xa0000138, 0                      , 0,
19643        CP1_                },        /* POOL32F_0~*(39) */
19644     { reserved_block      , 0                   , 0   , 32,
19645        0xfc0001ff, 0xa0000140, 0                      , 0,
19646        CP1_                },        /* POOL32F_0~*(40) */
19647     { reserved_block      , 0                   , 0   , 32,
19648        0xfc0001ff, 0xa0000148, 0                      , 0,
19649        CP1_                },        /* POOL32F_0~*(41) */
19650     { reserved_block      , 0                   , 0   , 32,
19651        0xfc0001ff, 0xa0000150, 0                      , 0,
19652        CP1_                },        /* POOL32F_0~*(42) */
19653     { reserved_block      , 0                   , 0   , 32,
19654        0xfc0001ff, 0xa0000158, 0                      , 0,
19655        CP1_                },        /* POOL32F_0~*(43) */
19656     { reserved_block      , 0                   , 0   , 32,
19657        0xfc0001ff, 0xa0000160, 0                      , 0,
19658        CP1_                },        /* POOL32F_0~*(44) */
19659     { reserved_block      , 0                   , 0   , 32,
19660        0xfc0001ff, 0xa0000168, 0                      , 0,
19661        CP1_                },        /* POOL32F_0~*(45) */
19662     { pool                , SUB_fmt1            , 2   , 32,
19663        0xfc0001ff, 0xa0000170, 0                      , 0,
19664        CP1_                },        /* SUB.fmt1 */
19665     { reserved_block      , 0                   , 0   , 32,
19666        0xfc0001ff, 0xa0000178, 0                      , 0,
19667        CP1_                },        /* POOL32F_0~*(47) */
19668     { reserved_block      , 0                   , 0   , 32,
19669        0xfc0001ff, 0xa0000180, 0                      , 0,
19670        CP1_                },        /* POOL32F_0~*(48) */
19671     { reserved_block      , 0                   , 0   , 32,
19672        0xfc0001ff, 0xa0000188, 0                      , 0,
19673        CP1_                },        /* POOL32F_0~*(49) */
19674     { reserved_block      , 0                   , 0   , 32,
19675        0xfc0001ff, 0xa0000190, 0                      , 0,
19676        CP1_                },        /* POOL32F_0~*(50) */
19677     { reserved_block      , 0                   , 0   , 32,
19678        0xfc0001ff, 0xa0000198, 0                      , 0,
19679        CP1_                },        /* POOL32F_0~*(51) */
19680     { reserved_block      , 0                   , 0   , 32,
19681        0xfc0001ff, 0xa00001a0, 0                      , 0,
19682        CP1_                },        /* POOL32F_0~*(52) */
19683     { reserved_block      , 0                   , 0   , 32,
19684        0xfc0001ff, 0xa00001a8, 0                      , 0,
19685        CP1_                },        /* POOL32F_0~*(53) */
19686     { pool                , MUL_fmt1            , 2   , 32,
19687        0xfc0001ff, 0xa00001b0, 0                      , 0,
19688        CP1_                },        /* MUL.fmt1 */
19689     { pool                , MADDF_fmt           , 2   , 32,
19690        0xfc0001ff, 0xa00001b8, 0                      , 0,
19691        CP1_                },        /* MADDF.fmt */
19692     { reserved_block      , 0                   , 0   , 32,
19693        0xfc0001ff, 0xa00001c0, 0                      , 0,
19694        CP1_                },        /* POOL32F_0~*(56) */
19695     { reserved_block      , 0                   , 0   , 32,
19696        0xfc0001ff, 0xa00001c8, 0                      , 0,
19697        CP1_                },        /* POOL32F_0~*(57) */
19698     { reserved_block      , 0                   , 0   , 32,
19699        0xfc0001ff, 0xa00001d0, 0                      , 0,
19700        CP1_                },        /* POOL32F_0~*(58) */
19701     { reserved_block      , 0                   , 0   , 32,
19702        0xfc0001ff, 0xa00001d8, 0                      , 0,
19703        CP1_                },        /* POOL32F_0~*(59) */
19704     { reserved_block      , 0                   , 0   , 32,
19705        0xfc0001ff, 0xa00001e0, 0                      , 0,
19706        CP1_                },        /* POOL32F_0~*(60) */
19707     { reserved_block      , 0                   , 0   , 32,
19708        0xfc0001ff, 0xa00001e8, 0                      , 0,
19709        CP1_                },        /* POOL32F_0~*(61) */
19710     { pool                , DIV_fmt1            , 2   , 32,
19711        0xfc0001ff, 0xa00001f0, 0                      , 0,
19712        CP1_                },        /* DIV.fmt1 */
19713     { pool                , MSUBF_fmt           , 2   , 32,
19714        0xfc0001ff, 0xa00001f8, 0                      , 0,
19715        CP1_                },        /* MSUBF.fmt */
19716 };
19717
19718
19719 NMD::Pool NMD::MIN_fmt[2] = {
19720     { instruction         , 0                   , 0   , 32,
19721        0xfc00023f, 0xa0000003, &NMD::MIN_S            , 0,
19722        CP1_                },        /* MIN.S */
19723     { instruction         , 0                   , 0   , 32,
19724        0xfc00023f, 0xa0000203, &NMD::MIN_D            , 0,
19725        CP1_                },        /* MIN.D */
19726 };
19727
19728
19729 NMD::Pool NMD::MAX_fmt[2] = {
19730     { instruction         , 0                   , 0   , 32,
19731        0xfc00023f, 0xa000000b, &NMD::MAX_S            , 0,
19732        CP1_                },        /* MAX.S */
19733     { instruction         , 0                   , 0   , 32,
19734        0xfc00023f, 0xa000020b, &NMD::MAX_D            , 0,
19735        CP1_                },        /* MAX.D */
19736 };
19737
19738
19739 NMD::Pool NMD::MINA_fmt[2] = {
19740     { instruction         , 0                   , 0   , 32,
19741        0xfc00023f, 0xa0000023, &NMD::MINA_S           , 0,
19742        CP1_                },        /* MINA.S */
19743     { instruction         , 0                   , 0   , 32,
19744        0xfc00023f, 0xa0000223, &NMD::MINA_D           , 0,
19745        CP1_                },        /* MINA.D */
19746 };
19747
19748
19749 NMD::Pool NMD::MAXA_fmt[2] = {
19750     { instruction         , 0                   , 0   , 32,
19751        0xfc00023f, 0xa000002b, &NMD::MAXA_S           , 0,
19752        CP1_                },        /* MAXA.S */
19753     { instruction         , 0                   , 0   , 32,
19754        0xfc00023f, 0xa000022b, &NMD::MAXA_D           , 0,
19755        CP1_                },        /* MAXA.D */
19756 };
19757
19758
19759 NMD::Pool NMD::CVT_L_fmt[2] = {
19760     { instruction         , 0                   , 0   , 32,
19761        0xfc007fff, 0xa000013b, &NMD::CVT_L_S          , 0,
19762        CP1_                },        /* CVT.L.S */
19763     { instruction         , 0                   , 0   , 32,
19764        0xfc007fff, 0xa000413b, &NMD::CVT_L_D          , 0,
19765        CP1_                },        /* CVT.L.D */
19766 };
19767
19768
19769 NMD::Pool NMD::RSQRT_fmt[2] = {
19770     { instruction         , 0                   , 0   , 32,
19771        0xfc007fff, 0xa000023b, &NMD::RSQRT_S          , 0,
19772        CP1_                },        /* RSQRT.S */
19773     { instruction         , 0                   , 0   , 32,
19774        0xfc007fff, 0xa000423b, &NMD::RSQRT_D          , 0,
19775        CP1_                },        /* RSQRT.D */
19776 };
19777
19778
19779 NMD::Pool NMD::FLOOR_L_fmt[2] = {
19780     { instruction         , 0                   , 0   , 32,
19781        0xfc007fff, 0xa000033b, &NMD::FLOOR_L_S        , 0,
19782        CP1_                },        /* FLOOR.L.S */
19783     { instruction         , 0                   , 0   , 32,
19784        0xfc007fff, 0xa000433b, &NMD::FLOOR_L_D        , 0,
19785        CP1_                },        /* FLOOR.L.D */
19786 };
19787
19788
19789 NMD::Pool NMD::CVT_W_fmt[2] = {
19790     { instruction         , 0                   , 0   , 32,
19791        0xfc007fff, 0xa000093b, &NMD::CVT_W_S          , 0,
19792        CP1_                },        /* CVT.W.S */
19793     { instruction         , 0                   , 0   , 32,
19794        0xfc007fff, 0xa000493b, &NMD::CVT_W_D          , 0,
19795        CP1_                },        /* CVT.W.D */
19796 };
19797
19798
19799 NMD::Pool NMD::SQRT_fmt[2] = {
19800     { instruction         , 0                   , 0   , 32,
19801        0xfc007fff, 0xa0000a3b, &NMD::SQRT_S           , 0,
19802        CP1_                },        /* SQRT.S */
19803     { instruction         , 0                   , 0   , 32,
19804        0xfc007fff, 0xa0004a3b, &NMD::SQRT_D           , 0,
19805        CP1_                },        /* SQRT.D */
19806 };
19807
19808
19809 NMD::Pool NMD::FLOOR_W_fmt[2] = {
19810     { instruction         , 0                   , 0   , 32,
19811        0xfc007fff, 0xa0000b3b, &NMD::FLOOR_W_S        , 0,
19812        CP1_                },        /* FLOOR.W.S */
19813     { instruction         , 0                   , 0   , 32,
19814        0xfc007fff, 0xa0004b3b, &NMD::FLOOR_W_D        , 0,
19815        CP1_                },        /* FLOOR.W.D */
19816 };
19817
19818
19819 NMD::Pool NMD::RECIP_fmt[2] = {
19820     { instruction         , 0                   , 0   , 32,
19821        0xfc007fff, 0xa000123b, &NMD::RECIP_S          , 0,
19822        CP1_                },        /* RECIP.S */
19823     { instruction         , 0                   , 0   , 32,
19824        0xfc007fff, 0xa000523b, &NMD::RECIP_D          , 0,
19825        CP1_                },        /* RECIP.D */
19826 };
19827
19828
19829 NMD::Pool NMD::CEIL_L_fmt[2] = {
19830     { instruction         , 0                   , 0   , 32,
19831        0xfc007fff, 0xa000133b, &NMD::CEIL_L_S         , 0,
19832        CP1_                },        /* CEIL.L.S */
19833     { instruction         , 0                   , 0   , 32,
19834        0xfc007fff, 0xa000533b, &NMD::CEIL_L_D         , 0,
19835        CP1_                },        /* CEIL.L.D */
19836 };
19837
19838
19839 NMD::Pool NMD::CEIL_W_fmt[2] = {
19840     { instruction         , 0                   , 0   , 32,
19841        0xfc007fff, 0xa0001b3b, &NMD::CEIL_W_S         , 0,
19842        CP1_                },        /* CEIL.W.S */
19843     { instruction         , 0                   , 0   , 32,
19844        0xfc007fff, 0xa0005b3b, &NMD::CEIL_W_D         , 0,
19845        CP1_                },        /* CEIL.W.D */
19846 };
19847
19848
19849 NMD::Pool NMD::TRUNC_L_fmt[2] = {
19850     { instruction         , 0                   , 0   , 32,
19851        0xfc007fff, 0xa000233b, &NMD::TRUNC_L_S        , 0,
19852        CP1_                },        /* TRUNC.L.S */
19853     { instruction         , 0                   , 0   , 32,
19854        0xfc007fff, 0xa000633b, &NMD::TRUNC_L_D        , 0,
19855        CP1_                },        /* TRUNC.L.D */
19856 };
19857
19858
19859 NMD::Pool NMD::TRUNC_W_fmt[2] = {
19860     { instruction         , 0                   , 0   , 32,
19861        0xfc007fff, 0xa0002b3b, &NMD::TRUNC_W_S        , 0,
19862        CP1_                },        /* TRUNC.W.S */
19863     { instruction         , 0                   , 0   , 32,
19864        0xfc007fff, 0xa0006b3b, &NMD::TRUNC_W_D        , 0,
19865        CP1_                },        /* TRUNC.W.D */
19866 };
19867
19868
19869 NMD::Pool NMD::ROUND_L_fmt[2] = {
19870     { instruction         , 0                   , 0   , 32,
19871        0xfc007fff, 0xa000333b, &NMD::ROUND_L_S        , 0,
19872        CP1_                },        /* ROUND.L.S */
19873     { instruction         , 0                   , 0   , 32,
19874        0xfc007fff, 0xa000733b, &NMD::ROUND_L_D        , 0,
19875        CP1_                },        /* ROUND.L.D */
19876 };
19877
19878
19879 NMD::Pool NMD::ROUND_W_fmt[2] = {
19880     { instruction         , 0                   , 0   , 32,
19881        0xfc007fff, 0xa0003b3b, &NMD::ROUND_W_S        , 0,
19882        CP1_                },        /* ROUND.W.S */
19883     { instruction         , 0                   , 0   , 32,
19884        0xfc007fff, 0xa0007b3b, &NMD::ROUND_W_D        , 0,
19885        CP1_                },        /* ROUND.W.D */
19886 };
19887
19888
19889 NMD::Pool NMD::POOL32Fxf_0[64] = {
19890     { reserved_block      , 0                   , 0   , 32,
19891        0xfc003fff, 0xa000003b, 0                      , 0,
19892        CP1_                },        /* POOL32Fxf_0~*(0) */
19893     { pool                , CVT_L_fmt           , 2   , 32,
19894        0xfc003fff, 0xa000013b, 0                      , 0,
19895        CP1_                },        /* CVT.L.fmt */
19896     { pool                , RSQRT_fmt           , 2   , 32,
19897        0xfc003fff, 0xa000023b, 0                      , 0,
19898        CP1_                },        /* RSQRT.fmt */
19899     { pool                , FLOOR_L_fmt         , 2   , 32,
19900        0xfc003fff, 0xa000033b, 0                      , 0,
19901        CP1_                },        /* FLOOR.L.fmt */
19902     { reserved_block      , 0                   , 0   , 32,
19903        0xfc003fff, 0xa000043b, 0                      , 0,
19904        CP1_                },        /* POOL32Fxf_0~*(4) */
19905     { reserved_block      , 0                   , 0   , 32,
19906        0xfc003fff, 0xa000053b, 0                      , 0,
19907        CP1_                },        /* POOL32Fxf_0~*(5) */
19908     { reserved_block      , 0                   , 0   , 32,
19909        0xfc003fff, 0xa000063b, 0                      , 0,
19910        CP1_                },        /* POOL32Fxf_0~*(6) */
19911     { reserved_block      , 0                   , 0   , 32,
19912        0xfc003fff, 0xa000073b, 0                      , 0,
19913        CP1_                },        /* POOL32Fxf_0~*(7) */
19914     { reserved_block      , 0                   , 0   , 32,
19915        0xfc003fff, 0xa000083b, 0                      , 0,
19916        CP1_                },        /* POOL32Fxf_0~*(8) */
19917     { pool                , CVT_W_fmt           , 2   , 32,
19918        0xfc003fff, 0xa000093b, 0                      , 0,
19919        CP1_                },        /* CVT.W.fmt */
19920     { pool                , SQRT_fmt            , 2   , 32,
19921        0xfc003fff, 0xa0000a3b, 0                      , 0,
19922        CP1_                },        /* SQRT.fmt */
19923     { pool                , FLOOR_W_fmt         , 2   , 32,
19924        0xfc003fff, 0xa0000b3b, 0                      , 0,
19925        CP1_                },        /* FLOOR.W.fmt */
19926     { reserved_block      , 0                   , 0   , 32,
19927        0xfc003fff, 0xa0000c3b, 0                      , 0,
19928        CP1_                },        /* POOL32Fxf_0~*(12) */
19929     { reserved_block      , 0                   , 0   , 32,
19930        0xfc003fff, 0xa0000d3b, 0                      , 0,
19931        CP1_                },        /* POOL32Fxf_0~*(13) */
19932     { reserved_block      , 0                   , 0   , 32,
19933        0xfc003fff, 0xa0000e3b, 0                      , 0,
19934        CP1_                },        /* POOL32Fxf_0~*(14) */
19935     { reserved_block      , 0                   , 0   , 32,
19936        0xfc003fff, 0xa0000f3b, 0                      , 0,
19937        CP1_                },        /* POOL32Fxf_0~*(15) */
19938     { instruction         , 0                   , 0   , 32,
19939        0xfc003fff, 0xa000103b, &NMD::CFC1             , 0,
19940        CP1_                },        /* CFC1 */
19941     { reserved_block      , 0                   , 0   , 32,
19942        0xfc003fff, 0xa000113b, 0                      , 0,
19943        CP1_                },        /* POOL32Fxf_0~*(17) */
19944     { pool                , RECIP_fmt           , 2   , 32,
19945        0xfc003fff, 0xa000123b, 0                      , 0,
19946        CP1_                },        /* RECIP.fmt */
19947     { pool                , CEIL_L_fmt          , 2   , 32,
19948        0xfc003fff, 0xa000133b, 0                      , 0,
19949        CP1_                },        /* CEIL.L.fmt */
19950     { reserved_block      , 0                   , 0   , 32,
19951        0xfc003fff, 0xa000143b, 0                      , 0,
19952        CP1_                },        /* POOL32Fxf_0~*(20) */
19953     { reserved_block      , 0                   , 0   , 32,
19954        0xfc003fff, 0xa000153b, 0                      , 0,
19955        CP1_                },        /* POOL32Fxf_0~*(21) */
19956     { reserved_block      , 0                   , 0   , 32,
19957        0xfc003fff, 0xa000163b, 0                      , 0,
19958        CP1_                },        /* POOL32Fxf_0~*(22) */
19959     { reserved_block      , 0                   , 0   , 32,
19960        0xfc003fff, 0xa000173b, 0                      , 0,
19961        CP1_                },        /* POOL32Fxf_0~*(23) */
19962     { instruction         , 0                   , 0   , 32,
19963        0xfc003fff, 0xa000183b, &NMD::CTC1             , 0,
19964        CP1_                },        /* CTC1 */
19965     { reserved_block      , 0                   , 0   , 32,
19966        0xfc003fff, 0xa000193b, 0                      , 0,
19967        CP1_                },        /* POOL32Fxf_0~*(25) */
19968     { reserved_block      , 0                   , 0   , 32,
19969        0xfc003fff, 0xa0001a3b, 0                      , 0,
19970        CP1_                },        /* POOL32Fxf_0~*(26) */
19971     { pool                , CEIL_W_fmt          , 2   , 32,
19972        0xfc003fff, 0xa0001b3b, 0                      , 0,
19973        CP1_                },        /* CEIL.W.fmt */
19974     { reserved_block      , 0                   , 0   , 32,
19975        0xfc003fff, 0xa0001c3b, 0                      , 0,
19976        CP1_                },        /* POOL32Fxf_0~*(28) */
19977     { reserved_block      , 0                   , 0   , 32,
19978        0xfc003fff, 0xa0001d3b, 0                      , 0,
19979        CP1_                },        /* POOL32Fxf_0~*(29) */
19980     { reserved_block      , 0                   , 0   , 32,
19981        0xfc003fff, 0xa0001e3b, 0                      , 0,
19982        CP1_                },        /* POOL32Fxf_0~*(30) */
19983     { reserved_block      , 0                   , 0   , 32,
19984        0xfc003fff, 0xa0001f3b, 0                      , 0,
19985        CP1_                },        /* POOL32Fxf_0~*(31) */
19986     { instruction         , 0                   , 0   , 32,
19987        0xfc003fff, 0xa000203b, &NMD::MFC1             , 0,
19988        CP1_                },        /* MFC1 */
19989     { instruction         , 0                   , 0   , 32,
19990        0xfc003fff, 0xa000213b, &NMD::CVT_S_PL         , 0,
19991        CP1_                },        /* CVT.S.PL */
19992     { reserved_block      , 0                   , 0   , 32,
19993        0xfc003fff, 0xa000223b, 0                      , 0,
19994        CP1_                },        /* POOL32Fxf_0~*(34) */
19995     { pool                , TRUNC_L_fmt         , 2   , 32,
19996        0xfc003fff, 0xa000233b, 0                      , 0,
19997        CP1_                },        /* TRUNC.L.fmt */
19998     { instruction         , 0                   , 0   , 32,
19999        0xfc003fff, 0xa000243b, &NMD::DMFC1            , 0,
20000        CP1_ | MIPS64_      },        /* DMFC1 */
20001     { reserved_block      , 0                   , 0   , 32,
20002        0xfc003fff, 0xa000253b, 0                      , 0,
20003        CP1_                },        /* POOL32Fxf_0~*(37) */
20004     { reserved_block      , 0                   , 0   , 32,
20005        0xfc003fff, 0xa000263b, 0                      , 0,
20006        CP1_                },        /* POOL32Fxf_0~*(38) */
20007     { reserved_block      , 0                   , 0   , 32,
20008        0xfc003fff, 0xa000273b, 0                      , 0,
20009        CP1_                },        /* POOL32Fxf_0~*(39) */
20010     { instruction         , 0                   , 0   , 32,
20011        0xfc003fff, 0xa000283b, &NMD::MTC1             , 0,
20012        CP1_                },        /* MTC1 */
20013     { instruction         , 0                   , 0   , 32,
20014        0xfc003fff, 0xa000293b, &NMD::CVT_S_PU         , 0,
20015        CP1_                },        /* CVT.S.PU */
20016     { reserved_block      , 0                   , 0   , 32,
20017        0xfc003fff, 0xa0002a3b, 0                      , 0,
20018        CP1_                },        /* POOL32Fxf_0~*(42) */
20019     { pool                , TRUNC_W_fmt         , 2   , 32,
20020        0xfc003fff, 0xa0002b3b, 0                      , 0,
20021        CP1_                },        /* TRUNC.W.fmt */
20022     { instruction         , 0                   , 0   , 32,
20023        0xfc003fff, 0xa0002c3b, &NMD::DMTC1            , 0,
20024        CP1_ | MIPS64_      },        /* DMTC1 */
20025     { reserved_block      , 0                   , 0   , 32,
20026        0xfc003fff, 0xa0002d3b, 0                      , 0,
20027        CP1_                },        /* POOL32Fxf_0~*(45) */
20028     { reserved_block      , 0                   , 0   , 32,
20029        0xfc003fff, 0xa0002e3b, 0                      , 0,
20030        CP1_                },        /* POOL32Fxf_0~*(46) */
20031     { reserved_block      , 0                   , 0   , 32,
20032        0xfc003fff, 0xa0002f3b, 0                      , 0,
20033        CP1_                },        /* POOL32Fxf_0~*(47) */
20034     { instruction         , 0                   , 0   , 32,
20035        0xfc003fff, 0xa000303b, &NMD::MFHC1            , 0,
20036        CP1_                },        /* MFHC1 */
20037     { reserved_block      , 0                   , 0   , 32,
20038        0xfc003fff, 0xa000313b, 0                      , 0,
20039        CP1_                },        /* POOL32Fxf_0~*(49) */
20040     { reserved_block      , 0                   , 0   , 32,
20041        0xfc003fff, 0xa000323b, 0                      , 0,
20042        CP1_                },        /* POOL32Fxf_0~*(50) */
20043     { pool                , ROUND_L_fmt         , 2   , 32,
20044        0xfc003fff, 0xa000333b, 0                      , 0,
20045        CP1_                },        /* ROUND.L.fmt */
20046     { reserved_block      , 0                   , 0   , 32,
20047        0xfc003fff, 0xa000343b, 0                      , 0,
20048        CP1_                },        /* POOL32Fxf_0~*(52) */
20049     { reserved_block      , 0                   , 0   , 32,
20050        0xfc003fff, 0xa000353b, 0                      , 0,
20051        CP1_                },        /* POOL32Fxf_0~*(53) */
20052     { reserved_block      , 0                   , 0   , 32,
20053        0xfc003fff, 0xa000363b, 0                      , 0,
20054        CP1_                },        /* POOL32Fxf_0~*(54) */
20055     { reserved_block      , 0                   , 0   , 32,
20056        0xfc003fff, 0xa000373b, 0                      , 0,
20057        CP1_                },        /* POOL32Fxf_0~*(55) */
20058     { instruction         , 0                   , 0   , 32,
20059        0xfc003fff, 0xa000383b, &NMD::MTHC1            , 0,
20060        CP1_                },        /* MTHC1 */
20061     { reserved_block      , 0                   , 0   , 32,
20062        0xfc003fff, 0xa000393b, 0                      , 0,
20063        CP1_                },        /* POOL32Fxf_0~*(57) */
20064     { reserved_block      , 0                   , 0   , 32,
20065        0xfc003fff, 0xa0003a3b, 0                      , 0,
20066        CP1_                },        /* POOL32Fxf_0~*(58) */
20067     { pool                , ROUND_W_fmt         , 2   , 32,
20068        0xfc003fff, 0xa0003b3b, 0                      , 0,
20069        CP1_                },        /* ROUND.W.fmt */
20070     { reserved_block      , 0                   , 0   , 32,
20071        0xfc003fff, 0xa0003c3b, 0                      , 0,
20072        CP1_                },        /* POOL32Fxf_0~*(60) */
20073     { reserved_block      , 0                   , 0   , 32,
20074        0xfc003fff, 0xa0003d3b, 0                      , 0,
20075        CP1_                },        /* POOL32Fxf_0~*(61) */
20076     { reserved_block      , 0                   , 0   , 32,
20077        0xfc003fff, 0xa0003e3b, 0                      , 0,
20078        CP1_                },        /* POOL32Fxf_0~*(62) */
20079     { reserved_block      , 0                   , 0   , 32,
20080        0xfc003fff, 0xa0003f3b, 0                      , 0,
20081        CP1_                },        /* POOL32Fxf_0~*(63) */
20082 };
20083
20084
20085 NMD::Pool NMD::MOV_fmt[4] = {
20086     { instruction         , 0                   , 0   , 32,
20087        0xfc007fff, 0xa000007b, &NMD::MOV_S            , 0,
20088        CP1_                },        /* MOV.S */
20089     { instruction         , 0                   , 0   , 32,
20090        0xfc007fff, 0xa000207b, &NMD::MOV_D            , 0,
20091        CP1_                },        /* MOV.D */
20092     { reserved_block      , 0                   , 0   , 32,
20093        0xfc007fff, 0xa000407b, 0                      , 0,
20094        CP1_                },        /* MOV.fmt~*(2) */
20095     { reserved_block      , 0                   , 0   , 32,
20096        0xfc007fff, 0xa000607b, 0                      , 0,
20097        CP1_                },        /* MOV.fmt~*(3) */
20098 };
20099
20100
20101 NMD::Pool NMD::ABS_fmt[4] = {
20102     { instruction         , 0                   , 0   , 32,
20103        0xfc007fff, 0xa000037b, &NMD::ABS_S            , 0,
20104        CP1_                },        /* ABS.S */
20105     { instruction         , 0                   , 0   , 32,
20106        0xfc007fff, 0xa000237b, &NMD::ABS_D            , 0,
20107        CP1_                },        /* ABS.D */
20108     { reserved_block      , 0                   , 0   , 32,
20109        0xfc007fff, 0xa000437b, 0                      , 0,
20110        CP1_                },        /* ABS.fmt~*(2) */
20111     { reserved_block      , 0                   , 0   , 32,
20112        0xfc007fff, 0xa000637b, 0                      , 0,
20113        CP1_                },        /* ABS.fmt~*(3) */
20114 };
20115
20116
20117 NMD::Pool NMD::NEG_fmt[4] = {
20118     { instruction         , 0                   , 0   , 32,
20119        0xfc007fff, 0xa0000b7b, &NMD::NEG_S            , 0,
20120        CP1_                },        /* NEG.S */
20121     { instruction         , 0                   , 0   , 32,
20122        0xfc007fff, 0xa0002b7b, &NMD::NEG_D            , 0,
20123        CP1_                },        /* NEG.D */
20124     { reserved_block      , 0                   , 0   , 32,
20125        0xfc007fff, 0xa0004b7b, 0                      , 0,
20126        CP1_                },        /* NEG.fmt~*(2) */
20127     { reserved_block      , 0                   , 0   , 32,
20128        0xfc007fff, 0xa0006b7b, 0                      , 0,
20129        CP1_                },        /* NEG.fmt~*(3) */
20130 };
20131
20132
20133 NMD::Pool NMD::CVT_D_fmt[4] = {
20134     { instruction         , 0                   , 0   , 32,
20135        0xfc007fff, 0xa000137b, &NMD::CVT_D_S          , 0,
20136        CP1_                },        /* CVT.D.S */
20137     { instruction         , 0                   , 0   , 32,
20138        0xfc007fff, 0xa000337b, &NMD::CVT_D_W          , 0,
20139        CP1_                },        /* CVT.D.W */
20140     { instruction         , 0                   , 0   , 32,
20141        0xfc007fff, 0xa000537b, &NMD::CVT_D_L          , 0,
20142        CP1_                },        /* CVT.D.L */
20143     { reserved_block      , 0                   , 0   , 32,
20144        0xfc007fff, 0xa000737b, 0                      , 0,
20145        CP1_                },        /* CVT.D.fmt~*(3) */
20146 };
20147
20148
20149 NMD::Pool NMD::CVT_S_fmt[4] = {
20150     { instruction         , 0                   , 0   , 32,
20151        0xfc007fff, 0xa0001b7b, &NMD::CVT_S_D          , 0,
20152        CP1_                },        /* CVT.S.D */
20153     { instruction         , 0                   , 0   , 32,
20154        0xfc007fff, 0xa0003b7b, &NMD::CVT_S_W          , 0,
20155        CP1_                },        /* CVT.S.W */
20156     { instruction         , 0                   , 0   , 32,
20157        0xfc007fff, 0xa0005b7b, &NMD::CVT_S_L          , 0,
20158        CP1_                },        /* CVT.S.L */
20159     { reserved_block      , 0                   , 0   , 32,
20160        0xfc007fff, 0xa0007b7b, 0                      , 0,
20161        CP1_                },        /* CVT.S.fmt~*(3) */
20162 };
20163
20164
20165 NMD::Pool NMD::POOL32Fxf_1[32] = {
20166     { pool                , MOV_fmt             , 4   , 32,
20167        0xfc001fff, 0xa000007b, 0                      , 0,
20168        CP1_                },        /* MOV.fmt */
20169     { reserved_block      , 0                   , 0   , 32,
20170        0xfc001fff, 0xa000017b, 0                      , 0,
20171        CP1_                },        /* POOL32Fxf_1~*(1) */
20172     { reserved_block      , 0                   , 0   , 32,
20173        0xfc001fff, 0xa000027b, 0                      , 0,
20174        CP1_                },        /* POOL32Fxf_1~*(2) */
20175     { pool                , ABS_fmt             , 4   , 32,
20176        0xfc001fff, 0xa000037b, 0                      , 0,
20177        CP1_                },        /* ABS.fmt */
20178     { reserved_block      , 0                   , 0   , 32,
20179        0xfc001fff, 0xa000047b, 0                      , 0,
20180        CP1_                },        /* POOL32Fxf_1~*(4) */
20181     { reserved_block      , 0                   , 0   , 32,
20182        0xfc001fff, 0xa000057b, 0                      , 0,
20183        CP1_                },        /* POOL32Fxf_1~*(5) */
20184     { reserved_block      , 0                   , 0   , 32,
20185        0xfc001fff, 0xa000067b, 0                      , 0,
20186        CP1_                },        /* POOL32Fxf_1~*(6) */
20187     { reserved_block      , 0                   , 0   , 32,
20188        0xfc001fff, 0xa000077b, 0                      , 0,
20189        CP1_                },        /* POOL32Fxf_1~*(7) */
20190     { reserved_block      , 0                   , 0   , 32,
20191        0xfc001fff, 0xa000087b, 0                      , 0,
20192        CP1_                },        /* POOL32Fxf_1~*(8) */
20193     { reserved_block      , 0                   , 0   , 32,
20194        0xfc001fff, 0xa000097b, 0                      , 0,
20195        CP1_                },        /* POOL32Fxf_1~*(9) */
20196     { reserved_block      , 0                   , 0   , 32,
20197        0xfc001fff, 0xa0000a7b, 0                      , 0,
20198        CP1_                },        /* POOL32Fxf_1~*(10) */
20199     { pool                , NEG_fmt             , 4   , 32,
20200        0xfc001fff, 0xa0000b7b, 0                      , 0,
20201        CP1_                },        /* NEG.fmt */
20202     { reserved_block      , 0                   , 0   , 32,
20203        0xfc001fff, 0xa0000c7b, 0                      , 0,
20204        CP1_                },        /* POOL32Fxf_1~*(12) */
20205     { reserved_block      , 0                   , 0   , 32,
20206        0xfc001fff, 0xa0000d7b, 0                      , 0,
20207        CP1_                },        /* POOL32Fxf_1~*(13) */
20208     { reserved_block      , 0                   , 0   , 32,
20209        0xfc001fff, 0xa0000e7b, 0                      , 0,
20210        CP1_                },        /* POOL32Fxf_1~*(14) */
20211     { reserved_block      , 0                   , 0   , 32,
20212        0xfc001fff, 0xa0000f7b, 0                      , 0,
20213        CP1_                },        /* POOL32Fxf_1~*(15) */
20214     { reserved_block      , 0                   , 0   , 32,
20215        0xfc001fff, 0xa000107b, 0                      , 0,
20216        CP1_                },        /* POOL32Fxf_1~*(16) */
20217     { reserved_block      , 0                   , 0   , 32,
20218        0xfc001fff, 0xa000117b, 0                      , 0,
20219        CP1_                },        /* POOL32Fxf_1~*(17) */
20220     { reserved_block      , 0                   , 0   , 32,
20221        0xfc001fff, 0xa000127b, 0                      , 0,
20222        CP1_                },        /* POOL32Fxf_1~*(18) */
20223     { pool                , CVT_D_fmt           , 4   , 32,
20224        0xfc001fff, 0xa000137b, 0                      , 0,
20225        CP1_                },        /* CVT.D.fmt */
20226     { reserved_block      , 0                   , 0   , 32,
20227        0xfc001fff, 0xa000147b, 0                      , 0,
20228        CP1_                },        /* POOL32Fxf_1~*(20) */
20229     { reserved_block      , 0                   , 0   , 32,
20230        0xfc001fff, 0xa000157b, 0                      , 0,
20231        CP1_                },        /* POOL32Fxf_1~*(21) */
20232     { reserved_block      , 0                   , 0   , 32,
20233        0xfc001fff, 0xa000167b, 0                      , 0,
20234        CP1_                },        /* POOL32Fxf_1~*(22) */
20235     { reserved_block      , 0                   , 0   , 32,
20236        0xfc001fff, 0xa000177b, 0                      , 0,
20237        CP1_                },        /* POOL32Fxf_1~*(23) */
20238     { reserved_block      , 0                   , 0   , 32,
20239        0xfc001fff, 0xa000187b, 0                      , 0,
20240        CP1_                },        /* POOL32Fxf_1~*(24) */
20241     { reserved_block      , 0                   , 0   , 32,
20242        0xfc001fff, 0xa000197b, 0                      , 0,
20243        CP1_                },        /* POOL32Fxf_1~*(25) */
20244     { reserved_block      , 0                   , 0   , 32,
20245        0xfc001fff, 0xa0001a7b, 0                      , 0,
20246        CP1_                },        /* POOL32Fxf_1~*(26) */
20247     { pool                , CVT_S_fmt           , 4   , 32,
20248        0xfc001fff, 0xa0001b7b, 0                      , 0,
20249        CP1_                },        /* CVT.S.fmt */
20250     { reserved_block      , 0                   , 0   , 32,
20251        0xfc001fff, 0xa0001c7b, 0                      , 0,
20252        CP1_                },        /* POOL32Fxf_1~*(28) */
20253     { reserved_block      , 0                   , 0   , 32,
20254        0xfc001fff, 0xa0001d7b, 0                      , 0,
20255        CP1_                },        /* POOL32Fxf_1~*(29) */
20256     { reserved_block      , 0                   , 0   , 32,
20257        0xfc001fff, 0xa0001e7b, 0                      , 0,
20258        CP1_                },        /* POOL32Fxf_1~*(30) */
20259     { reserved_block      , 0                   , 0   , 32,
20260        0xfc001fff, 0xa0001f7b, 0                      , 0,
20261        CP1_                },        /* POOL32Fxf_1~*(31) */
20262 };
20263
20264
20265 NMD::Pool NMD::POOL32Fxf[4] = {
20266     { pool                , POOL32Fxf_0         , 64  , 32,
20267        0xfc0000ff, 0xa000003b, 0                      , 0,
20268        CP1_                },        /* POOL32Fxf_0 */
20269     { pool                , POOL32Fxf_1         , 32  , 32,
20270        0xfc0000ff, 0xa000007b, 0                      , 0,
20271        CP1_                },        /* POOL32Fxf_1 */
20272     { reserved_block      , 0                   , 0   , 32,
20273        0xfc0000ff, 0xa00000bb, 0                      , 0,
20274        CP1_                },        /* POOL32Fxf~*(2) */
20275     { reserved_block      , 0                   , 0   , 32,
20276        0xfc0000ff, 0xa00000fb, 0                      , 0,
20277        CP1_                },        /* POOL32Fxf~*(3) */
20278 };
20279
20280
20281 NMD::Pool NMD::POOL32F_3[8] = {
20282     { pool                , MIN_fmt             , 2   , 32,
20283        0xfc00003f, 0xa0000003, 0                      , 0,
20284        CP1_                },        /* MIN.fmt */
20285     { pool                , MAX_fmt             , 2   , 32,
20286        0xfc00003f, 0xa000000b, 0                      , 0,
20287        CP1_                },        /* MAX.fmt */
20288     { reserved_block      , 0                   , 0   , 32,
20289        0xfc00003f, 0xa0000013, 0                      , 0,
20290        CP1_                },        /* POOL32F_3~*(2) */
20291     { reserved_block      , 0                   , 0   , 32,
20292        0xfc00003f, 0xa000001b, 0                      , 0,
20293        CP1_                },        /* POOL32F_3~*(3) */
20294     { pool                , MINA_fmt            , 2   , 32,
20295        0xfc00003f, 0xa0000023, 0                      , 0,
20296        CP1_                },        /* MINA.fmt */
20297     { pool                , MAXA_fmt            , 2   , 32,
20298        0xfc00003f, 0xa000002b, 0                      , 0,
20299        CP1_                },        /* MAXA.fmt */
20300     { reserved_block      , 0                   , 0   , 32,
20301        0xfc00003f, 0xa0000033, 0                      , 0,
20302        CP1_                },        /* POOL32F_3~*(6) */
20303     { pool                , POOL32Fxf           , 4   , 32,
20304        0xfc00003f, 0xa000003b, 0                      , 0,
20305        CP1_                },        /* POOL32Fxf */
20306 };
20307
20308
20309 NMD::Pool NMD::CMP_condn_S[32] = {
20310     { instruction         , 0                   , 0   , 32,
20311        0xfc0007ff, 0xa0000005, &NMD::CMP_AF_S         , 0,
20312        CP1_                },        /* CMP.AF.S */
20313     { instruction         , 0                   , 0   , 32,
20314        0xfc0007ff, 0xa0000045, &NMD::CMP_UN_S         , 0,
20315        CP1_                },        /* CMP.UN.S */
20316     { instruction         , 0                   , 0   , 32,
20317        0xfc0007ff, 0xa0000085, &NMD::CMP_EQ_S         , 0,
20318        CP1_                },        /* CMP.EQ.S */
20319     { instruction         , 0                   , 0   , 32,
20320        0xfc0007ff, 0xa00000c5, &NMD::CMP_UEQ_S        , 0,
20321        CP1_                },        /* CMP.UEQ.S */
20322     { instruction         , 0                   , 0   , 32,
20323        0xfc0007ff, 0xa0000105, &NMD::CMP_LT_S         , 0,
20324        CP1_                },        /* CMP.LT.S */
20325     { instruction         , 0                   , 0   , 32,
20326        0xfc0007ff, 0xa0000145, &NMD::CMP_ULT_S        , 0,
20327        CP1_                },        /* CMP.ULT.S */
20328     { instruction         , 0                   , 0   , 32,
20329        0xfc0007ff, 0xa0000185, &NMD::CMP_LE_S         , 0,
20330        CP1_                },        /* CMP.LE.S */
20331     { instruction         , 0                   , 0   , 32,
20332        0xfc0007ff, 0xa00001c5, &NMD::CMP_ULE_S        , 0,
20333        CP1_                },        /* CMP.ULE.S */
20334     { instruction         , 0                   , 0   , 32,
20335        0xfc0007ff, 0xa0000205, &NMD::CMP_SAF_S        , 0,
20336        CP1_                },        /* CMP.SAF.S */
20337     { instruction         , 0                   , 0   , 32,
20338        0xfc0007ff, 0xa0000245, &NMD::CMP_SUN_S        , 0,
20339        CP1_                },        /* CMP.SUN.S */
20340     { instruction         , 0                   , 0   , 32,
20341        0xfc0007ff, 0xa0000285, &NMD::CMP_SEQ_S        , 0,
20342        CP1_                },        /* CMP.SEQ.S */
20343     { instruction         , 0                   , 0   , 32,
20344        0xfc0007ff, 0xa00002c5, &NMD::CMP_SUEQ_S       , 0,
20345        CP1_                },        /* CMP.SUEQ.S */
20346     { instruction         , 0                   , 0   , 32,
20347        0xfc0007ff, 0xa0000305, &NMD::CMP_SLT_S        , 0,
20348        CP1_                },        /* CMP.SLT.S */
20349     { instruction         , 0                   , 0   , 32,
20350        0xfc0007ff, 0xa0000345, &NMD::CMP_SULT_S       , 0,
20351        CP1_                },        /* CMP.SULT.S */
20352     { instruction         , 0                   , 0   , 32,
20353        0xfc0007ff, 0xa0000385, &NMD::CMP_SLE_S        , 0,
20354        CP1_                },        /* CMP.SLE.S */
20355     { instruction         , 0                   , 0   , 32,
20356        0xfc0007ff, 0xa00003c5, &NMD::CMP_SULE_S       , 0,
20357        CP1_                },        /* CMP.SULE.S */
20358     { reserved_block      , 0                   , 0   , 32,
20359        0xfc0007ff, 0xa0000405, 0                      , 0,
20360        CP1_                },        /* CMP.condn.S~*(16) */
20361     { instruction         , 0                   , 0   , 32,
20362        0xfc0007ff, 0xa0000445, &NMD::CMP_OR_S         , 0,
20363        CP1_                },        /* CMP.OR.S */
20364     { instruction         , 0                   , 0   , 32,
20365        0xfc0007ff, 0xa0000485, &NMD::CMP_UNE_S        , 0,
20366        CP1_                },        /* CMP.UNE.S */
20367     { instruction         , 0                   , 0   , 32,
20368        0xfc0007ff, 0xa00004c5, &NMD::CMP_NE_S         , 0,
20369        CP1_                },        /* CMP.NE.S */
20370     { reserved_block      , 0                   , 0   , 32,
20371        0xfc0007ff, 0xa0000505, 0                      , 0,
20372        CP1_                },        /* CMP.condn.S~*(20) */
20373     { reserved_block      , 0                   , 0   , 32,
20374        0xfc0007ff, 0xa0000545, 0                      , 0,
20375        CP1_                },        /* CMP.condn.S~*(21) */
20376     { reserved_block      , 0                   , 0   , 32,
20377        0xfc0007ff, 0xa0000585, 0                      , 0,
20378        CP1_                },        /* CMP.condn.S~*(22) */
20379     { reserved_block      , 0                   , 0   , 32,
20380        0xfc0007ff, 0xa00005c5, 0                      , 0,
20381        CP1_                },        /* CMP.condn.S~*(23) */
20382     { reserved_block      , 0                   , 0   , 32,
20383        0xfc0007ff, 0xa0000605, 0                      , 0,
20384        CP1_                },        /* CMP.condn.S~*(24) */
20385     { instruction         , 0                   , 0   , 32,
20386        0xfc0007ff, 0xa0000645, &NMD::CMP_SOR_S        , 0,
20387        CP1_                },        /* CMP.SOR.S */
20388     { instruction         , 0                   , 0   , 32,
20389        0xfc0007ff, 0xa0000685, &NMD::CMP_SUNE_S       , 0,
20390        CP1_                },        /* CMP.SUNE.S */
20391     { instruction         , 0                   , 0   , 32,
20392        0xfc0007ff, 0xa00006c5, &NMD::CMP_SNE_S        , 0,
20393        CP1_                },        /* CMP.SNE.S */
20394     { reserved_block      , 0                   , 0   , 32,
20395        0xfc0007ff, 0xa0000705, 0                      , 0,
20396        CP1_                },        /* CMP.condn.S~*(28) */
20397     { reserved_block      , 0                   , 0   , 32,
20398        0xfc0007ff, 0xa0000745, 0                      , 0,
20399        CP1_                },        /* CMP.condn.S~*(29) */
20400     { reserved_block      , 0                   , 0   , 32,
20401        0xfc0007ff, 0xa0000785, 0                      , 0,
20402        CP1_                },        /* CMP.condn.S~*(30) */
20403     { reserved_block      , 0                   , 0   , 32,
20404        0xfc0007ff, 0xa00007c5, 0                      , 0,
20405        CP1_                },        /* CMP.condn.S~*(31) */
20406 };
20407
20408
20409 NMD::Pool NMD::CMP_condn_D[32] = {
20410     { instruction         , 0                   , 0   , 32,
20411        0xfc0007ff, 0xa0000015, &NMD::CMP_AF_D         , 0,
20412        CP1_                },        /* CMP.AF.D */
20413     { instruction         , 0                   , 0   , 32,
20414        0xfc0007ff, 0xa0000055, &NMD::CMP_UN_D         , 0,
20415        CP1_                },        /* CMP.UN.D */
20416     { instruction         , 0                   , 0   , 32,
20417        0xfc0007ff, 0xa0000095, &NMD::CMP_EQ_D         , 0,
20418        CP1_                },        /* CMP.EQ.D */
20419     { instruction         , 0                   , 0   , 32,
20420        0xfc0007ff, 0xa00000d5, &NMD::CMP_UEQ_D        , 0,
20421        CP1_                },        /* CMP.UEQ.D */
20422     { instruction         , 0                   , 0   , 32,
20423        0xfc0007ff, 0xa0000115, &NMD::CMP_LT_D         , 0,
20424        CP1_                },        /* CMP.LT.D */
20425     { instruction         , 0                   , 0   , 32,
20426        0xfc0007ff, 0xa0000155, &NMD::CMP_ULT_D        , 0,
20427        CP1_                },        /* CMP.ULT.D */
20428     { instruction         , 0                   , 0   , 32,
20429        0xfc0007ff, 0xa0000195, &NMD::CMP_LE_D         , 0,
20430        CP1_                },        /* CMP.LE.D */
20431     { instruction         , 0                   , 0   , 32,
20432        0xfc0007ff, 0xa00001d5, &NMD::CMP_ULE_D        , 0,
20433        CP1_                },        /* CMP.ULE.D */
20434     { instruction         , 0                   , 0   , 32,
20435        0xfc0007ff, 0xa0000215, &NMD::CMP_SAF_D        , 0,
20436        CP1_                },        /* CMP.SAF.D */
20437     { instruction         , 0                   , 0   , 32,
20438        0xfc0007ff, 0xa0000255, &NMD::CMP_SUN_D        , 0,
20439        CP1_                },        /* CMP.SUN.D */
20440     { instruction         , 0                   , 0   , 32,
20441        0xfc0007ff, 0xa0000295, &NMD::CMP_SEQ_D        , 0,
20442        CP1_                },        /* CMP.SEQ.D */
20443     { instruction         , 0                   , 0   , 32,
20444        0xfc0007ff, 0xa00002d5, &NMD::CMP_SUEQ_D       , 0,
20445        CP1_                },        /* CMP.SUEQ.D */
20446     { instruction         , 0                   , 0   , 32,
20447        0xfc0007ff, 0xa0000315, &NMD::CMP_SLT_D        , 0,
20448        CP1_                },        /* CMP.SLT.D */
20449     { instruction         , 0                   , 0   , 32,
20450        0xfc0007ff, 0xa0000355, &NMD::CMP_SULT_D       , 0,
20451        CP1_                },        /* CMP.SULT.D */
20452     { instruction         , 0                   , 0   , 32,
20453        0xfc0007ff, 0xa0000395, &NMD::CMP_SLE_D        , 0,
20454        CP1_                },        /* CMP.SLE.D */
20455     { instruction         , 0                   , 0   , 32,
20456        0xfc0007ff, 0xa00003d5, &NMD::CMP_SULE_D       , 0,
20457        CP1_                },        /* CMP.SULE.D */
20458     { reserved_block      , 0                   , 0   , 32,
20459        0xfc0007ff, 0xa0000415, 0                      , 0,
20460        CP1_                },        /* CMP.condn.D~*(16) */
20461     { instruction         , 0                   , 0   , 32,
20462        0xfc0007ff, 0xa0000455, &NMD::CMP_OR_D         , 0,
20463        CP1_                },        /* CMP.OR.D */
20464     { instruction         , 0                   , 0   , 32,
20465        0xfc0007ff, 0xa0000495, &NMD::CMP_UNE_D        , 0,
20466        CP1_                },        /* CMP.UNE.D */
20467     { instruction         , 0                   , 0   , 32,
20468        0xfc0007ff, 0xa00004d5, &NMD::CMP_NE_D         , 0,
20469        CP1_                },        /* CMP.NE.D */
20470     { reserved_block      , 0                   , 0   , 32,
20471        0xfc0007ff, 0xa0000515, 0                      , 0,
20472        CP1_                },        /* CMP.condn.D~*(20) */
20473     { reserved_block      , 0                   , 0   , 32,
20474        0xfc0007ff, 0xa0000555, 0                      , 0,
20475        CP1_                },        /* CMP.condn.D~*(21) */
20476     { reserved_block      , 0                   , 0   , 32,
20477        0xfc0007ff, 0xa0000595, 0                      , 0,
20478        CP1_                },        /* CMP.condn.D~*(22) */
20479     { reserved_block      , 0                   , 0   , 32,
20480        0xfc0007ff, 0xa00005d5, 0                      , 0,
20481        CP1_                },        /* CMP.condn.D~*(23) */
20482     { reserved_block      , 0                   , 0   , 32,
20483        0xfc0007ff, 0xa0000615, 0                      , 0,
20484        CP1_                },        /* CMP.condn.D~*(24) */
20485     { instruction         , 0                   , 0   , 32,
20486        0xfc0007ff, 0xa0000655, &NMD::CMP_SOR_D        , 0,
20487        CP1_                },        /* CMP.SOR.D */
20488     { instruction         , 0                   , 0   , 32,
20489        0xfc0007ff, 0xa0000695, &NMD::CMP_SUNE_D       , 0,
20490        CP1_                },        /* CMP.SUNE.D */
20491     { instruction         , 0                   , 0   , 32,
20492        0xfc0007ff, 0xa00006d5, &NMD::CMP_SNE_D        , 0,
20493        CP1_                },        /* CMP.SNE.D */
20494     { reserved_block      , 0                   , 0   , 32,
20495        0xfc0007ff, 0xa0000715, 0                      , 0,
20496        CP1_                },        /* CMP.condn.D~*(28) */
20497     { reserved_block      , 0                   , 0   , 32,
20498        0xfc0007ff, 0xa0000755, 0                      , 0,
20499        CP1_                },        /* CMP.condn.D~*(29) */
20500     { reserved_block      , 0                   , 0   , 32,
20501        0xfc0007ff, 0xa0000795, 0                      , 0,
20502        CP1_                },        /* CMP.condn.D~*(30) */
20503     { reserved_block      , 0                   , 0   , 32,
20504        0xfc0007ff, 0xa00007d5, 0                      , 0,
20505        CP1_                },        /* CMP.condn.D~*(31) */
20506 };
20507
20508
20509 NMD::Pool NMD::POOL32F_5[8] = {
20510     { pool                , CMP_condn_S         , 32  , 32,
20511        0xfc00003f, 0xa0000005, 0                      , 0,
20512        CP1_                },        /* CMP.condn.S */
20513     { reserved_block      , 0                   , 0   , 32,
20514        0xfc00003f, 0xa000000d, 0                      , 0,
20515        CP1_                },        /* POOL32F_5~*(1) */
20516     { pool                , CMP_condn_D         , 32  , 32,
20517        0xfc00003f, 0xa0000015, 0                      , 0,
20518        CP1_                },        /* CMP.condn.D */
20519     { reserved_block      , 0                   , 0   , 32,
20520        0xfc00003f, 0xa000001d, 0                      , 0,
20521        CP1_                },        /* POOL32F_5~*(3) */
20522     { reserved_block      , 0                   , 0   , 32,
20523        0xfc00003f, 0xa0000025, 0                      , 0,
20524        CP1_                },        /* POOL32F_5~*(4) */
20525     { reserved_block      , 0                   , 0   , 32,
20526        0xfc00003f, 0xa000002d, 0                      , 0,
20527        CP1_                },        /* POOL32F_5~*(5) */
20528     { reserved_block      , 0                   , 0   , 32,
20529        0xfc00003f, 0xa0000035, 0                      , 0,
20530        CP1_                },        /* POOL32F_5~*(6) */
20531     { reserved_block      , 0                   , 0   , 32,
20532        0xfc00003f, 0xa000003d, 0                      , 0,
20533        CP1_                },        /* POOL32F_5~*(7) */
20534 };
20535
20536
20537 NMD::Pool NMD::POOL32F[8] = {
20538     { pool                , POOL32F_0           , 64  , 32,
20539        0xfc000007, 0xa0000000, 0                      , 0,
20540        CP1_                },        /* POOL32F_0 */
20541     { reserved_block      , 0                   , 0   , 32,
20542        0xfc000007, 0xa0000001, 0                      , 0,
20543        CP1_                },        /* POOL32F~*(1) */
20544     { reserved_block      , 0                   , 0   , 32,
20545        0xfc000007, 0xa0000002, 0                      , 0,
20546        CP1_                },        /* POOL32F~*(2) */
20547     { pool                , POOL32F_3           , 8   , 32,
20548        0xfc000007, 0xa0000003, 0                      , 0,
20549        CP1_                },        /* POOL32F_3 */
20550     { reserved_block      , 0                   , 0   , 32,
20551        0xfc000007, 0xa0000004, 0                      , 0,
20552        CP1_                },        /* POOL32F~*(4) */
20553     { pool                , POOL32F_5           , 8   , 32,
20554        0xfc000007, 0xa0000005, 0                      , 0,
20555        CP1_                },        /* POOL32F_5 */
20556     { reserved_block      , 0                   , 0   , 32,
20557        0xfc000007, 0xa0000006, 0                      , 0,
20558        CP1_                },        /* POOL32F~*(6) */
20559     { reserved_block      , 0                   , 0   , 32,
20560        0xfc000007, 0xa0000007, 0                      , 0,
20561        CP1_                },        /* POOL32F~*(7) */
20562 };
20563
20564
20565 NMD::Pool NMD::POOL32S_0[64] = {
20566     { reserved_block      , 0                   , 0   , 32,
20567        0xfc0001ff, 0xc0000000, 0                      , 0,
20568        0x0                 },        /* POOL32S_0~*(0) */
20569     { instruction         , 0                   , 0   , 32,
20570        0xfc0001ff, 0xc0000008, &NMD::DLSA             , 0,
20571        MIPS64_             },        /* DLSA */
20572     { instruction         , 0                   , 0   , 32,
20573        0xfc0001ff, 0xc0000010, &NMD::DSLLV            , 0,
20574        MIPS64_             },        /* DSLLV */
20575     { instruction         , 0                   , 0   , 32,
20576        0xfc0001ff, 0xc0000018, &NMD::DMUL             , 0,
20577        MIPS64_             },        /* DMUL */
20578     { reserved_block      , 0                   , 0   , 32,
20579        0xfc0001ff, 0xc0000020, 0                      , 0,
20580        0x0                 },        /* POOL32S_0~*(4) */
20581     { reserved_block      , 0                   , 0   , 32,
20582        0xfc0001ff, 0xc0000028, 0                      , 0,
20583        0x0                 },        /* POOL32S_0~*(5) */
20584     { reserved_block      , 0                   , 0   , 32,
20585        0xfc0001ff, 0xc0000030, 0                      , 0,
20586        0x0                 },        /* POOL32S_0~*(6) */
20587     { reserved_block      , 0                   , 0   , 32,
20588        0xfc0001ff, 0xc0000038, 0                      , 0,
20589        0x0                 },        /* POOL32S_0~*(7) */
20590     { reserved_block      , 0                   , 0   , 32,
20591        0xfc0001ff, 0xc0000040, 0                      , 0,
20592        0x0                 },        /* POOL32S_0~*(8) */
20593     { reserved_block      , 0                   , 0   , 32,
20594        0xfc0001ff, 0xc0000048, 0                      , 0,
20595        0x0                 },        /* POOL32S_0~*(9) */
20596     { instruction         , 0                   , 0   , 32,
20597        0xfc0001ff, 0xc0000050, &NMD::DSRLV            , 0,
20598        MIPS64_             },        /* DSRLV */
20599     { instruction         , 0                   , 0   , 32,
20600        0xfc0001ff, 0xc0000058, &NMD::DMUH             , 0,
20601        MIPS64_             },        /* DMUH */
20602     { reserved_block      , 0                   , 0   , 32,
20603        0xfc0001ff, 0xc0000060, 0                      , 0,
20604        0x0                 },        /* POOL32S_0~*(12) */
20605     { reserved_block      , 0                   , 0   , 32,
20606        0xfc0001ff, 0xc0000068, 0                      , 0,
20607        0x0                 },        /* POOL32S_0~*(13) */
20608     { reserved_block      , 0                   , 0   , 32,
20609        0xfc0001ff, 0xc0000070, 0                      , 0,
20610        0x0                 },        /* POOL32S_0~*(14) */
20611     { reserved_block      , 0                   , 0   , 32,
20612        0xfc0001ff, 0xc0000078, 0                      , 0,
20613        0x0                 },        /* POOL32S_0~*(15) */
20614     { reserved_block      , 0                   , 0   , 32,
20615        0xfc0001ff, 0xc0000080, 0                      , 0,
20616        0x0                 },        /* POOL32S_0~*(16) */
20617     { reserved_block      , 0                   , 0   , 32,
20618        0xfc0001ff, 0xc0000088, 0                      , 0,
20619        0x0                 },        /* POOL32S_0~*(17) */
20620     { instruction         , 0                   , 0   , 32,
20621        0xfc0001ff, 0xc0000090, &NMD::DSRAV            , 0,
20622        MIPS64_             },        /* DSRAV */
20623     { instruction         , 0                   , 0   , 32,
20624        0xfc0001ff, 0xc0000098, &NMD::DMULU            , 0,
20625        MIPS64_             },        /* DMULU */
20626     { reserved_block      , 0                   , 0   , 32,
20627        0xfc0001ff, 0xc00000a0, 0                      , 0,
20628        0x0                 },        /* POOL32S_0~*(20) */
20629     { reserved_block      , 0                   , 0   , 32,
20630        0xfc0001ff, 0xc00000a8, 0                      , 0,
20631        0x0                 },        /* POOL32S_0~*(21) */
20632     { reserved_block      , 0                   , 0   , 32,
20633        0xfc0001ff, 0xc00000b0, 0                      , 0,
20634        0x0                 },        /* POOL32S_0~*(22) */
20635     { reserved_block      , 0                   , 0   , 32,
20636        0xfc0001ff, 0xc00000b8, 0                      , 0,
20637        0x0                 },        /* POOL32S_0~*(23) */
20638     { reserved_block      , 0                   , 0   , 32,
20639        0xfc0001ff, 0xc00000c0, 0                      , 0,
20640        0x0                 },        /* POOL32S_0~*(24) */
20641     { reserved_block      , 0                   , 0   , 32,
20642        0xfc0001ff, 0xc00000c8, 0                      , 0,
20643        0x0                 },        /* POOL32S_0~*(25) */
20644     { instruction         , 0                   , 0   , 32,
20645        0xfc0001ff, 0xc00000d0, &NMD::DROTRV           , 0,
20646        MIPS64_             },        /* DROTRV */
20647     { instruction         , 0                   , 0   , 32,
20648        0xfc0001ff, 0xc00000d8, &NMD::DMUHU            , 0,
20649        MIPS64_             },        /* DMUHU */
20650     { reserved_block      , 0                   , 0   , 32,
20651        0xfc0001ff, 0xc00000e0, 0                      , 0,
20652        0x0                 },        /* POOL32S_0~*(28) */
20653     { reserved_block      , 0                   , 0   , 32,
20654        0xfc0001ff, 0xc00000e8, 0                      , 0,
20655        0x0                 },        /* POOL32S_0~*(29) */
20656     { reserved_block      , 0                   , 0   , 32,
20657        0xfc0001ff, 0xc00000f0, 0                      , 0,
20658        0x0                 },        /* POOL32S_0~*(30) */
20659     { reserved_block      , 0                   , 0   , 32,
20660        0xfc0001ff, 0xc00000f8, 0                      , 0,
20661        0x0                 },        /* POOL32S_0~*(31) */
20662     { reserved_block      , 0                   , 0   , 32,
20663        0xfc0001ff, 0xc0000100, 0                      , 0,
20664        0x0                 },        /* POOL32S_0~*(32) */
20665     { reserved_block      , 0                   , 0   , 32,
20666        0xfc0001ff, 0xc0000108, 0                      , 0,
20667        0x0                 },        /* POOL32S_0~*(33) */
20668     { instruction         , 0                   , 0   , 32,
20669        0xfc0001ff, 0xc0000110, &NMD::DADD             , 0,
20670        MIPS64_             },        /* DADD */
20671     { instruction         , 0                   , 0   , 32,
20672        0xfc0001ff, 0xc0000118, &NMD::DDIV             , 0,
20673        MIPS64_             },        /* DDIV */
20674     { reserved_block      , 0                   , 0   , 32,
20675        0xfc0001ff, 0xc0000120, 0                      , 0,
20676        0x0                 },        /* POOL32S_0~*(36) */
20677     { reserved_block      , 0                   , 0   , 32,
20678        0xfc0001ff, 0xc0000128, 0                      , 0,
20679        0x0                 },        /* POOL32S_0~*(37) */
20680     { reserved_block      , 0                   , 0   , 32,
20681        0xfc0001ff, 0xc0000130, 0                      , 0,
20682        0x0                 },        /* POOL32S_0~*(38) */
20683     { reserved_block      , 0                   , 0   , 32,
20684        0xfc0001ff, 0xc0000138, 0                      , 0,
20685        0x0                 },        /* POOL32S_0~*(39) */
20686     { reserved_block      , 0                   , 0   , 32,
20687        0xfc0001ff, 0xc0000140, 0                      , 0,
20688        0x0                 },        /* POOL32S_0~*(40) */
20689     { reserved_block      , 0                   , 0   , 32,
20690        0xfc0001ff, 0xc0000148, 0                      , 0,
20691        0x0                 },        /* POOL32S_0~*(41) */
20692     { instruction         , 0                   , 0   , 32,
20693        0xfc0001ff, 0xc0000150, &NMD::DADDU            , 0,
20694        MIPS64_             },        /* DADDU */
20695     { instruction         , 0                   , 0   , 32,
20696        0xfc0001ff, 0xc0000158, &NMD::DMOD             , 0,
20697        MIPS64_             },        /* DMOD */
20698     { reserved_block      , 0                   , 0   , 32,
20699        0xfc0001ff, 0xc0000160, 0                      , 0,
20700        0x0                 },        /* POOL32S_0~*(44) */
20701     { reserved_block      , 0                   , 0   , 32,
20702        0xfc0001ff, 0xc0000168, 0                      , 0,
20703        0x0                 },        /* POOL32S_0~*(45) */
20704     { reserved_block      , 0                   , 0   , 32,
20705        0xfc0001ff, 0xc0000170, 0                      , 0,
20706        0x0                 },        /* POOL32S_0~*(46) */
20707     { reserved_block      , 0                   , 0   , 32,
20708        0xfc0001ff, 0xc0000178, 0                      , 0,
20709        0x0                 },        /* POOL32S_0~*(47) */
20710     { reserved_block      , 0                   , 0   , 32,
20711        0xfc0001ff, 0xc0000180, 0                      , 0,
20712        0x0                 },        /* POOL32S_0~*(48) */
20713     { reserved_block      , 0                   , 0   , 32,
20714        0xfc0001ff, 0xc0000188, 0                      , 0,
20715        0x0                 },        /* POOL32S_0~*(49) */
20716     { instruction         , 0                   , 0   , 32,
20717        0xfc0001ff, 0xc0000190, &NMD::DSUB             , 0,
20718        MIPS64_             },        /* DSUB */
20719     { instruction         , 0                   , 0   , 32,
20720        0xfc0001ff, 0xc0000198, &NMD::DDIVU            , 0,
20721        MIPS64_             },        /* DDIVU */
20722     { reserved_block      , 0                   , 0   , 32,
20723        0xfc0001ff, 0xc00001a0, 0                      , 0,
20724        0x0                 },        /* POOL32S_0~*(52) */
20725     { reserved_block      , 0                   , 0   , 32,
20726        0xfc0001ff, 0xc00001a8, 0                      , 0,
20727        0x0                 },        /* POOL32S_0~*(53) */
20728     { reserved_block      , 0                   , 0   , 32,
20729        0xfc0001ff, 0xc00001b0, 0                      , 0,
20730        0x0                 },        /* POOL32S_0~*(54) */
20731     { reserved_block      , 0                   , 0   , 32,
20732        0xfc0001ff, 0xc00001b8, 0                      , 0,
20733        0x0                 },        /* POOL32S_0~*(55) */
20734     { reserved_block      , 0                   , 0   , 32,
20735        0xfc0001ff, 0xc00001c0, 0                      , 0,
20736        0x0                 },        /* POOL32S_0~*(56) */
20737     { reserved_block      , 0                   , 0   , 32,
20738        0xfc0001ff, 0xc00001c8, 0                      , 0,
20739        0x0                 },        /* POOL32S_0~*(57) */
20740     { instruction         , 0                   , 0   , 32,
20741        0xfc0001ff, 0xc00001d0, &NMD::DSUBU            , 0,
20742        MIPS64_             },        /* DSUBU */
20743     { instruction         , 0                   , 0   , 32,
20744        0xfc0001ff, 0xc00001d8, &NMD::DMODU            , 0,
20745        MIPS64_             },        /* DMODU */
20746     { reserved_block      , 0                   , 0   , 32,
20747        0xfc0001ff, 0xc00001e0, 0                      , 0,
20748        0x0                 },        /* POOL32S_0~*(60) */
20749     { reserved_block      , 0                   , 0   , 32,
20750        0xfc0001ff, 0xc00001e8, 0                      , 0,
20751        0x0                 },        /* POOL32S_0~*(61) */
20752     { reserved_block      , 0                   , 0   , 32,
20753        0xfc0001ff, 0xc00001f0, 0                      , 0,
20754        0x0                 },        /* POOL32S_0~*(62) */
20755     { reserved_block      , 0                   , 0   , 32,
20756        0xfc0001ff, 0xc00001f8, 0                      , 0,
20757        0x0                 },        /* POOL32S_0~*(63) */
20758 };
20759
20760
20761 NMD::Pool NMD::POOL32Sxf_4[128] = {
20762     { reserved_block      , 0                   , 0   , 32,
20763        0xfc00ffff, 0xc000013c, 0                      , 0,
20764        0x0                 },        /* POOL32Sxf_4~*(0) */
20765     { reserved_block      , 0                   , 0   , 32,
20766        0xfc00ffff, 0xc000033c, 0                      , 0,
20767        0x0                 },        /* POOL32Sxf_4~*(1) */
20768     { reserved_block      , 0                   , 0   , 32,
20769        0xfc00ffff, 0xc000053c, 0                      , 0,
20770        0x0                 },        /* POOL32Sxf_4~*(2) */
20771     { reserved_block      , 0                   , 0   , 32,
20772        0xfc00ffff, 0xc000073c, 0                      , 0,
20773        0x0                 },        /* POOL32Sxf_4~*(3) */
20774     { reserved_block      , 0                   , 0   , 32,
20775        0xfc00ffff, 0xc000093c, 0                      , 0,
20776        0x0                 },        /* POOL32Sxf_4~*(4) */
20777     { reserved_block      , 0                   , 0   , 32,
20778        0xfc00ffff, 0xc0000b3c, 0                      , 0,
20779        0x0                 },        /* POOL32Sxf_4~*(5) */
20780     { reserved_block      , 0                   , 0   , 32,
20781        0xfc00ffff, 0xc0000d3c, 0                      , 0,
20782        0x0                 },        /* POOL32Sxf_4~*(6) */
20783     { reserved_block      , 0                   , 0   , 32,
20784        0xfc00ffff, 0xc0000f3c, 0                      , 0,
20785        0x0                 },        /* POOL32Sxf_4~*(7) */
20786     { reserved_block      , 0                   , 0   , 32,
20787        0xfc00ffff, 0xc000113c, 0                      , 0,
20788        0x0                 },        /* POOL32Sxf_4~*(8) */
20789     { reserved_block      , 0                   , 0   , 32,
20790        0xfc00ffff, 0xc000133c, 0                      , 0,
20791        0x0                 },        /* POOL32Sxf_4~*(9) */
20792     { reserved_block      , 0                   , 0   , 32,
20793        0xfc00ffff, 0xc000153c, 0                      , 0,
20794        0x0                 },        /* POOL32Sxf_4~*(10) */
20795     { reserved_block      , 0                   , 0   , 32,
20796        0xfc00ffff, 0xc000173c, 0                      , 0,
20797        0x0                 },        /* POOL32Sxf_4~*(11) */
20798     { reserved_block      , 0                   , 0   , 32,
20799        0xfc00ffff, 0xc000193c, 0                      , 0,
20800        0x0                 },        /* POOL32Sxf_4~*(12) */
20801     { reserved_block      , 0                   , 0   , 32,
20802        0xfc00ffff, 0xc0001b3c, 0                      , 0,
20803        0x0                 },        /* POOL32Sxf_4~*(13) */
20804     { reserved_block      , 0                   , 0   , 32,
20805        0xfc00ffff, 0xc0001d3c, 0                      , 0,
20806        0x0                 },        /* POOL32Sxf_4~*(14) */
20807     { reserved_block      , 0                   , 0   , 32,
20808        0xfc00ffff, 0xc0001f3c, 0                      , 0,
20809        0x0                 },        /* POOL32Sxf_4~*(15) */
20810     { reserved_block      , 0                   , 0   , 32,
20811        0xfc00ffff, 0xc000213c, 0                      , 0,
20812        0x0                 },        /* POOL32Sxf_4~*(16) */
20813     { reserved_block      , 0                   , 0   , 32,
20814        0xfc00ffff, 0xc000233c, 0                      , 0,
20815        0x0                 },        /* POOL32Sxf_4~*(17) */
20816     { reserved_block      , 0                   , 0   , 32,
20817        0xfc00ffff, 0xc000253c, 0                      , 0,
20818        0x0                 },        /* POOL32Sxf_4~*(18) */
20819     { reserved_block      , 0                   , 0   , 32,
20820        0xfc00ffff, 0xc000273c, 0                      , 0,
20821        0x0                 },        /* POOL32Sxf_4~*(19) */
20822     { reserved_block      , 0                   , 0   , 32,
20823        0xfc00ffff, 0xc000293c, 0                      , 0,
20824        0x0                 },        /* POOL32Sxf_4~*(20) */
20825     { reserved_block      , 0                   , 0   , 32,
20826        0xfc00ffff, 0xc0002b3c, 0                      , 0,
20827        0x0                 },        /* POOL32Sxf_4~*(21) */
20828     { reserved_block      , 0                   , 0   , 32,
20829        0xfc00ffff, 0xc0002d3c, 0                      , 0,
20830        0x0                 },        /* POOL32Sxf_4~*(22) */
20831     { reserved_block      , 0                   , 0   , 32,
20832        0xfc00ffff, 0xc0002f3c, 0                      , 0,
20833        0x0                 },        /* POOL32Sxf_4~*(23) */
20834     { reserved_block      , 0                   , 0   , 32,
20835        0xfc00ffff, 0xc000313c, 0                      , 0,
20836        0x0                 },        /* POOL32Sxf_4~*(24) */
20837     { reserved_block      , 0                   , 0   , 32,
20838        0xfc00ffff, 0xc000333c, 0                      , 0,
20839        0x0                 },        /* POOL32Sxf_4~*(25) */
20840     { reserved_block      , 0                   , 0   , 32,
20841        0xfc00ffff, 0xc000353c, 0                      , 0,
20842        0x0                 },        /* POOL32Sxf_4~*(26) */
20843     { reserved_block      , 0                   , 0   , 32,
20844        0xfc00ffff, 0xc000373c, 0                      , 0,
20845        0x0                 },        /* POOL32Sxf_4~*(27) */
20846     { reserved_block      , 0                   , 0   , 32,
20847        0xfc00ffff, 0xc000393c, 0                      , 0,
20848        0x0                 },        /* POOL32Sxf_4~*(28) */
20849     { reserved_block      , 0                   , 0   , 32,
20850        0xfc00ffff, 0xc0003b3c, 0                      , 0,
20851        0x0                 },        /* POOL32Sxf_4~*(29) */
20852     { reserved_block      , 0                   , 0   , 32,
20853        0xfc00ffff, 0xc0003d3c, 0                      , 0,
20854        0x0                 },        /* POOL32Sxf_4~*(30) */
20855     { reserved_block      , 0                   , 0   , 32,
20856        0xfc00ffff, 0xc0003f3c, 0                      , 0,
20857        0x0                 },        /* POOL32Sxf_4~*(31) */
20858     { reserved_block      , 0                   , 0   , 32,
20859        0xfc00ffff, 0xc000413c, 0                      , 0,
20860        0x0                 },        /* POOL32Sxf_4~*(32) */
20861     { reserved_block      , 0                   , 0   , 32,
20862        0xfc00ffff, 0xc000433c, 0                      , 0,
20863        0x0                 },        /* POOL32Sxf_4~*(33) */
20864     { reserved_block      , 0                   , 0   , 32,
20865        0xfc00ffff, 0xc000453c, 0                      , 0,
20866        0x0                 },        /* POOL32Sxf_4~*(34) */
20867     { reserved_block      , 0                   , 0   , 32,
20868        0xfc00ffff, 0xc000473c, 0                      , 0,
20869        0x0                 },        /* POOL32Sxf_4~*(35) */
20870     { reserved_block      , 0                   , 0   , 32,
20871        0xfc00ffff, 0xc000493c, 0                      , 0,
20872        0x0                 },        /* POOL32Sxf_4~*(36) */
20873     { instruction         , 0                   , 0   , 32,
20874        0xfc00ffff, 0xc0004b3c, &NMD::DCLO             , 0,
20875        MIPS64_             },        /* DCLO */
20876     { reserved_block      , 0                   , 0   , 32,
20877        0xfc00ffff, 0xc0004d3c, 0                      , 0,
20878        0x0                 },        /* POOL32Sxf_4~*(38) */
20879     { reserved_block      , 0                   , 0   , 32,
20880        0xfc00ffff, 0xc0004f3c, 0                      , 0,
20881        0x0                 },        /* POOL32Sxf_4~*(39) */
20882     { reserved_block      , 0                   , 0   , 32,
20883        0xfc00ffff, 0xc000513c, 0                      , 0,
20884        0x0                 },        /* POOL32Sxf_4~*(40) */
20885     { reserved_block      , 0                   , 0   , 32,
20886        0xfc00ffff, 0xc000533c, 0                      , 0,
20887        0x0                 },        /* POOL32Sxf_4~*(41) */
20888     { reserved_block      , 0                   , 0   , 32,
20889        0xfc00ffff, 0xc000553c, 0                      , 0,
20890        0x0                 },        /* POOL32Sxf_4~*(42) */
20891     { reserved_block      , 0                   , 0   , 32,
20892        0xfc00ffff, 0xc000573c, 0                      , 0,
20893        0x0                 },        /* POOL32Sxf_4~*(43) */
20894     { reserved_block      , 0                   , 0   , 32,
20895        0xfc00ffff, 0xc000593c, 0                      , 0,
20896        0x0                 },        /* POOL32Sxf_4~*(44) */
20897     { instruction         , 0                   , 0   , 32,
20898        0xfc00ffff, 0xc0005b3c, &NMD::DCLZ             , 0,
20899        MIPS64_             },        /* DCLZ */
20900     { reserved_block      , 0                   , 0   , 32,
20901        0xfc00ffff, 0xc0005d3c, 0                      , 0,
20902        0x0                 },        /* POOL32Sxf_4~*(46) */
20903     { reserved_block      , 0                   , 0   , 32,
20904        0xfc00ffff, 0xc0005f3c, 0                      , 0,
20905        0x0                 },        /* POOL32Sxf_4~*(47) */
20906     { reserved_block      , 0                   , 0   , 32,
20907        0xfc00ffff, 0xc000613c, 0                      , 0,
20908        0x0                 },        /* POOL32Sxf_4~*(48) */
20909     { reserved_block      , 0                   , 0   , 32,
20910        0xfc00ffff, 0xc000633c, 0                      , 0,
20911        0x0                 },        /* POOL32Sxf_4~*(49) */
20912     { reserved_block      , 0                   , 0   , 32,
20913        0xfc00ffff, 0xc000653c, 0                      , 0,
20914        0x0                 },        /* POOL32Sxf_4~*(50) */
20915     { reserved_block      , 0                   , 0   , 32,
20916        0xfc00ffff, 0xc000673c, 0                      , 0,
20917        0x0                 },        /* POOL32Sxf_4~*(51) */
20918     { reserved_block      , 0                   , 0   , 32,
20919        0xfc00ffff, 0xc000693c, 0                      , 0,
20920        0x0                 },        /* POOL32Sxf_4~*(52) */
20921     { reserved_block      , 0                   , 0   , 32,
20922        0xfc00ffff, 0xc0006b3c, 0                      , 0,
20923        0x0                 },        /* POOL32Sxf_4~*(53) */
20924     { reserved_block      , 0                   , 0   , 32,
20925        0xfc00ffff, 0xc0006d3c, 0                      , 0,
20926        0x0                 },        /* POOL32Sxf_4~*(54) */
20927     { reserved_block      , 0                   , 0   , 32,
20928        0xfc00ffff, 0xc0006f3c, 0                      , 0,
20929        0x0                 },        /* POOL32Sxf_4~*(55) */
20930     { reserved_block      , 0                   , 0   , 32,
20931        0xfc00ffff, 0xc000713c, 0                      , 0,
20932        0x0                 },        /* POOL32Sxf_4~*(56) */
20933     { reserved_block      , 0                   , 0   , 32,
20934        0xfc00ffff, 0xc000733c, 0                      , 0,
20935        0x0                 },        /* POOL32Sxf_4~*(57) */
20936     { reserved_block      , 0                   , 0   , 32,
20937        0xfc00ffff, 0xc000753c, 0                      , 0,
20938        0x0                 },        /* POOL32Sxf_4~*(58) */
20939     { reserved_block      , 0                   , 0   , 32,
20940        0xfc00ffff, 0xc000773c, 0                      , 0,
20941        0x0                 },        /* POOL32Sxf_4~*(59) */
20942     { reserved_block      , 0                   , 0   , 32,
20943        0xfc00ffff, 0xc000793c, 0                      , 0,
20944        0x0                 },        /* POOL32Sxf_4~*(60) */
20945     { reserved_block      , 0                   , 0   , 32,
20946        0xfc00ffff, 0xc0007b3c, 0                      , 0,
20947        0x0                 },        /* POOL32Sxf_4~*(61) */
20948     { reserved_block      , 0                   , 0   , 32,
20949        0xfc00ffff, 0xc0007d3c, 0                      , 0,
20950        0x0                 },        /* POOL32Sxf_4~*(62) */
20951     { reserved_block      , 0                   , 0   , 32,
20952        0xfc00ffff, 0xc0007f3c, 0                      , 0,
20953        0x0                 },        /* POOL32Sxf_4~*(63) */
20954     { reserved_block      , 0                   , 0   , 32,
20955        0xfc00ffff, 0xc000813c, 0                      , 0,
20956        0x0                 },        /* POOL32Sxf_4~*(64) */
20957     { reserved_block      , 0                   , 0   , 32,
20958        0xfc00ffff, 0xc000833c, 0                      , 0,
20959        0x0                 },        /* POOL32Sxf_4~*(65) */
20960     { reserved_block      , 0                   , 0   , 32,
20961        0xfc00ffff, 0xc000853c, 0                      , 0,
20962        0x0                 },        /* POOL32Sxf_4~*(66) */
20963     { reserved_block      , 0                   , 0   , 32,
20964        0xfc00ffff, 0xc000873c, 0                      , 0,
20965        0x0                 },        /* POOL32Sxf_4~*(67) */
20966     { reserved_block      , 0                   , 0   , 32,
20967        0xfc00ffff, 0xc000893c, 0                      , 0,
20968        0x0                 },        /* POOL32Sxf_4~*(68) */
20969     { reserved_block      , 0                   , 0   , 32,
20970        0xfc00ffff, 0xc0008b3c, 0                      , 0,
20971        0x0                 },        /* POOL32Sxf_4~*(69) */
20972     { reserved_block      , 0                   , 0   , 32,
20973        0xfc00ffff, 0xc0008d3c, 0                      , 0,
20974        0x0                 },        /* POOL32Sxf_4~*(70) */
20975     { reserved_block      , 0                   , 0   , 32,
20976        0xfc00ffff, 0xc0008f3c, 0                      , 0,
20977        0x0                 },        /* POOL32Sxf_4~*(71) */
20978     { reserved_block      , 0                   , 0   , 32,
20979        0xfc00ffff, 0xc000913c, 0                      , 0,
20980        0x0                 },        /* POOL32Sxf_4~*(72) */
20981     { reserved_block      , 0                   , 0   , 32,
20982        0xfc00ffff, 0xc000933c, 0                      , 0,
20983        0x0                 },        /* POOL32Sxf_4~*(73) */
20984     { reserved_block      , 0                   , 0   , 32,
20985        0xfc00ffff, 0xc000953c, 0                      , 0,
20986        0x0                 },        /* POOL32Sxf_4~*(74) */
20987     { reserved_block      , 0                   , 0   , 32,
20988        0xfc00ffff, 0xc000973c, 0                      , 0,
20989        0x0                 },        /* POOL32Sxf_4~*(75) */
20990     { reserved_block      , 0                   , 0   , 32,
20991        0xfc00ffff, 0xc000993c, 0                      , 0,
20992        0x0                 },        /* POOL32Sxf_4~*(76) */
20993     { reserved_block      , 0                   , 0   , 32,
20994        0xfc00ffff, 0xc0009b3c, 0                      , 0,
20995        0x0                 },        /* POOL32Sxf_4~*(77) */
20996     { reserved_block      , 0                   , 0   , 32,
20997        0xfc00ffff, 0xc0009d3c, 0                      , 0,
20998        0x0                 },        /* POOL32Sxf_4~*(78) */
20999     { reserved_block      , 0                   , 0   , 32,
21000        0xfc00ffff, 0xc0009f3c, 0                      , 0,
21001        0x0                 },        /* POOL32Sxf_4~*(79) */
21002     { reserved_block      , 0                   , 0   , 32,
21003        0xfc00ffff, 0xc000a13c, 0                      , 0,
21004        0x0                 },        /* POOL32Sxf_4~*(80) */
21005     { reserved_block      , 0                   , 0   , 32,
21006        0xfc00ffff, 0xc000a33c, 0                      , 0,
21007        0x0                 },        /* POOL32Sxf_4~*(81) */
21008     { reserved_block      , 0                   , 0   , 32,
21009        0xfc00ffff, 0xc000a53c, 0                      , 0,
21010        0x0                 },        /* POOL32Sxf_4~*(82) */
21011     { reserved_block      , 0                   , 0   , 32,
21012        0xfc00ffff, 0xc000a73c, 0                      , 0,
21013        0x0                 },        /* POOL32Sxf_4~*(83) */
21014     { reserved_block      , 0                   , 0   , 32,
21015        0xfc00ffff, 0xc000a93c, 0                      , 0,
21016        0x0                 },        /* POOL32Sxf_4~*(84) */
21017     { reserved_block      , 0                   , 0   , 32,
21018        0xfc00ffff, 0xc000ab3c, 0                      , 0,
21019        0x0                 },        /* POOL32Sxf_4~*(85) */
21020     { reserved_block      , 0                   , 0   , 32,
21021        0xfc00ffff, 0xc000ad3c, 0                      , 0,
21022        0x0                 },        /* POOL32Sxf_4~*(86) */
21023     { reserved_block      , 0                   , 0   , 32,
21024        0xfc00ffff, 0xc000af3c, 0                      , 0,
21025        0x0                 },        /* POOL32Sxf_4~*(87) */
21026     { reserved_block      , 0                   , 0   , 32,
21027        0xfc00ffff, 0xc000b13c, 0                      , 0,
21028        0x0                 },        /* POOL32Sxf_4~*(88) */
21029     { reserved_block      , 0                   , 0   , 32,
21030        0xfc00ffff, 0xc000b33c, 0                      , 0,
21031        0x0                 },        /* POOL32Sxf_4~*(89) */
21032     { reserved_block      , 0                   , 0   , 32,
21033        0xfc00ffff, 0xc000b53c, 0                      , 0,
21034        0x0                 },        /* POOL32Sxf_4~*(90) */
21035     { reserved_block      , 0                   , 0   , 32,
21036        0xfc00ffff, 0xc000b73c, 0                      , 0,
21037        0x0                 },        /* POOL32Sxf_4~*(91) */
21038     { reserved_block      , 0                   , 0   , 32,
21039        0xfc00ffff, 0xc000b93c, 0                      , 0,
21040        0x0                 },        /* POOL32Sxf_4~*(92) */
21041     { reserved_block      , 0                   , 0   , 32,
21042        0xfc00ffff, 0xc000bb3c, 0                      , 0,
21043        0x0                 },        /* POOL32Sxf_4~*(93) */
21044     { reserved_block      , 0                   , 0   , 32,
21045        0xfc00ffff, 0xc000bd3c, 0                      , 0,
21046        0x0                 },        /* POOL32Sxf_4~*(94) */
21047     { reserved_block      , 0                   , 0   , 32,
21048        0xfc00ffff, 0xc000bf3c, 0                      , 0,
21049        0x0                 },        /* POOL32Sxf_4~*(95) */
21050     { reserved_block      , 0                   , 0   , 32,
21051        0xfc00ffff, 0xc000c13c, 0                      , 0,
21052        0x0                 },        /* POOL32Sxf_4~*(96) */
21053     { reserved_block      , 0                   , 0   , 32,
21054        0xfc00ffff, 0xc000c33c, 0                      , 0,
21055        0x0                 },        /* POOL32Sxf_4~*(97) */
21056     { reserved_block      , 0                   , 0   , 32,
21057        0xfc00ffff, 0xc000c53c, 0                      , 0,
21058        0x0                 },        /* POOL32Sxf_4~*(98) */
21059     { reserved_block      , 0                   , 0   , 32,
21060        0xfc00ffff, 0xc000c73c, 0                      , 0,
21061        0x0                 },        /* POOL32Sxf_4~*(99) */
21062     { reserved_block      , 0                   , 0   , 32,
21063        0xfc00ffff, 0xc000c93c, 0                      , 0,
21064        0x0                 },        /* POOL32Sxf_4~*(100) */
21065     { reserved_block      , 0                   , 0   , 32,
21066        0xfc00ffff, 0xc000cb3c, 0                      , 0,
21067        0x0                 },        /* POOL32Sxf_4~*(101) */
21068     { reserved_block      , 0                   , 0   , 32,
21069        0xfc00ffff, 0xc000cd3c, 0                      , 0,
21070        0x0                 },        /* POOL32Sxf_4~*(102) */
21071     { reserved_block      , 0                   , 0   , 32,
21072        0xfc00ffff, 0xc000cf3c, 0                      , 0,
21073        0x0                 },        /* POOL32Sxf_4~*(103) */
21074     { reserved_block      , 0                   , 0   , 32,
21075        0xfc00ffff, 0xc000d13c, 0                      , 0,
21076        0x0                 },        /* POOL32Sxf_4~*(104) */
21077     { reserved_block      , 0                   , 0   , 32,
21078        0xfc00ffff, 0xc000d33c, 0                      , 0,
21079        0x0                 },        /* POOL32Sxf_4~*(105) */
21080     { reserved_block      , 0                   , 0   , 32,
21081        0xfc00ffff, 0xc000d53c, 0                      , 0,
21082        0x0                 },        /* POOL32Sxf_4~*(106) */
21083     { reserved_block      , 0                   , 0   , 32,
21084        0xfc00ffff, 0xc000d73c, 0                      , 0,
21085        0x0                 },        /* POOL32Sxf_4~*(107) */
21086     { reserved_block      , 0                   , 0   , 32,
21087        0xfc00ffff, 0xc000d93c, 0                      , 0,
21088        0x0                 },        /* POOL32Sxf_4~*(108) */
21089     { reserved_block      , 0                   , 0   , 32,
21090        0xfc00ffff, 0xc000db3c, 0                      , 0,
21091        0x0                 },        /* POOL32Sxf_4~*(109) */
21092     { reserved_block      , 0                   , 0   , 32,
21093        0xfc00ffff, 0xc000dd3c, 0                      , 0,
21094        0x0                 },        /* POOL32Sxf_4~*(110) */
21095     { reserved_block      , 0                   , 0   , 32,
21096        0xfc00ffff, 0xc000df3c, 0                      , 0,
21097        0x0                 },        /* POOL32Sxf_4~*(111) */
21098     { reserved_block      , 0                   , 0   , 32,
21099        0xfc00ffff, 0xc000e13c, 0                      , 0,
21100        0x0                 },        /* POOL32Sxf_4~*(112) */
21101     { reserved_block      , 0                   , 0   , 32,
21102        0xfc00ffff, 0xc000e33c, 0                      , 0,
21103        0x0                 },        /* POOL32Sxf_4~*(113) */
21104     { reserved_block      , 0                   , 0   , 32,
21105        0xfc00ffff, 0xc000e53c, 0                      , 0,
21106        0x0                 },        /* POOL32Sxf_4~*(114) */
21107     { reserved_block      , 0                   , 0   , 32,
21108        0xfc00ffff, 0xc000e73c, 0                      , 0,
21109        0x0                 },        /* POOL32Sxf_4~*(115) */
21110     { reserved_block      , 0                   , 0   , 32,
21111        0xfc00ffff, 0xc000e93c, 0                      , 0,
21112        0x0                 },        /* POOL32Sxf_4~*(116) */
21113     { reserved_block      , 0                   , 0   , 32,
21114        0xfc00ffff, 0xc000eb3c, 0                      , 0,
21115        0x0                 },        /* POOL32Sxf_4~*(117) */
21116     { reserved_block      , 0                   , 0   , 32,
21117        0xfc00ffff, 0xc000ed3c, 0                      , 0,
21118        0x0                 },        /* POOL32Sxf_4~*(118) */
21119     { reserved_block      , 0                   , 0   , 32,
21120        0xfc00ffff, 0xc000ef3c, 0                      , 0,
21121        0x0                 },        /* POOL32Sxf_4~*(119) */
21122     { reserved_block      , 0                   , 0   , 32,
21123        0xfc00ffff, 0xc000f13c, 0                      , 0,
21124        0x0                 },        /* POOL32Sxf_4~*(120) */
21125     { reserved_block      , 0                   , 0   , 32,
21126        0xfc00ffff, 0xc000f33c, 0                      , 0,
21127        0x0                 },        /* POOL32Sxf_4~*(121) */
21128     { reserved_block      , 0                   , 0   , 32,
21129        0xfc00ffff, 0xc000f53c, 0                      , 0,
21130        0x0                 },        /* POOL32Sxf_4~*(122) */
21131     { reserved_block      , 0                   , 0   , 32,
21132        0xfc00ffff, 0xc000f73c, 0                      , 0,
21133        0x0                 },        /* POOL32Sxf_4~*(123) */
21134     { reserved_block      , 0                   , 0   , 32,
21135        0xfc00ffff, 0xc000f93c, 0                      , 0,
21136        0x0                 },        /* POOL32Sxf_4~*(124) */
21137     { reserved_block      , 0                   , 0   , 32,
21138        0xfc00ffff, 0xc000fb3c, 0                      , 0,
21139        0x0                 },        /* POOL32Sxf_4~*(125) */
21140     { reserved_block      , 0                   , 0   , 32,
21141        0xfc00ffff, 0xc000fd3c, 0                      , 0,
21142        0x0                 },        /* POOL32Sxf_4~*(126) */
21143     { reserved_block      , 0                   , 0   , 32,
21144        0xfc00ffff, 0xc000ff3c, 0                      , 0,
21145        0x0                 },        /* POOL32Sxf_4~*(127) */
21146 };
21147
21148
21149 NMD::Pool NMD::POOL32Sxf[8] = {
21150     { reserved_block      , 0                   , 0   , 32,
21151        0xfc0001ff, 0xc000003c, 0                      , 0,
21152        0x0                 },        /* POOL32Sxf~*(0) */
21153     { reserved_block      , 0                   , 0   , 32,
21154        0xfc0001ff, 0xc000007c, 0                      , 0,
21155        0x0                 },        /* POOL32Sxf~*(1) */
21156     { reserved_block      , 0                   , 0   , 32,
21157        0xfc0001ff, 0xc00000bc, 0                      , 0,
21158        0x0                 },        /* POOL32Sxf~*(2) */
21159     { reserved_block      , 0                   , 0   , 32,
21160        0xfc0001ff, 0xc00000fc, 0                      , 0,
21161        0x0                 },        /* POOL32Sxf~*(3) */
21162     { pool                , POOL32Sxf_4         , 128 , 32,
21163        0xfc0001ff, 0xc000013c, 0                      , 0,
21164        0x0                 },        /* POOL32Sxf_4 */
21165     { reserved_block      , 0                   , 0   , 32,
21166        0xfc0001ff, 0xc000017c, 0                      , 0,
21167        0x0                 },        /* POOL32Sxf~*(5) */
21168     { reserved_block      , 0                   , 0   , 32,
21169        0xfc0001ff, 0xc00001bc, 0                      , 0,
21170        0x0                 },        /* POOL32Sxf~*(6) */
21171     { reserved_block      , 0                   , 0   , 32,
21172        0xfc0001ff, 0xc00001fc, 0                      , 0,
21173        0x0                 },        /* POOL32Sxf~*(7) */
21174 };
21175
21176
21177 NMD::Pool NMD::POOL32S_4[8] = {
21178     { instruction         , 0                   , 0   , 32,
21179        0xfc00003f, 0xc0000004, &NMD::EXTD             , 0,
21180        MIPS64_             },        /* EXTD */
21181     { instruction         , 0                   , 0   , 32,
21182        0xfc00003f, 0xc000000c, &NMD::EXTD32           , 0,
21183        MIPS64_             },        /* EXTD32 */
21184     { reserved_block      , 0                   , 0   , 32,
21185        0xfc00003f, 0xc0000014, 0                      , 0,
21186        0x0                 },        /* POOL32S_4~*(2) */
21187     { reserved_block      , 0                   , 0   , 32,
21188        0xfc00003f, 0xc000001c, 0                      , 0,
21189        0x0                 },        /* POOL32S_4~*(3) */
21190     { reserved_block      , 0                   , 0   , 32,
21191        0xfc00003f, 0xc0000024, 0                      , 0,
21192        0x0                 },        /* POOL32S_4~*(4) */
21193     { reserved_block      , 0                   , 0   , 32,
21194        0xfc00003f, 0xc000002c, 0                      , 0,
21195        0x0                 },        /* POOL32S_4~*(5) */
21196     { reserved_block      , 0                   , 0   , 32,
21197        0xfc00003f, 0xc0000034, 0                      , 0,
21198        0x0                 },        /* POOL32S_4~*(6) */
21199     { pool                , POOL32Sxf           , 8   , 32,
21200        0xfc00003f, 0xc000003c, 0                      , 0,
21201        0x0                 },        /* POOL32Sxf */
21202 };
21203
21204
21205 NMD::Pool NMD::POOL32S[8] = {
21206     { pool                , POOL32S_0           , 64  , 32,
21207        0xfc000007, 0xc0000000, 0                      , 0,
21208        0x0                 },        /* POOL32S_0 */
21209     { reserved_block      , 0                   , 0   , 32,
21210        0xfc000007, 0xc0000001, 0                      , 0,
21211        0x0                 },        /* POOL32S~*(1) */
21212     { reserved_block      , 0                   , 0   , 32,
21213        0xfc000007, 0xc0000002, 0                      , 0,
21214        0x0                 },        /* POOL32S~*(2) */
21215     { reserved_block      , 0                   , 0   , 32,
21216        0xfc000007, 0xc0000003, 0                      , 0,
21217        0x0                 },        /* POOL32S~*(3) */
21218     { pool                , POOL32S_4           , 8   , 32,
21219        0xfc000007, 0xc0000004, 0                      , 0,
21220        0x0                 },        /* POOL32S_4 */
21221     { reserved_block      , 0                   , 0   , 32,
21222        0xfc000007, 0xc0000005, 0                      , 0,
21223        0x0                 },        /* POOL32S~*(5) */
21224     { reserved_block      , 0                   , 0   , 32,
21225        0xfc000007, 0xc0000006, 0                      , 0,
21226        0x0                 },        /* POOL32S~*(6) */
21227     { reserved_block      , 0                   , 0   , 32,
21228        0xfc000007, 0xc0000007, 0                      , 0,
21229        0x0                 },        /* POOL32S~*(7) */
21230 };
21231
21232
21233 NMD::Pool NMD::P_LUI[2] = {
21234     { instruction         , 0                   , 0   , 32,
21235        0xfc000002, 0xe0000000, &NMD::LUI              , 0,
21236        0x0                 },        /* LUI */
21237     { instruction         , 0                   , 0   , 32,
21238        0xfc000002, 0xe0000002, &NMD::ALUIPC           , 0,
21239        0x0                 },        /* ALUIPC */
21240 };
21241
21242
21243 NMD::Pool NMD::P_GP_LH[2] = {
21244     { instruction         , 0                   , 0   , 32,
21245        0xfc1c0001, 0x44100000, &NMD::LH_GP_           , 0,
21246        0x0                 },        /* LH[GP] */
21247     { instruction         , 0                   , 0   , 32,
21248        0xfc1c0001, 0x44100001, &NMD::LHU_GP_          , 0,
21249        0x0                 },        /* LHU[GP] */
21250 };
21251
21252
21253 NMD::Pool NMD::P_GP_SH[2] = {
21254     { instruction         , 0                   , 0   , 32,
21255        0xfc1c0001, 0x44140000, &NMD::SH_GP_           , 0,
21256        0x0                 },        /* SH[GP] */
21257     { reserved_block      , 0                   , 0   , 32,
21258        0xfc1c0001, 0x44140001, 0                      , 0,
21259        0x0                 },        /* P.GP.SH~*(1) */
21260 };
21261
21262
21263 NMD::Pool NMD::P_GP_CP1[4] = {
21264     { instruction         , 0                   , 0   , 32,
21265        0xfc1c0003, 0x44180000, &NMD::LWC1_GP_         , 0,
21266        CP1_                },        /* LWC1[GP] */
21267     { instruction         , 0                   , 0   , 32,
21268        0xfc1c0003, 0x44180001, &NMD::SWC1_GP_         , 0,
21269        CP1_                },        /* SWC1[GP] */
21270     { instruction         , 0                   , 0   , 32,
21271        0xfc1c0003, 0x44180002, &NMD::LDC1_GP_         , 0,
21272        CP1_                },        /* LDC1[GP] */
21273     { instruction         , 0                   , 0   , 32,
21274        0xfc1c0003, 0x44180003, &NMD::SDC1_GP_         , 0,
21275        CP1_                },        /* SDC1[GP] */
21276 };
21277
21278
21279 NMD::Pool NMD::P_GP_M64[4] = {
21280     { instruction         , 0                   , 0   , 32,
21281        0xfc1c0003, 0x441c0000, &NMD::LWU_GP_          , 0,
21282        MIPS64_             },        /* LWU[GP] */
21283     { reserved_block      , 0                   , 0   , 32,
21284        0xfc1c0003, 0x441c0001, 0                      , 0,
21285        0x0                 },        /* P.GP.M64~*(1) */
21286     { reserved_block      , 0                   , 0   , 32,
21287        0xfc1c0003, 0x441c0002, 0                      , 0,
21288        0x0                 },        /* P.GP.M64~*(2) */
21289     { reserved_block      , 0                   , 0   , 32,
21290        0xfc1c0003, 0x441c0003, 0                      , 0,
21291        0x0                 },        /* P.GP.M64~*(3) */
21292 };
21293
21294
21295 NMD::Pool NMD::P_GP_BH[8] = {
21296     { instruction         , 0                   , 0   , 32,
21297        0xfc1c0000, 0x44000000, &NMD::LB_GP_           , 0,
21298        0x0                 },        /* LB[GP] */
21299     { instruction         , 0                   , 0   , 32,
21300        0xfc1c0000, 0x44040000, &NMD::SB_GP_           , 0,
21301        0x0                 },        /* SB[GP] */
21302     { instruction         , 0                   , 0   , 32,
21303        0xfc1c0000, 0x44080000, &NMD::LBU_GP_          , 0,
21304        0x0                 },        /* LBU[GP] */
21305     { instruction         , 0                   , 0   , 32,
21306        0xfc1c0000, 0x440c0000, &NMD::ADDIU_GP_B_      , 0,
21307        0x0                 },        /* ADDIU[GP.B] */
21308     { pool                , P_GP_LH             , 2   , 32,
21309        0xfc1c0000, 0x44100000, 0                      , 0,
21310        0x0                 },        /* P.GP.LH */
21311     { pool                , P_GP_SH             , 2   , 32,
21312        0xfc1c0000, 0x44140000, 0                      , 0,
21313        0x0                 },        /* P.GP.SH */
21314     { pool                , P_GP_CP1            , 4   , 32,
21315        0xfc1c0000, 0x44180000, 0                      , 0,
21316        0x0                 },        /* P.GP.CP1 */
21317     { pool                , P_GP_M64            , 4   , 32,
21318        0xfc1c0000, 0x441c0000, 0                      , 0,
21319        0x0                 },        /* P.GP.M64 */
21320 };
21321
21322
21323 NMD::Pool NMD::P_LS_U12[16] = {
21324     { instruction         , 0                   , 0   , 32,
21325        0xfc00f000, 0x84000000, &NMD::LB_U12_          , 0,
21326        0x0                 },        /* LB[U12] */
21327     { instruction         , 0                   , 0   , 32,
21328        0xfc00f000, 0x84001000, &NMD::SB_U12_          , 0,
21329        0x0                 },        /* SB[U12] */
21330     { instruction         , 0                   , 0   , 32,
21331        0xfc00f000, 0x84002000, &NMD::LBU_U12_         , 0,
21332        0x0                 },        /* LBU[U12] */
21333     { instruction         , 0                   , 0   , 32,
21334        0xfc00f000, 0x84003000, &NMD::PREF_U12_        , 0,
21335        0x0                 },        /* PREF[U12] */
21336     { instruction         , 0                   , 0   , 32,
21337        0xfc00f000, 0x84004000, &NMD::LH_U12_          , 0,
21338        0x0                 },        /* LH[U12] */
21339     { instruction         , 0                   , 0   , 32,
21340        0xfc00f000, 0x84005000, &NMD::SH_U12_          , 0,
21341        0x0                 },        /* SH[U12] */
21342     { instruction         , 0                   , 0   , 32,
21343        0xfc00f000, 0x84006000, &NMD::LHU_U12_         , 0,
21344        0x0                 },        /* LHU[U12] */
21345     { instruction         , 0                   , 0   , 32,
21346        0xfc00f000, 0x84007000, &NMD::LWU_U12_         , 0,
21347        MIPS64_             },        /* LWU[U12] */
21348     { instruction         , 0                   , 0   , 32,
21349        0xfc00f000, 0x84008000, &NMD::LW_U12_          , 0,
21350        0x0                 },        /* LW[U12] */
21351     { instruction         , 0                   , 0   , 32,
21352        0xfc00f000, 0x84009000, &NMD::SW_U12_          , 0,
21353        0x0                 },        /* SW[U12] */
21354     { instruction         , 0                   , 0   , 32,
21355        0xfc00f000, 0x8400a000, &NMD::LWC1_U12_        , 0,
21356        CP1_                },        /* LWC1[U12] */
21357     { instruction         , 0                   , 0   , 32,
21358        0xfc00f000, 0x8400b000, &NMD::SWC1_U12_        , 0,
21359        CP1_                },        /* SWC1[U12] */
21360     { instruction         , 0                   , 0   , 32,
21361        0xfc00f000, 0x8400c000, &NMD::LD_U12_          , 0,
21362        MIPS64_             },        /* LD[U12] */
21363     { instruction         , 0                   , 0   , 32,
21364        0xfc00f000, 0x8400d000, &NMD::SD_U12_          , 0,
21365        MIPS64_             },        /* SD[U12] */
21366     { instruction         , 0                   , 0   , 32,
21367        0xfc00f000, 0x8400e000, &NMD::LDC1_U12_        , 0,
21368        CP1_                },        /* LDC1[U12] */
21369     { instruction         , 0                   , 0   , 32,
21370        0xfc00f000, 0x8400f000, &NMD::SDC1_U12_        , 0,
21371        CP1_                },        /* SDC1[U12] */
21372 };
21373
21374
21375 NMD::Pool NMD::P_PREF_S9_[2] = {
21376     { instruction         , 0                   , 0   , 32,
21377        0xffe07f00, 0xa7e01800, &NMD::SYNCI            , 0,
21378        0x0                 },        /* SYNCI */
21379     { instruction         , 0                   , 0   , 32,
21380        0xfc007f00, 0xa4001800, &NMD::PREF_S9_         , &NMD::PREF_S9__cond    ,
21381        0x0                 },        /* PREF[S9] */
21382 };
21383
21384
21385 NMD::Pool NMD::P_LS_S0[16] = {
21386     { instruction         , 0                   , 0   , 32,
21387        0xfc007f00, 0xa4000000, &NMD::LB_S9_           , 0,
21388        0x0                 },        /* LB[S9] */
21389     { instruction         , 0                   , 0   , 32,
21390        0xfc007f00, 0xa4000800, &NMD::SB_S9_           , 0,
21391        0x0                 },        /* SB[S9] */
21392     { instruction         , 0                   , 0   , 32,
21393        0xfc007f00, 0xa4001000, &NMD::LBU_S9_          , 0,
21394        0x0                 },        /* LBU[S9] */
21395     { pool                , P_PREF_S9_          , 2   , 32,
21396        0xfc007f00, 0xa4001800, 0                      , 0,
21397        0x0                 },        /* P.PREF[S9] */
21398     { instruction         , 0                   , 0   , 32,
21399        0xfc007f00, 0xa4002000, &NMD::LH_S9_           , 0,
21400        0x0                 },        /* LH[S9] */
21401     { instruction         , 0                   , 0   , 32,
21402        0xfc007f00, 0xa4002800, &NMD::SH_S9_           , 0,
21403        0x0                 },        /* SH[S9] */
21404     { instruction         , 0                   , 0   , 32,
21405        0xfc007f00, 0xa4003000, &NMD::LHU_S9_          , 0,
21406        0x0                 },        /* LHU[S9] */
21407     { instruction         , 0                   , 0   , 32,
21408        0xfc007f00, 0xa4003800, &NMD::LWU_S9_          , 0,
21409        MIPS64_             },        /* LWU[S9] */
21410     { instruction         , 0                   , 0   , 32,
21411        0xfc007f00, 0xa4004000, &NMD::LW_S9_           , 0,
21412        0x0                 },        /* LW[S9] */
21413     { instruction         , 0                   , 0   , 32,
21414        0xfc007f00, 0xa4004800, &NMD::SW_S9_           , 0,
21415        0x0                 },        /* SW[S9] */
21416     { instruction         , 0                   , 0   , 32,
21417        0xfc007f00, 0xa4005000, &NMD::LWC1_S9_         , 0,
21418        CP1_                },        /* LWC1[S9] */
21419     { instruction         , 0                   , 0   , 32,
21420        0xfc007f00, 0xa4005800, &NMD::SWC1_S9_         , 0,
21421        CP1_                },        /* SWC1[S9] */
21422     { instruction         , 0                   , 0   , 32,
21423        0xfc007f00, 0xa4006000, &NMD::LD_S9_           , 0,
21424        MIPS64_             },        /* LD[S9] */
21425     { instruction         , 0                   , 0   , 32,
21426        0xfc007f00, 0xa4006800, &NMD::SD_S9_           , 0,
21427        MIPS64_             },        /* SD[S9] */
21428     { instruction         , 0                   , 0   , 32,
21429        0xfc007f00, 0xa4007000, &NMD::LDC1_S9_         , 0,
21430        CP1_                },        /* LDC1[S9] */
21431     { instruction         , 0                   , 0   , 32,
21432        0xfc007f00, 0xa4007800, &NMD::SDC1_S9_         , 0,
21433        CP1_                },        /* SDC1[S9] */
21434 };
21435
21436
21437 NMD::Pool NMD::ASET_ACLR[2] = {
21438     { instruction         , 0                   , 0   , 32,
21439        0xfe007f00, 0xa4001100, &NMD::ASET             , 0,
21440        MCU_                },        /* ASET */
21441     { instruction         , 0                   , 0   , 32,
21442        0xfe007f00, 0xa6001100, &NMD::ACLR             , 0,
21443        MCU_                },        /* ACLR */
21444 };
21445
21446
21447 NMD::Pool NMD::P_LL[4] = {
21448     { instruction         , 0                   , 0   , 32,
21449        0xfc007f03, 0xa4005100, &NMD::LL               , 0,
21450        0x0                 },        /* LL */
21451     { instruction         , 0                   , 0   , 32,
21452        0xfc007f03, 0xa4005101, &NMD::LLWP             , 0,
21453        XNP_                },        /* LLWP */
21454     { reserved_block      , 0                   , 0   , 32,
21455        0xfc007f03, 0xa4005102, 0                      , 0,
21456        0x0                 },        /* P.LL~*(2) */
21457     { reserved_block      , 0                   , 0   , 32,
21458        0xfc007f03, 0xa4005103, 0                      , 0,
21459        0x0                 },        /* P.LL~*(3) */
21460 };
21461
21462
21463 NMD::Pool NMD::P_SC[4] = {
21464     { instruction         , 0                   , 0   , 32,
21465        0xfc007f03, 0xa4005900, &NMD::SC               , 0,
21466        0x0                 },        /* SC */
21467     { instruction         , 0                   , 0   , 32,
21468        0xfc007f03, 0xa4005901, &NMD::SCWP             , 0,
21469        XNP_                },        /* SCWP */
21470     { reserved_block      , 0                   , 0   , 32,
21471        0xfc007f03, 0xa4005902, 0                      , 0,
21472        0x0                 },        /* P.SC~*(2) */
21473     { reserved_block      , 0                   , 0   , 32,
21474        0xfc007f03, 0xa4005903, 0                      , 0,
21475        0x0                 },        /* P.SC~*(3) */
21476 };
21477
21478
21479 NMD::Pool NMD::P_LLD[8] = {
21480     { instruction         , 0                   , 0   , 32,
21481        0xfc007f07, 0xa4007100, &NMD::LLD              , 0,
21482        MIPS64_             },        /* LLD */
21483     { instruction         , 0                   , 0   , 32,
21484        0xfc007f07, 0xa4007101, &NMD::LLDP             , 0,
21485        MIPS64_             },        /* LLDP */
21486     { reserved_block      , 0                   , 0   , 32,
21487        0xfc007f07, 0xa4007102, 0                      , 0,
21488        0x0                 },        /* P.LLD~*(2) */
21489     { reserved_block      , 0                   , 0   , 32,
21490        0xfc007f07, 0xa4007103, 0                      , 0,
21491        0x0                 },        /* P.LLD~*(3) */
21492     { reserved_block      , 0                   , 0   , 32,
21493        0xfc007f07, 0xa4007104, 0                      , 0,
21494        0x0                 },        /* P.LLD~*(4) */
21495     { reserved_block      , 0                   , 0   , 32,
21496        0xfc007f07, 0xa4007105, 0                      , 0,
21497        0x0                 },        /* P.LLD~*(5) */
21498     { reserved_block      , 0                   , 0   , 32,
21499        0xfc007f07, 0xa4007106, 0                      , 0,
21500        0x0                 },        /* P.LLD~*(6) */
21501     { reserved_block      , 0                   , 0   , 32,
21502        0xfc007f07, 0xa4007107, 0                      , 0,
21503        0x0                 },        /* P.LLD~*(7) */
21504 };
21505
21506
21507 NMD::Pool NMD::P_SCD[8] = {
21508     { instruction         , 0                   , 0   , 32,
21509        0xfc007f07, 0xa4007900, &NMD::SCD              , 0,
21510        MIPS64_             },        /* SCD */
21511     { instruction         , 0                   , 0   , 32,
21512        0xfc007f07, 0xa4007901, &NMD::SCDP             , 0,
21513        MIPS64_             },        /* SCDP */
21514     { reserved_block      , 0                   , 0   , 32,
21515        0xfc007f07, 0xa4007902, 0                      , 0,
21516        0x0                 },        /* P.SCD~*(2) */
21517     { reserved_block      , 0                   , 0   , 32,
21518        0xfc007f07, 0xa4007903, 0                      , 0,
21519        0x0                 },        /* P.SCD~*(3) */
21520     { reserved_block      , 0                   , 0   , 32,
21521        0xfc007f07, 0xa4007904, 0                      , 0,
21522        0x0                 },        /* P.SCD~*(4) */
21523     { reserved_block      , 0                   , 0   , 32,
21524        0xfc007f07, 0xa4007905, 0                      , 0,
21525        0x0                 },        /* P.SCD~*(5) */
21526     { reserved_block      , 0                   , 0   , 32,
21527        0xfc007f07, 0xa4007906, 0                      , 0,
21528        0x0                 },        /* P.SCD~*(6) */
21529     { reserved_block      , 0                   , 0   , 32,
21530        0xfc007f07, 0xa4007907, 0                      , 0,
21531        0x0                 },        /* P.SCD~*(7) */
21532 };
21533
21534
21535 NMD::Pool NMD::P_LS_S1[16] = {
21536     { reserved_block      , 0                   , 0   , 32,
21537        0xfc007f00, 0xa4000100, 0                      , 0,
21538        0x0                 },        /* P.LS.S1~*(0) */
21539     { reserved_block      , 0                   , 0   , 32,
21540        0xfc007f00, 0xa4000900, 0                      , 0,
21541        0x0                 },        /* P.LS.S1~*(1) */
21542     { pool                , ASET_ACLR           , 2   , 32,
21543        0xfc007f00, 0xa4001100, 0                      , 0,
21544        0x0                 },        /* ASET_ACLR */
21545     { reserved_block      , 0                   , 0   , 32,
21546        0xfc007f00, 0xa4001900, 0                      , 0,
21547        0x0                 },        /* P.LS.S1~*(3) */
21548     { instruction         , 0                   , 0   , 32,
21549        0xfc007f00, 0xa4002100, &NMD::UALH             , 0,
21550        XMMS_               },        /* UALH */
21551     { instruction         , 0                   , 0   , 32,
21552        0xfc007f00, 0xa4002900, &NMD::UASH             , 0,
21553        XMMS_               },        /* UASH */
21554     { reserved_block      , 0                   , 0   , 32,
21555        0xfc007f00, 0xa4003100, 0                      , 0,
21556        0x0                 },        /* P.LS.S1~*(6) */
21557     { instruction         , 0                   , 0   , 32,
21558        0xfc007f00, 0xa4003900, &NMD::CACHE            , 0,
21559        CP0_                },        /* CACHE */
21560     { instruction         , 0                   , 0   , 32,
21561        0xfc007f00, 0xa4004100, &NMD::LWC2             , 0,
21562        CP2_                },        /* LWC2 */
21563     { instruction         , 0                   , 0   , 32,
21564        0xfc007f00, 0xa4004900, &NMD::SWC2             , 0,
21565        CP2_                },        /* SWC2 */
21566     { pool                , P_LL                , 4   , 32,
21567        0xfc007f00, 0xa4005100, 0                      , 0,
21568        0x0                 },        /* P.LL */
21569     { pool                , P_SC                , 4   , 32,
21570        0xfc007f00, 0xa4005900, 0                      , 0,
21571        0x0                 },        /* P.SC */
21572     { instruction         , 0                   , 0   , 32,
21573        0xfc007f00, 0xa4006100, &NMD::LDC2             , 0,
21574        CP2_                },        /* LDC2 */
21575     { instruction         , 0                   , 0   , 32,
21576        0xfc007f00, 0xa4006900, &NMD::SDC2             , 0,
21577        CP2_                },        /* SDC2 */
21578     { pool                , P_LLD               , 8   , 32,
21579        0xfc007f00, 0xa4007100, 0                      , 0,
21580        0x0                 },        /* P.LLD */
21581     { pool                , P_SCD               , 8   , 32,
21582        0xfc007f00, 0xa4007900, 0                      , 0,
21583        0x0                 },        /* P.SCD */
21584 };
21585
21586
21587 NMD::Pool NMD::P_PREFE[2] = {
21588     { instruction         , 0                   , 0   , 32,
21589        0xffe07f00, 0xa7e01a00, &NMD::SYNCIE           , 0,
21590        CP0_ | EVA_         },        /* SYNCIE */
21591     { instruction         , 0                   , 0   , 32,
21592        0xfc007f00, 0xa4001a00, &NMD::PREFE            , &NMD::PREFE_cond       ,
21593        CP0_ | EVA_         },        /* PREFE */
21594 };
21595
21596
21597 NMD::Pool NMD::P_LLE[4] = {
21598     { instruction         , 0                   , 0   , 32,
21599        0xfc007f03, 0xa4005200, &NMD::LLE              , 0,
21600        CP0_ | EVA_         },        /* LLE */
21601     { instruction         , 0                   , 0   , 32,
21602        0xfc007f03, 0xa4005201, &NMD::LLWPE            , 0,
21603        CP0_ | EVA_         },        /* LLWPE */
21604     { reserved_block      , 0                   , 0   , 32,
21605        0xfc007f03, 0xa4005202, 0                      , 0,
21606        0x0                 },        /* P.LLE~*(2) */
21607     { reserved_block      , 0                   , 0   , 32,
21608        0xfc007f03, 0xa4005203, 0                      , 0,
21609        0x0                 },        /* P.LLE~*(3) */
21610 };
21611
21612
21613 NMD::Pool NMD::P_SCE[4] = {
21614     { instruction         , 0                   , 0   , 32,
21615        0xfc007f03, 0xa4005a00, &NMD::SCE              , 0,
21616        CP0_ | EVA_         },        /* SCE */
21617     { instruction         , 0                   , 0   , 32,
21618        0xfc007f03, 0xa4005a01, &NMD::SCWPE            , 0,
21619        CP0_ | EVA_         },        /* SCWPE */
21620     { reserved_block      , 0                   , 0   , 32,
21621        0xfc007f03, 0xa4005a02, 0                      , 0,
21622        0x0                 },        /* P.SCE~*(2) */
21623     { reserved_block      , 0                   , 0   , 32,
21624        0xfc007f03, 0xa4005a03, 0                      , 0,
21625        0x0                 },        /* P.SCE~*(3) */
21626 };
21627
21628
21629 NMD::Pool NMD::P_LS_E0[16] = {
21630     { instruction         , 0                   , 0   , 32,
21631        0xfc007f00, 0xa4000200, &NMD::LBE              , 0,
21632        CP0_ | EVA_         },        /* LBE */
21633     { instruction         , 0                   , 0   , 32,
21634        0xfc007f00, 0xa4000a00, &NMD::SBE              , 0,
21635        CP0_ | EVA_         },        /* SBE */
21636     { instruction         , 0                   , 0   , 32,
21637        0xfc007f00, 0xa4001200, &NMD::LBUE             , 0,
21638        CP0_ | EVA_         },        /* LBUE */
21639     { pool                , P_PREFE             , 2   , 32,
21640        0xfc007f00, 0xa4001a00, 0                      , 0,
21641        0x0                 },        /* P.PREFE */
21642     { instruction         , 0                   , 0   , 32,
21643        0xfc007f00, 0xa4002200, &NMD::LHE              , 0,
21644        CP0_ | EVA_         },        /* LHE */
21645     { instruction         , 0                   , 0   , 32,
21646        0xfc007f00, 0xa4002a00, &NMD::SHE              , 0,
21647        CP0_ | EVA_         },        /* SHE */
21648     { instruction         , 0                   , 0   , 32,
21649        0xfc007f00, 0xa4003200, &NMD::LHUE             , 0,
21650        CP0_ | EVA_         },        /* LHUE */
21651     { instruction         , 0                   , 0   , 32,
21652        0xfc007f00, 0xa4003a00, &NMD::CACHEE           , 0,
21653        CP0_ | EVA_         },        /* CACHEE */
21654     { instruction         , 0                   , 0   , 32,
21655        0xfc007f00, 0xa4004200, &NMD::LWE              , 0,
21656        CP0_ | EVA_         },        /* LWE */
21657     { instruction         , 0                   , 0   , 32,
21658        0xfc007f00, 0xa4004a00, &NMD::SWE              , 0,
21659        CP0_ | EVA_         },        /* SWE */
21660     { pool                , P_LLE               , 4   , 32,
21661        0xfc007f00, 0xa4005200, 0                      , 0,
21662        0x0                 },        /* P.LLE */
21663     { pool                , P_SCE               , 4   , 32,
21664        0xfc007f00, 0xa4005a00, 0                      , 0,
21665        0x0                 },        /* P.SCE */
21666     { reserved_block      , 0                   , 0   , 32,
21667        0xfc007f00, 0xa4006200, 0                      , 0,
21668        0x0                 },        /* P.LS.E0~*(12) */
21669     { reserved_block      , 0                   , 0   , 32,
21670        0xfc007f00, 0xa4006a00, 0                      , 0,
21671        0x0                 },        /* P.LS.E0~*(13) */
21672     { reserved_block      , 0                   , 0   , 32,
21673        0xfc007f00, 0xa4007200, 0                      , 0,
21674        0x0                 },        /* P.LS.E0~*(14) */
21675     { reserved_block      , 0                   , 0   , 32,
21676        0xfc007f00, 0xa4007a00, 0                      , 0,
21677        0x0                 },        /* P.LS.E0~*(15) */
21678 };
21679
21680
21681 NMD::Pool NMD::P_LS_WM[2] = {
21682     { instruction         , 0                   , 0   , 32,
21683        0xfc000f00, 0xa4000400, &NMD::LWM              , 0,
21684        XMMS_               },        /* LWM */
21685     { instruction         , 0                   , 0   , 32,
21686        0xfc000f00, 0xa4000c00, &NMD::SWM              , 0,
21687        XMMS_               },        /* SWM */
21688 };
21689
21690
21691 NMD::Pool NMD::P_LS_UAWM[2] = {
21692     { instruction         , 0                   , 0   , 32,
21693        0xfc000f00, 0xa4000500, &NMD::UALWM            , 0,
21694        XMMS_               },        /* UALWM */
21695     { instruction         , 0                   , 0   , 32,
21696        0xfc000f00, 0xa4000d00, &NMD::UASWM            , 0,
21697        XMMS_               },        /* UASWM */
21698 };
21699
21700
21701 NMD::Pool NMD::P_LS_DM[2] = {
21702     { instruction         , 0                   , 0   , 32,
21703        0xfc000f00, 0xa4000600, &NMD::LDM              , 0,
21704        MIPS64_             },        /* LDM */
21705     { instruction         , 0                   , 0   , 32,
21706        0xfc000f00, 0xa4000e00, &NMD::SDM              , 0,
21707        MIPS64_             },        /* SDM */
21708 };
21709
21710
21711 NMD::Pool NMD::P_LS_UADM[2] = {
21712     { instruction         , 0                   , 0   , 32,
21713        0xfc000f00, 0xa4000700, &NMD::UALDM            , 0,
21714        MIPS64_             },        /* UALDM */
21715     { instruction         , 0                   , 0   , 32,
21716        0xfc000f00, 0xa4000f00, &NMD::UASDM            , 0,
21717        MIPS64_             },        /* UASDM */
21718 };
21719
21720
21721 NMD::Pool NMD::P_LS_S9[8] = {
21722     { pool                , P_LS_S0             , 16  , 32,
21723        0xfc000700, 0xa4000000, 0                      , 0,
21724        0x0                 },        /* P.LS.S0 */
21725     { pool                , P_LS_S1             , 16  , 32,
21726        0xfc000700, 0xa4000100, 0                      , 0,
21727        0x0                 },        /* P.LS.S1 */
21728     { pool                , P_LS_E0             , 16  , 32,
21729        0xfc000700, 0xa4000200, 0                      , 0,
21730        0x0                 },        /* P.LS.E0 */
21731     { reserved_block      , 0                   , 0   , 32,
21732        0xfc000700, 0xa4000300, 0                      , 0,
21733        0x0                 },        /* P.LS.S9~*(3) */
21734     { pool                , P_LS_WM             , 2   , 32,
21735        0xfc000700, 0xa4000400, 0                      , 0,
21736        0x0                 },        /* P.LS.WM */
21737     { pool                , P_LS_UAWM           , 2   , 32,
21738        0xfc000700, 0xa4000500, 0                      , 0,
21739        0x0                 },        /* P.LS.UAWM */
21740     { pool                , P_LS_DM             , 2   , 32,
21741        0xfc000700, 0xa4000600, 0                      , 0,
21742        0x0                 },        /* P.LS.DM */
21743     { pool                , P_LS_UADM           , 2   , 32,
21744        0xfc000700, 0xa4000700, 0                      , 0,
21745        0x0                 },        /* P.LS.UADM */
21746 };
21747
21748
21749 NMD::Pool NMD::P_BAL[2] = {
21750     { branch_instruction  , 0                   , 0   , 32,
21751        0xfe000000, 0x28000000, &NMD::BC_32_           , 0,
21752        0x0                 },        /* BC[32] */
21753     { call_instruction    , 0                   , 0   , 32,
21754        0xfe000000, 0x2a000000, &NMD::BALC_32_         , 0,
21755        0x0                 },        /* BALC[32] */
21756 };
21757
21758
21759 NMD::Pool NMD::P_BALRSC[2] = {
21760     { branch_instruction  , 0                   , 0   , 32,
21761        0xffe0f000, 0x48008000, &NMD::BRSC             , 0,
21762        0x0                 },        /* BRSC */
21763     { call_instruction    , 0                   , 0   , 32,
21764        0xfc00f000, 0x48008000, &NMD::BALRSC           , &NMD::BALRSC_cond      ,
21765        0x0                 },        /* BALRSC */
21766 };
21767
21768
21769 NMD::Pool NMD::P_J[16] = {
21770     { call_instruction    , 0                   , 0   , 32,
21771        0xfc00f000, 0x48000000, &NMD::JALRC_32_        , 0,
21772        0x0                 },        /* JALRC[32] */
21773     { call_instruction    , 0                   , 0   , 32,
21774        0xfc00f000, 0x48001000, &NMD::JALRC_HB         , 0,
21775        0x0                 },        /* JALRC.HB */
21776     { reserved_block      , 0                   , 0   , 32,
21777        0xfc00f000, 0x48002000, 0                      , 0,
21778        0x0                 },        /* P.J~*(2) */
21779     { reserved_block      , 0                   , 0   , 32,
21780        0xfc00f000, 0x48003000, 0                      , 0,
21781        0x0                 },        /* P.J~*(3) */
21782     { reserved_block      , 0                   , 0   , 32,
21783        0xfc00f000, 0x48004000, 0                      , 0,
21784        0x0                 },        /* P.J~*(4) */
21785     { reserved_block      , 0                   , 0   , 32,
21786        0xfc00f000, 0x48005000, 0                      , 0,
21787        0x0                 },        /* P.J~*(5) */
21788     { reserved_block      , 0                   , 0   , 32,
21789        0xfc00f000, 0x48006000, 0                      , 0,
21790        0x0                 },        /* P.J~*(6) */
21791     { reserved_block      , 0                   , 0   , 32,
21792        0xfc00f000, 0x48007000, 0                      , 0,
21793        0x0                 },        /* P.J~*(7) */
21794     { pool                , P_BALRSC            , 2   , 32,
21795        0xfc00f000, 0x48008000, 0                      , 0,
21796        0x0                 },        /* P.BALRSC */
21797     { reserved_block      , 0                   , 0   , 32,
21798        0xfc00f000, 0x48009000, 0                      , 0,
21799        0x0                 },        /* P.J~*(9) */
21800     { reserved_block      , 0                   , 0   , 32,
21801        0xfc00f000, 0x4800a000, 0                      , 0,
21802        0x0                 },        /* P.J~*(10) */
21803     { reserved_block      , 0                   , 0   , 32,
21804        0xfc00f000, 0x4800b000, 0                      , 0,
21805        0x0                 },        /* P.J~*(11) */
21806     { reserved_block      , 0                   , 0   , 32,
21807        0xfc00f000, 0x4800c000, 0                      , 0,
21808        0x0                 },        /* P.J~*(12) */
21809     { reserved_block      , 0                   , 0   , 32,
21810        0xfc00f000, 0x4800d000, 0                      , 0,
21811        0x0                 },        /* P.J~*(13) */
21812     { reserved_block      , 0                   , 0   , 32,
21813        0xfc00f000, 0x4800e000, 0                      , 0,
21814        0x0                 },        /* P.J~*(14) */
21815     { reserved_block      , 0                   , 0   , 32,
21816        0xfc00f000, 0x4800f000, 0                      , 0,
21817        0x0                 },        /* P.J~*(15) */
21818 };
21819
21820
21821 NMD::Pool NMD::P_BR3A[32] = {
21822     { branch_instruction  , 0                   , 0   , 32,
21823        0xfc1fc000, 0x88004000, &NMD::BC1EQZC          , 0,
21824        CP1_                },        /* BC1EQZC */
21825     { branch_instruction  , 0                   , 0   , 32,
21826        0xfc1fc000, 0x88014000, &NMD::BC1NEZC          , 0,
21827        CP1_                },        /* BC1NEZC */
21828     { branch_instruction  , 0                   , 0   , 32,
21829        0xfc1fc000, 0x88024000, &NMD::BC2EQZC          , 0,
21830        CP2_                },        /* BC2EQZC */
21831     { branch_instruction  , 0                   , 0   , 32,
21832        0xfc1fc000, 0x88034000, &NMD::BC2NEZC          , 0,
21833        CP2_                },        /* BC2NEZC */
21834     { branch_instruction  , 0                   , 0   , 32,
21835        0xfc1fc000, 0x88044000, &NMD::BPOSGE32C        , 0,
21836        DSP_                },        /* BPOSGE32C */
21837     { reserved_block      , 0                   , 0   , 32,
21838        0xfc1fc000, 0x88054000, 0                      , 0,
21839        0x0                 },        /* P.BR3A~*(5) */
21840     { reserved_block      , 0                   , 0   , 32,
21841        0xfc1fc000, 0x88064000, 0                      , 0,
21842        0x0                 },        /* P.BR3A~*(6) */
21843     { reserved_block      , 0                   , 0   , 32,
21844        0xfc1fc000, 0x88074000, 0                      , 0,
21845        0x0                 },        /* P.BR3A~*(7) */
21846     { reserved_block      , 0                   , 0   , 32,
21847        0xfc1fc000, 0x88084000, 0                      , 0,
21848        0x0                 },        /* P.BR3A~*(8) */
21849     { reserved_block      , 0                   , 0   , 32,
21850        0xfc1fc000, 0x88094000, 0                      , 0,
21851        0x0                 },        /* P.BR3A~*(9) */
21852     { reserved_block      , 0                   , 0   , 32,
21853        0xfc1fc000, 0x880a4000, 0                      , 0,
21854        0x0                 },        /* P.BR3A~*(10) */
21855     { reserved_block      , 0                   , 0   , 32,
21856        0xfc1fc000, 0x880b4000, 0                      , 0,
21857        0x0                 },        /* P.BR3A~*(11) */
21858     { reserved_block      , 0                   , 0   , 32,
21859        0xfc1fc000, 0x880c4000, 0                      , 0,
21860        0x0                 },        /* P.BR3A~*(12) */
21861     { reserved_block      , 0                   , 0   , 32,
21862        0xfc1fc000, 0x880d4000, 0                      , 0,
21863        0x0                 },        /* P.BR3A~*(13) */
21864     { reserved_block      , 0                   , 0   , 32,
21865        0xfc1fc000, 0x880e4000, 0                      , 0,
21866        0x0                 },        /* P.BR3A~*(14) */
21867     { reserved_block      , 0                   , 0   , 32,
21868        0xfc1fc000, 0x880f4000, 0                      , 0,
21869        0x0                 },        /* P.BR3A~*(15) */
21870     { reserved_block      , 0                   , 0   , 32,
21871        0xfc1fc000, 0x88104000, 0                      , 0,
21872        0x0                 },        /* P.BR3A~*(16) */
21873     { reserved_block      , 0                   , 0   , 32,
21874        0xfc1fc000, 0x88114000, 0                      , 0,
21875        0x0                 },        /* P.BR3A~*(17) */
21876     { reserved_block      , 0                   , 0   , 32,
21877        0xfc1fc000, 0x88124000, 0                      , 0,
21878        0x0                 },        /* P.BR3A~*(18) */
21879     { reserved_block      , 0                   , 0   , 32,
21880        0xfc1fc000, 0x88134000, 0                      , 0,
21881        0x0                 },        /* P.BR3A~*(19) */
21882     { reserved_block      , 0                   , 0   , 32,
21883        0xfc1fc000, 0x88144000, 0                      , 0,
21884        0x0                 },        /* P.BR3A~*(20) */
21885     { reserved_block      , 0                   , 0   , 32,
21886        0xfc1fc000, 0x88154000, 0                      , 0,
21887        0x0                 },        /* P.BR3A~*(21) */
21888     { reserved_block      , 0                   , 0   , 32,
21889        0xfc1fc000, 0x88164000, 0                      , 0,
21890        0x0                 },        /* P.BR3A~*(22) */
21891     { reserved_block      , 0                   , 0   , 32,
21892        0xfc1fc000, 0x88174000, 0                      , 0,
21893        0x0                 },        /* P.BR3A~*(23) */
21894     { reserved_block      , 0                   , 0   , 32,
21895        0xfc1fc000, 0x88184000, 0                      , 0,
21896        0x0                 },        /* P.BR3A~*(24) */
21897     { reserved_block      , 0                   , 0   , 32,
21898        0xfc1fc000, 0x88194000, 0                      , 0,
21899        0x0                 },        /* P.BR3A~*(25) */
21900     { reserved_block      , 0                   , 0   , 32,
21901        0xfc1fc000, 0x881a4000, 0                      , 0,
21902        0x0                 },        /* P.BR3A~*(26) */
21903     { reserved_block      , 0                   , 0   , 32,
21904        0xfc1fc000, 0x881b4000, 0                      , 0,
21905        0x0                 },        /* P.BR3A~*(27) */
21906     { reserved_block      , 0                   , 0   , 32,
21907        0xfc1fc000, 0x881c4000, 0                      , 0,
21908        0x0                 },        /* P.BR3A~*(28) */
21909     { reserved_block      , 0                   , 0   , 32,
21910        0xfc1fc000, 0x881d4000, 0                      , 0,
21911        0x0                 },        /* P.BR3A~*(29) */
21912     { reserved_block      , 0                   , 0   , 32,
21913        0xfc1fc000, 0x881e4000, 0                      , 0,
21914        0x0                 },        /* P.BR3A~*(30) */
21915     { reserved_block      , 0                   , 0   , 32,
21916        0xfc1fc000, 0x881f4000, 0                      , 0,
21917        0x0                 },        /* P.BR3A~*(31) */
21918 };
21919
21920
21921 NMD::Pool NMD::P_BR1[4] = {
21922     { branch_instruction  , 0                   , 0   , 32,
21923        0xfc00c000, 0x88000000, &NMD::BEQC_32_         , 0,
21924        0x0                 },        /* BEQC[32] */
21925     { pool                , P_BR3A              , 32  , 32,
21926        0xfc00c000, 0x88004000, 0                      , 0,
21927        0x0                 },        /* P.BR3A */
21928     { branch_instruction  , 0                   , 0   , 32,
21929        0xfc00c000, 0x88008000, &NMD::BGEC             , 0,
21930        0x0                 },        /* BGEC */
21931     { branch_instruction  , 0                   , 0   , 32,
21932        0xfc00c000, 0x8800c000, &NMD::BGEUC            , 0,
21933        0x0                 },        /* BGEUC */
21934 };
21935
21936
21937 NMD::Pool NMD::P_BR2[4] = {
21938     { branch_instruction  , 0                   , 0   , 32,
21939        0xfc00c000, 0xa8000000, &NMD::BNEC_32_         , 0,
21940        0x0                 },        /* BNEC[32] */
21941     { reserved_block      , 0                   , 0   , 32,
21942        0xfc00c000, 0xa8004000, 0                      , 0,
21943        0x0                 },        /* P.BR2~*(1) */
21944     { branch_instruction  , 0                   , 0   , 32,
21945        0xfc00c000, 0xa8008000, &NMD::BLTC             , 0,
21946        0x0                 },        /* BLTC */
21947     { branch_instruction  , 0                   , 0   , 32,
21948        0xfc00c000, 0xa800c000, &NMD::BLTUC            , 0,
21949        0x0                 },        /* BLTUC */
21950 };
21951
21952
21953 NMD::Pool NMD::P_BRI[8] = {
21954     { branch_instruction  , 0                   , 0   , 32,
21955        0xfc1c0000, 0xc8000000, &NMD::BEQIC            , 0,
21956        0x0                 },        /* BEQIC */
21957     { branch_instruction  , 0                   , 0   , 32,
21958        0xfc1c0000, 0xc8040000, &NMD::BBEQZC           , 0,
21959        XMMS_               },        /* BBEQZC */
21960     { branch_instruction  , 0                   , 0   , 32,
21961        0xfc1c0000, 0xc8080000, &NMD::BGEIC            , 0,
21962        0x0                 },        /* BGEIC */
21963     { branch_instruction  , 0                   , 0   , 32,
21964        0xfc1c0000, 0xc80c0000, &NMD::BGEIUC           , 0,
21965        0x0                 },        /* BGEIUC */
21966     { branch_instruction  , 0                   , 0   , 32,
21967        0xfc1c0000, 0xc8100000, &NMD::BNEIC            , 0,
21968        0x0                 },        /* BNEIC */
21969     { branch_instruction  , 0                   , 0   , 32,
21970        0xfc1c0000, 0xc8140000, &NMD::BBNEZC           , 0,
21971        XMMS_               },        /* BBNEZC */
21972     { branch_instruction  , 0                   , 0   , 32,
21973        0xfc1c0000, 0xc8180000, &NMD::BLTIC            , 0,
21974        0x0                 },        /* BLTIC */
21975     { branch_instruction  , 0                   , 0   , 32,
21976        0xfc1c0000, 0xc81c0000, &NMD::BLTIUC           , 0,
21977        0x0                 },        /* BLTIUC */
21978 };
21979
21980
21981 NMD::Pool NMD::P32[32] = {
21982     { pool                , P_ADDIU             , 2   , 32,
21983        0xfc000000, 0x00000000, 0                      , 0,
21984        0x0                 },        /* P.ADDIU */
21985     { pool                , P32A                , 8   , 32,
21986        0xfc000000, 0x20000000, 0                      , 0,
21987        0x0                 },        /* P32A */
21988     { pool                , P_GP_W              , 4   , 32,
21989        0xfc000000, 0x40000000, 0                      , 0,
21990        0x0                 },        /* P.GP.W */
21991     { pool                , POOL48I             , 32  , 48,
21992        0xfc0000000000ull, 0x600000000000ull, 0                      , 0,
21993        0x0                 },        /* POOL48I */
21994     { pool                , P_U12               , 16  , 32,
21995        0xfc000000, 0x80000000, 0                      , 0,
21996        0x0                 },        /* P.U12 */
21997     { pool                , POOL32F             , 8   , 32,
21998        0xfc000000, 0xa0000000, 0                      , 0,
21999        CP1_                },        /* POOL32F */
22000     { pool                , POOL32S             , 8   , 32,
22001        0xfc000000, 0xc0000000, 0                      , 0,
22002        0x0                 },        /* POOL32S */
22003     { pool                , P_LUI               , 2   , 32,
22004        0xfc000000, 0xe0000000, 0                      , 0,
22005        0x0                 },        /* P.LUI */
22006     { instruction         , 0                   , 0   , 32,
22007        0xfc000000, 0x04000000, &NMD::ADDIUPC_32_      , 0,
22008        0x0                 },        /* ADDIUPC[32] */
22009     { reserved_block      , 0                   , 0   , 32,
22010        0xfc000000, 0x24000000, 0                      , 0,
22011        0x0                 },        /* P32~*(5) */
22012     { pool                , P_GP_BH             , 8   , 32,
22013        0xfc000000, 0x44000000, 0                      , 0,
22014        0x0                 },        /* P.GP.BH */
22015     { reserved_block      , 0                   , 0   , 32,
22016        0xfc000000, 0x64000000, 0                      , 0,
22017        0x0                 },        /* P32~*(13) */
22018     { pool                , P_LS_U12            , 16  , 32,
22019        0xfc000000, 0x84000000, 0                      , 0,
22020        0x0                 },        /* P.LS.U12 */
22021     { pool                , P_LS_S9             , 8   , 32,
22022        0xfc000000, 0xa4000000, 0                      , 0,
22023        0x0                 },        /* P.LS.S9 */
22024     { reserved_block      , 0                   , 0   , 32,
22025        0xfc000000, 0xc4000000, 0                      , 0,
22026        0x0                 },        /* P32~*(25) */
22027     { reserved_block      , 0                   , 0   , 32,
22028        0xfc000000, 0xe4000000, 0                      , 0,
22029        0x0                 },        /* P32~*(29) */
22030     { call_instruction    , 0                   , 0   , 32,
22031        0xfc000000, 0x08000000, &NMD::MOVE_BALC        , 0,
22032        XMMS_               },        /* MOVE.BALC */
22033     { pool                , P_BAL               , 2   , 32,
22034        0xfc000000, 0x28000000, 0                      , 0,
22035        0x0                 },        /* P.BAL */
22036     { pool                , P_J                 , 16  , 32,
22037        0xfc000000, 0x48000000, 0                      , 0,
22038        0x0                 },        /* P.J */
22039     { reserved_block      , 0                   , 0   , 32,
22040        0xfc000000, 0x68000000, 0                      , 0,
22041        0x0                 },        /* P32~*(14) */
22042     { pool                , P_BR1               , 4   , 32,
22043        0xfc000000, 0x88000000, 0                      , 0,
22044        0x0                 },        /* P.BR1 */
22045     { pool                , P_BR2               , 4   , 32,
22046        0xfc000000, 0xa8000000, 0                      , 0,
22047        0x0                 },        /* P.BR2 */
22048     { pool                , P_BRI               , 8   , 32,
22049        0xfc000000, 0xc8000000, 0                      , 0,
22050        0x0                 },        /* P.BRI */
22051     { reserved_block      , 0                   , 0   , 32,
22052        0xfc000000, 0xe8000000, 0                      , 0,
22053        0x0                 },        /* P32~*(30) */
22054     { reserved_block      , 0                   , 0   , 32,
22055        0xfc000000, 0x0c000000, 0                      , 0,
22056        0x0                 },        /* P32~*(3) */
22057     { reserved_block      , 0                   , 0   , 32,
22058        0xfc000000, 0x2c000000, 0                      , 0,
22059        0x0                 },        /* P32~*(7) */
22060     { reserved_block      , 0                   , 0   , 32,
22061        0xfc000000, 0x4c000000, 0                      , 0,
22062        0x0                 },        /* P32~*(11) */
22063     { reserved_block      , 0                   , 0   , 32,
22064        0xfc000000, 0x6c000000, 0                      , 0,
22065        0x0                 },        /* P32~*(15) */
22066     { reserved_block      , 0                   , 0   , 32,
22067        0xfc000000, 0x8c000000, 0                      , 0,
22068        0x0                 },        /* P32~*(19) */
22069     { reserved_block      , 0                   , 0   , 32,
22070        0xfc000000, 0xac000000, 0                      , 0,
22071        0x0                 },        /* P32~*(23) */
22072     { reserved_block      , 0                   , 0   , 32,
22073        0xfc000000, 0xcc000000, 0                      , 0,
22074        0x0                 },        /* P32~*(27) */
22075     { reserved_block      , 0                   , 0   , 32,
22076        0xfc000000, 0xec000000, 0                      , 0,
22077        0x0                 },        /* P32~*(31) */
22078 };
22079
22080
22081 NMD::Pool NMD::P16_SYSCALL[2] = {
22082     { instruction         , 0                   , 0   , 16,
22083        0xfffc    , 0x1008    , &NMD::SYSCALL_16_      , 0,
22084        0x0                 },        /* SYSCALL[16] */
22085     { instruction         , 0                   , 0   , 16,
22086        0xfffc    , 0x100c    , &NMD::HYPCALL_16_      , 0,
22087        CP0_ | VZ_          },        /* HYPCALL[16] */
22088 };
22089
22090
22091 NMD::Pool NMD::P16_RI[4] = {
22092     { reserved_block      , 0                   , 0   , 16,
22093        0xfff8    , 0x1000    , 0                      , 0,
22094        0x0                 },        /* P16.RI~*(0) */
22095     { pool                , P16_SYSCALL         , 2   , 16,
22096        0xfff8    , 0x1008    , 0                      , 0,
22097        0x0                 },        /* P16.SYSCALL */
22098     { instruction         , 0                   , 0   , 16,
22099        0xfff8    , 0x1010    , &NMD::BREAK_16_        , 0,
22100        0x0                 },        /* BREAK[16] */
22101     { instruction         , 0                   , 0   , 16,
22102        0xfff8    , 0x1018    , &NMD::SDBBP_16_        , 0,
22103        EJTAG_              },        /* SDBBP[16] */
22104 };
22105
22106
22107 NMD::Pool NMD::P16_MV[2] = {
22108     { pool                , P16_RI              , 4   , 16,
22109        0xffe0    , 0x1000    , 0                      , 0,
22110        0x0                 },        /* P16.RI */
22111     { instruction         , 0                   , 0   , 16,
22112        0xfc00    , 0x1000    , &NMD::MOVE             , &NMD::MOVE_cond        ,
22113        0x0                 },        /* MOVE */
22114 };
22115
22116
22117 NMD::Pool NMD::P16_SHIFT[2] = {
22118     { instruction         , 0                   , 0   , 16,
22119        0xfc08    , 0x3000    , &NMD::SLL_16_          , 0,
22120        0x0                 },        /* SLL[16] */
22121     { instruction         , 0                   , 0   , 16,
22122        0xfc08    , 0x3008    , &NMD::SRL_16_          , 0,
22123        0x0                 },        /* SRL[16] */
22124 };
22125
22126
22127 NMD::Pool NMD::POOL16C_00[4] = {
22128     { instruction         , 0                   , 0   , 16,
22129        0xfc0f    , 0x5000    , &NMD::NOT_16_          , 0,
22130        0x0                 },        /* NOT[16] */
22131     { instruction         , 0                   , 0   , 16,
22132        0xfc0f    , 0x5004    , &NMD::XOR_16_          , 0,
22133        0x0                 },        /* XOR[16] */
22134     { instruction         , 0                   , 0   , 16,
22135        0xfc0f    , 0x5008    , &NMD::AND_16_          , 0,
22136        0x0                 },        /* AND[16] */
22137     { instruction         , 0                   , 0   , 16,
22138        0xfc0f    , 0x500c    , &NMD::OR_16_           , 0,
22139        0x0                 },        /* OR[16] */
22140 };
22141
22142
22143 NMD::Pool NMD::POOL16C_0[2] = {
22144     { pool                , POOL16C_00          , 4   , 16,
22145        0xfc03    , 0x5000    , 0                      , 0,
22146        0x0                 },        /* POOL16C_00 */
22147     { reserved_block      , 0                   , 0   , 16,
22148        0xfc03    , 0x5002    , 0                      , 0,
22149        0x0                 },        /* POOL16C_0~*(1) */
22150 };
22151
22152
22153 NMD::Pool NMD::P16C[2] = {
22154     { pool                , POOL16C_0           , 2   , 16,
22155        0xfc01    , 0x5000    , 0                      , 0,
22156        0x0                 },        /* POOL16C_0 */
22157     { instruction         , 0                   , 0   , 16,
22158        0xfc01    , 0x5001    , &NMD::LWXS_16_         , 0,
22159        0x0                 },        /* LWXS[16] */
22160 };
22161
22162
22163 NMD::Pool NMD::P16_A1[2] = {
22164     { reserved_block      , 0                   , 0   , 16,
22165        0xfc40    , 0x7000    , 0                      , 0,
22166        0x0                 },        /* P16.A1~*(0) */
22167     { instruction         , 0                   , 0   , 16,
22168        0xfc40    , 0x7040    , &NMD::ADDIU_R1_SP_     , 0,
22169        0x0                 },        /* ADDIU[R1.SP] */
22170 };
22171
22172
22173 NMD::Pool NMD::P_ADDIU_RS5_[2] = {
22174     { instruction         , 0                   , 0   , 16,
22175        0xffe8    , 0x9008    , &NMD::NOP_16_          , 0,
22176        0x0                 },        /* NOP[16] */
22177     { instruction         , 0                   , 0   , 16,
22178        0xfc08    , 0x9008    , &NMD::ADDIU_RS5_       , &NMD::ADDIU_RS5__cond  ,
22179        0x0                 },        /* ADDIU[RS5] */
22180 };
22181
22182
22183 NMD::Pool NMD::P16_A2[2] = {
22184     { instruction         , 0                   , 0   , 16,
22185        0xfc08    , 0x9000    , &NMD::ADDIU_R2_        , 0,
22186        0x0                 },        /* ADDIU[R2] */
22187     { pool                , P_ADDIU_RS5_        , 2   , 16,
22188        0xfc08    , 0x9008    , 0                      , 0,
22189        0x0                 },        /* P.ADDIU[RS5] */
22190 };
22191
22192
22193 NMD::Pool NMD::P16_ADDU[2] = {
22194     { instruction         , 0                   , 0   , 16,
22195        0xfc01    , 0xb000    , &NMD::ADDU_16_         , 0,
22196        0x0                 },        /* ADDU[16] */
22197     { instruction         , 0                   , 0   , 16,
22198        0xfc01    , 0xb001    , &NMD::SUBU_16_         , 0,
22199        0x0                 },        /* SUBU[16] */
22200 };
22201
22202
22203 NMD::Pool NMD::P16_JRC[2] = {
22204     { branch_instruction  , 0                   , 0   , 16,
22205        0xfc1f    , 0xd800    , &NMD::JRC              , 0,
22206        0x0                 },        /* JRC */
22207     { call_instruction    , 0                   , 0   , 16,
22208        0xfc1f    , 0xd810    , &NMD::JALRC_16_        , 0,
22209        0x0                 },        /* JALRC[16] */
22210 };
22211
22212
22213 NMD::Pool NMD::P16_BR1[2] = {
22214     { branch_instruction  , 0                   , 0   , 16,
22215        0xfc00    , 0xd800    , &NMD::BEQC_16_         , &NMD::BEQC_16__cond    ,
22216        XMMS_               },        /* BEQC[16] */
22217     { branch_instruction  , 0                   , 0   , 16,
22218        0xfc00    , 0xd800    , &NMD::BNEC_16_         , &NMD::BNEC_16__cond    ,
22219        XMMS_               },        /* BNEC[16] */
22220 };
22221
22222
22223 NMD::Pool NMD::P16_BR[2] = {
22224     { pool                , P16_JRC             , 2   , 16,
22225        0xfc0f    , 0xd800    , 0                      , 0,
22226        0x0                 },        /* P16.JRC */
22227     { pool                , P16_BR1             , 2   , 16,
22228        0xfc00    , 0xd800    , 0                      , &NMD::P16_BR1_cond     ,
22229        0x0                 },        /* P16.BR1 */
22230 };
22231
22232
22233 NMD::Pool NMD::P16_SR[2] = {
22234     { instruction         , 0                   , 0   , 16,
22235        0xfd00    , 0x1c00    , &NMD::SAVE_16_         , 0,
22236        0x0                 },        /* SAVE[16] */
22237     { return_instruction  , 0                   , 0   , 16,
22238        0xfd00    , 0x1d00    , &NMD::RESTORE_JRC_16_  , 0,
22239        0x0                 },        /* RESTORE.JRC[16] */
22240 };
22241
22242
22243 NMD::Pool NMD::P16_4X4[4] = {
22244     { instruction         , 0                   , 0   , 16,
22245        0xfd08    , 0x3c00    , &NMD::ADDU_4X4_        , 0,
22246        XMMS_               },        /* ADDU[4X4] */
22247     { instruction         , 0                   , 0   , 16,
22248        0xfd08    , 0x3c08    , &NMD::MUL_4X4_         , 0,
22249        XMMS_               },        /* MUL[4X4] */
22250     { reserved_block      , 0                   , 0   , 16,
22251        0xfd08    , 0x3d00    , 0                      , 0,
22252        0x0                 },        /* P16.4X4~*(2) */
22253     { reserved_block      , 0                   , 0   , 16,
22254        0xfd08    , 0x3d08    , 0                      , 0,
22255        0x0                 },        /* P16.4X4~*(3) */
22256 };
22257
22258
22259 NMD::Pool NMD::P16_LB[4] = {
22260     { instruction         , 0                   , 0   , 16,
22261        0xfc0c    , 0x5c00    , &NMD::LB_16_           , 0,
22262        0x0                 },        /* LB[16] */
22263     { instruction         , 0                   , 0   , 16,
22264        0xfc0c    , 0x5c04    , &NMD::SB_16_           , 0,
22265        0x0                 },        /* SB[16] */
22266     { instruction         , 0                   , 0   , 16,
22267        0xfc0c    , 0x5c08    , &NMD::LBU_16_          , 0,
22268        0x0                 },        /* LBU[16] */
22269     { reserved_block      , 0                   , 0   , 16,
22270        0xfc0c    , 0x5c0c    , 0                      , 0,
22271        0x0                 },        /* P16.LB~*(3) */
22272 };
22273
22274
22275 NMD::Pool NMD::P16_LH[4] = {
22276     { instruction         , 0                   , 0   , 16,
22277        0xfc09    , 0x7c00    , &NMD::LH_16_           , 0,
22278        0x0                 },        /* LH[16] */
22279     { instruction         , 0                   , 0   , 16,
22280        0xfc09    , 0x7c01    , &NMD::SH_16_           , 0,
22281        0x0                 },        /* SH[16] */
22282     { instruction         , 0                   , 0   , 16,
22283        0xfc09    , 0x7c08    , &NMD::LHU_16_          , 0,
22284        0x0                 },        /* LHU[16] */
22285     { reserved_block      , 0                   , 0   , 16,
22286        0xfc09    , 0x7c09    , 0                      , 0,
22287        0x0                 },        /* P16.LH~*(3) */
22288 };
22289
22290
22291 NMD::Pool NMD::P16[32] = {
22292     { pool                , P16_MV              , 2   , 16,
22293        0xfc00    , 0x1000    , 0                      , 0,
22294        0x0                 },        /* P16.MV */
22295     { pool                , P16_SHIFT           , 2   , 16,
22296        0xfc00    , 0x3000    , 0                      , 0,
22297        0x0                 },        /* P16.SHIFT */
22298     { pool                , P16C                , 2   , 16,
22299        0xfc00    , 0x5000    , 0                      , 0,
22300        0x0                 },        /* P16C */
22301     { pool                , P16_A1              , 2   , 16,
22302        0xfc00    , 0x7000    , 0                      , 0,
22303        0x0                 },        /* P16.A1 */
22304     { pool                , P16_A2              , 2   , 16,
22305        0xfc00    , 0x9000    , 0                      , 0,
22306        0x0                 },        /* P16.A2 */
22307     { pool                , P16_ADDU            , 2   , 16,
22308        0xfc00    , 0xb000    , 0                      , 0,
22309        0x0                 },        /* P16.ADDU */
22310     { instruction         , 0                   , 0   , 16,
22311        0xfc00    , 0xd000    , &NMD::LI_16_           , 0,
22312        0x0                 },        /* LI[16] */
22313     { instruction         , 0                   , 0   , 16,
22314        0xfc00    , 0xf000    , &NMD::ANDI_16_         , 0,
22315        0x0                 },        /* ANDI[16] */
22316     { instruction         , 0                   , 0   , 16,
22317        0xfc00    , 0x1400    , &NMD::LW_16_           , 0,
22318        0x0                 },        /* LW[16] */
22319     { instruction         , 0                   , 0   , 16,
22320        0xfc00    , 0x3400    , &NMD::LW_SP_           , 0,
22321        0x0                 },        /* LW[SP] */
22322     { instruction         , 0                   , 0   , 16,
22323        0xfc00    , 0x5400    , &NMD::LW_GP16_         , 0,
22324        0x0                 },        /* LW[GP16] */
22325     { instruction         , 0                   , 0   , 16,
22326        0xfc00    , 0x7400    , &NMD::LW_4X4_          , 0,
22327        XMMS_               },        /* LW[4X4] */
22328     { instruction         , 0                   , 0   , 16,
22329        0xfc00    , 0x9400    , &NMD::SW_16_           , 0,
22330        0x0                 },        /* SW[16] */
22331     { instruction         , 0                   , 0   , 16,
22332        0xfc00    , 0xb400    , &NMD::SW_SP_           , 0,
22333        0x0                 },        /* SW[SP] */
22334     { instruction         , 0                   , 0   , 16,
22335        0xfc00    , 0xd400    , &NMD::SW_GP16_         , 0,
22336        0x0                 },        /* SW[GP16] */
22337     { instruction         , 0                   , 0   , 16,
22338        0xfc00    , 0xf400    , &NMD::SW_4X4_          , 0,
22339        XMMS_               },        /* SW[4X4] */
22340     { branch_instruction  , 0                   , 0   , 16,
22341        0xfc00    , 0x1800    , &NMD::BC_16_           , 0,
22342        0x0                 },        /* BC[16] */
22343     { call_instruction    , 0                   , 0   , 16,
22344        0xfc00    , 0x3800    , &NMD::BALC_16_         , 0,
22345        0x0                 },        /* BALC[16] */
22346     { reserved_block      , 0                   , 0   , 16,
22347        0xfc00    , 0x5800    , 0                      , 0,
22348        0x0                 },        /* P16~*(10) */
22349     { reserved_block      , 0                   , 0   , 16,
22350        0xfc00    , 0x7800    , 0                      , 0,
22351        0x0                 },        /* P16~*(14) */
22352     { branch_instruction  , 0                   , 0   , 16,
22353        0xfc00    , 0x9800    , &NMD::BEQZC_16_        , 0,
22354        0x0                 },        /* BEQZC[16] */
22355     { branch_instruction  , 0                   , 0   , 16,
22356        0xfc00    , 0xb800    , &NMD::BNEZC_16_        , 0,
22357        0x0                 },        /* BNEZC[16] */
22358     { pool                , P16_BR              , 2   , 16,
22359        0xfc00    , 0xd800    , 0                      , 0,
22360        0x0                 },        /* P16.BR */
22361     { reserved_block      , 0                   , 0   , 16,
22362        0xfc00    , 0xf800    , 0                      , 0,
22363        0x0                 },        /* P16~*(30) */
22364     { pool                , P16_SR              , 2   , 16,
22365        0xfc00    , 0x1c00    , 0                      , 0,
22366        0x0                 },        /* P16.SR */
22367     { pool                , P16_4X4             , 4   , 16,
22368        0xfc00    , 0x3c00    , 0                      , 0,
22369        0x0                 },        /* P16.4X4 */
22370     { pool                , P16_LB              , 4   , 16,
22371        0xfc00    , 0x5c00    , 0                      , 0,
22372        0x0                 },        /* P16.LB */
22373     { pool                , P16_LH              , 4   , 16,
22374        0xfc00    , 0x7c00    , 0                      , 0,
22375        0x0                 },        /* P16.LH */
22376     { reserved_block      , 0                   , 0   , 16,
22377        0xfc00    , 0x9c00    , 0                      , 0,
22378        0x0                 },        /* P16~*(19) */
22379     { instruction         , 0                   , 0   , 16,
22380        0xfc00    , 0xbc00    , &NMD::MOVEP            , 0,
22381        XMMS_               },        /* MOVEP */
22382     { reserved_block      , 0                   , 0   , 16,
22383        0xfc00    , 0xdc00    , 0                      , 0,
22384        0x0                 },        /* P16~*(27) */
22385     { instruction         , 0                   , 0   , 16,
22386        0xfc00    , 0xfc00    , &NMD::MOVEP_REV_       , 0,
22387        XMMS_               },        /* MOVEP[REV] */
22388 };
22389
22390
22391 NMD::Pool NMD::MAJOR[2] = {
22392     { pool                , P32                 , 32  , 32,
22393        0x10000000, 0x00000000, 0                      , 0,
22394        0x0                 },        /* P32 */
22395     { pool                , P16                 , 32  , 16,
22396        0x1000    , 0x1000    , 0                      , 0,
22397        0x0                 },        /* P16 */
22398 };