hw/loongarch/loongson3.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * QEMU loongson 3a5000 develop board emulation
   4  *
   5  * Copyright (c) 2021 Loongson Technology Corporation Limited
   6  */
   7 #include "qemu/osdep.h"
   8 #include "qemu/units.h"
   9 #include "qemu/datadir.h"
  10 #include "qapi/error.h"
  11 #include "hw/boards.h"
  12 #include "hw/char/serial.h"
  13 #include "sysemu/sysemu.h"
  14 #include "sysemu/qtest.h"
  15 #include "sysemu/runstate.h"
  16 #include "sysemu/reset.h"
  17 #include "sysemu/rtc.h"
  18 #include "hw/loongarch/virt.h"
  19 #include "exec/address-spaces.h"
  20 #include "hw/irq.h"
  21 #include "net/net.h"
  22 #include "hw/loader.h"
  23 #include "elf.h"
  24 #include "hw/intc/loongarch_ipi.h"
  25 #include "hw/intc/loongarch_extioi.h"
  26 #include "hw/intc/loongarch_pch_pic.h"
  27 #include "hw/intc/loongarch_pch_msi.h"
  28 #include "hw/pci-host/ls7a.h"
  29 #include "hw/pci-host/gpex.h"
  30 #include "hw/misc/unimp.h"
  31 #include "hw/loongarch/fw_cfg.h"
  32 #include "target/loongarch/cpu.h"
  33 #include "hw/firmware/smbios.h"
  34 #include "hw/acpi/aml-build.h"
  35 #include "qapi/qapi-visit-common.h"
  36 #include "hw/acpi/generic_event_device.h"
  37 #include "hw/mem/nvdimm.h"
  38
  39 #define PM_BASE 0x10080000
  40 #define PM_SIZE 0x100
  41 #define PM_CTRL 0x10
  42
  43 static void virt_build_smbios(LoongArchMachineState *lams)
  44 {
  45     MachineState *ms = MACHINE(lams);
  46     MachineClass *mc = MACHINE_GET_CLASS(lams);
  47     uint8_t *smbios_tables, *smbios_anchor;
  48     size_t smbios_tables_len, smbios_anchor_len;
  49     const char *product = "QEMU Virtual Machine";
  50
  51     if (!lams->fw_cfg) {
  52         return;
  53     }
  54
  55     smbios_set_defaults("QEMU", product, mc->name, false,
  56                         true, SMBIOS_ENTRY_POINT_TYPE_64);
  57
  58     smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len,
  59                       &smbios_anchor, &smbios_anchor_len, &error_fatal);
  60
  61     if (smbios_anchor) {
  62         fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables",
  63                         smbios_tables, smbios_tables_len);
  64         fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor",
  65                         smbios_anchor, smbios_anchor_len);
  66     }
  67 }
  68
  69 static void virt_machine_done(Notifier *notifier, void *data)
  70 {
  71     LoongArchMachineState *lams = container_of(notifier,
  72                                         LoongArchMachineState, machine_done);
  73     virt_build_smbios(lams);
  74     loongarch_acpi_setup(lams);
  75 }
  76
  77 struct memmap_entry {
  78     uint64_t address;
  79     uint64_t length;
  80     uint32_t type;
  81     uint32_t reserved;
  82 };
  83
  84 static struct memmap_entry *memmap_table;
  85 static unsigned memmap_entries;
  86
  87 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
  88 {
  89     /* Ensure there are no duplicate entries. */
  90     for (unsigned i = 0; i < memmap_entries; i++) {
  91         assert(memmap_table[i].address != address);
  92     }
  93
  94     memmap_table = g_renew(struct memmap_entry, memmap_table,
  95                            memmap_entries + 1);
  96     memmap_table[memmap_entries].address = cpu_to_le64(address);
  97     memmap_table[memmap_entries].length = cpu_to_le64(length);
  98     memmap_table[memmap_entries].type = cpu_to_le32(type);
  99     memmap_table[memmap_entries].reserved = 0;
 100     memmap_entries++;
 101 }
 102
 103 /*
 104  * This is a placeholder for missing ACPI,
 105  * and will eventually be replaced.
 106  */
 107 static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size)
 108 {
 109     return 0;
 110 }
 111
 112 static void loongarch_virt_pm_write(void *opaque, hwaddr addr,
 113                                uint64_t val, unsigned size)
 114 {
 115     if (addr != PM_CTRL) {
 116         return;
 117     }
 118
 119     switch (val) {
 120     case 0x00:
 121         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 122         return;
 123     case 0xff:
 124         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 125         return;
 126     default:
 127         return;
 128     }
 129 }
 130
 131 static const MemoryRegionOps loongarch_virt_pm_ops = {
 132     .read  = loongarch_virt_pm_read,
 133     .write = loongarch_virt_pm_write,
 134     .endianness = DEVICE_NATIVE_ENDIAN,
 135     .valid = {
 136         .min_access_size = 1,
 137         .max_access_size = 1
 138     }
 139 };
 140
 141 static struct _loaderparams {
 142     uint64_t ram_size;
 143     const char *kernel_filename;
 144     const char *kernel_cmdline;
 145     const char *initrd_filename;
 146 } loaderparams;
 147
 148 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
 149 {
 150     return addr & 0x1fffffffll;
 151 }
 152
 153 static int64_t load_kernel_info(void)
 154 {
 155     uint64_t kernel_entry, kernel_low, kernel_high;
 156     ssize_t kernel_size;
 157
 158     kernel_size = load_elf(loaderparams.kernel_filename, NULL,
 159                            cpu_loongarch_virt_to_phys, NULL,
 160                            &kernel_entry, &kernel_low,
 161                            &kernel_high, NULL, 0,
 162                            EM_LOONGARCH, 1, 0);
 163
 164     if (kernel_size < 0) {
 165         error_report("could not load kernel '%s': %s",
 166                      loaderparams.kernel_filename,
 167                      load_elf_strerror(kernel_size));
 168         exit(1);
 169     }
 170     return kernel_entry;
 171 }
 172
 173 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams)
 174 {
 175     DeviceState *dev;
 176     MachineState *ms = MACHINE(lams);
 177     uint32_t event = ACPI_GED_PWR_DOWN_EVT;
 178
 179     if (ms->ram_slots) {
 180         event |= ACPI_GED_MEM_HOTPLUG_EVT;
 181     }
 182     dev = qdev_new(TYPE_ACPI_GED);
 183     qdev_prop_set_uint32(dev, "ged-event", event);
 184
 185     /* ged event */
 186     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR);
 187     /* memory hotplug */
 188     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR);
 189     /* ged regs used for reset and power down */
 190     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);
 191
 192     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 193                        qdev_get_gpio_in(pch_pic, LS7A_SCI_IRQ - PCH_PIC_IRQ_OFFSET));
 194     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 195     return dev;
 196 }
 197
 198 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams)
 199 {
 200     DeviceState *gpex_dev;
 201     SysBusDevice *d;
 202     PCIBus *pci_bus;
 203     MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
 204     MemoryRegion *mmio_alias, *mmio_reg, *pm_mem;
 205     int i;
 206
 207     gpex_dev = qdev_new(TYPE_GPEX_HOST);
 208     d = SYS_BUS_DEVICE(gpex_dev);
 209     sysbus_realize_and_unref(d, &error_fatal);
 210     pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
 211
 212     /* Map only part size_ecam bytes of ECAM space */
 213     ecam_alias = g_new0(MemoryRegion, 1);
 214     ecam_reg = sysbus_mmio_get_region(d, 0);
 215     memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
 216                              ecam_reg, 0, LS_PCIECFG_SIZE);
 217     memory_region_add_subregion(get_system_memory(), LS_PCIECFG_BASE,
 218                                 ecam_alias);
 219
 220     /* Map PCI mem space */
 221     mmio_alias = g_new0(MemoryRegion, 1);
 222     mmio_reg = sysbus_mmio_get_region(d, 1);
 223     memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
 224                              mmio_reg, LS7A_PCI_MEM_BASE, LS7A_PCI_MEM_SIZE);
 225     memory_region_add_subregion(get_system_memory(), LS7A_PCI_MEM_BASE,
 226                                 mmio_alias);
 227
 228     /* Map PCI IO port space. */
 229     pio_alias = g_new0(MemoryRegion, 1);
 230     pio_reg = sysbus_mmio_get_region(d, 2);
 231     memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
 232                              LS7A_PCI_IO_OFFSET, LS7A_PCI_IO_SIZE);
 233     memory_region_add_subregion(get_system_memory(), LS7A_PCI_IO_BASE,
 234                                 pio_alias);
 235
 236     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 237         sysbus_connect_irq(d, i,
 238                            qdev_get_gpio_in(pch_pic, 16 + i));
 239         gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
 240     }
 241
 242     serial_mm_init(get_system_memory(), LS7A_UART_BASE, 0,
 243                    qdev_get_gpio_in(pch_pic,
 244                                     LS7A_UART_IRQ - PCH_PIC_IRQ_OFFSET),
 245                    115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 246
 247     /* Network init */
 248     for (i = 0; i < nb_nics; i++) {
 249         NICInfo *nd = &nd_table[i];
 250
 251         if (!nd->model) {
 252             nd->model = g_strdup("virtio");
 253         }
 254
 255         pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
 256     }
 257
 258     /* VGA setup */
 259     pci_vga_init(pci_bus);
 260
 261     /*
 262      * There are some invalid guest memory access.
 263      * Create some unimplemented devices to emulate this.
 264      */
 265     create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
 266     sysbus_create_simple("ls7a_rtc", LS7A_RTC_REG_BASE,
 267                          qdev_get_gpio_in(pch_pic,
 268                          LS7A_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
 269
 270     pm_mem = g_new(MemoryRegion, 1);
 271     memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
 272                           NULL, "loongarch_virt_pm", PM_SIZE);
 273     memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem);
 274     /* acpi ged */
 275     lams->acpi_ged = create_acpi_ged(pch_pic, lams);
 276 }
 277
 278 static void loongarch_irq_init(LoongArchMachineState *lams)
 279 {
 280     MachineState *ms = MACHINE(lams);
 281     DeviceState *pch_pic, *pch_msi, *cpudev;
 282     DeviceState *ipi, *extioi;
 283     SysBusDevice *d;
 284     LoongArchCPU *lacpu;
 285     CPULoongArchState *env;
 286     CPUState *cpu_state;
 287     int cpu, pin, i;
 288
 289     ipi = qdev_new(TYPE_LOONGARCH_IPI);
 290     sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
 291
 292     extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
 293     sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
 294
 295     /*
 296      * The connection of interrupts:
 297      *   +-----+    +---------+     +-------+
 298      *   | IPI |--> | CPUINTC | <-- | Timer |
 299      *   +-----+    +---------+     +-------+
 300      *                  ^
 301      *                  |
 302      *            +---------+
 303      *            | EIOINTC |
 304      *            +---------+
 305      *             ^       ^
 306      *             |       |
 307      *      +---------+ +---------+
 308      *      | PCH-PIC | | PCH-MSI |
 309      *      +---------+ +---------+
 310      *        ^      ^          ^
 311      *        |      |          |
 312      * +--------+ +---------+ +---------+
 313      * | UARTs  | | Devices | | Devices |
 314      * +--------+ +---------+ +---------+
 315      */
 316     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 317         cpu_state = qemu_get_cpu(cpu);
 318         cpudev = DEVICE(cpu_state);
 319         lacpu = LOONGARCH_CPU(cpu_state);
 320         env = &(lacpu->env);
 321
 322         /* connect ipi irq to cpu irq */
 323         qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
 324         /* IPI iocsr memory region */
 325         memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
 326                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
 327                                     cpu * 2));
 328         memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
 329                                     sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
 330                                     cpu * 2 + 1));
 331         /* extioi iocsr memory region */
 332         memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
 333                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
 334                                 cpu));
 335     }
 336
 337     /*
 338      * connect ext irq to the cpu irq
 339      * cpu_pin[9:2] <= intc_pin[7:0]
 340      */
 341     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 342         cpudev = DEVICE(qemu_get_cpu(cpu));
 343         for (pin = 0; pin < LS3A_INTC_IP; pin++) {
 344             qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
 345                                   qdev_get_gpio_in(cpudev, pin + 2));
 346         }
 347     }
 348
 349     pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
 350     d = SYS_BUS_DEVICE(pch_pic);
 351     sysbus_realize_and_unref(d, &error_fatal);
 352     memory_region_add_subregion(get_system_memory(), LS7A_IOAPIC_REG_BASE,
 353                             sysbus_mmio_get_region(d, 0));
 354     memory_region_add_subregion(get_system_memory(),
 355                             LS7A_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
 356                             sysbus_mmio_get_region(d, 1));
 357     memory_region_add_subregion(get_system_memory(),
 358                             LS7A_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
 359                             sysbus_mmio_get_region(d, 2));
 360
 361     /* Connect 64 pch_pic irqs to extioi */
 362     for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
 363         qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
 364     }
 365
 366     pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
 367     qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
 368     d = SYS_BUS_DEVICE(pch_msi);
 369     sysbus_realize_and_unref(d, &error_fatal);
 370     sysbus_mmio_map(d, 0, LS7A_PCH_MSI_ADDR_LOW);
 371     for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
 372         /* Connect 192 pch_msi irqs to extioi */
 373         qdev_connect_gpio_out(DEVICE(d), i,
 374                               qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
 375     }
 376
 377     loongarch_devices_init(pch_pic, lams);
 378 }
 379
 380 static void loongarch_firmware_init(LoongArchMachineState *lams)
 381 {
 382     char *filename = MACHINE(lams)->firmware;
 383     char *bios_name = NULL;
 384     int bios_size;
 385
 386     lams->bios_loaded = false;
 387     if (filename) {
 388         bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename);
 389         if (!bios_name) {
 390             error_report("Could not find ROM image '%s'", filename);
 391             exit(1);
 392         }
 393
 394         bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE);
 395         if (bios_size < 0) {
 396             error_report("Could not load ROM image '%s'", bios_name);
 397             exit(1);
 398         }
 399
 400         g_free(bios_name);
 401
 402         memory_region_init_ram(&lams->bios, NULL, "loongarch.bios",
 403                                VIRT_BIOS_SIZE, &error_fatal);
 404         memory_region_set_readonly(&lams->bios, true);
 405         memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios);
 406         lams->bios_loaded = true;
 407     }
 408
 409 }
 410
 411 static void reset_load_elf(void *opaque)
 412 {
 413     LoongArchCPU *cpu = opaque;
 414     CPULoongArchState *env = &cpu->env;
 415
 416     cpu_reset(CPU(cpu));
 417     if (env->load_elf) {
 418         cpu_set_pc(CPU(cpu), env->elf_address);
 419     }
 420 }
 421
 422 /* Load an image file into an fw_cfg entry identified by key. */
 423 static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
 424                                  uint16_t data_key, const char *image_name,
 425                                  bool try_decompress)
 426 {
 427     size_t size = -1;
 428     uint8_t *data;
 429
 430     if (image_name == NULL) {
 431         return;
 432     }
 433
 434     if (try_decompress) {
 435         size = load_image_gzipped_buffer(image_name,
 436                                          LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
 437     }
 438
 439     if (size == (size_t)-1) {
 440         gchar *contents;
 441         gsize length;
 442
 443         if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
 444             error_report("failed to load \"%s\"", image_name);
 445             exit(1);
 446         }
 447         size = length;
 448         data = (uint8_t *)contents;
 449     }
 450
 451     fw_cfg_add_i32(fw_cfg, size_key, size);
 452     fw_cfg_add_bytes(fw_cfg, data_key, data, size);
 453 }
 454
 455 static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg)
 456 {
 457     /*
 458      * Expose the kernel, the command line, and the initrd in fw_cfg.
 459      * We don't process them here at all, it's all left to the
 460      * firmware.
 461      */
 462     load_image_to_fw_cfg(fw_cfg,
 463                          FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
 464                          loaderparams.kernel_filename,
 465                          false);
 466
 467     if (loaderparams.initrd_filename) {
 468         load_image_to_fw_cfg(fw_cfg,
 469                              FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
 470                              loaderparams.initrd_filename, false);
 471     }
 472
 473     if (loaderparams.kernel_cmdline) {
 474         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 475                        strlen(loaderparams.kernel_cmdline) + 1);
 476         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 477                           loaderparams.kernel_cmdline);
 478     }
 479 }
 480
 481 static void loongarch_firmware_boot(LoongArchMachineState *lams)
 482 {
 483     fw_cfg_add_kernel_info(lams->fw_cfg);
 484 }
 485
 486 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams)
 487 {
 488     MachineState *machine = MACHINE(lams);
 489     int64_t kernel_addr = 0;
 490     LoongArchCPU *lacpu;
 491     int i;
 492
 493     kernel_addr = load_kernel_info();
 494     if (!machine->firmware) {
 495         for (i = 0; i < machine->smp.cpus; i++) {
 496             lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
 497             lacpu->env.load_elf = true;
 498             lacpu->env.elf_address = kernel_addr;
 499         }
 500     }
 501 }
 502
 503 static void loongarch_init(MachineState *machine)
 504 {
 505     LoongArchCPU *lacpu;
 506     const char *cpu_model = machine->cpu_type;
 507     ram_addr_t offset = 0;
 508     ram_addr_t ram_size = machine->ram_size;
 509     uint64_t highram_size = 0;
 510     MemoryRegion *address_space_mem = get_system_memory();
 511     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
 512     int i;
 513
 514     if (!cpu_model) {
 515         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
 516     }
 517
 518     if (!strstr(cpu_model, "la464")) {
 519         error_report("LoongArch/TCG needs cpu type la464");
 520         exit(1);
 521     }
 522
 523     if (ram_size < 1 * GiB) {
 524         error_report("ram_size must be greater than 1G.");
 525         exit(1);
 526     }
 527
 528     /* Init CPUs */
 529     for (i = 0; i < machine->smp.cpus; i++) {
 530         cpu_create(machine->cpu_type);
 531     }
 532
 533     /* Add memory region */
 534     memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
 535                              machine->ram, 0, 256 * MiB);
 536     memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
 537     offset += 256 * MiB;
 538     memmap_add_entry(0, 256 * MiB, 1);
 539     highram_size = ram_size - 256 * MiB;
 540     memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
 541                              machine->ram, offset, highram_size);
 542     memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
 543     memmap_add_entry(0x90000000, highram_size, 1);
 544     /* Add isa io region */
 545     memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
 546                              get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
 547     memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE,
 548                                 &lams->isa_io);
 549     /* load the BIOS image. */
 550     loongarch_firmware_init(lams);
 551
 552     /* fw_cfg init */
 553     lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine);
 554     rom_set_fw(lams->fw_cfg);
 555
 556     if (lams->fw_cfg != NULL) {
 557         fw_cfg_add_file(lams->fw_cfg, "etc/memmap",
 558                         memmap_table,
 559                         sizeof(struct memmap_entry) * (memmap_entries));
 560     }
 561     loaderparams.ram_size = ram_size;
 562     loaderparams.kernel_filename = machine->kernel_filename;
 563     loaderparams.kernel_cmdline = machine->kernel_cmdline;
 564     loaderparams.initrd_filename = machine->initrd_filename;
 565     /* load the kernel. */
 566     if (loaderparams.kernel_filename) {
 567         if (lams->bios_loaded) {
 568             loongarch_firmware_boot(lams);
 569         } else {
 570             loongarch_direct_kernel_boot(lams);
 571         }
 572     }
 573     /* register reset function */
 574     for (i = 0; i < machine->smp.cpus; i++) {
 575         lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
 576         qemu_register_reset(reset_load_elf, lacpu);
 577     }
 578     /* Initialize the IO interrupt subsystem */
 579     loongarch_irq_init(lams);
 580     lams->machine_done.notify = virt_machine_done;
 581     qemu_add_machine_init_done_notifier(&lams->machine_done);
 582 }
 583
 584 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
 585 {
 586     if (lams->acpi == ON_OFF_AUTO_OFF) {
 587         return false;
 588     }
 589     return true;
 590 }
 591
 592 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name,
 593                                void *opaque, Error **errp)
 594 {
 595     LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
 596     OnOffAuto acpi = lams->acpi;
 597
 598     visit_type_OnOffAuto(v, name, &acpi, errp);
 599 }
 600
 601 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name,
 602                                void *opaque, Error **errp)
 603 {
 604     LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
 605
 606     visit_type_OnOffAuto(v, name, &lams->acpi, errp);
 607 }
 608
 609 static void loongarch_machine_initfn(Object *obj)
 610 {
 611     LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
 612
 613     lams->acpi = ON_OFF_AUTO_AUTO;
 614     lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
 615     lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
 616 }
 617
 618 static void loongarch_class_init(ObjectClass *oc, void *data)
 619 {
 620     MachineClass *mc = MACHINE_CLASS(oc);
 621
 622     mc->desc = "Loongson-3A5000 LS7A1000 machine";
 623     mc->init = loongarch_init;
 624     mc->default_ram_size = 1 * GiB;
 625     mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
 626     mc->default_ram_id = "loongarch.ram";
 627     mc->max_cpus = LOONGARCH_MAX_VCPUS;
 628     mc->is_default = 1;
 629     mc->default_kernel_irqchip_split = false;
 630     mc->block_default_type = IF_VIRTIO;
 631     mc->default_boot_order = "c";
 632     mc->no_cdrom = 1;
 633
 634     object_class_property_add(oc, "acpi", "OnOffAuto",
 635         loongarch_get_acpi, loongarch_set_acpi,
 636         NULL, NULL);
 637     object_class_property_set_description(oc, "acpi",
 638         "Enable ACPI");
 639 }
 640
 641 static const TypeInfo loongarch_machine_types[] = {
 642     {
 643         .name           = TYPE_LOONGARCH_MACHINE,
 644         .parent         = TYPE_MACHINE,
 645         .instance_size  = sizeof(LoongArchMachineState),
 646         .class_init     = loongarch_class_init,
 647         .instance_init = loongarch_machine_initfn,
 648     }
 649 };
 650
 651 DEFINE_TYPES(loongarch_machine_types)