tests/ahci-test.c

   1 /*
   2  * AHCI test cases
   3  *
   4  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <stdio.h>
  28 #include <getopt.h>
  29 #include <glib.h>
  30
  31 #include "libqtest.h"
  32 #include "libqos/libqos-pc.h"
  33 #include "libqos/ahci.h"
  34 #include "libqos/pci-pc.h"
  35
  36 #include "qemu-common.h"
  37 #include "qemu/host-utils.h"
  38
  39 #include "hw/pci/pci_ids.h"
  40 #include "hw/pci/pci_regs.h"
  41
  42 /* Test-specific defines -- in MiB */
  43 #define TEST_IMAGE_SIZE_MB (200 * 1024)
  44 #define TEST_IMAGE_SECTORS ((TEST_IMAGE_SIZE_MB / AHCI_SECTOR_SIZE)     \
  45                             * 1024 * 1024)
  46
  47 /*** Globals ***/
  48 static char tmp_path[] = "/tmp/qtest.XXXXXX";
  49 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
  50 static bool ahci_pedantic;
  51
  52 /*** Function Declarations ***/
  53 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
  54 static void ahci_test_pci_spec(AHCIQState *ahci);
  55 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
  56                                uint8_t offset);
  57 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
  58 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
  59 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
  60
  61 /*** Utilities ***/
  62
  63 static void string_bswap16(uint16_t *s, size_t bytes)
  64 {
  65     g_assert_cmphex((bytes & 1), ==, 0);
  66     bytes /= 2;
  67
  68     while (bytes--) {
  69         *s = bswap16(*s);
  70         s++;
  71     }
  72 }
  73
  74 static void generate_pattern(void *buffer, size_t len, size_t cycle_len)
  75 {
  76     int i, j;
  77     unsigned char *tx = (unsigned char *)buffer;
  78     unsigned char p;
  79     size_t *sx;
  80
  81     /* Write an indicative pattern that varies and is unique per-cycle */
  82     p = rand() % 256;
  83     for (i = j = 0; i < len; i++, j++) {
  84         tx[i] = p;
  85         if (j % cycle_len == 0) {
  86             p = rand() % 256;
  87         }
  88     }
  89
  90     /* force uniqueness by writing an id per-cycle */
  91     for (i = 0; i < len / cycle_len; i++) {
  92         j = i * cycle_len;
  93         if (j + sizeof(*sx) <= len) {
  94             sx = (size_t *)&tx[j];
  95             *sx = i;
  96         }
  97     }
  98 }
  99
 100 /*** Test Setup & Teardown ***/
 101
 102 /**
 103  * Start a Q35 machine and bookmark a handle to the AHCI device.
 104  */
 105 static AHCIQState *ahci_vboot(const char *cli, va_list ap)
 106 {
 107     AHCIQState *s;
 108
 109     s = g_malloc0(sizeof(AHCIQState));
 110     s->parent = qtest_pc_vboot(cli, ap);
 111     alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
 112
 113     /* Verify that we have an AHCI device present. */
 114     s->dev = get_ahci_device(&s->fingerprint);
 115
 116     return s;
 117 }
 118
 119 /**
 120  * Start a Q35 machine and bookmark a handle to the AHCI device.
 121  */
 122 static AHCIQState *ahci_boot(const char *cli, ...)
 123 {
 124     AHCIQState *s;
 125     va_list ap;
 126
 127     if (cli) {
 128         va_start(ap, cli);
 129         s = ahci_vboot(cli, ap);
 130         va_end(ap);
 131     } else {
 132         cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
 133             ",format=qcow2"
 134             " -M q35 "
 135             "-device ide-hd,drive=drive0 "
 136             "-global ide-hd.ver=%s";
 137         s = ahci_boot(cli, tmp_path, "testdisk", "version");
 138     }
 139
 140     return s;
 141 }
 142
 143 /**
 144  * Clean up the PCI device, then terminate the QEMU instance.
 145  */
 146 static void ahci_shutdown(AHCIQState *ahci)
 147 {
 148     QOSState *qs = ahci->parent;
 149     ahci_clean_mem(ahci);
 150     free_ahci_device(ahci->dev);
 151     g_free(ahci);
 152     qtest_shutdown(qs);
 153 }
 154
 155 /**
 156  * Boot and fully enable the HBA device.
 157  * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
 158  */
 159 static AHCIQState *ahci_boot_and_enable(const char *cli, ...)
 160 {
 161     AHCIQState *ahci;
 162     va_list ap;
 163
 164     if (cli) {
 165         va_start(ap, cli);
 166         ahci = ahci_vboot(cli, ap);
 167         va_end(ap);
 168     } else {
 169         ahci = ahci_boot(NULL);
 170     }
 171
 172     ahci_pci_enable(ahci);
 173     ahci_hba_enable(ahci);
 174
 175     return ahci;
 176 }
 177
 178 /*** Specification Adherence Tests ***/
 179
 180 /**
 181  * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
 182  */
 183 static void ahci_test_pci_spec(AHCIQState *ahci)
 184 {
 185     uint8_t datab;
 186     uint16_t data;
 187     uint32_t datal;
 188
 189     /* Most of these bits should start cleared until we turn them on. */
 190     data = qpci_config_readw(ahci->dev, PCI_COMMAND);
 191     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
 192     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
 193     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);     /* Reserved */
 194     ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
 195     ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
 196     ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);        /* Reserved */
 197     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
 198     ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
 199     ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
 200     ASSERT_BIT_CLEAR(data, 0xF800);                  /* Reserved */
 201
 202     data = qpci_config_readw(ahci->dev, PCI_STATUS);
 203     ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);     /* Reserved */
 204     ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
 205     ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);      /* must be set */
 206     ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);         /* Reserved */
 207     ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
 208     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
 209     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
 210     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
 211     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
 212     ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
 213
 214     /* RID occupies the low byte, CCs occupy the high three. */
 215     datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
 216     if (ahci_pedantic) {
 217         /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
 218          * Though in practice this is likely seldom true. */
 219         ASSERT_BIT_CLEAR(datal, 0xFF);
 220     }
 221
 222     /* BCC *must* equal 0x01. */
 223     g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
 224     if (PCI_SCC(datal) == 0x01) {
 225         /* IDE */
 226         ASSERT_BIT_SET(0x80000000, datal);
 227         ASSERT_BIT_CLEAR(0x60000000, datal);
 228     } else if (PCI_SCC(datal) == 0x04) {
 229         /* RAID */
 230         g_assert_cmphex(PCI_PI(datal), ==, 0);
 231     } else if (PCI_SCC(datal) == 0x06) {
 232         /* AHCI */
 233         g_assert_cmphex(PCI_PI(datal), ==, 0x01);
 234     } else {
 235         g_assert_not_reached();
 236     }
 237
 238     datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
 239     g_assert_cmphex(datab, ==, 0);
 240
 241     datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
 242     g_assert_cmphex(datab, ==, 0);
 243
 244     /* Only the bottom 7 bits must be off. */
 245     datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
 246     ASSERT_BIT_CLEAR(datab, 0x7F);
 247
 248     /* BIST is optional, but the low 7 bits must always start off regardless. */
 249     datab = qpci_config_readb(ahci->dev, PCI_BIST);
 250     ASSERT_BIT_CLEAR(datab, 0x7F);
 251
 252     /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
 253     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 254     g_assert_cmphex(datal, ==, 0);
 255
 256     qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
 257     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 258     /* ABAR must be 32-bit, memory mapped, non-prefetchable and
 259      * must be >= 512 bytes. To that end, bits 0-8 must be off. */
 260     ASSERT_BIT_CLEAR(datal, 0xFF);
 261
 262     /* Capability list MUST be present, */
 263     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
 264     /* But these bits are reserved. */
 265     ASSERT_BIT_CLEAR(datal, ~0xFF);
 266     g_assert_cmphex(datal, !=, 0);
 267
 268     /* Check specification adherence for capability extenstions. */
 269     data = qpci_config_readw(ahci->dev, datal);
 270
 271     switch (ahci->fingerprint) {
 272     case AHCI_INTEL_ICH9:
 273         /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
 274         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
 275         break;
 276     default:
 277         /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
 278         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
 279     }
 280
 281     ahci_test_pci_caps(ahci, data, (uint8_t)datal);
 282
 283     /* Reserved. */
 284     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
 285     g_assert_cmphex(datal, ==, 0);
 286
 287     /* IPIN might vary, but ILINE must be off. */
 288     datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
 289     g_assert_cmphex(datab, ==, 0);
 290 }
 291
 292 /**
 293  * Test PCI capabilities for AHCI specification adherence.
 294  */
 295 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
 296                                uint8_t offset)
 297 {
 298     uint8_t cid = header & 0xFF;
 299     uint8_t next = header >> 8;
 300
 301     g_test_message("CID: %02x; next: %02x", cid, next);
 302
 303     switch (cid) {
 304     case PCI_CAP_ID_PM:
 305         ahci_test_pmcap(ahci, offset);
 306         break;
 307     case PCI_CAP_ID_MSI:
 308         ahci_test_msicap(ahci, offset);
 309         break;
 310     case PCI_CAP_ID_SATA:
 311         ahci_test_satacap(ahci, offset);
 312         break;
 313
 314     default:
 315         g_test_message("Unknown CAP 0x%02x", cid);
 316     }
 317
 318     if (next) {
 319         ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
 320     }
 321 }
 322
 323 /**
 324  * Test SATA PCI capabilitity for AHCI specification adherence.
 325  */
 326 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
 327 {
 328     uint16_t dataw;
 329     uint32_t datal;
 330
 331     g_test_message("Verifying SATACAP");
 332
 333     /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
 334     dataw = qpci_config_readw(ahci->dev, offset + 2);
 335     g_assert_cmphex(dataw, ==, 0x10);
 336
 337     /* Grab the SATACR1 register. */
 338     datal = qpci_config_readw(ahci->dev, offset + 4);
 339
 340     switch (datal & 0x0F) {
 341     case 0x04: /* BAR0 */
 342     case 0x05: /* BAR1 */
 343     case 0x06:
 344     case 0x07:
 345     case 0x08:
 346     case 0x09: /* BAR5 */
 347     case 0x0F: /* Immediately following SATACR1 in PCI config space. */
 348         break;
 349     default:
 350         /* Invalid BARLOC for the Index Data Pair. */
 351         g_assert_not_reached();
 352     }
 353
 354     /* Reserved. */
 355     g_assert_cmphex((datal >> 24), ==, 0x00);
 356 }
 357
 358 /**
 359  * Test MSI PCI capability for AHCI specification adherence.
 360  */
 361 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
 362 {
 363     uint16_t dataw;
 364     uint32_t datal;
 365
 366     g_test_message("Verifying MSICAP");
 367
 368     dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
 369     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
 370     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
 371     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
 372
 373     datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
 374     g_assert_cmphex(datal, ==, 0);
 375
 376     if (dataw & PCI_MSI_FLAGS_64BIT) {
 377         g_test_message("MSICAP is 64bit");
 378         datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
 379         g_assert_cmphex(datal, ==, 0);
 380         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
 381         g_assert_cmphex(dataw, ==, 0);
 382     } else {
 383         g_test_message("MSICAP is 32bit");
 384         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
 385         g_assert_cmphex(dataw, ==, 0);
 386     }
 387 }
 388
 389 /**
 390  * Test Power Management PCI capability for AHCI specification adherence.
 391  */
 392 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
 393 {
 394     uint16_t dataw;
 395
 396     g_test_message("Verifying PMCAP");
 397
 398     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
 399     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
 400     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
 401     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
 402     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
 403
 404     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
 405     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
 406     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
 407     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
 408     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
 409 }
 410
 411 static void ahci_test_hba_spec(AHCIQState *ahci)
 412 {
 413     unsigned i;
 414     uint32_t reg;
 415     uint32_t ports;
 416     uint8_t nports_impl;
 417     uint8_t maxports;
 418
 419     g_assert(ahci != NULL);
 420
 421     /*
 422      * Note that the AHCI spec does expect the BIOS to set up a few things:
 423      * CAP.SSS    - Support for staggered spin-up            (t/f)
 424      * CAP.SMPS   - Support for mechanical presence switches (t/f)
 425      * PI         - Ports Implemented                        (1-32)
 426      * PxCMD.HPCP - Hot Plug Capable Port
 427      * PxCMD.MPSP - Mechanical Presence Switch Present
 428      * PxCMD.CPD  - Cold Presence Detection support
 429      *
 430      * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
 431      * Foreach Port Implemented:
 432      * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
 433      * -PxCLB/U and PxFB/U are set to valid regions in memory
 434      * -PxSUD is set to 1.
 435      * -PxSSTS.DET is polled for presence; if detected, we continue:
 436      * -PxSERR is cleared with 1's.
 437      * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
 438      *  the device is ready.
 439      */
 440
 441     /* 1 CAP - Capabilities Register */
 442     ahci->cap = ahci_rreg(ahci, AHCI_CAP);
 443     ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
 444
 445     /* 2 GHC - Global Host Control */
 446     reg = ahci_rreg(ahci, AHCI_GHC);
 447     ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
 448     ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
 449     ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
 450     if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
 451         g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
 452         ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 453     } else {
 454         g_test_message("Supports AHCI/Legacy mix.");
 455         ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
 456     }
 457
 458     /* 3 IS - Interrupt Status */
 459     reg = ahci_rreg(ahci, AHCI_IS);
 460     g_assert_cmphex(reg, ==, 0);
 461
 462     /* 4 PI - Ports Implemented */
 463     ports = ahci_rreg(ahci, AHCI_PI);
 464     /* Ports Implemented must be non-zero. */
 465     g_assert_cmphex(ports, !=, 0);
 466     /* Ports Implemented must be <= Number of Ports. */
 467     nports_impl = ctpopl(ports);
 468     g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
 469
 470     /* Ports must be within the proper range. Given a mapping of SIZE,
 471      * 256 bytes are used for global HBA control, and the rest is used
 472      * for ports data, at 0x80 bytes each. */
 473     g_assert_cmphex(ahci->barsize, >, 0);
 474     maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
 475     /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
 476     g_assert_cmphex((reg >> maxports), ==, 0);
 477
 478     /* 5 AHCI Version */
 479     reg = ahci_rreg(ahci, AHCI_VS);
 480     switch (reg) {
 481     case AHCI_VERSION_0_95:
 482     case AHCI_VERSION_1_0:
 483     case AHCI_VERSION_1_1:
 484     case AHCI_VERSION_1_2:
 485     case AHCI_VERSION_1_3:
 486         break;
 487     default:
 488         g_assert_not_reached();
 489     }
 490
 491     /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
 492     reg = ahci_rreg(ahci, AHCI_CCCCTL);
 493     if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
 494         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
 495         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
 496         ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
 497         ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
 498     } else {
 499         g_assert_cmphex(reg, ==, 0);
 500     }
 501
 502     /* 7 CCC_PORTS */
 503     reg = ahci_rreg(ahci, AHCI_CCCPORTS);
 504     /* Must be zeroes initially regardless of CAP.CCCS */
 505     g_assert_cmphex(reg, ==, 0);
 506
 507     /* 8 EM_LOC */
 508     reg = ahci_rreg(ahci, AHCI_EMLOC);
 509     if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
 510         g_assert_cmphex(reg, ==, 0);
 511     }
 512
 513     /* 9 EM_CTL */
 514     reg = ahci_rreg(ahci, AHCI_EMCTL);
 515     if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
 516         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
 517         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
 518         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
 519         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
 520     } else {
 521         g_assert_cmphex(reg, ==, 0);
 522     }
 523
 524     /* 10 CAP2 -- Capabilities Extended */
 525     ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
 526     ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
 527
 528     /* 11 BOHC -- Bios/OS Handoff Control */
 529     reg = ahci_rreg(ahci, AHCI_BOHC);
 530     g_assert_cmphex(reg, ==, 0);
 531
 532     /* 12 -- 23: Reserved */
 533     g_test_message("Verifying HBA reserved area is empty.");
 534     for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
 535         reg = ahci_rreg(ahci, i);
 536         g_assert_cmphex(reg, ==, 0);
 537     }
 538
 539     /* 24 -- 39: NVMHCI */
 540     if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
 541         g_test_message("Verifying HBA/NVMHCI area is empty.");
 542         for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
 543             reg = ahci_rreg(ahci, i);
 544             g_assert_cmphex(reg, ==, 0);
 545         }
 546     }
 547
 548     /* 40 -- 63: Vendor */
 549     g_test_message("Verifying HBA/Vendor area is empty.");
 550     for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
 551         reg = ahci_rreg(ahci, i);
 552         g_assert_cmphex(reg, ==, 0);
 553     }
 554
 555     /* 64 -- XX: Port Space */
 556     for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
 557         if (BITSET(ports, 0x1)) {
 558             g_test_message("Testing port %u for spec", i);
 559             ahci_test_port_spec(ahci, i);
 560         } else {
 561             uint16_t j;
 562             uint16_t low = AHCI_PORTS + (32 * i);
 563             uint16_t high = AHCI_PORTS + (32 * (i + 1));
 564             g_test_message("Asserting unimplemented port %u "
 565                            "(reg [%u-%u]) is empty.",
 566                            i, low, high - 1);
 567             for (j = low; j < high; ++j) {
 568                 reg = ahci_rreg(ahci, j);
 569                 g_assert_cmphex(reg, ==, 0);
 570             }
 571         }
 572     }
 573 }
 574
 575 /**
 576  * Test the memory space for one port for specification adherence.
 577  */
 578 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
 579 {
 580     uint32_t reg;
 581     unsigned i;
 582
 583     /* (0) CLB */
 584     reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
 585     ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
 586
 587     /* (1) CLBU */
 588     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 589         reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
 590         g_assert_cmphex(reg, ==, 0);
 591     }
 592
 593     /* (2) FB */
 594     reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
 595     ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
 596
 597     /* (3) FBU */
 598     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 599         reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
 600         g_assert_cmphex(reg, ==, 0);
 601     }
 602
 603     /* (4) IS */
 604     reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
 605     g_assert_cmphex(reg, ==, 0);
 606
 607     /* (5) IE */
 608     reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
 609     g_assert_cmphex(reg, ==, 0);
 610
 611     /* (6) CMD */
 612     reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
 613     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
 614     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
 615     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
 616     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 617     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 618     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
 619     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
 620     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
 621     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
 622     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);  /* RW only if CAP.SALP */
 623     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);   /* RW only if CAP.SALP */
 624     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
 625     /* If CPDetect support does not exist, CPState must be off. */
 626     if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
 627         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
 628     }
 629     /* If MPSPresence is not set, MPSState must be off. */
 630     if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
 631         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 632     }
 633     /* If we do not support MPS, MPSS and MPSP must be off. */
 634     if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
 635         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 636         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
 637     }
 638     /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
 639     if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
 640         ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
 641     }
 642     /* HPCP and ESP cannot both be active. */
 643     g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
 644     /* If CAP.FBSS is not set, FBSCP must not be set. */
 645     if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
 646         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
 647     }
 648
 649     /* (7) RESERVED */
 650     reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
 651     g_assert_cmphex(reg, ==, 0);
 652
 653     /* (8) TFD */
 654     reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
 655     /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
 656      * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
 657     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
 658     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
 659     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
 660     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
 661     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
 662     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
 663     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
 664
 665     /* (9) SIG */
 666     /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
 667      * Even when GHC.ST is zero, the AHCI HBA may receive the initial
 668      * D2H register FIS and update the signature asynchronously,
 669      * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
 670
 671     /* (10) SSTS / SCR0: SStatus */
 672     reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
 673     ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
 674     /* Even though the register should be 0 at boot, it is asynchronous and
 675      * prone to change, so we cannot test any well known value. */
 676
 677     /* (11) SCTL / SCR2: SControl */
 678     reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
 679     g_assert_cmphex(reg, ==, 0);
 680
 681     /* (12) SERR / SCR1: SError */
 682     reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
 683     g_assert_cmphex(reg, ==, 0);
 684
 685     /* (13) SACT / SCR3: SActive */
 686     reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
 687     g_assert_cmphex(reg, ==, 0);
 688
 689     /* (14) CI */
 690     reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
 691     g_assert_cmphex(reg, ==, 0);
 692
 693     /* (15) SNTF */
 694     reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
 695     g_assert_cmphex(reg, ==, 0);
 696
 697     /* (16) FBS */
 698     reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
 699     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
 700     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
 701     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
 702     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
 703     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
 704     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
 705     if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
 706         /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
 707         g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
 708     }
 709
 710     /* [17 -- 27] RESERVED */
 711     for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
 712         reg = ahci_px_rreg(ahci, port, i);
 713         g_assert_cmphex(reg, ==, 0);
 714     }
 715
 716     /* [28 -- 31] Vendor-Specific */
 717     for (i = AHCI_PX_VS; i < 32; ++i) {
 718         reg = ahci_px_rreg(ahci, port, i);
 719         if (reg) {
 720             g_test_message("INFO: Vendor register %u non-empty", i);
 721         }
 722     }
 723 }
 724
 725 /**
 726  * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
 727  * device we see, then read and check the response.
 728  */
 729 static void ahci_test_identify(AHCIQState *ahci)
 730 {
 731     uint16_t buff[256];
 732     unsigned px;
 733     int rc;
 734     uint16_t sect_size;
 735     const size_t buffsize = 512;
 736
 737     g_assert(ahci != NULL);
 738
 739     /**
 740      * This serves as a bit of a tutorial on AHCI device programming:
 741      *
 742      * (1) Create a data buffer for the IDENTIFY response to be sent to
 743      * (2) Create a Command Table buffer, where we will store the
 744      *     command and PRDT (Physical Region Descriptor Table)
 745      * (3) Construct an FIS host-to-device command structure, and write it to
 746      *     the top of the Command Table buffer.
 747      * (4) Create one or more Physical Region Descriptors (PRDs) that describe
 748      *     a location in memory where data may be stored/retrieved.
 749      * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
 750      * (6) Each AHCI port has up to 32 command slots. Each slot contains a
 751      *     header that points to a Command Table buffer. Pick an unused slot
 752      *     and update it to point to the Command Table we have built.
 753      * (7) Now: Command #n points to our Command Table, and our Command Table
 754      *     contains the FIS (that describes our command) and the PRDTL, which
 755      *     describes our buffer.
 756      * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
 757      *     #n is ready for processing.
 758      */
 759
 760     /* Pick the first implemented and running port */
 761     px = ahci_port_select(ahci);
 762     g_test_message("Selected port %u for test", px);
 763
 764     /* Clear out the FIS Receive area and any pending interrupts. */
 765     ahci_port_clear(ahci, px);
 766
 767     /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
 768     ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0);
 769
 770     /* Check serial number/version in the buffer */
 771     /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
 772      * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
 773      * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
 774      * as a consequence, only needs to unchunk the data on LE machines. */
 775     string_bswap16(&buff[10], 20);
 776     rc = memcmp(&buff[10], "testdisk            ", 20);
 777     g_assert_cmphex(rc, ==, 0);
 778
 779     string_bswap16(&buff[23], 8);
 780     rc = memcmp(&buff[23], "version ", 8);
 781     g_assert_cmphex(rc, ==, 0);
 782
 783     sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
 784     g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE);
 785 }
 786
 787 static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize,
 788                                    uint64_t sector, uint8_t read_cmd,
 789                                    uint8_t write_cmd)
 790 {
 791     uint64_t ptr;
 792     uint8_t port;
 793     unsigned char *tx = g_malloc(bufsize);
 794     unsigned char *rx = g_malloc0(bufsize);
 795
 796     g_assert(ahci != NULL);
 797
 798     /* Pick the first running port and clear it. */
 799     port = ahci_port_select(ahci);
 800     ahci_port_clear(ahci, port);
 801
 802     /*** Create pattern and transfer to guest ***/
 803     /* Data buffer in the guest */
 804     ptr = ahci_alloc(ahci, bufsize);
 805     g_assert(ptr);
 806
 807     /* Write some indicative pattern to our buffer. */
 808     generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
 809     memwrite(ptr, tx, bufsize);
 810
 811     /* Write this buffer to disk, then read it back to the DMA buffer. */
 812     ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector);
 813     qmemset(ptr, 0x00, bufsize);
 814     ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector);
 815
 816     /*** Read back the Data ***/
 817     memread(ptr, rx, bufsize);
 818     g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
 819
 820     ahci_free(ahci, ptr);
 821     g_free(tx);
 822     g_free(rx);
 823 }
 824
 825 static void ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd)
 826 {
 827     uint8_t px;
 828     AHCICommand *cmd;
 829
 830     /* Sanitize */
 831     px = ahci_port_select(ahci);
 832     ahci_port_clear(ahci, px);
 833
 834     /* Issue Command */
 835     cmd = ahci_command_create(ide_cmd);
 836     ahci_command_commit(ahci, cmd, px);
 837     ahci_command_issue(ahci, cmd);
 838     ahci_command_verify(ahci, cmd);
 839     ahci_command_free(cmd);
 840 }
 841
 842 static void ahci_test_flush(AHCIQState *ahci)
 843 {
 844     ahci_test_nondata(ahci, CMD_FLUSH_CACHE);
 845 }
 846
 847
 848 /******************************************************************************/
 849 /* Test Interfaces                                                            */
 850 /******************************************************************************/
 851
 852 /**
 853  * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
 854  */
 855 static void test_sanity(void)
 856 {
 857     AHCIQState *ahci;
 858     ahci = ahci_boot(NULL);
 859     ahci_shutdown(ahci);
 860 }
 861
 862 /**
 863  * Ensure that the PCI configuration space for the AHCI device is in-line with
 864  * the AHCI 1.3 specification for initial values.
 865  */
 866 static void test_pci_spec(void)
 867 {
 868     AHCIQState *ahci;
 869     ahci = ahci_boot(NULL);
 870     ahci_test_pci_spec(ahci);
 871     ahci_shutdown(ahci);
 872 }
 873
 874 /**
 875  * Engage the PCI AHCI device and sanity check the response.
 876  * Perform additional PCI config space bringup for the HBA.
 877  */
 878 static void test_pci_enable(void)
 879 {
 880     AHCIQState *ahci;
 881     ahci = ahci_boot(NULL);
 882     ahci_pci_enable(ahci);
 883     ahci_shutdown(ahci);
 884 }
 885
 886 /**
 887  * Investigate the memory mapped regions of the HBA,
 888  * and test them for AHCI specification adherence.
 889  */
 890 static void test_hba_spec(void)
 891 {
 892     AHCIQState *ahci;
 893
 894     ahci = ahci_boot(NULL);
 895     ahci_pci_enable(ahci);
 896     ahci_test_hba_spec(ahci);
 897     ahci_shutdown(ahci);
 898 }
 899
 900 /**
 901  * Engage the HBA functionality of the AHCI PCI device,
 902  * and bring it into a functional idle state.
 903  */
 904 static void test_hba_enable(void)
 905 {
 906     AHCIQState *ahci;
 907
 908     ahci = ahci_boot(NULL);
 909     ahci_pci_enable(ahci);
 910     ahci_hba_enable(ahci);
 911     ahci_shutdown(ahci);
 912 }
 913
 914 /**
 915  * Bring up the device and issue an IDENTIFY command.
 916  * Inspect the state of the HBA device and the data returned.
 917  */
 918 static void test_identify(void)
 919 {
 920     AHCIQState *ahci;
 921
 922     ahci = ahci_boot_and_enable(NULL);
 923     ahci_test_identify(ahci);
 924     ahci_shutdown(ahci);
 925 }
 926
 927 /**
 928  * Fragmented DMA test: Perform a standard 4K DMA read/write
 929  * test, but make sure the physical regions are fragmented to
 930  * be very small, each just 32 bytes, to see how AHCI performs
 931  * with chunks defined to be much less than a sector.
 932  */
 933 static void test_dma_fragmented(void)
 934 {
 935     AHCIQState *ahci;
 936     AHCICommand *cmd;
 937     uint8_t px;
 938     size_t bufsize = 4096;
 939     unsigned char *tx = g_malloc(bufsize);
 940     unsigned char *rx = g_malloc0(bufsize);
 941     uint64_t ptr;
 942
 943     ahci = ahci_boot_and_enable(NULL);
 944     px = ahci_port_select(ahci);
 945     ahci_port_clear(ahci, px);
 946
 947     /* create pattern */
 948     generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE);
 949
 950     /* Create a DMA buffer in guest memory, and write our pattern to it. */
 951     ptr = guest_alloc(ahci->parent->alloc, bufsize);
 952     g_assert(ptr);
 953     memwrite(ptr, tx, bufsize);
 954
 955     cmd = ahci_command_create(CMD_WRITE_DMA);
 956     ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
 957     ahci_command_commit(ahci, cmd, px);
 958     ahci_command_issue(ahci, cmd);
 959     ahci_command_verify(ahci, cmd);
 960     g_free(cmd);
 961
 962     cmd = ahci_command_create(CMD_READ_DMA);
 963     ahci_command_adjust(cmd, 0, ptr, bufsize, 32);
 964     ahci_command_commit(ahci, cmd, px);
 965     ahci_command_issue(ahci, cmd);
 966     ahci_command_verify(ahci, cmd);
 967     g_free(cmd);
 968
 969     /* Read back the guest's receive buffer into local memory */
 970     memread(ptr, rx, bufsize);
 971     guest_free(ahci->parent->alloc, ptr);
 972
 973     g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
 974
 975     ahci_shutdown(ahci);
 976
 977     g_free(rx);
 978     g_free(tx);
 979 }
 980
 981 static void test_flush(void)
 982 {
 983     AHCIQState *ahci;
 984
 985     ahci = ahci_boot_and_enable(NULL);
 986     ahci_test_flush(ahci);
 987     ahci_shutdown(ahci);
 988 }
 989
 990 static void test_flush_retry(void)
 991 {
 992     AHCIQState *ahci;
 993     AHCICommand *cmd;
 994     uint8_t port;
 995     const char *s;
 996
 997     prepare_blkdebug_script(debug_path, "flush_to_disk");
 998     ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
 999                                 "format=qcow2,cache=writeback,"
1000                                 "rerror=stop,werror=stop "
1001                                 "-M q35 "
1002                                 "-device ide-hd,drive=drive0 ",
1003                                 debug_path,
1004                                 tmp_path);
1005
1006     /* Issue Flush Command */
1007     port = ahci_port_select(ahci);
1008     ahci_port_clear(ahci, port);
1009     cmd = ahci_command_create(CMD_FLUSH_CACHE);
1010     ahci_command_commit(ahci, cmd, port);
1011     ahci_command_issue_async(ahci, cmd);
1012     qmp_eventwait("STOP");
1013
1014     /* Complete the command */
1015     s = "{'execute':'cont' }";
1016     qmp_async(s);
1017     qmp_eventwait("RESUME");
1018     ahci_command_wait(ahci, cmd);
1019     ahci_command_verify(ahci, cmd);
1020
1021     ahci_command_free(cmd);
1022     ahci_shutdown(ahci);
1023 }
1024
1025 /******************************************************************************/
1026 /* AHCI I/O Test Matrix Definitions                                           */
1027
1028 enum BuffLen {
1029     LEN_BEGIN = 0,
1030     LEN_SIMPLE = LEN_BEGIN,
1031     LEN_DOUBLE,
1032     LEN_LONG,
1033     LEN_SHORT,
1034     NUM_LENGTHS
1035 };
1036
1037 static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double",
1038                                                  "long", "short" };
1039
1040 enum AddrMode {
1041     ADDR_MODE_BEGIN = 0,
1042     ADDR_MODE_LBA28 = ADDR_MODE_BEGIN,
1043     ADDR_MODE_LBA48,
1044     NUM_ADDR_MODES
1045 };
1046
1047 static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" };
1048
1049 enum IOMode {
1050     MODE_BEGIN = 0,
1051     MODE_PIO = MODE_BEGIN,
1052     MODE_DMA,
1053     NUM_MODES
1054 };
1055
1056 static const char *io_mode_str[NUM_MODES] = { "pio", "dma" };
1057
1058 enum IOOps {
1059     IO_BEGIN = 0,
1060     IO_READ = IO_BEGIN,
1061     IO_WRITE,
1062     NUM_IO_OPS
1063 };
1064
1065 enum OffsetType {
1066     OFFSET_BEGIN = 0,
1067     OFFSET_ZERO = OFFSET_BEGIN,
1068     OFFSET_LOW,
1069     OFFSET_HIGH,
1070     NUM_OFFSETS
1071 };
1072
1073 static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" };
1074
1075 typedef struct AHCIIOTestOptions {
1076     enum BuffLen length;
1077     enum AddrMode address_type;
1078     enum IOMode io_type;
1079     enum OffsetType offset;
1080 } AHCIIOTestOptions;
1081
1082 static uint64_t offset_sector(enum OffsetType ofst,
1083                               enum AddrMode addr_type,
1084                               uint64_t buffsize)
1085 {
1086     uint64_t ceil;
1087     uint64_t nsectors;
1088
1089     switch (ofst) {
1090     case OFFSET_ZERO:
1091         return 0;
1092     case OFFSET_LOW:
1093         return 1;
1094     case OFFSET_HIGH:
1095         ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff;
1096         ceil = MIN(ceil, TEST_IMAGE_SECTORS - 1);
1097         nsectors = buffsize / AHCI_SECTOR_SIZE;
1098         return ceil - nsectors + 1;
1099     default:
1100         g_assert_not_reached();
1101     }
1102 }
1103
1104 /**
1105  * Table of possible I/O ATA commands given a set of enumerations.
1106  */
1107 static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = {
1108     [MODE_PIO] = {
1109         [ADDR_MODE_LBA28] = {
1110             [IO_READ] = CMD_READ_PIO,
1111             [IO_WRITE] = CMD_WRITE_PIO },
1112         [ADDR_MODE_LBA48] = {
1113             [IO_READ] = CMD_READ_PIO_EXT,
1114             [IO_WRITE] = CMD_WRITE_PIO_EXT }
1115     },
1116     [MODE_DMA] = {
1117         [ADDR_MODE_LBA28] = {
1118             [IO_READ] = CMD_READ_DMA,
1119             [IO_WRITE] = CMD_WRITE_DMA },
1120         [ADDR_MODE_LBA48] = {
1121             [IO_READ] = CMD_READ_DMA_EXT,
1122             [IO_WRITE] = CMD_WRITE_DMA_EXT }
1123     }
1124 };
1125
1126 /**
1127  * Test a Read/Write pattern using various commands, addressing modes,
1128  * transfer modes, and buffer sizes.
1129  */
1130 static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma,
1131                                  unsigned bufsize, uint64_t sector)
1132 {
1133     AHCIQState *ahci;
1134
1135     ahci = ahci_boot_and_enable(NULL);
1136     ahci_test_io_rw_simple(ahci, bufsize, sector,
1137                            io_cmds[dma][lba48][IO_READ],
1138                            io_cmds[dma][lba48][IO_WRITE]);
1139     ahci_shutdown(ahci);
1140 }
1141
1142 /**
1143  * Demultiplex the test data and invoke the actual test routine.
1144  */
1145 static void test_io_interface(gconstpointer opaque)
1146 {
1147     AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque;
1148     unsigned bufsize;
1149     uint64_t sector;
1150
1151     switch (opts->length) {
1152     case LEN_SIMPLE:
1153         bufsize = 4096;
1154         break;
1155     case LEN_DOUBLE:
1156         bufsize = 8192;
1157         break;
1158     case LEN_LONG:
1159         bufsize = 4096 * 64;
1160         break;
1161     case LEN_SHORT:
1162         bufsize = 512;
1163         break;
1164     default:
1165         g_assert_not_reached();
1166     }
1167
1168     sector = offset_sector(opts->offset, opts->address_type, bufsize);
1169     test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector);
1170     g_free(opts);
1171     return;
1172 }
1173
1174 static void create_ahci_io_test(enum IOMode type, enum AddrMode addr,
1175                                 enum BuffLen len, enum OffsetType offset)
1176 {
1177     static const char *arch;
1178     char *name;
1179     AHCIIOTestOptions *opts = g_malloc(sizeof(AHCIIOTestOptions));
1180
1181     opts->length = len;
1182     opts->address_type = addr;
1183     opts->io_type = type;
1184     opts->offset = offset;
1185
1186     if (!arch) {
1187         arch = qtest_get_arch();
1188     }
1189
1190     name = g_strdup_printf("/%s/ahci/io/%s/%s/%s/%s", arch,
1191                            io_mode_str[type],
1192                            addr_mode_str[addr],
1193                            buff_len_str[len],
1194                            offset_str[offset]);
1195
1196     g_test_add_data_func(name, opts, test_io_interface);
1197     g_free(name);
1198 }
1199
1200 /******************************************************************************/
1201
1202 int main(int argc, char **argv)
1203 {
1204     const char *arch;
1205     int ret;
1206     int fd;
1207     int c;
1208     int i, j, k, m;
1209
1210     static struct option long_options[] = {
1211         {"pedantic", no_argument, 0, 'p' },
1212         {0, 0, 0, 0},
1213     };
1214
1215     /* Should be first to utilize g_test functionality, So we can see errors. */
1216     g_test_init(&argc, &argv, NULL);
1217
1218     while (1) {
1219         c = getopt_long(argc, argv, "", long_options, NULL);
1220         if (c == -1) {
1221             break;
1222         }
1223         switch (c) {
1224         case -1:
1225             break;
1226         case 'p':
1227             ahci_pedantic = 1;
1228             break;
1229         default:
1230             fprintf(stderr, "Unrecognized ahci_test option.\n");
1231             g_assert_not_reached();
1232         }
1233     }
1234
1235     /* Check architecture */
1236     arch = qtest_get_arch();
1237     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1238         g_test_message("Skipping test for non-x86");
1239         return 0;
1240     }
1241
1242     /* Create a temporary qcow2 image */
1243     close(mkstemp(tmp_path));
1244     mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB);
1245
1246     /* Create temporary blkdebug instructions */
1247     fd = mkstemp(debug_path);
1248     g_assert(fd >= 0);
1249     close(fd);
1250
1251     /* Run the tests */
1252     qtest_add_func("/ahci/sanity",     test_sanity);
1253     qtest_add_func("/ahci/pci_spec",   test_pci_spec);
1254     qtest_add_func("/ahci/pci_enable", test_pci_enable);
1255     qtest_add_func("/ahci/hba_spec",   test_hba_spec);
1256     qtest_add_func("/ahci/hba_enable", test_hba_enable);
1257     qtest_add_func("/ahci/identify",   test_identify);
1258
1259     for (i = MODE_BEGIN; i < NUM_MODES; i++) {
1260         for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) {
1261             for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) {
1262                 for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) {
1263                     create_ahci_io_test(i, j, k, m);
1264                 }
1265             }
1266         }
1267     }
1268
1269     qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented);
1270
1271     qtest_add_func("/ahci/flush/simple", test_flush);
1272     qtest_add_func("/ahci/flush/retry", test_flush_retry);
1273
1274     ret = g_test_run();
1275
1276     /* Cleanup */
1277     unlink(tmp_path);
1278     unlink(debug_path);
1279
1280     return ret;
1281 }