2 * HPPA emulation cpu translation for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "disas/disas.h"
23 #include "qemu/host-utils.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/cpu_ldst.h"
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
32 /* Since we have a distinction between register size and address size,
33 we need to redefine all of these. */
37 #undef tcg_global_mem_new
38 #undef tcg_temp_local_new
41 #if TARGET_LONG_BITS == 64
42 #define TCGv_tl TCGv_i64
43 #define tcg_temp_new_tl tcg_temp_new_i64
44 #define tcg_temp_free_tl tcg_temp_free_i64
45 #if TARGET_REGISTER_BITS == 64
46 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64
48 #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
51 #define TCGv_tl TCGv_i32
52 #define tcg_temp_new_tl tcg_temp_new_i32
53 #define tcg_temp_free_tl tcg_temp_free_i32
54 #define tcg_gen_extu_reg_tl tcg_gen_mov_i32
57 #if TARGET_REGISTER_BITS == 64
58 #define TCGv_reg TCGv_i64
60 #define tcg_temp_new tcg_temp_new_i64
61 #define tcg_global_mem_new tcg_global_mem_new_i64
62 #define tcg_temp_local_new tcg_temp_local_new_i64
63 #define tcg_temp_free tcg_temp_free_i64
65 #define tcg_gen_movi_reg tcg_gen_movi_i64
66 #define tcg_gen_mov_reg tcg_gen_mov_i64
67 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
68 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
69 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
70 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
71 #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
72 #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
73 #define tcg_gen_ld_reg tcg_gen_ld_i64
74 #define tcg_gen_st8_reg tcg_gen_st8_i64
75 #define tcg_gen_st16_reg tcg_gen_st16_i64
76 #define tcg_gen_st32_reg tcg_gen_st32_i64
77 #define tcg_gen_st_reg tcg_gen_st_i64
78 #define tcg_gen_add_reg tcg_gen_add_i64
79 #define tcg_gen_addi_reg tcg_gen_addi_i64
80 #define tcg_gen_sub_reg tcg_gen_sub_i64
81 #define tcg_gen_neg_reg tcg_gen_neg_i64
82 #define tcg_gen_subfi_reg tcg_gen_subfi_i64
83 #define tcg_gen_subi_reg tcg_gen_subi_i64
84 #define tcg_gen_and_reg tcg_gen_and_i64
85 #define tcg_gen_andi_reg tcg_gen_andi_i64
86 #define tcg_gen_or_reg tcg_gen_or_i64
87 #define tcg_gen_ori_reg tcg_gen_ori_i64
88 #define tcg_gen_xor_reg tcg_gen_xor_i64
89 #define tcg_gen_xori_reg tcg_gen_xori_i64
90 #define tcg_gen_not_reg tcg_gen_not_i64
91 #define tcg_gen_shl_reg tcg_gen_shl_i64
92 #define tcg_gen_shli_reg tcg_gen_shli_i64
93 #define tcg_gen_shr_reg tcg_gen_shr_i64
94 #define tcg_gen_shri_reg tcg_gen_shri_i64
95 #define tcg_gen_sar_reg tcg_gen_sar_i64
96 #define tcg_gen_sari_reg tcg_gen_sari_i64
97 #define tcg_gen_brcond_reg tcg_gen_brcond_i64
98 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
99 #define tcg_gen_setcond_reg tcg_gen_setcond_i64
100 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
101 #define tcg_gen_mul_reg tcg_gen_mul_i64
102 #define tcg_gen_muli_reg tcg_gen_muli_i64
103 #define tcg_gen_div_reg tcg_gen_div_i64
104 #define tcg_gen_rem_reg tcg_gen_rem_i64
105 #define tcg_gen_divu_reg tcg_gen_divu_i64
106 #define tcg_gen_remu_reg tcg_gen_remu_i64
107 #define tcg_gen_discard_reg tcg_gen_discard_i64
108 #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
109 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
110 #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
111 #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
112 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
113 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
114 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
115 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
116 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
117 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
118 #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
119 #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
120 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
121 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
122 #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
123 #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
124 #define tcg_gen_andc_reg tcg_gen_andc_i64
125 #define tcg_gen_eqv_reg tcg_gen_eqv_i64
126 #define tcg_gen_nand_reg tcg_gen_nand_i64
127 #define tcg_gen_nor_reg tcg_gen_nor_i64
128 #define tcg_gen_orc_reg tcg_gen_orc_i64
129 #define tcg_gen_clz_reg tcg_gen_clz_i64
130 #define tcg_gen_ctz_reg tcg_gen_ctz_i64
131 #define tcg_gen_clzi_reg tcg_gen_clzi_i64
132 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
133 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
134 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
135 #define tcg_gen_rotl_reg tcg_gen_rotl_i64
136 #define tcg_gen_rotli_reg tcg_gen_rotli_i64
137 #define tcg_gen_rotr_reg tcg_gen_rotr_i64
138 #define tcg_gen_rotri_reg tcg_gen_rotri_i64
139 #define tcg_gen_deposit_reg tcg_gen_deposit_i64
140 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
141 #define tcg_gen_extract_reg tcg_gen_extract_i64
142 #define tcg_gen_sextract_reg tcg_gen_sextract_i64
143 #define tcg_const_reg tcg_const_i64
144 #define tcg_const_local_reg tcg_const_local_i64
145 #define tcg_constant_reg tcg_constant_i64
146 #define tcg_gen_movcond_reg tcg_gen_movcond_i64
147 #define tcg_gen_add2_reg tcg_gen_add2_i64
148 #define tcg_gen_sub2_reg tcg_gen_sub2_i64
149 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
150 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
151 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
152 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
154 #define TCGv_reg TCGv_i32
155 #define tcg_temp_new tcg_temp_new_i32
156 #define tcg_global_mem_new tcg_global_mem_new_i32
157 #define tcg_temp_local_new tcg_temp_local_new_i32
158 #define tcg_temp_free tcg_temp_free_i32
160 #define tcg_gen_movi_reg tcg_gen_movi_i32
161 #define tcg_gen_mov_reg tcg_gen_mov_i32
162 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
163 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
164 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
165 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
166 #define tcg_gen_ld32u_reg tcg_gen_ld_i32
167 #define tcg_gen_ld32s_reg tcg_gen_ld_i32
168 #define tcg_gen_ld_reg tcg_gen_ld_i32
169 #define tcg_gen_st8_reg tcg_gen_st8_i32
170 #define tcg_gen_st16_reg tcg_gen_st16_i32
171 #define tcg_gen_st32_reg tcg_gen_st32_i32
172 #define tcg_gen_st_reg tcg_gen_st_i32
173 #define tcg_gen_add_reg tcg_gen_add_i32
174 #define tcg_gen_addi_reg tcg_gen_addi_i32
175 #define tcg_gen_sub_reg tcg_gen_sub_i32
176 #define tcg_gen_neg_reg tcg_gen_neg_i32
177 #define tcg_gen_subfi_reg tcg_gen_subfi_i32
178 #define tcg_gen_subi_reg tcg_gen_subi_i32
179 #define tcg_gen_and_reg tcg_gen_and_i32
180 #define tcg_gen_andi_reg tcg_gen_andi_i32
181 #define tcg_gen_or_reg tcg_gen_or_i32
182 #define tcg_gen_ori_reg tcg_gen_ori_i32
183 #define tcg_gen_xor_reg tcg_gen_xor_i32
184 #define tcg_gen_xori_reg tcg_gen_xori_i32
185 #define tcg_gen_not_reg tcg_gen_not_i32
186 #define tcg_gen_shl_reg tcg_gen_shl_i32
187 #define tcg_gen_shli_reg tcg_gen_shli_i32
188 #define tcg_gen_shr_reg tcg_gen_shr_i32
189 #define tcg_gen_shri_reg tcg_gen_shri_i32
190 #define tcg_gen_sar_reg tcg_gen_sar_i32
191 #define tcg_gen_sari_reg tcg_gen_sari_i32
192 #define tcg_gen_brcond_reg tcg_gen_brcond_i32
193 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
194 #define tcg_gen_setcond_reg tcg_gen_setcond_i32
195 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
196 #define tcg_gen_mul_reg tcg_gen_mul_i32
197 #define tcg_gen_muli_reg tcg_gen_muli_i32
198 #define tcg_gen_div_reg tcg_gen_div_i32
199 #define tcg_gen_rem_reg tcg_gen_rem_i32
200 #define tcg_gen_divu_reg tcg_gen_divu_i32
201 #define tcg_gen_remu_reg tcg_gen_remu_i32
202 #define tcg_gen_discard_reg tcg_gen_discard_i32
203 #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
204 #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
205 #define tcg_gen_extu_i32_reg tcg_gen_mov_i32
206 #define tcg_gen_ext_i32_reg tcg_gen_mov_i32
207 #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
208 #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
209 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
210 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
211 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
212 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
213 #define tcg_gen_ext32u_reg tcg_gen_mov_i32
214 #define tcg_gen_ext32s_reg tcg_gen_mov_i32
215 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
216 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
217 #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
218 #define tcg_gen_andc_reg tcg_gen_andc_i32
219 #define tcg_gen_eqv_reg tcg_gen_eqv_i32
220 #define tcg_gen_nand_reg tcg_gen_nand_i32
221 #define tcg_gen_nor_reg tcg_gen_nor_i32
222 #define tcg_gen_orc_reg tcg_gen_orc_i32
223 #define tcg_gen_clz_reg tcg_gen_clz_i32
224 #define tcg_gen_ctz_reg tcg_gen_ctz_i32
225 #define tcg_gen_clzi_reg tcg_gen_clzi_i32
226 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
227 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
228 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
229 #define tcg_gen_rotl_reg tcg_gen_rotl_i32
230 #define tcg_gen_rotli_reg tcg_gen_rotli_i32
231 #define tcg_gen_rotr_reg tcg_gen_rotr_i32
232 #define tcg_gen_rotri_reg tcg_gen_rotri_i32
233 #define tcg_gen_deposit_reg tcg_gen_deposit_i32
234 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
235 #define tcg_gen_extract_reg tcg_gen_extract_i32
236 #define tcg_gen_sextract_reg tcg_gen_sextract_i32
237 #define tcg_const_reg tcg_const_i32
238 #define tcg_const_local_reg tcg_const_local_i32
239 #define tcg_constant_reg tcg_constant_i32
240 #define tcg_gen_movcond_reg tcg_gen_movcond_i32
241 #define tcg_gen_add2_reg tcg_gen_add2_i32
242 #define tcg_gen_sub2_reg tcg_gen_sub2_i32
243 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
244 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
245 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
246 #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
247 #endif /* TARGET_REGISTER_BITS */
249 typedef struct DisasCond
{
254 typedef struct DisasContext
{
255 DisasContextBase base
;
277 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
278 static int expand_sm_imm(DisasContext
*ctx
, int val
)
280 if (val
& PSW_SM_E
) {
281 val
= (val
& ~PSW_SM_E
) | PSW_E
;
283 if (val
& PSW_SM_W
) {
284 val
= (val
& ~PSW_SM_W
) | PSW_W
;
289 /* Inverted space register indicates 0 means sr0 not inferred from base. */
290 static int expand_sr3x(DisasContext
*ctx
, int val
)
295 /* Convert the M:A bits within a memory insn to the tri-state value
296 we use for the final M. */
297 static int ma_to_m(DisasContext
*ctx
, int val
)
299 return val
& 2 ? (val
& 1 ? -1 : 1) : 0;
302 /* Convert the sign of the displacement to a pre or post-modify. */
303 static int pos_to_m(DisasContext
*ctx
, int val
)
308 static int neg_to_m(DisasContext
*ctx
, int val
)
313 /* Used for branch targets and fp memory ops. */
314 static int expand_shl2(DisasContext
*ctx
, int val
)
319 /* Used for fp memory ops. */
320 static int expand_shl3(DisasContext
*ctx
, int val
)
325 /* Used for assemble_21. */
326 static int expand_shl11(DisasContext
*ctx
, int val
)
332 /* Include the auto-generated decoder. */
333 #include "decode-insns.c.inc"
335 /* We are not using a goto_tb (for whatever reason), but have updated
336 the iaq (for whatever reason), so don't do it again on exit. */
337 #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0
339 /* We are exiting the TB, but have neither emitted a goto_tb, nor
340 updated the iaq for the next instruction to be executed. */
341 #define DISAS_IAQ_N_STALE DISAS_TARGET_1
343 /* Similarly, but we want to return to the main loop immediately
344 to recognize unmasked interrupts. */
345 #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2
346 #define DISAS_EXIT DISAS_TARGET_3
348 /* global register indexes */
349 static TCGv_reg cpu_gr
[32];
350 static TCGv_i64 cpu_sr
[4];
351 static TCGv_i64 cpu_srH
;
352 static TCGv_reg cpu_iaoq_f
;
353 static TCGv_reg cpu_iaoq_b
;
354 static TCGv_i64 cpu_iasq_f
;
355 static TCGv_i64 cpu_iasq_b
;
356 static TCGv_reg cpu_sar
;
357 static TCGv_reg cpu_psw_n
;
358 static TCGv_reg cpu_psw_v
;
359 static TCGv_reg cpu_psw_cb
;
360 static TCGv_reg cpu_psw_cb_msb
;
362 #include "exec/gen-icount.h"
364 void hppa_translate_init(void)
366 #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
368 typedef struct { TCGv_reg
*var
; const char *name
; int ofs
; } GlobalVar
;
369 static const GlobalVar vars
[] = {
370 { &cpu_sar
, "sar", offsetof(CPUHPPAState
, cr
[CR_SAR
]) },
381 /* Use the symbolic register names that match the disassembler. */
382 static const char gr_names
[32][4] = {
383 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
384 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
385 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
386 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
388 /* SR[4-7] are not global registers so that we can index them. */
389 static const char sr_names
[5][4] = {
390 "sr0", "sr1", "sr2", "sr3", "srH"
396 for (i
= 1; i
< 32; i
++) {
397 cpu_gr
[i
] = tcg_global_mem_new(cpu_env
,
398 offsetof(CPUHPPAState
, gr
[i
]),
401 for (i
= 0; i
< 4; i
++) {
402 cpu_sr
[i
] = tcg_global_mem_new_i64(cpu_env
,
403 offsetof(CPUHPPAState
, sr
[i
]),
406 cpu_srH
= tcg_global_mem_new_i64(cpu_env
,
407 offsetof(CPUHPPAState
, sr
[4]),
410 for (i
= 0; i
< ARRAY_SIZE(vars
); ++i
) {
411 const GlobalVar
*v
= &vars
[i
];
412 *v
->var
= tcg_global_mem_new(cpu_env
, v
->ofs
, v
->name
);
415 cpu_iasq_f
= tcg_global_mem_new_i64(cpu_env
,
416 offsetof(CPUHPPAState
, iasq_f
),
418 cpu_iasq_b
= tcg_global_mem_new_i64(cpu_env
,
419 offsetof(CPUHPPAState
, iasq_b
),
423 static DisasCond
cond_make_f(void)
432 static DisasCond
cond_make_t(void)
435 .c
= TCG_COND_ALWAYS
,
441 static DisasCond
cond_make_n(void)
446 .a1
= tcg_constant_reg(0)
450 static DisasCond
cond_make_0_tmp(TCGCond c
, TCGv_reg a0
)
452 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
454 .c
= c
, .a0
= a0
, .a1
= tcg_constant_reg(0)
458 static DisasCond
cond_make_0(TCGCond c
, TCGv_reg a0
)
460 TCGv_reg tmp
= tcg_temp_new();
461 tcg_gen_mov_reg(tmp
, a0
);
462 return cond_make_0_tmp(c
, tmp
);
465 static DisasCond
cond_make(TCGCond c
, TCGv_reg a0
, TCGv_reg a1
)
467 DisasCond r
= { .c
= c
};
469 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
470 r
.a0
= tcg_temp_new();
471 tcg_gen_mov_reg(r
.a0
, a0
);
472 r
.a1
= tcg_temp_new();
473 tcg_gen_mov_reg(r
.a1
, a1
);
478 static void cond_free(DisasCond
*cond
)
482 if (cond
->a0
!= cpu_psw_n
) {
483 tcg_temp_free(cond
->a0
);
485 tcg_temp_free(cond
->a1
);
489 case TCG_COND_ALWAYS
:
490 cond
->c
= TCG_COND_NEVER
;
497 static TCGv_reg
get_temp(DisasContext
*ctx
)
499 unsigned i
= ctx
->ntempr
++;
500 g_assert(i
< ARRAY_SIZE(ctx
->tempr
));
501 return ctx
->tempr
[i
] = tcg_temp_new();
504 #ifndef CONFIG_USER_ONLY
505 static TCGv_tl
get_temp_tl(DisasContext
*ctx
)
507 unsigned i
= ctx
->ntempl
++;
508 g_assert(i
< ARRAY_SIZE(ctx
->templ
));
509 return ctx
->templ
[i
] = tcg_temp_new_tl();
513 static TCGv_reg
load_const(DisasContext
*ctx
, target_sreg v
)
515 TCGv_reg t
= get_temp(ctx
);
516 tcg_gen_movi_reg(t
, v
);
520 static TCGv_reg
load_gpr(DisasContext
*ctx
, unsigned reg
)
523 TCGv_reg t
= get_temp(ctx
);
524 tcg_gen_movi_reg(t
, 0);
531 static TCGv_reg
dest_gpr(DisasContext
*ctx
, unsigned reg
)
533 if (reg
== 0 || ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
534 return get_temp(ctx
);
540 static void save_or_nullify(DisasContext
*ctx
, TCGv_reg dest
, TCGv_reg t
)
542 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
543 tcg_gen_movcond_reg(ctx
->null_cond
.c
, dest
, ctx
->null_cond
.a0
,
544 ctx
->null_cond
.a1
, dest
, t
);
546 tcg_gen_mov_reg(dest
, t
);
550 static void save_gpr(DisasContext
*ctx
, unsigned reg
, TCGv_reg t
)
553 save_or_nullify(ctx
, cpu_gr
[reg
], t
);
557 #ifdef HOST_WORDS_BIGENDIAN
565 static TCGv_i32
load_frw_i32(unsigned rt
)
567 TCGv_i32 ret
= tcg_temp_new_i32();
568 tcg_gen_ld_i32(ret
, cpu_env
,
569 offsetof(CPUHPPAState
, fr
[rt
& 31])
570 + (rt
& 32 ? LO_OFS
: HI_OFS
));
574 static TCGv_i32
load_frw0_i32(unsigned rt
)
577 return tcg_const_i32(0);
579 return load_frw_i32(rt
);
583 static TCGv_i64
load_frw0_i64(unsigned rt
)
586 return tcg_const_i64(0);
588 TCGv_i64 ret
= tcg_temp_new_i64();
589 tcg_gen_ld32u_i64(ret
, cpu_env
,
590 offsetof(CPUHPPAState
, fr
[rt
& 31])
591 + (rt
& 32 ? LO_OFS
: HI_OFS
));
596 static void save_frw_i32(unsigned rt
, TCGv_i32 val
)
598 tcg_gen_st_i32(val
, cpu_env
,
599 offsetof(CPUHPPAState
, fr
[rt
& 31])
600 + (rt
& 32 ? LO_OFS
: HI_OFS
));
606 static TCGv_i64
load_frd(unsigned rt
)
608 TCGv_i64 ret
= tcg_temp_new_i64();
609 tcg_gen_ld_i64(ret
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
613 static TCGv_i64
load_frd0(unsigned rt
)
616 return tcg_const_i64(0);
622 static void save_frd(unsigned rt
, TCGv_i64 val
)
624 tcg_gen_st_i64(val
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
627 static void load_spr(DisasContext
*ctx
, TCGv_i64 dest
, unsigned reg
)
629 #ifdef CONFIG_USER_ONLY
630 tcg_gen_movi_i64(dest
, 0);
633 tcg_gen_mov_i64(dest
, cpu_sr
[reg
]);
634 } else if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
635 tcg_gen_mov_i64(dest
, cpu_srH
);
637 tcg_gen_ld_i64(dest
, cpu_env
, offsetof(CPUHPPAState
, sr
[reg
]));
642 /* Skip over the implementation of an insn that has been nullified.
643 Use this when the insn is too complex for a conditional move. */
644 static void nullify_over(DisasContext
*ctx
)
646 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
647 /* The always condition should have been handled in the main loop. */
648 assert(ctx
->null_cond
.c
!= TCG_COND_ALWAYS
);
650 ctx
->null_lab
= gen_new_label();
652 /* If we're using PSW[N], copy it to a temp because... */
653 if (ctx
->null_cond
.a0
== cpu_psw_n
) {
654 ctx
->null_cond
.a0
= tcg_temp_new();
655 tcg_gen_mov_reg(ctx
->null_cond
.a0
, cpu_psw_n
);
657 /* ... we clear it before branching over the implementation,
658 so that (1) it's clear after nullifying this insn and
659 (2) if this insn nullifies the next, PSW[N] is valid. */
660 if (ctx
->psw_n_nonzero
) {
661 ctx
->psw_n_nonzero
= false;
662 tcg_gen_movi_reg(cpu_psw_n
, 0);
665 tcg_gen_brcond_reg(ctx
->null_cond
.c
, ctx
->null_cond
.a0
,
666 ctx
->null_cond
.a1
, ctx
->null_lab
);
667 cond_free(&ctx
->null_cond
);
671 /* Save the current nullification state to PSW[N]. */
672 static void nullify_save(DisasContext
*ctx
)
674 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
675 if (ctx
->psw_n_nonzero
) {
676 tcg_gen_movi_reg(cpu_psw_n
, 0);
680 if (ctx
->null_cond
.a0
!= cpu_psw_n
) {
681 tcg_gen_setcond_reg(ctx
->null_cond
.c
, cpu_psw_n
,
682 ctx
->null_cond
.a0
, ctx
->null_cond
.a1
);
683 ctx
->psw_n_nonzero
= true;
685 cond_free(&ctx
->null_cond
);
688 /* Set a PSW[N] to X. The intention is that this is used immediately
689 before a goto_tb/exit_tb, so that there is no fallthru path to other
690 code within the TB. Therefore we do not update psw_n_nonzero. */
691 static void nullify_set(DisasContext
*ctx
, bool x
)
693 if (ctx
->psw_n_nonzero
|| x
) {
694 tcg_gen_movi_reg(cpu_psw_n
, x
);
698 /* Mark the end of an instruction that may have been nullified.
699 This is the pair to nullify_over. Always returns true so that
700 it may be tail-called from a translate function. */
701 static bool nullify_end(DisasContext
*ctx
)
703 TCGLabel
*null_lab
= ctx
->null_lab
;
704 DisasJumpType status
= ctx
->base
.is_jmp
;
706 /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
707 For UPDATED, we cannot update on the nullified path. */
708 assert(status
!= DISAS_IAQ_N_UPDATED
);
710 if (likely(null_lab
== NULL
)) {
711 /* The current insn wasn't conditional or handled the condition
712 applied to it without a branch, so the (new) setting of
713 NULL_COND can be applied directly to the next insn. */
716 ctx
->null_lab
= NULL
;
718 if (likely(ctx
->null_cond
.c
== TCG_COND_NEVER
)) {
719 /* The next instruction will be unconditional,
720 and NULL_COND already reflects that. */
721 gen_set_label(null_lab
);
723 /* The insn that we just executed is itself nullifying the next
724 instruction. Store the condition in the PSW[N] global.
725 We asserted PSW[N] = 0 in nullify_over, so that after the
726 label we have the proper value in place. */
728 gen_set_label(null_lab
);
729 ctx
->null_cond
= cond_make_n();
731 if (status
== DISAS_NORETURN
) {
732 ctx
->base
.is_jmp
= DISAS_NEXT
;
737 static void copy_iaoq_entry(TCGv_reg dest
, target_ureg ival
, TCGv_reg vval
)
739 if (unlikely(ival
== -1)) {
740 tcg_gen_mov_reg(dest
, vval
);
742 tcg_gen_movi_reg(dest
, ival
);
746 static inline target_ureg
iaoq_dest(DisasContext
*ctx
, target_sreg disp
)
748 return ctx
->iaoq_f
+ disp
+ 8;
751 static void gen_excp_1(int exception
)
753 gen_helper_excp(cpu_env
, tcg_constant_i32(exception
));
756 static void gen_excp(DisasContext
*ctx
, int exception
)
758 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
759 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
761 gen_excp_1(exception
);
762 ctx
->base
.is_jmp
= DISAS_NORETURN
;
765 static bool gen_excp_iir(DisasContext
*ctx
, int exc
)
768 tcg_gen_st_reg(tcg_constant_reg(ctx
->insn
),
769 cpu_env
, offsetof(CPUHPPAState
, cr
[CR_IIR
]));
771 return nullify_end(ctx
);
774 static bool gen_illegal(DisasContext
*ctx
)
776 return gen_excp_iir(ctx
, EXCP_ILL
);
779 #ifdef CONFIG_USER_ONLY
780 #define CHECK_MOST_PRIVILEGED(EXCP) \
781 return gen_excp_iir(ctx, EXCP)
783 #define CHECK_MOST_PRIVILEGED(EXCP) \
785 if (ctx->privilege != 0) { \
786 return gen_excp_iir(ctx, EXCP); \
791 static bool use_goto_tb(DisasContext
*ctx
, target_ureg dest
)
793 return translator_use_goto_tb(&ctx
->base
, dest
);
796 /* If the next insn is to be nullified, and it's on the same page,
797 and we're not attempting to set a breakpoint on it, then we can
798 totally skip the nullified insn. This avoids creating and
799 executing a TB that merely branches to the next TB. */
800 static bool use_nullify_skip(DisasContext
*ctx
)
802 return (((ctx
->iaoq_b
^ ctx
->iaoq_f
) & TARGET_PAGE_MASK
) == 0
803 && !cpu_breakpoint_test(ctx
->cs
, ctx
->iaoq_b
, BP_ANY
));
806 static void gen_goto_tb(DisasContext
*ctx
, int which
,
807 target_ureg f
, target_ureg b
)
809 if (f
!= -1 && b
!= -1 && use_goto_tb(ctx
, f
)) {
810 tcg_gen_goto_tb(which
);
811 tcg_gen_movi_reg(cpu_iaoq_f
, f
);
812 tcg_gen_movi_reg(cpu_iaoq_b
, b
);
813 tcg_gen_exit_tb(ctx
->base
.tb
, which
);
815 copy_iaoq_entry(cpu_iaoq_f
, f
, cpu_iaoq_b
);
816 copy_iaoq_entry(cpu_iaoq_b
, b
, ctx
->iaoq_n_var
);
817 tcg_gen_lookup_and_goto_ptr();
821 static bool cond_need_sv(int c
)
823 return c
== 2 || c
== 3 || c
== 6;
826 static bool cond_need_cb(int c
)
828 return c
== 4 || c
== 5;
832 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
833 * the Parisc 1.1 Architecture Reference Manual for details.
836 static DisasCond
do_cond(unsigned cf
, TCGv_reg res
,
837 TCGv_reg cb_msb
, TCGv_reg sv
)
843 case 0: /* Never / TR (0 / 1) */
844 cond
= cond_make_f();
846 case 1: /* = / <> (Z / !Z) */
847 cond
= cond_make_0(TCG_COND_EQ
, res
);
849 case 2: /* < / >= (N ^ V / !(N ^ V) */
850 tmp
= tcg_temp_new();
851 tcg_gen_xor_reg(tmp
, res
, sv
);
852 cond
= cond_make_0_tmp(TCG_COND_LT
, tmp
);
854 case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
858 * ((res < 0) ^ (sv < 0)) | !res
859 * ((res ^ sv) < 0) | !res
860 * (~(res ^ sv) >= 0) | !res
861 * !(~(res ^ sv) >> 31) | !res
862 * !(~(res ^ sv) >> 31 & res)
864 tmp
= tcg_temp_new();
865 tcg_gen_eqv_reg(tmp
, res
, sv
);
866 tcg_gen_sari_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
867 tcg_gen_and_reg(tmp
, tmp
, res
);
868 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
870 case 4: /* NUV / UV (!C / C) */
871 cond
= cond_make_0(TCG_COND_EQ
, cb_msb
);
873 case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
874 tmp
= tcg_temp_new();
875 tcg_gen_neg_reg(tmp
, cb_msb
);
876 tcg_gen_and_reg(tmp
, tmp
, res
);
877 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
879 case 6: /* SV / NSV (V / !V) */
880 cond
= cond_make_0(TCG_COND_LT
, sv
);
882 case 7: /* OD / EV */
883 tmp
= tcg_temp_new();
884 tcg_gen_andi_reg(tmp
, res
, 1);
885 cond
= cond_make_0_tmp(TCG_COND_NE
, tmp
);
888 g_assert_not_reached();
891 cond
.c
= tcg_invert_cond(cond
.c
);
897 /* Similar, but for the special case of subtraction without borrow, we
898 can use the inputs directly. This can allow other computation to be
899 deleted as unused. */
901 static DisasCond
do_sub_cond(unsigned cf
, TCGv_reg res
,
902 TCGv_reg in1
, TCGv_reg in2
, TCGv_reg sv
)
908 cond
= cond_make(TCG_COND_EQ
, in1
, in2
);
911 cond
= cond_make(TCG_COND_LT
, in1
, in2
);
914 cond
= cond_make(TCG_COND_LE
, in1
, in2
);
916 case 4: /* << / >>= */
917 cond
= cond_make(TCG_COND_LTU
, in1
, in2
);
919 case 5: /* <<= / >> */
920 cond
= cond_make(TCG_COND_LEU
, in1
, in2
);
923 return do_cond(cf
, res
, NULL
, sv
);
926 cond
.c
= tcg_invert_cond(cond
.c
);
933 * Similar, but for logicals, where the carry and overflow bits are not
934 * computed, and use of them is undefined.
936 * Undefined or not, hardware does not trap. It seems reasonable to
937 * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
938 * how cases c={2,3} are treated.
941 static DisasCond
do_log_cond(unsigned cf
, TCGv_reg res
)
945 case 9: /* undef, C */
946 case 11: /* undef, C & !Z */
947 case 12: /* undef, V */
948 return cond_make_f();
951 case 8: /* undef, !C */
952 case 10: /* undef, !C | Z */
953 case 13: /* undef, !V */
954 return cond_make_t();
957 return cond_make_0(TCG_COND_EQ
, res
);
959 return cond_make_0(TCG_COND_NE
, res
);
961 return cond_make_0(TCG_COND_LT
, res
);
963 return cond_make_0(TCG_COND_GE
, res
);
965 return cond_make_0(TCG_COND_LE
, res
);
967 return cond_make_0(TCG_COND_GT
, res
);
971 return do_cond(cf
, res
, NULL
, NULL
);
974 g_assert_not_reached();
978 /* Similar, but for shift/extract/deposit conditions. */
980 static DisasCond
do_sed_cond(unsigned orig
, TCGv_reg res
)
984 /* Convert the compressed condition codes to standard.
985 0-2 are the same as logicals (nv,<,<=), while 3 is OD.
986 4-7 are the reverse of 0-3. */
993 return do_log_cond(c
* 2 + f
, res
);
996 /* Similar, but for unit conditions. */
998 static DisasCond
do_unit_cond(unsigned cf
, TCGv_reg res
,
999 TCGv_reg in1
, TCGv_reg in2
)
1002 TCGv_reg tmp
, cb
= NULL
;
1005 /* Since we want to test lots of carry-out bits all at once, do not
1006 * do our normal thing and compute carry-in of bit B+1 since that
1007 * leaves us with carry bits spread across two words.
1009 cb
= tcg_temp_new();
1010 tmp
= tcg_temp_new();
1011 tcg_gen_or_reg(cb
, in1
, in2
);
1012 tcg_gen_and_reg(tmp
, in1
, in2
);
1013 tcg_gen_andc_reg(cb
, cb
, res
);
1014 tcg_gen_or_reg(cb
, cb
, tmp
);
1019 case 0: /* never / TR */
1020 case 1: /* undefined */
1021 case 5: /* undefined */
1022 cond
= cond_make_f();
1025 case 2: /* SBZ / NBZ */
1026 /* See hasless(v,1) from
1027 * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
1029 tmp
= tcg_temp_new();
1030 tcg_gen_subi_reg(tmp
, res
, 0x01010101u
);
1031 tcg_gen_andc_reg(tmp
, tmp
, res
);
1032 tcg_gen_andi_reg(tmp
, tmp
, 0x80808080u
);
1033 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1037 case 3: /* SHZ / NHZ */
1038 tmp
= tcg_temp_new();
1039 tcg_gen_subi_reg(tmp
, res
, 0x00010001u
);
1040 tcg_gen_andc_reg(tmp
, tmp
, res
);
1041 tcg_gen_andi_reg(tmp
, tmp
, 0x80008000u
);
1042 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1046 case 4: /* SDC / NDC */
1047 tcg_gen_andi_reg(cb
, cb
, 0x88888888u
);
1048 cond
= cond_make_0(TCG_COND_NE
, cb
);
1051 case 6: /* SBC / NBC */
1052 tcg_gen_andi_reg(cb
, cb
, 0x80808080u
);
1053 cond
= cond_make_0(TCG_COND_NE
, cb
);
1056 case 7: /* SHC / NHC */
1057 tcg_gen_andi_reg(cb
, cb
, 0x80008000u
);
1058 cond
= cond_make_0(TCG_COND_NE
, cb
);
1062 g_assert_not_reached();
1068 cond
.c
= tcg_invert_cond(cond
.c
);
1074 /* Compute signed overflow for addition. */
1075 static TCGv_reg
do_add_sv(DisasContext
*ctx
, TCGv_reg res
,
1076 TCGv_reg in1
, TCGv_reg in2
)
1078 TCGv_reg sv
= get_temp(ctx
);
1079 TCGv_reg tmp
= tcg_temp_new();
1081 tcg_gen_xor_reg(sv
, res
, in1
);
1082 tcg_gen_xor_reg(tmp
, in1
, in2
);
1083 tcg_gen_andc_reg(sv
, sv
, tmp
);
1089 /* Compute signed overflow for subtraction. */
1090 static TCGv_reg
do_sub_sv(DisasContext
*ctx
, TCGv_reg res
,
1091 TCGv_reg in1
, TCGv_reg in2
)
1093 TCGv_reg sv
= get_temp(ctx
);
1094 TCGv_reg tmp
= tcg_temp_new();
1096 tcg_gen_xor_reg(sv
, res
, in1
);
1097 tcg_gen_xor_reg(tmp
, in1
, in2
);
1098 tcg_gen_and_reg(sv
, sv
, tmp
);
1104 static void do_add(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1105 TCGv_reg in2
, unsigned shift
, bool is_l
,
1106 bool is_tsv
, bool is_tc
, bool is_c
, unsigned cf
)
1108 TCGv_reg dest
, cb
, cb_msb
, sv
, tmp
;
1109 unsigned c
= cf
>> 1;
1112 dest
= tcg_temp_new();
1117 tmp
= get_temp(ctx
);
1118 tcg_gen_shli_reg(tmp
, in1
, shift
);
1122 if (!is_l
|| cond_need_cb(c
)) {
1123 TCGv_reg zero
= tcg_constant_reg(0);
1124 cb_msb
= get_temp(ctx
);
1125 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, in2
, zero
);
1127 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cpu_psw_cb_msb
, zero
);
1131 tcg_gen_xor_reg(cb
, in1
, in2
);
1132 tcg_gen_xor_reg(cb
, cb
, dest
);
1135 tcg_gen_add_reg(dest
, in1
, in2
);
1137 tcg_gen_add_reg(dest
, dest
, cpu_psw_cb_msb
);
1141 /* Compute signed overflow if required. */
1143 if (is_tsv
|| cond_need_sv(c
)) {
1144 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
1146 /* ??? Need to include overflow from shift. */
1147 gen_helper_tsv(cpu_env
, sv
);
1151 /* Emit any conditional trap before any writeback. */
1152 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1154 tmp
= tcg_temp_new();
1155 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1156 gen_helper_tcond(cpu_env
, tmp
);
1160 /* Write back the result. */
1162 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1163 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1165 save_gpr(ctx
, rt
, dest
);
1166 tcg_temp_free(dest
);
1168 /* Install the new nullification. */
1169 cond_free(&ctx
->null_cond
);
1170 ctx
->null_cond
= cond
;
1173 static bool do_add_reg(DisasContext
*ctx
, arg_rrr_cf_sh
*a
,
1174 bool is_l
, bool is_tsv
, bool is_tc
, bool is_c
)
1176 TCGv_reg tcg_r1
, tcg_r2
;
1181 tcg_r1
= load_gpr(ctx
, a
->r1
);
1182 tcg_r2
= load_gpr(ctx
, a
->r2
);
1183 do_add(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->sh
, is_l
, is_tsv
, is_tc
, is_c
, a
->cf
);
1184 return nullify_end(ctx
);
1187 static bool do_add_imm(DisasContext
*ctx
, arg_rri_cf
*a
,
1188 bool is_tsv
, bool is_tc
)
1190 TCGv_reg tcg_im
, tcg_r2
;
1195 tcg_im
= load_const(ctx
, a
->i
);
1196 tcg_r2
= load_gpr(ctx
, a
->r
);
1197 do_add(ctx
, a
->t
, tcg_im
, tcg_r2
, 0, 0, is_tsv
, is_tc
, 0, a
->cf
);
1198 return nullify_end(ctx
);
1201 static void do_sub(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1202 TCGv_reg in2
, bool is_tsv
, bool is_b
,
1203 bool is_tc
, unsigned cf
)
1205 TCGv_reg dest
, sv
, cb
, cb_msb
, zero
, tmp
;
1206 unsigned c
= cf
>> 1;
1209 dest
= tcg_temp_new();
1210 cb
= tcg_temp_new();
1211 cb_msb
= tcg_temp_new();
1213 zero
= tcg_constant_reg(0);
1215 /* DEST,C = IN1 + ~IN2 + C. */
1216 tcg_gen_not_reg(cb
, in2
);
1217 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, cpu_psw_cb_msb
, zero
);
1218 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cb
, zero
);
1219 tcg_gen_xor_reg(cb
, cb
, in1
);
1220 tcg_gen_xor_reg(cb
, cb
, dest
);
1222 /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
1223 operations by seeding the high word with 1 and subtracting. */
1224 tcg_gen_movi_reg(cb_msb
, 1);
1225 tcg_gen_sub2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, zero
);
1226 tcg_gen_eqv_reg(cb
, in1
, in2
);
1227 tcg_gen_xor_reg(cb
, cb
, dest
);
1230 /* Compute signed overflow if required. */
1232 if (is_tsv
|| cond_need_sv(c
)) {
1233 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1235 gen_helper_tsv(cpu_env
, sv
);
1239 /* Compute the condition. We cannot use the special case for borrow. */
1241 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1243 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1246 /* Emit any conditional trap before any writeback. */
1248 tmp
= tcg_temp_new();
1249 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1250 gen_helper_tcond(cpu_env
, tmp
);
1254 /* Write back the result. */
1255 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1256 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1257 save_gpr(ctx
, rt
, dest
);
1258 tcg_temp_free(dest
);
1260 tcg_temp_free(cb_msb
);
1262 /* Install the new nullification. */
1263 cond_free(&ctx
->null_cond
);
1264 ctx
->null_cond
= cond
;
1267 static bool do_sub_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1268 bool is_tsv
, bool is_b
, bool is_tc
)
1270 TCGv_reg tcg_r1
, tcg_r2
;
1275 tcg_r1
= load_gpr(ctx
, a
->r1
);
1276 tcg_r2
= load_gpr(ctx
, a
->r2
);
1277 do_sub(ctx
, a
->t
, tcg_r1
, tcg_r2
, is_tsv
, is_b
, is_tc
, a
->cf
);
1278 return nullify_end(ctx
);
1281 static bool do_sub_imm(DisasContext
*ctx
, arg_rri_cf
*a
, bool is_tsv
)
1283 TCGv_reg tcg_im
, tcg_r2
;
1288 tcg_im
= load_const(ctx
, a
->i
);
1289 tcg_r2
= load_gpr(ctx
, a
->r
);
1290 do_sub(ctx
, a
->t
, tcg_im
, tcg_r2
, is_tsv
, 0, 0, a
->cf
);
1291 return nullify_end(ctx
);
1294 static void do_cmpclr(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1295 TCGv_reg in2
, unsigned cf
)
1300 dest
= tcg_temp_new();
1301 tcg_gen_sub_reg(dest
, in1
, in2
);
1303 /* Compute signed overflow if required. */
1305 if (cond_need_sv(cf
>> 1)) {
1306 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1309 /* Form the condition for the compare. */
1310 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1313 tcg_gen_movi_reg(dest
, 0);
1314 save_gpr(ctx
, rt
, dest
);
1315 tcg_temp_free(dest
);
1317 /* Install the new nullification. */
1318 cond_free(&ctx
->null_cond
);
1319 ctx
->null_cond
= cond
;
1322 static void do_log(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1323 TCGv_reg in2
, unsigned cf
,
1324 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1326 TCGv_reg dest
= dest_gpr(ctx
, rt
);
1328 /* Perform the operation, and writeback. */
1330 save_gpr(ctx
, rt
, dest
);
1332 /* Install the new nullification. */
1333 cond_free(&ctx
->null_cond
);
1335 ctx
->null_cond
= do_log_cond(cf
, dest
);
1339 static bool do_log_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1340 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1342 TCGv_reg tcg_r1
, tcg_r2
;
1347 tcg_r1
= load_gpr(ctx
, a
->r1
);
1348 tcg_r2
= load_gpr(ctx
, a
->r2
);
1349 do_log(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, fn
);
1350 return nullify_end(ctx
);
1353 static void do_unit(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1354 TCGv_reg in2
, unsigned cf
, bool is_tc
,
1355 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1361 dest
= dest_gpr(ctx
, rt
);
1363 save_gpr(ctx
, rt
, dest
);
1364 cond_free(&ctx
->null_cond
);
1366 dest
= tcg_temp_new();
1369 cond
= do_unit_cond(cf
, dest
, in1
, in2
);
1372 TCGv_reg tmp
= tcg_temp_new();
1373 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1374 gen_helper_tcond(cpu_env
, tmp
);
1377 save_gpr(ctx
, rt
, dest
);
1379 cond_free(&ctx
->null_cond
);
1380 ctx
->null_cond
= cond
;
1384 #ifndef CONFIG_USER_ONLY
1385 /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
1386 from the top 2 bits of the base register. There are a few system
1387 instructions that have a 3-bit space specifier, for which SR0 is
1388 not special. To handle this, pass ~SP. */
1389 static TCGv_i64
space_select(DisasContext
*ctx
, int sp
, TCGv_reg base
)
1399 spc
= get_temp_tl(ctx
);
1400 load_spr(ctx
, spc
, sp
);
1403 if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
1407 ptr
= tcg_temp_new_ptr();
1408 tmp
= tcg_temp_new();
1409 spc
= get_temp_tl(ctx
);
1411 tcg_gen_shri_reg(tmp
, base
, TARGET_REGISTER_BITS
- 5);
1412 tcg_gen_andi_reg(tmp
, tmp
, 030);
1413 tcg_gen_trunc_reg_ptr(ptr
, tmp
);
1416 tcg_gen_add_ptr(ptr
, ptr
, cpu_env
);
1417 tcg_gen_ld_i64(spc
, ptr
, offsetof(CPUHPPAState
, sr
[4]));
1418 tcg_temp_free_ptr(ptr
);
1424 static void form_gva(DisasContext
*ctx
, TCGv_tl
*pgva
, TCGv_reg
*pofs
,
1425 unsigned rb
, unsigned rx
, int scale
, target_sreg disp
,
1426 unsigned sp
, int modify
, bool is_phys
)
1428 TCGv_reg base
= load_gpr(ctx
, rb
);
1431 /* Note that RX is mutually exclusive with DISP. */
1433 ofs
= get_temp(ctx
);
1434 tcg_gen_shli_reg(ofs
, cpu_gr
[rx
], scale
);
1435 tcg_gen_add_reg(ofs
, ofs
, base
);
1436 } else if (disp
|| modify
) {
1437 ofs
= get_temp(ctx
);
1438 tcg_gen_addi_reg(ofs
, base
, disp
);
1444 #ifdef CONFIG_USER_ONLY
1445 *pgva
= (modify
<= 0 ? ofs
: base
);
1447 TCGv_tl addr
= get_temp_tl(ctx
);
1448 tcg_gen_extu_reg_tl(addr
, modify
<= 0 ? ofs
: base
);
1449 if (ctx
->tb_flags
& PSW_W
) {
1450 tcg_gen_andi_tl(addr
, addr
, 0x3fffffffffffffffull
);
1453 tcg_gen_or_tl(addr
, addr
, space_select(ctx
, sp
, base
));
1459 /* Emit a memory load. The modify parameter should be
1460 * < 0 for pre-modify,
1461 * > 0 for post-modify,
1462 * = 0 for no base register update.
1464 static void do_load_32(DisasContext
*ctx
, TCGv_i32 dest
, unsigned rb
,
1465 unsigned rx
, int scale
, target_sreg disp
,
1466 unsigned sp
, int modify
, MemOp mop
)
1471 /* Caller uses nullify_over/nullify_end. */
1472 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1474 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1475 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1476 tcg_gen_qemu_ld_reg(dest
, addr
, ctx
->mmu_idx
, mop
);
1478 save_gpr(ctx
, rb
, ofs
);
1482 static void do_load_64(DisasContext
*ctx
, TCGv_i64 dest
, unsigned rb
,
1483 unsigned rx
, int scale
, target_sreg disp
,
1484 unsigned sp
, int modify
, MemOp mop
)
1489 /* Caller uses nullify_over/nullify_end. */
1490 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1492 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1493 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1494 tcg_gen_qemu_ld_i64(dest
, addr
, ctx
->mmu_idx
, mop
);
1496 save_gpr(ctx
, rb
, ofs
);
1500 static void do_store_32(DisasContext
*ctx
, TCGv_i32 src
, unsigned rb
,
1501 unsigned rx
, int scale
, target_sreg disp
,
1502 unsigned sp
, int modify
, MemOp mop
)
1507 /* Caller uses nullify_over/nullify_end. */
1508 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1510 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1511 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1512 tcg_gen_qemu_st_i32(src
, addr
, ctx
->mmu_idx
, mop
);
1514 save_gpr(ctx
, rb
, ofs
);
1518 static void do_store_64(DisasContext
*ctx
, TCGv_i64 src
, unsigned rb
,
1519 unsigned rx
, int scale
, target_sreg disp
,
1520 unsigned sp
, int modify
, MemOp mop
)
1525 /* Caller uses nullify_over/nullify_end. */
1526 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1528 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1529 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1530 tcg_gen_qemu_st_i64(src
, addr
, ctx
->mmu_idx
, mop
);
1532 save_gpr(ctx
, rb
, ofs
);
1536 #if TARGET_REGISTER_BITS == 64
1537 #define do_load_reg do_load_64
1538 #define do_store_reg do_store_64
1540 #define do_load_reg do_load_32
1541 #define do_store_reg do_store_32
1544 static bool do_load(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1545 unsigned rx
, int scale
, target_sreg disp
,
1546 unsigned sp
, int modify
, MemOp mop
)
1553 /* No base register update. */
1554 dest
= dest_gpr(ctx
, rt
);
1556 /* Make sure if RT == RB, we see the result of the load. */
1557 dest
= get_temp(ctx
);
1559 do_load_reg(ctx
, dest
, rb
, rx
, scale
, disp
, sp
, modify
, mop
);
1560 save_gpr(ctx
, rt
, dest
);
1562 return nullify_end(ctx
);
1565 static bool do_floadw(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1566 unsigned rx
, int scale
, target_sreg disp
,
1567 unsigned sp
, int modify
)
1573 tmp
= tcg_temp_new_i32();
1574 do_load_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1575 save_frw_i32(rt
, tmp
);
1576 tcg_temp_free_i32(tmp
);
1579 gen_helper_loaded_fr0(cpu_env
);
1582 return nullify_end(ctx
);
1585 static bool trans_fldw(DisasContext
*ctx
, arg_ldst
*a
)
1587 return do_floadw(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1588 a
->disp
, a
->sp
, a
->m
);
1591 static bool do_floadd(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1592 unsigned rx
, int scale
, target_sreg disp
,
1593 unsigned sp
, int modify
)
1599 tmp
= tcg_temp_new_i64();
1600 do_load_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEQ
);
1602 tcg_temp_free_i64(tmp
);
1605 gen_helper_loaded_fr0(cpu_env
);
1608 return nullify_end(ctx
);
1611 static bool trans_fldd(DisasContext
*ctx
, arg_ldst
*a
)
1613 return do_floadd(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1614 a
->disp
, a
->sp
, a
->m
);
1617 static bool do_store(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1618 target_sreg disp
, unsigned sp
,
1619 int modify
, MemOp mop
)
1622 do_store_reg(ctx
, load_gpr(ctx
, rt
), rb
, 0, 0, disp
, sp
, modify
, mop
);
1623 return nullify_end(ctx
);
1626 static bool do_fstorew(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1627 unsigned rx
, int scale
, target_sreg disp
,
1628 unsigned sp
, int modify
)
1634 tmp
= load_frw_i32(rt
);
1635 do_store_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1636 tcg_temp_free_i32(tmp
);
1638 return nullify_end(ctx
);
1641 static bool trans_fstw(DisasContext
*ctx
, arg_ldst
*a
)
1643 return do_fstorew(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1644 a
->disp
, a
->sp
, a
->m
);
1647 static bool do_fstored(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1648 unsigned rx
, int scale
, target_sreg disp
,
1649 unsigned sp
, int modify
)
1656 do_store_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEQ
);
1657 tcg_temp_free_i64(tmp
);
1659 return nullify_end(ctx
);
1662 static bool trans_fstd(DisasContext
*ctx
, arg_ldst
*a
)
1664 return do_fstored(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1665 a
->disp
, a
->sp
, a
->m
);
1668 static bool do_fop_wew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1669 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
))
1674 tmp
= load_frw0_i32(ra
);
1676 func(tmp
, cpu_env
, tmp
);
1678 save_frw_i32(rt
, tmp
);
1679 tcg_temp_free_i32(tmp
);
1680 return nullify_end(ctx
);
1683 static bool do_fop_wed(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1684 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i64
))
1691 dst
= tcg_temp_new_i32();
1693 func(dst
, cpu_env
, src
);
1695 tcg_temp_free_i64(src
);
1696 save_frw_i32(rt
, dst
);
1697 tcg_temp_free_i32(dst
);
1698 return nullify_end(ctx
);
1701 static bool do_fop_ded(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1702 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
1707 tmp
= load_frd0(ra
);
1709 func(tmp
, cpu_env
, tmp
);
1712 tcg_temp_free_i64(tmp
);
1713 return nullify_end(ctx
);
1716 static bool do_fop_dew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1717 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i32
))
1723 src
= load_frw0_i32(ra
);
1724 dst
= tcg_temp_new_i64();
1726 func(dst
, cpu_env
, src
);
1728 tcg_temp_free_i32(src
);
1730 tcg_temp_free_i64(dst
);
1731 return nullify_end(ctx
);
1734 static bool do_fop_weww(DisasContext
*ctx
, unsigned rt
,
1735 unsigned ra
, unsigned rb
,
1736 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
1741 a
= load_frw0_i32(ra
);
1742 b
= load_frw0_i32(rb
);
1744 func(a
, cpu_env
, a
, b
);
1746 tcg_temp_free_i32(b
);
1747 save_frw_i32(rt
, a
);
1748 tcg_temp_free_i32(a
);
1749 return nullify_end(ctx
);
1752 static bool do_fop_dedd(DisasContext
*ctx
, unsigned rt
,
1753 unsigned ra
, unsigned rb
,
1754 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
1762 func(a
, cpu_env
, a
, b
);
1764 tcg_temp_free_i64(b
);
1766 tcg_temp_free_i64(a
);
1767 return nullify_end(ctx
);
1770 /* Emit an unconditional branch to a direct target, which may or may not
1771 have already had nullification handled. */
1772 static bool do_dbranch(DisasContext
*ctx
, target_ureg dest
,
1773 unsigned link
, bool is_n
)
1775 if (ctx
->null_cond
.c
== TCG_COND_NEVER
&& ctx
->null_lab
== NULL
) {
1777 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1781 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1787 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1790 if (is_n
&& use_nullify_skip(ctx
)) {
1791 nullify_set(ctx
, 0);
1792 gen_goto_tb(ctx
, 0, dest
, dest
+ 4);
1794 nullify_set(ctx
, is_n
);
1795 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, dest
);
1800 nullify_set(ctx
, 0);
1801 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, ctx
->iaoq_n
);
1802 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1807 /* Emit a conditional branch to a direct target. If the branch itself
1808 is nullified, we should have already used nullify_over. */
1809 static bool do_cbranch(DisasContext
*ctx
, target_sreg disp
, bool is_n
,
1812 target_ureg dest
= iaoq_dest(ctx
, disp
);
1813 TCGLabel
*taken
= NULL
;
1814 TCGCond c
= cond
->c
;
1817 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1819 /* Handle TRUE and NEVER as direct branches. */
1820 if (c
== TCG_COND_ALWAYS
) {
1821 return do_dbranch(ctx
, dest
, 0, is_n
&& disp
>= 0);
1823 if (c
== TCG_COND_NEVER
) {
1824 return do_dbranch(ctx
, ctx
->iaoq_n
, 0, is_n
&& disp
< 0);
1827 taken
= gen_new_label();
1828 tcg_gen_brcond_reg(c
, cond
->a0
, cond
->a1
, taken
);
1831 /* Not taken: Condition not satisfied; nullify on backward branches. */
1832 n
= is_n
&& disp
< 0;
1833 if (n
&& use_nullify_skip(ctx
)) {
1834 nullify_set(ctx
, 0);
1835 gen_goto_tb(ctx
, 0, ctx
->iaoq_n
, ctx
->iaoq_n
+ 4);
1837 if (!n
&& ctx
->null_lab
) {
1838 gen_set_label(ctx
->null_lab
);
1839 ctx
->null_lab
= NULL
;
1841 nullify_set(ctx
, n
);
1842 if (ctx
->iaoq_n
== -1) {
1843 /* The temporary iaoq_n_var died at the branch above.
1844 Regenerate it here instead of saving it. */
1845 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
1847 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
1850 gen_set_label(taken
);
1852 /* Taken: Condition satisfied; nullify on forward branches. */
1853 n
= is_n
&& disp
>= 0;
1854 if (n
&& use_nullify_skip(ctx
)) {
1855 nullify_set(ctx
, 0);
1856 gen_goto_tb(ctx
, 1, dest
, dest
+ 4);
1858 nullify_set(ctx
, n
);
1859 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, dest
);
1862 /* Not taken: the branch itself was nullified. */
1863 if (ctx
->null_lab
) {
1864 gen_set_label(ctx
->null_lab
);
1865 ctx
->null_lab
= NULL
;
1866 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
1868 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1873 /* Emit an unconditional branch to an indirect target. This handles
1874 nullification of the branch itself. */
1875 static bool do_ibranch(DisasContext
*ctx
, TCGv_reg dest
,
1876 unsigned link
, bool is_n
)
1878 TCGv_reg a0
, a1
, next
, tmp
;
1881 assert(ctx
->null_lab
== NULL
);
1883 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
1885 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1887 next
= get_temp(ctx
);
1888 tcg_gen_mov_reg(next
, dest
);
1890 if (use_nullify_skip(ctx
)) {
1891 tcg_gen_mov_reg(cpu_iaoq_f
, next
);
1892 tcg_gen_addi_reg(cpu_iaoq_b
, next
, 4);
1893 nullify_set(ctx
, 0);
1894 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
1897 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1900 ctx
->iaoq_n_var
= next
;
1901 } else if (is_n
&& use_nullify_skip(ctx
)) {
1902 /* The (conditional) branch, B, nullifies the next insn, N,
1903 and we're allowed to skip execution N (no single-step or
1904 tracepoint in effect). Since the goto_ptr that we must use
1905 for the indirect branch consumes no special resources, we
1906 can (conditionally) skip B and continue execution. */
1907 /* The use_nullify_skip test implies we have a known control path. */
1908 tcg_debug_assert(ctx
->iaoq_b
!= -1);
1909 tcg_debug_assert(ctx
->iaoq_n
!= -1);
1911 /* We do have to handle the non-local temporary, DEST, before
1912 branching. Since IOAQ_F is not really live at this point, we
1913 can simply store DEST optimistically. Similarly with IAOQ_B. */
1914 tcg_gen_mov_reg(cpu_iaoq_f
, dest
);
1915 tcg_gen_addi_reg(cpu_iaoq_b
, dest
, 4);
1919 tcg_gen_movi_reg(cpu_gr
[link
], ctx
->iaoq_n
);
1921 tcg_gen_lookup_and_goto_ptr();
1922 return nullify_end(ctx
);
1924 c
= ctx
->null_cond
.c
;
1925 a0
= ctx
->null_cond
.a0
;
1926 a1
= ctx
->null_cond
.a1
;
1928 tmp
= tcg_temp_new();
1929 next
= get_temp(ctx
);
1931 copy_iaoq_entry(tmp
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1932 tcg_gen_movcond_reg(c
, next
, a0
, a1
, tmp
, dest
);
1934 ctx
->iaoq_n_var
= next
;
1937 tcg_gen_movcond_reg(c
, cpu_gr
[link
], a0
, a1
, cpu_gr
[link
], tmp
);
1941 /* The branch nullifies the next insn, which means the state of N
1942 after the branch is the inverse of the state of N that applied
1944 tcg_gen_setcond_reg(tcg_invert_cond(c
), cpu_psw_n
, a0
, a1
);
1945 cond_free(&ctx
->null_cond
);
1946 ctx
->null_cond
= cond_make_n();
1947 ctx
->psw_n_nonzero
= true;
1949 cond_free(&ctx
->null_cond
);
1956 * if (IAOQ_Front{30..31} < GR[b]{30..31})
1957 * IAOQ_Next{30..31} ← GR[b]{30..31};
1959 * IAOQ_Next{30..31} ← IAOQ_Front{30..31};
1960 * which keeps the privilege level from being increased.
1962 static TCGv_reg
do_ibranch_priv(DisasContext
*ctx
, TCGv_reg offset
)
1965 switch (ctx
->privilege
) {
1967 /* Privilege 0 is maximum and is allowed to decrease. */
1970 /* Privilege 3 is minimum and is never allowed to increase. */
1971 dest
= get_temp(ctx
);
1972 tcg_gen_ori_reg(dest
, offset
, 3);
1975 dest
= get_temp(ctx
);
1976 tcg_gen_andi_reg(dest
, offset
, -4);
1977 tcg_gen_ori_reg(dest
, dest
, ctx
->privilege
);
1978 tcg_gen_movcond_reg(TCG_COND_GTU
, dest
, dest
, offset
, dest
, offset
);
1984 #ifdef CONFIG_USER_ONLY
1985 /* On Linux, page zero is normally marked execute only + gateway.
1986 Therefore normal read or write is supposed to fail, but specific
1987 offsets have kernel code mapped to raise permissions to implement
1988 system calls. Handling this via an explicit check here, rather
1989 in than the "be disp(sr2,r0)" instruction that probably sent us
1990 here, is the easiest way to handle the branch delay slot on the
1991 aforementioned BE. */
1992 static void do_page_zero(DisasContext
*ctx
)
1994 /* If by some means we get here with PSW[N]=1, that implies that
1995 the B,GATE instruction would be skipped, and we'd fault on the
1996 next insn within the privilaged page. */
1997 switch (ctx
->null_cond
.c
) {
1998 case TCG_COND_NEVER
:
2000 case TCG_COND_ALWAYS
:
2001 tcg_gen_movi_reg(cpu_psw_n
, 0);
2004 /* Since this is always the first (and only) insn within the
2005 TB, we should know the state of PSW[N] from TB->FLAGS. */
2006 g_assert_not_reached();
2009 /* Check that we didn't arrive here via some means that allowed
2010 non-sequential instruction execution. Normally the PSW[B] bit
2011 detects this by disallowing the B,GATE instruction to execute
2012 under such conditions. */
2013 if (ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
2017 switch (ctx
->iaoq_f
& -4) {
2018 case 0x00: /* Null pointer call */
2019 gen_excp_1(EXCP_IMP
);
2020 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2023 case 0xb0: /* LWS */
2024 gen_excp_1(EXCP_SYSCALL_LWS
);
2025 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2028 case 0xe0: /* SET_THREAD_POINTER */
2029 tcg_gen_st_reg(cpu_gr
[26], cpu_env
, offsetof(CPUHPPAState
, cr
[27]));
2030 tcg_gen_ori_reg(cpu_iaoq_f
, cpu_gr
[31], 3);
2031 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
2032 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
2035 case 0x100: /* SYSCALL */
2036 gen_excp_1(EXCP_SYSCALL
);
2037 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2042 gen_excp_1(EXCP_ILL
);
2043 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2049 static bool trans_nop(DisasContext
*ctx
, arg_nop
*a
)
2051 cond_free(&ctx
->null_cond
);
2055 static bool trans_break(DisasContext
*ctx
, arg_break
*a
)
2057 return gen_excp_iir(ctx
, EXCP_BREAK
);
2060 static bool trans_sync(DisasContext
*ctx
, arg_sync
*a
)
2062 /* No point in nullifying the memory barrier. */
2063 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
2065 cond_free(&ctx
->null_cond
);
2069 static bool trans_mfia(DisasContext
*ctx
, arg_mfia
*a
)
2072 TCGv_reg tmp
= dest_gpr(ctx
, rt
);
2073 tcg_gen_movi_reg(tmp
, ctx
->iaoq_f
);
2074 save_gpr(ctx
, rt
, tmp
);
2076 cond_free(&ctx
->null_cond
);
2080 static bool trans_mfsp(DisasContext
*ctx
, arg_mfsp
*a
)
2083 unsigned rs
= a
->sp
;
2084 TCGv_i64 t0
= tcg_temp_new_i64();
2085 TCGv_reg t1
= tcg_temp_new();
2087 load_spr(ctx
, t0
, rs
);
2088 tcg_gen_shri_i64(t0
, t0
, 32);
2089 tcg_gen_trunc_i64_reg(t1
, t0
);
2091 save_gpr(ctx
, rt
, t1
);
2093 tcg_temp_free_i64(t0
);
2095 cond_free(&ctx
->null_cond
);
2099 static bool trans_mfctl(DisasContext
*ctx
, arg_mfctl
*a
)
2102 unsigned ctl
= a
->r
;
2107 #ifdef TARGET_HPPA64
2109 /* MFSAR without ,W masks low 5 bits. */
2110 tmp
= dest_gpr(ctx
, rt
);
2111 tcg_gen_andi_reg(tmp
, cpu_sar
, 31);
2112 save_gpr(ctx
, rt
, tmp
);
2116 save_gpr(ctx
, rt
, cpu_sar
);
2118 case CR_IT
: /* Interval Timer */
2119 /* FIXME: Respect PSW_S bit. */
2121 tmp
= dest_gpr(ctx
, rt
);
2122 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
2124 gen_helper_read_interval_timer(tmp
);
2125 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2127 gen_helper_read_interval_timer(tmp
);
2129 save_gpr(ctx
, rt
, tmp
);
2130 return nullify_end(ctx
);
2135 /* All other control registers are privileged. */
2136 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2140 tmp
= get_temp(ctx
);
2141 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2142 save_gpr(ctx
, rt
, tmp
);
2145 cond_free(&ctx
->null_cond
);
2149 static bool trans_mtsp(DisasContext
*ctx
, arg_mtsp
*a
)
2152 unsigned rs
= a
->sp
;
2156 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2160 t64
= tcg_temp_new_i64();
2161 tcg_gen_extu_reg_i64(t64
, load_gpr(ctx
, rr
));
2162 tcg_gen_shli_i64(t64
, t64
, 32);
2165 tcg_gen_st_i64(t64
, cpu_env
, offsetof(CPUHPPAState
, sr
[rs
]));
2166 ctx
->tb_flags
&= ~TB_FLAG_SR_SAME
;
2168 tcg_gen_mov_i64(cpu_sr
[rs
], t64
);
2170 tcg_temp_free_i64(t64
);
2172 return nullify_end(ctx
);
2175 static bool trans_mtctl(DisasContext
*ctx
, arg_mtctl
*a
)
2177 unsigned ctl
= a
->t
;
2181 if (ctl
== CR_SAR
) {
2182 reg
= load_gpr(ctx
, a
->r
);
2183 tmp
= tcg_temp_new();
2184 tcg_gen_andi_reg(tmp
, reg
, TARGET_REGISTER_BITS
- 1);
2185 save_or_nullify(ctx
, cpu_sar
, tmp
);
2188 cond_free(&ctx
->null_cond
);
2192 /* All other control registers are privileged or read-only. */
2193 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2195 #ifndef CONFIG_USER_ONLY
2197 reg
= load_gpr(ctx
, a
->r
);
2201 gen_helper_write_interval_timer(cpu_env
, reg
);
2204 gen_helper_write_eirr(cpu_env
, reg
);
2207 gen_helper_write_eiem(cpu_env
, reg
);
2208 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2213 /* FIXME: Respect PSW_Q bit */
2214 /* The write advances the queue and stores to the back element. */
2215 tmp
= get_temp(ctx
);
2216 tcg_gen_ld_reg(tmp
, cpu_env
,
2217 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2218 tcg_gen_st_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2219 tcg_gen_st_reg(reg
, cpu_env
,
2220 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2227 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2228 #ifndef CONFIG_USER_ONLY
2229 gen_helper_change_prot_id(cpu_env
);
2234 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2237 return nullify_end(ctx
);
2241 static bool trans_mtsarcm(DisasContext
*ctx
, arg_mtsarcm
*a
)
2243 TCGv_reg tmp
= tcg_temp_new();
2245 tcg_gen_not_reg(tmp
, load_gpr(ctx
, a
->r
));
2246 tcg_gen_andi_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
2247 save_or_nullify(ctx
, cpu_sar
, tmp
);
2250 cond_free(&ctx
->null_cond
);
2254 static bool trans_ldsid(DisasContext
*ctx
, arg_ldsid
*a
)
2256 TCGv_reg dest
= dest_gpr(ctx
, a
->t
);
2258 #ifdef CONFIG_USER_ONLY
2259 /* We don't implement space registers in user mode. */
2260 tcg_gen_movi_reg(dest
, 0);
2262 TCGv_i64 t0
= tcg_temp_new_i64();
2264 tcg_gen_mov_i64(t0
, space_select(ctx
, a
->sp
, load_gpr(ctx
, a
->b
)));
2265 tcg_gen_shri_i64(t0
, t0
, 32);
2266 tcg_gen_trunc_i64_reg(dest
, t0
);
2268 tcg_temp_free_i64(t0
);
2270 save_gpr(ctx
, a
->t
, dest
);
2272 cond_free(&ctx
->null_cond
);
2276 static bool trans_rsm(DisasContext
*ctx
, arg_rsm
*a
)
2278 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2279 #ifndef CONFIG_USER_ONLY
2284 tmp
= get_temp(ctx
);
2285 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2286 tcg_gen_andi_reg(tmp
, tmp
, ~a
->i
);
2287 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2288 save_gpr(ctx
, a
->t
, tmp
);
2290 /* Exit the TB to recognize new interrupts, e.g. PSW_M. */
2291 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2292 return nullify_end(ctx
);
2296 static bool trans_ssm(DisasContext
*ctx
, arg_ssm
*a
)
2298 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2299 #ifndef CONFIG_USER_ONLY
2304 tmp
= get_temp(ctx
);
2305 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2306 tcg_gen_ori_reg(tmp
, tmp
, a
->i
);
2307 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2308 save_gpr(ctx
, a
->t
, tmp
);
2310 /* Exit the TB to recognize new interrupts, e.g. PSW_I. */
2311 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2312 return nullify_end(ctx
);
2316 static bool trans_mtsm(DisasContext
*ctx
, arg_mtsm
*a
)
2318 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2319 #ifndef CONFIG_USER_ONLY
2323 reg
= load_gpr(ctx
, a
->r
);
2324 tmp
= get_temp(ctx
);
2325 gen_helper_swap_system_mask(tmp
, cpu_env
, reg
);
2327 /* Exit the TB to recognize new interrupts. */
2328 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2329 return nullify_end(ctx
);
2333 static bool do_rfi(DisasContext
*ctx
, bool rfi_r
)
2335 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2336 #ifndef CONFIG_USER_ONLY
2340 gen_helper_rfi_r(cpu_env
);
2342 gen_helper_rfi(cpu_env
);
2344 /* Exit the TB to recognize new interrupts. */
2345 tcg_gen_exit_tb(NULL
, 0);
2346 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2348 return nullify_end(ctx
);
2352 static bool trans_rfi(DisasContext
*ctx
, arg_rfi
*a
)
2354 return do_rfi(ctx
, false);
2357 static bool trans_rfi_r(DisasContext
*ctx
, arg_rfi_r
*a
)
2359 return do_rfi(ctx
, true);
2362 static bool trans_halt(DisasContext
*ctx
, arg_halt
*a
)
2364 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2365 #ifndef CONFIG_USER_ONLY
2367 gen_helper_halt(cpu_env
);
2368 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2369 return nullify_end(ctx
);
2373 static bool trans_reset(DisasContext
*ctx
, arg_reset
*a
)
2375 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2376 #ifndef CONFIG_USER_ONLY
2378 gen_helper_reset(cpu_env
);
2379 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2380 return nullify_end(ctx
);
2384 static bool trans_nop_addrx(DisasContext
*ctx
, arg_ldst
*a
)
2387 TCGv_reg dest
= dest_gpr(ctx
, a
->b
);
2388 TCGv_reg src1
= load_gpr(ctx
, a
->b
);
2389 TCGv_reg src2
= load_gpr(ctx
, a
->x
);
2391 /* The only thing we need to do is the base register modification. */
2392 tcg_gen_add_reg(dest
, src1
, src2
);
2393 save_gpr(ctx
, a
->b
, dest
);
2395 cond_free(&ctx
->null_cond
);
2399 static bool trans_probe(DisasContext
*ctx
, arg_probe
*a
)
2402 TCGv_i32 level
, want
;
2407 dest
= dest_gpr(ctx
, a
->t
);
2408 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2411 level
= tcg_constant_i32(a
->ri
);
2413 level
= tcg_temp_new_i32();
2414 tcg_gen_trunc_reg_i32(level
, load_gpr(ctx
, a
->ri
));
2415 tcg_gen_andi_i32(level
, level
, 3);
2417 want
= tcg_constant_i32(a
->write
? PAGE_WRITE
: PAGE_READ
);
2419 gen_helper_probe(dest
, cpu_env
, addr
, level
, want
);
2421 tcg_temp_free_i32(level
);
2423 save_gpr(ctx
, a
->t
, dest
);
2424 return nullify_end(ctx
);
2427 static bool trans_ixtlbx(DisasContext
*ctx
, arg_ixtlbx
*a
)
2429 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2430 #ifndef CONFIG_USER_ONLY
2436 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2437 reg
= load_gpr(ctx
, a
->r
);
2439 gen_helper_itlba(cpu_env
, addr
, reg
);
2441 gen_helper_itlbp(cpu_env
, addr
, reg
);
2444 /* Exit TB for TLB change if mmu is enabled. */
2445 if (ctx
->tb_flags
& PSW_C
) {
2446 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2448 return nullify_end(ctx
);
2452 static bool trans_pxtlbx(DisasContext
*ctx
, arg_pxtlbx
*a
)
2454 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2455 #ifndef CONFIG_USER_ONLY
2461 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2463 save_gpr(ctx
, a
->b
, ofs
);
2466 gen_helper_ptlbe(cpu_env
);
2468 gen_helper_ptlb(cpu_env
, addr
);
2471 /* Exit TB for TLB change if mmu is enabled. */
2472 if (ctx
->tb_flags
& PSW_C
) {
2473 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2475 return nullify_end(ctx
);
2480 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2482 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2483 * page 13-9 (195/206)
2485 static bool trans_ixtlbxf(DisasContext
*ctx
, arg_ixtlbxf
*a
)
2487 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2488 #ifndef CONFIG_USER_ONLY
2489 TCGv_tl addr
, atl
, stl
;
2496 * if (not (pcxl or pcxl2))
2497 * return gen_illegal(ctx);
2499 * Note for future: these are 32-bit systems; no hppa64.
2502 atl
= tcg_temp_new_tl();
2503 stl
= tcg_temp_new_tl();
2504 addr
= tcg_temp_new_tl();
2506 tcg_gen_ld32u_i64(stl
, cpu_env
,
2507 a
->data
? offsetof(CPUHPPAState
, cr
[CR_ISR
])
2508 : offsetof(CPUHPPAState
, cr
[CR_IIASQ
]));
2509 tcg_gen_ld32u_i64(atl
, cpu_env
,
2510 a
->data
? offsetof(CPUHPPAState
, cr
[CR_IOR
])
2511 : offsetof(CPUHPPAState
, cr
[CR_IIAOQ
]));
2512 tcg_gen_shli_i64(stl
, stl
, 32);
2513 tcg_gen_or_tl(addr
, atl
, stl
);
2514 tcg_temp_free_tl(atl
);
2515 tcg_temp_free_tl(stl
);
2517 reg
= load_gpr(ctx
, a
->r
);
2519 gen_helper_itlba(cpu_env
, addr
, reg
);
2521 gen_helper_itlbp(cpu_env
, addr
, reg
);
2523 tcg_temp_free_tl(addr
);
2525 /* Exit TB for TLB change if mmu is enabled. */
2526 if (ctx
->tb_flags
& PSW_C
) {
2527 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2529 return nullify_end(ctx
);
2533 static bool trans_lpa(DisasContext
*ctx
, arg_ldst
*a
)
2535 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2536 #ifndef CONFIG_USER_ONLY
2538 TCGv_reg ofs
, paddr
;
2542 form_gva(ctx
, &vaddr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2544 paddr
= tcg_temp_new();
2545 gen_helper_lpa(paddr
, cpu_env
, vaddr
);
2547 /* Note that physical address result overrides base modification. */
2549 save_gpr(ctx
, a
->b
, ofs
);
2551 save_gpr(ctx
, a
->t
, paddr
);
2552 tcg_temp_free(paddr
);
2554 return nullify_end(ctx
);
2558 static bool trans_lci(DisasContext
*ctx
, arg_lci
*a
)
2560 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2562 /* The Coherence Index is an implementation-defined function of the
2563 physical address. Two addresses with the same CI have a coherent
2564 view of the cache. Our implementation is to return 0 for all,
2565 since the entire address space is coherent. */
2566 save_gpr(ctx
, a
->t
, tcg_constant_reg(0));
2568 cond_free(&ctx
->null_cond
);
2572 static bool trans_add(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2574 return do_add_reg(ctx
, a
, false, false, false, false);
2577 static bool trans_add_l(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2579 return do_add_reg(ctx
, a
, true, false, false, false);
2582 static bool trans_add_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2584 return do_add_reg(ctx
, a
, false, true, false, false);
2587 static bool trans_add_c(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2589 return do_add_reg(ctx
, a
, false, false, false, true);
2592 static bool trans_add_c_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2594 return do_add_reg(ctx
, a
, false, true, false, true);
2597 static bool trans_sub(DisasContext
*ctx
, arg_rrr_cf
*a
)
2599 return do_sub_reg(ctx
, a
, false, false, false);
2602 static bool trans_sub_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2604 return do_sub_reg(ctx
, a
, true, false, false);
2607 static bool trans_sub_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2609 return do_sub_reg(ctx
, a
, false, false, true);
2612 static bool trans_sub_tsv_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2614 return do_sub_reg(ctx
, a
, true, false, true);
2617 static bool trans_sub_b(DisasContext
*ctx
, arg_rrr_cf
*a
)
2619 return do_sub_reg(ctx
, a
, false, true, false);
2622 static bool trans_sub_b_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2624 return do_sub_reg(ctx
, a
, true, true, false);
2627 static bool trans_andcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2629 return do_log_reg(ctx
, a
, tcg_gen_andc_reg
);
2632 static bool trans_and(DisasContext
*ctx
, arg_rrr_cf
*a
)
2634 return do_log_reg(ctx
, a
, tcg_gen_and_reg
);
2637 static bool trans_or(DisasContext
*ctx
, arg_rrr_cf
*a
)
2640 unsigned r2
= a
->r2
;
2641 unsigned r1
= a
->r1
;
2644 if (rt
== 0) { /* NOP */
2645 cond_free(&ctx
->null_cond
);
2648 if (r2
== 0) { /* COPY */
2650 TCGv_reg dest
= dest_gpr(ctx
, rt
);
2651 tcg_gen_movi_reg(dest
, 0);
2652 save_gpr(ctx
, rt
, dest
);
2654 save_gpr(ctx
, rt
, cpu_gr
[r1
]);
2656 cond_free(&ctx
->null_cond
);
2659 #ifndef CONFIG_USER_ONLY
2660 /* These are QEMU extensions and are nops in the real architecture:
2662 * or %r10,%r10,%r10 -- idle loop; wait for interrupt
2663 * or %r31,%r31,%r31 -- death loop; offline cpu
2664 * currently implemented as idle.
2666 if ((rt
== 10 || rt
== 31) && r1
== rt
&& r2
== rt
) { /* PAUSE */
2667 /* No need to check for supervisor, as userland can only pause
2668 until the next timer interrupt. */
2671 /* Advance the instruction queue. */
2672 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
2673 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
2674 nullify_set(ctx
, 0);
2676 /* Tell the qemu main loop to halt until this cpu has work. */
2677 tcg_gen_st_i32(tcg_constant_i32(1), cpu_env
,
2678 offsetof(CPUState
, halted
) - offsetof(HPPACPU
, env
));
2679 gen_excp_1(EXCP_HALTED
);
2680 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2682 return nullify_end(ctx
);
2686 return do_log_reg(ctx
, a
, tcg_gen_or_reg
);
2689 static bool trans_xor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2691 return do_log_reg(ctx
, a
, tcg_gen_xor_reg
);
2694 static bool trans_cmpclr(DisasContext
*ctx
, arg_rrr_cf
*a
)
2696 TCGv_reg tcg_r1
, tcg_r2
;
2701 tcg_r1
= load_gpr(ctx
, a
->r1
);
2702 tcg_r2
= load_gpr(ctx
, a
->r2
);
2703 do_cmpclr(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
);
2704 return nullify_end(ctx
);
2707 static bool trans_uxor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2709 TCGv_reg tcg_r1
, tcg_r2
;
2714 tcg_r1
= load_gpr(ctx
, a
->r1
);
2715 tcg_r2
= load_gpr(ctx
, a
->r2
);
2716 do_unit(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, false, tcg_gen_xor_reg
);
2717 return nullify_end(ctx
);
2720 static bool do_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
, bool is_tc
)
2722 TCGv_reg tcg_r1
, tcg_r2
, tmp
;
2727 tcg_r1
= load_gpr(ctx
, a
->r1
);
2728 tcg_r2
= load_gpr(ctx
, a
->r2
);
2729 tmp
= get_temp(ctx
);
2730 tcg_gen_not_reg(tmp
, tcg_r2
);
2731 do_unit(ctx
, a
->t
, tcg_r1
, tmp
, a
->cf
, is_tc
, tcg_gen_add_reg
);
2732 return nullify_end(ctx
);
2735 static bool trans_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2737 return do_uaddcm(ctx
, a
, false);
2740 static bool trans_uaddcm_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2742 return do_uaddcm(ctx
, a
, true);
2745 static bool do_dcor(DisasContext
*ctx
, arg_rr_cf
*a
, bool is_i
)
2751 tmp
= get_temp(ctx
);
2752 tcg_gen_shri_reg(tmp
, cpu_psw_cb
, 3);
2754 tcg_gen_not_reg(tmp
, tmp
);
2756 tcg_gen_andi_reg(tmp
, tmp
, 0x11111111);
2757 tcg_gen_muli_reg(tmp
, tmp
, 6);
2758 do_unit(ctx
, a
->t
, load_gpr(ctx
, a
->r
), tmp
, a
->cf
, false,
2759 is_i
? tcg_gen_add_reg
: tcg_gen_sub_reg
);
2760 return nullify_end(ctx
);
2763 static bool trans_dcor(DisasContext
*ctx
, arg_rr_cf
*a
)
2765 return do_dcor(ctx
, a
, false);
2768 static bool trans_dcor_i(DisasContext
*ctx
, arg_rr_cf
*a
)
2770 return do_dcor(ctx
, a
, true);
2773 static bool trans_ds(DisasContext
*ctx
, arg_rrr_cf
*a
)
2775 TCGv_reg dest
, add1
, add2
, addc
, zero
, in1
, in2
;
2779 in1
= load_gpr(ctx
, a
->r1
);
2780 in2
= load_gpr(ctx
, a
->r2
);
2782 add1
= tcg_temp_new();
2783 add2
= tcg_temp_new();
2784 addc
= tcg_temp_new();
2785 dest
= tcg_temp_new();
2786 zero
= tcg_constant_reg(0);
2788 /* Form R1 << 1 | PSW[CB]{8}. */
2789 tcg_gen_add_reg(add1
, in1
, in1
);
2790 tcg_gen_add_reg(add1
, add1
, cpu_psw_cb_msb
);
2792 /* Add or subtract R2, depending on PSW[V]. Proper computation of
2793 carry{8} requires that we subtract via + ~R2 + 1, as described in
2794 the manual. By extracting and masking V, we can produce the
2795 proper inputs to the addition without movcond. */
2796 tcg_gen_sari_reg(addc
, cpu_psw_v
, TARGET_REGISTER_BITS
- 1);
2797 tcg_gen_xor_reg(add2
, in2
, addc
);
2798 tcg_gen_andi_reg(addc
, addc
, 1);
2799 /* ??? This is only correct for 32-bit. */
2800 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, add1
, zero
, add2
, zero
);
2801 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, dest
, cpu_psw_cb_msb
, addc
, zero
);
2803 tcg_temp_free(addc
);
2805 /* Write back the result register. */
2806 save_gpr(ctx
, a
->t
, dest
);
2808 /* Write back PSW[CB]. */
2809 tcg_gen_xor_reg(cpu_psw_cb
, add1
, add2
);
2810 tcg_gen_xor_reg(cpu_psw_cb
, cpu_psw_cb
, dest
);
2812 /* Write back PSW[V] for the division step. */
2813 tcg_gen_neg_reg(cpu_psw_v
, cpu_psw_cb_msb
);
2814 tcg_gen_xor_reg(cpu_psw_v
, cpu_psw_v
, in2
);
2816 /* Install the new nullification. */
2819 if (cond_need_sv(a
->cf
>> 1)) {
2820 /* ??? The lshift is supposed to contribute to overflow. */
2821 sv
= do_add_sv(ctx
, dest
, add1
, add2
);
2823 ctx
->null_cond
= do_cond(a
->cf
, dest
, cpu_psw_cb_msb
, sv
);
2826 tcg_temp_free(add1
);
2827 tcg_temp_free(add2
);
2828 tcg_temp_free(dest
);
2830 return nullify_end(ctx
);
2833 static bool trans_addi(DisasContext
*ctx
, arg_rri_cf
*a
)
2835 return do_add_imm(ctx
, a
, false, false);
2838 static bool trans_addi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2840 return do_add_imm(ctx
, a
, true, false);
2843 static bool trans_addi_tc(DisasContext
*ctx
, arg_rri_cf
*a
)
2845 return do_add_imm(ctx
, a
, false, true);
2848 static bool trans_addi_tc_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2850 return do_add_imm(ctx
, a
, true, true);
2853 static bool trans_subi(DisasContext
*ctx
, arg_rri_cf
*a
)
2855 return do_sub_imm(ctx
, a
, false);
2858 static bool trans_subi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2860 return do_sub_imm(ctx
, a
, true);
2863 static bool trans_cmpiclr(DisasContext
*ctx
, arg_rri_cf
*a
)
2865 TCGv_reg tcg_im
, tcg_r2
;
2871 tcg_im
= load_const(ctx
, a
->i
);
2872 tcg_r2
= load_gpr(ctx
, a
->r
);
2873 do_cmpclr(ctx
, a
->t
, tcg_im
, tcg_r2
, a
->cf
);
2875 return nullify_end(ctx
);
2878 static bool trans_ld(DisasContext
*ctx
, arg_ldst
*a
)
2880 return do_load(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2881 a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2884 static bool trans_st(DisasContext
*ctx
, arg_ldst
*a
)
2886 assert(a
->x
== 0 && a
->scale
== 0);
2887 return do_store(ctx
, a
->t
, a
->b
, a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2890 static bool trans_ldc(DisasContext
*ctx
, arg_ldst
*a
)
2892 MemOp mop
= MO_TE
| MO_ALIGN
| a
->size
;
2893 TCGv_reg zero
, dest
, ofs
;
2899 /* Base register modification. Make sure if RT == RB,
2900 we see the result of the load. */
2901 dest
= get_temp(ctx
);
2903 dest
= dest_gpr(ctx
, a
->t
);
2906 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2907 a
->disp
, a
->sp
, a
->m
, ctx
->mmu_idx
== MMU_PHYS_IDX
);
2910 * For hppa1.1, LDCW is undefined unless aligned mod 16.
2911 * However actual hardware succeeds with aligned mod 4.
2912 * Detect this case and log a GUEST_ERROR.
2914 * TODO: HPPA64 relaxes the over-alignment requirement
2915 * with the ,co completer.
2917 gen_helper_ldc_check(addr
);
2919 zero
= tcg_constant_reg(0);
2920 tcg_gen_atomic_xchg_reg(dest
, addr
, zero
, ctx
->mmu_idx
, mop
);
2923 save_gpr(ctx
, a
->b
, ofs
);
2925 save_gpr(ctx
, a
->t
, dest
);
2927 return nullify_end(ctx
);
2930 static bool trans_stby(DisasContext
*ctx
, arg_stby
*a
)
2937 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, a
->disp
, a
->sp
, a
->m
,
2938 ctx
->mmu_idx
== MMU_PHYS_IDX
);
2939 val
= load_gpr(ctx
, a
->r
);
2941 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2942 gen_helper_stby_e_parallel(cpu_env
, addr
, val
);
2944 gen_helper_stby_e(cpu_env
, addr
, val
);
2947 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2948 gen_helper_stby_b_parallel(cpu_env
, addr
, val
);
2950 gen_helper_stby_b(cpu_env
, addr
, val
);
2954 tcg_gen_andi_reg(ofs
, ofs
, ~3);
2955 save_gpr(ctx
, a
->b
, ofs
);
2958 return nullify_end(ctx
);
2961 static bool trans_lda(DisasContext
*ctx
, arg_ldst
*a
)
2963 int hold_mmu_idx
= ctx
->mmu_idx
;
2965 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2966 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2968 ctx
->mmu_idx
= hold_mmu_idx
;
2972 static bool trans_sta(DisasContext
*ctx
, arg_ldst
*a
)
2974 int hold_mmu_idx
= ctx
->mmu_idx
;
2976 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2977 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2979 ctx
->mmu_idx
= hold_mmu_idx
;
2983 static bool trans_ldil(DisasContext
*ctx
, arg_ldil
*a
)
2985 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
2987 tcg_gen_movi_reg(tcg_rt
, a
->i
);
2988 save_gpr(ctx
, a
->t
, tcg_rt
);
2989 cond_free(&ctx
->null_cond
);
2993 static bool trans_addil(DisasContext
*ctx
, arg_addil
*a
)
2995 TCGv_reg tcg_rt
= load_gpr(ctx
, a
->r
);
2996 TCGv_reg tcg_r1
= dest_gpr(ctx
, 1);
2998 tcg_gen_addi_reg(tcg_r1
, tcg_rt
, a
->i
);
2999 save_gpr(ctx
, 1, tcg_r1
);
3000 cond_free(&ctx
->null_cond
);
3004 static bool trans_ldo(DisasContext
*ctx
, arg_ldo
*a
)
3006 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
3008 /* Special case rb == 0, for the LDI pseudo-op.
3009 The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
3011 tcg_gen_movi_reg(tcg_rt
, a
->i
);
3013 tcg_gen_addi_reg(tcg_rt
, cpu_gr
[a
->b
], a
->i
);
3015 save_gpr(ctx
, a
->t
, tcg_rt
);
3016 cond_free(&ctx
->null_cond
);
3020 static bool do_cmpb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3021 unsigned c
, unsigned f
, unsigned n
, int disp
)
3023 TCGv_reg dest
, in2
, sv
;
3026 in2
= load_gpr(ctx
, r
);
3027 dest
= get_temp(ctx
);
3029 tcg_gen_sub_reg(dest
, in1
, in2
);
3032 if (cond_need_sv(c
)) {
3033 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
3036 cond
= do_sub_cond(c
* 2 + f
, dest
, in1
, in2
, sv
);
3037 return do_cbranch(ctx
, disp
, n
, &cond
);
3040 static bool trans_cmpb(DisasContext
*ctx
, arg_cmpb
*a
)
3043 return do_cmpb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3046 static bool trans_cmpbi(DisasContext
*ctx
, arg_cmpbi
*a
)
3049 return do_cmpb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3052 static bool do_addb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3053 unsigned c
, unsigned f
, unsigned n
, int disp
)
3055 TCGv_reg dest
, in2
, sv
, cb_msb
;
3058 in2
= load_gpr(ctx
, r
);
3059 dest
= tcg_temp_new();
3063 if (cond_need_cb(c
)) {
3064 cb_msb
= get_temp(ctx
);
3065 tcg_gen_movi_reg(cb_msb
, 0);
3066 tcg_gen_add2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, cb_msb
);
3068 tcg_gen_add_reg(dest
, in1
, in2
);
3070 if (cond_need_sv(c
)) {
3071 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
3074 cond
= do_cond(c
* 2 + f
, dest
, cb_msb
, sv
);
3075 save_gpr(ctx
, r
, dest
);
3076 tcg_temp_free(dest
);
3077 return do_cbranch(ctx
, disp
, n
, &cond
);
3080 static bool trans_addb(DisasContext
*ctx
, arg_addb
*a
)
3083 return do_addb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3086 static bool trans_addbi(DisasContext
*ctx
, arg_addbi
*a
)
3089 return do_addb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3092 static bool trans_bb_sar(DisasContext
*ctx
, arg_bb_sar
*a
)
3094 TCGv_reg tmp
, tcg_r
;
3099 tmp
= tcg_temp_new();
3100 tcg_r
= load_gpr(ctx
, a
->r
);
3101 tcg_gen_shl_reg(tmp
, tcg_r
, cpu_sar
);
3103 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3105 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3108 static bool trans_bb_imm(DisasContext
*ctx
, arg_bb_imm
*a
)
3110 TCGv_reg tmp
, tcg_r
;
3115 tmp
= tcg_temp_new();
3116 tcg_r
= load_gpr(ctx
, a
->r
);
3117 tcg_gen_shli_reg(tmp
, tcg_r
, a
->p
);
3119 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3121 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3124 static bool trans_movb(DisasContext
*ctx
, arg_movb
*a
)
3131 dest
= dest_gpr(ctx
, a
->r2
);
3133 tcg_gen_movi_reg(dest
, 0);
3135 tcg_gen_mov_reg(dest
, cpu_gr
[a
->r1
]);
3138 cond
= do_sed_cond(a
->c
, dest
);
3139 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3142 static bool trans_movbi(DisasContext
*ctx
, arg_movbi
*a
)
3149 dest
= dest_gpr(ctx
, a
->r
);
3150 tcg_gen_movi_reg(dest
, a
->i
);
3152 cond
= do_sed_cond(a
->c
, dest
);
3153 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3156 static bool trans_shrpw_sar(DisasContext
*ctx
, arg_shrpw_sar
*a
)
3164 dest
= dest_gpr(ctx
, a
->t
);
3166 tcg_gen_ext32u_reg(dest
, load_gpr(ctx
, a
->r2
));
3167 tcg_gen_shr_reg(dest
, dest
, cpu_sar
);
3168 } else if (a
->r1
== a
->r2
) {
3169 TCGv_i32 t32
= tcg_temp_new_i32();
3170 tcg_gen_trunc_reg_i32(t32
, load_gpr(ctx
, a
->r2
));
3171 tcg_gen_rotr_i32(t32
, t32
, cpu_sar
);
3172 tcg_gen_extu_i32_reg(dest
, t32
);
3173 tcg_temp_free_i32(t32
);
3175 TCGv_i64 t
= tcg_temp_new_i64();
3176 TCGv_i64 s
= tcg_temp_new_i64();
3178 tcg_gen_concat_reg_i64(t
, load_gpr(ctx
, a
->r2
), load_gpr(ctx
, a
->r1
));
3179 tcg_gen_extu_reg_i64(s
, cpu_sar
);
3180 tcg_gen_shr_i64(t
, t
, s
);
3181 tcg_gen_trunc_i64_reg(dest
, t
);
3183 tcg_temp_free_i64(t
);
3184 tcg_temp_free_i64(s
);
3186 save_gpr(ctx
, a
->t
, dest
);
3188 /* Install the new nullification. */
3189 cond_free(&ctx
->null_cond
);
3191 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3193 return nullify_end(ctx
);
3196 static bool trans_shrpw_imm(DisasContext
*ctx
, arg_shrpw_imm
*a
)
3198 unsigned sa
= 31 - a
->cpos
;
3205 dest
= dest_gpr(ctx
, a
->t
);
3206 t2
= load_gpr(ctx
, a
->r2
);
3207 if (a
->r1
== a
->r2
) {
3208 TCGv_i32 t32
= tcg_temp_new_i32();
3209 tcg_gen_trunc_reg_i32(t32
, t2
);
3210 tcg_gen_rotri_i32(t32
, t32
, sa
);
3211 tcg_gen_extu_i32_reg(dest
, t32
);
3212 tcg_temp_free_i32(t32
);
3213 } else if (a
->r1
== 0) {
3214 tcg_gen_extract_reg(dest
, t2
, sa
, 32 - sa
);
3216 TCGv_reg t0
= tcg_temp_new();
3217 tcg_gen_extract_reg(t0
, t2
, sa
, 32 - sa
);
3218 tcg_gen_deposit_reg(dest
, t0
, cpu_gr
[a
->r1
], 32 - sa
, sa
);
3221 save_gpr(ctx
, a
->t
, dest
);
3223 /* Install the new nullification. */
3224 cond_free(&ctx
->null_cond
);
3226 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3228 return nullify_end(ctx
);
3231 static bool trans_extrw_sar(DisasContext
*ctx
, arg_extrw_sar
*a
)
3233 unsigned len
= 32 - a
->clen
;
3234 TCGv_reg dest
, src
, tmp
;
3240 dest
= dest_gpr(ctx
, a
->t
);
3241 src
= load_gpr(ctx
, a
->r
);
3242 tmp
= tcg_temp_new();
3244 /* Recall that SAR is using big-endian bit numbering. */
3245 tcg_gen_xori_reg(tmp
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3247 tcg_gen_sar_reg(dest
, src
, tmp
);
3248 tcg_gen_sextract_reg(dest
, dest
, 0, len
);
3250 tcg_gen_shr_reg(dest
, src
, tmp
);
3251 tcg_gen_extract_reg(dest
, dest
, 0, len
);
3254 save_gpr(ctx
, a
->t
, dest
);
3256 /* Install the new nullification. */
3257 cond_free(&ctx
->null_cond
);
3259 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3261 return nullify_end(ctx
);
3264 static bool trans_extrw_imm(DisasContext
*ctx
, arg_extrw_imm
*a
)
3266 unsigned len
= 32 - a
->clen
;
3267 unsigned cpos
= 31 - a
->pos
;
3274 dest
= dest_gpr(ctx
, a
->t
);
3275 src
= load_gpr(ctx
, a
->r
);
3277 tcg_gen_sextract_reg(dest
, src
, cpos
, len
);
3279 tcg_gen_extract_reg(dest
, src
, cpos
, len
);
3281 save_gpr(ctx
, a
->t
, dest
);
3283 /* Install the new nullification. */
3284 cond_free(&ctx
->null_cond
);
3286 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3288 return nullify_end(ctx
);
3291 static bool trans_depwi_imm(DisasContext
*ctx
, arg_depwi_imm
*a
)
3293 unsigned len
= 32 - a
->clen
;
3294 target_sreg mask0
, mask1
;
3300 if (a
->cpos
+ len
> 32) {
3304 dest
= dest_gpr(ctx
, a
->t
);
3305 mask0
= deposit64(0, a
->cpos
, len
, a
->i
);
3306 mask1
= deposit64(-1, a
->cpos
, len
, a
->i
);
3309 TCGv_reg src
= load_gpr(ctx
, a
->t
);
3311 tcg_gen_andi_reg(dest
, src
, mask1
);
3314 tcg_gen_ori_reg(dest
, src
, mask0
);
3316 tcg_gen_movi_reg(dest
, mask0
);
3318 save_gpr(ctx
, a
->t
, dest
);
3320 /* Install the new nullification. */
3321 cond_free(&ctx
->null_cond
);
3323 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3325 return nullify_end(ctx
);
3328 static bool trans_depw_imm(DisasContext
*ctx
, arg_depw_imm
*a
)
3330 unsigned rs
= a
->nz
? a
->t
: 0;
3331 unsigned len
= 32 - a
->clen
;
3337 if (a
->cpos
+ len
> 32) {
3341 dest
= dest_gpr(ctx
, a
->t
);
3342 val
= load_gpr(ctx
, a
->r
);
3344 tcg_gen_deposit_z_reg(dest
, val
, a
->cpos
, len
);
3346 tcg_gen_deposit_reg(dest
, cpu_gr
[rs
], val
, a
->cpos
, len
);
3348 save_gpr(ctx
, a
->t
, dest
);
3350 /* Install the new nullification. */
3351 cond_free(&ctx
->null_cond
);
3353 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3355 return nullify_end(ctx
);
3358 static bool do_depw_sar(DisasContext
*ctx
, unsigned rt
, unsigned c
,
3359 unsigned nz
, unsigned clen
, TCGv_reg val
)
3361 unsigned rs
= nz
? rt
: 0;
3362 unsigned len
= 32 - clen
;
3363 TCGv_reg mask
, tmp
, shift
, dest
;
3364 unsigned msb
= 1U << (len
- 1);
3366 dest
= dest_gpr(ctx
, rt
);
3367 shift
= tcg_temp_new();
3368 tmp
= tcg_temp_new();
3370 /* Convert big-endian bit numbering in SAR to left-shift. */
3371 tcg_gen_xori_reg(shift
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3373 mask
= tcg_const_reg(msb
+ (msb
- 1));
3374 tcg_gen_and_reg(tmp
, val
, mask
);
3376 tcg_gen_shl_reg(mask
, mask
, shift
);
3377 tcg_gen_shl_reg(tmp
, tmp
, shift
);
3378 tcg_gen_andc_reg(dest
, cpu_gr
[rs
], mask
);
3379 tcg_gen_or_reg(dest
, dest
, tmp
);
3381 tcg_gen_shl_reg(dest
, tmp
, shift
);
3383 tcg_temp_free(shift
);
3384 tcg_temp_free(mask
);
3386 save_gpr(ctx
, rt
, dest
);
3388 /* Install the new nullification. */
3389 cond_free(&ctx
->null_cond
);
3391 ctx
->null_cond
= do_sed_cond(c
, dest
);
3393 return nullify_end(ctx
);
3396 static bool trans_depw_sar(DisasContext
*ctx
, arg_depw_sar
*a
)
3401 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_gpr(ctx
, a
->r
));
3404 static bool trans_depwi_sar(DisasContext
*ctx
, arg_depwi_sar
*a
)
3409 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_const(ctx
, a
->i
));
3412 static bool trans_be(DisasContext
*ctx
, arg_be
*a
)
3416 #ifdef CONFIG_USER_ONLY
3417 /* ??? It seems like there should be a good way of using
3418 "be disp(sr2, r0)", the canonical gateway entry mechanism
3419 to our advantage. But that appears to be inconvenient to
3420 manage along side branch delay slots. Therefore we handle
3421 entry into the gateway page via absolute address. */
3422 /* Since we don't implement spaces, just branch. Do notice the special
3423 case of "be disp(*,r0)" using a direct branch to disp, so that we can
3424 goto_tb to the TB containing the syscall. */
3426 return do_dbranch(ctx
, a
->disp
, a
->l
, a
->n
);
3432 tmp
= get_temp(ctx
);
3433 tcg_gen_addi_reg(tmp
, load_gpr(ctx
, a
->b
), a
->disp
);
3434 tmp
= do_ibranch_priv(ctx
, tmp
);
3436 #ifdef CONFIG_USER_ONLY
3437 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3439 TCGv_i64 new_spc
= tcg_temp_new_i64();
3441 load_spr(ctx
, new_spc
, a
->sp
);
3443 copy_iaoq_entry(cpu_gr
[31], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3444 tcg_gen_mov_i64(cpu_sr
[0], cpu_iasq_f
);
3446 if (a
->n
&& use_nullify_skip(ctx
)) {
3447 tcg_gen_mov_reg(cpu_iaoq_f
, tmp
);
3448 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
3449 tcg_gen_mov_i64(cpu_iasq_f
, new_spc
);
3450 tcg_gen_mov_i64(cpu_iasq_b
, cpu_iasq_f
);
3452 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3453 if (ctx
->iaoq_b
== -1) {
3454 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3456 tcg_gen_mov_reg(cpu_iaoq_b
, tmp
);
3457 tcg_gen_mov_i64(cpu_iasq_b
, new_spc
);
3458 nullify_set(ctx
, a
->n
);
3460 tcg_temp_free_i64(new_spc
);
3461 tcg_gen_lookup_and_goto_ptr();
3462 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3463 return nullify_end(ctx
);
3467 static bool trans_bl(DisasContext
*ctx
, arg_bl
*a
)
3469 return do_dbranch(ctx
, iaoq_dest(ctx
, a
->disp
), a
->l
, a
->n
);
3472 static bool trans_b_gate(DisasContext
*ctx
, arg_b_gate
*a
)
3474 target_ureg dest
= iaoq_dest(ctx
, a
->disp
);
3478 /* Make sure the caller hasn't done something weird with the queue.
3479 * ??? This is not quite the same as the PSW[B] bit, which would be
3480 * expensive to track. Real hardware will trap for
3482 * b gateway+4 (in delay slot of first branch)
3483 * However, checking for a non-sequential instruction queue *will*
3484 * diagnose the security hole
3487 * in which instructions at evil would run with increased privs.
3489 if (ctx
->iaoq_b
== -1 || ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
3490 return gen_illegal(ctx
);
3493 #ifndef CONFIG_USER_ONLY
3494 if (ctx
->tb_flags
& PSW_C
) {
3495 CPUHPPAState
*env
= ctx
->cs
->env_ptr
;
3496 int type
= hppa_artype_for_page(env
, ctx
->base
.pc_next
);
3497 /* If we could not find a TLB entry, then we need to generate an
3498 ITLB miss exception so the kernel will provide it.
3499 The resulting TLB fill operation will invalidate this TB and
3500 we will re-translate, at which point we *will* be able to find
3501 the TLB entry and determine if this is in fact a gateway page. */
3503 gen_excp(ctx
, EXCP_ITLB_MISS
);
3506 /* No change for non-gateway pages or for priv decrease. */
3507 if (type
>= 4 && type
- 4 < ctx
->privilege
) {
3508 dest
= deposit32(dest
, 0, 2, type
- 4);
3511 dest
&= -4; /* priv = 0 */
3516 TCGv_reg tmp
= dest_gpr(ctx
, a
->l
);
3517 if (ctx
->privilege
< 3) {
3518 tcg_gen_andi_reg(tmp
, tmp
, -4);
3520 tcg_gen_ori_reg(tmp
, tmp
, ctx
->privilege
);
3521 save_gpr(ctx
, a
->l
, tmp
);
3524 return do_dbranch(ctx
, dest
, 0, a
->n
);
3527 static bool trans_blr(DisasContext
*ctx
, arg_blr
*a
)
3530 TCGv_reg tmp
= get_temp(ctx
);
3531 tcg_gen_shli_reg(tmp
, load_gpr(ctx
, a
->x
), 3);
3532 tcg_gen_addi_reg(tmp
, tmp
, ctx
->iaoq_f
+ 8);
3533 /* The computation here never changes privilege level. */
3534 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3536 /* BLR R0,RX is a good way to load PC+8 into RX. */
3537 return do_dbranch(ctx
, ctx
->iaoq_f
+ 8, a
->l
, a
->n
);
3541 static bool trans_bv(DisasContext
*ctx
, arg_bv
*a
)
3546 dest
= load_gpr(ctx
, a
->b
);
3548 dest
= get_temp(ctx
);
3549 tcg_gen_shli_reg(dest
, load_gpr(ctx
, a
->x
), 3);
3550 tcg_gen_add_reg(dest
, dest
, load_gpr(ctx
, a
->b
));
3552 dest
= do_ibranch_priv(ctx
, dest
);
3553 return do_ibranch(ctx
, dest
, 0, a
->n
);
3556 static bool trans_bve(DisasContext
*ctx
, arg_bve
*a
)
3560 #ifdef CONFIG_USER_ONLY
3561 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3562 return do_ibranch(ctx
, dest
, a
->l
, a
->n
);
3565 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3567 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3568 if (ctx
->iaoq_b
== -1) {
3569 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3571 copy_iaoq_entry(cpu_iaoq_b
, -1, dest
);
3572 tcg_gen_mov_i64(cpu_iasq_b
, space_select(ctx
, 0, dest
));
3574 copy_iaoq_entry(cpu_gr
[a
->l
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3576 nullify_set(ctx
, a
->n
);
3577 tcg_gen_lookup_and_goto_ptr();
3578 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3579 return nullify_end(ctx
);
3587 static void gen_fcpy_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3589 tcg_gen_mov_i32(dst
, src
);
3592 static bool trans_fcpy_f(DisasContext
*ctx
, arg_fclass01
*a
)
3594 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fcpy_f
);
3597 static void gen_fcpy_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3599 tcg_gen_mov_i64(dst
, src
);
3602 static bool trans_fcpy_d(DisasContext
*ctx
, arg_fclass01
*a
)
3604 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fcpy_d
);
3607 static void gen_fabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3609 tcg_gen_andi_i32(dst
, src
, INT32_MAX
);
3612 static bool trans_fabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3614 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fabs_f
);
3617 static void gen_fabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3619 tcg_gen_andi_i64(dst
, src
, INT64_MAX
);
3622 static bool trans_fabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3624 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fabs_d
);
3627 static bool trans_fsqrt_f(DisasContext
*ctx
, arg_fclass01
*a
)
3629 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_s
);
3632 static bool trans_fsqrt_d(DisasContext
*ctx
, arg_fclass01
*a
)
3634 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_d
);
3637 static bool trans_frnd_f(DisasContext
*ctx
, arg_fclass01
*a
)
3639 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_frnd_s
);
3642 static bool trans_frnd_d(DisasContext
*ctx
, arg_fclass01
*a
)
3644 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_frnd_d
);
3647 static void gen_fneg_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3649 tcg_gen_xori_i32(dst
, src
, INT32_MIN
);
3652 static bool trans_fneg_f(DisasContext
*ctx
, arg_fclass01
*a
)
3654 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fneg_f
);
3657 static void gen_fneg_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3659 tcg_gen_xori_i64(dst
, src
, INT64_MIN
);
3662 static bool trans_fneg_d(DisasContext
*ctx
, arg_fclass01
*a
)
3664 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fneg_d
);
3667 static void gen_fnegabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3669 tcg_gen_ori_i32(dst
, src
, INT32_MIN
);
3672 static bool trans_fnegabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3674 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fnegabs_f
);
3677 static void gen_fnegabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3679 tcg_gen_ori_i64(dst
, src
, INT64_MIN
);
3682 static bool trans_fnegabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3684 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fnegabs_d
);
3691 static bool trans_fcnv_d_f(DisasContext
*ctx
, arg_fclass01
*a
)
3693 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_s
);
3696 static bool trans_fcnv_f_d(DisasContext
*ctx
, arg_fclass01
*a
)
3698 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_d
);
3701 static bool trans_fcnv_w_f(DisasContext
*ctx
, arg_fclass01
*a
)
3703 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_s
);
3706 static bool trans_fcnv_q_f(DisasContext
*ctx
, arg_fclass01
*a
)
3708 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_s
);
3711 static bool trans_fcnv_w_d(DisasContext
*ctx
, arg_fclass01
*a
)
3713 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_d
);
3716 static bool trans_fcnv_q_d(DisasContext
*ctx
, arg_fclass01
*a
)
3718 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_d
);
3721 static bool trans_fcnv_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3723 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_w
);
3726 static bool trans_fcnv_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3728 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_w
);
3731 static bool trans_fcnv_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3733 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_dw
);
3736 static bool trans_fcnv_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3738 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_dw
);
3741 static bool trans_fcnv_t_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3743 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_w
);
3746 static bool trans_fcnv_t_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3748 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_w
);
3751 static bool trans_fcnv_t_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3753 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_dw
);
3756 static bool trans_fcnv_t_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3758 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_dw
);
3761 static bool trans_fcnv_uw_f(DisasContext
*ctx
, arg_fclass01
*a
)
3763 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_s
);
3766 static bool trans_fcnv_uq_f(DisasContext
*ctx
, arg_fclass01
*a
)
3768 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_s
);
3771 static bool trans_fcnv_uw_d(DisasContext
*ctx
, arg_fclass01
*a
)
3773 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_d
);
3776 static bool trans_fcnv_uq_d(DisasContext
*ctx
, arg_fclass01
*a
)
3778 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_d
);
3781 static bool trans_fcnv_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3783 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_uw
);
3786 static bool trans_fcnv_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3788 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_uw
);
3791 static bool trans_fcnv_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3793 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_udw
);
3796 static bool trans_fcnv_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3798 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_udw
);
3801 static bool trans_fcnv_t_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3803 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_uw
);
3806 static bool trans_fcnv_t_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3808 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_uw
);
3811 static bool trans_fcnv_t_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3813 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_udw
);
3816 static bool trans_fcnv_t_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3818 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_udw
);
3825 static bool trans_fcmp_f(DisasContext
*ctx
, arg_fclass2
*a
)
3827 TCGv_i32 ta
, tb
, tc
, ty
;
3831 ta
= load_frw0_i32(a
->r1
);
3832 tb
= load_frw0_i32(a
->r2
);
3833 ty
= tcg_constant_i32(a
->y
);
3834 tc
= tcg_constant_i32(a
->c
);
3836 gen_helper_fcmp_s(cpu_env
, ta
, tb
, ty
, tc
);
3838 tcg_temp_free_i32(ta
);
3839 tcg_temp_free_i32(tb
);
3841 return nullify_end(ctx
);
3844 static bool trans_fcmp_d(DisasContext
*ctx
, arg_fclass2
*a
)
3851 ta
= load_frd0(a
->r1
);
3852 tb
= load_frd0(a
->r2
);
3853 ty
= tcg_constant_i32(a
->y
);
3854 tc
= tcg_constant_i32(a
->c
);
3856 gen_helper_fcmp_d(cpu_env
, ta
, tb
, ty
, tc
);
3858 tcg_temp_free_i64(ta
);
3859 tcg_temp_free_i64(tb
);
3861 return nullify_end(ctx
);
3864 static bool trans_ftest(DisasContext
*ctx
, arg_ftest
*a
)
3871 tcg_gen_ld32u_reg(t
, cpu_env
, offsetof(CPUHPPAState
, fr0_shadow
));
3878 case 0: /* simple */
3879 tcg_gen_andi_reg(t
, t
, 0x4000000);
3880 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3908 TCGv_reg c
= load_const(ctx
, mask
);
3909 tcg_gen_or_reg(t
, t
, c
);
3910 ctx
->null_cond
= cond_make(TCG_COND_EQ
, t
, c
);
3912 tcg_gen_andi_reg(t
, t
, mask
);
3913 ctx
->null_cond
= cond_make_0(TCG_COND_EQ
, t
);
3916 unsigned cbit
= (a
->y
^ 1) - 1;
3918 tcg_gen_extract_reg(t
, t
, 21 - cbit
, 1);
3919 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3924 return nullify_end(ctx
);
3931 static bool trans_fadd_f(DisasContext
*ctx
, arg_fclass3
*a
)
3933 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_s
);
3936 static bool trans_fadd_d(DisasContext
*ctx
, arg_fclass3
*a
)
3938 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_d
);
3941 static bool trans_fsub_f(DisasContext
*ctx
, arg_fclass3
*a
)
3943 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_s
);
3946 static bool trans_fsub_d(DisasContext
*ctx
, arg_fclass3
*a
)
3948 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_d
);
3951 static bool trans_fmpy_f(DisasContext
*ctx
, arg_fclass3
*a
)
3953 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_s
);
3956 static bool trans_fmpy_d(DisasContext
*ctx
, arg_fclass3
*a
)
3958 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_d
);
3961 static bool trans_fdiv_f(DisasContext
*ctx
, arg_fclass3
*a
)
3963 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_s
);
3966 static bool trans_fdiv_d(DisasContext
*ctx
, arg_fclass3
*a
)
3968 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_d
);
3971 static bool trans_xmpyu(DisasContext
*ctx
, arg_xmpyu
*a
)
3977 x
= load_frw0_i64(a
->r1
);
3978 y
= load_frw0_i64(a
->r2
);
3979 tcg_gen_mul_i64(x
, x
, y
);
3981 tcg_temp_free_i64(x
);
3982 tcg_temp_free_i64(y
);
3984 return nullify_end(ctx
);
3987 /* Convert the fmpyadd single-precision register encodings to standard. */
3988 static inline int fmpyadd_s_reg(unsigned r
)
3990 return (r
& 16) * 2 + 16 + (r
& 15);
3993 static bool do_fmpyadd_s(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
3995 int tm
= fmpyadd_s_reg(a
->tm
);
3996 int ra
= fmpyadd_s_reg(a
->ra
);
3997 int ta
= fmpyadd_s_reg(a
->ta
);
3998 int rm2
= fmpyadd_s_reg(a
->rm2
);
3999 int rm1
= fmpyadd_s_reg(a
->rm1
);
4003 do_fop_weww(ctx
, tm
, rm1
, rm2
, gen_helper_fmpy_s
);
4004 do_fop_weww(ctx
, ta
, ta
, ra
,
4005 is_sub
? gen_helper_fsub_s
: gen_helper_fadd_s
);
4007 return nullify_end(ctx
);
4010 static bool trans_fmpyadd_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4012 return do_fmpyadd_s(ctx
, a
, false);
4015 static bool trans_fmpysub_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4017 return do_fmpyadd_s(ctx
, a
, true);
4020 static bool do_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4024 do_fop_dedd(ctx
, a
->tm
, a
->rm1
, a
->rm2
, gen_helper_fmpy_d
);
4025 do_fop_dedd(ctx
, a
->ta
, a
->ta
, a
->ra
,
4026 is_sub
? gen_helper_fsub_d
: gen_helper_fadd_d
);
4028 return nullify_end(ctx
);
4031 static bool trans_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4033 return do_fmpyadd_d(ctx
, a
, false);
4036 static bool trans_fmpysub_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4038 return do_fmpyadd_d(ctx
, a
, true);
4041 static bool trans_fmpyfadd_f(DisasContext
*ctx
, arg_fmpyfadd_f
*a
)
4046 x
= load_frw0_i32(a
->rm1
);
4047 y
= load_frw0_i32(a
->rm2
);
4048 z
= load_frw0_i32(a
->ra3
);
4051 gen_helper_fmpynfadd_s(x
, cpu_env
, x
, y
, z
);
4053 gen_helper_fmpyfadd_s(x
, cpu_env
, x
, y
, z
);
4056 tcg_temp_free_i32(y
);
4057 tcg_temp_free_i32(z
);
4058 save_frw_i32(a
->t
, x
);
4059 tcg_temp_free_i32(x
);
4060 return nullify_end(ctx
);
4063 static bool trans_fmpyfadd_d(DisasContext
*ctx
, arg_fmpyfadd_d
*a
)
4068 x
= load_frd0(a
->rm1
);
4069 y
= load_frd0(a
->rm2
);
4070 z
= load_frd0(a
->ra3
);
4073 gen_helper_fmpynfadd_d(x
, cpu_env
, x
, y
, z
);
4075 gen_helper_fmpyfadd_d(x
, cpu_env
, x
, y
, z
);
4078 tcg_temp_free_i64(y
);
4079 tcg_temp_free_i64(z
);
4081 tcg_temp_free_i64(x
);
4082 return nullify_end(ctx
);
4085 static bool trans_diag(DisasContext
*ctx
, arg_diag
*a
)
4087 qemu_log_mask(LOG_UNIMP
, "DIAG opcode ignored\n");
4088 cond_free(&ctx
->null_cond
);
4092 static void hppa_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
4094 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4098 ctx
->tb_flags
= ctx
->base
.tb
->flags
;
4100 #ifdef CONFIG_USER_ONLY
4101 ctx
->privilege
= MMU_USER_IDX
;
4102 ctx
->mmu_idx
= MMU_USER_IDX
;
4103 ctx
->iaoq_f
= ctx
->base
.pc_first
| MMU_USER_IDX
;
4104 ctx
->iaoq_b
= ctx
->base
.tb
->cs_base
| MMU_USER_IDX
;
4106 ctx
->privilege
= (ctx
->tb_flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
4107 ctx
->mmu_idx
= (ctx
->tb_flags
& PSW_D
? ctx
->privilege
: MMU_PHYS_IDX
);
4109 /* Recover the IAOQ values from the GVA + PRIV. */
4110 uint64_t cs_base
= ctx
->base
.tb
->cs_base
;
4111 uint64_t iasq_f
= cs_base
& ~0xffffffffull
;
4112 int32_t diff
= cs_base
;
4114 ctx
->iaoq_f
= (ctx
->base
.pc_first
& ~iasq_f
) + ctx
->privilege
;
4115 ctx
->iaoq_b
= (diff
? ctx
->iaoq_f
+ diff
: -1);
4118 ctx
->iaoq_n_var
= NULL
;
4120 /* Bound the number of instructions by those left on the page. */
4121 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
4122 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
4126 memset(ctx
->tempr
, 0, sizeof(ctx
->tempr
));
4127 memset(ctx
->templ
, 0, sizeof(ctx
->templ
));
4130 static void hppa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4132 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4134 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */
4135 ctx
->null_cond
= cond_make_f();
4136 ctx
->psw_n_nonzero
= false;
4137 if (ctx
->tb_flags
& PSW_N
) {
4138 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
4139 ctx
->psw_n_nonzero
= true;
4141 ctx
->null_lab
= NULL
;
4144 static void hppa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4146 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4148 tcg_gen_insn_start(ctx
->iaoq_f
, ctx
->iaoq_b
);
4151 static void hppa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
4153 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4154 CPUHPPAState
*env
= cs
->env_ptr
;
4158 /* Execute one insn. */
4159 #ifdef CONFIG_USER_ONLY
4160 if (ctx
->base
.pc_next
< TARGET_PAGE_SIZE
) {
4162 ret
= ctx
->base
.is_jmp
;
4163 assert(ret
!= DISAS_NEXT
);
4167 /* Always fetch the insn, even if nullified, so that we check
4168 the page permissions for execute. */
4169 uint32_t insn
= translator_ldl(env
, &ctx
->base
, ctx
->base
.pc_next
);
4171 /* Set up the IA queue for the next insn.
4172 This will be overwritten by a branch. */
4173 if (ctx
->iaoq_b
== -1) {
4175 ctx
->iaoq_n_var
= get_temp(ctx
);
4176 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
4178 ctx
->iaoq_n
= ctx
->iaoq_b
+ 4;
4179 ctx
->iaoq_n_var
= NULL
;
4182 if (unlikely(ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4183 ctx
->null_cond
.c
= TCG_COND_NEVER
;
4187 if (!decode(ctx
, insn
)) {
4190 ret
= ctx
->base
.is_jmp
;
4191 assert(ctx
->null_lab
== NULL
);
4195 /* Free any temporaries allocated. */
4196 for (i
= 0, n
= ctx
->ntempr
; i
< n
; ++i
) {
4197 tcg_temp_free(ctx
->tempr
[i
]);
4198 ctx
->tempr
[i
] = NULL
;
4200 for (i
= 0, n
= ctx
->ntempl
; i
< n
; ++i
) {
4201 tcg_temp_free_tl(ctx
->templ
[i
]);
4202 ctx
->templ
[i
] = NULL
;
4207 /* Advance the insn queue. Note that this check also detects
4208 a priority change within the instruction queue. */
4209 if (ret
== DISAS_NEXT
&& ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
4210 if (ctx
->iaoq_b
!= -1 && ctx
->iaoq_n
!= -1
4211 && use_goto_tb(ctx
, ctx
->iaoq_b
)
4212 && (ctx
->null_cond
.c
== TCG_COND_NEVER
4213 || ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4214 nullify_set(ctx
, ctx
->null_cond
.c
== TCG_COND_ALWAYS
);
4215 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
4216 ctx
->base
.is_jmp
= ret
= DISAS_NORETURN
;
4218 ctx
->base
.is_jmp
= ret
= DISAS_IAQ_N_STALE
;
4221 ctx
->iaoq_f
= ctx
->iaoq_b
;
4222 ctx
->iaoq_b
= ctx
->iaoq_n
;
4223 ctx
->base
.pc_next
+= 4;
4226 case DISAS_NORETURN
:
4227 case DISAS_IAQ_N_UPDATED
:
4231 case DISAS_IAQ_N_STALE
:
4232 case DISAS_IAQ_N_STALE_EXIT
:
4233 if (ctx
->iaoq_f
== -1) {
4234 tcg_gen_mov_reg(cpu_iaoq_f
, cpu_iaoq_b
);
4235 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
4236 #ifndef CONFIG_USER_ONLY
4237 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
4240 ctx
->base
.is_jmp
= (ret
== DISAS_IAQ_N_STALE_EXIT
4242 : DISAS_IAQ_N_UPDATED
);
4243 } else if (ctx
->iaoq_b
== -1) {
4244 tcg_gen_mov_reg(cpu_iaoq_b
, ctx
->iaoq_n_var
);
4249 g_assert_not_reached();
4253 static void hppa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
4255 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4256 DisasJumpType is_jmp
= ctx
->base
.is_jmp
;
4259 case DISAS_NORETURN
:
4261 case DISAS_TOO_MANY
:
4262 case DISAS_IAQ_N_STALE
:
4263 case DISAS_IAQ_N_STALE_EXIT
:
4264 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
4265 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
4268 case DISAS_IAQ_N_UPDATED
:
4269 if (is_jmp
!= DISAS_IAQ_N_STALE_EXIT
) {
4270 tcg_gen_lookup_and_goto_ptr();
4275 tcg_gen_exit_tb(NULL
, 0);
4278 g_assert_not_reached();
4282 static void hppa_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
4284 target_ulong pc
= dcbase
->pc_first
;
4286 #ifdef CONFIG_USER_ONLY
4289 qemu_log("IN:\n0x00000000: (null)\n");
4292 qemu_log("IN:\n0x000000b0: light-weight-syscall\n");
4295 qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n");
4298 qemu_log("IN:\n0x00000100: syscall\n");
4303 qemu_log("IN: %s\n", lookup_symbol(pc
));
4304 log_target_disas(cs
, pc
, dcbase
->tb
->size
);
4307 static const TranslatorOps hppa_tr_ops
= {
4308 .init_disas_context
= hppa_tr_init_disas_context
,
4309 .tb_start
= hppa_tr_tb_start
,
4310 .insn_start
= hppa_tr_insn_start
,
4311 .translate_insn
= hppa_tr_translate_insn
,
4312 .tb_stop
= hppa_tr_tb_stop
,
4313 .disas_log
= hppa_tr_disas_log
,
4316 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
4319 translator_loop(&hppa_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
4322 void restore_state_to_opc(CPUHPPAState
*env
, TranslationBlock
*tb
,
4325 env
->iaoq_f
= data
[0];
4326 if (data
[1] != (target_ureg
)-1) {
4327 env
->iaoq_b
= data
[1];
4329 /* Since we were executing the instruction at IAOQ_F, and took some
4330 sort of action that provoked the cpu_restore_state, we can infer
4331 that the instruction was not nullified. */