hw/arm/stm32f405_soc.c

   1 /*
   2  * STM32F405 SoC
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "exec/address-spaces.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/arm/stm32f405_soc.h"
  31 #include "hw/qdev-clock.h"
  32 #include "hw/misc/unimp.h"
  33
  34 #define SYSCFG_ADD                     0x40013800
  35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
  36                                        0x40004C00, 0x40005000, 0x40011400,
  37                                        0x40007800, 0x40007C00 };
  38 /* At the moment only Timer 2 to 5 are modelled */
  39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
  40                                        0x40000800, 0x40000C00 };
  41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
  42                                      0x40012300, 0x40012400, 0x40012500 };
  43 static const uint32_t spi_addr[] =   { 0x40013000, 0x40003800, 0x40003C00,
  44                                        0x40013400, 0x40015000, 0x40015400 };
  45 #define EXTI_ADDR                      0x40013C00
  46
  47 #define SYSCFG_IRQ               71
  48 static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
  49 static const int timer_irq[] = { 28, 29, 30, 50 };
  50 #define ADC_IRQ 18
  51 static const int spi_irq[] =   { 35, 36, 51, 0, 0, 0 };
  52 static const int exti_irq[] =  { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
  53                                  40, 40, 40, 40, 40} ;
  54
  55
  56 static void stm32f405_soc_initfn(Object *obj)
  57 {
  58     STM32F405State *s = STM32F405_SOC(obj);
  59     int i;
  60
  61     object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
  62
  63     object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
  64
  65     for (i = 0; i < STM_NUM_USARTS; i++) {
  66         object_initialize_child(obj, "usart[*]", &s->usart[i],
  67                                 TYPE_STM32F2XX_USART);
  68     }
  69
  70     for (i = 0; i < STM_NUM_TIMERS; i++) {
  71         object_initialize_child(obj, "timer[*]", &s->timer[i],
  72                                 TYPE_STM32F2XX_TIMER);
  73     }
  74
  75     for (i = 0; i < STM_NUM_ADCS; i++) {
  76         object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
  77     }
  78
  79     for (i = 0; i < STM_NUM_SPIS; i++) {
  80         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
  81     }
  82
  83     object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
  84
  85     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
  86     s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
  87 }
  88
  89 static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
  90 {
  91     STM32F405State *s = STM32F405_SOC(dev_soc);
  92     MemoryRegion *system_memory = get_system_memory();
  93     DeviceState *dev, *armv7m;
  94     SysBusDevice *busdev;
  95     Error *err = NULL;
  96     int i;
  97
  98     /*
  99      * We use s->refclk internally and only define it with qdev_init_clock_in()
 100      * so it is correctly parented and not leaked on an init/deinit; it is not
 101      * intended as an externally exposed clock.
 102      */
 103     if (clock_has_source(s->refclk)) {
 104         error_setg(errp, "refclk clock must not be wired up by the board code");
 105         return;
 106     }
 107
 108     if (!clock_has_source(s->sysclk)) {
 109         error_setg(errp, "sysclk clock must be wired up by the board code");
 110         return;
 111     }
 112
 113     /*
 114      * TODO: ideally we should model the SoC RCC and its ability to
 115      * change the sysclk frequency and define different sysclk sources.
 116      */
 117
 118     /* The refclk always runs at frequency HCLK / 8 */
 119     clock_set_mul_div(s->refclk, 8, 1);
 120     clock_set_source(s->refclk, s->sysclk);
 121
 122     memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
 123                            FLASH_SIZE, &err);
 124     if (err != NULL) {
 125         error_propagate(errp, err);
 126         return;
 127     }
 128     memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
 129                              "STM32F405.flash.alias", &s->flash, 0,
 130                              FLASH_SIZE);
 131
 132     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
 133     memory_region_add_subregion(system_memory, 0, &s->flash_alias);
 134
 135     memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
 136                            &err);
 137     if (err != NULL) {
 138         error_propagate(errp, err);
 139         return;
 140     }
 141     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
 142
 143     armv7m = DEVICE(&s->armv7m);
 144     qdev_prop_set_uint32(armv7m, "num-irq", 96);
 145     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 146     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 147     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
 148     qdev_connect_clock_in(armv7m, "refclk", s->refclk);
 149     object_property_set_link(OBJECT(&s->armv7m), "memory",
 150                              OBJECT(system_memory), &error_abort);
 151     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
 152         return;
 153     }
 154
 155     /* System configuration controller */
 156     dev = DEVICE(&s->syscfg);
 157     if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
 158         return;
 159     }
 160     busdev = SYS_BUS_DEVICE(dev);
 161     sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
 162     sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
 163
 164     /* Attach UART (uses USART registers) and USART controllers */
 165     for (i = 0; i < STM_NUM_USARTS; i++) {
 166         dev = DEVICE(&(s->usart[i]));
 167         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 168         if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
 169             return;
 170         }
 171         busdev = SYS_BUS_DEVICE(dev);
 172         sysbus_mmio_map(busdev, 0, usart_addr[i]);
 173         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
 174     }
 175
 176     /* Timer 2 to 5 */
 177     for (i = 0; i < STM_NUM_TIMERS; i++) {
 178         dev = DEVICE(&(s->timer[i]));
 179         qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
 180         if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
 181             return;
 182         }
 183         busdev = SYS_BUS_DEVICE(dev);
 184         sysbus_mmio_map(busdev, 0, timer_addr[i]);
 185         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
 186     }
 187
 188     /* ADC device, the IRQs are ORed together */
 189     if (!object_initialize_child_with_props(OBJECT(s), "adc-orirq",
 190                                             &s->adc_irqs, sizeof(s->adc_irqs),
 191                                             TYPE_OR_IRQ, errp, NULL)) {
 192         return;
 193     }
 194     object_property_set_int(OBJECT(&s->adc_irqs), "num-lines", STM_NUM_ADCS,
 195                             &error_abort);
 196     if (!qdev_realize(DEVICE(&s->adc_irqs), NULL, errp)) {
 197         return;
 198     }
 199     qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
 200                           qdev_get_gpio_in(armv7m, ADC_IRQ));
 201
 202     for (i = 0; i < STM_NUM_ADCS; i++) {
 203         dev = DEVICE(&(s->adc[i]));
 204         if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
 205             return;
 206         }
 207         busdev = SYS_BUS_DEVICE(dev);
 208         sysbus_mmio_map(busdev, 0, adc_addr[i]);
 209         sysbus_connect_irq(busdev, 0,
 210                            qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
 211     }
 212
 213     /* SPI devices */
 214     for (i = 0; i < STM_NUM_SPIS; i++) {
 215         dev = DEVICE(&(s->spi[i]));
 216         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
 217             return;
 218         }
 219         busdev = SYS_BUS_DEVICE(dev);
 220         sysbus_mmio_map(busdev, 0, spi_addr[i]);
 221         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
 222     }
 223
 224     /* EXTI device */
 225     dev = DEVICE(&s->exti);
 226     if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) {
 227         return;
 228     }
 229     busdev = SYS_BUS_DEVICE(dev);
 230     sysbus_mmio_map(busdev, 0, EXTI_ADDR);
 231     for (i = 0; i < 16; i++) {
 232         sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
 233     }
 234     for (i = 0; i < 16; i++) {
 235         qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
 236     }
 237
 238     create_unimplemented_device("timer[7]",    0x40001400, 0x400);
 239     create_unimplemented_device("timer[12]",   0x40001800, 0x400);
 240     create_unimplemented_device("timer[6]",    0x40001000, 0x400);
 241     create_unimplemented_device("timer[13]",   0x40001C00, 0x400);
 242     create_unimplemented_device("timer[14]",   0x40002000, 0x400);
 243     create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
 244     create_unimplemented_device("WWDG",        0x40002C00, 0x400);
 245     create_unimplemented_device("IWDG",        0x40003000, 0x400);
 246     create_unimplemented_device("I2S2ext",     0x40003000, 0x400);
 247     create_unimplemented_device("I2S3ext",     0x40004000, 0x400);
 248     create_unimplemented_device("I2C1",        0x40005400, 0x400);
 249     create_unimplemented_device("I2C2",        0x40005800, 0x400);
 250     create_unimplemented_device("I2C3",        0x40005C00, 0x400);
 251     create_unimplemented_device("CAN1",        0x40006400, 0x400);
 252     create_unimplemented_device("CAN2",        0x40006800, 0x400);
 253     create_unimplemented_device("PWR",         0x40007000, 0x400);
 254     create_unimplemented_device("DAC",         0x40007400, 0x400);
 255     create_unimplemented_device("timer[1]",    0x40010000, 0x400);
 256     create_unimplemented_device("timer[8]",    0x40010400, 0x400);
 257     create_unimplemented_device("SDIO",        0x40012C00, 0x400);
 258     create_unimplemented_device("timer[9]",    0x40014000, 0x400);
 259     create_unimplemented_device("timer[10]",   0x40014400, 0x400);
 260     create_unimplemented_device("timer[11]",   0x40014800, 0x400);
 261     create_unimplemented_device("GPIOA",       0x40020000, 0x400);
 262     create_unimplemented_device("GPIOB",       0x40020400, 0x400);
 263     create_unimplemented_device("GPIOC",       0x40020800, 0x400);
 264     create_unimplemented_device("GPIOD",       0x40020C00, 0x400);
 265     create_unimplemented_device("GPIOE",       0x40021000, 0x400);
 266     create_unimplemented_device("GPIOF",       0x40021400, 0x400);
 267     create_unimplemented_device("GPIOG",       0x40021800, 0x400);
 268     create_unimplemented_device("GPIOH",       0x40021C00, 0x400);
 269     create_unimplemented_device("GPIOI",       0x40022000, 0x400);
 270     create_unimplemented_device("CRC",         0x40023000, 0x400);
 271     create_unimplemented_device("RCC",         0x40023800, 0x400);
 272     create_unimplemented_device("Flash Int",   0x40023C00, 0x400);
 273     create_unimplemented_device("BKPSRAM",     0x40024000, 0x400);
 274     create_unimplemented_device("DMA1",        0x40026000, 0x400);
 275     create_unimplemented_device("DMA2",        0x40026400, 0x400);
 276     create_unimplemented_device("Ethernet",    0x40028000, 0x1400);
 277     create_unimplemented_device("USB OTG HS",  0x40040000, 0x30000);
 278     create_unimplemented_device("USB OTG FS",  0x50000000, 0x31000);
 279     create_unimplemented_device("DCMI",        0x50050000, 0x400);
 280     create_unimplemented_device("RNG",         0x50060800, 0x400);
 281 }
 282
 283 static Property stm32f405_soc_properties[] = {
 284     DEFINE_PROP_STRING("cpu-type", STM32F405State, cpu_type),
 285     DEFINE_PROP_END_OF_LIST(),
 286 };
 287
 288 static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
 289 {
 290     DeviceClass *dc = DEVICE_CLASS(klass);
 291
 292     dc->realize = stm32f405_soc_realize;
 293     device_class_set_props(dc, stm32f405_soc_properties);
 294     /* No vmstate or reset required: device has no internal state */
 295 }
 296
 297 static const TypeInfo stm32f405_soc_info = {
 298     .name          = TYPE_STM32F405_SOC,
 299     .parent        = TYPE_SYS_BUS_DEVICE,
 300     .instance_size = sizeof(STM32F405State),
 301     .instance_init = stm32f405_soc_initfn,
 302     .class_init    = stm32f405_soc_class_init,
 303 };
 304
 305 static void stm32f405_soc_types(void)
 306 {
 307     type_register_static(&stm32f405_soc_info);
 308 }
 309
 310 type_init(stm32f405_soc_types)