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target/ppc: Filter mtmsr[d] input before setting MSR
[qemu/rayw.git] / hw / arm / aspeed.c
blobf5916e81262eb80f0526c3f67636281bfc866b27
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/i2c/i2c_mux_pca954x.h"
18 #include "hw/i2c/smbus_eeprom.h"
19 #include "hw/misc/pca9552.h"
20 #include "hw/sensor/tmp105.h"
21 #include "hw/misc/led.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/block-backend.h"
24 #include "hw/loader.h"
25 #include "qemu/error-report.h"
26 #include "qemu/units.h"
27
28 static struct arm_boot_info aspeed_board_binfo = {
29 .board_id = -1, /* device-tree-only board */
30 };
31
32 struct AspeedMachineState {
33 /* Private */
34 MachineState parent_obj;
35 /* Public */
36
37 AspeedSoCState soc;
38 MemoryRegion ram_container;
39 MemoryRegion max_ram;
40 bool mmio_exec;
41 char *fmc_model;
42 char *spi_model;
43 };
44
45 /* Palmetto hardware value: 0x120CE416 */
46 #define PALMETTO_BMC_HW_STRAP1 ( \
47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
49 SCU_AST2400_HW_STRAP_ACPI_DIS | \
50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
51 SCU_HW_STRAP_VGA_CLASS_CODE | \
52 SCU_HW_STRAP_LPC_RESET_PIN | \
53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
55 SCU_HW_STRAP_SPI_WIDTH | \
56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
58
59 /* TODO: Find the actual hardware value */
60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
63 SCU_AST2400_HW_STRAP_ACPI_DIS | \
64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
65 SCU_HW_STRAP_VGA_CLASS_CODE | \
66 SCU_HW_STRAP_LPC_RESET_PIN | \
67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69 SCU_HW_STRAP_SPI_WIDTH | \
70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72
73 /* AST2500 evb hardware value: 0xF100C2E6 */
74 #define AST2500_EVB_HW_STRAP1 (( \
75 AST2500_HW_STRAP1_DEFAULTS | \
76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
78 SCU_AST2500_HW_STRAP_UART_DEBUG | \
79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
80 SCU_HW_STRAP_MAC1_RGMII | \
81 SCU_HW_STRAP_MAC0_RGMII) & \
82 ~SCU_HW_STRAP_2ND_BOOT_WDT)
83
84 /* Romulus hardware value: 0xF10AD206 */
85 #define ROMULUS_BMC_HW_STRAP1 ( \
86 AST2500_HW_STRAP1_DEFAULTS | \
87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
89 SCU_AST2500_HW_STRAP_UART_DEBUG | \
90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
93
94 /* Sonorapass hardware value: 0xF100D216 */
95 #define SONORAPASS_BMC_HW_STRAP1 ( \
96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
98 SCU_AST2500_HW_STRAP_UART_DEBUG | \
99 SCU_AST2500_HW_STRAP_RESERVED28 | \
100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
101 SCU_HW_STRAP_VGA_CLASS_CODE | \
102 SCU_HW_STRAP_LPC_RESET_PIN | \
103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
105 SCU_HW_STRAP_VGA_BIOS_ROM | \
106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
107 SCU_AST2500_HW_STRAP_RESERVED1)
108
109 /* Swift hardware value: 0xF11AD206 */
110 #define SWIFT_BMC_HW_STRAP1 ( \
111 AST2500_HW_STRAP1_DEFAULTS | \
112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
114 SCU_AST2500_HW_STRAP_UART_DEBUG | \
115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
116 SCU_H_PLL_BYPASS_EN | \
117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
119
120 #define G220A_BMC_HW_STRAP1 ( \
121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
123 SCU_AST2500_HW_STRAP_UART_DEBUG | \
124 SCU_AST2500_HW_STRAP_RESERVED28 | \
125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
126 SCU_HW_STRAP_2ND_BOOT_WDT | \
127 SCU_HW_STRAP_VGA_CLASS_CODE | \
128 SCU_HW_STRAP_LPC_RESET_PIN | \
129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
132 SCU_AST2500_HW_STRAP_RESERVED1)
133
134 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
135 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
136
137 /* Quanta-Q71l hardware value */
138 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
139 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
140 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
141 SCU_AST2400_HW_STRAP_ACPI_DIS | \
142 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
143 SCU_HW_STRAP_VGA_CLASS_CODE | \
144 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
145 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
146 SCU_HW_STRAP_SPI_WIDTH | \
147 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
148 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
149
150 /* AST2600 evb hardware value */
151 #define AST2600_EVB_HW_STRAP1 0x000000C0
152 #define AST2600_EVB_HW_STRAP2 0x00000003
153
154 /* Tacoma hardware value */
155 #define TACOMA_BMC_HW_STRAP1 0x00000000
156 #define TACOMA_BMC_HW_STRAP2 0x00000040
157
158 /* Rainier hardware value: (QEMU prototype) */
159 #define RAINIER_BMC_HW_STRAP1 0x00000000
160 #define RAINIER_BMC_HW_STRAP2 0x00000000
161
162 /* Fuji hardware value */
163 #define FUJI_BMC_HW_STRAP1 0x00000000
164 #define FUJI_BMC_HW_STRAP2 0x00000000
165
166 /*
167 * The max ram region is for firmwares that scan the address space
168 * with load/store to guess how much RAM the SoC has.
169 */
170 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
171 {
172 return 0;
173 }
174
175 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
176 unsigned size)
177 {
178 /* Discard writes */
179 }
180
181 static const MemoryRegionOps max_ram_ops = {
182 .read = max_ram_read,
183 .write = max_ram_write,
184 .endianness = DEVICE_NATIVE_ENDIAN,
185 };
186
187 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
188 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
189 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
190 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
191 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
192 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
193 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
194
195 static void aspeed_write_smpboot(ARMCPU *cpu,
196 const struct arm_boot_info *info)
197 {
198 static const uint32_t poll_mailbox_ready[] = {
199 /*
200 * r2 = per-cpu go sign value
201 * r1 = AST_SMP_MBOX_FIELD_ENTRY
202 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
203 */
204 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
205 0xe21000ff, /* ands r0, r0, #255 */
206 0xe59f201c, /* ldr r2, [pc, #28] */
207 0xe1822000, /* orr r2, r2, r0 */
208
209 0xe59f1018, /* ldr r1, [pc, #24] */
210 0xe59f0018, /* ldr r0, [pc, #24] */
211
212 0xe320f002, /* wfe */
213 0xe5904000, /* ldr r4, [r0] */
214 0xe1520004, /* cmp r2, r4 */
215 0x1afffffb, /* bne <wfe> */
216 0xe591f000, /* ldr pc, [r1] */
217 AST_SMP_MBOX_GOSIGN,
218 AST_SMP_MBOX_FIELD_ENTRY,
219 AST_SMP_MBOX_FIELD_GOSIGN,
220 };
221
222 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
223 sizeof(poll_mailbox_ready),
224 info->smp_loader_start);
225 }
226
227 static void aspeed_reset_secondary(ARMCPU *cpu,
228 const struct arm_boot_info *info)
229 {
230 AddressSpace *as = arm_boot_address_space(cpu, info);
231 CPUState *cs = CPU(cpu);
232
233 /* info->smp_bootreg_addr */
234 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
235 MEMTXATTRS_UNSPECIFIED, NULL);
236 cpu_set_pc(cs, info->smp_loader_start);
237 }
238
239 #define FIRMWARE_ADDR 0x0
240
241 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
242 Error **errp)
243 {
244 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
245 uint8_t *storage;
246 int64_t size;
247
248 /* The block backend size should have already been 'validated' by
249 * the creation of the m25p80 object.
250 */
251 size = blk_getlength(blk);
252 if (size <= 0) {
253 error_setg(errp, "failed to get flash size");
254 return;
255 }
256
257 if (rom_size > size) {
258 rom_size = size;
259 }
260
261 storage = g_new0(uint8_t, rom_size);
262 if (blk_pread(blk, 0, storage, rom_size) < 0) {
263 error_setg(errp, "failed to read the initial flash content");
264 return;
265 }
266
267 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
268 g_free(storage);
269 }
270
271 static void aspeed_board_init_flashes(AspeedSMCState *s,
272 const char *flashtype)
273 {
274 int i ;
275
276 for (i = 0; i < s->num_cs; ++i) {
277 DriveInfo *dinfo = drive_get_next(IF_MTD);
278 qemu_irq cs_line;
279 DeviceState *dev;
280
281 dev = qdev_new(flashtype);
282 if (dinfo) {
283 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
284 }
285 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
286
287 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
288 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
289 }
290 }
291
292 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
293 {
294 DeviceState *card;
295
296 if (!dinfo) {
297 return;
298 }
299 card = qdev_new(TYPE_SD_CARD);
300 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
301 &error_fatal);
302 qdev_realize_and_unref(card,
303 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
304 &error_fatal);
305 }
306
307 static void aspeed_machine_init(MachineState *machine)
308 {
309 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
310 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
311 AspeedSoCClass *sc;
312 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
313 ram_addr_t max_ram_size;
314 int i;
315 NICInfo *nd = &nd_table[0];
316
317 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
318 4 * GiB);
319 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
320
321 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
322
323 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
324
325 /*
326 * This will error out if isize is not supported by memory controller.
327 */
328 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
329 &error_fatal);
330
331 for (i = 0; i < sc->macs_num; i++) {
332 if ((amc->macs_mask & (1 << i)) && nd->used) {
333 qemu_check_nic_model(nd, TYPE_FTGMAC100);
334 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
335 nd++;
336 }
337 }
338
339 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
340 &error_abort);
341 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
342 &error_abort);
343 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
344 &error_abort);
345 object_property_set_link(OBJECT(&bmc->soc), "dram",
346 OBJECT(machine->ram), &error_abort);
347 if (machine->kernel_filename) {
348 /*
349 * When booting with a -kernel command line there is no u-boot
350 * that runs to unlock the SCU. In this case set the default to
351 * be unlocked as the kernel expects
352 */
353 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
354 ASPEED_SCU_PROT_KEY, &error_abort);
355 }
356 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
357 amc->uart_default);
358 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
359
360 memory_region_add_subregion(get_system_memory(),
361 sc->memmap[ASPEED_DEV_SDRAM],
362 &bmc->ram_container);
363
364 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
365 &error_abort);
366 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
367 "max_ram", max_ram_size - machine->ram_size);
368 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
369
370 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
371 bmc->fmc_model : amc->fmc_model);
372 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
373 bmc->spi_model : amc->spi_model);
374
375 /* Install first FMC flash content as a boot rom. */
376 if (drive0) {
377 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
378 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
379 uint64_t size = memory_region_size(&fl->mmio);
380
381 /*
382 * create a ROM region using the default mapping window size of
383 * the flash module. The window size is 64MB for the AST2400
384 * SoC and 128MB for the AST2500 SoC, which is twice as big as
385 * needed by the flash modules of the Aspeed machines.
386 */
387 if (ASPEED_MACHINE(machine)->mmio_exec) {
388 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
389 &fl->mmio, 0, size);
390 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
391 boot_rom);
392 } else {
393 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
394 size, &error_abort);
395 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
396 boot_rom);
397 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
398 }
399 }
400
401 if (machine->kernel_filename && sc->num_cpus > 1) {
402 /* With no u-boot we must set up a boot stub for the secondary CPU */
403 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
404 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
405 0x80, &error_abort);
406 memory_region_add_subregion(get_system_memory(),
407 AST_SMP_MAILBOX_BASE, smpboot);
408
409 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
410 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
411 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
412 }
413
414 aspeed_board_binfo.ram_size = machine->ram_size;
415 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
416 aspeed_board_binfo.nb_cpus = sc->num_cpus;
417
418 if (amc->i2c_init) {
419 amc->i2c_init(bmc);
420 }
421
422 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
423 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
424 }
425
426 if (bmc->soc.emmc.num_slots) {
427 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
428 }
429
430 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
431 }
432
433 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
434 {
435 AspeedSoCState *soc = &bmc->soc;
436 DeviceState *dev;
437 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
438
439 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
440 * enough to provide basic RTC features. Alarms will be missing */
441 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
442
443 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
444 eeprom_buf);
445
446 /* add a TMP423 temperature sensor */
447 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
448 "tmp423", 0x4c));
449 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
450 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
451 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
452 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
453 }
454
455 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
456 {
457 AspeedSoCState *soc = &bmc->soc;
458
459 /*
460 * The quanta-q71l platform expects tmp75s which are compatible with
461 * tmp105s.
462 */
463 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
464 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
465 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
466
467 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
468 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
469 /* TODO: Add Memory Riser i2c mux and eeproms. */
470
471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
473
474 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
475
476 /* i2c-7 */
477 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
478 /* - i2c@0: pmbus@59 */
479 /* - i2c@1: pmbus@58 */
480 /* - i2c@2: pmbus@58 */
481 /* - i2c@3: pmbus@59 */
482
483 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
484 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
485 }
486
487 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
488 {
489 AspeedSoCState *soc = &bmc->soc;
490 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
491
492 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
493 eeprom_buf);
494
495 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
497 TYPE_TMP105, 0x4d);
498
499 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
500 * plugged on the I2C bus header */
501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
502 }
503
504 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
505 {
506 /* Start with some devices on our I2C busses */
507 ast2500_evb_i2c_init(bmc);
508 }
509
510 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
511 {
512 AspeedSoCState *soc = &bmc->soc;
513
514 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
515 * good enough */
516 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
517 }
518
519 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
520 {
521 AspeedSoCState *soc = &bmc->soc;
522
523 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
524
525 /* The swift board expects a TMP275 but a TMP105 is compatible */
526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
527 /* The swift board expects a pca9551 but a pca9552 is compatible */
528 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
529
530 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
531 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
533
534 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
535 /* The swift board expects a pca9539 but a pca9552 is compatible */
536 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
537
538 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
539 /* The swift board expects a pca9539 but a pca9552 is compatible */
540 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
541 0x74);
542
543 /* The swift board expects a TMP275 but a TMP105 is compatible */
544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
545 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
546 }
547
548 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
549 {
550 AspeedSoCState *soc = &bmc->soc;
551
552 /* bus 2 : */
553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
555 /* bus 2 : pca9546 @ 0x73 */
556
557 /* bus 3 : pca9548 @ 0x70 */
558
559 /* bus 4 : */
560 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
561 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
562 eeprom4_54);
563 /* PCA9539 @ 0x76, but PCA9552 is compatible */
564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
565 /* PCA9539 @ 0x77, but PCA9552 is compatible */
566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
567
568 /* bus 6 : */
569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
571 /* bus 6 : pca9546 @ 0x73 */
572
573 /* bus 8 : */
574 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
575 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
576 eeprom8_56);
577 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
579 /* bus 8 : adc128d818 @ 0x1d */
580 /* bus 8 : adc128d818 @ 0x1f */
581
582 /*
583 * bus 13 : pca9548 @ 0x71
584 * - channel 3:
585 * - tmm421 @ 0x4c
586 * - tmp421 @ 0x4e
587 * - tmp421 @ 0x4f
588 */
589
590 }
591
592 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
593 {
594 static const struct {
595 unsigned gpio_id;
596 LEDColor color;
597 const char *description;
598 bool gpio_polarity;
599 } pca1_leds[] = {
600 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
601 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
602 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
603 };
604 AspeedSoCState *soc = &bmc->soc;
605 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
606 DeviceState *dev;
607 LEDState *led;
608
609 /* Bus 3: TODO bmp280@77 */
610 /* Bus 3: TODO max31785@52 */
611 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
612 qdev_prop_set_string(dev, "description", "pca1");
613 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
614 aspeed_i2c_get_bus(&soc->i2c, 3),
615 &error_fatal);
616
617 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
618 led = led_create_simple(OBJECT(bmc),
619 pca1_leds[i].gpio_polarity,
620 pca1_leds[i].color,
621 pca1_leds[i].description);
622 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
623 qdev_get_gpio_in(DEVICE(led), 0));
624 }
625 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
627 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
628
629 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
630 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
631 0x4a);
632
633 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
634 * good enough */
635 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
636
637 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
638 eeprom_buf);
639 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
640 qdev_prop_set_string(dev, "description", "pca0");
641 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
642 aspeed_i2c_get_bus(&soc->i2c, 11),
643 &error_fatal);
644 /* Bus 11: TODO ucd90160@64 */
645 }
646
647 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
648 {
649 AspeedSoCState *soc = &bmc->soc;
650 DeviceState *dev;
651
652 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
653 "emc1413", 0x4c));
654 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
655 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
656 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
657
658 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
659 "emc1413", 0x4c));
660 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
661 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
662 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
663
664 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
665 "emc1413", 0x4c));
666 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
667 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
668 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
669
670 static uint8_t eeprom_buf[2 * 1024] = {
671 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
672 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
673 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
674 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
675 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
676 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
677 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
678 };
679 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
680 eeprom_buf);
681 }
682
683 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
684 {
685 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
686 DeviceState *dev = DEVICE(i2c_dev);
687
688 qdev_prop_set_uint32(dev, "rom-size", rsize);
689 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
690 }
691
692 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
693 {
694 AspeedSoCState *soc = &bmc->soc;
695 I2CSlave *i2c_mux;
696
697 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
698
699 /* The rainier expects a TMP275 but a TMP105 is compatible */
700 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
701 0x48);
702 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
703 0x49);
704 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
705 0x4a);
706 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
707 "pca9546", 0x70);
708 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
709 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
710 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
711
712 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
713 0x48);
714 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
715 0x49);
716 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
717 "pca9546", 0x70);
718 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
719 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
720
721 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
722 0x48);
723 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
724 0x4a);
725 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
726 0x4b);
727 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
728 "pca9546", 0x70);
729 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
730 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
731 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
732 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
733
734 /* Bus 7: TODO max31785@52 */
735 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
736 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
737 /* Bus 7: TODO si7021-a20@20 */
738 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
739 0x48);
740 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
741 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
742
743 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
744 0x48);
745 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
746 0x4a);
747 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
748 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
750 /* Bus 8: ucd90320@11 */
751 /* Bus 8: ucd90320@b */
752 /* Bus 8: ucd90320@c */
753
754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
755 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
756 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
757
758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
759 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
760 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
761
762 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
763 0x48);
764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
765 0x49);
766 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
767 "pca9546", 0x70);
768 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
769 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
770
771
772 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
773
774 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
775
776 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
777 }
778
779 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
780 I2CBus **channels)
781 {
782 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
783 for (int i = 0; i < 8; i++) {
784 channels[i] = pca954x_i2c_get_bus(mux, i);
785 }
786 }
787
788 #define TYPE_LM75 TYPE_TMP105
789 #define TYPE_TMP75 TYPE_TMP105
790 #define TYPE_TMP422 "tmp422"
791
792 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
793 {
794 AspeedSoCState *soc = &bmc->soc;
795 I2CBus *i2c[144] = {};
796
797 for (int i = 0; i < 16; i++) {
798 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
799 }
800 I2CBus *i2c180 = i2c[2];
801 I2CBus *i2c480 = i2c[8];
802 I2CBus *i2c600 = i2c[11];
803
804 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
805 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
806 /* NOTE: The device tree skips [32, 40) in the alias numbering */
807 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
808 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
809 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
810 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
811 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
812 for (int i = 0; i < 8; i++) {
813 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
814 }
815
816 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
817 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
818
819 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
820 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
821 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
822
823 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
824 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
825 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
826 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
827
828 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
829 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
830
831 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
832 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
833 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
834 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
835
836 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
837 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
838
839 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
840 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
841 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
842 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
843 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
844 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
845 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
846
847 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
848 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
849 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
850 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
851 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
852 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
853 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
854 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
855
856 for (int i = 0; i < 8; i++) {
857 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
858 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
859 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
860 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
861 }
862 }
863
864 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
865 {
866 return ASPEED_MACHINE(obj)->mmio_exec;
867 }
868
869 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
870 {
871 ASPEED_MACHINE(obj)->mmio_exec = value;
872 }
873
874 static void aspeed_machine_instance_init(Object *obj)
875 {
876 ASPEED_MACHINE(obj)->mmio_exec = false;
877 }
878
879 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
880 {
881 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
882 return g_strdup(bmc->fmc_model);
883 }
884
885 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
886 {
887 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
888
889 g_free(bmc->fmc_model);
890 bmc->fmc_model = g_strdup(value);
891 }
892
893 static char *aspeed_get_spi_model(Object *obj, Error **errp)
894 {
895 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
896 return g_strdup(bmc->spi_model);
897 }
898
899 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
900 {
901 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
902
903 g_free(bmc->spi_model);
904 bmc->spi_model = g_strdup(value);
905 }
906
907 static void aspeed_machine_class_props_init(ObjectClass *oc)
908 {
909 object_class_property_add_bool(oc, "execute-in-place",
910 aspeed_get_mmio_exec,
911 aspeed_set_mmio_exec);
912 object_class_property_set_description(oc, "execute-in-place",
913 "boot directly from CE0 flash device");
914
915 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
916 aspeed_set_fmc_model);
917 object_class_property_set_description(oc, "fmc-model",
918 "Change the FMC Flash model");
919 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
920 aspeed_set_spi_model);
921 object_class_property_set_description(oc, "spi-model",
922 "Change the SPI Flash model");
923 }
924
925 static int aspeed_soc_num_cpus(const char *soc_name)
926 {
927 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
928 return sc->num_cpus;
929 }
930
931 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
932 {
933 MachineClass *mc = MACHINE_CLASS(oc);
934 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
935
936 mc->init = aspeed_machine_init;
937 mc->no_floppy = 1;
938 mc->no_cdrom = 1;
939 mc->no_parallel = 1;
940 mc->default_ram_id = "ram";
941 amc->macs_mask = ASPEED_MAC0_ON;
942 amc->uart_default = ASPEED_DEV_UART5;
943
944 aspeed_machine_class_props_init(oc);
945 }
946
947 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
948 {
949 MachineClass *mc = MACHINE_CLASS(oc);
950 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
951
952 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
953 amc->soc_name = "ast2400-a1";
954 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
955 amc->fmc_model = "n25q256a";
956 amc->spi_model = "mx25l25635e";
957 amc->num_cs = 1;
958 amc->i2c_init = palmetto_bmc_i2c_init;
959 mc->default_ram_size = 256 * MiB;
960 mc->default_cpus = mc->min_cpus = mc->max_cpus =
961 aspeed_soc_num_cpus(amc->soc_name);
962 };
963
964 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
965 {
966 MachineClass *mc = MACHINE_CLASS(oc);
967 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
968
969 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
970 amc->soc_name = "ast2400-a1";
971 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
972 amc->fmc_model = "n25q256a";
973 amc->spi_model = "mx25l25635e";
974 amc->num_cs = 1;
975 amc->i2c_init = quanta_q71l_bmc_i2c_init;
976 mc->default_ram_size = 128 * MiB;
977 mc->default_cpus = mc->min_cpus = mc->max_cpus =
978 aspeed_soc_num_cpus(amc->soc_name);
979 }
980
981 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
982 void *data)
983 {
984 MachineClass *mc = MACHINE_CLASS(oc);
985 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
986
987 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
988 amc->soc_name = "ast2400-a1";
989 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
990 amc->fmc_model = "mx25l25635e";
991 amc->spi_model = "mx25l25635e";
992 amc->num_cs = 1;
993 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
994 amc->i2c_init = palmetto_bmc_i2c_init;
995 mc->default_ram_size = 256 * MiB;
996 }
997
998 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
999 {
1000 MachineClass *mc = MACHINE_CLASS(oc);
1001 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1002
1003 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1004 amc->soc_name = "ast2500-a1";
1005 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1006 amc->fmc_model = "w25q256";
1007 amc->spi_model = "mx25l25635e";
1008 amc->num_cs = 1;
1009 amc->i2c_init = ast2500_evb_i2c_init;
1010 mc->default_ram_size = 512 * MiB;
1011 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1012 aspeed_soc_num_cpus(amc->soc_name);
1013 };
1014
1015 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1016 {
1017 MachineClass *mc = MACHINE_CLASS(oc);
1018 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1019
1020 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1021 amc->soc_name = "ast2500-a1";
1022 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1023 amc->fmc_model = "n25q256a";
1024 amc->spi_model = "mx66l1g45g";
1025 amc->num_cs = 2;
1026 amc->i2c_init = romulus_bmc_i2c_init;
1027 mc->default_ram_size = 512 * MiB;
1028 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1029 aspeed_soc_num_cpus(amc->soc_name);
1030 };
1031
1032 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1033 {
1034 MachineClass *mc = MACHINE_CLASS(oc);
1035 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1036
1037 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1038 amc->soc_name = "ast2500-a1";
1039 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1040 amc->fmc_model = "mx66l1g45g";
1041 amc->spi_model = "mx66l1g45g";
1042 amc->num_cs = 2;
1043 amc->i2c_init = sonorapass_bmc_i2c_init;
1044 mc->default_ram_size = 512 * MiB;
1045 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1046 aspeed_soc_num_cpus(amc->soc_name);
1047 };
1048
1049 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
1050 {
1051 MachineClass *mc = MACHINE_CLASS(oc);
1052 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1053
1054 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
1055 amc->soc_name = "ast2500-a1";
1056 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
1057 amc->fmc_model = "mx66l1g45g";
1058 amc->spi_model = "mx66l1g45g";
1059 amc->num_cs = 2;
1060 amc->i2c_init = swift_bmc_i2c_init;
1061 mc->default_ram_size = 512 * MiB;
1062 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1063 aspeed_soc_num_cpus(amc->soc_name);
1064
1065 mc->deprecation_reason = "redundant system. Please use a similar "
1066 "OpenPOWER BMC, Witherspoon or Romulus.";
1067 };
1068
1069 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1070 {
1071 MachineClass *mc = MACHINE_CLASS(oc);
1072 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1073
1074 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1075 amc->soc_name = "ast2500-a1";
1076 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1077 amc->fmc_model = "mx25l25635e";
1078 amc->spi_model = "mx66l1g45g";
1079 amc->num_cs = 2;
1080 amc->i2c_init = witherspoon_bmc_i2c_init;
1081 mc->default_ram_size = 512 * MiB;
1082 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1083 aspeed_soc_num_cpus(amc->soc_name);
1084 };
1085
1086 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1087 {
1088 MachineClass *mc = MACHINE_CLASS(oc);
1089 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1090
1091 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1092 amc->soc_name = "ast2600-a3";
1093 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1094 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1095 amc->fmc_model = "w25q512jv";
1096 amc->spi_model = "mx66u51235f";
1097 amc->num_cs = 1;
1098 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1099 ASPEED_MAC3_ON;
1100 amc->i2c_init = ast2600_evb_i2c_init;
1101 mc->default_ram_size = 1 * GiB;
1102 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1103 aspeed_soc_num_cpus(amc->soc_name);
1104 };
1105
1106 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1107 {
1108 MachineClass *mc = MACHINE_CLASS(oc);
1109 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1110
1111 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1112 amc->soc_name = "ast2600-a3";
1113 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1114 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1115 amc->fmc_model = "mx66l1g45g";
1116 amc->spi_model = "mx66l1g45g";
1117 amc->num_cs = 2;
1118 amc->macs_mask = ASPEED_MAC2_ON;
1119 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1120 mc->default_ram_size = 1 * GiB;
1121 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1122 aspeed_soc_num_cpus(amc->soc_name);
1123 };
1124
1125 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1126 {
1127 MachineClass *mc = MACHINE_CLASS(oc);
1128 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1129
1130 mc->desc = "Bytedance G220A BMC (ARM1176)";
1131 amc->soc_name = "ast2500-a1";
1132 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1133 amc->fmc_model = "n25q512a";
1134 amc->spi_model = "mx25l25635e";
1135 amc->num_cs = 2;
1136 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1137 amc->i2c_init = g220a_bmc_i2c_init;
1138 mc->default_ram_size = 1024 * MiB;
1139 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1140 aspeed_soc_num_cpus(amc->soc_name);
1141 };
1142
1143 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1144 {
1145 MachineClass *mc = MACHINE_CLASS(oc);
1146 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1147
1148 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1149 amc->soc_name = "ast2600-a3";
1150 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1151 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1152 amc->fmc_model = "mx66l1g45g";
1153 amc->spi_model = "mx66l1g45g";
1154 amc->num_cs = 2;
1155 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1156 amc->i2c_init = rainier_bmc_i2c_init;
1157 mc->default_ram_size = 1 * GiB;
1158 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1159 aspeed_soc_num_cpus(amc->soc_name);
1160 };
1161
1162 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1163 #if HOST_LONG_BITS == 32
1164 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1165 #else
1166 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1167 #endif
1168
1169 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1170 {
1171 MachineClass *mc = MACHINE_CLASS(oc);
1172 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1173
1174 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1175 amc->soc_name = "ast2600-a3";
1176 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1177 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1178 amc->fmc_model = "mx66l1g45g";
1179 amc->spi_model = "mx66l1g45g";
1180 amc->num_cs = 2;
1181 amc->macs_mask = ASPEED_MAC3_ON;
1182 amc->i2c_init = fuji_bmc_i2c_init;
1183 amc->uart_default = ASPEED_DEV_UART1;
1184 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1185 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1186 aspeed_soc_num_cpus(amc->soc_name);
1187 };
1188
1189 static const TypeInfo aspeed_machine_types[] = {
1190 {
1191 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1192 .parent = TYPE_ASPEED_MACHINE,
1193 .class_init = aspeed_machine_palmetto_class_init,
1194 }, {
1195 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1196 .parent = TYPE_ASPEED_MACHINE,
1197 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1198 }, {
1199 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1200 .parent = TYPE_ASPEED_MACHINE,
1201 .class_init = aspeed_machine_ast2500_evb_class_init,
1202 }, {
1203 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1204 .parent = TYPE_ASPEED_MACHINE,
1205 .class_init = aspeed_machine_romulus_class_init,
1206 }, {
1207 .name = MACHINE_TYPE_NAME("swift-bmc"),
1208 .parent = TYPE_ASPEED_MACHINE,
1209 .class_init = aspeed_machine_swift_class_init,
1210 }, {
1211 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1212 .parent = TYPE_ASPEED_MACHINE,
1213 .class_init = aspeed_machine_sonorapass_class_init,
1214 }, {
1215 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1216 .parent = TYPE_ASPEED_MACHINE,
1217 .class_init = aspeed_machine_witherspoon_class_init,
1218 }, {
1219 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1220 .parent = TYPE_ASPEED_MACHINE,
1221 .class_init = aspeed_machine_ast2600_evb_class_init,
1222 }, {
1223 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1224 .parent = TYPE_ASPEED_MACHINE,
1225 .class_init = aspeed_machine_tacoma_class_init,
1226 }, {
1227 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1228 .parent = TYPE_ASPEED_MACHINE,
1229 .class_init = aspeed_machine_g220a_class_init,
1230 }, {
1231 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1232 .parent = TYPE_ASPEED_MACHINE,
1233 .class_init = aspeed_machine_quanta_q71l_class_init,
1234 }, {
1235 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1236 .parent = TYPE_ASPEED_MACHINE,
1237 .class_init = aspeed_machine_rainier_class_init,
1238 }, {
1239 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1240 .parent = TYPE_ASPEED_MACHINE,
1241 .class_init = aspeed_machine_fuji_class_init,
1242 }, {
1243 .name = TYPE_ASPEED_MACHINE,
1244 .parent = TYPE_MACHINE,
1245 .instance_size = sizeof(AspeedMachineState),
1246 .instance_init = aspeed_machine_instance_init,
1247 .class_size = sizeof(AspeedMachineClass),
1248 .class_init = aspeed_machine_class_init,
1249 .abstract = true,
1250 }
1251 };
1252
1253 DEFINE_TYPES(aspeed_machine_types)
Ray Wang's QEMU Repository