util/cacheinfo.c

   1 /*
   2  * cacheinfo.c - helpers to query the host about its caches
   3  *
   4  * Copyright (C) 2017, Emilio G. Cota <cota@braap.org>
   5  * License: GNU GPL, version 2 or later.
   6  *   See the COPYING file in the top-level directory.
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "qemu/host-utils.h"
  11 #include "qemu/atomic.h"
  12 #include "qemu/cacheinfo.h"
  13
  14 int qemu_icache_linesize = 0;
  15 int qemu_icache_linesize_log;
  16 int qemu_dcache_linesize = 0;
  17 int qemu_dcache_linesize_log;
  18
  19 /*
  20  * Operating system specific detection mechanisms.
  21  */
  22
  23 #if defined(_WIN32)
  24
  25 static void sys_cache_info(int *isize, int *dsize)
  26 {
  27     SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf;
  28     DWORD size = 0;
  29     BOOL success;
  30     size_t i, n;
  31
  32     /* Check for the required buffer size first.  Note that if the zero
  33        size we use for the probe results in success, then there is no
  34        data available; fail in that case.  */
  35     success = GetLogicalProcessorInformation(0, &size);
  36     if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
  37         return;
  38     }
  39
  40     n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
  41     size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
  42     buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n);
  43     if (!GetLogicalProcessorInformation(buf, &size)) {
  44         goto fail;
  45     }
  46
  47     for (i = 0; i < n; i++) {
  48         if (buf[i].Relationship == RelationCache
  49             && buf[i].Cache.Level == 1) {
  50             switch (buf[i].Cache.Type) {
  51             case CacheUnified:
  52                 *isize = *dsize = buf[i].Cache.LineSize;
  53                 break;
  54             case CacheInstruction:
  55                 *isize = buf[i].Cache.LineSize;
  56                 break;
  57             case CacheData:
  58                 *dsize = buf[i].Cache.LineSize;
  59                 break;
  60             default:
  61                 break;
  62             }
  63         }
  64     }
  65  fail:
  66     g_free(buf);
  67 }
  68
  69 #elif defined(__APPLE__)
  70 # include <sys/sysctl.h>
  71 static void sys_cache_info(int *isize, int *dsize)
  72 {
  73     /* There's only a single sysctl for both I/D cache line sizes.  */
  74     long size;
  75     size_t len = sizeof(size);
  76     if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) {
  77         *isize = *dsize = size;
  78     }
  79 }
  80 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
  81 # include <sys/sysctl.h>
  82 static void sys_cache_info(int *isize, int *dsize)
  83 {
  84     /* There's only a single sysctl for both I/D cache line sizes.  */
  85     int size;
  86     size_t len = sizeof(size);
  87     if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) {
  88         *isize = *dsize = size;
  89     }
  90 }
  91 #else
  92 /* POSIX */
  93
  94 static void sys_cache_info(int *isize, int *dsize)
  95 {
  96 # ifdef _SC_LEVEL1_ICACHE_LINESIZE
  97     int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
  98     if (tmp_isize > 0) {
  99         *isize = tmp_isize;
 100     }
 101 # endif
 102 # ifdef _SC_LEVEL1_DCACHE_LINESIZE
 103     int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
 104     if (tmp_dsize > 0) {
 105         *dsize = tmp_dsize;
 106     }
 107 # endif
 108 }
 109 #endif /* sys_cache_info */
 110
 111 /*
 112  * Architecture (+ OS) specific detection mechanisms.
 113  */
 114
 115 #if defined(__aarch64__)
 116
 117 static void arch_cache_info(int *isize, int *dsize)
 118 {
 119     if (*isize == 0 || *dsize == 0) {
 120         uint64_t ctr;
 121
 122         /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
 123            but (at least under Linux) these are marked protected by the
 124            kernel.  However, CTR_EL0 contains the minimum linesize in the
 125            entire hierarchy, and is used by userspace cache flushing.  */
 126         asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
 127         if (*isize == 0) {
 128             *isize = 4 << (ctr & 0xf);
 129         }
 130         if (*dsize == 0) {
 131             *dsize = 4 << ((ctr >> 16) & 0xf);
 132         }
 133     }
 134 }
 135
 136 #elif defined(_ARCH_PPC) && defined(__linux__)
 137 # include "elf.h"
 138
 139 static void arch_cache_info(int *isize, int *dsize)
 140 {
 141     if (*isize == 0) {
 142         *isize = qemu_getauxval(AT_ICACHEBSIZE);
 143     }
 144     if (*dsize == 0) {
 145         *dsize = qemu_getauxval(AT_DCACHEBSIZE);
 146     }
 147 }
 148
 149 #else
 150 static void arch_cache_info(int *isize, int *dsize) { }
 151 #endif /* arch_cache_info */
 152
 153 /*
 154  * ... and if all else fails ...
 155  */
 156
 157 static void fallback_cache_info(int *isize, int *dsize)
 158 {
 159     /* If we can only find one of the two, assume they're the same.  */
 160     if (*isize) {
 161         if (*dsize) {
 162             /* Success! */
 163         } else {
 164             *dsize = *isize;
 165         }
 166     } else if (*dsize) {
 167         *isize = *dsize;
 168     } else {
 169 #if defined(_ARCH_PPC)
 170         /*
 171          * For PPC, we're going to use the cache sizes computed for
 172          * flush_idcache_range.  Which means that we must use the
 173          * architecture minimum.
 174          */
 175         *isize = *dsize = 16;
 176 #else
 177         /* Otherwise, 64 bytes is not uncommon.  */
 178         *isize = *dsize = 64;
 179 #endif
 180     }
 181 }
 182
 183 static void __attribute__((constructor)) init_cache_info(void)
 184 {
 185     int isize = 0, dsize = 0;
 186
 187     sys_cache_info(&isize, &dsize);
 188     arch_cache_info(&isize, &dsize);
 189     fallback_cache_info(&isize, &dsize);
 190
 191     assert((isize & (isize - 1)) == 0);
 192     assert((dsize & (dsize - 1)) == 0);
 193
 194     qemu_icache_linesize = isize;
 195     qemu_icache_linesize_log = ctz32(isize);
 196     qemu_dcache_linesize = dsize;
 197     qemu_dcache_linesize_log = ctz32(dsize);
 198
 199     qatomic64_init();
 200 }