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hostmem: add merge and dump properties
[qemu/rayw.git] / target-ppc / translate.c
blob48017219a4ac25594b160ea85bee5fa1cb598067
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 + 10*4 + 22*5 /* SPE GPRh */
50 + 10*4 + 22*5 /* FPR */
51 + 2*(10*6 + 22*7) /* AVRh, AVRl */
52 + 10*5 + 22*6 /* VSR */
53 + 8*5 /* CRF */];
54 static TCGv cpu_gpr[32];
55 static TCGv cpu_gprh[32];
56 static TCGv_i64 cpu_fpr[32];
57 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
58 static TCGv_i64 cpu_vsr[32];
59 static TCGv_i32 cpu_crf[8];
60 static TCGv cpu_nip;
61 static TCGv cpu_msr;
62 static TCGv cpu_ctr;
63 static TCGv cpu_lr;
64 #if defined(TARGET_PPC64)
65 static TCGv cpu_cfar;
66 #endif
67 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
68 static TCGv cpu_reserve;
69 static TCGv cpu_fpscr;
70 static TCGv_i32 cpu_access_type;
71
72 #include "exec/gen-icount.h"
73
74 void ppc_translate_init(void)
75 {
76 int i;
77 char* p;
78 size_t cpu_reg_names_size;
79 static int done_init = 0;
80
81 if (done_init)
82 return;
83
84 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
85
86 p = cpu_reg_names;
87 cpu_reg_names_size = sizeof(cpu_reg_names);
88
89 for (i = 0; i < 8; i++) {
90 snprintf(p, cpu_reg_names_size, "crf%d", i);
91 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
92 offsetof(CPUPPCState, crf[i]), p);
93 p += 5;
94 cpu_reg_names_size -= 5;
95 }
96
97 for (i = 0; i < 32; i++) {
98 snprintf(p, cpu_reg_names_size, "r%d", i);
99 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
100 offsetof(CPUPPCState, gpr[i]), p);
101 p += (i < 10) ? 3 : 4;
102 cpu_reg_names_size -= (i < 10) ? 3 : 4;
103 snprintf(p, cpu_reg_names_size, "r%dH", i);
104 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
105 offsetof(CPUPPCState, gprh[i]), p);
106 p += (i < 10) ? 4 : 5;
107 cpu_reg_names_size -= (i < 10) ? 4 : 5;
108
109 snprintf(p, cpu_reg_names_size, "fp%d", i);
110 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
111 offsetof(CPUPPCState, fpr[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "avr%dH", i);
116 #ifdef HOST_WORDS_BIGENDIAN
117 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUPPCState, avr[i].u64[0]), p);
119 #else
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[1]), p);
122 #endif
123 p += (i < 10) ? 6 : 7;
124 cpu_reg_names_size -= (i < 10) ? 6 : 7;
125
126 snprintf(p, cpu_reg_names_size, "avr%dL", i);
127 #ifdef HOST_WORDS_BIGENDIAN
128 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
129 offsetof(CPUPPCState, avr[i].u64[1]), p);
130 #else
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[0]), p);
133 #endif
134 p += (i < 10) ? 6 : 7;
135 cpu_reg_names_size -= (i < 10) ? 6 : 7;
136 snprintf(p, cpu_reg_names_size, "vsr%d", i);
137 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, vsr[i]), p);
139 p += (i < 10) ? 5 : 6;
140 cpu_reg_names_size -= (i < 10) ? 5 : 6;
141 }
142
143 cpu_nip = tcg_global_mem_new(TCG_AREG0,
144 offsetof(CPUPPCState, nip), "nip");
145
146 cpu_msr = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, msr), "msr");
148
149 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, ctr), "ctr");
151
152 cpu_lr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, lr), "lr");
154
155 #if defined(TARGET_PPC64)
156 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
157 offsetof(CPUPPCState, cfar), "cfar");
158 #endif
159
160 cpu_xer = tcg_global_mem_new(TCG_AREG0,
161 offsetof(CPUPPCState, xer), "xer");
162 cpu_so = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, so), "SO");
164 cpu_ov = tcg_global_mem_new(TCG_AREG0,
165 offsetof(CPUPPCState, ov), "OV");
166 cpu_ca = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, ca), "CA");
168
169 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, reserve_addr),
171 "reserve_addr");
172
173 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
174 offsetof(CPUPPCState, fpscr), "fpscr");
175
176 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
177 offsetof(CPUPPCState, access_type), "access_type");
178
179 done_init = 1;
180 }
181
182 /* internal defines */
183 typedef struct DisasContext {
184 struct TranslationBlock *tb;
185 target_ulong nip;
186 uint32_t opcode;
187 uint32_t exception;
188 /* Routine used to access memory */
189 int mem_idx;
190 int access_type;
191 /* Translation flags */
192 int le_mode;
193 TCGMemOp default_tcg_memop_mask;
194 #if defined(TARGET_PPC64)
195 int sf_mode;
196 int has_cfar;
197 #endif
198 int fpu_enabled;
199 int altivec_enabled;
200 int vsx_enabled;
201 int spe_enabled;
202 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
203 int singlestep_enabled;
204 uint64_t insns_flags;
205 uint64_t insns_flags2;
206 } DisasContext;
207
208 /* Return true iff byteswap is needed in a scalar memop */
209 static inline bool need_byteswap(const DisasContext *ctx)
210 {
211 #if defined(TARGET_WORDS_BIGENDIAN)
212 return ctx->le_mode;
213 #else
214 return !ctx->le_mode;
215 #endif
216 }
217
218 /* True when active word size < size of target_long. */
219 #ifdef TARGET_PPC64
220 # define NARROW_MODE(C) (!(C)->sf_mode)
221 #else
222 # define NARROW_MODE(C) 0
223 #endif
224
225 struct opc_handler_t {
226 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
227 uint32_t inval1;
228 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
229 uint32_t inval2;
230 /* instruction type */
231 uint64_t type;
232 /* extended instruction type */
233 uint64_t type2;
234 /* handler */
235 void (*handler)(DisasContext *ctx);
236 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
237 const char *oname;
238 #endif
239 #if defined(DO_PPC_STATISTICS)
240 uint64_t count;
241 #endif
242 };
243
244 static inline void gen_reset_fpstatus(void)
245 {
246 gen_helper_reset_fpstatus(cpu_env);
247 }
248
249 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
250 {
251 TCGv_i32 t0 = tcg_temp_new_i32();
252
253 if (set_fprf != 0) {
254 /* This case might be optimized later */
255 tcg_gen_movi_i32(t0, 1);
256 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
257 if (unlikely(set_rc)) {
258 tcg_gen_mov_i32(cpu_crf[1], t0);
259 }
260 gen_helper_float_check_status(cpu_env);
261 } else if (unlikely(set_rc)) {
262 /* We always need to compute fpcc */
263 tcg_gen_movi_i32(t0, 0);
264 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
265 tcg_gen_mov_i32(cpu_crf[1], t0);
266 }
267
268 tcg_temp_free_i32(t0);
269 }
270
271 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
272 {
273 if (ctx->access_type != access_type) {
274 tcg_gen_movi_i32(cpu_access_type, access_type);
275 ctx->access_type = access_type;
276 }
277 }
278
279 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
280 {
281 if (NARROW_MODE(ctx)) {
282 nip = (uint32_t)nip;
283 }
284 tcg_gen_movi_tl(cpu_nip, nip);
285 }
286
287 void gen_update_current_nip(void *opaque)
288 {
289 DisasContext *ctx = opaque;
290
291 tcg_gen_movi_tl(cpu_nip, ctx->nip);
292 }
293
294 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
295 {
296 TCGv_i32 t0, t1;
297 if (ctx->exception == POWERPC_EXCP_NONE) {
298 gen_update_nip(ctx, ctx->nip);
299 }
300 t0 = tcg_const_i32(excp);
301 t1 = tcg_const_i32(error);
302 gen_helper_raise_exception_err(cpu_env, t0, t1);
303 tcg_temp_free_i32(t0);
304 tcg_temp_free_i32(t1);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
309 {
310 TCGv_i32 t0;
311 if (ctx->exception == POWERPC_EXCP_NONE) {
312 gen_update_nip(ctx, ctx->nip);
313 }
314 t0 = tcg_const_i32(excp);
315 gen_helper_raise_exception(cpu_env, t0);
316 tcg_temp_free_i32(t0);
317 ctx->exception = (excp);
318 }
319
320 static inline void gen_debug_exception(DisasContext *ctx)
321 {
322 TCGv_i32 t0;
323
324 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
325 (ctx->exception != POWERPC_EXCP_SYNC)) {
326 gen_update_nip(ctx, ctx->nip);
327 }
328 t0 = tcg_const_i32(EXCP_DEBUG);
329 gen_helper_raise_exception(cpu_env, t0);
330 tcg_temp_free_i32(t0);
331 }
332
333 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
334 {
335 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
336 }
337
338 /* Stop translation */
339 static inline void gen_stop_exception(DisasContext *ctx)
340 {
341 gen_update_nip(ctx, ctx->nip);
342 ctx->exception = POWERPC_EXCP_STOP;
343 }
344
345 /* No need to update nip here, as execution flow will change */
346 static inline void gen_sync_exception(DisasContext *ctx)
347 {
348 ctx->exception = POWERPC_EXCP_SYNC;
349 }
350
351 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
352 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
353
354 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
355 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
356
357 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
358 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
359
360 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
361 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
362
363 typedef struct opcode_t {
364 unsigned char opc1, opc2, opc3;
365 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
366 unsigned char pad[5];
367 #else
368 unsigned char pad[1];
369 #endif
370 opc_handler_t handler;
371 const char *oname;
372 } opcode_t;
373
374 /*****************************************************************************/
375 /*** Instruction decoding ***/
376 #define EXTRACT_HELPER(name, shift, nb) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
380 }
381
382 #define EXTRACT_SHELPER(name, shift, nb) \
383 static inline int32_t name(uint32_t opcode) \
384 { \
385 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
386 }
387
388 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
389 static inline uint32_t name(uint32_t opcode) \
390 { \
391 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
392 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
393 }
394 /* Opcode part 1 */
395 EXTRACT_HELPER(opc1, 26, 6);
396 /* Opcode part 2 */
397 EXTRACT_HELPER(opc2, 1, 5);
398 /* Opcode part 3 */
399 EXTRACT_HELPER(opc3, 6, 5);
400 /* Update Cr0 flags */
401 EXTRACT_HELPER(Rc, 0, 1);
402 /* Update Cr6 flags (Altivec) */
403 EXTRACT_HELPER(Rc21, 10, 1);
404 /* Destination */
405 EXTRACT_HELPER(rD, 21, 5);
406 /* Source */
407 EXTRACT_HELPER(rS, 21, 5);
408 /* First operand */
409 EXTRACT_HELPER(rA, 16, 5);
410 /* Second operand */
411 EXTRACT_HELPER(rB, 11, 5);
412 /* Third operand */
413 EXTRACT_HELPER(rC, 6, 5);
414 /*** Get CRn ***/
415 EXTRACT_HELPER(crfD, 23, 3);
416 EXTRACT_HELPER(crfS, 18, 3);
417 EXTRACT_HELPER(crbD, 21, 5);
418 EXTRACT_HELPER(crbA, 16, 5);
419 EXTRACT_HELPER(crbB, 11, 5);
420 /* SPR / TBL */
421 EXTRACT_HELPER(_SPR, 11, 10);
422 static inline uint32_t SPR(uint32_t opcode)
423 {
424 uint32_t sprn = _SPR(opcode);
425
426 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
427 }
428 /*** Get constants ***/
429 EXTRACT_HELPER(IMM, 12, 8);
430 /* 16 bits signed immediate value */
431 EXTRACT_SHELPER(SIMM, 0, 16);
432 /* 16 bits unsigned immediate value */
433 EXTRACT_HELPER(UIMM, 0, 16);
434 /* 5 bits signed immediate value */
435 EXTRACT_HELPER(SIMM5, 16, 5);
436 /* 5 bits signed immediate value */
437 EXTRACT_HELPER(UIMM5, 16, 5);
438 /* Bit count */
439 EXTRACT_HELPER(NB, 11, 5);
440 /* Shift count */
441 EXTRACT_HELPER(SH, 11, 5);
442 /* Vector shift count */
443 EXTRACT_HELPER(VSH, 6, 4);
444 /* Mask start */
445 EXTRACT_HELPER(MB, 6, 5);
446 /* Mask end */
447 EXTRACT_HELPER(ME, 1, 5);
448 /* Trap operand */
449 EXTRACT_HELPER(TO, 21, 5);
450
451 EXTRACT_HELPER(CRM, 12, 8);
452 EXTRACT_HELPER(SR, 16, 4);
453
454 /* mtfsf/mtfsfi */
455 EXTRACT_HELPER(FPBF, 23, 3);
456 EXTRACT_HELPER(FPIMM, 12, 4);
457 EXTRACT_HELPER(FPL, 25, 1);
458 EXTRACT_HELPER(FPFLM, 17, 8);
459 EXTRACT_HELPER(FPW, 16, 1);
460
461 /*** Jump target decoding ***/
462 /* Displacement */
463 EXTRACT_SHELPER(d, 0, 16);
464 /* Immediate address */
465 static inline target_ulong LI(uint32_t opcode)
466 {
467 return (opcode >> 0) & 0x03FFFFFC;
468 }
469
470 static inline uint32_t BD(uint32_t opcode)
471 {
472 return (opcode >> 0) & 0xFFFC;
473 }
474
475 EXTRACT_HELPER(BO, 21, 5);
476 EXTRACT_HELPER(BI, 16, 5);
477 /* Absolute/relative address */
478 EXTRACT_HELPER(AA, 1, 1);
479 /* Link */
480 EXTRACT_HELPER(LK, 0, 1);
481
482 /* DFP Z22-form */
483 EXTRACT_HELPER(DCM, 10, 6)
484
485 /* DFP Z23-form */
486 EXTRACT_HELPER(RMC, 9, 2)
487
488 /* Create a mask between <start> and <end> bits */
489 static inline target_ulong MASK(uint32_t start, uint32_t end)
490 {
491 target_ulong ret;
492
493 #if defined(TARGET_PPC64)
494 if (likely(start == 0)) {
495 ret = UINT64_MAX << (63 - end);
496 } else if (likely(end == 63)) {
497 ret = UINT64_MAX >> start;
498 }
499 #else
500 if (likely(start == 0)) {
501 ret = UINT32_MAX << (31 - end);
502 } else if (likely(end == 31)) {
503 ret = UINT32_MAX >> start;
504 }
505 #endif
506 else {
507 ret = (((target_ulong)(-1ULL)) >> (start)) ^
508 (((target_ulong)(-1ULL) >> (end)) >> 1);
509 if (unlikely(start > end))
510 return ~ret;
511 }
512
513 return ret;
514 }
515
516 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
517 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
518 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
519 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
520 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
521 EXTRACT_HELPER(DM, 8, 2);
522 EXTRACT_HELPER(UIM, 16, 2);
523 EXTRACT_HELPER(SHW, 8, 2);
524 EXTRACT_HELPER(SP, 19, 2);
525 /*****************************************************************************/
526 /* PowerPC instructions table */
527
528 #if defined(DO_PPC_STATISTICS)
529 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
530 { \
531 .opc1 = op1, \
532 .opc2 = op2, \
533 .opc3 = op3, \
534 .pad = { 0, }, \
535 .handler = { \
536 .inval1 = invl, \
537 .type = _typ, \
538 .type2 = _typ2, \
539 .handler = &gen_##name, \
540 .oname = stringify(name), \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 .oname = stringify(name), \
557 }, \
558 .oname = stringify(name), \
559 }
560 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
561 { \
562 .opc1 = op1, \
563 .opc2 = op2, \
564 .opc3 = op3, \
565 .pad = { 0, }, \
566 .handler = { \
567 .inval1 = invl, \
568 .type = _typ, \
569 .type2 = _typ2, \
570 .handler = &gen_##name, \
571 .oname = onam, \
572 }, \
573 .oname = onam, \
574 }
575 #else
576 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
577 { \
578 .opc1 = op1, \
579 .opc2 = op2, \
580 .opc3 = op3, \
581 .pad = { 0, }, \
582 .handler = { \
583 .inval1 = invl, \
584 .type = _typ, \
585 .type2 = _typ2, \
586 .handler = &gen_##name, \
587 }, \
588 .oname = stringify(name), \
589 }
590 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
591 { \
592 .opc1 = op1, \
593 .opc2 = op2, \
594 .opc3 = op3, \
595 .pad = { 0, }, \
596 .handler = { \
597 .inval1 = invl1, \
598 .inval2 = invl2, \
599 .type = _typ, \
600 .type2 = _typ2, \
601 .handler = &gen_##name, \
602 }, \
603 .oname = stringify(name), \
604 }
605 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
606 { \
607 .opc1 = op1, \
608 .opc2 = op2, \
609 .opc3 = op3, \
610 .pad = { 0, }, \
611 .handler = { \
612 .inval1 = invl, \
613 .type = _typ, \
614 .type2 = _typ2, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618 }
619 #endif
620
621 /* SPR load/store helpers */
622 static inline void gen_load_spr(TCGv t, int reg)
623 {
624 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
625 }
626
627 static inline void gen_store_spr(int reg, TCGv t)
628 {
629 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
630 }
631
632 /* Invalid instruction */
633 static void gen_invalid(DisasContext *ctx)
634 {
635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
636 }
637
638 static opc_handler_t invalid_handler = {
639 .inval1 = 0xFFFFFFFF,
640 .inval2 = 0xFFFFFFFF,
641 .type = PPC_NONE,
642 .type2 = PPC_NONE,
643 .handler = gen_invalid,
644 };
645
646 #if defined(TARGET_PPC64)
647 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
648 /* so the function is wrapped in the standard 64-bit ifdef in order to */
649 /* avoid compiler warnings in 32-bit implementations. */
650 static bool is_user_mode(DisasContext *ctx)
651 {
652 #if defined(CONFIG_USER_ONLY)
653 return true;
654 #else
655 return ctx->mem_idx == 0;
656 #endif
657 }
658 #endif
659
660 /*** Integer comparison ***/
661
662 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
663 {
664 TCGv t0 = tcg_temp_new();
665 TCGv_i32 t1 = tcg_temp_new_i32();
666
667 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
668
669 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
670 tcg_gen_trunc_tl_i32(t1, t0);
671 tcg_gen_shli_i32(t1, t1, CRF_LT);
672 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
673
674 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
675 tcg_gen_trunc_tl_i32(t1, t0);
676 tcg_gen_shli_i32(t1, t1, CRF_GT);
677 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
678
679 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
680 tcg_gen_trunc_tl_i32(t1, t0);
681 tcg_gen_shli_i32(t1, t1, CRF_EQ);
682 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
683
684 tcg_temp_free(t0);
685 tcg_temp_free_i32(t1);
686 }
687
688 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
689 {
690 TCGv t0 = tcg_const_tl(arg1);
691 gen_op_cmp(arg0, t0, s, crf);
692 tcg_temp_free(t0);
693 }
694
695 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
696 {
697 TCGv t0, t1;
698 t0 = tcg_temp_new();
699 t1 = tcg_temp_new();
700 if (s) {
701 tcg_gen_ext32s_tl(t0, arg0);
702 tcg_gen_ext32s_tl(t1, arg1);
703 } else {
704 tcg_gen_ext32u_tl(t0, arg0);
705 tcg_gen_ext32u_tl(t1, arg1);
706 }
707 gen_op_cmp(t0, t1, s, crf);
708 tcg_temp_free(t1);
709 tcg_temp_free(t0);
710 }
711
712 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
713 {
714 TCGv t0 = tcg_const_tl(arg1);
715 gen_op_cmp32(arg0, t0, s, crf);
716 tcg_temp_free(t0);
717 }
718
719 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
720 {
721 if (NARROW_MODE(ctx)) {
722 gen_op_cmpi32(reg, 0, 1, 0);
723 } else {
724 gen_op_cmpi(reg, 0, 1, 0);
725 }
726 }
727
728 /* cmp */
729 static void gen_cmp(DisasContext *ctx)
730 {
731 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
732 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
733 1, crfD(ctx->opcode));
734 } else {
735 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 1, crfD(ctx->opcode));
737 }
738 }
739
740 /* cmpi */
741 static void gen_cmpi(DisasContext *ctx)
742 {
743 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
744 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
745 1, crfD(ctx->opcode));
746 } else {
747 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
748 1, crfD(ctx->opcode));
749 }
750 }
751
752 /* cmpl */
753 static void gen_cmpl(DisasContext *ctx)
754 {
755 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
756 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
757 0, crfD(ctx->opcode));
758 } else {
759 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
760 0, crfD(ctx->opcode));
761 }
762 }
763
764 /* cmpli */
765 static void gen_cmpli(DisasContext *ctx)
766 {
767 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
768 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
769 0, crfD(ctx->opcode));
770 } else {
771 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
772 0, crfD(ctx->opcode));
773 }
774 }
775
776 /* isel (PowerPC 2.03 specification) */
777 static void gen_isel(DisasContext *ctx)
778 {
779 int l1, l2;
780 uint32_t bi = rC(ctx->opcode);
781 uint32_t mask;
782 TCGv_i32 t0;
783
784 l1 = gen_new_label();
785 l2 = gen_new_label();
786
787 mask = 1 << (3 - (bi & 0x03));
788 t0 = tcg_temp_new_i32();
789 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
790 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
791 if (rA(ctx->opcode) == 0)
792 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
793 else
794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
795 tcg_gen_br(l2);
796 gen_set_label(l1);
797 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
798 gen_set_label(l2);
799 tcg_temp_free_i32(t0);
800 }
801
802 /* cmpb: PowerPC 2.05 specification */
803 static void gen_cmpb(DisasContext *ctx)
804 {
805 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
806 cpu_gpr[rB(ctx->opcode)]);
807 }
808
809 /*** Integer arithmetic ***/
810
811 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
812 TCGv arg1, TCGv arg2, int sub)
813 {
814 TCGv t0 = tcg_temp_new();
815
816 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
817 tcg_gen_xor_tl(t0, arg1, arg2);
818 if (sub) {
819 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
820 } else {
821 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
822 }
823 tcg_temp_free(t0);
824 if (NARROW_MODE(ctx)) {
825 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
826 }
827 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
828 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
829 }
830
831 /* Common add function */
832 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
833 TCGv arg2, bool add_ca, bool compute_ca,
834 bool compute_ov, bool compute_rc0)
835 {
836 TCGv t0 = ret;
837
838 if (compute_ca || compute_ov) {
839 t0 = tcg_temp_new();
840 }
841
842 if (compute_ca) {
843 if (NARROW_MODE(ctx)) {
844 /* Caution: a non-obvious corner case of the spec is that we
845 must produce the *entire* 64-bit addition, but produce the
846 carry into bit 32. */
847 TCGv t1 = tcg_temp_new();
848 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
849 tcg_gen_add_tl(t0, arg1, arg2);
850 if (add_ca) {
851 tcg_gen_add_tl(t0, t0, cpu_ca);
852 }
853 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
854 tcg_temp_free(t1);
855 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
856 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
857 } else {
858 TCGv zero = tcg_const_tl(0);
859 if (add_ca) {
860 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
861 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
862 } else {
863 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
864 }
865 tcg_temp_free(zero);
866 }
867 } else {
868 tcg_gen_add_tl(t0, arg1, arg2);
869 if (add_ca) {
870 tcg_gen_add_tl(t0, t0, cpu_ca);
871 }
872 }
873
874 if (compute_ov) {
875 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
876 }
877 if (unlikely(compute_rc0)) {
878 gen_set_Rc0(ctx, t0);
879 }
880
881 if (!TCGV_EQUAL(t0, ret)) {
882 tcg_gen_mov_tl(ret, t0);
883 tcg_temp_free(t0);
884 }
885 }
886 /* Add functions with two operands */
887 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
888 static void glue(gen_, name)(DisasContext *ctx) \
889 { \
890 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
891 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
892 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
893 }
894 /* Add functions with one operand and one immediate */
895 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
896 add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
898 { \
899 TCGv t0 = tcg_const_tl(const_val); \
900 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
901 cpu_gpr[rA(ctx->opcode)], t0, \
902 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
903 tcg_temp_free(t0); \
904 }
905
906 /* add add. addo addo. */
907 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
908 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
909 /* addc addc. addco addco. */
910 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
911 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
912 /* adde adde. addeo addeo. */
913 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
914 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
915 /* addme addme. addmeo addmeo. */
916 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
917 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
918 /* addze addze. addzeo addzeo.*/
919 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
920 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
921 /* addi */
922 static void gen_addi(DisasContext *ctx)
923 {
924 target_long simm = SIMM(ctx->opcode);
925
926 if (rA(ctx->opcode) == 0) {
927 /* li case */
928 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
929 } else {
930 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
931 cpu_gpr[rA(ctx->opcode)], simm);
932 }
933 }
934 /* addic addic.*/
935 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
936 {
937 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
938 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
939 c, 0, 1, 0, compute_rc0);
940 tcg_temp_free(c);
941 }
942
943 static void gen_addic(DisasContext *ctx)
944 {
945 gen_op_addic(ctx, 0);
946 }
947
948 static void gen_addic_(DisasContext *ctx)
949 {
950 gen_op_addic(ctx, 1);
951 }
952
953 /* addis */
954 static void gen_addis(DisasContext *ctx)
955 {
956 target_long simm = SIMM(ctx->opcode);
957
958 if (rA(ctx->opcode) == 0) {
959 /* lis case */
960 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
961 } else {
962 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
963 cpu_gpr[rA(ctx->opcode)], simm << 16);
964 }
965 }
966
967 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
968 TCGv arg2, int sign, int compute_ov)
969 {
970 int l1 = gen_new_label();
971 int l2 = gen_new_label();
972 TCGv_i32 t0 = tcg_temp_local_new_i32();
973 TCGv_i32 t1 = tcg_temp_local_new_i32();
974
975 tcg_gen_trunc_tl_i32(t0, arg1);
976 tcg_gen_trunc_tl_i32(t1, arg2);
977 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
978 if (sign) {
979 int l3 = gen_new_label();
980 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
981 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
982 gen_set_label(l3);
983 tcg_gen_div_i32(t0, t0, t1);
984 } else {
985 tcg_gen_divu_i32(t0, t0, t1);
986 }
987 if (compute_ov) {
988 tcg_gen_movi_tl(cpu_ov, 0);
989 }
990 tcg_gen_br(l2);
991 gen_set_label(l1);
992 if (sign) {
993 tcg_gen_sari_i32(t0, t0, 31);
994 } else {
995 tcg_gen_movi_i32(t0, 0);
996 }
997 if (compute_ov) {
998 tcg_gen_movi_tl(cpu_ov, 1);
999 tcg_gen_movi_tl(cpu_so, 1);
1000 }
1001 gen_set_label(l2);
1002 tcg_gen_extu_i32_tl(ret, t0);
1003 tcg_temp_free_i32(t0);
1004 tcg_temp_free_i32(t1);
1005 if (unlikely(Rc(ctx->opcode) != 0))
1006 gen_set_Rc0(ctx, ret);
1007 }
1008 /* Div functions */
1009 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 sign, compute_ov); \
1015 }
1016 /* divwu divwu. divwuo divwuo. */
1017 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1018 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1019 /* divw divw. divwo divwo. */
1020 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1021 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1022
1023 /* div[wd]eu[o][.] */
1024 #define GEN_DIVE(name, hlpr, compute_ov) \
1025 static void gen_##name(DisasContext *ctx) \
1026 { \
1027 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1028 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1029 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1030 tcg_temp_free_i32(t0); \
1031 if (unlikely(Rc(ctx->opcode) != 0)) { \
1032 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1033 } \
1034 }
1035
1036 GEN_DIVE(divweu, divweu, 0);
1037 GEN_DIVE(divweuo, divweu, 1);
1038 GEN_DIVE(divwe, divwe, 0);
1039 GEN_DIVE(divweo, divwe, 1);
1040
1041 #if defined(TARGET_PPC64)
1042 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1043 TCGv arg2, int sign, int compute_ov)
1044 {
1045 int l1 = gen_new_label();
1046 int l2 = gen_new_label();
1047
1048 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1049 if (sign) {
1050 int l3 = gen_new_label();
1051 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1052 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1053 gen_set_label(l3);
1054 tcg_gen_div_i64(ret, arg1, arg2);
1055 } else {
1056 tcg_gen_divu_i64(ret, arg1, arg2);
1057 }
1058 if (compute_ov) {
1059 tcg_gen_movi_tl(cpu_ov, 0);
1060 }
1061 tcg_gen_br(l2);
1062 gen_set_label(l1);
1063 if (sign) {
1064 tcg_gen_sari_i64(ret, arg1, 63);
1065 } else {
1066 tcg_gen_movi_i64(ret, 0);
1067 }
1068 if (compute_ov) {
1069 tcg_gen_movi_tl(cpu_ov, 1);
1070 tcg_gen_movi_tl(cpu_so, 1);
1071 }
1072 gen_set_label(l2);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, ret);
1075 }
1076 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1077 static void glue(gen_, name)(DisasContext *ctx) \
1078 { \
1079 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1080 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1081 sign, compute_ov); \
1082 }
1083 /* divwu divwu. divwuo divwuo. */
1084 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1085 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1086 /* divw divw. divwo divwo. */
1087 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1088 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1089
1090 GEN_DIVE(divdeu, divdeu, 0);
1091 GEN_DIVE(divdeuo, divdeu, 1);
1092 GEN_DIVE(divde, divde, 0);
1093 GEN_DIVE(divdeo, divde, 1);
1094 #endif
1095
1096 /* mulhw mulhw. */
1097 static void gen_mulhw(DisasContext *ctx)
1098 {
1099 TCGv_i32 t0 = tcg_temp_new_i32();
1100 TCGv_i32 t1 = tcg_temp_new_i32();
1101
1102 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1103 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1104 tcg_gen_muls2_i32(t0, t1, t0, t1);
1105 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1106 tcg_temp_free_i32(t0);
1107 tcg_temp_free_i32(t1);
1108 if (unlikely(Rc(ctx->opcode) != 0))
1109 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1110 }
1111
1112 /* mulhwu mulhwu. */
1113 static void gen_mulhwu(DisasContext *ctx)
1114 {
1115 TCGv_i32 t0 = tcg_temp_new_i32();
1116 TCGv_i32 t1 = tcg_temp_new_i32();
1117
1118 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1119 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1120 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1121 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1122 tcg_temp_free_i32(t0);
1123 tcg_temp_free_i32(t1);
1124 if (unlikely(Rc(ctx->opcode) != 0))
1125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1126 }
1127
1128 /* mullw mullw. */
1129 static void gen_mullw(DisasContext *ctx)
1130 {
1131 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1132 cpu_gpr[rB(ctx->opcode)]);
1133 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1134 if (unlikely(Rc(ctx->opcode) != 0))
1135 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1136 }
1137
1138 /* mullwo mullwo. */
1139 static void gen_mullwo(DisasContext *ctx)
1140 {
1141 TCGv_i32 t0 = tcg_temp_new_i32();
1142 TCGv_i32 t1 = tcg_temp_new_i32();
1143
1144 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1145 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1146 tcg_gen_muls2_i32(t0, t1, t0, t1);
1147 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1148
1149 tcg_gen_sari_i32(t0, t0, 31);
1150 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1151 tcg_gen_extu_i32_tl(cpu_ov, t0);
1152 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1153
1154 tcg_temp_free_i32(t0);
1155 tcg_temp_free_i32(t1);
1156 if (unlikely(Rc(ctx->opcode) != 0))
1157 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1158 }
1159
1160 /* mulli */
1161 static void gen_mulli(DisasContext *ctx)
1162 {
1163 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1164 SIMM(ctx->opcode));
1165 }
1166
1167 #if defined(TARGET_PPC64)
1168 /* mulhd mulhd. */
1169 static void gen_mulhd(DisasContext *ctx)
1170 {
1171 TCGv lo = tcg_temp_new();
1172 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1174 tcg_temp_free(lo);
1175 if (unlikely(Rc(ctx->opcode) != 0)) {
1176 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1177 }
1178 }
1179
1180 /* mulhdu mulhdu. */
1181 static void gen_mulhdu(DisasContext *ctx)
1182 {
1183 TCGv lo = tcg_temp_new();
1184 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1185 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1186 tcg_temp_free(lo);
1187 if (unlikely(Rc(ctx->opcode) != 0)) {
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189 }
1190 }
1191
1192 /* mulld mulld. */
1193 static void gen_mulld(DisasContext *ctx)
1194 {
1195 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1196 cpu_gpr[rB(ctx->opcode)]);
1197 if (unlikely(Rc(ctx->opcode) != 0))
1198 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1199 }
1200
1201 /* mulldo mulldo. */
1202 static void gen_mulldo(DisasContext *ctx)
1203 {
1204 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1206 if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1208 }
1209 }
1210 #endif
1211
1212 /* Common subf function */
1213 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1214 TCGv arg2, bool add_ca, bool compute_ca,
1215 bool compute_ov, bool compute_rc0)
1216 {
1217 TCGv t0 = ret;
1218
1219 if (compute_ca || compute_ov) {
1220 t0 = tcg_temp_new();
1221 }
1222
1223 if (compute_ca) {
1224 /* dest = ~arg1 + arg2 [+ ca]. */
1225 if (NARROW_MODE(ctx)) {
1226 /* Caution: a non-obvious corner case of the spec is that we
1227 must produce the *entire* 64-bit addition, but produce the
1228 carry into bit 32. */
1229 TCGv inv1 = tcg_temp_new();
1230 TCGv t1 = tcg_temp_new();
1231 tcg_gen_not_tl(inv1, arg1);
1232 if (add_ca) {
1233 tcg_gen_add_tl(t0, arg2, cpu_ca);
1234 } else {
1235 tcg_gen_addi_tl(t0, arg2, 1);
1236 }
1237 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1238 tcg_gen_add_tl(t0, t0, inv1);
1239 tcg_temp_free(inv1);
1240 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1241 tcg_temp_free(t1);
1242 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1243 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1244 } else if (add_ca) {
1245 TCGv zero, inv1 = tcg_temp_new();
1246 tcg_gen_not_tl(inv1, arg1);
1247 zero = tcg_const_tl(0);
1248 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1249 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1250 tcg_temp_free(zero);
1251 tcg_temp_free(inv1);
1252 } else {
1253 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1254 tcg_gen_sub_tl(t0, arg2, arg1);
1255 }
1256 } else if (add_ca) {
1257 /* Since we're ignoring carry-out, we can simplify the
1258 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1259 tcg_gen_sub_tl(t0, arg2, arg1);
1260 tcg_gen_add_tl(t0, t0, cpu_ca);
1261 tcg_gen_subi_tl(t0, t0, 1);
1262 } else {
1263 tcg_gen_sub_tl(t0, arg2, arg1);
1264 }
1265
1266 if (compute_ov) {
1267 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1268 }
1269 if (unlikely(compute_rc0)) {
1270 gen_set_Rc0(ctx, t0);
1271 }
1272
1273 if (!TCGV_EQUAL(t0, ret)) {
1274 tcg_gen_mov_tl(ret, t0);
1275 tcg_temp_free(t0);
1276 }
1277 }
1278 /* Sub functions with Two operands functions */
1279 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1280 static void glue(gen_, name)(DisasContext *ctx) \
1281 { \
1282 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1283 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1284 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1285 }
1286 /* Sub functions with one operand and one immediate */
1287 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1288 add_ca, compute_ca, compute_ov) \
1289 static void glue(gen_, name)(DisasContext *ctx) \
1290 { \
1291 TCGv t0 = tcg_const_tl(const_val); \
1292 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1293 cpu_gpr[rA(ctx->opcode)], t0, \
1294 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1295 tcg_temp_free(t0); \
1296 }
1297 /* subf subf. subfo subfo. */
1298 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1299 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1300 /* subfc subfc. subfco subfco. */
1301 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1302 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1303 /* subfe subfe. subfeo subfo. */
1304 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1305 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1306 /* subfme subfme. subfmeo subfmeo. */
1307 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1309 /* subfze subfze. subfzeo subfzeo.*/
1310 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1312
1313 /* subfic */
1314 static void gen_subfic(DisasContext *ctx)
1315 {
1316 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1317 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1318 c, 0, 1, 0, 0);
1319 tcg_temp_free(c);
1320 }
1321
1322 /* neg neg. nego nego. */
1323 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1324 {
1325 TCGv zero = tcg_const_tl(0);
1326 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1327 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1328 tcg_temp_free(zero);
1329 }
1330
1331 static void gen_neg(DisasContext *ctx)
1332 {
1333 gen_op_arith_neg(ctx, 0);
1334 }
1335
1336 static void gen_nego(DisasContext *ctx)
1337 {
1338 gen_op_arith_neg(ctx, 1);
1339 }
1340
1341 /*** Integer logical ***/
1342 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1343 static void glue(gen_, name)(DisasContext *ctx) \
1344 { \
1345 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1346 cpu_gpr[rB(ctx->opcode)]); \
1347 if (unlikely(Rc(ctx->opcode) != 0)) \
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1349 }
1350
1351 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1352 static void glue(gen_, name)(DisasContext *ctx) \
1353 { \
1354 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1355 if (unlikely(Rc(ctx->opcode) != 0)) \
1356 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1357 }
1358
1359 /* and & and. */
1360 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1361 /* andc & andc. */
1362 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1363
1364 /* andi. */
1365 static void gen_andi_(DisasContext *ctx)
1366 {
1367 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1368 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1369 }
1370
1371 /* andis. */
1372 static void gen_andis_(DisasContext *ctx)
1373 {
1374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1376 }
1377
1378 /* cntlzw */
1379 static void gen_cntlzw(DisasContext *ctx)
1380 {
1381 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1384 }
1385 /* eqv & eqv. */
1386 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1387 /* extsb & extsb. */
1388 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1389 /* extsh & extsh. */
1390 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1391 /* nand & nand. */
1392 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1393 /* nor & nor. */
1394 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1395
1396 /* or & or. */
1397 static void gen_or(DisasContext *ctx)
1398 {
1399 int rs, ra, rb;
1400
1401 rs = rS(ctx->opcode);
1402 ra = rA(ctx->opcode);
1403 rb = rB(ctx->opcode);
1404 /* Optimisation for mr. ri case */
1405 if (rs != ra || rs != rb) {
1406 if (rs != rb)
1407 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1408 else
1409 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1410 if (unlikely(Rc(ctx->opcode) != 0))
1411 gen_set_Rc0(ctx, cpu_gpr[ra]);
1412 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1413 gen_set_Rc0(ctx, cpu_gpr[rs]);
1414 #if defined(TARGET_PPC64)
1415 } else {
1416 int prio = 0;
1417
1418 switch (rs) {
1419 case 1:
1420 /* Set process priority to low */
1421 prio = 2;
1422 break;
1423 case 6:
1424 /* Set process priority to medium-low */
1425 prio = 3;
1426 break;
1427 case 2:
1428 /* Set process priority to normal */
1429 prio = 4;
1430 break;
1431 #if !defined(CONFIG_USER_ONLY)
1432 case 31:
1433 if (ctx->mem_idx > 0) {
1434 /* Set process priority to very low */
1435 prio = 1;
1436 }
1437 break;
1438 case 5:
1439 if (ctx->mem_idx > 0) {
1440 /* Set process priority to medium-hight */
1441 prio = 5;
1442 }
1443 break;
1444 case 3:
1445 if (ctx->mem_idx > 0) {
1446 /* Set process priority to high */
1447 prio = 6;
1448 }
1449 break;
1450 case 7:
1451 if (ctx->mem_idx > 1) {
1452 /* Set process priority to very high */
1453 prio = 7;
1454 }
1455 break;
1456 #endif
1457 default:
1458 /* nop */
1459 break;
1460 }
1461 if (prio) {
1462 TCGv t0 = tcg_temp_new();
1463 gen_load_spr(t0, SPR_PPR);
1464 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1465 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1466 gen_store_spr(SPR_PPR, t0);
1467 tcg_temp_free(t0);
1468 }
1469 #endif
1470 }
1471 }
1472 /* orc & orc. */
1473 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1474
1475 /* xor & xor. */
1476 static void gen_xor(DisasContext *ctx)
1477 {
1478 /* Optimisation for "set to zero" case */
1479 if (rS(ctx->opcode) != rB(ctx->opcode))
1480 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1481 else
1482 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485 }
1486
1487 /* ori */
1488 static void gen_ori(DisasContext *ctx)
1489 {
1490 target_ulong uimm = UIMM(ctx->opcode);
1491
1492 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1493 /* NOP */
1494 /* XXX: should handle special NOPs for POWER series */
1495 return;
1496 }
1497 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1498 }
1499
1500 /* oris */
1501 static void gen_oris(DisasContext *ctx)
1502 {
1503 target_ulong uimm = UIMM(ctx->opcode);
1504
1505 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1506 /* NOP */
1507 return;
1508 }
1509 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1510 }
1511
1512 /* xori */
1513 static void gen_xori(DisasContext *ctx)
1514 {
1515 target_ulong uimm = UIMM(ctx->opcode);
1516
1517 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1518 /* NOP */
1519 return;
1520 }
1521 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1522 }
1523
1524 /* xoris */
1525 static void gen_xoris(DisasContext *ctx)
1526 {
1527 target_ulong uimm = UIMM(ctx->opcode);
1528
1529 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1530 /* NOP */
1531 return;
1532 }
1533 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1534 }
1535
1536 /* popcntb : PowerPC 2.03 specification */
1537 static void gen_popcntb(DisasContext *ctx)
1538 {
1539 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1540 }
1541
1542 static void gen_popcntw(DisasContext *ctx)
1543 {
1544 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545 }
1546
1547 #if defined(TARGET_PPC64)
1548 /* popcntd: PowerPC 2.06 specification */
1549 static void gen_popcntd(DisasContext *ctx)
1550 {
1551 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1552 }
1553 #endif
1554
1555 /* prtyw: PowerPC 2.05 specification */
1556 static void gen_prtyw(DisasContext *ctx)
1557 {
1558 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1559 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1560 TCGv t0 = tcg_temp_new();
1561 tcg_gen_shri_tl(t0, rs, 16);
1562 tcg_gen_xor_tl(ra, rs, t0);
1563 tcg_gen_shri_tl(t0, ra, 8);
1564 tcg_gen_xor_tl(ra, ra, t0);
1565 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1566 tcg_temp_free(t0);
1567 }
1568
1569 #if defined(TARGET_PPC64)
1570 /* prtyd: PowerPC 2.05 specification */
1571 static void gen_prtyd(DisasContext *ctx)
1572 {
1573 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1574 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1575 TCGv t0 = tcg_temp_new();
1576 tcg_gen_shri_tl(t0, rs, 32);
1577 tcg_gen_xor_tl(ra, rs, t0);
1578 tcg_gen_shri_tl(t0, ra, 16);
1579 tcg_gen_xor_tl(ra, ra, t0);
1580 tcg_gen_shri_tl(t0, ra, 8);
1581 tcg_gen_xor_tl(ra, ra, t0);
1582 tcg_gen_andi_tl(ra, ra, 1);
1583 tcg_temp_free(t0);
1584 }
1585 #endif
1586
1587 #if defined(TARGET_PPC64)
1588 /* bpermd */
1589 static void gen_bpermd(DisasContext *ctx)
1590 {
1591 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1592 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1593 }
1594 #endif
1595
1596 #if defined(TARGET_PPC64)
1597 /* extsw & extsw. */
1598 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1599
1600 /* cntlzd */
1601 static void gen_cntlzd(DisasContext *ctx)
1602 {
1603 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1604 if (unlikely(Rc(ctx->opcode) != 0))
1605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1606 }
1607 #endif
1608
1609 /*** Integer rotate ***/
1610
1611 /* rlwimi & rlwimi. */
1612 static void gen_rlwimi(DisasContext *ctx)
1613 {
1614 uint32_t mb, me, sh;
1615
1616 mb = MB(ctx->opcode);
1617 me = ME(ctx->opcode);
1618 sh = SH(ctx->opcode);
1619 if (likely(sh == 0 && mb == 0 && me == 31)) {
1620 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1621 } else {
1622 target_ulong mask;
1623 TCGv t1;
1624 TCGv t0 = tcg_temp_new();
1625 #if defined(TARGET_PPC64)
1626 TCGv_i32 t2 = tcg_temp_new_i32();
1627 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1628 tcg_gen_rotli_i32(t2, t2, sh);
1629 tcg_gen_extu_i32_i64(t0, t2);
1630 tcg_temp_free_i32(t2);
1631 #else
1632 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1633 #endif
1634 #if defined(TARGET_PPC64)
1635 mb += 32;
1636 me += 32;
1637 #endif
1638 mask = MASK(mb, me);
1639 t1 = tcg_temp_new();
1640 tcg_gen_andi_tl(t0, t0, mask);
1641 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1642 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1643 tcg_temp_free(t0);
1644 tcg_temp_free(t1);
1645 }
1646 if (unlikely(Rc(ctx->opcode) != 0))
1647 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1648 }
1649
1650 /* rlwinm & rlwinm. */
1651 static void gen_rlwinm(DisasContext *ctx)
1652 {
1653 uint32_t mb, me, sh;
1654
1655 sh = SH(ctx->opcode);
1656 mb = MB(ctx->opcode);
1657 me = ME(ctx->opcode);
1658
1659 if (likely(mb == 0 && me == (31 - sh))) {
1660 if (likely(sh == 0)) {
1661 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1662 } else {
1663 TCGv t0 = tcg_temp_new();
1664 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1665 tcg_gen_shli_tl(t0, t0, sh);
1666 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1667 tcg_temp_free(t0);
1668 }
1669 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1670 TCGv t0 = tcg_temp_new();
1671 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1672 tcg_gen_shri_tl(t0, t0, mb);
1673 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1674 tcg_temp_free(t0);
1675 } else {
1676 TCGv t0 = tcg_temp_new();
1677 #if defined(TARGET_PPC64)
1678 TCGv_i32 t1 = tcg_temp_new_i32();
1679 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1680 tcg_gen_rotli_i32(t1, t1, sh);
1681 tcg_gen_extu_i32_i64(t0, t1);
1682 tcg_temp_free_i32(t1);
1683 #else
1684 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1685 #endif
1686 #if defined(TARGET_PPC64)
1687 mb += 32;
1688 me += 32;
1689 #endif
1690 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1691 tcg_temp_free(t0);
1692 }
1693 if (unlikely(Rc(ctx->opcode) != 0))
1694 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1695 }
1696
1697 /* rlwnm & rlwnm. */
1698 static void gen_rlwnm(DisasContext *ctx)
1699 {
1700 uint32_t mb, me;
1701 TCGv t0;
1702 #if defined(TARGET_PPC64)
1703 TCGv_i32 t1, t2;
1704 #endif
1705
1706 mb = MB(ctx->opcode);
1707 me = ME(ctx->opcode);
1708 t0 = tcg_temp_new();
1709 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1710 #if defined(TARGET_PPC64)
1711 t1 = tcg_temp_new_i32();
1712 t2 = tcg_temp_new_i32();
1713 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1714 tcg_gen_trunc_i64_i32(t2, t0);
1715 tcg_gen_rotl_i32(t1, t1, t2);
1716 tcg_gen_extu_i32_i64(t0, t1);
1717 tcg_temp_free_i32(t1);
1718 tcg_temp_free_i32(t2);
1719 #else
1720 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1721 #endif
1722 if (unlikely(mb != 0 || me != 31)) {
1723 #if defined(TARGET_PPC64)
1724 mb += 32;
1725 me += 32;
1726 #endif
1727 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1728 } else {
1729 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1730 }
1731 tcg_temp_free(t0);
1732 if (unlikely(Rc(ctx->opcode) != 0))
1733 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1734 }
1735
1736 #if defined(TARGET_PPC64)
1737 #define GEN_PPC64_R2(name, opc1, opc2) \
1738 static void glue(gen_, name##0)(DisasContext *ctx) \
1739 { \
1740 gen_##name(ctx, 0); \
1741 } \
1742 \
1743 static void glue(gen_, name##1)(DisasContext *ctx) \
1744 { \
1745 gen_##name(ctx, 1); \
1746 }
1747 #define GEN_PPC64_R4(name, opc1, opc2) \
1748 static void glue(gen_, name##0)(DisasContext *ctx) \
1749 { \
1750 gen_##name(ctx, 0, 0); \
1751 } \
1752 \
1753 static void glue(gen_, name##1)(DisasContext *ctx) \
1754 { \
1755 gen_##name(ctx, 0, 1); \
1756 } \
1757 \
1758 static void glue(gen_, name##2)(DisasContext *ctx) \
1759 { \
1760 gen_##name(ctx, 1, 0); \
1761 } \
1762 \
1763 static void glue(gen_, name##3)(DisasContext *ctx) \
1764 { \
1765 gen_##name(ctx, 1, 1); \
1766 }
1767
1768 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1769 uint32_t sh)
1770 {
1771 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1772 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1773 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1774 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1775 } else {
1776 TCGv t0 = tcg_temp_new();
1777 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1778 if (likely(mb == 0 && me == 63)) {
1779 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1780 } else {
1781 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1782 }
1783 tcg_temp_free(t0);
1784 }
1785 if (unlikely(Rc(ctx->opcode) != 0))
1786 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1787 }
1788 /* rldicl - rldicl. */
1789 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1790 {
1791 uint32_t sh, mb;
1792
1793 sh = SH(ctx->opcode) | (shn << 5);
1794 mb = MB(ctx->opcode) | (mbn << 5);
1795 gen_rldinm(ctx, mb, 63, sh);
1796 }
1797 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1798 /* rldicr - rldicr. */
1799 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1800 {
1801 uint32_t sh, me;
1802
1803 sh = SH(ctx->opcode) | (shn << 5);
1804 me = MB(ctx->opcode) | (men << 5);
1805 gen_rldinm(ctx, 0, me, sh);
1806 }
1807 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1808 /* rldic - rldic. */
1809 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1810 {
1811 uint32_t sh, mb;
1812
1813 sh = SH(ctx->opcode) | (shn << 5);
1814 mb = MB(ctx->opcode) | (mbn << 5);
1815 gen_rldinm(ctx, mb, 63 - sh, sh);
1816 }
1817 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1818
1819 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1820 {
1821 TCGv t0;
1822
1823 t0 = tcg_temp_new();
1824 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1825 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1826 if (unlikely(mb != 0 || me != 63)) {
1827 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1828 } else {
1829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1830 }
1831 tcg_temp_free(t0);
1832 if (unlikely(Rc(ctx->opcode) != 0))
1833 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1834 }
1835
1836 /* rldcl - rldcl. */
1837 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1838 {
1839 uint32_t mb;
1840
1841 mb = MB(ctx->opcode) | (mbn << 5);
1842 gen_rldnm(ctx, mb, 63);
1843 }
1844 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1845 /* rldcr - rldcr. */
1846 static inline void gen_rldcr(DisasContext *ctx, int men)
1847 {
1848 uint32_t me;
1849
1850 me = MB(ctx->opcode) | (men << 5);
1851 gen_rldnm(ctx, 0, me);
1852 }
1853 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1854 /* rldimi - rldimi. */
1855 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1856 {
1857 uint32_t sh, mb, me;
1858
1859 sh = SH(ctx->opcode) | (shn << 5);
1860 mb = MB(ctx->opcode) | (mbn << 5);
1861 me = 63 - sh;
1862 if (unlikely(sh == 0 && mb == 0)) {
1863 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1864 } else {
1865 TCGv t0, t1;
1866 target_ulong mask;
1867
1868 t0 = tcg_temp_new();
1869 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1870 t1 = tcg_temp_new();
1871 mask = MASK(mb, me);
1872 tcg_gen_andi_tl(t0, t0, mask);
1873 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1874 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1875 tcg_temp_free(t0);
1876 tcg_temp_free(t1);
1877 }
1878 if (unlikely(Rc(ctx->opcode) != 0))
1879 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1880 }
1881 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1882 #endif
1883
1884 /*** Integer shift ***/
1885
1886 /* slw & slw. */
1887 static void gen_slw(DisasContext *ctx)
1888 {
1889 TCGv t0, t1;
1890
1891 t0 = tcg_temp_new();
1892 /* AND rS with a mask that is 0 when rB >= 0x20 */
1893 #if defined(TARGET_PPC64)
1894 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1895 tcg_gen_sari_tl(t0, t0, 0x3f);
1896 #else
1897 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1898 tcg_gen_sari_tl(t0, t0, 0x1f);
1899 #endif
1900 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1901 t1 = tcg_temp_new();
1902 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1903 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1904 tcg_temp_free(t1);
1905 tcg_temp_free(t0);
1906 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1907 if (unlikely(Rc(ctx->opcode) != 0))
1908 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1909 }
1910
1911 /* sraw & sraw. */
1912 static void gen_sraw(DisasContext *ctx)
1913 {
1914 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1915 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1916 if (unlikely(Rc(ctx->opcode) != 0))
1917 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1918 }
1919
1920 /* srawi & srawi. */
1921 static void gen_srawi(DisasContext *ctx)
1922 {
1923 int sh = SH(ctx->opcode);
1924 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1925 TCGv src = cpu_gpr[rS(ctx->opcode)];
1926 if (sh == 0) {
1927 tcg_gen_mov_tl(dst, src);
1928 tcg_gen_movi_tl(cpu_ca, 0);
1929 } else {
1930 TCGv t0;
1931 tcg_gen_ext32s_tl(dst, src);
1932 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1933 t0 = tcg_temp_new();
1934 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1935 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1936 tcg_temp_free(t0);
1937 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1938 tcg_gen_sari_tl(dst, dst, sh);
1939 }
1940 if (unlikely(Rc(ctx->opcode) != 0)) {
1941 gen_set_Rc0(ctx, dst);
1942 }
1943 }
1944
1945 /* srw & srw. */
1946 static void gen_srw(DisasContext *ctx)
1947 {
1948 TCGv t0, t1;
1949
1950 t0 = tcg_temp_new();
1951 /* AND rS with a mask that is 0 when rB >= 0x20 */
1952 #if defined(TARGET_PPC64)
1953 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1954 tcg_gen_sari_tl(t0, t0, 0x3f);
1955 #else
1956 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1957 tcg_gen_sari_tl(t0, t0, 0x1f);
1958 #endif
1959 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1960 tcg_gen_ext32u_tl(t0, t0);
1961 t1 = tcg_temp_new();
1962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1963 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1964 tcg_temp_free(t1);
1965 tcg_temp_free(t0);
1966 if (unlikely(Rc(ctx->opcode) != 0))
1967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1968 }
1969
1970 #if defined(TARGET_PPC64)
1971 /* sld & sld. */
1972 static void gen_sld(DisasContext *ctx)
1973 {
1974 TCGv t0, t1;
1975
1976 t0 = tcg_temp_new();
1977 /* AND rS with a mask that is 0 when rB >= 0x40 */
1978 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1979 tcg_gen_sari_tl(t0, t0, 0x3f);
1980 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1981 t1 = tcg_temp_new();
1982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1983 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1984 tcg_temp_free(t1);
1985 tcg_temp_free(t0);
1986 if (unlikely(Rc(ctx->opcode) != 0))
1987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1988 }
1989
1990 /* srad & srad. */
1991 static void gen_srad(DisasContext *ctx)
1992 {
1993 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1994 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1995 if (unlikely(Rc(ctx->opcode) != 0))
1996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1997 }
1998 /* sradi & sradi. */
1999 static inline void gen_sradi(DisasContext *ctx, int n)
2000 {
2001 int sh = SH(ctx->opcode) + (n << 5);
2002 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2003 TCGv src = cpu_gpr[rS(ctx->opcode)];
2004 if (sh == 0) {
2005 tcg_gen_mov_tl(dst, src);
2006 tcg_gen_movi_tl(cpu_ca, 0);
2007 } else {
2008 TCGv t0;
2009 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2010 t0 = tcg_temp_new();
2011 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2012 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2013 tcg_temp_free(t0);
2014 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2015 tcg_gen_sari_tl(dst, src, sh);
2016 }
2017 if (unlikely(Rc(ctx->opcode) != 0)) {
2018 gen_set_Rc0(ctx, dst);
2019 }
2020 }
2021
2022 static void gen_sradi0(DisasContext *ctx)
2023 {
2024 gen_sradi(ctx, 0);
2025 }
2026
2027 static void gen_sradi1(DisasContext *ctx)
2028 {
2029 gen_sradi(ctx, 1);
2030 }
2031
2032 /* srd & srd. */
2033 static void gen_srd(DisasContext *ctx)
2034 {
2035 TCGv t0, t1;
2036
2037 t0 = tcg_temp_new();
2038 /* AND rS with a mask that is 0 when rB >= 0x40 */
2039 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2040 tcg_gen_sari_tl(t0, t0, 0x3f);
2041 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2042 t1 = tcg_temp_new();
2043 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2044 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2045 tcg_temp_free(t1);
2046 tcg_temp_free(t0);
2047 if (unlikely(Rc(ctx->opcode) != 0))
2048 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2049 }
2050 #endif
2051
2052 /*** Floating-Point arithmetic ***/
2053 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2054 static void gen_f##name(DisasContext *ctx) \
2055 { \
2056 if (unlikely(!ctx->fpu_enabled)) { \
2057 gen_exception(ctx, POWERPC_EXCP_FPU); \
2058 return; \
2059 } \
2060 /* NIP cannot be restored if the memory exception comes from an helper */ \
2061 gen_update_nip(ctx, ctx->nip - 4); \
2062 gen_reset_fpstatus(); \
2063 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2064 cpu_fpr[rA(ctx->opcode)], \
2065 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2066 if (isfloat) { \
2067 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rD(ctx->opcode)]); \
2069 } \
2070 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2071 Rc(ctx->opcode) != 0); \
2072 }
2073
2074 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2075 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2076 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2077
2078 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2079 static void gen_f##name(DisasContext *ctx) \
2080 { \
2081 if (unlikely(!ctx->fpu_enabled)) { \
2082 gen_exception(ctx, POWERPC_EXCP_FPU); \
2083 return; \
2084 } \
2085 /* NIP cannot be restored if the memory exception comes from an helper */ \
2086 gen_update_nip(ctx, ctx->nip - 4); \
2087 gen_reset_fpstatus(); \
2088 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2089 cpu_fpr[rA(ctx->opcode)], \
2090 cpu_fpr[rB(ctx->opcode)]); \
2091 if (isfloat) { \
2092 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2093 cpu_fpr[rD(ctx->opcode)]); \
2094 } \
2095 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2096 set_fprf, Rc(ctx->opcode) != 0); \
2097 }
2098 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2099 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2100 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2101
2102 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2103 static void gen_f##name(DisasContext *ctx) \
2104 { \
2105 if (unlikely(!ctx->fpu_enabled)) { \
2106 gen_exception(ctx, POWERPC_EXCP_FPU); \
2107 return; \
2108 } \
2109 /* NIP cannot be restored if the memory exception comes from an helper */ \
2110 gen_update_nip(ctx, ctx->nip - 4); \
2111 gen_reset_fpstatus(); \
2112 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2113 cpu_fpr[rA(ctx->opcode)], \
2114 cpu_fpr[rC(ctx->opcode)]); \
2115 if (isfloat) { \
2116 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rD(ctx->opcode)]); \
2118 } \
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2120 set_fprf, Rc(ctx->opcode) != 0); \
2121 }
2122 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2123 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2124 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2125
2126 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2127 static void gen_f##name(DisasContext *ctx) \
2128 { \
2129 if (unlikely(!ctx->fpu_enabled)) { \
2130 gen_exception(ctx, POWERPC_EXCP_FPU); \
2131 return; \
2132 } \
2133 /* NIP cannot be restored if the memory exception comes from an helper */ \
2134 gen_update_nip(ctx, ctx->nip - 4); \
2135 gen_reset_fpstatus(); \
2136 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2137 cpu_fpr[rB(ctx->opcode)]); \
2138 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2139 set_fprf, Rc(ctx->opcode) != 0); \
2140 }
2141
2142 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2143 static void gen_f##name(DisasContext *ctx) \
2144 { \
2145 if (unlikely(!ctx->fpu_enabled)) { \
2146 gen_exception(ctx, POWERPC_EXCP_FPU); \
2147 return; \
2148 } \
2149 /* NIP cannot be restored if the memory exception comes from an helper */ \
2150 gen_update_nip(ctx, ctx->nip - 4); \
2151 gen_reset_fpstatus(); \
2152 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2153 cpu_fpr[rB(ctx->opcode)]); \
2154 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2155 set_fprf, Rc(ctx->opcode) != 0); \
2156 }
2157
2158 /* fadd - fadds */
2159 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2160 /* fdiv - fdivs */
2161 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2162 /* fmul - fmuls */
2163 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2164
2165 /* fre */
2166 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2167
2168 /* fres */
2169 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2170
2171 /* frsqrte */
2172 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2173
2174 /* frsqrtes */
2175 static void gen_frsqrtes(DisasContext *ctx)
2176 {
2177 if (unlikely(!ctx->fpu_enabled)) {
2178 gen_exception(ctx, POWERPC_EXCP_FPU);
2179 return;
2180 }
2181 /* NIP cannot be restored if the memory exception comes from an helper */
2182 gen_update_nip(ctx, ctx->nip - 4);
2183 gen_reset_fpstatus();
2184 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2185 cpu_fpr[rB(ctx->opcode)]);
2186 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2187 cpu_fpr[rD(ctx->opcode)]);
2188 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2189 }
2190
2191 /* fsel */
2192 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2193 /* fsub - fsubs */
2194 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2195 /* Optional: */
2196
2197 /* fsqrt */
2198 static void gen_fsqrt(DisasContext *ctx)
2199 {
2200 if (unlikely(!ctx->fpu_enabled)) {
2201 gen_exception(ctx, POWERPC_EXCP_FPU);
2202 return;
2203 }
2204 /* NIP cannot be restored if the memory exception comes from an helper */
2205 gen_update_nip(ctx, ctx->nip - 4);
2206 gen_reset_fpstatus();
2207 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2208 cpu_fpr[rB(ctx->opcode)]);
2209 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2210 }
2211
2212 static void gen_fsqrts(DisasContext *ctx)
2213 {
2214 if (unlikely(!ctx->fpu_enabled)) {
2215 gen_exception(ctx, POWERPC_EXCP_FPU);
2216 return;
2217 }
2218 /* NIP cannot be restored if the memory exception comes from an helper */
2219 gen_update_nip(ctx, ctx->nip - 4);
2220 gen_reset_fpstatus();
2221 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2222 cpu_fpr[rB(ctx->opcode)]);
2223 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2224 cpu_fpr[rD(ctx->opcode)]);
2225 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2226 }
2227
2228 /*** Floating-Point multiply-and-add ***/
2229 /* fmadd - fmadds */
2230 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2231 /* fmsub - fmsubs */
2232 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2233 /* fnmadd - fnmadds */
2234 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2235 /* fnmsub - fnmsubs */
2236 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2237
2238 /*** Floating-Point round & convert ***/
2239 /* fctiw */
2240 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2241 /* fctiwu */
2242 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2243 /* fctiwz */
2244 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2245 /* fctiwuz */
2246 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2247 /* frsp */
2248 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2249 #if defined(TARGET_PPC64)
2250 /* fcfid */
2251 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2252 /* fcfids */
2253 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2254 /* fcfidu */
2255 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2256 /* fcfidus */
2257 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2258 /* fctid */
2259 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2260 /* fctidu */
2261 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2262 /* fctidz */
2263 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2264 /* fctidu */
2265 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2266 #endif
2267
2268 /* frin */
2269 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2270 /* friz */
2271 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2272 /* frip */
2273 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2274 /* frim */
2275 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2276
2277 static void gen_ftdiv(DisasContext *ctx)
2278 {
2279 if (unlikely(!ctx->fpu_enabled)) {
2280 gen_exception(ctx, POWERPC_EXCP_FPU);
2281 return;
2282 }
2283 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2284 cpu_fpr[rB(ctx->opcode)]);
2285 }
2286
2287 static void gen_ftsqrt(DisasContext *ctx)
2288 {
2289 if (unlikely(!ctx->fpu_enabled)) {
2290 gen_exception(ctx, POWERPC_EXCP_FPU);
2291 return;
2292 }
2293 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2294 }
2295
2296
2297
2298 /*** Floating-Point compare ***/
2299
2300 /* fcmpo */
2301 static void gen_fcmpo(DisasContext *ctx)
2302 {
2303 TCGv_i32 crf;
2304 if (unlikely(!ctx->fpu_enabled)) {
2305 gen_exception(ctx, POWERPC_EXCP_FPU);
2306 return;
2307 }
2308 /* NIP cannot be restored if the memory exception comes from an helper */
2309 gen_update_nip(ctx, ctx->nip - 4);
2310 gen_reset_fpstatus();
2311 crf = tcg_const_i32(crfD(ctx->opcode));
2312 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2313 cpu_fpr[rB(ctx->opcode)], crf);
2314 tcg_temp_free_i32(crf);
2315 gen_helper_float_check_status(cpu_env);
2316 }
2317
2318 /* fcmpu */
2319 static void gen_fcmpu(DisasContext *ctx)
2320 {
2321 TCGv_i32 crf;
2322 if (unlikely(!ctx->fpu_enabled)) {
2323 gen_exception(ctx, POWERPC_EXCP_FPU);
2324 return;
2325 }
2326 /* NIP cannot be restored if the memory exception comes from an helper */
2327 gen_update_nip(ctx, ctx->nip - 4);
2328 gen_reset_fpstatus();
2329 crf = tcg_const_i32(crfD(ctx->opcode));
2330 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2331 cpu_fpr[rB(ctx->opcode)], crf);
2332 tcg_temp_free_i32(crf);
2333 gen_helper_float_check_status(cpu_env);
2334 }
2335
2336 /*** Floating-point move ***/
2337 /* fabs */
2338 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2339 static void gen_fabs(DisasContext *ctx)
2340 {
2341 if (unlikely(!ctx->fpu_enabled)) {
2342 gen_exception(ctx, POWERPC_EXCP_FPU);
2343 return;
2344 }
2345 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2346 ~(1ULL << 63));
2347 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2348 }
2349
2350 /* fmr - fmr. */
2351 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2352 static void gen_fmr(DisasContext *ctx)
2353 {
2354 if (unlikely(!ctx->fpu_enabled)) {
2355 gen_exception(ctx, POWERPC_EXCP_FPU);
2356 return;
2357 }
2358 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2359 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2360 }
2361
2362 /* fnabs */
2363 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2364 static void gen_fnabs(DisasContext *ctx)
2365 {
2366 if (unlikely(!ctx->fpu_enabled)) {
2367 gen_exception(ctx, POWERPC_EXCP_FPU);
2368 return;
2369 }
2370 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2371 1ULL << 63);
2372 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2373 }
2374
2375 /* fneg */
2376 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2377 static void gen_fneg(DisasContext *ctx)
2378 {
2379 if (unlikely(!ctx->fpu_enabled)) {
2380 gen_exception(ctx, POWERPC_EXCP_FPU);
2381 return;
2382 }
2383 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2384 1ULL << 63);
2385 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2386 }
2387
2388 /* fcpsgn: PowerPC 2.05 specification */
2389 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2390 static void gen_fcpsgn(DisasContext *ctx)
2391 {
2392 if (unlikely(!ctx->fpu_enabled)) {
2393 gen_exception(ctx, POWERPC_EXCP_FPU);
2394 return;
2395 }
2396 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2397 cpu_fpr[rB(ctx->opcode)], 0, 63);
2398 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2399 }
2400
2401 static void gen_fmrgew(DisasContext *ctx)
2402 {
2403 TCGv_i64 b0;
2404 if (unlikely(!ctx->fpu_enabled)) {
2405 gen_exception(ctx, POWERPC_EXCP_FPU);
2406 return;
2407 }
2408 b0 = tcg_temp_new_i64();
2409 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2410 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2411 b0, 0, 32);
2412 tcg_temp_free_i64(b0);
2413 }
2414
2415 static void gen_fmrgow(DisasContext *ctx)
2416 {
2417 if (unlikely(!ctx->fpu_enabled)) {
2418 gen_exception(ctx, POWERPC_EXCP_FPU);
2419 return;
2420 }
2421 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2422 cpu_fpr[rB(ctx->opcode)],
2423 cpu_fpr[rA(ctx->opcode)],
2424 32, 32);
2425 }
2426
2427 /*** Floating-Point status & ctrl register ***/
2428
2429 /* mcrfs */
2430 static void gen_mcrfs(DisasContext *ctx)
2431 {
2432 TCGv tmp = tcg_temp_new();
2433 int bfa;
2434
2435 if (unlikely(!ctx->fpu_enabled)) {
2436 gen_exception(ctx, POWERPC_EXCP_FPU);
2437 return;
2438 }
2439 bfa = 4 * (7 - crfS(ctx->opcode));
2440 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2441 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2442 tcg_temp_free(tmp);
2443 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2444 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2445 }
2446
2447 /* mffs */
2448 static void gen_mffs(DisasContext *ctx)
2449 {
2450 if (unlikely(!ctx->fpu_enabled)) {
2451 gen_exception(ctx, POWERPC_EXCP_FPU);
2452 return;
2453 }
2454 gen_reset_fpstatus();
2455 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2456 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2457 }
2458
2459 /* mtfsb0 */
2460 static void gen_mtfsb0(DisasContext *ctx)
2461 {
2462 uint8_t crb;
2463
2464 if (unlikely(!ctx->fpu_enabled)) {
2465 gen_exception(ctx, POWERPC_EXCP_FPU);
2466 return;
2467 }
2468 crb = 31 - crbD(ctx->opcode);
2469 gen_reset_fpstatus();
2470 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2471 TCGv_i32 t0;
2472 /* NIP cannot be restored if the memory exception comes from an helper */
2473 gen_update_nip(ctx, ctx->nip - 4);
2474 t0 = tcg_const_i32(crb);
2475 gen_helper_fpscr_clrbit(cpu_env, t0);
2476 tcg_temp_free_i32(t0);
2477 }
2478 if (unlikely(Rc(ctx->opcode) != 0)) {
2479 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2480 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2481 }
2482 }
2483
2484 /* mtfsb1 */
2485 static void gen_mtfsb1(DisasContext *ctx)
2486 {
2487 uint8_t crb;
2488
2489 if (unlikely(!ctx->fpu_enabled)) {
2490 gen_exception(ctx, POWERPC_EXCP_FPU);
2491 return;
2492 }
2493 crb = 31 - crbD(ctx->opcode);
2494 gen_reset_fpstatus();
2495 /* XXX: we pretend we can only do IEEE floating-point computations */
2496 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2497 TCGv_i32 t0;
2498 /* NIP cannot be restored if the memory exception comes from an helper */
2499 gen_update_nip(ctx, ctx->nip - 4);
2500 t0 = tcg_const_i32(crb);
2501 gen_helper_fpscr_setbit(cpu_env, t0);
2502 tcg_temp_free_i32(t0);
2503 }
2504 if (unlikely(Rc(ctx->opcode) != 0)) {
2505 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2506 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2507 }
2508 /* We can raise a differed exception */
2509 gen_helper_float_check_status(cpu_env);
2510 }
2511
2512 /* mtfsf */
2513 static void gen_mtfsf(DisasContext *ctx)
2514 {
2515 TCGv_i32 t0;
2516 int flm, l, w;
2517
2518 if (unlikely(!ctx->fpu_enabled)) {
2519 gen_exception(ctx, POWERPC_EXCP_FPU);
2520 return;
2521 }
2522 flm = FPFLM(ctx->opcode);
2523 l = FPL(ctx->opcode);
2524 w = FPW(ctx->opcode);
2525 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2526 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2527 return;
2528 }
2529 /* NIP cannot be restored if the memory exception comes from an helper */
2530 gen_update_nip(ctx, ctx->nip - 4);
2531 gen_reset_fpstatus();
2532 if (l) {
2533 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2534 } else {
2535 t0 = tcg_const_i32(flm << (w * 8));
2536 }
2537 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2538 tcg_temp_free_i32(t0);
2539 if (unlikely(Rc(ctx->opcode) != 0)) {
2540 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2541 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2542 }
2543 /* We can raise a differed exception */
2544 gen_helper_float_check_status(cpu_env);
2545 }
2546
2547 /* mtfsfi */
2548 static void gen_mtfsfi(DisasContext *ctx)
2549 {
2550 int bf, sh, w;
2551 TCGv_i64 t0;
2552 TCGv_i32 t1;
2553
2554 if (unlikely(!ctx->fpu_enabled)) {
2555 gen_exception(ctx, POWERPC_EXCP_FPU);
2556 return;
2557 }
2558 w = FPW(ctx->opcode);
2559 bf = FPBF(ctx->opcode);
2560 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2561 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2562 return;
2563 }
2564 sh = (8 * w) + 7 - bf;
2565 /* NIP cannot be restored if the memory exception comes from an helper */
2566 gen_update_nip(ctx, ctx->nip - 4);
2567 gen_reset_fpstatus();
2568 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2569 t1 = tcg_const_i32(1 << sh);
2570 gen_helper_store_fpscr(cpu_env, t0, t1);
2571 tcg_temp_free_i64(t0);
2572 tcg_temp_free_i32(t1);
2573 if (unlikely(Rc(ctx->opcode) != 0)) {
2574 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2575 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2576 }
2577 /* We can raise a differed exception */
2578 gen_helper_float_check_status(cpu_env);
2579 }
2580
2581 /*** Addressing modes ***/
2582 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2583 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2584 target_long maskl)
2585 {
2586 target_long simm = SIMM(ctx->opcode);
2587
2588 simm &= ~maskl;
2589 if (rA(ctx->opcode) == 0) {
2590 if (NARROW_MODE(ctx)) {
2591 simm = (uint32_t)simm;
2592 }
2593 tcg_gen_movi_tl(EA, simm);
2594 } else if (likely(simm != 0)) {
2595 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2596 if (NARROW_MODE(ctx)) {
2597 tcg_gen_ext32u_tl(EA, EA);
2598 }
2599 } else {
2600 if (NARROW_MODE(ctx)) {
2601 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2602 } else {
2603 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2604 }
2605 }
2606 }
2607
2608 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2609 {
2610 if (rA(ctx->opcode) == 0) {
2611 if (NARROW_MODE(ctx)) {
2612 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2613 } else {
2614 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2615 }
2616 } else {
2617 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2618 if (NARROW_MODE(ctx)) {
2619 tcg_gen_ext32u_tl(EA, EA);
2620 }
2621 }
2622 }
2623
2624 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2625 {
2626 if (rA(ctx->opcode) == 0) {
2627 tcg_gen_movi_tl(EA, 0);
2628 } else if (NARROW_MODE(ctx)) {
2629 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2630 } else {
2631 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2632 }
2633 }
2634
2635 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2636 target_long val)
2637 {
2638 tcg_gen_addi_tl(ret, arg1, val);
2639 if (NARROW_MODE(ctx)) {
2640 tcg_gen_ext32u_tl(ret, ret);
2641 }
2642 }
2643
2644 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2645 {
2646 int l1 = gen_new_label();
2647 TCGv t0 = tcg_temp_new();
2648 TCGv_i32 t1, t2;
2649 /* NIP cannot be restored if the memory exception comes from an helper */
2650 gen_update_nip(ctx, ctx->nip - 4);
2651 tcg_gen_andi_tl(t0, EA, mask);
2652 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2653 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2654 t2 = tcg_const_i32(0);
2655 gen_helper_raise_exception_err(cpu_env, t1, t2);
2656 tcg_temp_free_i32(t1);
2657 tcg_temp_free_i32(t2);
2658 gen_set_label(l1);
2659 tcg_temp_free(t0);
2660 }
2661
2662 /*** Integer load ***/
2663 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2664 {
2665 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2666 }
2667
2668 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2669 {
2670 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2671 }
2672
2673 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2674 {
2675 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2676 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2677 }
2678
2679 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2680 {
2681 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2682 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2683 }
2684
2685 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2686 {
2687 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2688 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2689 }
2690
2691 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2692 {
2693 TCGv tmp = tcg_temp_new();
2694 gen_qemu_ld32u(ctx, tmp, addr);
2695 tcg_gen_extu_tl_i64(val, tmp);
2696 tcg_temp_free(tmp);
2697 }
2698
2699 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2700 {
2701 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2702 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2703 }
2704
2705 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2706 {
2707 TCGv tmp = tcg_temp_new();
2708 gen_qemu_ld32s(ctx, tmp, addr);
2709 tcg_gen_ext_tl_i64(val, tmp);
2710 tcg_temp_free(tmp);
2711 }
2712
2713 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2714 {
2715 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2716 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2717 }
2718
2719 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2720 {
2721 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2722 }
2723
2724 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2725 {
2726 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2727 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2728 }
2729
2730 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2731 {
2732 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2733 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2734 }
2735
2736 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2737 {
2738 TCGv tmp = tcg_temp_new();
2739 tcg_gen_trunc_i64_tl(tmp, val);
2740 gen_qemu_st32(ctx, tmp, addr);
2741 tcg_temp_free(tmp);
2742 }
2743
2744 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2745 {
2746 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2747 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2748 }
2749
2750 #define GEN_LD(name, ldop, opc, type) \
2751 static void glue(gen_, name)(DisasContext *ctx) \
2752 { \
2753 TCGv EA; \
2754 gen_set_access_type(ctx, ACCESS_INT); \
2755 EA = tcg_temp_new(); \
2756 gen_addr_imm_index(ctx, EA, 0); \
2757 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2758 tcg_temp_free(EA); \
2759 }
2760
2761 #define GEN_LDU(name, ldop, opc, type) \
2762 static void glue(gen_, name##u)(DisasContext *ctx) \
2763 { \
2764 TCGv EA; \
2765 if (unlikely(rA(ctx->opcode) == 0 || \
2766 rA(ctx->opcode) == rD(ctx->opcode))) { \
2767 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2768 return; \
2769 } \
2770 gen_set_access_type(ctx, ACCESS_INT); \
2771 EA = tcg_temp_new(); \
2772 if (type == PPC_64B) \
2773 gen_addr_imm_index(ctx, EA, 0x03); \
2774 else \
2775 gen_addr_imm_index(ctx, EA, 0); \
2776 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2777 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2778 tcg_temp_free(EA); \
2779 }
2780
2781 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2782 static void glue(gen_, name##ux)(DisasContext *ctx) \
2783 { \
2784 TCGv EA; \
2785 if (unlikely(rA(ctx->opcode) == 0 || \
2786 rA(ctx->opcode) == rD(ctx->opcode))) { \
2787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2788 return; \
2789 } \
2790 gen_set_access_type(ctx, ACCESS_INT); \
2791 EA = tcg_temp_new(); \
2792 gen_addr_reg_index(ctx, EA); \
2793 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2794 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2795 tcg_temp_free(EA); \
2796 }
2797
2798 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2799 static void glue(gen_, name##x)(DisasContext *ctx) \
2800 { \
2801 TCGv EA; \
2802 gen_set_access_type(ctx, ACCESS_INT); \
2803 EA = tcg_temp_new(); \
2804 gen_addr_reg_index(ctx, EA); \
2805 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2806 tcg_temp_free(EA); \
2807 }
2808 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2809 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2810
2811 #define GEN_LDS(name, ldop, op, type) \
2812 GEN_LD(name, ldop, op | 0x20, type); \
2813 GEN_LDU(name, ldop, op | 0x21, type); \
2814 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2815 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2816
2817 /* lbz lbzu lbzux lbzx */
2818 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2819 /* lha lhau lhaux lhax */
2820 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2821 /* lhz lhzu lhzux lhzx */
2822 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2823 /* lwz lwzu lwzux lwzx */
2824 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2825 #if defined(TARGET_PPC64)
2826 /* lwaux */
2827 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2828 /* lwax */
2829 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2830 /* ldux */
2831 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2832 /* ldx */
2833 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2834
2835 static void gen_ld(DisasContext *ctx)
2836 {
2837 TCGv EA;
2838 if (Rc(ctx->opcode)) {
2839 if (unlikely(rA(ctx->opcode) == 0 ||
2840 rA(ctx->opcode) == rD(ctx->opcode))) {
2841 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2842 return;
2843 }
2844 }
2845 gen_set_access_type(ctx, ACCESS_INT);
2846 EA = tcg_temp_new();
2847 gen_addr_imm_index(ctx, EA, 0x03);
2848 if (ctx->opcode & 0x02) {
2849 /* lwa (lwau is undefined) */
2850 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2851 } else {
2852 /* ld - ldu */
2853 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2854 }
2855 if (Rc(ctx->opcode))
2856 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2857 tcg_temp_free(EA);
2858 }
2859
2860 /* lq */
2861 static void gen_lq(DisasContext *ctx)
2862 {
2863 int ra, rd;
2864 TCGv EA;
2865
2866 /* lq is a legal user mode instruction starting in ISA 2.07 */
2867 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2868 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2869
2870 if (!legal_in_user_mode && is_user_mode(ctx)) {
2871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2872 return;
2873 }
2874
2875 if (!le_is_supported && ctx->le_mode) {
2876 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2877 return;
2878 }
2879
2880 ra = rA(ctx->opcode);
2881 rd = rD(ctx->opcode);
2882 if (unlikely((rd & 1) || rd == ra)) {
2883 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2884 return;
2885 }
2886
2887 gen_set_access_type(ctx, ACCESS_INT);
2888 EA = tcg_temp_new();
2889 gen_addr_imm_index(ctx, EA, 0x0F);
2890
2891 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2892 64-bit byteswap already. */
2893 if (unlikely(ctx->le_mode)) {
2894 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2895 gen_addr_add(ctx, EA, EA, 8);
2896 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2897 } else {
2898 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2899 gen_addr_add(ctx, EA, EA, 8);
2900 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2901 }
2902 tcg_temp_free(EA);
2903 }
2904 #endif
2905
2906 /*** Integer store ***/
2907 #define GEN_ST(name, stop, opc, type) \
2908 static void glue(gen_, name)(DisasContext *ctx) \
2909 { \
2910 TCGv EA; \
2911 gen_set_access_type(ctx, ACCESS_INT); \
2912 EA = tcg_temp_new(); \
2913 gen_addr_imm_index(ctx, EA, 0); \
2914 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2915 tcg_temp_free(EA); \
2916 }
2917
2918 #define GEN_STU(name, stop, opc, type) \
2919 static void glue(gen_, stop##u)(DisasContext *ctx) \
2920 { \
2921 TCGv EA; \
2922 if (unlikely(rA(ctx->opcode) == 0)) { \
2923 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2924 return; \
2925 } \
2926 gen_set_access_type(ctx, ACCESS_INT); \
2927 EA = tcg_temp_new(); \
2928 if (type == PPC_64B) \
2929 gen_addr_imm_index(ctx, EA, 0x03); \
2930 else \
2931 gen_addr_imm_index(ctx, EA, 0); \
2932 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2933 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2934 tcg_temp_free(EA); \
2935 }
2936
2937 #define GEN_STUX(name, stop, opc2, opc3, type) \
2938 static void glue(gen_, name##ux)(DisasContext *ctx) \
2939 { \
2940 TCGv EA; \
2941 if (unlikely(rA(ctx->opcode) == 0)) { \
2942 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2943 return; \
2944 } \
2945 gen_set_access_type(ctx, ACCESS_INT); \
2946 EA = tcg_temp_new(); \
2947 gen_addr_reg_index(ctx, EA); \
2948 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2949 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2950 tcg_temp_free(EA); \
2951 }
2952
2953 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2954 static void glue(gen_, name##x)(DisasContext *ctx) \
2955 { \
2956 TCGv EA; \
2957 gen_set_access_type(ctx, ACCESS_INT); \
2958 EA = tcg_temp_new(); \
2959 gen_addr_reg_index(ctx, EA); \
2960 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2961 tcg_temp_free(EA); \
2962 }
2963 #define GEN_STX(name, stop, opc2, opc3, type) \
2964 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2965
2966 #define GEN_STS(name, stop, op, type) \
2967 GEN_ST(name, stop, op | 0x20, type); \
2968 GEN_STU(name, stop, op | 0x21, type); \
2969 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2970 GEN_STX(name, stop, 0x17, op | 0x00, type)
2971
2972 /* stb stbu stbux stbx */
2973 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2974 /* sth sthu sthux sthx */
2975 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2976 /* stw stwu stwux stwx */
2977 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2978 #if defined(TARGET_PPC64)
2979 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2980 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2981
2982 static void gen_std(DisasContext *ctx)
2983 {
2984 int rs;
2985 TCGv EA;
2986
2987 rs = rS(ctx->opcode);
2988 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2989
2990 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2991 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2992
2993 if (!legal_in_user_mode && is_user_mode(ctx)) {
2994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2995 return;
2996 }
2997
2998 if (!le_is_supported && ctx->le_mode) {
2999 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3000 return;
3001 }
3002
3003 if (unlikely(rs & 1)) {
3004 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3005 return;
3006 }
3007 gen_set_access_type(ctx, ACCESS_INT);
3008 EA = tcg_temp_new();
3009 gen_addr_imm_index(ctx, EA, 0x03);
3010
3011 /* We only need to swap high and low halves. gen_qemu_st64 does
3012 necessary 64-bit byteswap already. */
3013 if (unlikely(ctx->le_mode)) {
3014 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3015 gen_addr_add(ctx, EA, EA, 8);
3016 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3017 } else {
3018 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3019 gen_addr_add(ctx, EA, EA, 8);
3020 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3021 }
3022 tcg_temp_free(EA);
3023 } else {
3024 /* std / stdu*/
3025 if (Rc(ctx->opcode)) {
3026 if (unlikely(rA(ctx->opcode) == 0)) {
3027 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3028 return;
3029 }
3030 }
3031 gen_set_access_type(ctx, ACCESS_INT);
3032 EA = tcg_temp_new();
3033 gen_addr_imm_index(ctx, EA, 0x03);
3034 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3035 if (Rc(ctx->opcode))
3036 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3037 tcg_temp_free(EA);
3038 }
3039 }
3040 #endif
3041 /*** Integer load and store with byte reverse ***/
3042
3043 /* lhbrx */
3044 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3045 {
3046 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3047 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3048 }
3049 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3050
3051 /* lwbrx */
3052 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3053 {
3054 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3055 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3056 }
3057 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3058
3059 #if defined(TARGET_PPC64)
3060 /* ldbrx */
3061 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3062 {
3063 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3064 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3065 }
3066 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3067 #endif /* TARGET_PPC64 */
3068
3069 /* sthbrx */
3070 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3071 {
3072 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3073 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3074 }
3075 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3076
3077 /* stwbrx */
3078 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3079 {
3080 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3081 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3082 }
3083 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3084
3085 #if defined(TARGET_PPC64)
3086 /* stdbrx */
3087 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3088 {
3089 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3090 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3091 }
3092 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3093 #endif /* TARGET_PPC64 */
3094
3095 /*** Integer load and store multiple ***/
3096
3097 /* lmw */
3098 static void gen_lmw(DisasContext *ctx)
3099 {
3100 TCGv t0;
3101 TCGv_i32 t1;
3102 gen_set_access_type(ctx, ACCESS_INT);
3103 /* NIP cannot be restored if the memory exception comes from an helper */
3104 gen_update_nip(ctx, ctx->nip - 4);
3105 t0 = tcg_temp_new();
3106 t1 = tcg_const_i32(rD(ctx->opcode));
3107 gen_addr_imm_index(ctx, t0, 0);
3108 gen_helper_lmw(cpu_env, t0, t1);
3109 tcg_temp_free(t0);
3110 tcg_temp_free_i32(t1);
3111 }
3112
3113 /* stmw */
3114 static void gen_stmw(DisasContext *ctx)
3115 {
3116 TCGv t0;
3117 TCGv_i32 t1;
3118 gen_set_access_type(ctx, ACCESS_INT);
3119 /* NIP cannot be restored if the memory exception comes from an helper */
3120 gen_update_nip(ctx, ctx->nip - 4);
3121 t0 = tcg_temp_new();
3122 t1 = tcg_const_i32(rS(ctx->opcode));
3123 gen_addr_imm_index(ctx, t0, 0);
3124 gen_helper_stmw(cpu_env, t0, t1);
3125 tcg_temp_free(t0);
3126 tcg_temp_free_i32(t1);
3127 }
3128
3129 /*** Integer load and store strings ***/
3130
3131 /* lswi */
3132 /* PowerPC32 specification says we must generate an exception if
3133 * rA is in the range of registers to be loaded.
3134 * In an other hand, IBM says this is valid, but rA won't be loaded.
3135 * For now, I'll follow the spec...
3136 */
3137 static void gen_lswi(DisasContext *ctx)
3138 {
3139 TCGv t0;
3140 TCGv_i32 t1, t2;
3141 int nb = NB(ctx->opcode);
3142 int start = rD(ctx->opcode);
3143 int ra = rA(ctx->opcode);
3144 int nr;
3145
3146 if (nb == 0)
3147 nb = 32;
3148 nr = nb / 4;
3149 if (unlikely(((start + nr) > 32 &&
3150 start <= ra && (start + nr - 32) > ra) ||
3151 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3152 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3153 return;
3154 }
3155 gen_set_access_type(ctx, ACCESS_INT);
3156 /* NIP cannot be restored if the memory exception comes from an helper */
3157 gen_update_nip(ctx, ctx->nip - 4);
3158 t0 = tcg_temp_new();
3159 gen_addr_register(ctx, t0);
3160 t1 = tcg_const_i32(nb);
3161 t2 = tcg_const_i32(start);
3162 gen_helper_lsw(cpu_env, t0, t1, t2);
3163 tcg_temp_free(t0);
3164 tcg_temp_free_i32(t1);
3165 tcg_temp_free_i32(t2);
3166 }
3167
3168 /* lswx */
3169 static void gen_lswx(DisasContext *ctx)
3170 {
3171 TCGv t0;
3172 TCGv_i32 t1, t2, t3;
3173 gen_set_access_type(ctx, ACCESS_INT);
3174 /* NIP cannot be restored if the memory exception comes from an helper */
3175 gen_update_nip(ctx, ctx->nip - 4);
3176 t0 = tcg_temp_new();
3177 gen_addr_reg_index(ctx, t0);
3178 t1 = tcg_const_i32(rD(ctx->opcode));
3179 t2 = tcg_const_i32(rA(ctx->opcode));
3180 t3 = tcg_const_i32(rB(ctx->opcode));
3181 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3182 tcg_temp_free(t0);
3183 tcg_temp_free_i32(t1);
3184 tcg_temp_free_i32(t2);
3185 tcg_temp_free_i32(t3);
3186 }
3187
3188 /* stswi */
3189 static void gen_stswi(DisasContext *ctx)
3190 {
3191 TCGv t0;
3192 TCGv_i32 t1, t2;
3193 int nb = NB(ctx->opcode);
3194 gen_set_access_type(ctx, ACCESS_INT);
3195 /* NIP cannot be restored if the memory exception comes from an helper */
3196 gen_update_nip(ctx, ctx->nip - 4);
3197 t0 = tcg_temp_new();
3198 gen_addr_register(ctx, t0);
3199 if (nb == 0)
3200 nb = 32;
3201 t1 = tcg_const_i32(nb);
3202 t2 = tcg_const_i32(rS(ctx->opcode));
3203 gen_helper_stsw(cpu_env, t0, t1, t2);
3204 tcg_temp_free(t0);
3205 tcg_temp_free_i32(t1);
3206 tcg_temp_free_i32(t2);
3207 }
3208
3209 /* stswx */
3210 static void gen_stswx(DisasContext *ctx)
3211 {
3212 TCGv t0;
3213 TCGv_i32 t1, t2;
3214 gen_set_access_type(ctx, ACCESS_INT);
3215 /* NIP cannot be restored if the memory exception comes from an helper */
3216 gen_update_nip(ctx, ctx->nip - 4);
3217 t0 = tcg_temp_new();
3218 gen_addr_reg_index(ctx, t0);
3219 t1 = tcg_temp_new_i32();
3220 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3221 tcg_gen_andi_i32(t1, t1, 0x7F);
3222 t2 = tcg_const_i32(rS(ctx->opcode));
3223 gen_helper_stsw(cpu_env, t0, t1, t2);
3224 tcg_temp_free(t0);
3225 tcg_temp_free_i32(t1);
3226 tcg_temp_free_i32(t2);
3227 }
3228
3229 /*** Memory synchronisation ***/
3230 /* eieio */
3231 static void gen_eieio(DisasContext *ctx)
3232 {
3233 }
3234
3235 /* isync */
3236 static void gen_isync(DisasContext *ctx)
3237 {
3238 gen_stop_exception(ctx);
3239 }
3240
3241 #define LARX(name, len, loadop) \
3242 static void gen_##name(DisasContext *ctx) \
3243 { \
3244 TCGv t0; \
3245 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3246 gen_set_access_type(ctx, ACCESS_RES); \
3247 t0 = tcg_temp_local_new(); \
3248 gen_addr_reg_index(ctx, t0); \
3249 if ((len) > 1) { \
3250 gen_check_align(ctx, t0, (len)-1); \
3251 } \
3252 gen_qemu_##loadop(ctx, gpr, t0); \
3253 tcg_gen_mov_tl(cpu_reserve, t0); \
3254 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3255 tcg_temp_free(t0); \
3256 }
3257
3258 /* lwarx */
3259 LARX(lbarx, 1, ld8u);
3260 LARX(lharx, 2, ld16u);
3261 LARX(lwarx, 4, ld32u);
3262
3263
3264 #if defined(CONFIG_USER_ONLY)
3265 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3266 int reg, int size)
3267 {
3268 TCGv t0 = tcg_temp_new();
3269 uint32_t save_exception = ctx->exception;
3270
3271 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3272 tcg_gen_movi_tl(t0, (size << 5) | reg);
3273 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3274 tcg_temp_free(t0);
3275 gen_update_nip(ctx, ctx->nip-4);
3276 ctx->exception = POWERPC_EXCP_BRANCH;
3277 gen_exception(ctx, POWERPC_EXCP_STCX);
3278 ctx->exception = save_exception;
3279 }
3280 #else
3281 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3282 int reg, int size)
3283 {
3284 int l1;
3285
3286 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3287 l1 = gen_new_label();
3288 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3289 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3290 #if defined(TARGET_PPC64)
3291 if (size == 8) {
3292 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3293 } else
3294 #endif
3295 if (size == 4) {
3296 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3297 } else if (size == 2) {
3298 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3299 #if defined(TARGET_PPC64)
3300 } else if (size == 16) {
3301 TCGv gpr1, gpr2 , EA8;
3302 if (unlikely(ctx->le_mode)) {
3303 gpr1 = cpu_gpr[reg+1];
3304 gpr2 = cpu_gpr[reg];
3305 } else {
3306 gpr1 = cpu_gpr[reg];
3307 gpr2 = cpu_gpr[reg+1];
3308 }
3309 gen_qemu_st64(ctx, gpr1, EA);
3310 EA8 = tcg_temp_local_new();
3311 gen_addr_add(ctx, EA8, EA, 8);
3312 gen_qemu_st64(ctx, gpr2, EA8);
3313 tcg_temp_free(EA8);
3314 #endif
3315 } else {
3316 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3317 }
3318 gen_set_label(l1);
3319 tcg_gen_movi_tl(cpu_reserve, -1);
3320 }
3321 #endif
3322
3323 #define STCX(name, len) \
3324 static void gen_##name(DisasContext *ctx) \
3325 { \
3326 TCGv t0; \
3327 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3328 gen_inval_exception(ctx, \
3329 POWERPC_EXCP_INVAL_INVAL); \
3330 return; \
3331 } \
3332 gen_set_access_type(ctx, ACCESS_RES); \
3333 t0 = tcg_temp_local_new(); \
3334 gen_addr_reg_index(ctx, t0); \
3335 if (len > 1) { \
3336 gen_check_align(ctx, t0, (len)-1); \
3337 } \
3338 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3339 tcg_temp_free(t0); \
3340 }
3341
3342 STCX(stbcx_, 1);
3343 STCX(sthcx_, 2);
3344 STCX(stwcx_, 4);
3345
3346 #if defined(TARGET_PPC64)
3347 /* ldarx */
3348 LARX(ldarx, 8, ld64);
3349
3350 /* lqarx */
3351 static void gen_lqarx(DisasContext *ctx)
3352 {
3353 TCGv EA;
3354 int rd = rD(ctx->opcode);
3355 TCGv gpr1, gpr2;
3356
3357 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3358 (rd == rB(ctx->opcode)))) {
3359 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3360 return;
3361 }
3362
3363 gen_set_access_type(ctx, ACCESS_RES);
3364 EA = tcg_temp_local_new();
3365 gen_addr_reg_index(ctx, EA);
3366 gen_check_align(ctx, EA, 15);
3367 if (unlikely(ctx->le_mode)) {
3368 gpr1 = cpu_gpr[rd+1];
3369 gpr2 = cpu_gpr[rd];
3370 } else {
3371 gpr1 = cpu_gpr[rd];
3372 gpr2 = cpu_gpr[rd+1];
3373 }
3374 gen_qemu_ld64(ctx, gpr1, EA);
3375 tcg_gen_mov_tl(cpu_reserve, EA);
3376
3377 gen_addr_add(ctx, EA, EA, 8);
3378 gen_qemu_ld64(ctx, gpr2, EA);
3379
3380 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3381 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3382
3383 tcg_temp_free(EA);
3384 }
3385
3386 /* stdcx. */
3387 STCX(stdcx_, 8);
3388 STCX(stqcx_, 16);
3389 #endif /* defined(TARGET_PPC64) */
3390
3391 /* sync */
3392 static void gen_sync(DisasContext *ctx)
3393 {
3394 }
3395
3396 /* wait */
3397 static void gen_wait(DisasContext *ctx)
3398 {
3399 TCGv_i32 t0 = tcg_temp_new_i32();
3400 tcg_gen_st_i32(t0, cpu_env,
3401 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3402 tcg_temp_free_i32(t0);
3403 /* Stop translation, as the CPU is supposed to sleep from now */
3404 gen_exception_err(ctx, EXCP_HLT, 1);
3405 }
3406
3407 /*** Floating-point load ***/
3408 #define GEN_LDF(name, ldop, opc, type) \
3409 static void glue(gen_, name)(DisasContext *ctx) \
3410 { \
3411 TCGv EA; \
3412 if (unlikely(!ctx->fpu_enabled)) { \
3413 gen_exception(ctx, POWERPC_EXCP_FPU); \
3414 return; \
3415 } \
3416 gen_set_access_type(ctx, ACCESS_FLOAT); \
3417 EA = tcg_temp_new(); \
3418 gen_addr_imm_index(ctx, EA, 0); \
3419 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3420 tcg_temp_free(EA); \
3421 }
3422
3423 #define GEN_LDUF(name, ldop, opc, type) \
3424 static void glue(gen_, name##u)(DisasContext *ctx) \
3425 { \
3426 TCGv EA; \
3427 if (unlikely(!ctx->fpu_enabled)) { \
3428 gen_exception(ctx, POWERPC_EXCP_FPU); \
3429 return; \
3430 } \
3431 if (unlikely(rA(ctx->opcode) == 0)) { \
3432 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3433 return; \
3434 } \
3435 gen_set_access_type(ctx, ACCESS_FLOAT); \
3436 EA = tcg_temp_new(); \
3437 gen_addr_imm_index(ctx, EA, 0); \
3438 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3439 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3440 tcg_temp_free(EA); \
3441 }
3442
3443 #define GEN_LDUXF(name, ldop, opc, type) \
3444 static void glue(gen_, name##ux)(DisasContext *ctx) \
3445 { \
3446 TCGv EA; \
3447 if (unlikely(!ctx->fpu_enabled)) { \
3448 gen_exception(ctx, POWERPC_EXCP_FPU); \
3449 return; \
3450 } \
3451 if (unlikely(rA(ctx->opcode) == 0)) { \
3452 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3453 return; \
3454 } \
3455 gen_set_access_type(ctx, ACCESS_FLOAT); \
3456 EA = tcg_temp_new(); \
3457 gen_addr_reg_index(ctx, EA); \
3458 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3459 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3460 tcg_temp_free(EA); \
3461 }
3462
3463 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3464 static void glue(gen_, name##x)(DisasContext *ctx) \
3465 { \
3466 TCGv EA; \
3467 if (unlikely(!ctx->fpu_enabled)) { \
3468 gen_exception(ctx, POWERPC_EXCP_FPU); \
3469 return; \
3470 } \
3471 gen_set_access_type(ctx, ACCESS_FLOAT); \
3472 EA = tcg_temp_new(); \
3473 gen_addr_reg_index(ctx, EA); \
3474 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3475 tcg_temp_free(EA); \
3476 }
3477
3478 #define GEN_LDFS(name, ldop, op, type) \
3479 GEN_LDF(name, ldop, op | 0x20, type); \
3480 GEN_LDUF(name, ldop, op | 0x21, type); \
3481 GEN_LDUXF(name, ldop, op | 0x01, type); \
3482 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3483
3484 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3485 {
3486 TCGv t0 = tcg_temp_new();
3487 TCGv_i32 t1 = tcg_temp_new_i32();
3488 gen_qemu_ld32u(ctx, t0, arg2);
3489 tcg_gen_trunc_tl_i32(t1, t0);
3490 tcg_temp_free(t0);
3491 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3492 tcg_temp_free_i32(t1);
3493 }
3494
3495 /* lfd lfdu lfdux lfdx */
3496 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3497 /* lfs lfsu lfsux lfsx */
3498 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3499
3500 /* lfdp */
3501 static void gen_lfdp(DisasContext *ctx)
3502 {
3503 TCGv EA;
3504 if (unlikely(!ctx->fpu_enabled)) {
3505 gen_exception(ctx, POWERPC_EXCP_FPU);
3506 return;
3507 }
3508 gen_set_access_type(ctx, ACCESS_FLOAT);
3509 EA = tcg_temp_new();
3510 gen_addr_imm_index(ctx, EA, 0);
3511 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3512 64-bit byteswap already. */
3513 if (unlikely(ctx->le_mode)) {
3514 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3515 tcg_gen_addi_tl(EA, EA, 8);
3516 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3517 } else {
3518 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3519 tcg_gen_addi_tl(EA, EA, 8);
3520 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3521 }
3522 tcg_temp_free(EA);
3523 }
3524
3525 /* lfdpx */
3526 static void gen_lfdpx(DisasContext *ctx)
3527 {
3528 TCGv EA;
3529 if (unlikely(!ctx->fpu_enabled)) {
3530 gen_exception(ctx, POWERPC_EXCP_FPU);
3531 return;
3532 }
3533 gen_set_access_type(ctx, ACCESS_FLOAT);
3534 EA = tcg_temp_new();
3535 gen_addr_reg_index(ctx, EA);
3536 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3537 64-bit byteswap already. */
3538 if (unlikely(ctx->le_mode)) {
3539 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3540 tcg_gen_addi_tl(EA, EA, 8);
3541 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3542 } else {
3543 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3544 tcg_gen_addi_tl(EA, EA, 8);
3545 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3546 }
3547 tcg_temp_free(EA);
3548 }
3549
3550 /* lfiwax */
3551 static void gen_lfiwax(DisasContext *ctx)
3552 {
3553 TCGv EA;
3554 TCGv t0;
3555 if (unlikely(!ctx->fpu_enabled)) {
3556 gen_exception(ctx, POWERPC_EXCP_FPU);
3557 return;
3558 }
3559 gen_set_access_type(ctx, ACCESS_FLOAT);
3560 EA = tcg_temp_new();
3561 t0 = tcg_temp_new();
3562 gen_addr_reg_index(ctx, EA);
3563 gen_qemu_ld32s(ctx, t0, EA);
3564 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3565 tcg_temp_free(EA);
3566 tcg_temp_free(t0);
3567 }
3568
3569 /* lfiwzx */
3570 static void gen_lfiwzx(DisasContext *ctx)
3571 {
3572 TCGv EA;
3573 if (unlikely(!ctx->fpu_enabled)) {
3574 gen_exception(ctx, POWERPC_EXCP_FPU);
3575 return;
3576 }
3577 gen_set_access_type(ctx, ACCESS_FLOAT);
3578 EA = tcg_temp_new();
3579 gen_addr_reg_index(ctx, EA);
3580 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3581 tcg_temp_free(EA);
3582 }
3583 /*** Floating-point store ***/
3584 #define GEN_STF(name, stop, opc, type) \
3585 static void glue(gen_, name)(DisasContext *ctx) \
3586 { \
3587 TCGv EA; \
3588 if (unlikely(!ctx->fpu_enabled)) { \
3589 gen_exception(ctx, POWERPC_EXCP_FPU); \
3590 return; \
3591 } \
3592 gen_set_access_type(ctx, ACCESS_FLOAT); \
3593 EA = tcg_temp_new(); \
3594 gen_addr_imm_index(ctx, EA, 0); \
3595 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3596 tcg_temp_free(EA); \
3597 }
3598
3599 #define GEN_STUF(name, stop, opc, type) \
3600 static void glue(gen_, name##u)(DisasContext *ctx) \
3601 { \
3602 TCGv EA; \
3603 if (unlikely(!ctx->fpu_enabled)) { \
3604 gen_exception(ctx, POWERPC_EXCP_FPU); \
3605 return; \
3606 } \
3607 if (unlikely(rA(ctx->opcode) == 0)) { \
3608 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3609 return; \
3610 } \
3611 gen_set_access_type(ctx, ACCESS_FLOAT); \
3612 EA = tcg_temp_new(); \
3613 gen_addr_imm_index(ctx, EA, 0); \
3614 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3615 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3616 tcg_temp_free(EA); \
3617 }
3618
3619 #define GEN_STUXF(name, stop, opc, type) \
3620 static void glue(gen_, name##ux)(DisasContext *ctx) \
3621 { \
3622 TCGv EA; \
3623 if (unlikely(!ctx->fpu_enabled)) { \
3624 gen_exception(ctx, POWERPC_EXCP_FPU); \
3625 return; \
3626 } \
3627 if (unlikely(rA(ctx->opcode) == 0)) { \
3628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3629 return; \
3630 } \
3631 gen_set_access_type(ctx, ACCESS_FLOAT); \
3632 EA = tcg_temp_new(); \
3633 gen_addr_reg_index(ctx, EA); \
3634 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3635 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3636 tcg_temp_free(EA); \
3637 }
3638
3639 #define GEN_STXF(name, stop, opc2, opc3, type) \
3640 static void glue(gen_, name##x)(DisasContext *ctx) \
3641 { \
3642 TCGv EA; \
3643 if (unlikely(!ctx->fpu_enabled)) { \
3644 gen_exception(ctx, POWERPC_EXCP_FPU); \
3645 return; \
3646 } \
3647 gen_set_access_type(ctx, ACCESS_FLOAT); \
3648 EA = tcg_temp_new(); \
3649 gen_addr_reg_index(ctx, EA); \
3650 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3651 tcg_temp_free(EA); \
3652 }
3653
3654 #define GEN_STFS(name, stop, op, type) \
3655 GEN_STF(name, stop, op | 0x20, type); \
3656 GEN_STUF(name, stop, op | 0x21, type); \
3657 GEN_STUXF(name, stop, op | 0x01, type); \
3658 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3659
3660 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3661 {
3662 TCGv_i32 t0 = tcg_temp_new_i32();
3663 TCGv t1 = tcg_temp_new();
3664 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3665 tcg_gen_extu_i32_tl(t1, t0);
3666 tcg_temp_free_i32(t0);
3667 gen_qemu_st32(ctx, t1, arg2);
3668 tcg_temp_free(t1);
3669 }
3670
3671 /* stfd stfdu stfdux stfdx */
3672 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3673 /* stfs stfsu stfsux stfsx */
3674 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3675
3676 /* stfdp */
3677 static void gen_stfdp(DisasContext *ctx)
3678 {
3679 TCGv EA;
3680 if (unlikely(!ctx->fpu_enabled)) {
3681 gen_exception(ctx, POWERPC_EXCP_FPU);
3682 return;
3683 }
3684 gen_set_access_type(ctx, ACCESS_FLOAT);
3685 EA = tcg_temp_new();
3686 gen_addr_imm_index(ctx, EA, 0);
3687 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3688 64-bit byteswap already. */
3689 if (unlikely(ctx->le_mode)) {
3690 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3691 tcg_gen_addi_tl(EA, EA, 8);
3692 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3693 } else {
3694 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3695 tcg_gen_addi_tl(EA, EA, 8);
3696 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3697 }
3698 tcg_temp_free(EA);
3699 }
3700
3701 /* stfdpx */
3702 static void gen_stfdpx(DisasContext *ctx)
3703 {
3704 TCGv EA;
3705 if (unlikely(!ctx->fpu_enabled)) {
3706 gen_exception(ctx, POWERPC_EXCP_FPU);
3707 return;
3708 }
3709 gen_set_access_type(ctx, ACCESS_FLOAT);
3710 EA = tcg_temp_new();
3711 gen_addr_reg_index(ctx, EA);
3712 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3713 64-bit byteswap already. */
3714 if (unlikely(ctx->le_mode)) {
3715 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3716 tcg_gen_addi_tl(EA, EA, 8);
3717 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3718 } else {
3719 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3720 tcg_gen_addi_tl(EA, EA, 8);
3721 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3722 }
3723 tcg_temp_free(EA);
3724 }
3725
3726 /* Optional: */
3727 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3728 {
3729 TCGv t0 = tcg_temp_new();
3730 tcg_gen_trunc_i64_tl(t0, arg1),
3731 gen_qemu_st32(ctx, t0, arg2);
3732 tcg_temp_free(t0);
3733 }
3734 /* stfiwx */
3735 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3736
3737 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3738 {
3739 #if defined(TARGET_PPC64)
3740 if (ctx->has_cfar)
3741 tcg_gen_movi_tl(cpu_cfar, nip);
3742 #endif
3743 }
3744
3745 /*** Branch ***/
3746 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3747 {
3748 TranslationBlock *tb;
3749 tb = ctx->tb;
3750 if (NARROW_MODE(ctx)) {
3751 dest = (uint32_t) dest;
3752 }
3753 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3754 likely(!ctx->singlestep_enabled)) {
3755 tcg_gen_goto_tb(n);
3756 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3757 tcg_gen_exit_tb((uintptr_t)tb + n);
3758 } else {
3759 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3760 if (unlikely(ctx->singlestep_enabled)) {
3761 if ((ctx->singlestep_enabled &
3762 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3763 (ctx->exception == POWERPC_EXCP_BRANCH ||
3764 ctx->exception == POWERPC_EXCP_TRACE)) {
3765 target_ulong tmp = ctx->nip;
3766 ctx->nip = dest;
3767 gen_exception(ctx, POWERPC_EXCP_TRACE);
3768 ctx->nip = tmp;
3769 }
3770 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3771 gen_debug_exception(ctx);
3772 }
3773 }
3774 tcg_gen_exit_tb(0);
3775 }
3776 }
3777
3778 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3779 {
3780 if (NARROW_MODE(ctx)) {
3781 nip = (uint32_t)nip;
3782 }
3783 tcg_gen_movi_tl(cpu_lr, nip);
3784 }
3785
3786 /* b ba bl bla */
3787 static void gen_b(DisasContext *ctx)
3788 {
3789 target_ulong li, target;
3790
3791 ctx->exception = POWERPC_EXCP_BRANCH;
3792 /* sign extend LI */
3793 li = LI(ctx->opcode);
3794 li = (li ^ 0x02000000) - 0x02000000;
3795 if (likely(AA(ctx->opcode) == 0)) {
3796 target = ctx->nip + li - 4;
3797 } else {
3798 target = li;
3799 }
3800 if (LK(ctx->opcode)) {
3801 gen_setlr(ctx, ctx->nip);
3802 }
3803 gen_update_cfar(ctx, ctx->nip);
3804 gen_goto_tb(ctx, 0, target);
3805 }
3806
3807 #define BCOND_IM 0
3808 #define BCOND_LR 1
3809 #define BCOND_CTR 2
3810 #define BCOND_TAR 3
3811
3812 static inline void gen_bcond(DisasContext *ctx, int type)
3813 {
3814 uint32_t bo = BO(ctx->opcode);
3815 int l1;
3816 TCGv target;
3817
3818 ctx->exception = POWERPC_EXCP_BRANCH;
3819 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3820 target = tcg_temp_local_new();
3821 if (type == BCOND_CTR)
3822 tcg_gen_mov_tl(target, cpu_ctr);
3823 else if (type == BCOND_TAR)
3824 gen_load_spr(target, SPR_TAR);
3825 else
3826 tcg_gen_mov_tl(target, cpu_lr);
3827 } else {
3828 TCGV_UNUSED(target);
3829 }
3830 if (LK(ctx->opcode))
3831 gen_setlr(ctx, ctx->nip);
3832 l1 = gen_new_label();
3833 if ((bo & 0x4) == 0) {
3834 /* Decrement and test CTR */
3835 TCGv temp = tcg_temp_new();
3836 if (unlikely(type == BCOND_CTR)) {
3837 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3838 return;
3839 }
3840 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3841 if (NARROW_MODE(ctx)) {
3842 tcg_gen_ext32u_tl(temp, cpu_ctr);
3843 } else {
3844 tcg_gen_mov_tl(temp, cpu_ctr);
3845 }
3846 if (bo & 0x2) {
3847 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3848 } else {
3849 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3850 }
3851 tcg_temp_free(temp);
3852 }
3853 if ((bo & 0x10) == 0) {
3854 /* Test CR */
3855 uint32_t bi = BI(ctx->opcode);
3856 uint32_t mask = 1 << (3 - (bi & 0x03));
3857 TCGv_i32 temp = tcg_temp_new_i32();
3858
3859 if (bo & 0x8) {
3860 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3861 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3862 } else {
3863 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3864 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3865 }
3866 tcg_temp_free_i32(temp);
3867 }
3868 gen_update_cfar(ctx, ctx->nip);
3869 if (type == BCOND_IM) {
3870 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3871 if (likely(AA(ctx->opcode) == 0)) {
3872 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3873 } else {
3874 gen_goto_tb(ctx, 0, li);
3875 }
3876 gen_set_label(l1);
3877 gen_goto_tb(ctx, 1, ctx->nip);
3878 } else {
3879 if (NARROW_MODE(ctx)) {
3880 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3881 } else {
3882 tcg_gen_andi_tl(cpu_nip, target, ~3);
3883 }
3884 tcg_gen_exit_tb(0);
3885 gen_set_label(l1);
3886 gen_update_nip(ctx, ctx->nip);
3887 tcg_gen_exit_tb(0);
3888 }
3889 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3890 tcg_temp_free(target);
3891 }
3892 }
3893
3894 static void gen_bc(DisasContext *ctx)
3895 {
3896 gen_bcond(ctx, BCOND_IM);
3897 }
3898
3899 static void gen_bcctr(DisasContext *ctx)
3900 {
3901 gen_bcond(ctx, BCOND_CTR);
3902 }
3903
3904 static void gen_bclr(DisasContext *ctx)
3905 {
3906 gen_bcond(ctx, BCOND_LR);
3907 }
3908
3909 static void gen_bctar(DisasContext *ctx)
3910 {
3911 gen_bcond(ctx, BCOND_TAR);
3912 }
3913
3914 /*** Condition register logical ***/
3915 #define GEN_CRLOGIC(name, tcg_op, opc) \
3916 static void glue(gen_, name)(DisasContext *ctx) \
3917 { \
3918 uint8_t bitmask; \
3919 int sh; \
3920 TCGv_i32 t0, t1; \
3921 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3922 t0 = tcg_temp_new_i32(); \
3923 if (sh > 0) \
3924 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3925 else if (sh < 0) \
3926 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3927 else \
3928 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3929 t1 = tcg_temp_new_i32(); \
3930 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3931 if (sh > 0) \
3932 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3933 else if (sh < 0) \
3934 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3935 else \
3936 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3937 tcg_op(t0, t0, t1); \
3938 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3939 tcg_gen_andi_i32(t0, t0, bitmask); \
3940 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3941 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3942 tcg_temp_free_i32(t0); \
3943 tcg_temp_free_i32(t1); \
3944 }
3945
3946 /* crand */
3947 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3948 /* crandc */
3949 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3950 /* creqv */
3951 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3952 /* crnand */
3953 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3954 /* crnor */
3955 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3956 /* cror */
3957 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3958 /* crorc */
3959 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3960 /* crxor */
3961 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3962
3963 /* mcrf */
3964 static void gen_mcrf(DisasContext *ctx)
3965 {
3966 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3967 }
3968
3969 /*** System linkage ***/
3970
3971 /* rfi (mem_idx only) */
3972 static void gen_rfi(DisasContext *ctx)
3973 {
3974 #if defined(CONFIG_USER_ONLY)
3975 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3976 #else
3977 /* Restore CPU state */
3978 if (unlikely(!ctx->mem_idx)) {
3979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3980 return;
3981 }
3982 gen_update_cfar(ctx, ctx->nip);
3983 gen_helper_rfi(cpu_env);
3984 gen_sync_exception(ctx);
3985 #endif
3986 }
3987
3988 #if defined(TARGET_PPC64)
3989 static void gen_rfid(DisasContext *ctx)
3990 {
3991 #if defined(CONFIG_USER_ONLY)
3992 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3993 #else
3994 /* Restore CPU state */
3995 if (unlikely(!ctx->mem_idx)) {
3996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3997 return;
3998 }
3999 gen_update_cfar(ctx, ctx->nip);
4000 gen_helper_rfid(cpu_env);
4001 gen_sync_exception(ctx);
4002 #endif
4003 }
4004
4005 static void gen_hrfid(DisasContext *ctx)
4006 {
4007 #if defined(CONFIG_USER_ONLY)
4008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4009 #else
4010 /* Restore CPU state */
4011 if (unlikely(ctx->mem_idx <= 1)) {
4012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4013 return;
4014 }
4015 gen_helper_hrfid(cpu_env);
4016 gen_sync_exception(ctx);
4017 #endif
4018 }
4019 #endif
4020
4021 /* sc */
4022 #if defined(CONFIG_USER_ONLY)
4023 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4024 #else
4025 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4026 #endif
4027 static void gen_sc(DisasContext *ctx)
4028 {
4029 uint32_t lev;
4030
4031 lev = (ctx->opcode >> 5) & 0x7F;
4032 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4033 }
4034
4035 /*** Trap ***/
4036
4037 /* tw */
4038 static void gen_tw(DisasContext *ctx)
4039 {
4040 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4041 /* Update the nip since this might generate a trap exception */
4042 gen_update_nip(ctx, ctx->nip);
4043 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4044 t0);
4045 tcg_temp_free_i32(t0);
4046 }
4047
4048 /* twi */
4049 static void gen_twi(DisasContext *ctx)
4050 {
4051 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4052 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4053 /* Update the nip since this might generate a trap exception */
4054 gen_update_nip(ctx, ctx->nip);
4055 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4056 tcg_temp_free(t0);
4057 tcg_temp_free_i32(t1);
4058 }
4059
4060 #if defined(TARGET_PPC64)
4061 /* td */
4062 static void gen_td(DisasContext *ctx)
4063 {
4064 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4065 /* Update the nip since this might generate a trap exception */
4066 gen_update_nip(ctx, ctx->nip);
4067 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4068 t0);
4069 tcg_temp_free_i32(t0);
4070 }
4071
4072 /* tdi */
4073 static void gen_tdi(DisasContext *ctx)
4074 {
4075 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4076 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4077 /* Update the nip since this might generate a trap exception */
4078 gen_update_nip(ctx, ctx->nip);
4079 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4080 tcg_temp_free(t0);
4081 tcg_temp_free_i32(t1);
4082 }
4083 #endif
4084
4085 /*** Processor control ***/
4086
4087 static void gen_read_xer(TCGv dst)
4088 {
4089 TCGv t0 = tcg_temp_new();
4090 TCGv t1 = tcg_temp_new();
4091 TCGv t2 = tcg_temp_new();
4092 tcg_gen_mov_tl(dst, cpu_xer);
4093 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4094 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4095 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4096 tcg_gen_or_tl(t0, t0, t1);
4097 tcg_gen_or_tl(dst, dst, t2);
4098 tcg_gen_or_tl(dst, dst, t0);
4099 tcg_temp_free(t0);
4100 tcg_temp_free(t1);
4101 tcg_temp_free(t2);
4102 }
4103
4104 static void gen_write_xer(TCGv src)
4105 {
4106 tcg_gen_andi_tl(cpu_xer, src,
4107 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4108 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4109 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4110 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4111 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4112 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4113 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4114 }
4115
4116 /* mcrxr */
4117 static void gen_mcrxr(DisasContext *ctx)
4118 {
4119 TCGv_i32 t0 = tcg_temp_new_i32();
4120 TCGv_i32 t1 = tcg_temp_new_i32();
4121 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4122
4123 tcg_gen_trunc_tl_i32(t0, cpu_so);
4124 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4125 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4126 tcg_gen_shri_i32(t0, t0, 2);
4127 tcg_gen_shri_i32(t1, t1, 1);
4128 tcg_gen_or_i32(dst, dst, t0);
4129 tcg_gen_or_i32(dst, dst, t1);
4130 tcg_temp_free_i32(t0);
4131 tcg_temp_free_i32(t1);
4132
4133 tcg_gen_movi_tl(cpu_so, 0);
4134 tcg_gen_movi_tl(cpu_ov, 0);
4135 tcg_gen_movi_tl(cpu_ca, 0);
4136 }
4137
4138 /* mfcr mfocrf */
4139 static void gen_mfcr(DisasContext *ctx)
4140 {
4141 uint32_t crm, crn;
4142
4143 if (likely(ctx->opcode & 0x00100000)) {
4144 crm = CRM(ctx->opcode);
4145 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4146 crn = ctz32 (crm);
4147 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4148 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4149 cpu_gpr[rD(ctx->opcode)], crn * 4);
4150 }
4151 } else {
4152 TCGv_i32 t0 = tcg_temp_new_i32();
4153 tcg_gen_mov_i32(t0, cpu_crf[0]);
4154 tcg_gen_shli_i32(t0, t0, 4);
4155 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4156 tcg_gen_shli_i32(t0, t0, 4);
4157 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4158 tcg_gen_shli_i32(t0, t0, 4);
4159 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4160 tcg_gen_shli_i32(t0, t0, 4);
4161 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4162 tcg_gen_shli_i32(t0, t0, 4);
4163 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4164 tcg_gen_shli_i32(t0, t0, 4);
4165 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4166 tcg_gen_shli_i32(t0, t0, 4);
4167 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4168 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4169 tcg_temp_free_i32(t0);
4170 }
4171 }
4172
4173 /* mfmsr */
4174 static void gen_mfmsr(DisasContext *ctx)
4175 {
4176 #if defined(CONFIG_USER_ONLY)
4177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4178 #else
4179 if (unlikely(!ctx->mem_idx)) {
4180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4181 return;
4182 }
4183 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4184 #endif
4185 }
4186
4187 static void spr_noaccess(void *opaque, int gprn, int sprn)
4188 {
4189 #if 0
4190 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4191 printf("ERROR: try to access SPR %d !\n", sprn);
4192 #endif
4193 }
4194 #define SPR_NOACCESS (&spr_noaccess)
4195
4196 /* mfspr */
4197 static inline void gen_op_mfspr(DisasContext *ctx)
4198 {
4199 void (*read_cb)(void *opaque, int gprn, int sprn);
4200 uint32_t sprn = SPR(ctx->opcode);
4201
4202 #if !defined(CONFIG_USER_ONLY)
4203 if (ctx->mem_idx == 2)
4204 read_cb = ctx->spr_cb[sprn].hea_read;
4205 else if (ctx->mem_idx)
4206 read_cb = ctx->spr_cb[sprn].oea_read;
4207 else
4208 #endif
4209 read_cb = ctx->spr_cb[sprn].uea_read;
4210 if (likely(read_cb != NULL)) {
4211 if (likely(read_cb != SPR_NOACCESS)) {
4212 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4213 } else {
4214 /* Privilege exception */
4215 /* This is a hack to avoid warnings when running Linux:
4216 * this OS breaks the PowerPC virtualisation model,
4217 * allowing userland application to read the PVR
4218 */
4219 if (sprn != SPR_PVR) {
4220 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4221 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4222 printf("Trying to read privileged spr %d (0x%03x) at "
4223 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4224 }
4225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4226 }
4227 } else {
4228 /* Not defined */
4229 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4230 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4231 printf("Trying to read invalid spr %d (0x%03x) at "
4232 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4233 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4234 }
4235 }
4236
4237 static void gen_mfspr(DisasContext *ctx)
4238 {
4239 gen_op_mfspr(ctx);
4240 }
4241
4242 /* mftb */
4243 static void gen_mftb(DisasContext *ctx)
4244 {
4245 gen_op_mfspr(ctx);
4246 }
4247
4248 /* mtcrf mtocrf*/
4249 static void gen_mtcrf(DisasContext *ctx)
4250 {
4251 uint32_t crm, crn;
4252
4253 crm = CRM(ctx->opcode);
4254 if (likely((ctx->opcode & 0x00100000))) {
4255 if (crm && ((crm & (crm - 1)) == 0)) {
4256 TCGv_i32 temp = tcg_temp_new_i32();
4257 crn = ctz32 (crm);
4258 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4259 tcg_gen_shri_i32(temp, temp, crn * 4);
4260 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4261 tcg_temp_free_i32(temp);
4262 }
4263 } else {
4264 TCGv_i32 temp = tcg_temp_new_i32();
4265 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4266 for (crn = 0 ; crn < 8 ; crn++) {
4267 if (crm & (1 << crn)) {
4268 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4269 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4270 }
4271 }
4272 tcg_temp_free_i32(temp);
4273 }
4274 }
4275
4276 /* mtmsr */
4277 #if defined(TARGET_PPC64)
4278 static void gen_mtmsrd(DisasContext *ctx)
4279 {
4280 #if defined(CONFIG_USER_ONLY)
4281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4282 #else
4283 if (unlikely(!ctx->mem_idx)) {
4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4285 return;
4286 }
4287 if (ctx->opcode & 0x00010000) {
4288 /* Special form that does not need any synchronisation */
4289 TCGv t0 = tcg_temp_new();
4290 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4291 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4292 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4293 tcg_temp_free(t0);
4294 } else {
4295 /* XXX: we need to update nip before the store
4296 * if we enter power saving mode, we will exit the loop
4297 * directly from ppc_store_msr
4298 */
4299 gen_update_nip(ctx, ctx->nip);
4300 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4301 /* Must stop the translation as machine state (may have) changed */
4302 /* Note that mtmsr is not always defined as context-synchronizing */
4303 gen_stop_exception(ctx);
4304 }
4305 #endif
4306 }
4307 #endif
4308
4309 static void gen_mtmsr(DisasContext *ctx)
4310 {
4311 #if defined(CONFIG_USER_ONLY)
4312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4313 #else
4314 if (unlikely(!ctx->mem_idx)) {
4315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4316 return;
4317 }
4318 if (ctx->opcode & 0x00010000) {
4319 /* Special form that does not need any synchronisation */
4320 TCGv t0 = tcg_temp_new();
4321 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4322 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4323 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4324 tcg_temp_free(t0);
4325 } else {
4326 TCGv msr = tcg_temp_new();
4327
4328 /* XXX: we need to update nip before the store
4329 * if we enter power saving mode, we will exit the loop
4330 * directly from ppc_store_msr
4331 */
4332 gen_update_nip(ctx, ctx->nip);
4333 #if defined(TARGET_PPC64)
4334 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4335 #else
4336 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4337 #endif
4338 gen_helper_store_msr(cpu_env, msr);
4339 tcg_temp_free(msr);
4340 /* Must stop the translation as machine state (may have) changed */
4341 /* Note that mtmsr is not always defined as context-synchronizing */
4342 gen_stop_exception(ctx);
4343 }
4344 #endif
4345 }
4346
4347 /* mtspr */
4348 static void gen_mtspr(DisasContext *ctx)
4349 {
4350 void (*write_cb)(void *opaque, int sprn, int gprn);
4351 uint32_t sprn = SPR(ctx->opcode);
4352
4353 #if !defined(CONFIG_USER_ONLY)
4354 if (ctx->mem_idx == 2)
4355 write_cb = ctx->spr_cb[sprn].hea_write;
4356 else if (ctx->mem_idx)
4357 write_cb = ctx->spr_cb[sprn].oea_write;
4358 else
4359 #endif
4360 write_cb = ctx->spr_cb[sprn].uea_write;
4361 if (likely(write_cb != NULL)) {
4362 if (likely(write_cb != SPR_NOACCESS)) {
4363 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4364 } else {
4365 /* Privilege exception */
4366 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4367 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4368 printf("Trying to write privileged spr %d (0x%03x) at "
4369 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4371 }
4372 } else {
4373 /* Not defined */
4374 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4375 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4376 printf("Trying to write invalid spr %d (0x%03x) at "
4377 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4378 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4379 }
4380 }
4381
4382 /*** Cache management ***/
4383
4384 /* dcbf */
4385 static void gen_dcbf(DisasContext *ctx)
4386 {
4387 /* XXX: specification says this is treated as a load by the MMU */
4388 TCGv t0;
4389 gen_set_access_type(ctx, ACCESS_CACHE);
4390 t0 = tcg_temp_new();
4391 gen_addr_reg_index(ctx, t0);
4392 gen_qemu_ld8u(ctx, t0, t0);
4393 tcg_temp_free(t0);
4394 }
4395
4396 /* dcbi (Supervisor only) */
4397 static void gen_dcbi(DisasContext *ctx)
4398 {
4399 #if defined(CONFIG_USER_ONLY)
4400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4401 #else
4402 TCGv EA, val;
4403 if (unlikely(!ctx->mem_idx)) {
4404 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4405 return;
4406 }
4407 EA = tcg_temp_new();
4408 gen_set_access_type(ctx, ACCESS_CACHE);
4409 gen_addr_reg_index(ctx, EA);
4410 val = tcg_temp_new();
4411 /* XXX: specification says this should be treated as a store by the MMU */
4412 gen_qemu_ld8u(ctx, val, EA);
4413 gen_qemu_st8(ctx, val, EA);
4414 tcg_temp_free(val);
4415 tcg_temp_free(EA);
4416 #endif
4417 }
4418
4419 /* dcdst */
4420 static void gen_dcbst(DisasContext *ctx)
4421 {
4422 /* XXX: specification say this is treated as a load by the MMU */
4423 TCGv t0;
4424 gen_set_access_type(ctx, ACCESS_CACHE);
4425 t0 = tcg_temp_new();
4426 gen_addr_reg_index(ctx, t0);
4427 gen_qemu_ld8u(ctx, t0, t0);
4428 tcg_temp_free(t0);
4429 }
4430
4431 /* dcbt */
4432 static void gen_dcbt(DisasContext *ctx)
4433 {
4434 /* interpreted as no-op */
4435 /* XXX: specification say this is treated as a load by the MMU
4436 * but does not generate any exception
4437 */
4438 }
4439
4440 /* dcbtst */
4441 static void gen_dcbtst(DisasContext *ctx)
4442 {
4443 /* interpreted as no-op */
4444 /* XXX: specification say this is treated as a load by the MMU
4445 * but does not generate any exception
4446 */
4447 }
4448
4449 /* dcbtls */
4450 static void gen_dcbtls(DisasContext *ctx)
4451 {
4452 /* Always fails locking the cache */
4453 TCGv t0 = tcg_temp_new();
4454 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4455 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4456 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4457 tcg_temp_free(t0);
4458 }
4459
4460 /* dcbz */
4461 static void gen_dcbz(DisasContext *ctx)
4462 {
4463 TCGv tcgv_addr;
4464 TCGv_i32 tcgv_is_dcbzl;
4465 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4466
4467 gen_set_access_type(ctx, ACCESS_CACHE);
4468 /* NIP cannot be restored if the memory exception comes from an helper */
4469 gen_update_nip(ctx, ctx->nip - 4);
4470 tcgv_addr = tcg_temp_new();
4471 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4472
4473 gen_addr_reg_index(ctx, tcgv_addr);
4474 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4475
4476 tcg_temp_free(tcgv_addr);
4477 tcg_temp_free_i32(tcgv_is_dcbzl);
4478 }
4479
4480 /* dst / dstt */
4481 static void gen_dst(DisasContext *ctx)
4482 {
4483 if (rA(ctx->opcode) == 0) {
4484 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4485 } else {
4486 /* interpreted as no-op */
4487 }
4488 }
4489
4490 /* dstst /dststt */
4491 static void gen_dstst(DisasContext *ctx)
4492 {
4493 if (rA(ctx->opcode) == 0) {
4494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4495 } else {
4496 /* interpreted as no-op */
4497 }
4498
4499 }
4500
4501 /* dss / dssall */
4502 static void gen_dss(DisasContext *ctx)
4503 {
4504 /* interpreted as no-op */
4505 }
4506
4507 /* icbi */
4508 static void gen_icbi(DisasContext *ctx)
4509 {
4510 TCGv t0;
4511 gen_set_access_type(ctx, ACCESS_CACHE);
4512 /* NIP cannot be restored if the memory exception comes from an helper */
4513 gen_update_nip(ctx, ctx->nip - 4);
4514 t0 = tcg_temp_new();
4515 gen_addr_reg_index(ctx, t0);
4516 gen_helper_icbi(cpu_env, t0);
4517 tcg_temp_free(t0);
4518 }
4519
4520 /* Optional: */
4521 /* dcba */
4522 static void gen_dcba(DisasContext *ctx)
4523 {
4524 /* interpreted as no-op */
4525 /* XXX: specification say this is treated as a store by the MMU
4526 * but does not generate any exception
4527 */
4528 }
4529
4530 /*** Segment register manipulation ***/
4531 /* Supervisor only: */
4532
4533 /* mfsr */
4534 static void gen_mfsr(DisasContext *ctx)
4535 {
4536 #if defined(CONFIG_USER_ONLY)
4537 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4538 #else
4539 TCGv t0;
4540 if (unlikely(!ctx->mem_idx)) {
4541 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4542 return;
4543 }
4544 t0 = tcg_const_tl(SR(ctx->opcode));
4545 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4546 tcg_temp_free(t0);
4547 #endif
4548 }
4549
4550 /* mfsrin */
4551 static void gen_mfsrin(DisasContext *ctx)
4552 {
4553 #if defined(CONFIG_USER_ONLY)
4554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4555 #else
4556 TCGv t0;
4557 if (unlikely(!ctx->mem_idx)) {
4558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4559 return;
4560 }
4561 t0 = tcg_temp_new();
4562 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4563 tcg_gen_andi_tl(t0, t0, 0xF);
4564 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4565 tcg_temp_free(t0);
4566 #endif
4567 }
4568
4569 /* mtsr */
4570 static void gen_mtsr(DisasContext *ctx)
4571 {
4572 #if defined(CONFIG_USER_ONLY)
4573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4574 #else
4575 TCGv t0;
4576 if (unlikely(!ctx->mem_idx)) {
4577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4578 return;
4579 }
4580 t0 = tcg_const_tl(SR(ctx->opcode));
4581 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4582 tcg_temp_free(t0);
4583 #endif
4584 }
4585
4586 /* mtsrin */
4587 static void gen_mtsrin(DisasContext *ctx)
4588 {
4589 #if defined(CONFIG_USER_ONLY)
4590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4591 #else
4592 TCGv t0;
4593 if (unlikely(!ctx->mem_idx)) {
4594 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4595 return;
4596 }
4597 t0 = tcg_temp_new();
4598 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4599 tcg_gen_andi_tl(t0, t0, 0xF);
4600 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4601 tcg_temp_free(t0);
4602 #endif
4603 }
4604
4605 #if defined(TARGET_PPC64)
4606 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4607
4608 /* mfsr */
4609 static void gen_mfsr_64b(DisasContext *ctx)
4610 {
4611 #if defined(CONFIG_USER_ONLY)
4612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4613 #else
4614 TCGv t0;
4615 if (unlikely(!ctx->mem_idx)) {
4616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4617 return;
4618 }
4619 t0 = tcg_const_tl(SR(ctx->opcode));
4620 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4621 tcg_temp_free(t0);
4622 #endif
4623 }
4624
4625 /* mfsrin */
4626 static void gen_mfsrin_64b(DisasContext *ctx)
4627 {
4628 #if defined(CONFIG_USER_ONLY)
4629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4630 #else
4631 TCGv t0;
4632 if (unlikely(!ctx->mem_idx)) {
4633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4634 return;
4635 }
4636 t0 = tcg_temp_new();
4637 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4638 tcg_gen_andi_tl(t0, t0, 0xF);
4639 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4640 tcg_temp_free(t0);
4641 #endif
4642 }
4643
4644 /* mtsr */
4645 static void gen_mtsr_64b(DisasContext *ctx)
4646 {
4647 #if defined(CONFIG_USER_ONLY)
4648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4649 #else
4650 TCGv t0;
4651 if (unlikely(!ctx->mem_idx)) {
4652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4653 return;
4654 }
4655 t0 = tcg_const_tl(SR(ctx->opcode));
4656 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4657 tcg_temp_free(t0);
4658 #endif
4659 }
4660
4661 /* mtsrin */
4662 static void gen_mtsrin_64b(DisasContext *ctx)
4663 {
4664 #if defined(CONFIG_USER_ONLY)
4665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4666 #else
4667 TCGv t0;
4668 if (unlikely(!ctx->mem_idx)) {
4669 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4670 return;
4671 }
4672 t0 = tcg_temp_new();
4673 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4674 tcg_gen_andi_tl(t0, t0, 0xF);
4675 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4676 tcg_temp_free(t0);
4677 #endif
4678 }
4679
4680 /* slbmte */
4681 static void gen_slbmte(DisasContext *ctx)
4682 {
4683 #if defined(CONFIG_USER_ONLY)
4684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4685 #else
4686 if (unlikely(!ctx->mem_idx)) {
4687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4688 return;
4689 }
4690 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4691 cpu_gpr[rS(ctx->opcode)]);
4692 #endif
4693 }
4694
4695 static void gen_slbmfee(DisasContext *ctx)
4696 {
4697 #if defined(CONFIG_USER_ONLY)
4698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4699 #else
4700 if (unlikely(!ctx->mem_idx)) {
4701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4702 return;
4703 }
4704 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4705 cpu_gpr[rB(ctx->opcode)]);
4706 #endif
4707 }
4708
4709 static void gen_slbmfev(DisasContext *ctx)
4710 {
4711 #if defined(CONFIG_USER_ONLY)
4712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4713 #else
4714 if (unlikely(!ctx->mem_idx)) {
4715 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4716 return;
4717 }
4718 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4719 cpu_gpr[rB(ctx->opcode)]);
4720 #endif
4721 }
4722 #endif /* defined(TARGET_PPC64) */
4723
4724 /*** Lookaside buffer management ***/
4725 /* Optional & mem_idx only: */
4726
4727 /* tlbia */
4728 static void gen_tlbia(DisasContext *ctx)
4729 {
4730 #if defined(CONFIG_USER_ONLY)
4731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4732 #else
4733 if (unlikely(!ctx->mem_idx)) {
4734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4735 return;
4736 }
4737 gen_helper_tlbia(cpu_env);
4738 #endif
4739 }
4740
4741 /* tlbiel */
4742 static void gen_tlbiel(DisasContext *ctx)
4743 {
4744 #if defined(CONFIG_USER_ONLY)
4745 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4746 #else
4747 if (unlikely(!ctx->mem_idx)) {
4748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4749 return;
4750 }
4751 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4752 #endif
4753 }
4754
4755 /* tlbie */
4756 static void gen_tlbie(DisasContext *ctx)
4757 {
4758 #if defined(CONFIG_USER_ONLY)
4759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4760 #else
4761 if (unlikely(!ctx->mem_idx)) {
4762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4763 return;
4764 }
4765 if (NARROW_MODE(ctx)) {
4766 TCGv t0 = tcg_temp_new();
4767 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4768 gen_helper_tlbie(cpu_env, t0);
4769 tcg_temp_free(t0);
4770 } else {
4771 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4772 }
4773 #endif
4774 }
4775
4776 /* tlbsync */
4777 static void gen_tlbsync(DisasContext *ctx)
4778 {
4779 #if defined(CONFIG_USER_ONLY)
4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4781 #else
4782 if (unlikely(!ctx->mem_idx)) {
4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4784 return;
4785 }
4786 /* This has no effect: it should ensure that all previous
4787 * tlbie have completed
4788 */
4789 gen_stop_exception(ctx);
4790 #endif
4791 }
4792
4793 #if defined(TARGET_PPC64)
4794 /* slbia */
4795 static void gen_slbia(DisasContext *ctx)
4796 {
4797 #if defined(CONFIG_USER_ONLY)
4798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4799 #else
4800 if (unlikely(!ctx->mem_idx)) {
4801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4802 return;
4803 }
4804 gen_helper_slbia(cpu_env);
4805 #endif
4806 }
4807
4808 /* slbie */
4809 static void gen_slbie(DisasContext *ctx)
4810 {
4811 #if defined(CONFIG_USER_ONLY)
4812 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4813 #else
4814 if (unlikely(!ctx->mem_idx)) {
4815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4816 return;
4817 }
4818 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4819 #endif
4820 }
4821 #endif
4822
4823 /*** External control ***/
4824 /* Optional: */
4825
4826 /* eciwx */
4827 static void gen_eciwx(DisasContext *ctx)
4828 {
4829 TCGv t0;
4830 /* Should check EAR[E] ! */
4831 gen_set_access_type(ctx, ACCESS_EXT);
4832 t0 = tcg_temp_new();
4833 gen_addr_reg_index(ctx, t0);
4834 gen_check_align(ctx, t0, 0x03);
4835 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4836 tcg_temp_free(t0);
4837 }
4838
4839 /* ecowx */
4840 static void gen_ecowx(DisasContext *ctx)
4841 {
4842 TCGv t0;
4843 /* Should check EAR[E] ! */
4844 gen_set_access_type(ctx, ACCESS_EXT);
4845 t0 = tcg_temp_new();
4846 gen_addr_reg_index(ctx, t0);
4847 gen_check_align(ctx, t0, 0x03);
4848 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4849 tcg_temp_free(t0);
4850 }
4851
4852 /* PowerPC 601 specific instructions */
4853
4854 /* abs - abs. */
4855 static void gen_abs(DisasContext *ctx)
4856 {
4857 int l1 = gen_new_label();
4858 int l2 = gen_new_label();
4859 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4860 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4861 tcg_gen_br(l2);
4862 gen_set_label(l1);
4863 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4864 gen_set_label(l2);
4865 if (unlikely(Rc(ctx->opcode) != 0))
4866 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4867 }
4868
4869 /* abso - abso. */
4870 static void gen_abso(DisasContext *ctx)
4871 {
4872 int l1 = gen_new_label();
4873 int l2 = gen_new_label();
4874 int l3 = gen_new_label();
4875 /* Start with XER OV disabled, the most likely case */
4876 tcg_gen_movi_tl(cpu_ov, 0);
4877 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4878 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4879 tcg_gen_movi_tl(cpu_ov, 1);
4880 tcg_gen_movi_tl(cpu_so, 1);
4881 tcg_gen_br(l2);
4882 gen_set_label(l1);
4883 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4884 tcg_gen_br(l3);
4885 gen_set_label(l2);
4886 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4887 gen_set_label(l3);
4888 if (unlikely(Rc(ctx->opcode) != 0))
4889 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4890 }
4891
4892 /* clcs */
4893 static void gen_clcs(DisasContext *ctx)
4894 {
4895 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4896 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4897 tcg_temp_free_i32(t0);
4898 /* Rc=1 sets CR0 to an undefined state */
4899 }
4900
4901 /* div - div. */
4902 static void gen_div(DisasContext *ctx)
4903 {
4904 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4905 cpu_gpr[rB(ctx->opcode)]);
4906 if (unlikely(Rc(ctx->opcode) != 0))
4907 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4908 }
4909
4910 /* divo - divo. */
4911 static void gen_divo(DisasContext *ctx)
4912 {
4913 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4914 cpu_gpr[rB(ctx->opcode)]);
4915 if (unlikely(Rc(ctx->opcode) != 0))
4916 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4917 }
4918
4919 /* divs - divs. */
4920 static void gen_divs(DisasContext *ctx)
4921 {
4922 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4923 cpu_gpr[rB(ctx->opcode)]);
4924 if (unlikely(Rc(ctx->opcode) != 0))
4925 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4926 }
4927
4928 /* divso - divso. */
4929 static void gen_divso(DisasContext *ctx)
4930 {
4931 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4932 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4933 if (unlikely(Rc(ctx->opcode) != 0))
4934 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4935 }
4936
4937 /* doz - doz. */
4938 static void gen_doz(DisasContext *ctx)
4939 {
4940 int l1 = gen_new_label();
4941 int l2 = gen_new_label();
4942 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4943 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4944 tcg_gen_br(l2);
4945 gen_set_label(l1);
4946 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4947 gen_set_label(l2);
4948 if (unlikely(Rc(ctx->opcode) != 0))
4949 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4950 }
4951
4952 /* dozo - dozo. */
4953 static void gen_dozo(DisasContext *ctx)
4954 {
4955 int l1 = gen_new_label();
4956 int l2 = gen_new_label();
4957 TCGv t0 = tcg_temp_new();
4958 TCGv t1 = tcg_temp_new();
4959 TCGv t2 = tcg_temp_new();
4960 /* Start with XER OV disabled, the most likely case */
4961 tcg_gen_movi_tl(cpu_ov, 0);
4962 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4963 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4964 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4965 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4966 tcg_gen_andc_tl(t1, t1, t2);
4967 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4968 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4969 tcg_gen_movi_tl(cpu_ov, 1);
4970 tcg_gen_movi_tl(cpu_so, 1);
4971 tcg_gen_br(l2);
4972 gen_set_label(l1);
4973 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4974 gen_set_label(l2);
4975 tcg_temp_free(t0);
4976 tcg_temp_free(t1);
4977 tcg_temp_free(t2);
4978 if (unlikely(Rc(ctx->opcode) != 0))
4979 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4980 }
4981
4982 /* dozi */
4983 static void gen_dozi(DisasContext *ctx)
4984 {
4985 target_long simm = SIMM(ctx->opcode);
4986 int l1 = gen_new_label();
4987 int l2 = gen_new_label();
4988 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4989 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4990 tcg_gen_br(l2);
4991 gen_set_label(l1);
4992 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4993 gen_set_label(l2);
4994 if (unlikely(Rc(ctx->opcode) != 0))
4995 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4996 }
4997
4998 /* lscbx - lscbx. */
4999 static void gen_lscbx(DisasContext *ctx)
5000 {
5001 TCGv t0 = tcg_temp_new();
5002 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5003 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5004 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5005
5006 gen_addr_reg_index(ctx, t0);
5007 /* NIP cannot be restored if the memory exception comes from an helper */
5008 gen_update_nip(ctx, ctx->nip - 4);
5009 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5010 tcg_temp_free_i32(t1);
5011 tcg_temp_free_i32(t2);
5012 tcg_temp_free_i32(t3);
5013 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5014 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, t0);
5017 tcg_temp_free(t0);
5018 }
5019
5020 /* maskg - maskg. */
5021 static void gen_maskg(DisasContext *ctx)
5022 {
5023 int l1 = gen_new_label();
5024 TCGv t0 = tcg_temp_new();
5025 TCGv t1 = tcg_temp_new();
5026 TCGv t2 = tcg_temp_new();
5027 TCGv t3 = tcg_temp_new();
5028 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5029 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5030 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5031 tcg_gen_addi_tl(t2, t0, 1);
5032 tcg_gen_shr_tl(t2, t3, t2);
5033 tcg_gen_shr_tl(t3, t3, t1);
5034 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5035 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5036 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5037 gen_set_label(l1);
5038 tcg_temp_free(t0);
5039 tcg_temp_free(t1);
5040 tcg_temp_free(t2);
5041 tcg_temp_free(t3);
5042 if (unlikely(Rc(ctx->opcode) != 0))
5043 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5044 }
5045
5046 /* maskir - maskir. */
5047 static void gen_maskir(DisasContext *ctx)
5048 {
5049 TCGv t0 = tcg_temp_new();
5050 TCGv t1 = tcg_temp_new();
5051 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5052 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5053 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5054 tcg_temp_free(t0);
5055 tcg_temp_free(t1);
5056 if (unlikely(Rc(ctx->opcode) != 0))
5057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5058 }
5059
5060 /* mul - mul. */
5061 static void gen_mul(DisasContext *ctx)
5062 {
5063 TCGv_i64 t0 = tcg_temp_new_i64();
5064 TCGv_i64 t1 = tcg_temp_new_i64();
5065 TCGv t2 = tcg_temp_new();
5066 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5067 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5068 tcg_gen_mul_i64(t0, t0, t1);
5069 tcg_gen_trunc_i64_tl(t2, t0);
5070 gen_store_spr(SPR_MQ, t2);
5071 tcg_gen_shri_i64(t1, t0, 32);
5072 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5073 tcg_temp_free_i64(t0);
5074 tcg_temp_free_i64(t1);
5075 tcg_temp_free(t2);
5076 if (unlikely(Rc(ctx->opcode) != 0))
5077 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5078 }
5079
5080 /* mulo - mulo. */
5081 static void gen_mulo(DisasContext *ctx)
5082 {
5083 int l1 = gen_new_label();
5084 TCGv_i64 t0 = tcg_temp_new_i64();
5085 TCGv_i64 t1 = tcg_temp_new_i64();
5086 TCGv t2 = tcg_temp_new();
5087 /* Start with XER OV disabled, the most likely case */
5088 tcg_gen_movi_tl(cpu_ov, 0);
5089 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5090 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5091 tcg_gen_mul_i64(t0, t0, t1);
5092 tcg_gen_trunc_i64_tl(t2, t0);
5093 gen_store_spr(SPR_MQ, t2);
5094 tcg_gen_shri_i64(t1, t0, 32);
5095 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5096 tcg_gen_ext32s_i64(t1, t0);
5097 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5098 tcg_gen_movi_tl(cpu_ov, 1);
5099 tcg_gen_movi_tl(cpu_so, 1);
5100 gen_set_label(l1);
5101 tcg_temp_free_i64(t0);
5102 tcg_temp_free_i64(t1);
5103 tcg_temp_free(t2);
5104 if (unlikely(Rc(ctx->opcode) != 0))
5105 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5106 }
5107
5108 /* nabs - nabs. */
5109 static void gen_nabs(DisasContext *ctx)
5110 {
5111 int l1 = gen_new_label();
5112 int l2 = gen_new_label();
5113 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5114 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5115 tcg_gen_br(l2);
5116 gen_set_label(l1);
5117 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5118 gen_set_label(l2);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5121 }
5122
5123 /* nabso - nabso. */
5124 static void gen_nabso(DisasContext *ctx)
5125 {
5126 int l1 = gen_new_label();
5127 int l2 = gen_new_label();
5128 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5129 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5130 tcg_gen_br(l2);
5131 gen_set_label(l1);
5132 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5133 gen_set_label(l2);
5134 /* nabs never overflows */
5135 tcg_gen_movi_tl(cpu_ov, 0);
5136 if (unlikely(Rc(ctx->opcode) != 0))
5137 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5138 }
5139
5140 /* rlmi - rlmi. */
5141 static void gen_rlmi(DisasContext *ctx)
5142 {
5143 uint32_t mb = MB(ctx->opcode);
5144 uint32_t me = ME(ctx->opcode);
5145 TCGv t0 = tcg_temp_new();
5146 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5147 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5148 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5149 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5150 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5151 tcg_temp_free(t0);
5152 if (unlikely(Rc(ctx->opcode) != 0))
5153 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5154 }
5155
5156 /* rrib - rrib. */
5157 static void gen_rrib(DisasContext *ctx)
5158 {
5159 TCGv t0 = tcg_temp_new();
5160 TCGv t1 = tcg_temp_new();
5161 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5162 tcg_gen_movi_tl(t1, 0x80000000);
5163 tcg_gen_shr_tl(t1, t1, t0);
5164 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5165 tcg_gen_and_tl(t0, t0, t1);
5166 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5167 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5168 tcg_temp_free(t0);
5169 tcg_temp_free(t1);
5170 if (unlikely(Rc(ctx->opcode) != 0))
5171 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5172 }
5173
5174 /* sle - sle. */
5175 static void gen_sle(DisasContext *ctx)
5176 {
5177 TCGv t0 = tcg_temp_new();
5178 TCGv t1 = tcg_temp_new();
5179 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5180 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5181 tcg_gen_subfi_tl(t1, 32, t1);
5182 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5183 tcg_gen_or_tl(t1, t0, t1);
5184 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5185 gen_store_spr(SPR_MQ, t1);
5186 tcg_temp_free(t0);
5187 tcg_temp_free(t1);
5188 if (unlikely(Rc(ctx->opcode) != 0))
5189 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5190 }
5191
5192 /* sleq - sleq. */
5193 static void gen_sleq(DisasContext *ctx)
5194 {
5195 TCGv t0 = tcg_temp_new();
5196 TCGv t1 = tcg_temp_new();
5197 TCGv t2 = tcg_temp_new();
5198 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5199 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5200 tcg_gen_shl_tl(t2, t2, t0);
5201 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5202 gen_load_spr(t1, SPR_MQ);
5203 gen_store_spr(SPR_MQ, t0);
5204 tcg_gen_and_tl(t0, t0, t2);
5205 tcg_gen_andc_tl(t1, t1, t2);
5206 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5207 tcg_temp_free(t0);
5208 tcg_temp_free(t1);
5209 tcg_temp_free(t2);
5210 if (unlikely(Rc(ctx->opcode) != 0))
5211 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5212 }
5213
5214 /* sliq - sliq. */
5215 static void gen_sliq(DisasContext *ctx)
5216 {
5217 int sh = SH(ctx->opcode);
5218 TCGv t0 = tcg_temp_new();
5219 TCGv t1 = tcg_temp_new();
5220 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5221 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5222 tcg_gen_or_tl(t1, t0, t1);
5223 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5224 gen_store_spr(SPR_MQ, t1);
5225 tcg_temp_free(t0);
5226 tcg_temp_free(t1);
5227 if (unlikely(Rc(ctx->opcode) != 0))
5228 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5229 }
5230
5231 /* slliq - slliq. */
5232 static void gen_slliq(DisasContext *ctx)
5233 {
5234 int sh = SH(ctx->opcode);
5235 TCGv t0 = tcg_temp_new();
5236 TCGv t1 = tcg_temp_new();
5237 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5238 gen_load_spr(t1, SPR_MQ);
5239 gen_store_spr(SPR_MQ, t0);
5240 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5241 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5242 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5243 tcg_temp_free(t0);
5244 tcg_temp_free(t1);
5245 if (unlikely(Rc(ctx->opcode) != 0))
5246 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5247 }
5248
5249 /* sllq - sllq. */
5250 static void gen_sllq(DisasContext *ctx)
5251 {
5252 int l1 = gen_new_label();
5253 int l2 = gen_new_label();
5254 TCGv t0 = tcg_temp_local_new();
5255 TCGv t1 = tcg_temp_local_new();
5256 TCGv t2 = tcg_temp_local_new();
5257 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5258 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5259 tcg_gen_shl_tl(t1, t1, t2);
5260 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5261 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5262 gen_load_spr(t0, SPR_MQ);
5263 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5264 tcg_gen_br(l2);
5265 gen_set_label(l1);
5266 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5267 gen_load_spr(t2, SPR_MQ);
5268 tcg_gen_andc_tl(t1, t2, t1);
5269 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5270 gen_set_label(l2);
5271 tcg_temp_free(t0);
5272 tcg_temp_free(t1);
5273 tcg_temp_free(t2);
5274 if (unlikely(Rc(ctx->opcode) != 0))
5275 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5276 }
5277
5278 /* slq - slq. */
5279 static void gen_slq(DisasContext *ctx)
5280 {
5281 int l1 = gen_new_label();
5282 TCGv t0 = tcg_temp_new();
5283 TCGv t1 = tcg_temp_new();
5284 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5285 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5286 tcg_gen_subfi_tl(t1, 32, t1);
5287 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5288 tcg_gen_or_tl(t1, t0, t1);
5289 gen_store_spr(SPR_MQ, t1);
5290 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5291 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5292 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5293 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5294 gen_set_label(l1);
5295 tcg_temp_free(t0);
5296 tcg_temp_free(t1);
5297 if (unlikely(Rc(ctx->opcode) != 0))
5298 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5299 }
5300
5301 /* sraiq - sraiq. */
5302 static void gen_sraiq(DisasContext *ctx)
5303 {
5304 int sh = SH(ctx->opcode);
5305 int l1 = gen_new_label();
5306 TCGv t0 = tcg_temp_new();
5307 TCGv t1 = tcg_temp_new();
5308 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5309 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5310 tcg_gen_or_tl(t0, t0, t1);
5311 gen_store_spr(SPR_MQ, t0);
5312 tcg_gen_movi_tl(cpu_ca, 0);
5313 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5314 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5315 tcg_gen_movi_tl(cpu_ca, 1);
5316 gen_set_label(l1);
5317 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5318 tcg_temp_free(t0);
5319 tcg_temp_free(t1);
5320 if (unlikely(Rc(ctx->opcode) != 0))
5321 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5322 }
5323
5324 /* sraq - sraq. */
5325 static void gen_sraq(DisasContext *ctx)
5326 {
5327 int l1 = gen_new_label();
5328 int l2 = gen_new_label();
5329 TCGv t0 = tcg_temp_new();
5330 TCGv t1 = tcg_temp_local_new();
5331 TCGv t2 = tcg_temp_local_new();
5332 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5333 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5334 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5335 tcg_gen_subfi_tl(t2, 32, t2);
5336 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5337 tcg_gen_or_tl(t0, t0, t2);
5338 gen_store_spr(SPR_MQ, t0);
5339 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5340 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5341 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5342 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5343 gen_set_label(l1);
5344 tcg_temp_free(t0);
5345 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5346 tcg_gen_movi_tl(cpu_ca, 0);
5347 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5348 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5349 tcg_gen_movi_tl(cpu_ca, 1);
5350 gen_set_label(l2);
5351 tcg_temp_free(t1);
5352 tcg_temp_free(t2);
5353 if (unlikely(Rc(ctx->opcode) != 0))
5354 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5355 }
5356
5357 /* sre - sre. */
5358 static void gen_sre(DisasContext *ctx)
5359 {
5360 TCGv t0 = tcg_temp_new();
5361 TCGv t1 = tcg_temp_new();
5362 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5363 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5364 tcg_gen_subfi_tl(t1, 32, t1);
5365 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5366 tcg_gen_or_tl(t1, t0, t1);
5367 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5368 gen_store_spr(SPR_MQ, t1);
5369 tcg_temp_free(t0);
5370 tcg_temp_free(t1);
5371 if (unlikely(Rc(ctx->opcode) != 0))
5372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5373 }
5374
5375 /* srea - srea. */
5376 static void gen_srea(DisasContext *ctx)
5377 {
5378 TCGv t0 = tcg_temp_new();
5379 TCGv t1 = tcg_temp_new();
5380 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5381 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5382 gen_store_spr(SPR_MQ, t0);
5383 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5384 tcg_temp_free(t0);
5385 tcg_temp_free(t1);
5386 if (unlikely(Rc(ctx->opcode) != 0))
5387 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5388 }
5389
5390 /* sreq */
5391 static void gen_sreq(DisasContext *ctx)
5392 {
5393 TCGv t0 = tcg_temp_new();
5394 TCGv t1 = tcg_temp_new();
5395 TCGv t2 = tcg_temp_new();
5396 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5397 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5398 tcg_gen_shr_tl(t1, t1, t0);
5399 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5400 gen_load_spr(t2, SPR_MQ);
5401 gen_store_spr(SPR_MQ, t0);
5402 tcg_gen_and_tl(t0, t0, t1);
5403 tcg_gen_andc_tl(t2, t2, t1);
5404 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5405 tcg_temp_free(t0);
5406 tcg_temp_free(t1);
5407 tcg_temp_free(t2);
5408 if (unlikely(Rc(ctx->opcode) != 0))
5409 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5410 }
5411
5412 /* sriq */
5413 static void gen_sriq(DisasContext *ctx)
5414 {
5415 int sh = SH(ctx->opcode);
5416 TCGv t0 = tcg_temp_new();
5417 TCGv t1 = tcg_temp_new();
5418 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5419 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5420 tcg_gen_or_tl(t1, t0, t1);
5421 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5422 gen_store_spr(SPR_MQ, t1);
5423 tcg_temp_free(t0);
5424 tcg_temp_free(t1);
5425 if (unlikely(Rc(ctx->opcode) != 0))
5426 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5427 }
5428
5429 /* srliq */
5430 static void gen_srliq(DisasContext *ctx)
5431 {
5432 int sh = SH(ctx->opcode);
5433 TCGv t0 = tcg_temp_new();
5434 TCGv t1 = tcg_temp_new();
5435 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5436 gen_load_spr(t1, SPR_MQ);
5437 gen_store_spr(SPR_MQ, t0);
5438 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5439 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5440 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5441 tcg_temp_free(t0);
5442 tcg_temp_free(t1);
5443 if (unlikely(Rc(ctx->opcode) != 0))
5444 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5445 }
5446
5447 /* srlq */
5448 static void gen_srlq(DisasContext *ctx)
5449 {
5450 int l1 = gen_new_label();
5451 int l2 = gen_new_label();
5452 TCGv t0 = tcg_temp_local_new();
5453 TCGv t1 = tcg_temp_local_new();
5454 TCGv t2 = tcg_temp_local_new();
5455 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5456 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5457 tcg_gen_shr_tl(t2, t1, t2);
5458 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5459 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5460 gen_load_spr(t0, SPR_MQ);
5461 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5462 tcg_gen_br(l2);
5463 gen_set_label(l1);
5464 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5465 tcg_gen_and_tl(t0, t0, t2);
5466 gen_load_spr(t1, SPR_MQ);
5467 tcg_gen_andc_tl(t1, t1, t2);
5468 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5469 gen_set_label(l2);
5470 tcg_temp_free(t0);
5471 tcg_temp_free(t1);
5472 tcg_temp_free(t2);
5473 if (unlikely(Rc(ctx->opcode) != 0))
5474 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5475 }
5476
5477 /* srq */
5478 static void gen_srq(DisasContext *ctx)
5479 {
5480 int l1 = gen_new_label();
5481 TCGv t0 = tcg_temp_new();
5482 TCGv t1 = tcg_temp_new();
5483 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5484 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5485 tcg_gen_subfi_tl(t1, 32, t1);
5486 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5487 tcg_gen_or_tl(t1, t0, t1);
5488 gen_store_spr(SPR_MQ, t1);
5489 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5490 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5491 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5492 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5493 gen_set_label(l1);
5494 tcg_temp_free(t0);
5495 tcg_temp_free(t1);
5496 if (unlikely(Rc(ctx->opcode) != 0))
5497 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5498 }
5499
5500 /* PowerPC 602 specific instructions */
5501
5502 /* dsa */
5503 static void gen_dsa(DisasContext *ctx)
5504 {
5505 /* XXX: TODO */
5506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5507 }
5508
5509 /* esa */
5510 static void gen_esa(DisasContext *ctx)
5511 {
5512 /* XXX: TODO */
5513 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5514 }
5515
5516 /* mfrom */
5517 static void gen_mfrom(DisasContext *ctx)
5518 {
5519 #if defined(CONFIG_USER_ONLY)
5520 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5521 #else
5522 if (unlikely(!ctx->mem_idx)) {
5523 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5524 return;
5525 }
5526 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5527 #endif
5528 }
5529
5530 /* 602 - 603 - G2 TLB management */
5531
5532 /* tlbld */
5533 static void gen_tlbld_6xx(DisasContext *ctx)
5534 {
5535 #if defined(CONFIG_USER_ONLY)
5536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5537 #else
5538 if (unlikely(!ctx->mem_idx)) {
5539 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5540 return;
5541 }
5542 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5543 #endif
5544 }
5545
5546 /* tlbli */
5547 static void gen_tlbli_6xx(DisasContext *ctx)
5548 {
5549 #if defined(CONFIG_USER_ONLY)
5550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5551 #else
5552 if (unlikely(!ctx->mem_idx)) {
5553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5554 return;
5555 }
5556 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5557 #endif
5558 }
5559
5560 /* 74xx TLB management */
5561
5562 /* tlbld */
5563 static void gen_tlbld_74xx(DisasContext *ctx)
5564 {
5565 #if defined(CONFIG_USER_ONLY)
5566 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5567 #else
5568 if (unlikely(!ctx->mem_idx)) {
5569 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5570 return;
5571 }
5572 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5573 #endif
5574 }
5575
5576 /* tlbli */
5577 static void gen_tlbli_74xx(DisasContext *ctx)
5578 {
5579 #if defined(CONFIG_USER_ONLY)
5580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5581 #else
5582 if (unlikely(!ctx->mem_idx)) {
5583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5584 return;
5585 }
5586 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5587 #endif
5588 }
5589
5590 /* POWER instructions not in PowerPC 601 */
5591
5592 /* clf */
5593 static void gen_clf(DisasContext *ctx)
5594 {
5595 /* Cache line flush: implemented as no-op */
5596 }
5597
5598 /* cli */
5599 static void gen_cli(DisasContext *ctx)
5600 {
5601 /* Cache line invalidate: privileged and treated as no-op */
5602 #if defined(CONFIG_USER_ONLY)
5603 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5604 #else
5605 if (unlikely(!ctx->mem_idx)) {
5606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5607 return;
5608 }
5609 #endif
5610 }
5611
5612 /* dclst */
5613 static void gen_dclst(DisasContext *ctx)
5614 {
5615 /* Data cache line store: treated as no-op */
5616 }
5617
5618 static void gen_mfsri(DisasContext *ctx)
5619 {
5620 #if defined(CONFIG_USER_ONLY)
5621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5622 #else
5623 int ra = rA(ctx->opcode);
5624 int rd = rD(ctx->opcode);
5625 TCGv t0;
5626 if (unlikely(!ctx->mem_idx)) {
5627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5628 return;
5629 }
5630 t0 = tcg_temp_new();
5631 gen_addr_reg_index(ctx, t0);
5632 tcg_gen_shri_tl(t0, t0, 28);
5633 tcg_gen_andi_tl(t0, t0, 0xF);
5634 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5635 tcg_temp_free(t0);
5636 if (ra != 0 && ra != rd)
5637 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5638 #endif
5639 }
5640
5641 static void gen_rac(DisasContext *ctx)
5642 {
5643 #if defined(CONFIG_USER_ONLY)
5644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5645 #else
5646 TCGv t0;
5647 if (unlikely(!ctx->mem_idx)) {
5648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5649 return;
5650 }
5651 t0 = tcg_temp_new();
5652 gen_addr_reg_index(ctx, t0);
5653 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5654 tcg_temp_free(t0);
5655 #endif
5656 }
5657
5658 static void gen_rfsvc(DisasContext *ctx)
5659 {
5660 #if defined(CONFIG_USER_ONLY)
5661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5662 #else
5663 if (unlikely(!ctx->mem_idx)) {
5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5665 return;
5666 }
5667 gen_helper_rfsvc(cpu_env);
5668 gen_sync_exception(ctx);
5669 #endif
5670 }
5671
5672 /* svc is not implemented for now */
5673
5674 /* POWER2 specific instructions */
5675 /* Quad manipulation (load/store two floats at a time) */
5676
5677 /* lfq */
5678 static void gen_lfq(DisasContext *ctx)
5679 {
5680 int rd = rD(ctx->opcode);
5681 TCGv t0;
5682 gen_set_access_type(ctx, ACCESS_FLOAT);
5683 t0 = tcg_temp_new();
5684 gen_addr_imm_index(ctx, t0, 0);
5685 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5686 gen_addr_add(ctx, t0, t0, 8);
5687 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5688 tcg_temp_free(t0);
5689 }
5690
5691 /* lfqu */
5692 static void gen_lfqu(DisasContext *ctx)
5693 {
5694 int ra = rA(ctx->opcode);
5695 int rd = rD(ctx->opcode);
5696 TCGv t0, t1;
5697 gen_set_access_type(ctx, ACCESS_FLOAT);
5698 t0 = tcg_temp_new();
5699 t1 = tcg_temp_new();
5700 gen_addr_imm_index(ctx, t0, 0);
5701 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5702 gen_addr_add(ctx, t1, t0, 8);
5703 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5704 if (ra != 0)
5705 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5706 tcg_temp_free(t0);
5707 tcg_temp_free(t1);
5708 }
5709
5710 /* lfqux */
5711 static void gen_lfqux(DisasContext *ctx)
5712 {
5713 int ra = rA(ctx->opcode);
5714 int rd = rD(ctx->opcode);
5715 gen_set_access_type(ctx, ACCESS_FLOAT);
5716 TCGv t0, t1;
5717 t0 = tcg_temp_new();
5718 gen_addr_reg_index(ctx, t0);
5719 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5720 t1 = tcg_temp_new();
5721 gen_addr_add(ctx, t1, t0, 8);
5722 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5723 tcg_temp_free(t1);
5724 if (ra != 0)
5725 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5726 tcg_temp_free(t0);
5727 }
5728
5729 /* lfqx */
5730 static void gen_lfqx(DisasContext *ctx)
5731 {
5732 int rd = rD(ctx->opcode);
5733 TCGv t0;
5734 gen_set_access_type(ctx, ACCESS_FLOAT);
5735 t0 = tcg_temp_new();
5736 gen_addr_reg_index(ctx, t0);
5737 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5738 gen_addr_add(ctx, t0, t0, 8);
5739 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5740 tcg_temp_free(t0);
5741 }
5742
5743 /* stfq */
5744 static void gen_stfq(DisasContext *ctx)
5745 {
5746 int rd = rD(ctx->opcode);
5747 TCGv t0;
5748 gen_set_access_type(ctx, ACCESS_FLOAT);
5749 t0 = tcg_temp_new();
5750 gen_addr_imm_index(ctx, t0, 0);
5751 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5752 gen_addr_add(ctx, t0, t0, 8);
5753 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5754 tcg_temp_free(t0);
5755 }
5756
5757 /* stfqu */
5758 static void gen_stfqu(DisasContext *ctx)
5759 {
5760 int ra = rA(ctx->opcode);
5761 int rd = rD(ctx->opcode);
5762 TCGv t0, t1;
5763 gen_set_access_type(ctx, ACCESS_FLOAT);
5764 t0 = tcg_temp_new();
5765 gen_addr_imm_index(ctx, t0, 0);
5766 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5767 t1 = tcg_temp_new();
5768 gen_addr_add(ctx, t1, t0, 8);
5769 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5770 tcg_temp_free(t1);
5771 if (ra != 0)
5772 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5773 tcg_temp_free(t0);
5774 }
5775
5776 /* stfqux */
5777 static void gen_stfqux(DisasContext *ctx)
5778 {
5779 int ra = rA(ctx->opcode);
5780 int rd = rD(ctx->opcode);
5781 TCGv t0, t1;
5782 gen_set_access_type(ctx, ACCESS_FLOAT);
5783 t0 = tcg_temp_new();
5784 gen_addr_reg_index(ctx, t0);
5785 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5786 t1 = tcg_temp_new();
5787 gen_addr_add(ctx, t1, t0, 8);
5788 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5789 tcg_temp_free(t1);
5790 if (ra != 0)
5791 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5792 tcg_temp_free(t0);
5793 }
5794
5795 /* stfqx */
5796 static void gen_stfqx(DisasContext *ctx)
5797 {
5798 int rd = rD(ctx->opcode);
5799 TCGv t0;
5800 gen_set_access_type(ctx, ACCESS_FLOAT);
5801 t0 = tcg_temp_new();
5802 gen_addr_reg_index(ctx, t0);
5803 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5804 gen_addr_add(ctx, t0, t0, 8);
5805 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5806 tcg_temp_free(t0);
5807 }
5808
5809 /* BookE specific instructions */
5810
5811 /* XXX: not implemented on 440 ? */
5812 static void gen_mfapidi(DisasContext *ctx)
5813 {
5814 /* XXX: TODO */
5815 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5816 }
5817
5818 /* XXX: not implemented on 440 ? */
5819 static void gen_tlbiva(DisasContext *ctx)
5820 {
5821 #if defined(CONFIG_USER_ONLY)
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 #else
5824 TCGv t0;
5825 if (unlikely(!ctx->mem_idx)) {
5826 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5827 return;
5828 }
5829 t0 = tcg_temp_new();
5830 gen_addr_reg_index(ctx, t0);
5831 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5832 tcg_temp_free(t0);
5833 #endif
5834 }
5835
5836 /* All 405 MAC instructions are translated here */
5837 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5838 int ra, int rb, int rt, int Rc)
5839 {
5840 TCGv t0, t1;
5841
5842 t0 = tcg_temp_local_new();
5843 t1 = tcg_temp_local_new();
5844
5845 switch (opc3 & 0x0D) {
5846 case 0x05:
5847 /* macchw - macchw. - macchwo - macchwo. */
5848 /* macchws - macchws. - macchwso - macchwso. */
5849 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5850 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5851 /* mulchw - mulchw. */
5852 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5853 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5854 tcg_gen_ext16s_tl(t1, t1);
5855 break;
5856 case 0x04:
5857 /* macchwu - macchwu. - macchwuo - macchwuo. */
5858 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5859 /* mulchwu - mulchwu. */
5860 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5861 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5862 tcg_gen_ext16u_tl(t1, t1);
5863 break;
5864 case 0x01:
5865 /* machhw - machhw. - machhwo - machhwo. */
5866 /* machhws - machhws. - machhwso - machhwso. */
5867 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5868 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5869 /* mulhhw - mulhhw. */
5870 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5871 tcg_gen_ext16s_tl(t0, t0);
5872 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5873 tcg_gen_ext16s_tl(t1, t1);
5874 break;
5875 case 0x00:
5876 /* machhwu - machhwu. - machhwuo - machhwuo. */
5877 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5878 /* mulhhwu - mulhhwu. */
5879 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5880 tcg_gen_ext16u_tl(t0, t0);
5881 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5882 tcg_gen_ext16u_tl(t1, t1);
5883 break;
5884 case 0x0D:
5885 /* maclhw - maclhw. - maclhwo - maclhwo. */
5886 /* maclhws - maclhws. - maclhwso - maclhwso. */
5887 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5888 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5889 /* mullhw - mullhw. */
5890 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5891 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5892 break;
5893 case 0x0C:
5894 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5895 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5896 /* mullhwu - mullhwu. */
5897 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5898 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5899 break;
5900 }
5901 if (opc2 & 0x04) {
5902 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5903 tcg_gen_mul_tl(t1, t0, t1);
5904 if (opc2 & 0x02) {
5905 /* nmultiply-and-accumulate (0x0E) */
5906 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5907 } else {
5908 /* multiply-and-accumulate (0x0C) */
5909 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5910 }
5911
5912 if (opc3 & 0x12) {
5913 /* Check overflow and/or saturate */
5914 int l1 = gen_new_label();
5915
5916 if (opc3 & 0x10) {
5917 /* Start with XER OV disabled, the most likely case */
5918 tcg_gen_movi_tl(cpu_ov, 0);
5919 }
5920 if (opc3 & 0x01) {
5921 /* Signed */
5922 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5923 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5924 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5925 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5926 if (opc3 & 0x02) {
5927 /* Saturate */
5928 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5929 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5930 }
5931 } else {
5932 /* Unsigned */
5933 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5934 if (opc3 & 0x02) {
5935 /* Saturate */
5936 tcg_gen_movi_tl(t0, UINT32_MAX);
5937 }
5938 }
5939 if (opc3 & 0x10) {
5940 /* Check overflow */
5941 tcg_gen_movi_tl(cpu_ov, 1);
5942 tcg_gen_movi_tl(cpu_so, 1);
5943 }
5944 gen_set_label(l1);
5945 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5946 }
5947 } else {
5948 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5949 }
5950 tcg_temp_free(t0);
5951 tcg_temp_free(t1);
5952 if (unlikely(Rc) != 0) {
5953 /* Update Rc0 */
5954 gen_set_Rc0(ctx, cpu_gpr[rt]);
5955 }
5956 }
5957
5958 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5959 static void glue(gen_, name)(DisasContext *ctx) \
5960 { \
5961 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5962 rD(ctx->opcode), Rc(ctx->opcode)); \
5963 }
5964
5965 /* macchw - macchw. */
5966 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5967 /* macchwo - macchwo. */
5968 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5969 /* macchws - macchws. */
5970 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5971 /* macchwso - macchwso. */
5972 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5973 /* macchwsu - macchwsu. */
5974 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5975 /* macchwsuo - macchwsuo. */
5976 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5977 /* macchwu - macchwu. */
5978 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5979 /* macchwuo - macchwuo. */
5980 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5981 /* machhw - machhw. */
5982 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5983 /* machhwo - machhwo. */
5984 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5985 /* machhws - machhws. */
5986 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5987 /* machhwso - machhwso. */
5988 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5989 /* machhwsu - machhwsu. */
5990 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5991 /* machhwsuo - machhwsuo. */
5992 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5993 /* machhwu - machhwu. */
5994 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5995 /* machhwuo - machhwuo. */
5996 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5997 /* maclhw - maclhw. */
5998 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5999 /* maclhwo - maclhwo. */
6000 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6001 /* maclhws - maclhws. */
6002 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6003 /* maclhwso - maclhwso. */
6004 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6005 /* maclhwu - maclhwu. */
6006 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6007 /* maclhwuo - maclhwuo. */
6008 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6009 /* maclhwsu - maclhwsu. */
6010 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6011 /* maclhwsuo - maclhwsuo. */
6012 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6013 /* nmacchw - nmacchw. */
6014 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6015 /* nmacchwo - nmacchwo. */
6016 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6017 /* nmacchws - nmacchws. */
6018 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6019 /* nmacchwso - nmacchwso. */
6020 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6021 /* nmachhw - nmachhw. */
6022 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6023 /* nmachhwo - nmachhwo. */
6024 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6025 /* nmachhws - nmachhws. */
6026 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6027 /* nmachhwso - nmachhwso. */
6028 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6029 /* nmaclhw - nmaclhw. */
6030 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6031 /* nmaclhwo - nmaclhwo. */
6032 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6033 /* nmaclhws - nmaclhws. */
6034 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6035 /* nmaclhwso - nmaclhwso. */
6036 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6037
6038 /* mulchw - mulchw. */
6039 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6040 /* mulchwu - mulchwu. */
6041 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6042 /* mulhhw - mulhhw. */
6043 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6044 /* mulhhwu - mulhhwu. */
6045 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6046 /* mullhw - mullhw. */
6047 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6048 /* mullhwu - mullhwu. */
6049 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6050
6051 /* mfdcr */
6052 static void gen_mfdcr(DisasContext *ctx)
6053 {
6054 #if defined(CONFIG_USER_ONLY)
6055 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6056 #else
6057 TCGv dcrn;
6058 if (unlikely(!ctx->mem_idx)) {
6059 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6060 return;
6061 }
6062 /* NIP cannot be restored if the memory exception comes from an helper */
6063 gen_update_nip(ctx, ctx->nip - 4);
6064 dcrn = tcg_const_tl(SPR(ctx->opcode));
6065 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6066 tcg_temp_free(dcrn);
6067 #endif
6068 }
6069
6070 /* mtdcr */
6071 static void gen_mtdcr(DisasContext *ctx)
6072 {
6073 #if defined(CONFIG_USER_ONLY)
6074 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6075 #else
6076 TCGv dcrn;
6077 if (unlikely(!ctx->mem_idx)) {
6078 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6079 return;
6080 }
6081 /* NIP cannot be restored if the memory exception comes from an helper */
6082 gen_update_nip(ctx, ctx->nip - 4);
6083 dcrn = tcg_const_tl(SPR(ctx->opcode));
6084 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6085 tcg_temp_free(dcrn);
6086 #endif
6087 }
6088
6089 /* mfdcrx */
6090 /* XXX: not implemented on 440 ? */
6091 static void gen_mfdcrx(DisasContext *ctx)
6092 {
6093 #if defined(CONFIG_USER_ONLY)
6094 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6095 #else
6096 if (unlikely(!ctx->mem_idx)) {
6097 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6098 return;
6099 }
6100 /* NIP cannot be restored if the memory exception comes from an helper */
6101 gen_update_nip(ctx, ctx->nip - 4);
6102 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6103 cpu_gpr[rA(ctx->opcode)]);
6104 /* Note: Rc update flag set leads to undefined state of Rc0 */
6105 #endif
6106 }
6107
6108 /* mtdcrx */
6109 /* XXX: not implemented on 440 ? */
6110 static void gen_mtdcrx(DisasContext *ctx)
6111 {
6112 #if defined(CONFIG_USER_ONLY)
6113 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6114 #else
6115 if (unlikely(!ctx->mem_idx)) {
6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6117 return;
6118 }
6119 /* NIP cannot be restored if the memory exception comes from an helper */
6120 gen_update_nip(ctx, ctx->nip - 4);
6121 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6122 cpu_gpr[rS(ctx->opcode)]);
6123 /* Note: Rc update flag set leads to undefined state of Rc0 */
6124 #endif
6125 }
6126
6127 /* mfdcrux (PPC 460) : user-mode access to DCR */
6128 static void gen_mfdcrux(DisasContext *ctx)
6129 {
6130 /* NIP cannot be restored if the memory exception comes from an helper */
6131 gen_update_nip(ctx, ctx->nip - 4);
6132 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6133 cpu_gpr[rA(ctx->opcode)]);
6134 /* Note: Rc update flag set leads to undefined state of Rc0 */
6135 }
6136
6137 /* mtdcrux (PPC 460) : user-mode access to DCR */
6138 static void gen_mtdcrux(DisasContext *ctx)
6139 {
6140 /* NIP cannot be restored if the memory exception comes from an helper */
6141 gen_update_nip(ctx, ctx->nip - 4);
6142 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6143 cpu_gpr[rS(ctx->opcode)]);
6144 /* Note: Rc update flag set leads to undefined state of Rc0 */
6145 }
6146
6147 /* dccci */
6148 static void gen_dccci(DisasContext *ctx)
6149 {
6150 #if defined(CONFIG_USER_ONLY)
6151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6152 #else
6153 if (unlikely(!ctx->mem_idx)) {
6154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6155 return;
6156 }
6157 /* interpreted as no-op */
6158 #endif
6159 }
6160
6161 /* dcread */
6162 static void gen_dcread(DisasContext *ctx)
6163 {
6164 #if defined(CONFIG_USER_ONLY)
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6166 #else
6167 TCGv EA, val;
6168 if (unlikely(!ctx->mem_idx)) {
6169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6170 return;
6171 }
6172 gen_set_access_type(ctx, ACCESS_CACHE);
6173 EA = tcg_temp_new();
6174 gen_addr_reg_index(ctx, EA);
6175 val = tcg_temp_new();
6176 gen_qemu_ld32u(ctx, val, EA);
6177 tcg_temp_free(val);
6178 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6179 tcg_temp_free(EA);
6180 #endif
6181 }
6182
6183 /* icbt */
6184 static void gen_icbt_40x(DisasContext *ctx)
6185 {
6186 /* interpreted as no-op */
6187 /* XXX: specification say this is treated as a load by the MMU
6188 * but does not generate any exception
6189 */
6190 }
6191
6192 /* iccci */
6193 static void gen_iccci(DisasContext *ctx)
6194 {
6195 #if defined(CONFIG_USER_ONLY)
6196 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6197 #else
6198 if (unlikely(!ctx->mem_idx)) {
6199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6200 return;
6201 }
6202 /* interpreted as no-op */
6203 #endif
6204 }
6205
6206 /* icread */
6207 static void gen_icread(DisasContext *ctx)
6208 {
6209 #if defined(CONFIG_USER_ONLY)
6210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6211 #else
6212 if (unlikely(!ctx->mem_idx)) {
6213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6214 return;
6215 }
6216 /* interpreted as no-op */
6217 #endif
6218 }
6219
6220 /* rfci (mem_idx only) */
6221 static void gen_rfci_40x(DisasContext *ctx)
6222 {
6223 #if defined(CONFIG_USER_ONLY)
6224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6225 #else
6226 if (unlikely(!ctx->mem_idx)) {
6227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6228 return;
6229 }
6230 /* Restore CPU state */
6231 gen_helper_40x_rfci(cpu_env);
6232 gen_sync_exception(ctx);
6233 #endif
6234 }
6235
6236 static void gen_rfci(DisasContext *ctx)
6237 {
6238 #if defined(CONFIG_USER_ONLY)
6239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6240 #else
6241 if (unlikely(!ctx->mem_idx)) {
6242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6243 return;
6244 }
6245 /* Restore CPU state */
6246 gen_helper_rfci(cpu_env);
6247 gen_sync_exception(ctx);
6248 #endif
6249 }
6250
6251 /* BookE specific */
6252
6253 /* XXX: not implemented on 440 ? */
6254 static void gen_rfdi(DisasContext *ctx)
6255 {
6256 #if defined(CONFIG_USER_ONLY)
6257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6258 #else
6259 if (unlikely(!ctx->mem_idx)) {
6260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6261 return;
6262 }
6263 /* Restore CPU state */
6264 gen_helper_rfdi(cpu_env);
6265 gen_sync_exception(ctx);
6266 #endif
6267 }
6268
6269 /* XXX: not implemented on 440 ? */
6270 static void gen_rfmci(DisasContext *ctx)
6271 {
6272 #if defined(CONFIG_USER_ONLY)
6273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6274 #else
6275 if (unlikely(!ctx->mem_idx)) {
6276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6277 return;
6278 }
6279 /* Restore CPU state */
6280 gen_helper_rfmci(cpu_env);
6281 gen_sync_exception(ctx);
6282 #endif
6283 }
6284
6285 /* TLB management - PowerPC 405 implementation */
6286
6287 /* tlbre */
6288 static void gen_tlbre_40x(DisasContext *ctx)
6289 {
6290 #if defined(CONFIG_USER_ONLY)
6291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6292 #else
6293 if (unlikely(!ctx->mem_idx)) {
6294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6295 return;
6296 }
6297 switch (rB(ctx->opcode)) {
6298 case 0:
6299 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6300 cpu_gpr[rA(ctx->opcode)]);
6301 break;
6302 case 1:
6303 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6304 cpu_gpr[rA(ctx->opcode)]);
6305 break;
6306 default:
6307 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6308 break;
6309 }
6310 #endif
6311 }
6312
6313 /* tlbsx - tlbsx. */
6314 static void gen_tlbsx_40x(DisasContext *ctx)
6315 {
6316 #if defined(CONFIG_USER_ONLY)
6317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6318 #else
6319 TCGv t0;
6320 if (unlikely(!ctx->mem_idx)) {
6321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6322 return;
6323 }
6324 t0 = tcg_temp_new();
6325 gen_addr_reg_index(ctx, t0);
6326 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6327 tcg_temp_free(t0);
6328 if (Rc(ctx->opcode)) {
6329 int l1 = gen_new_label();
6330 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6331 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6332 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6333 gen_set_label(l1);
6334 }
6335 #endif
6336 }
6337
6338 /* tlbwe */
6339 static void gen_tlbwe_40x(DisasContext *ctx)
6340 {
6341 #if defined(CONFIG_USER_ONLY)
6342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6343 #else
6344 if (unlikely(!ctx->mem_idx)) {
6345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6346 return;
6347 }
6348 switch (rB(ctx->opcode)) {
6349 case 0:
6350 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6351 cpu_gpr[rS(ctx->opcode)]);
6352 break;
6353 case 1:
6354 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6355 cpu_gpr[rS(ctx->opcode)]);
6356 break;
6357 default:
6358 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6359 break;
6360 }
6361 #endif
6362 }
6363
6364 /* TLB management - PowerPC 440 implementation */
6365
6366 /* tlbre */
6367 static void gen_tlbre_440(DisasContext *ctx)
6368 {
6369 #if defined(CONFIG_USER_ONLY)
6370 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6371 #else
6372 if (unlikely(!ctx->mem_idx)) {
6373 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6374 return;
6375 }
6376 switch (rB(ctx->opcode)) {
6377 case 0:
6378 case 1:
6379 case 2:
6380 {
6381 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6382 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6383 t0, cpu_gpr[rA(ctx->opcode)]);
6384 tcg_temp_free_i32(t0);
6385 }
6386 break;
6387 default:
6388 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6389 break;
6390 }
6391 #endif
6392 }
6393
6394 /* tlbsx - tlbsx. */
6395 static void gen_tlbsx_440(DisasContext *ctx)
6396 {
6397 #if defined(CONFIG_USER_ONLY)
6398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6399 #else
6400 TCGv t0;
6401 if (unlikely(!ctx->mem_idx)) {
6402 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6403 return;
6404 }
6405 t0 = tcg_temp_new();
6406 gen_addr_reg_index(ctx, t0);
6407 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6408 tcg_temp_free(t0);
6409 if (Rc(ctx->opcode)) {
6410 int l1 = gen_new_label();
6411 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6412 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6413 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6414 gen_set_label(l1);
6415 }
6416 #endif
6417 }
6418
6419 /* tlbwe */
6420 static void gen_tlbwe_440(DisasContext *ctx)
6421 {
6422 #if defined(CONFIG_USER_ONLY)
6423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6424 #else
6425 if (unlikely(!ctx->mem_idx)) {
6426 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6427 return;
6428 }
6429 switch (rB(ctx->opcode)) {
6430 case 0:
6431 case 1:
6432 case 2:
6433 {
6434 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6435 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6436 cpu_gpr[rS(ctx->opcode)]);
6437 tcg_temp_free_i32(t0);
6438 }
6439 break;
6440 default:
6441 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6442 break;
6443 }
6444 #endif
6445 }
6446
6447 /* TLB management - PowerPC BookE 2.06 implementation */
6448
6449 /* tlbre */
6450 static void gen_tlbre_booke206(DisasContext *ctx)
6451 {
6452 #if defined(CONFIG_USER_ONLY)
6453 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6454 #else
6455 if (unlikely(!ctx->mem_idx)) {
6456 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6457 return;
6458 }
6459
6460 gen_helper_booke206_tlbre(cpu_env);
6461 #endif
6462 }
6463
6464 /* tlbsx - tlbsx. */
6465 static void gen_tlbsx_booke206(DisasContext *ctx)
6466 {
6467 #if defined(CONFIG_USER_ONLY)
6468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6469 #else
6470 TCGv t0;
6471 if (unlikely(!ctx->mem_idx)) {
6472 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6473 return;
6474 }
6475
6476 if (rA(ctx->opcode)) {
6477 t0 = tcg_temp_new();
6478 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6479 } else {
6480 t0 = tcg_const_tl(0);
6481 }
6482
6483 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6484 gen_helper_booke206_tlbsx(cpu_env, t0);
6485 tcg_temp_free(t0);
6486 #endif
6487 }
6488
6489 /* tlbwe */
6490 static void gen_tlbwe_booke206(DisasContext *ctx)
6491 {
6492 #if defined(CONFIG_USER_ONLY)
6493 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6494 #else
6495 if (unlikely(!ctx->mem_idx)) {
6496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6497 return;
6498 }
6499 gen_update_nip(ctx, ctx->nip - 4);
6500 gen_helper_booke206_tlbwe(cpu_env);
6501 #endif
6502 }
6503
6504 static void gen_tlbivax_booke206(DisasContext *ctx)
6505 {
6506 #if defined(CONFIG_USER_ONLY)
6507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6508 #else
6509 TCGv t0;
6510 if (unlikely(!ctx->mem_idx)) {
6511 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6512 return;
6513 }
6514
6515 t0 = tcg_temp_new();
6516 gen_addr_reg_index(ctx, t0);
6517
6518 gen_helper_booke206_tlbivax(cpu_env, t0);
6519 tcg_temp_free(t0);
6520 #endif
6521 }
6522
6523 static void gen_tlbilx_booke206(DisasContext *ctx)
6524 {
6525 #if defined(CONFIG_USER_ONLY)
6526 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6527 #else
6528 TCGv t0;
6529 if (unlikely(!ctx->mem_idx)) {
6530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6531 return;
6532 }
6533
6534 t0 = tcg_temp_new();
6535 gen_addr_reg_index(ctx, t0);
6536
6537 switch((ctx->opcode >> 21) & 0x3) {
6538 case 0:
6539 gen_helper_booke206_tlbilx0(cpu_env, t0);
6540 break;
6541 case 1:
6542 gen_helper_booke206_tlbilx1(cpu_env, t0);
6543 break;
6544 case 3:
6545 gen_helper_booke206_tlbilx3(cpu_env, t0);
6546 break;
6547 default:
6548 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6549 break;
6550 }
6551
6552 tcg_temp_free(t0);
6553 #endif
6554 }
6555
6556
6557 /* wrtee */
6558 static void gen_wrtee(DisasContext *ctx)
6559 {
6560 #if defined(CONFIG_USER_ONLY)
6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562 #else
6563 TCGv t0;
6564 if (unlikely(!ctx->mem_idx)) {
6565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6566 return;
6567 }
6568 t0 = tcg_temp_new();
6569 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6570 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6571 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6572 tcg_temp_free(t0);
6573 /* Stop translation to have a chance to raise an exception
6574 * if we just set msr_ee to 1
6575 */
6576 gen_stop_exception(ctx);
6577 #endif
6578 }
6579
6580 /* wrteei */
6581 static void gen_wrteei(DisasContext *ctx)
6582 {
6583 #if defined(CONFIG_USER_ONLY)
6584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6585 #else
6586 if (unlikely(!ctx->mem_idx)) {
6587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6588 return;
6589 }
6590 if (ctx->opcode & 0x00008000) {
6591 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6592 /* Stop translation to have a chance to raise an exception */
6593 gen_stop_exception(ctx);
6594 } else {
6595 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6596 }
6597 #endif
6598 }
6599
6600 /* PowerPC 440 specific instructions */
6601
6602 /* dlmzb */
6603 static void gen_dlmzb(DisasContext *ctx)
6604 {
6605 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6606 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6607 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6608 tcg_temp_free_i32(t0);
6609 }
6610
6611 /* mbar replaces eieio on 440 */
6612 static void gen_mbar(DisasContext *ctx)
6613 {
6614 /* interpreted as no-op */
6615 }
6616
6617 /* msync replaces sync on 440 */
6618 static void gen_msync_4xx(DisasContext *ctx)
6619 {
6620 /* interpreted as no-op */
6621 }
6622
6623 /* icbt */
6624 static void gen_icbt_440(DisasContext *ctx)
6625 {
6626 /* interpreted as no-op */
6627 /* XXX: specification say this is treated as a load by the MMU
6628 * but does not generate any exception
6629 */
6630 }
6631
6632 /* Embedded.Processor Control */
6633
6634 static void gen_msgclr(DisasContext *ctx)
6635 {
6636 #if defined(CONFIG_USER_ONLY)
6637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6638 #else
6639 if (unlikely(ctx->mem_idx == 0)) {
6640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6641 return;
6642 }
6643
6644 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6645 #endif
6646 }
6647
6648 static void gen_msgsnd(DisasContext *ctx)
6649 {
6650 #if defined(CONFIG_USER_ONLY)
6651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6652 #else
6653 if (unlikely(ctx->mem_idx == 0)) {
6654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6655 return;
6656 }
6657
6658 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6659 #endif
6660 }
6661
6662 /*** Altivec vector extension ***/
6663 /* Altivec registers moves */
6664
6665 static inline TCGv_ptr gen_avr_ptr(int reg)
6666 {
6667 TCGv_ptr r = tcg_temp_new_ptr();
6668 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6669 return r;
6670 }
6671
6672 #define GEN_VR_LDX(name, opc2, opc3) \
6673 static void glue(gen_, name)(DisasContext *ctx) \
6674 { \
6675 TCGv EA; \
6676 if (unlikely(!ctx->altivec_enabled)) { \
6677 gen_exception(ctx, POWERPC_EXCP_VPU); \
6678 return; \
6679 } \
6680 gen_set_access_type(ctx, ACCESS_INT); \
6681 EA = tcg_temp_new(); \
6682 gen_addr_reg_index(ctx, EA); \
6683 tcg_gen_andi_tl(EA, EA, ~0xf); \
6684 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6685 64-bit byteswap already. */ \
6686 if (ctx->le_mode) { \
6687 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6688 tcg_gen_addi_tl(EA, EA, 8); \
6689 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6690 } else { \
6691 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6692 tcg_gen_addi_tl(EA, EA, 8); \
6693 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6694 } \
6695 tcg_temp_free(EA); \
6696 }
6697
6698 #define GEN_VR_STX(name, opc2, opc3) \
6699 static void gen_st##name(DisasContext *ctx) \
6700 { \
6701 TCGv EA; \
6702 if (unlikely(!ctx->altivec_enabled)) { \
6703 gen_exception(ctx, POWERPC_EXCP_VPU); \
6704 return; \
6705 } \
6706 gen_set_access_type(ctx, ACCESS_INT); \
6707 EA = tcg_temp_new(); \
6708 gen_addr_reg_index(ctx, EA); \
6709 tcg_gen_andi_tl(EA, EA, ~0xf); \
6710 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6711 64-bit byteswap already. */ \
6712 if (ctx->le_mode) { \
6713 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6714 tcg_gen_addi_tl(EA, EA, 8); \
6715 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6716 } else { \
6717 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6718 tcg_gen_addi_tl(EA, EA, 8); \
6719 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6720 } \
6721 tcg_temp_free(EA); \
6722 }
6723
6724 #define GEN_VR_LVE(name, opc2, opc3) \
6725 static void gen_lve##name(DisasContext *ctx) \
6726 { \
6727 TCGv EA; \
6728 TCGv_ptr rs; \
6729 if (unlikely(!ctx->altivec_enabled)) { \
6730 gen_exception(ctx, POWERPC_EXCP_VPU); \
6731 return; \
6732 } \
6733 gen_set_access_type(ctx, ACCESS_INT); \
6734 EA = tcg_temp_new(); \
6735 gen_addr_reg_index(ctx, EA); \
6736 rs = gen_avr_ptr(rS(ctx->opcode)); \
6737 gen_helper_lve##name(cpu_env, rs, EA); \
6738 tcg_temp_free(EA); \
6739 tcg_temp_free_ptr(rs); \
6740 }
6741
6742 #define GEN_VR_STVE(name, opc2, opc3) \
6743 static void gen_stve##name(DisasContext *ctx) \
6744 { \
6745 TCGv EA; \
6746 TCGv_ptr rs; \
6747 if (unlikely(!ctx->altivec_enabled)) { \
6748 gen_exception(ctx, POWERPC_EXCP_VPU); \
6749 return; \
6750 } \
6751 gen_set_access_type(ctx, ACCESS_INT); \
6752 EA = tcg_temp_new(); \
6753 gen_addr_reg_index(ctx, EA); \
6754 rs = gen_avr_ptr(rS(ctx->opcode)); \
6755 gen_helper_stve##name(cpu_env, rs, EA); \
6756 tcg_temp_free(EA); \
6757 tcg_temp_free_ptr(rs); \
6758 }
6759
6760 GEN_VR_LDX(lvx, 0x07, 0x03);
6761 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6762 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6763
6764 GEN_VR_LVE(bx, 0x07, 0x00);
6765 GEN_VR_LVE(hx, 0x07, 0x01);
6766 GEN_VR_LVE(wx, 0x07, 0x02);
6767
6768 GEN_VR_STX(svx, 0x07, 0x07);
6769 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6770 GEN_VR_STX(svxl, 0x07, 0x0F);
6771
6772 GEN_VR_STVE(bx, 0x07, 0x04);
6773 GEN_VR_STVE(hx, 0x07, 0x05);
6774 GEN_VR_STVE(wx, 0x07, 0x06);
6775
6776 static void gen_lvsl(DisasContext *ctx)
6777 {
6778 TCGv_ptr rd;
6779 TCGv EA;
6780 if (unlikely(!ctx->altivec_enabled)) {
6781 gen_exception(ctx, POWERPC_EXCP_VPU);
6782 return;
6783 }
6784 EA = tcg_temp_new();
6785 gen_addr_reg_index(ctx, EA);
6786 rd = gen_avr_ptr(rD(ctx->opcode));
6787 gen_helper_lvsl(rd, EA);
6788 tcg_temp_free(EA);
6789 tcg_temp_free_ptr(rd);
6790 }
6791
6792 static void gen_lvsr(DisasContext *ctx)
6793 {
6794 TCGv_ptr rd;
6795 TCGv EA;
6796 if (unlikely(!ctx->altivec_enabled)) {
6797 gen_exception(ctx, POWERPC_EXCP_VPU);
6798 return;
6799 }
6800 EA = tcg_temp_new();
6801 gen_addr_reg_index(ctx, EA);
6802 rd = gen_avr_ptr(rD(ctx->opcode));
6803 gen_helper_lvsr(rd, EA);
6804 tcg_temp_free(EA);
6805 tcg_temp_free_ptr(rd);
6806 }
6807
6808 static void gen_mfvscr(DisasContext *ctx)
6809 {
6810 TCGv_i32 t;
6811 if (unlikely(!ctx->altivec_enabled)) {
6812 gen_exception(ctx, POWERPC_EXCP_VPU);
6813 return;
6814 }
6815 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6816 t = tcg_temp_new_i32();
6817 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6818 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6819 tcg_temp_free_i32(t);
6820 }
6821
6822 static void gen_mtvscr(DisasContext *ctx)
6823 {
6824 TCGv_ptr p;
6825 if (unlikely(!ctx->altivec_enabled)) {
6826 gen_exception(ctx, POWERPC_EXCP_VPU);
6827 return;
6828 }
6829 p = gen_avr_ptr(rD(ctx->opcode));
6830 gen_helper_mtvscr(cpu_env, p);
6831 tcg_temp_free_ptr(p);
6832 }
6833
6834 /* Logical operations */
6835 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6836 static void glue(gen_, name)(DisasContext *ctx) \
6837 { \
6838 if (unlikely(!ctx->altivec_enabled)) { \
6839 gen_exception(ctx, POWERPC_EXCP_VPU); \
6840 return; \
6841 } \
6842 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6843 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6844 }
6845
6846 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6847 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6848 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6849 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6850 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6851 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6852 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6853 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6854
6855 #define GEN_VXFORM(name, opc2, opc3) \
6856 static void glue(gen_, name)(DisasContext *ctx) \
6857 { \
6858 TCGv_ptr ra, rb, rd; \
6859 if (unlikely(!ctx->altivec_enabled)) { \
6860 gen_exception(ctx, POWERPC_EXCP_VPU); \
6861 return; \
6862 } \
6863 ra = gen_avr_ptr(rA(ctx->opcode)); \
6864 rb = gen_avr_ptr(rB(ctx->opcode)); \
6865 rd = gen_avr_ptr(rD(ctx->opcode)); \
6866 gen_helper_##name (rd, ra, rb); \
6867 tcg_temp_free_ptr(ra); \
6868 tcg_temp_free_ptr(rb); \
6869 tcg_temp_free_ptr(rd); \
6870 }
6871
6872 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6873 static void glue(gen_, name)(DisasContext *ctx) \
6874 { \
6875 TCGv_ptr ra, rb, rd; \
6876 if (unlikely(!ctx->altivec_enabled)) { \
6877 gen_exception(ctx, POWERPC_EXCP_VPU); \
6878 return; \
6879 } \
6880 ra = gen_avr_ptr(rA(ctx->opcode)); \
6881 rb = gen_avr_ptr(rB(ctx->opcode)); \
6882 rd = gen_avr_ptr(rD(ctx->opcode)); \
6883 gen_helper_##name(cpu_env, rd, ra, rb); \
6884 tcg_temp_free_ptr(ra); \
6885 tcg_temp_free_ptr(rb); \
6886 tcg_temp_free_ptr(rd); \
6887 }
6888
6889 #define GEN_VXFORM3(name, opc2, opc3) \
6890 static void glue(gen_, name)(DisasContext *ctx) \
6891 { \
6892 TCGv_ptr ra, rb, rc, rd; \
6893 if (unlikely(!ctx->altivec_enabled)) { \
6894 gen_exception(ctx, POWERPC_EXCP_VPU); \
6895 return; \
6896 } \
6897 ra = gen_avr_ptr(rA(ctx->opcode)); \
6898 rb = gen_avr_ptr(rB(ctx->opcode)); \
6899 rc = gen_avr_ptr(rC(ctx->opcode)); \
6900 rd = gen_avr_ptr(rD(ctx->opcode)); \
6901 gen_helper_##name(rd, ra, rb, rc); \
6902 tcg_temp_free_ptr(ra); \
6903 tcg_temp_free_ptr(rb); \
6904 tcg_temp_free_ptr(rc); \
6905 tcg_temp_free_ptr(rd); \
6906 }
6907
6908 /*
6909 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6910 * an opcode bit. In general, these pairs come from different
6911 * versions of the ISA, so we must also support a pair of flags for
6912 * each instruction.
6913 */
6914 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6915 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6916 { \
6917 if ((Rc(ctx->opcode) == 0) && \
6918 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6919 gen_##name0(ctx); \
6920 } else if ((Rc(ctx->opcode) == 1) && \
6921 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6922 gen_##name1(ctx); \
6923 } else { \
6924 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6925 } \
6926 }
6927
6928 GEN_VXFORM(vaddubm, 0, 0);
6929 GEN_VXFORM(vadduhm, 0, 1);
6930 GEN_VXFORM(vadduwm, 0, 2);
6931 GEN_VXFORM(vaddudm, 0, 3);
6932 GEN_VXFORM(vsububm, 0, 16);
6933 GEN_VXFORM(vsubuhm, 0, 17);
6934 GEN_VXFORM(vsubuwm, 0, 18);
6935 GEN_VXFORM(vsubudm, 0, 19);
6936 GEN_VXFORM(vmaxub, 1, 0);
6937 GEN_VXFORM(vmaxuh, 1, 1);
6938 GEN_VXFORM(vmaxuw, 1, 2);
6939 GEN_VXFORM(vmaxud, 1, 3);
6940 GEN_VXFORM(vmaxsb, 1, 4);
6941 GEN_VXFORM(vmaxsh, 1, 5);
6942 GEN_VXFORM(vmaxsw, 1, 6);
6943 GEN_VXFORM(vmaxsd, 1, 7);
6944 GEN_VXFORM(vminub, 1, 8);
6945 GEN_VXFORM(vminuh, 1, 9);
6946 GEN_VXFORM(vminuw, 1, 10);
6947 GEN_VXFORM(vminud, 1, 11);
6948 GEN_VXFORM(vminsb, 1, 12);
6949 GEN_VXFORM(vminsh, 1, 13);
6950 GEN_VXFORM(vminsw, 1, 14);
6951 GEN_VXFORM(vminsd, 1, 15);
6952 GEN_VXFORM(vavgub, 1, 16);
6953 GEN_VXFORM(vavguh, 1, 17);
6954 GEN_VXFORM(vavguw, 1, 18);
6955 GEN_VXFORM(vavgsb, 1, 20);
6956 GEN_VXFORM(vavgsh, 1, 21);
6957 GEN_VXFORM(vavgsw, 1, 22);
6958 GEN_VXFORM(vmrghb, 6, 0);
6959 GEN_VXFORM(vmrghh, 6, 1);
6960 GEN_VXFORM(vmrghw, 6, 2);
6961 GEN_VXFORM(vmrglb, 6, 4);
6962 GEN_VXFORM(vmrglh, 6, 5);
6963 GEN_VXFORM(vmrglw, 6, 6);
6964
6965 static void gen_vmrgew(DisasContext *ctx)
6966 {
6967 TCGv_i64 tmp;
6968 int VT, VA, VB;
6969 if (unlikely(!ctx->altivec_enabled)) {
6970 gen_exception(ctx, POWERPC_EXCP_VPU);
6971 return;
6972 }
6973 VT = rD(ctx->opcode);
6974 VA = rA(ctx->opcode);
6975 VB = rB(ctx->opcode);
6976 tmp = tcg_temp_new_i64();
6977 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
6978 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
6979 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
6980 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
6981 tcg_temp_free_i64(tmp);
6982 }
6983
6984 static void gen_vmrgow(DisasContext *ctx)
6985 {
6986 int VT, VA, VB;
6987 if (unlikely(!ctx->altivec_enabled)) {
6988 gen_exception(ctx, POWERPC_EXCP_VPU);
6989 return;
6990 }
6991 VT = rD(ctx->opcode);
6992 VA = rA(ctx->opcode);
6993 VB = rB(ctx->opcode);
6994
6995 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
6996 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
6997 }
6998
6999 GEN_VXFORM(vmuloub, 4, 0);
7000 GEN_VXFORM(vmulouh, 4, 1);
7001 GEN_VXFORM(vmulouw, 4, 2);
7002 GEN_VXFORM(vmuluwm, 4, 2);
7003 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7004 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7005 GEN_VXFORM(vmulosb, 4, 4);
7006 GEN_VXFORM(vmulosh, 4, 5);
7007 GEN_VXFORM(vmulosw, 4, 6);
7008 GEN_VXFORM(vmuleub, 4, 8);
7009 GEN_VXFORM(vmuleuh, 4, 9);
7010 GEN_VXFORM(vmuleuw, 4, 10);
7011 GEN_VXFORM(vmulesb, 4, 12);
7012 GEN_VXFORM(vmulesh, 4, 13);
7013 GEN_VXFORM(vmulesw, 4, 14);
7014 GEN_VXFORM(vslb, 2, 4);
7015 GEN_VXFORM(vslh, 2, 5);
7016 GEN_VXFORM(vslw, 2, 6);
7017 GEN_VXFORM(vsld, 2, 23);
7018 GEN_VXFORM(vsrb, 2, 8);
7019 GEN_VXFORM(vsrh, 2, 9);
7020 GEN_VXFORM(vsrw, 2, 10);
7021 GEN_VXFORM(vsrd, 2, 27);
7022 GEN_VXFORM(vsrab, 2, 12);
7023 GEN_VXFORM(vsrah, 2, 13);
7024 GEN_VXFORM(vsraw, 2, 14);
7025 GEN_VXFORM(vsrad, 2, 15);
7026 GEN_VXFORM(vslo, 6, 16);
7027 GEN_VXFORM(vsro, 6, 17);
7028 GEN_VXFORM(vaddcuw, 0, 6);
7029 GEN_VXFORM(vsubcuw, 0, 22);
7030 GEN_VXFORM_ENV(vaddubs, 0, 8);
7031 GEN_VXFORM_ENV(vadduhs, 0, 9);
7032 GEN_VXFORM_ENV(vadduws, 0, 10);
7033 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7034 GEN_VXFORM_ENV(vaddshs, 0, 13);
7035 GEN_VXFORM_ENV(vaddsws, 0, 14);
7036 GEN_VXFORM_ENV(vsububs, 0, 24);
7037 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7038 GEN_VXFORM_ENV(vsubuws, 0, 26);
7039 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7040 GEN_VXFORM_ENV(vsubshs, 0, 29);
7041 GEN_VXFORM_ENV(vsubsws, 0, 30);
7042 GEN_VXFORM(vadduqm, 0, 4);
7043 GEN_VXFORM(vaddcuq, 0, 5);
7044 GEN_VXFORM3(vaddeuqm, 30, 0);
7045 GEN_VXFORM3(vaddecuq, 30, 0);
7046 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7047 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7048 GEN_VXFORM(vsubuqm, 0, 20);
7049 GEN_VXFORM(vsubcuq, 0, 21);
7050 GEN_VXFORM3(vsubeuqm, 31, 0);
7051 GEN_VXFORM3(vsubecuq, 31, 0);
7052 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7053 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7054 GEN_VXFORM(vrlb, 2, 0);
7055 GEN_VXFORM(vrlh, 2, 1);
7056 GEN_VXFORM(vrlw, 2, 2);
7057 GEN_VXFORM(vrld, 2, 3);
7058 GEN_VXFORM(vsl, 2, 7);
7059 GEN_VXFORM(vsr, 2, 11);
7060 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7061 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7062 GEN_VXFORM_ENV(vpkudum, 7, 17);
7063 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7064 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7065 GEN_VXFORM_ENV(vpkudus, 7, 19);
7066 GEN_VXFORM_ENV(vpkshus, 7, 4);
7067 GEN_VXFORM_ENV(vpkswus, 7, 5);
7068 GEN_VXFORM_ENV(vpksdus, 7, 21);
7069 GEN_VXFORM_ENV(vpkshss, 7, 6);
7070 GEN_VXFORM_ENV(vpkswss, 7, 7);
7071 GEN_VXFORM_ENV(vpksdss, 7, 23);
7072 GEN_VXFORM(vpkpx, 7, 12);
7073 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7074 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7075 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7076 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7077 GEN_VXFORM_ENV(vsumsws, 4, 30);
7078 GEN_VXFORM_ENV(vaddfp, 5, 0);
7079 GEN_VXFORM_ENV(vsubfp, 5, 1);
7080 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7081 GEN_VXFORM_ENV(vminfp, 5, 17);
7082
7083 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7084 static void glue(gen_, name)(DisasContext *ctx) \
7085 { \
7086 TCGv_ptr ra, rb, rd; \
7087 if (unlikely(!ctx->altivec_enabled)) { \
7088 gen_exception(ctx, POWERPC_EXCP_VPU); \
7089 return; \
7090 } \
7091 ra = gen_avr_ptr(rA(ctx->opcode)); \
7092 rb = gen_avr_ptr(rB(ctx->opcode)); \
7093 rd = gen_avr_ptr(rD(ctx->opcode)); \
7094 gen_helper_##opname(cpu_env, rd, ra, rb); \
7095 tcg_temp_free_ptr(ra); \
7096 tcg_temp_free_ptr(rb); \
7097 tcg_temp_free_ptr(rd); \
7098 }
7099
7100 #define GEN_VXRFORM(name, opc2, opc3) \
7101 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7102 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7103
7104 /*
7105 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7106 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7107 * come from different versions of the ISA, so we must also support a
7108 * pair of flags for each instruction.
7109 */
7110 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7111 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7112 { \
7113 if ((Rc(ctx->opcode) == 0) && \
7114 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7115 if (Rc21(ctx->opcode) == 0) { \
7116 gen_##name0(ctx); \
7117 } else { \
7118 gen_##name0##_(ctx); \
7119 } \
7120 } else if ((Rc(ctx->opcode) == 1) && \
7121 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7122 if (Rc21(ctx->opcode) == 0) { \
7123 gen_##name1(ctx); \
7124 } else { \
7125 gen_##name1##_(ctx); \
7126 } \
7127 } else { \
7128 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7129 } \
7130 }
7131
7132 GEN_VXRFORM(vcmpequb, 3, 0)
7133 GEN_VXRFORM(vcmpequh, 3, 1)
7134 GEN_VXRFORM(vcmpequw, 3, 2)
7135 GEN_VXRFORM(vcmpequd, 3, 3)
7136 GEN_VXRFORM(vcmpgtsb, 3, 12)
7137 GEN_VXRFORM(vcmpgtsh, 3, 13)
7138 GEN_VXRFORM(vcmpgtsw, 3, 14)
7139 GEN_VXRFORM(vcmpgtsd, 3, 15)
7140 GEN_VXRFORM(vcmpgtub, 3, 8)
7141 GEN_VXRFORM(vcmpgtuh, 3, 9)
7142 GEN_VXRFORM(vcmpgtuw, 3, 10)
7143 GEN_VXRFORM(vcmpgtud, 3, 11)
7144 GEN_VXRFORM(vcmpeqfp, 3, 3)
7145 GEN_VXRFORM(vcmpgefp, 3, 7)
7146 GEN_VXRFORM(vcmpgtfp, 3, 11)
7147 GEN_VXRFORM(vcmpbfp, 3, 15)
7148
7149 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7150 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7151 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7152 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7153 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7154 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7155
7156 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7157 static void glue(gen_, name)(DisasContext *ctx) \
7158 { \
7159 TCGv_ptr rd; \
7160 TCGv_i32 simm; \
7161 if (unlikely(!ctx->altivec_enabled)) { \
7162 gen_exception(ctx, POWERPC_EXCP_VPU); \
7163 return; \
7164 } \
7165 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7166 rd = gen_avr_ptr(rD(ctx->opcode)); \
7167 gen_helper_##name (rd, simm); \
7168 tcg_temp_free_i32(simm); \
7169 tcg_temp_free_ptr(rd); \
7170 }
7171
7172 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7173 GEN_VXFORM_SIMM(vspltish, 6, 13);
7174 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7175
7176 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7177 static void glue(gen_, name)(DisasContext *ctx) \
7178 { \
7179 TCGv_ptr rb, rd; \
7180 if (unlikely(!ctx->altivec_enabled)) { \
7181 gen_exception(ctx, POWERPC_EXCP_VPU); \
7182 return; \
7183 } \
7184 rb = gen_avr_ptr(rB(ctx->opcode)); \
7185 rd = gen_avr_ptr(rD(ctx->opcode)); \
7186 gen_helper_##name (rd, rb); \
7187 tcg_temp_free_ptr(rb); \
7188 tcg_temp_free_ptr(rd); \
7189 }
7190
7191 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7192 static void glue(gen_, name)(DisasContext *ctx) \
7193 { \
7194 TCGv_ptr rb, rd; \
7195 \
7196 if (unlikely(!ctx->altivec_enabled)) { \
7197 gen_exception(ctx, POWERPC_EXCP_VPU); \
7198 return; \
7199 } \
7200 rb = gen_avr_ptr(rB(ctx->opcode)); \
7201 rd = gen_avr_ptr(rD(ctx->opcode)); \
7202 gen_helper_##name(cpu_env, rd, rb); \
7203 tcg_temp_free_ptr(rb); \
7204 tcg_temp_free_ptr(rd); \
7205 }
7206
7207 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7208 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7209 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7210 GEN_VXFORM_NOA(vupklsb, 7, 10);
7211 GEN_VXFORM_NOA(vupklsh, 7, 11);
7212 GEN_VXFORM_NOA(vupklsw, 7, 27);
7213 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7214 GEN_VXFORM_NOA(vupklpx, 7, 15);
7215 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7216 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7217 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7218 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7219 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7220 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7221 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7222 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7223
7224 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7225 static void glue(gen_, name)(DisasContext *ctx) \
7226 { \
7227 TCGv_ptr rd; \
7228 TCGv_i32 simm; \
7229 if (unlikely(!ctx->altivec_enabled)) { \
7230 gen_exception(ctx, POWERPC_EXCP_VPU); \
7231 return; \
7232 } \
7233 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7234 rd = gen_avr_ptr(rD(ctx->opcode)); \
7235 gen_helper_##name (rd, simm); \
7236 tcg_temp_free_i32(simm); \
7237 tcg_temp_free_ptr(rd); \
7238 }
7239
7240 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7241 static void glue(gen_, name)(DisasContext *ctx) \
7242 { \
7243 TCGv_ptr rb, rd; \
7244 TCGv_i32 uimm; \
7245 if (unlikely(!ctx->altivec_enabled)) { \
7246 gen_exception(ctx, POWERPC_EXCP_VPU); \
7247 return; \
7248 } \
7249 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7250 rb = gen_avr_ptr(rB(ctx->opcode)); \
7251 rd = gen_avr_ptr(rD(ctx->opcode)); \
7252 gen_helper_##name (rd, rb, uimm); \
7253 tcg_temp_free_i32(uimm); \
7254 tcg_temp_free_ptr(rb); \
7255 tcg_temp_free_ptr(rd); \
7256 }
7257
7258 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7259 static void glue(gen_, name)(DisasContext *ctx) \
7260 { \
7261 TCGv_ptr rb, rd; \
7262 TCGv_i32 uimm; \
7263 \
7264 if (unlikely(!ctx->altivec_enabled)) { \
7265 gen_exception(ctx, POWERPC_EXCP_VPU); \
7266 return; \
7267 } \
7268 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7269 rb = gen_avr_ptr(rB(ctx->opcode)); \
7270 rd = gen_avr_ptr(rD(ctx->opcode)); \
7271 gen_helper_##name(cpu_env, rd, rb, uimm); \
7272 tcg_temp_free_i32(uimm); \
7273 tcg_temp_free_ptr(rb); \
7274 tcg_temp_free_ptr(rd); \
7275 }
7276
7277 GEN_VXFORM_UIMM(vspltb, 6, 8);
7278 GEN_VXFORM_UIMM(vsplth, 6, 9);
7279 GEN_VXFORM_UIMM(vspltw, 6, 10);
7280 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7281 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7282 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7283 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7284
7285 static void gen_vsldoi(DisasContext *ctx)
7286 {
7287 TCGv_ptr ra, rb, rd;
7288 TCGv_i32 sh;
7289 if (unlikely(!ctx->altivec_enabled)) {
7290 gen_exception(ctx, POWERPC_EXCP_VPU);
7291 return;
7292 }
7293 ra = gen_avr_ptr(rA(ctx->opcode));
7294 rb = gen_avr_ptr(rB(ctx->opcode));
7295 rd = gen_avr_ptr(rD(ctx->opcode));
7296 sh = tcg_const_i32(VSH(ctx->opcode));
7297 gen_helper_vsldoi (rd, ra, rb, sh);
7298 tcg_temp_free_ptr(ra);
7299 tcg_temp_free_ptr(rb);
7300 tcg_temp_free_ptr(rd);
7301 tcg_temp_free_i32(sh);
7302 }
7303
7304 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7305 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7306 { \
7307 TCGv_ptr ra, rb, rc, rd; \
7308 if (unlikely(!ctx->altivec_enabled)) { \
7309 gen_exception(ctx, POWERPC_EXCP_VPU); \
7310 return; \
7311 } \
7312 ra = gen_avr_ptr(rA(ctx->opcode)); \
7313 rb = gen_avr_ptr(rB(ctx->opcode)); \
7314 rc = gen_avr_ptr(rC(ctx->opcode)); \
7315 rd = gen_avr_ptr(rD(ctx->opcode)); \
7316 if (Rc(ctx->opcode)) { \
7317 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7318 } else { \
7319 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7320 } \
7321 tcg_temp_free_ptr(ra); \
7322 tcg_temp_free_ptr(rb); \
7323 tcg_temp_free_ptr(rc); \
7324 tcg_temp_free_ptr(rd); \
7325 }
7326
7327 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7328
7329 static void gen_vmladduhm(DisasContext *ctx)
7330 {
7331 TCGv_ptr ra, rb, rc, rd;
7332 if (unlikely(!ctx->altivec_enabled)) {
7333 gen_exception(ctx, POWERPC_EXCP_VPU);
7334 return;
7335 }
7336 ra = gen_avr_ptr(rA(ctx->opcode));
7337 rb = gen_avr_ptr(rB(ctx->opcode));
7338 rc = gen_avr_ptr(rC(ctx->opcode));
7339 rd = gen_avr_ptr(rD(ctx->opcode));
7340 gen_helper_vmladduhm(rd, ra, rb, rc);
7341 tcg_temp_free_ptr(ra);
7342 tcg_temp_free_ptr(rb);
7343 tcg_temp_free_ptr(rc);
7344 tcg_temp_free_ptr(rd);
7345 }
7346
7347 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7348 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7349 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7350 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7351 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7352
7353 GEN_VXFORM_NOA(vclzb, 1, 28)
7354 GEN_VXFORM_NOA(vclzh, 1, 29)
7355 GEN_VXFORM_NOA(vclzw, 1, 30)
7356 GEN_VXFORM_NOA(vclzd, 1, 31)
7357 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7358 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7359 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7360 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7361 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7362 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7363 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7364 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7365 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7366 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7367 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7368 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7369 GEN_VXFORM(vbpermq, 6, 21);
7370 GEN_VXFORM_NOA(vgbbd, 6, 20);
7371 GEN_VXFORM(vpmsumb, 4, 16)
7372 GEN_VXFORM(vpmsumh, 4, 17)
7373 GEN_VXFORM(vpmsumw, 4, 18)
7374 GEN_VXFORM(vpmsumd, 4, 19)
7375
7376 #define GEN_BCD(op) \
7377 static void gen_##op(DisasContext *ctx) \
7378 { \
7379 TCGv_ptr ra, rb, rd; \
7380 TCGv_i32 ps; \
7381 \
7382 if (unlikely(!ctx->altivec_enabled)) { \
7383 gen_exception(ctx, POWERPC_EXCP_VPU); \
7384 return; \
7385 } \
7386 \
7387 ra = gen_avr_ptr(rA(ctx->opcode)); \
7388 rb = gen_avr_ptr(rB(ctx->opcode)); \
7389 rd = gen_avr_ptr(rD(ctx->opcode)); \
7390 \
7391 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7392 \
7393 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7394 \
7395 tcg_temp_free_ptr(ra); \
7396 tcg_temp_free_ptr(rb); \
7397 tcg_temp_free_ptr(rd); \
7398 tcg_temp_free_i32(ps); \
7399 }
7400
7401 GEN_BCD(bcdadd)
7402 GEN_BCD(bcdsub)
7403
7404 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7405 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7406 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7407 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7408 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7409 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7410 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7411 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7412
7413 static void gen_vsbox(DisasContext *ctx)
7414 {
7415 TCGv_ptr ra, rd;
7416 if (unlikely(!ctx->altivec_enabled)) {
7417 gen_exception(ctx, POWERPC_EXCP_VPU);
7418 return;
7419 }
7420 ra = gen_avr_ptr(rA(ctx->opcode));
7421 rd = gen_avr_ptr(rD(ctx->opcode));
7422 gen_helper_vsbox(rd, ra);
7423 tcg_temp_free_ptr(ra);
7424 tcg_temp_free_ptr(rd);
7425 }
7426
7427 GEN_VXFORM(vcipher, 4, 20)
7428 GEN_VXFORM(vcipherlast, 4, 20)
7429 GEN_VXFORM(vncipher, 4, 21)
7430 GEN_VXFORM(vncipherlast, 4, 21)
7431
7432 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7433 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7434 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7435 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7436
7437 #define VSHASIGMA(op) \
7438 static void gen_##op(DisasContext *ctx) \
7439 { \
7440 TCGv_ptr ra, rd; \
7441 TCGv_i32 st_six; \
7442 if (unlikely(!ctx->altivec_enabled)) { \
7443 gen_exception(ctx, POWERPC_EXCP_VPU); \
7444 return; \
7445 } \
7446 ra = gen_avr_ptr(rA(ctx->opcode)); \
7447 rd = gen_avr_ptr(rD(ctx->opcode)); \
7448 st_six = tcg_const_i32(rB(ctx->opcode)); \
7449 gen_helper_##op(rd, ra, st_six); \
7450 tcg_temp_free_ptr(ra); \
7451 tcg_temp_free_ptr(rd); \
7452 tcg_temp_free_i32(st_six); \
7453 }
7454
7455 VSHASIGMA(vshasigmaw)
7456 VSHASIGMA(vshasigmad)
7457
7458 GEN_VXFORM3(vpermxor, 22, 0xFF)
7459 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7460 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7461
7462 /*** VSX extension ***/
7463
7464 static inline TCGv_i64 cpu_vsrh(int n)
7465 {
7466 if (n < 32) {
7467 return cpu_fpr[n];
7468 } else {
7469 return cpu_avrh[n-32];
7470 }
7471 }
7472
7473 static inline TCGv_i64 cpu_vsrl(int n)
7474 {
7475 if (n < 32) {
7476 return cpu_vsr[n];
7477 } else {
7478 return cpu_avrl[n-32];
7479 }
7480 }
7481
7482 #define VSX_LOAD_SCALAR(name, operation) \
7483 static void gen_##name(DisasContext *ctx) \
7484 { \
7485 TCGv EA; \
7486 if (unlikely(!ctx->vsx_enabled)) { \
7487 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7488 return; \
7489 } \
7490 gen_set_access_type(ctx, ACCESS_INT); \
7491 EA = tcg_temp_new(); \
7492 gen_addr_reg_index(ctx, EA); \
7493 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7494 /* NOTE: cpu_vsrl is undefined */ \
7495 tcg_temp_free(EA); \
7496 }
7497
7498 VSX_LOAD_SCALAR(lxsdx, ld64)
7499 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7500 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7501 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7502
7503 static void gen_lxvd2x(DisasContext *ctx)
7504 {
7505 TCGv EA;
7506 if (unlikely(!ctx->vsx_enabled)) {
7507 gen_exception(ctx, POWERPC_EXCP_VSXU);
7508 return;
7509 }
7510 gen_set_access_type(ctx, ACCESS_INT);
7511 EA = tcg_temp_new();
7512 gen_addr_reg_index(ctx, EA);
7513 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7514 tcg_gen_addi_tl(EA, EA, 8);
7515 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7516 tcg_temp_free(EA);
7517 }
7518
7519 static void gen_lxvdsx(DisasContext *ctx)
7520 {
7521 TCGv EA;
7522 if (unlikely(!ctx->vsx_enabled)) {
7523 gen_exception(ctx, POWERPC_EXCP_VSXU);
7524 return;
7525 }
7526 gen_set_access_type(ctx, ACCESS_INT);
7527 EA = tcg_temp_new();
7528 gen_addr_reg_index(ctx, EA);
7529 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7530 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7531 tcg_temp_free(EA);
7532 }
7533
7534 static void gen_lxvw4x(DisasContext *ctx)
7535 {
7536 TCGv EA;
7537 TCGv_i64 tmp;
7538 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7539 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7540 if (unlikely(!ctx->vsx_enabled)) {
7541 gen_exception(ctx, POWERPC_EXCP_VSXU);
7542 return;
7543 }
7544 gen_set_access_type(ctx, ACCESS_INT);
7545 EA = tcg_temp_new();
7546 tmp = tcg_temp_new_i64();
7547
7548 gen_addr_reg_index(ctx, EA);
7549 gen_qemu_ld32u_i64(ctx, tmp, EA);
7550 tcg_gen_addi_tl(EA, EA, 4);
7551 gen_qemu_ld32u_i64(ctx, xth, EA);
7552 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7553
7554 tcg_gen_addi_tl(EA, EA, 4);
7555 gen_qemu_ld32u_i64(ctx, tmp, EA);
7556 tcg_gen_addi_tl(EA, EA, 4);
7557 gen_qemu_ld32u_i64(ctx, xtl, EA);
7558 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7559
7560 tcg_temp_free(EA);
7561 tcg_temp_free_i64(tmp);
7562 }
7563
7564 #define VSX_STORE_SCALAR(name, operation) \
7565 static void gen_##name(DisasContext *ctx) \
7566 { \
7567 TCGv EA; \
7568 if (unlikely(!ctx->vsx_enabled)) { \
7569 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7570 return; \
7571 } \
7572 gen_set_access_type(ctx, ACCESS_INT); \
7573 EA = tcg_temp_new(); \
7574 gen_addr_reg_index(ctx, EA); \
7575 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7576 tcg_temp_free(EA); \
7577 }
7578
7579 VSX_STORE_SCALAR(stxsdx, st64)
7580 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7581 VSX_STORE_SCALAR(stxsspx, st32fs)
7582
7583 static void gen_stxvd2x(DisasContext *ctx)
7584 {
7585 TCGv EA;
7586 if (unlikely(!ctx->vsx_enabled)) {
7587 gen_exception(ctx, POWERPC_EXCP_VSXU);
7588 return;
7589 }
7590 gen_set_access_type(ctx, ACCESS_INT);
7591 EA = tcg_temp_new();
7592 gen_addr_reg_index(ctx, EA);
7593 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7594 tcg_gen_addi_tl(EA, EA, 8);
7595 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7596 tcg_temp_free(EA);
7597 }
7598
7599 static void gen_stxvw4x(DisasContext *ctx)
7600 {
7601 TCGv_i64 tmp;
7602 TCGv EA;
7603 if (unlikely(!ctx->vsx_enabled)) {
7604 gen_exception(ctx, POWERPC_EXCP_VSXU);
7605 return;
7606 }
7607 gen_set_access_type(ctx, ACCESS_INT);
7608 EA = tcg_temp_new();
7609 gen_addr_reg_index(ctx, EA);
7610 tmp = tcg_temp_new_i64();
7611
7612 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7613 gen_qemu_st32_i64(ctx, tmp, EA);
7614 tcg_gen_addi_tl(EA, EA, 4);
7615 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7616
7617 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7618 tcg_gen_addi_tl(EA, EA, 4);
7619 gen_qemu_st32_i64(ctx, tmp, EA);
7620 tcg_gen_addi_tl(EA, EA, 4);
7621 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7622
7623 tcg_temp_free(EA);
7624 tcg_temp_free_i64(tmp);
7625 }
7626
7627 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7628 static void gen_##name(DisasContext *ctx) \
7629 { \
7630 if (xS(ctx->opcode) < 32) { \
7631 if (unlikely(!ctx->fpu_enabled)) { \
7632 gen_exception(ctx, POWERPC_EXCP_FPU); \
7633 return; \
7634 } \
7635 } else { \
7636 if (unlikely(!ctx->altivec_enabled)) { \
7637 gen_exception(ctx, POWERPC_EXCP_VPU); \
7638 return; \
7639 } \
7640 } \
7641 TCGv_i64 tmp = tcg_temp_new_i64(); \
7642 tcg_gen_##tcgop1(tmp, source); \
7643 tcg_gen_##tcgop2(target, tmp); \
7644 tcg_temp_free_i64(tmp); \
7645 }
7646
7647
7648 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7649 cpu_vsrh(xS(ctx->opcode)))
7650 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7651 cpu_gpr[rA(ctx->opcode)])
7652 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7653 cpu_gpr[rA(ctx->opcode)])
7654
7655 #if defined(TARGET_PPC64)
7656 #define MV_VSRD(name, target, source) \
7657 static void gen_##name(DisasContext *ctx) \
7658 { \
7659 if (xS(ctx->opcode) < 32) { \
7660 if (unlikely(!ctx->fpu_enabled)) { \
7661 gen_exception(ctx, POWERPC_EXCP_FPU); \
7662 return; \
7663 } \
7664 } else { \
7665 if (unlikely(!ctx->altivec_enabled)) { \
7666 gen_exception(ctx, POWERPC_EXCP_VPU); \
7667 return; \
7668 } \
7669 } \
7670 tcg_gen_mov_i64(target, source); \
7671 }
7672
7673 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7674 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7675
7676 #endif
7677
7678 static void gen_xxpermdi(DisasContext *ctx)
7679 {
7680 if (unlikely(!ctx->vsx_enabled)) {
7681 gen_exception(ctx, POWERPC_EXCP_VSXU);
7682 return;
7683 }
7684
7685 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7686 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7687 TCGv_i64 xh, xl;
7688
7689 xh = tcg_temp_new_i64();
7690 xl = tcg_temp_new_i64();
7691
7692 if ((DM(ctx->opcode) & 2) == 0) {
7693 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7694 } else {
7695 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7696 }
7697 if ((DM(ctx->opcode) & 1) == 0) {
7698 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7699 } else {
7700 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7701 }
7702
7703 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7704 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7705
7706 tcg_temp_free_i64(xh);
7707 tcg_temp_free_i64(xl);
7708 } else {
7709 if ((DM(ctx->opcode) & 2) == 0) {
7710 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7711 } else {
7712 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7713 }
7714 if ((DM(ctx->opcode) & 1) == 0) {
7715 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7716 } else {
7717 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7718 }
7719 }
7720 }
7721
7722 #define OP_ABS 1
7723 #define OP_NABS 2
7724 #define OP_NEG 3
7725 #define OP_CPSGN 4
7726 #define SGN_MASK_DP 0x8000000000000000ull
7727 #define SGN_MASK_SP 0x8000000080000000ull
7728
7729 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7730 static void glue(gen_, name)(DisasContext * ctx) \
7731 { \
7732 TCGv_i64 xb, sgm; \
7733 if (unlikely(!ctx->vsx_enabled)) { \
7734 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7735 return; \
7736 } \
7737 xb = tcg_temp_new_i64(); \
7738 sgm = tcg_temp_new_i64(); \
7739 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7740 tcg_gen_movi_i64(sgm, sgn_mask); \
7741 switch (op) { \
7742 case OP_ABS: { \
7743 tcg_gen_andc_i64(xb, xb, sgm); \
7744 break; \
7745 } \
7746 case OP_NABS: { \
7747 tcg_gen_or_i64(xb, xb, sgm); \
7748 break; \
7749 } \
7750 case OP_NEG: { \
7751 tcg_gen_xor_i64(xb, xb, sgm); \
7752 break; \
7753 } \
7754 case OP_CPSGN: { \
7755 TCGv_i64 xa = tcg_temp_new_i64(); \
7756 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7757 tcg_gen_and_i64(xa, xa, sgm); \
7758 tcg_gen_andc_i64(xb, xb, sgm); \
7759 tcg_gen_or_i64(xb, xb, xa); \
7760 tcg_temp_free_i64(xa); \
7761 break; \
7762 } \
7763 } \
7764 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7765 tcg_temp_free_i64(xb); \
7766 tcg_temp_free_i64(sgm); \
7767 }
7768
7769 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7770 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7771 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7772 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7773
7774 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7775 static void glue(gen_, name)(DisasContext * ctx) \
7776 { \
7777 TCGv_i64 xbh, xbl, sgm; \
7778 if (unlikely(!ctx->vsx_enabled)) { \
7779 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7780 return; \
7781 } \
7782 xbh = tcg_temp_new_i64(); \
7783 xbl = tcg_temp_new_i64(); \
7784 sgm = tcg_temp_new_i64(); \
7785 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7786 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7787 tcg_gen_movi_i64(sgm, sgn_mask); \
7788 switch (op) { \
7789 case OP_ABS: { \
7790 tcg_gen_andc_i64(xbh, xbh, sgm); \
7791 tcg_gen_andc_i64(xbl, xbl, sgm); \
7792 break; \
7793 } \
7794 case OP_NABS: { \
7795 tcg_gen_or_i64(xbh, xbh, sgm); \
7796 tcg_gen_or_i64(xbl, xbl, sgm); \
7797 break; \
7798 } \
7799 case OP_NEG: { \
7800 tcg_gen_xor_i64(xbh, xbh, sgm); \
7801 tcg_gen_xor_i64(xbl, xbl, sgm); \
7802 break; \
7803 } \
7804 case OP_CPSGN: { \
7805 TCGv_i64 xah = tcg_temp_new_i64(); \
7806 TCGv_i64 xal = tcg_temp_new_i64(); \
7807 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7808 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7809 tcg_gen_and_i64(xah, xah, sgm); \
7810 tcg_gen_and_i64(xal, xal, sgm); \
7811 tcg_gen_andc_i64(xbh, xbh, sgm); \
7812 tcg_gen_andc_i64(xbl, xbl, sgm); \
7813 tcg_gen_or_i64(xbh, xbh, xah); \
7814 tcg_gen_or_i64(xbl, xbl, xal); \
7815 tcg_temp_free_i64(xah); \
7816 tcg_temp_free_i64(xal); \
7817 break; \
7818 } \
7819 } \
7820 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7821 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7822 tcg_temp_free_i64(xbh); \
7823 tcg_temp_free_i64(xbl); \
7824 tcg_temp_free_i64(sgm); \
7825 }
7826
7827 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7828 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7829 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7830 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7831 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7832 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7833 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7834 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7835
7836 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7837 static void gen_##name(DisasContext * ctx) \
7838 { \
7839 TCGv_i32 opc; \
7840 if (unlikely(!ctx->vsx_enabled)) { \
7841 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7842 return; \
7843 } \
7844 /* NIP cannot be restored if the memory exception comes from an helper */ \
7845 gen_update_nip(ctx, ctx->nip - 4); \
7846 opc = tcg_const_i32(ctx->opcode); \
7847 gen_helper_##name(cpu_env, opc); \
7848 tcg_temp_free_i32(opc); \
7849 }
7850
7851 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7852 static void gen_##name(DisasContext * ctx) \
7853 { \
7854 if (unlikely(!ctx->vsx_enabled)) { \
7855 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7856 return; \
7857 } \
7858 /* NIP cannot be restored if the exception comes */ \
7859 /* from a helper. */ \
7860 gen_update_nip(ctx, ctx->nip - 4); \
7861 \
7862 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7863 cpu_vsrh(xB(ctx->opcode))); \
7864 }
7865
7866 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7867 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7868 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7869 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7870 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7871 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7872 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7873 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7874 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7875 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7876 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7877 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7878 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7879 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7880 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7881 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7882 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7883 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7884 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7885 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7886 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7887 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7888 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7889 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7890 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7891 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7892 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7893 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7894 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7895 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7896 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7897 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7898 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7899 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7900 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7901 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7902 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7903
7904 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7905 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7906 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7907 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7908 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7909 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7910 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7911 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7912 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7913 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7914 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7915 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7916 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7917 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7918 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7919 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7920 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7921
7922 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7923 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7924 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7925 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7926 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7927 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7928 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7929 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7930 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7931 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7932 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7933 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7934 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7935 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7936 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7937 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7938 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7939 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7940 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7958
7959 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7995
7996 #define VSX_LOGICAL(name, tcg_op) \
7997 static void glue(gen_, name)(DisasContext * ctx) \
7998 { \
7999 if (unlikely(!ctx->vsx_enabled)) { \
8000 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8001 return; \
8002 } \
8003 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8004 cpu_vsrh(xB(ctx->opcode))); \
8005 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8006 cpu_vsrl(xB(ctx->opcode))); \
8007 }
8008
8009 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8010 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8011 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8012 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8013 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8014 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8015 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8016 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8017
8018 #define VSX_XXMRG(name, high) \
8019 static void glue(gen_, name)(DisasContext * ctx) \
8020 { \
8021 TCGv_i64 a0, a1, b0, b1; \
8022 if (unlikely(!ctx->vsx_enabled)) { \
8023 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8024 return; \
8025 } \
8026 a0 = tcg_temp_new_i64(); \
8027 a1 = tcg_temp_new_i64(); \
8028 b0 = tcg_temp_new_i64(); \
8029 b1 = tcg_temp_new_i64(); \
8030 if (high) { \
8031 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8032 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8033 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8034 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8035 } else { \
8036 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8037 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8038 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8039 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8040 } \
8041 tcg_gen_shri_i64(a0, a0, 32); \
8042 tcg_gen_shri_i64(b0, b0, 32); \
8043 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8044 b0, a0, 32, 32); \
8045 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8046 b1, a1, 32, 32); \
8047 tcg_temp_free_i64(a0); \
8048 tcg_temp_free_i64(a1); \
8049 tcg_temp_free_i64(b0); \
8050 tcg_temp_free_i64(b1); \
8051 }
8052
8053 VSX_XXMRG(xxmrghw, 1)
8054 VSX_XXMRG(xxmrglw, 0)
8055
8056 static void gen_xxsel(DisasContext * ctx)
8057 {
8058 TCGv_i64 a, b, c;
8059 if (unlikely(!ctx->vsx_enabled)) {
8060 gen_exception(ctx, POWERPC_EXCP_VSXU);
8061 return;
8062 }
8063 a = tcg_temp_new_i64();
8064 b = tcg_temp_new_i64();
8065 c = tcg_temp_new_i64();
8066
8067 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8068 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8069 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8070
8071 tcg_gen_and_i64(b, b, c);
8072 tcg_gen_andc_i64(a, a, c);
8073 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8074
8075 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8076 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8077 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8078
8079 tcg_gen_and_i64(b, b, c);
8080 tcg_gen_andc_i64(a, a, c);
8081 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8082
8083 tcg_temp_free_i64(a);
8084 tcg_temp_free_i64(b);
8085 tcg_temp_free_i64(c);
8086 }
8087
8088 static void gen_xxspltw(DisasContext *ctx)
8089 {
8090 TCGv_i64 b, b2;
8091 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8092 cpu_vsrl(xB(ctx->opcode)) :
8093 cpu_vsrh(xB(ctx->opcode));
8094
8095 if (unlikely(!ctx->vsx_enabled)) {
8096 gen_exception(ctx, POWERPC_EXCP_VSXU);
8097 return;
8098 }
8099
8100 b = tcg_temp_new_i64();
8101 b2 = tcg_temp_new_i64();
8102
8103 if (UIM(ctx->opcode) & 1) {
8104 tcg_gen_ext32u_i64(b, vsr);
8105 } else {
8106 tcg_gen_shri_i64(b, vsr, 32);
8107 }
8108
8109 tcg_gen_shli_i64(b2, b, 32);
8110 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8111 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8112
8113 tcg_temp_free_i64(b);
8114 tcg_temp_free_i64(b2);
8115 }
8116
8117 static void gen_xxsldwi(DisasContext *ctx)
8118 {
8119 TCGv_i64 xth, xtl;
8120 if (unlikely(!ctx->vsx_enabled)) {
8121 gen_exception(ctx, POWERPC_EXCP_VSXU);
8122 return;
8123 }
8124 xth = tcg_temp_new_i64();
8125 xtl = tcg_temp_new_i64();
8126
8127 switch (SHW(ctx->opcode)) {
8128 case 0: {
8129 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8130 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8131 break;
8132 }
8133 case 1: {
8134 TCGv_i64 t0 = tcg_temp_new_i64();
8135 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8136 tcg_gen_shli_i64(xth, xth, 32);
8137 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8138 tcg_gen_shri_i64(t0, t0, 32);
8139 tcg_gen_or_i64(xth, xth, t0);
8140 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8141 tcg_gen_shli_i64(xtl, xtl, 32);
8142 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8143 tcg_gen_shri_i64(t0, t0, 32);
8144 tcg_gen_or_i64(xtl, xtl, t0);
8145 tcg_temp_free_i64(t0);
8146 break;
8147 }
8148 case 2: {
8149 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8150 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8151 break;
8152 }
8153 case 3: {
8154 TCGv_i64 t0 = tcg_temp_new_i64();
8155 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8156 tcg_gen_shli_i64(xth, xth, 32);
8157 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8158 tcg_gen_shri_i64(t0, t0, 32);
8159 tcg_gen_or_i64(xth, xth, t0);
8160 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8161 tcg_gen_shli_i64(xtl, xtl, 32);
8162 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8163 tcg_gen_shri_i64(t0, t0, 32);
8164 tcg_gen_or_i64(xtl, xtl, t0);
8165 tcg_temp_free_i64(t0);
8166 break;
8167 }
8168 }
8169
8170 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8171 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8172
8173 tcg_temp_free_i64(xth);
8174 tcg_temp_free_i64(xtl);
8175 }
8176
8177 /*** Decimal Floating Point ***/
8178
8179 static inline TCGv_ptr gen_fprp_ptr(int reg)
8180 {
8181 TCGv_ptr r = tcg_temp_new_ptr();
8182 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8183 return r;
8184 }
8185
8186 #if defined(TARGET_PPC64)
8187 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8188 {
8189 TCGv_i32 tmp = tcg_temp_new_i32();
8190 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
8191 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
8192 tcg_temp_free_i32(tmp);
8193 }
8194 #else
8195 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8196 {
8197 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
8198 }
8199 #endif
8200
8201 #define GEN_DFP_T_A_B_Rc(name) \
8202 static void gen_##name(DisasContext *ctx) \
8203 { \
8204 TCGv_ptr rd, ra, rb; \
8205 if (unlikely(!ctx->fpu_enabled)) { \
8206 gen_exception(ctx, POWERPC_EXCP_FPU); \
8207 return; \
8208 } \
8209 gen_update_nip(ctx, ctx->nip - 4); \
8210 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8211 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8212 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8213 gen_helper_##name(cpu_env, rd, ra, rb); \
8214 if (unlikely(Rc(ctx->opcode) != 0)) { \
8215 gen_set_cr6_from_fpscr(ctx); \
8216 } \
8217 tcg_temp_free_ptr(rd); \
8218 tcg_temp_free_ptr(ra); \
8219 tcg_temp_free_ptr(rb); \
8220 }
8221
8222 #define GEN_DFP_BF_A_B(name) \
8223 static void gen_##name(DisasContext *ctx) \
8224 { \
8225 TCGv_ptr ra, rb; \
8226 if (unlikely(!ctx->fpu_enabled)) { \
8227 gen_exception(ctx, POWERPC_EXCP_FPU); \
8228 return; \
8229 } \
8230 gen_update_nip(ctx, ctx->nip - 4); \
8231 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8232 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8233 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8234 cpu_env, ra, rb); \
8235 tcg_temp_free_ptr(ra); \
8236 tcg_temp_free_ptr(rb); \
8237 }
8238
8239 #define GEN_DFP_BF_A_DCM(name) \
8240 static void gen_##name(DisasContext *ctx) \
8241 { \
8242 TCGv_ptr ra; \
8243 TCGv_i32 dcm; \
8244 if (unlikely(!ctx->fpu_enabled)) { \
8245 gen_exception(ctx, POWERPC_EXCP_FPU); \
8246 return; \
8247 } \
8248 gen_update_nip(ctx, ctx->nip - 4); \
8249 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8250 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8251 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8252 cpu_env, ra, dcm); \
8253 tcg_temp_free_ptr(ra); \
8254 tcg_temp_free_i32(dcm); \
8255 }
8256
8257 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8258 static void gen_##name(DisasContext *ctx) \
8259 { \
8260 TCGv_ptr rt, rb; \
8261 TCGv_i32 u32_1, u32_2; \
8262 if (unlikely(!ctx->fpu_enabled)) { \
8263 gen_exception(ctx, POWERPC_EXCP_FPU); \
8264 return; \
8265 } \
8266 gen_update_nip(ctx, ctx->nip - 4); \
8267 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8268 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8269 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8270 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8271 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8272 if (unlikely(Rc(ctx->opcode) != 0)) { \
8273 gen_set_cr6_from_fpscr(ctx); \
8274 } \
8275 tcg_temp_free_ptr(rt); \
8276 tcg_temp_free_ptr(rb); \
8277 tcg_temp_free_i32(u32_1); \
8278 tcg_temp_free_i32(u32_2); \
8279 }
8280
8281 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8282 static void gen_##name(DisasContext *ctx) \
8283 { \
8284 TCGv_ptr rt, ra, rb; \
8285 TCGv_i32 i32; \
8286 if (unlikely(!ctx->fpu_enabled)) { \
8287 gen_exception(ctx, POWERPC_EXCP_FPU); \
8288 return; \
8289 } \
8290 gen_update_nip(ctx, ctx->nip - 4); \
8291 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8292 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8293 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8294 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8295 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8296 if (unlikely(Rc(ctx->opcode) != 0)) { \
8297 gen_set_cr6_from_fpscr(ctx); \
8298 } \
8299 tcg_temp_free_ptr(rt); \
8300 tcg_temp_free_ptr(rb); \
8301 tcg_temp_free_ptr(ra); \
8302 tcg_temp_free_i32(i32); \
8303 }
8304
8305 #define GEN_DFP_T_B_Rc(name) \
8306 static void gen_##name(DisasContext *ctx) \
8307 { \
8308 TCGv_ptr rt, rb; \
8309 if (unlikely(!ctx->fpu_enabled)) { \
8310 gen_exception(ctx, POWERPC_EXCP_FPU); \
8311 return; \
8312 } \
8313 gen_update_nip(ctx, ctx->nip - 4); \
8314 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8315 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8316 gen_helper_##name(cpu_env, rt, rb); \
8317 if (unlikely(Rc(ctx->opcode) != 0)) { \
8318 gen_set_cr6_from_fpscr(ctx); \
8319 } \
8320 tcg_temp_free_ptr(rt); \
8321 tcg_temp_free_ptr(rb); \
8322 }
8323
8324 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8325 static void gen_##name(DisasContext *ctx) \
8326 { \
8327 TCGv_ptr rt, rs; \
8328 TCGv_i32 i32; \
8329 if (unlikely(!ctx->fpu_enabled)) { \
8330 gen_exception(ctx, POWERPC_EXCP_FPU); \
8331 return; \
8332 } \
8333 gen_update_nip(ctx, ctx->nip - 4); \
8334 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8335 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8336 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8337 gen_helper_##name(cpu_env, rt, rs, i32); \
8338 if (unlikely(Rc(ctx->opcode) != 0)) { \
8339 gen_set_cr6_from_fpscr(ctx); \
8340 } \
8341 tcg_temp_free_ptr(rt); \
8342 tcg_temp_free_ptr(rs); \
8343 tcg_temp_free_i32(i32); \
8344 }
8345
8346 GEN_DFP_T_A_B_Rc(dadd)
8347 GEN_DFP_T_A_B_Rc(daddq)
8348 GEN_DFP_T_A_B_Rc(dsub)
8349 GEN_DFP_T_A_B_Rc(dsubq)
8350 GEN_DFP_T_A_B_Rc(dmul)
8351 GEN_DFP_T_A_B_Rc(dmulq)
8352 GEN_DFP_T_A_B_Rc(ddiv)
8353 GEN_DFP_T_A_B_Rc(ddivq)
8354 GEN_DFP_BF_A_B(dcmpu)
8355 GEN_DFP_BF_A_B(dcmpuq)
8356 GEN_DFP_BF_A_B(dcmpo)
8357 GEN_DFP_BF_A_B(dcmpoq)
8358 GEN_DFP_BF_A_DCM(dtstdc)
8359 GEN_DFP_BF_A_DCM(dtstdcq)
8360 GEN_DFP_BF_A_DCM(dtstdg)
8361 GEN_DFP_BF_A_DCM(dtstdgq)
8362 GEN_DFP_BF_A_B(dtstex)
8363 GEN_DFP_BF_A_B(dtstexq)
8364 GEN_DFP_BF_A_B(dtstsf)
8365 GEN_DFP_BF_A_B(dtstsfq)
8366 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8367 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8368 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8369 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8370 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8371 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8372 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8373 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8374 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8375 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8376 GEN_DFP_T_B_Rc(dctdp)
8377 GEN_DFP_T_B_Rc(dctqpq)
8378 GEN_DFP_T_B_Rc(drsp)
8379 GEN_DFP_T_B_Rc(drdpq)
8380 GEN_DFP_T_B_Rc(dcffix)
8381 GEN_DFP_T_B_Rc(dcffixq)
8382 GEN_DFP_T_B_Rc(dctfix)
8383 GEN_DFP_T_B_Rc(dctfixq)
8384 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8385 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8386 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8387 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8388 GEN_DFP_T_B_Rc(dxex)
8389 GEN_DFP_T_B_Rc(dxexq)
8390 GEN_DFP_T_A_B_Rc(diex)
8391 GEN_DFP_T_A_B_Rc(diexq)
8392 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8393 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8394 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8395 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8396
8397 /*** SPE extension ***/
8398 /* Register moves */
8399
8400 static inline void gen_evmra(DisasContext *ctx)
8401 {
8402
8403 if (unlikely(!ctx->spe_enabled)) {
8404 gen_exception(ctx, POWERPC_EXCP_SPEU);
8405 return;
8406 }
8407
8408 TCGv_i64 tmp = tcg_temp_new_i64();
8409
8410 /* tmp := rA_lo + rA_hi << 32 */
8411 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8412
8413 /* spe_acc := tmp */
8414 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8415 tcg_temp_free_i64(tmp);
8416
8417 /* rD := rA */
8418 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8419 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8420 }
8421
8422 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8423 {
8424 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8425 }
8426
8427 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8428 {
8429 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8430 }
8431
8432 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8433 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8434 { \
8435 if (Rc(ctx->opcode)) \
8436 gen_##name1(ctx); \
8437 else \
8438 gen_##name0(ctx); \
8439 }
8440
8441 /* Handler for undefined SPE opcodes */
8442 static inline void gen_speundef(DisasContext *ctx)
8443 {
8444 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8445 }
8446
8447 /* SPE logic */
8448 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8449 static inline void gen_##name(DisasContext *ctx) \
8450 { \
8451 if (unlikely(!ctx->spe_enabled)) { \
8452 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8453 return; \
8454 } \
8455 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8456 cpu_gpr[rB(ctx->opcode)]); \
8457 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8458 cpu_gprh[rB(ctx->opcode)]); \
8459 }
8460
8461 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8462 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8463 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8464 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8465 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8466 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8467 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8468 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8469
8470 /* SPE logic immediate */
8471 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8472 static inline void gen_##name(DisasContext *ctx) \
8473 { \
8474 TCGv_i32 t0; \
8475 if (unlikely(!ctx->spe_enabled)) { \
8476 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8477 return; \
8478 } \
8479 t0 = tcg_temp_new_i32(); \
8480 \
8481 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8482 tcg_opi(t0, t0, rB(ctx->opcode)); \
8483 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8484 \
8485 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8486 tcg_opi(t0, t0, rB(ctx->opcode)); \
8487 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8488 \
8489 tcg_temp_free_i32(t0); \
8490 }
8491 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8492 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8493 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8494 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8495
8496 /* SPE arithmetic */
8497 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8498 static inline void gen_##name(DisasContext *ctx) \
8499 { \
8500 TCGv_i32 t0; \
8501 if (unlikely(!ctx->spe_enabled)) { \
8502 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8503 return; \
8504 } \
8505 t0 = tcg_temp_new_i32(); \
8506 \
8507 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8508 tcg_op(t0, t0); \
8509 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8510 \
8511 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8512 tcg_op(t0, t0); \
8513 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8514 \
8515 tcg_temp_free_i32(t0); \
8516 }
8517
8518 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8519 {
8520 int l1 = gen_new_label();
8521 int l2 = gen_new_label();
8522
8523 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8524 tcg_gen_neg_i32(ret, arg1);
8525 tcg_gen_br(l2);
8526 gen_set_label(l1);
8527 tcg_gen_mov_i32(ret, arg1);
8528 gen_set_label(l2);
8529 }
8530 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8531 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8532 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8533 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8534 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8535 {
8536 tcg_gen_addi_i32(ret, arg1, 0x8000);
8537 tcg_gen_ext16u_i32(ret, ret);
8538 }
8539 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8540 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8541 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8542
8543 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8544 static inline void gen_##name(DisasContext *ctx) \
8545 { \
8546 TCGv_i32 t0, t1; \
8547 if (unlikely(!ctx->spe_enabled)) { \
8548 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8549 return; \
8550 } \
8551 t0 = tcg_temp_new_i32(); \
8552 t1 = tcg_temp_new_i32(); \
8553 \
8554 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8555 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8556 tcg_op(t0, t0, t1); \
8557 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8558 \
8559 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8560 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8561 tcg_op(t0, t0, t1); \
8562 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8563 \
8564 tcg_temp_free_i32(t0); \
8565 tcg_temp_free_i32(t1); \
8566 }
8567
8568 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8569 {
8570 TCGv_i32 t0;
8571 int l1, l2;
8572
8573 l1 = gen_new_label();
8574 l2 = gen_new_label();
8575 t0 = tcg_temp_local_new_i32();
8576 /* No error here: 6 bits are used */
8577 tcg_gen_andi_i32(t0, arg2, 0x3F);
8578 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8579 tcg_gen_shr_i32(ret, arg1, t0);
8580 tcg_gen_br(l2);
8581 gen_set_label(l1);
8582 tcg_gen_movi_i32(ret, 0);
8583 gen_set_label(l2);
8584 tcg_temp_free_i32(t0);
8585 }
8586 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8587 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8588 {
8589 TCGv_i32 t0;
8590 int l1, l2;
8591
8592 l1 = gen_new_label();
8593 l2 = gen_new_label();
8594 t0 = tcg_temp_local_new_i32();
8595 /* No error here: 6 bits are used */
8596 tcg_gen_andi_i32(t0, arg2, 0x3F);
8597 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8598 tcg_gen_sar_i32(ret, arg1, t0);
8599 tcg_gen_br(l2);
8600 gen_set_label(l1);
8601 tcg_gen_movi_i32(ret, 0);
8602 gen_set_label(l2);
8603 tcg_temp_free_i32(t0);
8604 }
8605 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8606 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8607 {
8608 TCGv_i32 t0;
8609 int l1, l2;
8610
8611 l1 = gen_new_label();
8612 l2 = gen_new_label();
8613 t0 = tcg_temp_local_new_i32();
8614 /* No error here: 6 bits are used */
8615 tcg_gen_andi_i32(t0, arg2, 0x3F);
8616 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8617 tcg_gen_shl_i32(ret, arg1, t0);
8618 tcg_gen_br(l2);
8619 gen_set_label(l1);
8620 tcg_gen_movi_i32(ret, 0);
8621 gen_set_label(l2);
8622 tcg_temp_free_i32(t0);
8623 }
8624 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8625 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8626 {
8627 TCGv_i32 t0 = tcg_temp_new_i32();
8628 tcg_gen_andi_i32(t0, arg2, 0x1F);
8629 tcg_gen_rotl_i32(ret, arg1, t0);
8630 tcg_temp_free_i32(t0);
8631 }
8632 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8633 static inline void gen_evmergehi(DisasContext *ctx)
8634 {
8635 if (unlikely(!ctx->spe_enabled)) {
8636 gen_exception(ctx, POWERPC_EXCP_SPEU);
8637 return;
8638 }
8639 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8640 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8641 }
8642 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8643 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8644 {
8645 tcg_gen_sub_i32(ret, arg2, arg1);
8646 }
8647 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8648
8649 /* SPE arithmetic immediate */
8650 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8651 static inline void gen_##name(DisasContext *ctx) \
8652 { \
8653 TCGv_i32 t0; \
8654 if (unlikely(!ctx->spe_enabled)) { \
8655 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8656 return; \
8657 } \
8658 t0 = tcg_temp_new_i32(); \
8659 \
8660 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8661 tcg_op(t0, t0, rA(ctx->opcode)); \
8662 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8663 \
8664 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8665 tcg_op(t0, t0, rA(ctx->opcode)); \
8666 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8667 \
8668 tcg_temp_free_i32(t0); \
8669 }
8670 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8671 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8672
8673 /* SPE comparison */
8674 #define GEN_SPEOP_COMP(name, tcg_cond) \
8675 static inline void gen_##name(DisasContext *ctx) \
8676 { \
8677 if (unlikely(!ctx->spe_enabled)) { \
8678 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8679 return; \
8680 } \
8681 int l1 = gen_new_label(); \
8682 int l2 = gen_new_label(); \
8683 int l3 = gen_new_label(); \
8684 int l4 = gen_new_label(); \
8685 \
8686 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8687 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8688 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8689 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8690 \
8691 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8692 cpu_gpr[rB(ctx->opcode)], l1); \
8693 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8694 tcg_gen_br(l2); \
8695 gen_set_label(l1); \
8696 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8697 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8698 gen_set_label(l2); \
8699 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8700 cpu_gprh[rB(ctx->opcode)], l3); \
8701 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8702 ~(CRF_CH | CRF_CH_AND_CL)); \
8703 tcg_gen_br(l4); \
8704 gen_set_label(l3); \
8705 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8706 CRF_CH | CRF_CH_OR_CL); \
8707 gen_set_label(l4); \
8708 }
8709 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8710 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8711 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8712 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8713 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8714
8715 /* SPE misc */
8716 static inline void gen_brinc(DisasContext *ctx)
8717 {
8718 /* Note: brinc is usable even if SPE is disabled */
8719 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8720 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8721 }
8722 static inline void gen_evmergelo(DisasContext *ctx)
8723 {
8724 if (unlikely(!ctx->spe_enabled)) {
8725 gen_exception(ctx, POWERPC_EXCP_SPEU);
8726 return;
8727 }
8728 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8730 }
8731 static inline void gen_evmergehilo(DisasContext *ctx)
8732 {
8733 if (unlikely(!ctx->spe_enabled)) {
8734 gen_exception(ctx, POWERPC_EXCP_SPEU);
8735 return;
8736 }
8737 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8738 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8739 }
8740 static inline void gen_evmergelohi(DisasContext *ctx)
8741 {
8742 if (unlikely(!ctx->spe_enabled)) {
8743 gen_exception(ctx, POWERPC_EXCP_SPEU);
8744 return;
8745 }
8746 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8747 TCGv tmp = tcg_temp_new();
8748 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8749 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8750 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8751 tcg_temp_free(tmp);
8752 } else {
8753 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8754 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8755 }
8756 }
8757 static inline void gen_evsplati(DisasContext *ctx)
8758 {
8759 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8760
8761 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8762 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8763 }
8764 static inline void gen_evsplatfi(DisasContext *ctx)
8765 {
8766 uint64_t imm = rA(ctx->opcode) << 27;
8767
8768 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8769 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8770 }
8771
8772 static inline void gen_evsel(DisasContext *ctx)
8773 {
8774 int l1 = gen_new_label();
8775 int l2 = gen_new_label();
8776 int l3 = gen_new_label();
8777 int l4 = gen_new_label();
8778 TCGv_i32 t0 = tcg_temp_local_new_i32();
8779 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8780 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8781 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8782 tcg_gen_br(l2);
8783 gen_set_label(l1);
8784 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8785 gen_set_label(l2);
8786 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8787 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8788 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8789 tcg_gen_br(l4);
8790 gen_set_label(l3);
8791 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8792 gen_set_label(l4);
8793 tcg_temp_free_i32(t0);
8794 }
8795
8796 static void gen_evsel0(DisasContext *ctx)
8797 {
8798 gen_evsel(ctx);
8799 }
8800
8801 static void gen_evsel1(DisasContext *ctx)
8802 {
8803 gen_evsel(ctx);
8804 }
8805
8806 static void gen_evsel2(DisasContext *ctx)
8807 {
8808 gen_evsel(ctx);
8809 }
8810
8811 static void gen_evsel3(DisasContext *ctx)
8812 {
8813 gen_evsel(ctx);
8814 }
8815
8816 /* Multiply */
8817
8818 static inline void gen_evmwumi(DisasContext *ctx)
8819 {
8820 TCGv_i64 t0, t1;
8821
8822 if (unlikely(!ctx->spe_enabled)) {
8823 gen_exception(ctx, POWERPC_EXCP_SPEU);
8824 return;
8825 }
8826
8827 t0 = tcg_temp_new_i64();
8828 t1 = tcg_temp_new_i64();
8829
8830 /* t0 := rA; t1 := rB */
8831 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8832 tcg_gen_ext32u_i64(t0, t0);
8833 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8834 tcg_gen_ext32u_i64(t1, t1);
8835
8836 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8837
8838 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8839
8840 tcg_temp_free_i64(t0);
8841 tcg_temp_free_i64(t1);
8842 }
8843
8844 static inline void gen_evmwumia(DisasContext *ctx)
8845 {
8846 TCGv_i64 tmp;
8847
8848 if (unlikely(!ctx->spe_enabled)) {
8849 gen_exception(ctx, POWERPC_EXCP_SPEU);
8850 return;
8851 }
8852
8853 gen_evmwumi(ctx); /* rD := rA * rB */
8854
8855 tmp = tcg_temp_new_i64();
8856
8857 /* acc := rD */
8858 gen_load_gpr64(tmp, rD(ctx->opcode));
8859 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8860 tcg_temp_free_i64(tmp);
8861 }
8862
8863 static inline void gen_evmwumiaa(DisasContext *ctx)
8864 {
8865 TCGv_i64 acc;
8866 TCGv_i64 tmp;
8867
8868 if (unlikely(!ctx->spe_enabled)) {
8869 gen_exception(ctx, POWERPC_EXCP_SPEU);
8870 return;
8871 }
8872
8873 gen_evmwumi(ctx); /* rD := rA * rB */
8874
8875 acc = tcg_temp_new_i64();
8876 tmp = tcg_temp_new_i64();
8877
8878 /* tmp := rD */
8879 gen_load_gpr64(tmp, rD(ctx->opcode));
8880
8881 /* Load acc */
8882 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8883
8884 /* acc := tmp + acc */
8885 tcg_gen_add_i64(acc, acc, tmp);
8886
8887 /* Store acc */
8888 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8889
8890 /* rD := acc */
8891 gen_store_gpr64(rD(ctx->opcode), acc);
8892
8893 tcg_temp_free_i64(acc);
8894 tcg_temp_free_i64(tmp);
8895 }
8896
8897 static inline void gen_evmwsmi(DisasContext *ctx)
8898 {
8899 TCGv_i64 t0, t1;
8900
8901 if (unlikely(!ctx->spe_enabled)) {
8902 gen_exception(ctx, POWERPC_EXCP_SPEU);
8903 return;
8904 }
8905
8906 t0 = tcg_temp_new_i64();
8907 t1 = tcg_temp_new_i64();
8908
8909 /* t0 := rA; t1 := rB */
8910 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8911 tcg_gen_ext32s_i64(t0, t0);
8912 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8913 tcg_gen_ext32s_i64(t1, t1);
8914
8915 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8916
8917 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8918
8919 tcg_temp_free_i64(t0);
8920 tcg_temp_free_i64(t1);
8921 }
8922
8923 static inline void gen_evmwsmia(DisasContext *ctx)
8924 {
8925 TCGv_i64 tmp;
8926
8927 gen_evmwsmi(ctx); /* rD := rA * rB */
8928
8929 tmp = tcg_temp_new_i64();
8930
8931 /* acc := rD */
8932 gen_load_gpr64(tmp, rD(ctx->opcode));
8933 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8934
8935 tcg_temp_free_i64(tmp);
8936 }
8937
8938 static inline void gen_evmwsmiaa(DisasContext *ctx)
8939 {
8940 TCGv_i64 acc = tcg_temp_new_i64();
8941 TCGv_i64 tmp = tcg_temp_new_i64();
8942
8943 gen_evmwsmi(ctx); /* rD := rA * rB */
8944
8945 acc = tcg_temp_new_i64();
8946 tmp = tcg_temp_new_i64();
8947
8948 /* tmp := rD */
8949 gen_load_gpr64(tmp, rD(ctx->opcode));
8950
8951 /* Load acc */
8952 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8953
8954 /* acc := tmp + acc */
8955 tcg_gen_add_i64(acc, acc, tmp);
8956
8957 /* Store acc */
8958 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8959
8960 /* rD := acc */
8961 gen_store_gpr64(rD(ctx->opcode), acc);
8962
8963 tcg_temp_free_i64(acc);
8964 tcg_temp_free_i64(tmp);
8965 }
8966
8967 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8968 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8969 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8970 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8971 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8972 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8973 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8974 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8975 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8976 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8977 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8978 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8979 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8980 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8981 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8982 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8983 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8984 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8985 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8986 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8987 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8988 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8989 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8990 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8991 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8992 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8993 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8994 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8995 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8996
8997 /* SPE load and stores */
8998 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8999 {
9000 target_ulong uimm = rB(ctx->opcode);
9001
9002 if (rA(ctx->opcode) == 0) {
9003 tcg_gen_movi_tl(EA, uimm << sh);
9004 } else {
9005 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9006 if (NARROW_MODE(ctx)) {
9007 tcg_gen_ext32u_tl(EA, EA);
9008 }
9009 }
9010 }
9011
9012 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9013 {
9014 TCGv_i64 t0 = tcg_temp_new_i64();
9015 gen_qemu_ld64(ctx, t0, addr);
9016 gen_store_gpr64(rD(ctx->opcode), t0);
9017 tcg_temp_free_i64(t0);
9018 }
9019
9020 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9021 {
9022 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9023 gen_addr_add(ctx, addr, addr, 4);
9024 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9025 }
9026
9027 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9028 {
9029 TCGv t0 = tcg_temp_new();
9030 gen_qemu_ld16u(ctx, t0, addr);
9031 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9032 gen_addr_add(ctx, addr, addr, 2);
9033 gen_qemu_ld16u(ctx, t0, addr);
9034 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9035 gen_addr_add(ctx, addr, addr, 2);
9036 gen_qemu_ld16u(ctx, t0, addr);
9037 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9038 gen_addr_add(ctx, addr, addr, 2);
9039 gen_qemu_ld16u(ctx, t0, addr);
9040 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9041 tcg_temp_free(t0);
9042 }
9043
9044 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9045 {
9046 TCGv t0 = tcg_temp_new();
9047 gen_qemu_ld16u(ctx, t0, addr);
9048 tcg_gen_shli_tl(t0, t0, 16);
9049 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9050 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9051 tcg_temp_free(t0);
9052 }
9053
9054 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9055 {
9056 TCGv t0 = tcg_temp_new();
9057 gen_qemu_ld16u(ctx, t0, addr);
9058 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9059 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9060 tcg_temp_free(t0);
9061 }
9062
9063 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9064 {
9065 TCGv t0 = tcg_temp_new();
9066 gen_qemu_ld16s(ctx, t0, addr);
9067 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9068 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9069 tcg_temp_free(t0);
9070 }
9071
9072 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9073 {
9074 TCGv t0 = tcg_temp_new();
9075 gen_qemu_ld16u(ctx, t0, addr);
9076 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9077 gen_addr_add(ctx, addr, addr, 2);
9078 gen_qemu_ld16u(ctx, t0, addr);
9079 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9080 tcg_temp_free(t0);
9081 }
9082
9083 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9084 {
9085 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9086 gen_addr_add(ctx, addr, addr, 2);
9087 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9088 }
9089
9090 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9091 {
9092 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9093 gen_addr_add(ctx, addr, addr, 2);
9094 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9095 }
9096
9097 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9098 {
9099 TCGv t0 = tcg_temp_new();
9100 gen_qemu_ld32u(ctx, t0, addr);
9101 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9102 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9103 tcg_temp_free(t0);
9104 }
9105
9106 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9107 {
9108 TCGv t0 = tcg_temp_new();
9109 gen_qemu_ld16u(ctx, t0, addr);
9110 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9111 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9112 gen_addr_add(ctx, addr, addr, 2);
9113 gen_qemu_ld16u(ctx, t0, addr);
9114 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9115 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9116 tcg_temp_free(t0);
9117 }
9118
9119 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9120 {
9121 TCGv_i64 t0 = tcg_temp_new_i64();
9122 gen_load_gpr64(t0, rS(ctx->opcode));
9123 gen_qemu_st64(ctx, t0, addr);
9124 tcg_temp_free_i64(t0);
9125 }
9126
9127 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9128 {
9129 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9130 gen_addr_add(ctx, addr, addr, 4);
9131 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9132 }
9133
9134 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9135 {
9136 TCGv t0 = tcg_temp_new();
9137 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9138 gen_qemu_st16(ctx, t0, addr);
9139 gen_addr_add(ctx, addr, addr, 2);
9140 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9141 gen_addr_add(ctx, addr, addr, 2);
9142 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9143 gen_qemu_st16(ctx, t0, addr);
9144 tcg_temp_free(t0);
9145 gen_addr_add(ctx, addr, addr, 2);
9146 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9147 }
9148
9149 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9150 {
9151 TCGv t0 = tcg_temp_new();
9152 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9153 gen_qemu_st16(ctx, t0, addr);
9154 gen_addr_add(ctx, addr, addr, 2);
9155 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9156 gen_qemu_st16(ctx, t0, addr);
9157 tcg_temp_free(t0);
9158 }
9159
9160 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9161 {
9162 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9163 gen_addr_add(ctx, addr, addr, 2);
9164 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9165 }
9166
9167 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9168 {
9169 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9170 }
9171
9172 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9173 {
9174 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9175 }
9176
9177 #define GEN_SPEOP_LDST(name, opc2, sh) \
9178 static void glue(gen_, name)(DisasContext *ctx) \
9179 { \
9180 TCGv t0; \
9181 if (unlikely(!ctx->spe_enabled)) { \
9182 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9183 return; \
9184 } \
9185 gen_set_access_type(ctx, ACCESS_INT); \
9186 t0 = tcg_temp_new(); \
9187 if (Rc(ctx->opcode)) { \
9188 gen_addr_spe_imm_index(ctx, t0, sh); \
9189 } else { \
9190 gen_addr_reg_index(ctx, t0); \
9191 } \
9192 gen_op_##name(ctx, t0); \
9193 tcg_temp_free(t0); \
9194 }
9195
9196 GEN_SPEOP_LDST(evldd, 0x00, 3);
9197 GEN_SPEOP_LDST(evldw, 0x01, 3);
9198 GEN_SPEOP_LDST(evldh, 0x02, 3);
9199 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9200 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9201 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9202 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9203 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9204 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9205 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9206 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9207
9208 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9209 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9210 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9211 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9212 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9213 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9214 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9215
9216 /* Multiply and add - TODO */
9217 #if 0
9218 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9219 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9220 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9221 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9222 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9223 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9224 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9225 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9226 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9227 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9228 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9229 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9230
9231 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9232 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9233 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9234 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9235 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9236 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9237 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9238 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9239 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9240 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9241 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9242 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9243
9244 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9245 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9246 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9247 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9248 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9249
9250 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9251 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9252 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9253 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9254 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9255 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9256 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9257 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9258 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9259 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9260 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9261 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9262
9263 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9264 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9265 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9266 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9267
9268 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9269 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9270 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9271 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9272 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9273 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9275 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9276 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9277 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9279 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280
9281 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9282 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9283 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9284 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9285 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9286 #endif
9287
9288 /*** SPE floating-point extension ***/
9289 #define GEN_SPEFPUOP_CONV_32_32(name) \
9290 static inline void gen_##name(DisasContext *ctx) \
9291 { \
9292 TCGv_i32 t0 = tcg_temp_new_i32(); \
9293 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9294 gen_helper_##name(t0, cpu_env, t0); \
9295 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9296 tcg_temp_free_i32(t0); \
9297 }
9298 #define GEN_SPEFPUOP_CONV_32_64(name) \
9299 static inline void gen_##name(DisasContext *ctx) \
9300 { \
9301 TCGv_i64 t0 = tcg_temp_new_i64(); \
9302 TCGv_i32 t1 = tcg_temp_new_i32(); \
9303 gen_load_gpr64(t0, rB(ctx->opcode)); \
9304 gen_helper_##name(t1, cpu_env, t0); \
9305 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9306 tcg_temp_free_i64(t0); \
9307 tcg_temp_free_i32(t1); \
9308 }
9309 #define GEN_SPEFPUOP_CONV_64_32(name) \
9310 static inline void gen_##name(DisasContext *ctx) \
9311 { \
9312 TCGv_i64 t0 = tcg_temp_new_i64(); \
9313 TCGv_i32 t1 = tcg_temp_new_i32(); \
9314 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9315 gen_helper_##name(t0, cpu_env, t1); \
9316 gen_store_gpr64(rD(ctx->opcode), t0); \
9317 tcg_temp_free_i64(t0); \
9318 tcg_temp_free_i32(t1); \
9319 }
9320 #define GEN_SPEFPUOP_CONV_64_64(name) \
9321 static inline void gen_##name(DisasContext *ctx) \
9322 { \
9323 TCGv_i64 t0 = tcg_temp_new_i64(); \
9324 gen_load_gpr64(t0, rB(ctx->opcode)); \
9325 gen_helper_##name(t0, cpu_env, t0); \
9326 gen_store_gpr64(rD(ctx->opcode), t0); \
9327 tcg_temp_free_i64(t0); \
9328 }
9329 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9330 static inline void gen_##name(DisasContext *ctx) \
9331 { \
9332 TCGv_i32 t0, t1; \
9333 if (unlikely(!ctx->spe_enabled)) { \
9334 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9335 return; \
9336 } \
9337 t0 = tcg_temp_new_i32(); \
9338 t1 = tcg_temp_new_i32(); \
9339 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9340 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9341 gen_helper_##name(t0, cpu_env, t0, t1); \
9342 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9343 \
9344 tcg_temp_free_i32(t0); \
9345 tcg_temp_free_i32(t1); \
9346 }
9347 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9348 static inline void gen_##name(DisasContext *ctx) \
9349 { \
9350 TCGv_i64 t0, t1; \
9351 if (unlikely(!ctx->spe_enabled)) { \
9352 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9353 return; \
9354 } \
9355 t0 = tcg_temp_new_i64(); \
9356 t1 = tcg_temp_new_i64(); \
9357 gen_load_gpr64(t0, rA(ctx->opcode)); \
9358 gen_load_gpr64(t1, rB(ctx->opcode)); \
9359 gen_helper_##name(t0, cpu_env, t0, t1); \
9360 gen_store_gpr64(rD(ctx->opcode), t0); \
9361 tcg_temp_free_i64(t0); \
9362 tcg_temp_free_i64(t1); \
9363 }
9364 #define GEN_SPEFPUOP_COMP_32(name) \
9365 static inline void gen_##name(DisasContext *ctx) \
9366 { \
9367 TCGv_i32 t0, t1; \
9368 if (unlikely(!ctx->spe_enabled)) { \
9369 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9370 return; \
9371 } \
9372 t0 = tcg_temp_new_i32(); \
9373 t1 = tcg_temp_new_i32(); \
9374 \
9375 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9376 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9377 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9378 \
9379 tcg_temp_free_i32(t0); \
9380 tcg_temp_free_i32(t1); \
9381 }
9382 #define GEN_SPEFPUOP_COMP_64(name) \
9383 static inline void gen_##name(DisasContext *ctx) \
9384 { \
9385 TCGv_i64 t0, t1; \
9386 if (unlikely(!ctx->spe_enabled)) { \
9387 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9388 return; \
9389 } \
9390 t0 = tcg_temp_new_i64(); \
9391 t1 = tcg_temp_new_i64(); \
9392 gen_load_gpr64(t0, rA(ctx->opcode)); \
9393 gen_load_gpr64(t1, rB(ctx->opcode)); \
9394 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9395 tcg_temp_free_i64(t0); \
9396 tcg_temp_free_i64(t1); \
9397 }
9398
9399 /* Single precision floating-point vectors operations */
9400 /* Arithmetic */
9401 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9402 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9403 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9404 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9405 static inline void gen_evfsabs(DisasContext *ctx)
9406 {
9407 if (unlikely(!ctx->spe_enabled)) {
9408 gen_exception(ctx, POWERPC_EXCP_SPEU);
9409 return;
9410 }
9411 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9412 ~0x80000000);
9413 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9414 ~0x80000000);
9415 }
9416 static inline void gen_evfsnabs(DisasContext *ctx)
9417 {
9418 if (unlikely(!ctx->spe_enabled)) {
9419 gen_exception(ctx, POWERPC_EXCP_SPEU);
9420 return;
9421 }
9422 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9423 0x80000000);
9424 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9425 0x80000000);
9426 }
9427 static inline void gen_evfsneg(DisasContext *ctx)
9428 {
9429 if (unlikely(!ctx->spe_enabled)) {
9430 gen_exception(ctx, POWERPC_EXCP_SPEU);
9431 return;
9432 }
9433 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9434 0x80000000);
9435 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9436 0x80000000);
9437 }
9438
9439 /* Conversion */
9440 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9441 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9442 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9443 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9444 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9445 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9446 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9447 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9448 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9449 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9450
9451 /* Comparison */
9452 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9453 GEN_SPEFPUOP_COMP_64(evfscmplt);
9454 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9455 GEN_SPEFPUOP_COMP_64(evfststgt);
9456 GEN_SPEFPUOP_COMP_64(evfststlt);
9457 GEN_SPEFPUOP_COMP_64(evfststeq);
9458
9459 /* Opcodes definitions */
9460 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9461 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9462 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9463 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9464 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9465 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9466 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9467 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9468 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9469 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9470 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9471 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9472 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9473 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9474
9475 /* Single precision floating-point operations */
9476 /* Arithmetic */
9477 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9478 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9479 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9480 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9481 static inline void gen_efsabs(DisasContext *ctx)
9482 {
9483 if (unlikely(!ctx->spe_enabled)) {
9484 gen_exception(ctx, POWERPC_EXCP_SPEU);
9485 return;
9486 }
9487 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9488 }
9489 static inline void gen_efsnabs(DisasContext *ctx)
9490 {
9491 if (unlikely(!ctx->spe_enabled)) {
9492 gen_exception(ctx, POWERPC_EXCP_SPEU);
9493 return;
9494 }
9495 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9496 }
9497 static inline void gen_efsneg(DisasContext *ctx)
9498 {
9499 if (unlikely(!ctx->spe_enabled)) {
9500 gen_exception(ctx, POWERPC_EXCP_SPEU);
9501 return;
9502 }
9503 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9504 }
9505
9506 /* Conversion */
9507 GEN_SPEFPUOP_CONV_32_32(efscfui);
9508 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9509 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9510 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9511 GEN_SPEFPUOP_CONV_32_32(efsctui);
9512 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9513 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9514 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9515 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9516 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9517 GEN_SPEFPUOP_CONV_32_64(efscfd);
9518
9519 /* Comparison */
9520 GEN_SPEFPUOP_COMP_32(efscmpgt);
9521 GEN_SPEFPUOP_COMP_32(efscmplt);
9522 GEN_SPEFPUOP_COMP_32(efscmpeq);
9523 GEN_SPEFPUOP_COMP_32(efststgt);
9524 GEN_SPEFPUOP_COMP_32(efststlt);
9525 GEN_SPEFPUOP_COMP_32(efststeq);
9526
9527 /* Opcodes definitions */
9528 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9529 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9530 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9531 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9532 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9533 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9534 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9535 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9536 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9537 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9538 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9539 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9540 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9541 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9542
9543 /* Double precision floating-point operations */
9544 /* Arithmetic */
9545 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9546 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9547 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9548 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9549 static inline void gen_efdabs(DisasContext *ctx)
9550 {
9551 if (unlikely(!ctx->spe_enabled)) {
9552 gen_exception(ctx, POWERPC_EXCP_SPEU);
9553 return;
9554 }
9555 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9556 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9557 ~0x80000000);
9558 }
9559 static inline void gen_efdnabs(DisasContext *ctx)
9560 {
9561 if (unlikely(!ctx->spe_enabled)) {
9562 gen_exception(ctx, POWERPC_EXCP_SPEU);
9563 return;
9564 }
9565 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9566 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9567 0x80000000);
9568 }
9569 static inline void gen_efdneg(DisasContext *ctx)
9570 {
9571 if (unlikely(!ctx->spe_enabled)) {
9572 gen_exception(ctx, POWERPC_EXCP_SPEU);
9573 return;
9574 }
9575 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9576 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9577 0x80000000);
9578 }
9579
9580 /* Conversion */
9581 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9582 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9583 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9584 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9585 GEN_SPEFPUOP_CONV_32_64(efdctui);
9586 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9587 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9588 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9589 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9590 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9591 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9592 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9593 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9594 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9595 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9596
9597 /* Comparison */
9598 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9599 GEN_SPEFPUOP_COMP_64(efdcmplt);
9600 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9601 GEN_SPEFPUOP_COMP_64(efdtstgt);
9602 GEN_SPEFPUOP_COMP_64(efdtstlt);
9603 GEN_SPEFPUOP_COMP_64(efdtsteq);
9604
9605 /* Opcodes definitions */
9606 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9607 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9608 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9609 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9610 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9611 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9612 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9613 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9614 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9615 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9616 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9617 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9618 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9619 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9620 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9621 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9622
9623 static opcode_t opcodes[] = {
9624 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9625 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9626 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9627 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9628 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9629 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9630 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9631 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9632 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9633 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9634 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9635 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9636 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9637 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9638 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9639 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9640 #if defined(TARGET_PPC64)
9641 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9642 #endif
9643 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9644 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9645 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9646 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9647 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9648 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9649 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9650 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9651 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9652 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9653 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9654 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9655 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9656 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9657 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9658 #if defined(TARGET_PPC64)
9659 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9660 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9661 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9662 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9663 #endif
9664 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9665 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9666 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9667 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9668 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9669 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9670 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9671 #if defined(TARGET_PPC64)
9672 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9673 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9674 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9675 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9676 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9677 #endif
9678 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9679 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9680 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9681 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9682 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9683 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9684 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9685 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9686 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9687 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9688 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9689 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9690 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9691 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9692 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9693 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9694 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9695 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9696 #if defined(TARGET_PPC64)
9697 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9698 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9699 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9700 #endif
9701 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9702 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9703 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9704 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9705 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9706 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9707 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9708 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9709 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9710 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9711 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9712 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9713 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9714 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9715 #if defined(TARGET_PPC64)
9716 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9717 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9718 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9719 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9720 #endif
9721 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9722 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9723 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9724 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9725 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9726 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9727 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9728 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9729 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9730 #if defined(TARGET_PPC64)
9731 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9732 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9733 #endif
9734 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9735 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9736 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9737 #if defined(TARGET_PPC64)
9738 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9739 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9740 #endif
9741 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9742 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9743 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9744 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9745 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9746 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9747 #if defined(TARGET_PPC64)
9748 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9749 #endif
9750 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9751 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9752 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9753 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9754 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9755 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9756 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9757 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9758 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9759 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9760 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9761 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9762 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9763 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9764 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9765 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9766 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9767 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9768 #if defined(TARGET_PPC64)
9769 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9770 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9771 PPC_SEGMENT_64B),
9772 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9773 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9774 PPC_SEGMENT_64B),
9775 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9776 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9777 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9778 #endif
9779 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9780 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9781 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9782 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9783 #if defined(TARGET_PPC64)
9784 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9785 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9786 #endif
9787 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9788 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9789 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9790 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9791 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9792 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9793 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9794 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9795 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9796 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9797 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9798 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9799 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9800 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9801 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9802 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9803 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9804 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9805 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9806 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9807 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9808 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9809 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9810 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9811 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9812 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9813 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9814 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9815 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9816 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9817 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9818 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9819 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9820 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9821 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9822 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9823 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9824 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9825 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9826 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9827 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9828 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9829 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9830 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9831 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9832 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9833 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9834 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9835 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9836 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9837 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9838 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9839 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9840 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9841 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9842 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9843 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9844 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9845 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9846 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9847 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9848 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9849 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9850 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9851 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9852 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9853 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9854 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9855 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9856 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9857 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9858 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9859 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9860 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9861 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9862 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9863 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9864 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9865 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9866 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9867 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9868 PPC_NONE, PPC2_BOOKE206),
9869 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9870 PPC_NONE, PPC2_BOOKE206),
9871 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9872 PPC_NONE, PPC2_BOOKE206),
9873 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9874 PPC_NONE, PPC2_BOOKE206),
9875 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9876 PPC_NONE, PPC2_BOOKE206),
9877 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9878 PPC_NONE, PPC2_PRCNTL),
9879 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9880 PPC_NONE, PPC2_PRCNTL),
9881 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9882 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9883 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9884 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9885 PPC_BOOKE, PPC2_BOOKE206),
9886 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9887 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9888 PPC_BOOKE, PPC2_BOOKE206),
9889 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9890 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9891 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9892 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9893 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9894 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9895 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9896 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9897 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9898
9899 #undef GEN_INT_ARITH_ADD
9900 #undef GEN_INT_ARITH_ADD_CONST
9901 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9902 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9903 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9904 add_ca, compute_ca, compute_ov) \
9905 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9906 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9907 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9908 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9909 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9910 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9911 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9912 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9913 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9914 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9915 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9916
9917 #undef GEN_INT_ARITH_DIVW
9918 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9919 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9920 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9921 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9922 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9923 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9924 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9925 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9926 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9927 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9928
9929 #if defined(TARGET_PPC64)
9930 #undef GEN_INT_ARITH_DIVD
9931 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9932 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9933 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9934 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9935 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9936 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9937
9938 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9939 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9940 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9941 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9942
9943 #undef GEN_INT_ARITH_MUL_HELPER
9944 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9945 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9946 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9947 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9948 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9949 #endif
9950
9951 #undef GEN_INT_ARITH_SUBF
9952 #undef GEN_INT_ARITH_SUBF_CONST
9953 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9954 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9955 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9956 add_ca, compute_ca, compute_ov) \
9957 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9958 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9959 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9960 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9961 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9962 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9963 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9964 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9965 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9966 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9967 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9968
9969 #undef GEN_LOGICAL1
9970 #undef GEN_LOGICAL2
9971 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9972 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9973 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9974 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9975 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9976 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9977 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9978 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9979 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9980 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9981 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9982 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9983 #if defined(TARGET_PPC64)
9984 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9985 #endif
9986
9987 #if defined(TARGET_PPC64)
9988 #undef GEN_PPC64_R2
9989 #undef GEN_PPC64_R4
9990 #define GEN_PPC64_R2(name, opc1, opc2) \
9991 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9992 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9993 PPC_64B)
9994 #define GEN_PPC64_R4(name, opc1, opc2) \
9995 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9996 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9997 PPC_64B), \
9998 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9999 PPC_64B), \
10000 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10001 PPC_64B)
10002 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10003 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10004 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10005 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10006 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10007 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10008 #endif
10009
10010 #undef _GEN_FLOAT_ACB
10011 #undef GEN_FLOAT_ACB
10012 #undef _GEN_FLOAT_AB
10013 #undef GEN_FLOAT_AB
10014 #undef _GEN_FLOAT_AC
10015 #undef GEN_FLOAT_AC
10016 #undef GEN_FLOAT_B
10017 #undef GEN_FLOAT_BS
10018 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10019 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10020 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10021 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10022 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10023 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10024 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10025 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10026 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10027 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10028 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10029 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10030 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10031 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10032 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10033 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10034 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10035 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10036 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10037
10038 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10039 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10040 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10041 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10042 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10043 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10044 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10045 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10046 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10047 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10048 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10049 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10050 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10051 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10052 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10053 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10054 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10055 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10056 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10057 #if defined(TARGET_PPC64)
10058 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10059 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10060 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10061 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10062 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10063 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10064 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10065 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10066 #endif
10067 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10068 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10069 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10070 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10071
10072 #undef GEN_LD
10073 #undef GEN_LDU
10074 #undef GEN_LDUX
10075 #undef GEN_LDX_E
10076 #undef GEN_LDS
10077 #define GEN_LD(name, ldop, opc, type) \
10078 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10079 #define GEN_LDU(name, ldop, opc, type) \
10080 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10081 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10082 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10083 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10084 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10085 #define GEN_LDS(name, ldop, op, type) \
10086 GEN_LD(name, ldop, op | 0x20, type) \
10087 GEN_LDU(name, ldop, op | 0x21, type) \
10088 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10089 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10090
10091 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10092 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10093 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10094 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10095 #if defined(TARGET_PPC64)
10096 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10097 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10098 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10099 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10100 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10101 #endif
10102 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10103 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10104
10105 #undef GEN_ST
10106 #undef GEN_STU
10107 #undef GEN_STUX
10108 #undef GEN_STX_E
10109 #undef GEN_STS
10110 #define GEN_ST(name, stop, opc, type) \
10111 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10112 #define GEN_STU(name, stop, opc, type) \
10113 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10114 #define GEN_STUX(name, stop, opc2, opc3, type) \
10115 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10116 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10117 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10118 #define GEN_STS(name, stop, op, type) \
10119 GEN_ST(name, stop, op | 0x20, type) \
10120 GEN_STU(name, stop, op | 0x21, type) \
10121 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10122 GEN_STX(name, stop, 0x17, op | 0x00, type)
10123
10124 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10125 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10126 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10127 #if defined(TARGET_PPC64)
10128 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10129 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10130 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10131 #endif
10132 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10133 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10134
10135 #undef GEN_LDF
10136 #undef GEN_LDUF
10137 #undef GEN_LDUXF
10138 #undef GEN_LDXF
10139 #undef GEN_LDFS
10140 #define GEN_LDF(name, ldop, opc, type) \
10141 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10142 #define GEN_LDUF(name, ldop, opc, type) \
10143 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10144 #define GEN_LDUXF(name, ldop, opc, type) \
10145 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10146 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10147 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10148 #define GEN_LDFS(name, ldop, op, type) \
10149 GEN_LDF(name, ldop, op | 0x20, type) \
10150 GEN_LDUF(name, ldop, op | 0x21, type) \
10151 GEN_LDUXF(name, ldop, op | 0x01, type) \
10152 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10153
10154 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10155 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10156 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10157 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10158 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10159 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10160
10161 #undef GEN_STF
10162 #undef GEN_STUF
10163 #undef GEN_STUXF
10164 #undef GEN_STXF
10165 #undef GEN_STFS
10166 #define GEN_STF(name, stop, opc, type) \
10167 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10168 #define GEN_STUF(name, stop, opc, type) \
10169 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10170 #define GEN_STUXF(name, stop, opc, type) \
10171 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10172 #define GEN_STXF(name, stop, opc2, opc3, type) \
10173 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10174 #define GEN_STFS(name, stop, op, type) \
10175 GEN_STF(name, stop, op | 0x20, type) \
10176 GEN_STUF(name, stop, op | 0x21, type) \
10177 GEN_STUXF(name, stop, op | 0x01, type) \
10178 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10179
10180 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10181 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10182 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10183 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10184 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10185
10186 #undef GEN_CRLOGIC
10187 #define GEN_CRLOGIC(name, tcg_op, opc) \
10188 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10189 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10190 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10191 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10192 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10193 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10194 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10195 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10196 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10197
10198 #undef GEN_MAC_HANDLER
10199 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10200 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10201 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10202 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10203 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10204 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10205 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10206 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10207 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10208 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10209 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10210 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10211 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10212 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10213 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10214 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10215 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10216 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10217 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10218 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10219 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10220 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10221 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10222 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10223 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10224 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10225 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10226 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10227 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10228 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10229 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10230 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10231 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10232 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10233 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10234 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10235 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10236 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10237 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10238 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10239 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10240 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10241 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10242 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10243
10244 #undef GEN_VR_LDX
10245 #undef GEN_VR_STX
10246 #undef GEN_VR_LVE
10247 #undef GEN_VR_STVE
10248 #define GEN_VR_LDX(name, opc2, opc3) \
10249 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10250 #define GEN_VR_STX(name, opc2, opc3) \
10251 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10252 #define GEN_VR_LVE(name, opc2, opc3) \
10253 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10254 #define GEN_VR_STVE(name, opc2, opc3) \
10255 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10256 GEN_VR_LDX(lvx, 0x07, 0x03),
10257 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10258 GEN_VR_LVE(bx, 0x07, 0x00),
10259 GEN_VR_LVE(hx, 0x07, 0x01),
10260 GEN_VR_LVE(wx, 0x07, 0x02),
10261 GEN_VR_STX(svx, 0x07, 0x07),
10262 GEN_VR_STX(svxl, 0x07, 0x0F),
10263 GEN_VR_STVE(bx, 0x07, 0x04),
10264 GEN_VR_STVE(hx, 0x07, 0x05),
10265 GEN_VR_STVE(wx, 0x07, 0x06),
10266
10267 #undef GEN_VX_LOGICAL
10268 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10269 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10270
10271 #undef GEN_VX_LOGICAL_207
10272 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10273 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10274
10275 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10276 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10277 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10278 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10279 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10280 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10281 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10282 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10283
10284 #undef GEN_VXFORM
10285 #define GEN_VXFORM(name, opc2, opc3) \
10286 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10287
10288 #undef GEN_VXFORM_207
10289 #define GEN_VXFORM_207(name, opc2, opc3) \
10290 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10291
10292 #undef GEN_VXFORM_DUAL
10293 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10294 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10295
10296 #undef GEN_VXRFORM_DUAL
10297 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10298 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10299 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10300
10301 GEN_VXFORM(vaddubm, 0, 0),
10302 GEN_VXFORM(vadduhm, 0, 1),
10303 GEN_VXFORM(vadduwm, 0, 2),
10304 GEN_VXFORM_207(vaddudm, 0, 3),
10305 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10306 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10307 GEN_VXFORM(vsubuwm, 0, 18),
10308 GEN_VXFORM_207(vsubudm, 0, 19),
10309 GEN_VXFORM(vmaxub, 1, 0),
10310 GEN_VXFORM(vmaxuh, 1, 1),
10311 GEN_VXFORM(vmaxuw, 1, 2),
10312 GEN_VXFORM_207(vmaxud, 1, 3),
10313 GEN_VXFORM(vmaxsb, 1, 4),
10314 GEN_VXFORM(vmaxsh, 1, 5),
10315 GEN_VXFORM(vmaxsw, 1, 6),
10316 GEN_VXFORM_207(vmaxsd, 1, 7),
10317 GEN_VXFORM(vminub, 1, 8),
10318 GEN_VXFORM(vminuh, 1, 9),
10319 GEN_VXFORM(vminuw, 1, 10),
10320 GEN_VXFORM_207(vminud, 1, 11),
10321 GEN_VXFORM(vminsb, 1, 12),
10322 GEN_VXFORM(vminsh, 1, 13),
10323 GEN_VXFORM(vminsw, 1, 14),
10324 GEN_VXFORM_207(vminsd, 1, 15),
10325 GEN_VXFORM(vavgub, 1, 16),
10326 GEN_VXFORM(vavguh, 1, 17),
10327 GEN_VXFORM(vavguw, 1, 18),
10328 GEN_VXFORM(vavgsb, 1, 20),
10329 GEN_VXFORM(vavgsh, 1, 21),
10330 GEN_VXFORM(vavgsw, 1, 22),
10331 GEN_VXFORM(vmrghb, 6, 0),
10332 GEN_VXFORM(vmrghh, 6, 1),
10333 GEN_VXFORM(vmrghw, 6, 2),
10334 GEN_VXFORM(vmrglb, 6, 4),
10335 GEN_VXFORM(vmrglh, 6, 5),
10336 GEN_VXFORM(vmrglw, 6, 6),
10337 GEN_VXFORM_207(vmrgew, 6, 30),
10338 GEN_VXFORM_207(vmrgow, 6, 26),
10339 GEN_VXFORM(vmuloub, 4, 0),
10340 GEN_VXFORM(vmulouh, 4, 1),
10341 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10342 GEN_VXFORM(vmulosb, 4, 4),
10343 GEN_VXFORM(vmulosh, 4, 5),
10344 GEN_VXFORM_207(vmulosw, 4, 6),
10345 GEN_VXFORM(vmuleub, 4, 8),
10346 GEN_VXFORM(vmuleuh, 4, 9),
10347 GEN_VXFORM_207(vmuleuw, 4, 10),
10348 GEN_VXFORM(vmulesb, 4, 12),
10349 GEN_VXFORM(vmulesh, 4, 13),
10350 GEN_VXFORM_207(vmulesw, 4, 14),
10351 GEN_VXFORM(vslb, 2, 4),
10352 GEN_VXFORM(vslh, 2, 5),
10353 GEN_VXFORM(vslw, 2, 6),
10354 GEN_VXFORM_207(vsld, 2, 23),
10355 GEN_VXFORM(vsrb, 2, 8),
10356 GEN_VXFORM(vsrh, 2, 9),
10357 GEN_VXFORM(vsrw, 2, 10),
10358 GEN_VXFORM_207(vsrd, 2, 27),
10359 GEN_VXFORM(vsrab, 2, 12),
10360 GEN_VXFORM(vsrah, 2, 13),
10361 GEN_VXFORM(vsraw, 2, 14),
10362 GEN_VXFORM_207(vsrad, 2, 15),
10363 GEN_VXFORM(vslo, 6, 16),
10364 GEN_VXFORM(vsro, 6, 17),
10365 GEN_VXFORM(vaddcuw, 0, 6),
10366 GEN_VXFORM(vsubcuw, 0, 22),
10367 GEN_VXFORM(vaddubs, 0, 8),
10368 GEN_VXFORM(vadduhs, 0, 9),
10369 GEN_VXFORM(vadduws, 0, 10),
10370 GEN_VXFORM(vaddsbs, 0, 12),
10371 GEN_VXFORM(vaddshs, 0, 13),
10372 GEN_VXFORM(vaddsws, 0, 14),
10373 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10374 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10375 GEN_VXFORM(vsubuws, 0, 26),
10376 GEN_VXFORM(vsubsbs, 0, 28),
10377 GEN_VXFORM(vsubshs, 0, 29),
10378 GEN_VXFORM(vsubsws, 0, 30),
10379 GEN_VXFORM_207(vadduqm, 0, 4),
10380 GEN_VXFORM_207(vaddcuq, 0, 5),
10381 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10382 GEN_VXFORM_207(vsubuqm, 0, 20),
10383 GEN_VXFORM_207(vsubcuq, 0, 21),
10384 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10385 GEN_VXFORM(vrlb, 2, 0),
10386 GEN_VXFORM(vrlh, 2, 1),
10387 GEN_VXFORM(vrlw, 2, 2),
10388 GEN_VXFORM_207(vrld, 2, 3),
10389 GEN_VXFORM(vsl, 2, 7),
10390 GEN_VXFORM(vsr, 2, 11),
10391 GEN_VXFORM(vpkuhum, 7, 0),
10392 GEN_VXFORM(vpkuwum, 7, 1),
10393 GEN_VXFORM_207(vpkudum, 7, 17),
10394 GEN_VXFORM(vpkuhus, 7, 2),
10395 GEN_VXFORM(vpkuwus, 7, 3),
10396 GEN_VXFORM_207(vpkudus, 7, 19),
10397 GEN_VXFORM(vpkshus, 7, 4),
10398 GEN_VXFORM(vpkswus, 7, 5),
10399 GEN_VXFORM_207(vpksdus, 7, 21),
10400 GEN_VXFORM(vpkshss, 7, 6),
10401 GEN_VXFORM(vpkswss, 7, 7),
10402 GEN_VXFORM_207(vpksdss, 7, 23),
10403 GEN_VXFORM(vpkpx, 7, 12),
10404 GEN_VXFORM(vsum4ubs, 4, 24),
10405 GEN_VXFORM(vsum4sbs, 4, 28),
10406 GEN_VXFORM(vsum4shs, 4, 25),
10407 GEN_VXFORM(vsum2sws, 4, 26),
10408 GEN_VXFORM(vsumsws, 4, 30),
10409 GEN_VXFORM(vaddfp, 5, 0),
10410 GEN_VXFORM(vsubfp, 5, 1),
10411 GEN_VXFORM(vmaxfp, 5, 16),
10412 GEN_VXFORM(vminfp, 5, 17),
10413
10414 #undef GEN_VXRFORM1
10415 #undef GEN_VXRFORM
10416 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10417 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10418 #define GEN_VXRFORM(name, opc2, opc3) \
10419 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10420 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10421 GEN_VXRFORM(vcmpequb, 3, 0)
10422 GEN_VXRFORM(vcmpequh, 3, 1)
10423 GEN_VXRFORM(vcmpequw, 3, 2)
10424 GEN_VXRFORM(vcmpgtsb, 3, 12)
10425 GEN_VXRFORM(vcmpgtsh, 3, 13)
10426 GEN_VXRFORM(vcmpgtsw, 3, 14)
10427 GEN_VXRFORM(vcmpgtub, 3, 8)
10428 GEN_VXRFORM(vcmpgtuh, 3, 9)
10429 GEN_VXRFORM(vcmpgtuw, 3, 10)
10430 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10431 GEN_VXRFORM(vcmpgefp, 3, 7)
10432 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10433 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10434
10435 #undef GEN_VXFORM_SIMM
10436 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10437 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10438 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10439 GEN_VXFORM_SIMM(vspltish, 6, 13),
10440 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10441
10442 #undef GEN_VXFORM_NOA
10443 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10444 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10445 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10446 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10447 GEN_VXFORM_207(vupkhsw, 7, 25),
10448 GEN_VXFORM_NOA(vupklsb, 7, 10),
10449 GEN_VXFORM_NOA(vupklsh, 7, 11),
10450 GEN_VXFORM_207(vupklsw, 7, 27),
10451 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10452 GEN_VXFORM_NOA(vupklpx, 7, 15),
10453 GEN_VXFORM_NOA(vrefp, 5, 4),
10454 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10455 GEN_VXFORM_NOA(vexptefp, 5, 6),
10456 GEN_VXFORM_NOA(vlogefp, 5, 7),
10457 GEN_VXFORM_NOA(vrfim, 5, 8),
10458 GEN_VXFORM_NOA(vrfin, 5, 9),
10459 GEN_VXFORM_NOA(vrfip, 5, 10),
10460 GEN_VXFORM_NOA(vrfiz, 5, 11),
10461
10462 #undef GEN_VXFORM_UIMM
10463 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10464 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10465 GEN_VXFORM_UIMM(vspltb, 6, 8),
10466 GEN_VXFORM_UIMM(vsplth, 6, 9),
10467 GEN_VXFORM_UIMM(vspltw, 6, 10),
10468 GEN_VXFORM_UIMM(vcfux, 5, 12),
10469 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10470 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10471 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10472
10473 #undef GEN_VAFORM_PAIRED
10474 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10475 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10476 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10477 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10478 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10479 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10480 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10481 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10482
10483 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10484 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10485 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10486 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10487
10488 GEN_VXFORM_207(vbpermq, 6, 21),
10489 GEN_VXFORM_207(vgbbd, 6, 20),
10490 GEN_VXFORM_207(vpmsumb, 4, 16),
10491 GEN_VXFORM_207(vpmsumh, 4, 17),
10492 GEN_VXFORM_207(vpmsumw, 4, 18),
10493 GEN_VXFORM_207(vpmsumd, 4, 19),
10494
10495 GEN_VXFORM_207(vsbox, 4, 23),
10496
10497 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10498 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10499
10500 GEN_VXFORM_207(vshasigmaw, 1, 26),
10501 GEN_VXFORM_207(vshasigmad, 1, 27),
10502
10503 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10504
10505 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10506 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10507 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10508 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10509 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10510 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10511 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10512
10513 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10514 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10515 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10516 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10517 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10518
10519 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10520 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10521 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10522 #if defined(TARGET_PPC64)
10523 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10524 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10525 #endif
10526
10527 #undef GEN_XX2FORM
10528 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10529 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10530 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10531
10532 #undef GEN_XX3FORM
10533 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10534 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10535 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10536 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10537 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10538
10539 #undef GEN_XX3_RC_FORM
10540 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10541 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10542 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10543 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10544 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10545 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10546 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10547 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10548 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10549
10550 #undef GEN_XX3FORM_DM
10551 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10552 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10553 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10554 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10555 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10556 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10557 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10558 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10559 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10560 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10561 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10562 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10563 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10564 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10565 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10566 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10567 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10568
10569 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10570 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10571 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10572 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10573
10574 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10575 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10576 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10577 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10578 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10579 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10580 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10581 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10582
10583 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10584 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10585 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10586 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10587 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10588 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10589 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10590 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10591 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10592 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10593 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10594 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10595 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10596 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10597 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10598 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10599 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10600 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10601 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10602 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10603 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10604 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10605 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10606 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10607 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10608 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10609 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10610 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10611 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10612 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10613 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10614 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10615 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10616 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10617 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10618 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10619
10620 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10621 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10622 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10623 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10624 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10625 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10626 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10627 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10628 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10629 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10630 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10631 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10632 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10633 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10634 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10635 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10636 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10637 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10638
10639 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10640 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10641 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10642 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10643 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10644 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10645 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10646 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10647 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10648 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10649 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10650 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10651 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10652 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10653 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10654 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10655 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10656 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10657 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10658 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10659 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10660 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10661 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10662 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10663 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10664 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10665 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10666 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10667 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10668 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10669 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10670 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10671 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10672 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10673 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10674 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10675
10676 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10677 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10678 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10679 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10680 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10681 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10682 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10683 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10684 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10685 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10686 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10687 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10688 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10689 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10690 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10691 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10692 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10693 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10694 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10695 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10696 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10697 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10698 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10699 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10700 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10701 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10702 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10703 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10704 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10705 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10706 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10707 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10708 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10709 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10710 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10711 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10712
10713 #undef VSX_LOGICAL
10714 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10715 GEN_XX3FORM(name, opc2, opc3, fl2)
10716
10717 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10718 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10719 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10720 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10721 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10722 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10723 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10724 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10725 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10726 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10727 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10728 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10729
10730 #define GEN_XXSEL_ROW(opc3) \
10731 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10732 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10733 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10734 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10735 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10736 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10737 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10738 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10739
10740 GEN_XXSEL_ROW(0x00)
10741 GEN_XXSEL_ROW(0x01)
10742 GEN_XXSEL_ROW(0x02)
10743 GEN_XXSEL_ROW(0x03)
10744 GEN_XXSEL_ROW(0x04)
10745 GEN_XXSEL_ROW(0x05)
10746 GEN_XXSEL_ROW(0x06)
10747 GEN_XXSEL_ROW(0x07)
10748 GEN_XXSEL_ROW(0x08)
10749 GEN_XXSEL_ROW(0x09)
10750 GEN_XXSEL_ROW(0x0A)
10751 GEN_XXSEL_ROW(0x0B)
10752 GEN_XXSEL_ROW(0x0C)
10753 GEN_XXSEL_ROW(0x0D)
10754 GEN_XXSEL_ROW(0x0E)
10755 GEN_XXSEL_ROW(0x0F)
10756 GEN_XXSEL_ROW(0x10)
10757 GEN_XXSEL_ROW(0x11)
10758 GEN_XXSEL_ROW(0x12)
10759 GEN_XXSEL_ROW(0x13)
10760 GEN_XXSEL_ROW(0x14)
10761 GEN_XXSEL_ROW(0x15)
10762 GEN_XXSEL_ROW(0x16)
10763 GEN_XXSEL_ROW(0x17)
10764 GEN_XXSEL_ROW(0x18)
10765 GEN_XXSEL_ROW(0x19)
10766 GEN_XXSEL_ROW(0x1A)
10767 GEN_XXSEL_ROW(0x1B)
10768 GEN_XXSEL_ROW(0x1C)
10769 GEN_XXSEL_ROW(0x1D)
10770 GEN_XXSEL_ROW(0x1E)
10771 GEN_XXSEL_ROW(0x1F)
10772
10773 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10774
10775 #undef GEN_DFP_T_A_B_Rc
10776 #undef GEN_DFP_BF_A_B
10777 #undef GEN_DFP_BF_A_DCM
10778 #undef GEN_DFP_T_B_U32_U32_Rc
10779 #undef GEN_DFP_T_A_B_I32_Rc
10780 #undef GEN_DFP_T_B_Rc
10781 #undef GEN_DFP_T_FPR_I32_Rc
10782
10783 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10784 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10785
10786 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10787 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10788 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10789
10790 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10791 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10792 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10793 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10794 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10795
10796 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10797 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10798
10799 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10800 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10801 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10802
10803 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10804 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10805 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10806 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10807 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10808
10809 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10810 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10811
10812 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10813 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10814
10815 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10816 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10817
10818 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10819 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10820
10821 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10822 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10823
10824 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10825 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10826
10827 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10828 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10829
10830 #define GEN_DFP_BF_A_B(name, op1, op2) \
10831 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10832
10833 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10834 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10835
10836 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10837 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10838
10839 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10840 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10841
10842 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10843 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10844
10845 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10846 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10847
10848 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10849 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10850
10851 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10852 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10853
10854 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10855 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10856
10857 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10858 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10859
10860 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10861 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10862
10863 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10864 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10865
10866 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10867 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10868
10869 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10870 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10871
10872 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10873 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10874
10875 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10876 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10877
10878 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10879 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10880
10881 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10882 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10883
10884 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10885 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
10886 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10887 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
10888 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10889 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
10890 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10891 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
10892 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10893 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10894 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10895 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
10896 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10897 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
10898 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10899 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
10900 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10901 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
10902 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10903 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
10904 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10905 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10906 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10907 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
10908 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10909 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
10910 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10911 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10912 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10913 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
10914 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
10915 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
10916 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
10917 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
10918 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
10919 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
10920 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
10921 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
10922 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
10923 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
10924 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
10925 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
10926 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
10927 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
10928 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
10929 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
10930 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
10931 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
10932 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
10933 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
10934
10935 #undef GEN_SPE
10936 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10937 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10938 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10939 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10940 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10941 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10942 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10943 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10944 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10945 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10946 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10947 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10948 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10949 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10950 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10951 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10952 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10953 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10954 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10955 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10956 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10957 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10958 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10959 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10960 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10961 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10962 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10963 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10964 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10965 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10966 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10967
10968 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10969 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10970 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10971 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10972 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10973 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10974 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10975 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10976 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10977 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10978 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10979 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10980 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10981 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10982
10983 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10984 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10985 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10986 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10987 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10988 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10989 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10990 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10991 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10992 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10993 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10994 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10995 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10996 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10997
10998 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10999 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11000 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11001 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11002 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11003 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11004 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11005 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11006 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11007 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11008 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11009 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11010 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11011 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11012 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11013 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11014
11015 #undef GEN_SPEOP_LDST
11016 #define GEN_SPEOP_LDST(name, opc2, sh) \
11017 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11018 GEN_SPEOP_LDST(evldd, 0x00, 3),
11019 GEN_SPEOP_LDST(evldw, 0x01, 3),
11020 GEN_SPEOP_LDST(evldh, 0x02, 3),
11021 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11022 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11023 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11024 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11025 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11026 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11027 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11028 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11029
11030 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11031 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11032 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11033 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11034 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11035 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11036 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11037 };
11038
11039 #include "helper_regs.h"
11040 #include "translate_init.c"
11041
11042 /*****************************************************************************/
11043 /* Misc PowerPC helpers */
11044 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11045 int flags)
11046 {
11047 #define RGPL 4
11048 #define RFPL 4
11049
11050 PowerPCCPU *cpu = POWERPC_CPU(cs);
11051 CPUPPCState *env = &cpu->env;
11052 int i;
11053
11054 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11055 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11056 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11057 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11058 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11059 env->hflags, env->mmu_idx);
11060 #if !defined(NO_TIMER_DUMP)
11061 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11062 #if !defined(CONFIG_USER_ONLY)
11063 " DECR %08" PRIu32
11064 #endif
11065 "\n",
11066 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11067 #if !defined(CONFIG_USER_ONLY)
11068 , cpu_ppc_load_decr(env)
11069 #endif
11070 );
11071 #endif
11072 for (i = 0; i < 32; i++) {
11073 if ((i & (RGPL - 1)) == 0)
11074 cpu_fprintf(f, "GPR%02d", i);
11075 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11076 if ((i & (RGPL - 1)) == (RGPL - 1))
11077 cpu_fprintf(f, "\n");
11078 }
11079 cpu_fprintf(f, "CR ");
11080 for (i = 0; i < 8; i++)
11081 cpu_fprintf(f, "%01x", env->crf[i]);
11082 cpu_fprintf(f, " [");
11083 for (i = 0; i < 8; i++) {
11084 char a = '-';
11085 if (env->crf[i] & 0x08)
11086 a = 'L';
11087 else if (env->crf[i] & 0x04)
11088 a = 'G';
11089 else if (env->crf[i] & 0x02)
11090 a = 'E';
11091 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11092 }
11093 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11094 env->reserve_addr);
11095 for (i = 0; i < 32; i++) {
11096 if ((i & (RFPL - 1)) == 0)
11097 cpu_fprintf(f, "FPR%02d", i);
11098 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11099 if ((i & (RFPL - 1)) == (RFPL - 1))
11100 cpu_fprintf(f, "\n");
11101 }
11102 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11103 #if !defined(CONFIG_USER_ONLY)
11104 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11105 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11106 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11107 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11108
11109 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11110 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11111 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11112 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11113
11114 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11115 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11116 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11117 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11118
11119 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11120 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11121 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11122 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11123 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11124
11125 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11126 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11127 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11128 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11129
11130 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11131 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11132 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11133 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11134
11135 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11136 " EPR " TARGET_FMT_lx "\n",
11137 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11138 env->spr[SPR_BOOKE_EPR]);
11139
11140 /* FSL-specific */
11141 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11142 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11143 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11144 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11145
11146 /*
11147 * IVORs are left out as they are large and do not change often --
11148 * they can be read with "p $ivor0", "p $ivor1", etc.
11149 */
11150 }
11151
11152 #if defined(TARGET_PPC64)
11153 if (env->flags & POWERPC_FLAG_CFAR) {
11154 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11155 }
11156 #endif
11157
11158 switch (env->mmu_model) {
11159 case POWERPC_MMU_32B:
11160 case POWERPC_MMU_601:
11161 case POWERPC_MMU_SOFT_6xx:
11162 case POWERPC_MMU_SOFT_74xx:
11163 #if defined(TARGET_PPC64)
11164 case POWERPC_MMU_64B:
11165 case POWERPC_MMU_2_06:
11166 case POWERPC_MMU_2_06a:
11167 case POWERPC_MMU_2_06d:
11168 #endif
11169 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11170 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11171 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11172 break;
11173 case POWERPC_MMU_BOOKE206:
11174 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11175 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11176 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11177 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11178
11179 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11180 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11181 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11182 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11183
11184 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11185 " TLB1CFG " TARGET_FMT_lx "\n",
11186 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11187 env->spr[SPR_BOOKE_TLB1CFG]);
11188 break;
11189 default:
11190 break;
11191 }
11192 #endif
11193
11194 #undef RGPL
11195 #undef RFPL
11196 }
11197
11198 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11199 fprintf_function cpu_fprintf, int flags)
11200 {
11201 #if defined(DO_PPC_STATISTICS)
11202 PowerPCCPU *cpu = POWERPC_CPU(cs);
11203 opc_handler_t **t1, **t2, **t3, *handler;
11204 int op1, op2, op3;
11205
11206 t1 = cpu->env.opcodes;
11207 for (op1 = 0; op1 < 64; op1++) {
11208 handler = t1[op1];
11209 if (is_indirect_opcode(handler)) {
11210 t2 = ind_table(handler);
11211 for (op2 = 0; op2 < 32; op2++) {
11212 handler = t2[op2];
11213 if (is_indirect_opcode(handler)) {
11214 t3 = ind_table(handler);
11215 for (op3 = 0; op3 < 32; op3++) {
11216 handler = t3[op3];
11217 if (handler->count == 0)
11218 continue;
11219 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11220 "%016" PRIx64 " %" PRId64 "\n",
11221 op1, op2, op3, op1, (op3 << 5) | op2,
11222 handler->oname,
11223 handler->count, handler->count);
11224 }
11225 } else {
11226 if (handler->count == 0)
11227 continue;
11228 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11229 "%016" PRIx64 " %" PRId64 "\n",
11230 op1, op2, op1, op2, handler->oname,
11231 handler->count, handler->count);
11232 }
11233 }
11234 } else {
11235 if (handler->count == 0)
11236 continue;
11237 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11238 " %" PRId64 "\n",
11239 op1, op1, handler->oname,
11240 handler->count, handler->count);
11241 }
11242 }
11243 #endif
11244 }
11245
11246 /*****************************************************************************/
11247 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11248 TranslationBlock *tb,
11249 bool search_pc)
11250 {
11251 CPUState *cs = CPU(cpu);
11252 CPUPPCState *env = &cpu->env;
11253 DisasContext ctx, *ctxp = &ctx;
11254 opc_handler_t **table, *handler;
11255 target_ulong pc_start;
11256 uint16_t *gen_opc_end;
11257 CPUBreakpoint *bp;
11258 int j, lj = -1;
11259 int num_insns;
11260 int max_insns;
11261
11262 pc_start = tb->pc;
11263 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11264 ctx.nip = pc_start;
11265 ctx.tb = tb;
11266 ctx.exception = POWERPC_EXCP_NONE;
11267 ctx.spr_cb = env->spr_cb;
11268 ctx.mem_idx = env->mmu_idx;
11269 ctx.insns_flags = env->insns_flags;
11270 ctx.insns_flags2 = env->insns_flags2;
11271 ctx.access_type = -1;
11272 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11273 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11274 #if defined(TARGET_PPC64)
11275 ctx.sf_mode = msr_is_64bit(env, env->msr);
11276 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11277 #endif
11278 ctx.fpu_enabled = msr_fp;
11279 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11280 ctx.spe_enabled = msr_spe;
11281 else
11282 ctx.spe_enabled = 0;
11283 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11284 ctx.altivec_enabled = msr_vr;
11285 else
11286 ctx.altivec_enabled = 0;
11287 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11288 ctx.vsx_enabled = msr_vsx;
11289 } else {
11290 ctx.vsx_enabled = 0;
11291 }
11292 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11293 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11294 else
11295 ctx.singlestep_enabled = 0;
11296 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11297 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11298 if (unlikely(cs->singlestep_enabled)) {
11299 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11300 }
11301 #if defined (DO_SINGLE_STEP) && 0
11302 /* Single step trace mode */
11303 msr_se = 1;
11304 #endif
11305 num_insns = 0;
11306 max_insns = tb->cflags & CF_COUNT_MASK;
11307 if (max_insns == 0)
11308 max_insns = CF_COUNT_MASK;
11309
11310 gen_tb_start();
11311 tcg_clear_temp_count();
11312 /* Set env in case of segfault during code fetch */
11313 while (ctx.exception == POWERPC_EXCP_NONE
11314 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11315 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11316 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11317 if (bp->pc == ctx.nip) {
11318 gen_debug_exception(ctxp);
11319 break;
11320 }
11321 }
11322 }
11323 if (unlikely(search_pc)) {
11324 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11325 if (lj < j) {
11326 lj++;
11327 while (lj < j)
11328 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11329 }
11330 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11331 tcg_ctx.gen_opc_instr_start[lj] = 1;
11332 tcg_ctx.gen_opc_icount[lj] = num_insns;
11333 }
11334 LOG_DISAS("----------------\n");
11335 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11336 ctx.nip, ctx.mem_idx, (int)msr_ir);
11337 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11338 gen_io_start();
11339 if (unlikely(need_byteswap(&ctx))) {
11340 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11341 } else {
11342 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11343 }
11344 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11345 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11346 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11347 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11348 tcg_gen_debug_insn_start(ctx.nip);
11349 }
11350 ctx.nip += 4;
11351 table = env->opcodes;
11352 num_insns++;
11353 handler = table[opc1(ctx.opcode)];
11354 if (is_indirect_opcode(handler)) {
11355 table = ind_table(handler);
11356 handler = table[opc2(ctx.opcode)];
11357 if (is_indirect_opcode(handler)) {
11358 table = ind_table(handler);
11359 handler = table[opc3(ctx.opcode)];
11360 }
11361 }
11362 /* Is opcode *REALLY* valid ? */
11363 if (unlikely(handler->handler == &gen_invalid)) {
11364 if (qemu_log_enabled()) {
11365 qemu_log("invalid/unsupported opcode: "
11366 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11367 opc1(ctx.opcode), opc2(ctx.opcode),
11368 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11369 }
11370 } else {
11371 uint32_t inval;
11372
11373 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11374 inval = handler->inval2;
11375 } else {
11376 inval = handler->inval1;
11377 }
11378
11379 if (unlikely((ctx.opcode & inval) != 0)) {
11380 if (qemu_log_enabled()) {
11381 qemu_log("invalid bits: %08x for opcode: "
11382 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11383 ctx.opcode & inval, opc1(ctx.opcode),
11384 opc2(ctx.opcode), opc3(ctx.opcode),
11385 ctx.opcode, ctx.nip - 4);
11386 }
11387 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11388 break;
11389 }
11390 }
11391 (*(handler->handler))(&ctx);
11392 #if defined(DO_PPC_STATISTICS)
11393 handler->count++;
11394 #endif
11395 /* Check trace mode exceptions */
11396 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11397 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11398 ctx.exception != POWERPC_SYSCALL &&
11399 ctx.exception != POWERPC_EXCP_TRAP &&
11400 ctx.exception != POWERPC_EXCP_BRANCH)) {
11401 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11402 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11403 (cs->singlestep_enabled) ||
11404 singlestep ||
11405 num_insns >= max_insns)) {
11406 /* if we reach a page boundary or are single stepping, stop
11407 * generation
11408 */
11409 break;
11410 }
11411 if (tcg_check_temp_count()) {
11412 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11413 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11414 ctx.opcode);
11415 exit(1);
11416 }
11417 }
11418 if (tb->cflags & CF_LAST_IO)
11419 gen_io_end();
11420 if (ctx.exception == POWERPC_EXCP_NONE) {
11421 gen_goto_tb(&ctx, 0, ctx.nip);
11422 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11423 if (unlikely(cs->singlestep_enabled)) {
11424 gen_debug_exception(ctxp);
11425 }
11426 /* Generate the return instruction */
11427 tcg_gen_exit_tb(0);
11428 }
11429 gen_tb_end(tb, num_insns);
11430 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11431 if (unlikely(search_pc)) {
11432 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11433 lj++;
11434 while (lj <= j)
11435 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11436 } else {
11437 tb->size = ctx.nip - pc_start;
11438 tb->icount = num_insns;
11439 }
11440 #if defined(DEBUG_DISAS)
11441 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11442 int flags;
11443 flags = env->bfd_mach;
11444 flags |= ctx.le_mode << 16;
11445 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11446 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11447 qemu_log("\n");
11448 }
11449 #endif
11450 }
11451
11452 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11453 {
11454 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11455 }
11456
11457 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11458 {
11459 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11460 }
11461
11462 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11463 {
11464 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11465 }
Ray Wang's QEMU Repository