hw/pci-host/prep.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2011-2013 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/units.h"
  28 #include "qapi/error.h"
  29 #include "hw/hw.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/pci/pci_bus.h"
  32 #include "hw/pci/pci_host.h"
  33 #include "hw/i386/pc.h"
  34 #include "hw/loader.h"
  35 #include "exec/address-spaces.h"
  36 #include "elf.h"
  37
  38 #define TYPE_RAVEN_PCI_DEVICE "raven"
  39 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
  40
  41 #define RAVEN_PCI_DEVICE(obj) \
  42     OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
  43
  44 typedef struct RavenPCIState {
  45     PCIDevice dev;
  46
  47     uint32_t elf_machine;
  48     char *bios_name;
  49     MemoryRegion bios;
  50 } RavenPCIState;
  51
  52 #define RAVEN_PCI_HOST_BRIDGE(obj) \
  53     OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
  54
  55 typedef struct PRePPCIState {
  56     PCIHostState parent_obj;
  57
  58     qemu_irq pci_irqs[PCI_NUM_PINS];
  59     PCIBus pci_bus;
  60     AddressSpace pci_io_as;
  61     MemoryRegion pci_io;
  62     MemoryRegion pci_io_non_contiguous;
  63     MemoryRegion pci_memory;
  64     MemoryRegion pci_intack;
  65     MemoryRegion bm;
  66     MemoryRegion bm_ram_alias;
  67     MemoryRegion bm_pci_memory_alias;
  68     AddressSpace bm_as;
  69     RavenPCIState pci_dev;
  70
  71     int contiguous_map;
  72 } PREPPCIState;
  73
  74 #define BIOS_SIZE (1 * MiB)
  75
  76 static inline uint32_t raven_pci_io_config(hwaddr addr)
  77 {
  78     int i;
  79
  80     for (i = 0; i < 11; i++) {
  81         if ((addr & (1 << (11 + i))) != 0) {
  82             break;
  83         }
  84     }
  85     return (addr & 0x7ff) |  (i << 11);
  86 }
  87
  88 static void raven_pci_io_write(void *opaque, hwaddr addr,
  89                                uint64_t val, unsigned int size)
  90 {
  91     PREPPCIState *s = opaque;
  92     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  93     pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
  94 }
  95
  96 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
  97                                   unsigned int size)
  98 {
  99     PREPPCIState *s = opaque;
 100     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 101     return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
 102 }
 103
 104 static const MemoryRegionOps raven_pci_io_ops = {
 105     .read = raven_pci_io_read,
 106     .write = raven_pci_io_write,
 107     .endianness = DEVICE_LITTLE_ENDIAN,
 108 };
 109
 110 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
 111                                   unsigned int size)
 112 {
 113     return pic_read_irq(isa_pic);
 114 }
 115
 116 static const MemoryRegionOps raven_intack_ops = {
 117     .read = raven_intack_read,
 118     .valid = {
 119         .max_access_size = 1,
 120     },
 121 };
 122
 123 static inline hwaddr raven_io_address(PREPPCIState *s,
 124                                       hwaddr addr)
 125 {
 126     if (s->contiguous_map == 0) {
 127         /* 64 KB contiguous space for IOs */
 128         addr &= 0xFFFF;
 129     } else {
 130         /* 8 MB non-contiguous space for IOs */
 131         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 132     }
 133
 134     /* FIXME: handle endianness switch */
 135
 136     return addr;
 137 }
 138
 139 static uint64_t raven_io_read(void *opaque, hwaddr addr,
 140                               unsigned int size)
 141 {
 142     PREPPCIState *s = opaque;
 143     uint8_t buf[4];
 144
 145     addr = raven_io_address(s, addr);
 146     address_space_read(&s->pci_io_as, addr + 0x80000000,
 147                        MEMTXATTRS_UNSPECIFIED, buf, size);
 148
 149     if (size == 1) {
 150         return buf[0];
 151     } else if (size == 2) {
 152         return lduw_le_p(buf);
 153     } else if (size == 4) {
 154         return ldl_le_p(buf);
 155     } else {
 156         g_assert_not_reached();
 157     }
 158 }
 159
 160 static void raven_io_write(void *opaque, hwaddr addr,
 161                            uint64_t val, unsigned int size)
 162 {
 163     PREPPCIState *s = opaque;
 164     uint8_t buf[4];
 165
 166     addr = raven_io_address(s, addr);
 167
 168     if (size == 1) {
 169         buf[0] = val;
 170     } else if (size == 2) {
 171         stw_le_p(buf, val);
 172     } else if (size == 4) {
 173         stl_le_p(buf, val);
 174     } else {
 175         g_assert_not_reached();
 176     }
 177
 178     address_space_write(&s->pci_io_as, addr + 0x80000000,
 179                         MEMTXATTRS_UNSPECIFIED, buf, size);
 180 }
 181
 182 static const MemoryRegionOps raven_io_ops = {
 183     .read = raven_io_read,
 184     .write = raven_io_write,
 185     .endianness = DEVICE_LITTLE_ENDIAN,
 186     .impl.max_access_size = 4,
 187     .valid.unaligned = true,
 188 };
 189
 190 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
 191 {
 192     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 193 }
 194
 195 static void raven_set_irq(void *opaque, int irq_num, int level)
 196 {
 197     PREPPCIState *s = opaque;
 198
 199     qemu_set_irq(s->pci_irqs[irq_num], level);
 200 }
 201
 202 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
 203                                              int devfn)
 204 {
 205     PREPPCIState *s = opaque;
 206
 207     return &s->bm_as;
 208 }
 209
 210 static void raven_change_gpio(void *opaque, int n, int level)
 211 {
 212     PREPPCIState *s = opaque;
 213
 214     s->contiguous_map = level;
 215 }
 216
 217 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
 218 {
 219     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 220     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 221     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
 222     MemoryRegion *address_space_mem = get_system_memory();
 223     int i;
 224
 225     for (i = 0; i < PCI_NUM_PINS; i++) {
 226         sysbus_init_irq(dev, &s->pci_irqs[i]);
 227     }
 228
 229     qdev_init_gpio_in(d, raven_change_gpio, 1);
 230
 231     pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
 232
 233     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
 234                           "pci-conf-idx", 4);
 235     memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
 236
 237     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
 238                           "pci-conf-data", 4);
 239     memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
 240
 241     memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
 242                           "pciio", 0x00400000);
 243     memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 244
 245     memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
 246                           "pci-intack", 1);
 247     memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
 248
 249     /* TODO Remove once realize propagates to child devices. */
 250     object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
 251     object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
 252 }
 253
 254 static void raven_pcihost_initfn(Object *obj)
 255 {
 256     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 257     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
 258     MemoryRegion *address_space_mem = get_system_memory();
 259     DeviceState *pci_dev;
 260
 261     memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
 262     memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
 263                           "pci-io-non-contiguous", 0x00800000);
 264     memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
 265     address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
 266
 267     /* CPU address space */
 268     memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
 269     memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
 270                                         &s->pci_io_non_contiguous, 1);
 271     memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
 272     pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
 273                              &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
 274
 275     /* Bus master address space */
 276     memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
 277     memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
 278                              &s->pci_memory, 0,
 279                              memory_region_size(&s->pci_memory));
 280     memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
 281                              get_system_memory(), 0, 0x80000000);
 282     memory_region_add_subregion(&s->bm, 0         , &s->bm_pci_memory_alias);
 283     memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
 284     address_space_init(&s->bm_as, &s->bm, "raven-bm");
 285     pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
 286
 287     h->bus = &s->pci_bus;
 288
 289     object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
 290     pci_dev = DEVICE(&s->pci_dev);
 291     qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
 292     object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
 293                             NULL);
 294     qdev_prop_set_bit(pci_dev, "multifunction", false);
 295 }
 296
 297 static void raven_realize(PCIDevice *d, Error **errp)
 298 {
 299     RavenPCIState *s = RAVEN_PCI_DEVICE(d);
 300     char *filename;
 301     int bios_size = -1;
 302
 303     d->config[0x0C] = 0x08; // cache_line_size
 304     d->config[0x0D] = 0x10; // latency_timer
 305     d->config[0x34] = 0x00; // capabilities_pointer
 306
 307     memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
 308                            &error_fatal);
 309     memory_region_set_readonly(&s->bios, true);
 310     memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
 311                                 &s->bios);
 312     if (s->bios_name) {
 313         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
 314         if (filename) {
 315             if (s->elf_machine != EM_NONE) {
 316                 bios_size = load_elf(filename, NULL, NULL, NULL,
 317                                      NULL, NULL, 1, s->elf_machine, 0, 0);
 318             }
 319             if (bios_size < 0) {
 320                 bios_size = get_image_size(filename);
 321                 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 322                     hwaddr bios_addr;
 323                     bios_size = (bios_size + 0xfff) & ~0xfff;
 324                     bios_addr = (uint32_t)(-BIOS_SIZE);
 325                     bios_size = load_image_targphys(filename, bios_addr,
 326                                                     bios_size);
 327                 }
 328             }
 329         }
 330         g_free(filename);
 331         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 332             memory_region_del_subregion(get_system_memory(), &s->bios);
 333             error_setg(errp, "Could not load bios image '%s'", s->bios_name);
 334             return;
 335         }
 336     }
 337
 338     vmstate_register_ram_global(&s->bios);
 339 }
 340
 341 static const VMStateDescription vmstate_raven = {
 342     .name = "raven",
 343     .version_id = 0,
 344     .minimum_version_id = 0,
 345     .fields = (VMStateField[]) {
 346         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 347         VMSTATE_END_OF_LIST()
 348     },
 349 };
 350
 351 static void raven_class_init(ObjectClass *klass, void *data)
 352 {
 353     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 354     DeviceClass *dc = DEVICE_CLASS(klass);
 355
 356     k->realize = raven_realize;
 357     k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
 358     k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
 359     k->revision = 0x00;
 360     k->class_id = PCI_CLASS_BRIDGE_HOST;
 361     dc->desc = "PReP Host Bridge - Motorola Raven";
 362     dc->vmsd = &vmstate_raven;
 363     /*
 364      * Reason: PCI-facing part of the host bridge, not usable without
 365      * the host-facing part, which can't be device_add'ed, yet.
 366      */
 367     dc->user_creatable = false;
 368 }
 369
 370 static const TypeInfo raven_info = {
 371     .name = TYPE_RAVEN_PCI_DEVICE,
 372     .parent = TYPE_PCI_DEVICE,
 373     .instance_size = sizeof(RavenPCIState),
 374     .class_init = raven_class_init,
 375     .interfaces = (InterfaceInfo[]) {
 376         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 377         { },
 378     },
 379 };
 380
 381 static Property raven_pcihost_properties[] = {
 382     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
 383                        EM_NONE),
 384     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
 385     DEFINE_PROP_END_OF_LIST()
 386 };
 387
 388 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
 389 {
 390     DeviceClass *dc = DEVICE_CLASS(klass);
 391
 392     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 393     dc->realize = raven_pcihost_realizefn;
 394     dc->props = raven_pcihost_properties;
 395     dc->fw_name = "pci";
 396 }
 397
 398 static const TypeInfo raven_pcihost_info = {
 399     .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
 400     .parent = TYPE_PCI_HOST_BRIDGE,
 401     .instance_size = sizeof(PREPPCIState),
 402     .instance_init = raven_pcihost_initfn,
 403     .class_init = raven_pcihost_class_init,
 404 };
 405
 406 static void raven_register_types(void)
 407 {
 408     type_register_static(&raven_pcihost_info);
 409     type_register_static(&raven_info);
 410 }
 411
 412 type_init(raven_register_types)